Voltage glitch detector

Abstract

In the example described, the voltage glitch detector (146) includes a current source (310), a latch (320), and first, second, third, fourth, and fifth transistors (308, 306, 304, 314, and 312). The source of the third transistor (304) is coupled to the source of the second transistor (306), and the gate and drain of the third transistor are coupled to the gates of the first and second transistors (308 and 306) and to the first terminal of the current source. The drain of the fourth transistor (314) is coupled to the drain of the first transistor (308) and to the input of the latch (320). The source of the fifth transistor (312) is coupled to the source of the fourth transistor (314) and to the second terminal of the current source. The gate and drain of the fifth transistor (312) are coupled to the gate of the fourth transistor (314) and the drain of the second transistor (306).

Description

[Technical Field]

[0001] This application relates to voltage glitch detection in general, and more particularly to the detection of voltage glitches in the supply voltage. [Background technology]

[0002] In some cases, fluctuations in the supply voltage outside the designed operating limits (supply voltage glitches) can cause unpredictable or unreliable downstream circuit behavior. Deliberately introduced supply voltage glitches have been used as a fault injection method to attack mixed-signal electronic circuits such as microcontroller units (MCUs) in the Internet of Things (IoT) and other application devices. In some cases, these attacks have been used to skip or bypass commands corresponding to encryption or other security checks during the firmware boot process. This can leave the MCU or other device vulnerable to adversarial physical access, potentially leading to data leakage or other undesirable hacking. [Overview of the project]

[0003] In the example described, the voltage glitch detector includes a current source, a latch, and first, second, third, fourth, and fifth transistors. The source of the third transistor is coupled to the source of the second transistor, and the gate and drain of the third transistor are coupled to the gates of the first and second transistors and to the first terminal of the current source. The drain of the fourth transistor is coupled to the drain of the first transistor and to the input of the latch. The source of the fifth transistor is coupled to the source of the fourth transistor and to the second terminal of the current source. The gate and drain of the fifth transistor are coupled to the gate of the fourth transistor and to the drain of the second transistor. [Brief explanation of the drawing]

[0004] [Figure 1]This is a schematic diagram of an example microcontroller unit (MCU) including a voltage glitch detection module (VGM).

[0005] [Figure 2] This is a circuit diagram of an example negative glitch detector.

[0006] [Figure 3] This is a circuit diagram providing an alternative diagram of a partial example of the negative voltage glitch detector shown in Figure 2.

[0007] [Figure 4] Figure 2 is a set of graphs showing example signals in a negative glitch detector.

[0008] [Figure 5] This is a circuit diagram of an example positive glitch detector.

[0009] [Figure 6] This is a circuit diagram providing an alternative diagram of a partial example of the positive glitch detector in Figure 5.

[0010] [Figure 7] Figure 5 is a set of graphs showing example signals in a positive glitch detector. [Modes for carrying out the invention]

[0011] Figure 1 is a schematic diagram of an exemplary microcontroller unit (MCU) system 100 including a voltage glitch detection module (VGM) 102. The MCU system 100 includes MCU 104, first capacitor (cap1) 106, second capacitor (cap2) 108, V DDR Domain grounding 110, and V DDD Includes domain grounding 112. MCU104 has voltage V DDS V provides DDS Voltage source (V DDS )114, V DDS Voltage domain 116, voltage V DDR V providesDDR Voltage source (V DDR ) 118, V DDR Voltage domain 120, voltage V DDD to provide V DDD Voltage source (V DDD ) 122, V DDD Voltage domain 124 includes a first pin (PIN1) 126 and a second pin (PIN2) 128.

[0012] V DDS Voltage domain 116 includes a first voltage regulator (voltage regulator 1) 130 (or multiple voltage regulators), power-on reset (POR) logic 132, and a first isolation (isolation 1) 134. V DDR Voltage domain 120 includes a second voltage regulator (voltage regulator 2) 136 (or multiple voltage regulators), a first blown out detector (BOD1) 138, and a second isolation (isolation 2) 140. V DDD Voltage domain 124 includes a central processing unit (CPU) 142, a second blown out detector (BOD2) 144, and VGM102. VGM102 includes a negative glitch detector 146 configured to detect a transient voltage below the intended supply voltage (negative voltage glitch) and a positive glitch detector 148 configured to detect a transient voltage above the intended supply voltage (positive voltage glitch).

[0013] V DDS 114 is V DDS connected to voltage domain 116 and VGM102. VGM102 is also DDS connected to the output to POR132 (or in some examples, another security circuit) in voltage domain 116. V DDS Voltage domain 116 is connected to V DDR 118, pin 1 126, and V DDR voltage domain 120 via isolation 1 134. Pin 1 126 is connected to the first terminal of cap1 106, and the second terminal of cap1 106 is connected to V DDR domain ground 110. V DDRVoltage domain 120 is V through isolation 2 140 DDD 122 and pin 2, 128 and V DDD It is connected to voltage domain 124. Pin 2 128 is connected to the first terminal of cap2 108, and the second terminal of cap2 108 is connected to V DDD It is connected to domain ground 112.

[0014] V DDS 114 is a physical power source such as a coin cell or other battery that provides direct current (DC) power. DDR 118 uses voltage regulator 130 to V DDS This is a step-down voltage source derived from 114, V DDD 122 uses voltage regulator 2 136 to V DDR This is a step-down voltage source derived from 118, and therefore indirectly from VDDS114. DDR 118 is V DDS This is a voltage domain lower than 114, V DDD 122 is V DDR This means a voltage domain lower than 118. In some examples, using relatively low voltages can enable faster and smaller circuits, such as CPU 142. Voltage regulator 1 130 and voltage regulator 2 136 are, for example, low dropout voltage regulators or other DC-DC voltage regulators. Isolation 1 134 and isolation 2 140 isolate different voltage domains from each other.

[0015] In some cases, an attacker exploits a supply voltage glitch to manipulate the behavior of CPU142 by removing cap2 108 and injecting a voltage spike at pin 2 128. This results in V DDDA temporary error may occur in 122, which could interfere with the CPU 142's ability to comply with reliable and secure behavior. In some cases, if VGM 102 detects a positive or negative voltage glitch (also referred to as a positive glitch or negative glitch, respectively), VGM 102 triggers POR 132 to reset MCU 104, resulting in the discarding of any malicious commands applied to an attack if the voltage glitch was part of the attack. In some cases, indicators of a positive or negative glitch may also trigger security functions or actions of MCU 104 in addition to or in addition to POR 132.

[0016] Figure 2 is a schematic diagram of an illustrative negative glitch detector 146. In the drawing, the same reference number or other reference identifier is used to indicate the same or similar features (structurally and / or functionally). The negative glitch detector 146 is V DDS 114, Differential amplifier 202, First p-channel MOSFET (M1P) 204, Second p-channel MOSFET (M2P) 206, Third p-channel MOSFET (M3P) 208, Reference current I REF A current source (I REF )210, 1st n-channel MOSFET (M1N)212, 2nd n-channel MOSFET (M2N)214, 3rd n-channel MOSFET (M3N)216, 4th n-channel MOSFET (M4N)218, V DDD 122 and V DDD It includes a domain ground 112, a resistor 220, a capacitor 222, a first inverter 224, a second inverter 226, a third inverter 228, an SR latch 230, a buffer 232, a level shifter 234, and a D latch 236.

[0017] The non-inverting input of differential amplifier 202 is the reference voltage V REF It is configured to receive V REF For example, this is a bandcap reference voltage. In some examples, V REFThis is a voltage derived from the bandcap reference voltage by using a resistive voltage divider or capacitive voltage divider, etc. REF This acts as a threshold voltage for detecting negative glitches.

[0018] The inverting input of differential amplifier 202 is connected to the output of differential amplifier 202, the source of M1P204, and the source of M2P206. Differential amplifier 202 is V DDS Powered by 114, the output of the differential amplifier 202 has a higher current than the non-inverting input of the differential amplifier 202, and the voltage V REF It has such a feature. Thus, the differential amplifier 202 has a reference voltage V REF It functions as a buffer for, and in other examples, the differential amplifier 202 is supplemented or replaced by other buffer circuit elements. Therefore, the source of both AM1P204 and M2P206 is voltage V REF Receive.

[0019] The gate and drain of M1P204 are connected to the gate of M2P206, the gate of M3P208, and the drain of M2N214. M1P204, M2P206, and M3P208 are matched, which means they have the same current response according to a multiplier. The multiplier may be greater than 1, equal to 1, or less than 1. Thus, M1P204, M2P206, and M3P208 together form the first current mirror 238.

[0020] I REF The first terminal of 210 is V DDS It connects to 114. REF The second terminal of 210 is connected to the drain and gate of M1N212 and the gate of M2N214. The source of M1N212 is connected to the source of M2N214, the source of M3N216, the source of M4N218, and V DDD It is connected to the domain ground 112. M1N212 and M2N214 are matched. Thus, M1N212 and M2N214 together form the second current mirror 240.

[0021] The drain and gate of M3N216 are connected to the drain of M2P206. The drain of M4N218 is connected to the drain of M3P208 and to the input of the first inverter 224. M3N216 and M4N218 are matched. Thus, M3N216 and M4N218 form a third current mirror 242. The gate voltages of M1N240, M2N214, M3N216, M4N218, M1P204, M2P206, and M3P208 are applied to the diode-connected transistors M1N212, M3N216, and M1P204. REF It is set by [the specified method / system].

[0022] The source code for M3P208 is V DDD 122 is connected to the first terminal of resistor 220. The second terminal of resistor 220 is connected to the first terminal of capacitor 222, the voltage input of the first inverter 224, the voltage input of SR latch 230, the voltage input of buffer 232, and the first voltage input of level shifter 234. The second terminal of capacitor 222 is connected to V DDD It is connected to the domain ground 112. Both resistor 220 and capacitor 222 are negative voltage glitches, etc. DDD A low-pass filter is formed to remove short-term transient fluctuations at 122. This allows the device connected to node A244 to receive V DDD Power will be supplied from point 122.

[0023] The output of the first inverter 224 is connected to the set (S) input of the SR latch 230. The output of the second inverter 226 is connected to the reset (R) input of the SR latch 230. In one example, the input of the second inverter 226 is connected to the (V) input when the boot sequence of the MCU 104 is completed successfully, such as when the boot sequence is completed without detecting a voltage glitch. DDD(In voltage domain 124) it is set to logic 0. By setting the input of the second inverter 226 to zero, the output of the second inverter 226 becomes logic 1. This triggers the reset function of the SR latch 230, setting the latched value and output of the SR latch 230 to zero. The output (Q) of the SR latch 230 is connected to the input of the buffer 232.

[0024] The output of buffer 232 is connected to the data input (IN) of level shifter 234. The output of third inverter 228 is connected to the / ENABLE (inverted enable) input of level shifter 234 and the / CLR (inverted clear) input of D latch 236. In one example, when the boot sequence of MCU 104 is successfully completed, the input of third inverter 228 is (V DDS (In voltage domain 116) set to logic 0.

[0025] The output of level shifter 234 is set to the CLK input of D latch 236. DDS 114 is connected to the second voltage input of the level shifter 234, and as a result the level shifter 234 adjusts the V at its input. DDD From voltage domain 122, the V at its output DDS The voltage can be shifted to domain 116. DDS 114 is also connected to the voltage input of D latch 236 and the data input (D) of D latch 236. Thus, the data input of D latch 236 is logic 1 (V DDS The D latch 236 receives the voltage corresponding to 114). The D latch 236 does not store this logic 1 until its CLK input receives a rising edge (low-to-high voltage transition). The output (Q) of the D latch 236 is the output of the negative glitch detector 146, indicating whether or not a negative glitch was detected.

[0026] The level shifter 234 has the same logical value as the input signal but operates in a different voltage range (for example, 0V to V at the input). DDD During the interval and at the output, 0V to V DDSIt generates an output signal spanning (between), and therefore this output signal is compatible with circuit elements in another voltage domain. Thus, the level shifter 234 shifts the output from VGM102 (voltage glitch index) indicating a voltage glitch to V DDS Enables the provision of POR132 or other security circuits in voltage domain 116. The voltage glitch index is V DDD Voltage domain 122 to V DDS Shifting to voltage domain 116 helps protect the voltage glitch indicator and any actions that may be taken in response to it against external adversarial interference in which a voltage glitch indicator signal may exist.

[0027] When the input to the third inverter 228 is logic 1, the level shifter 234 is enabled and the D latch 236 is reset to store logic 0. In some examples, the input to the third inverter 228 is configured to be logic 1 after a successful boot sequence of the MCU 104.

[0028] The M2N214 has the same gate-source voltage (V) as the M1N212. GS Since it has, the second current mirror 240 receives I from the drain-source path of the diode-connected M1N212. REF Reflecting this, the current flows through the drain-source path of M2N214 (using a first current multiplier that depends on the parameters of M1N212 and M2N214). Similarly, M2P206 has the same V as M1P204. GS Therefore, the first current mirror 238 has I from the source-drain path of the diode-connected M1P204. REF This is reflected and the current flows through the source-drain path of M2P206 (using a second current multiplier that depends on the parameters of M1P204 and M2P206).

[0029] The M3P208 receives the same gate voltage as the M1P204, and as a result, the M3P208 has the same V GSWhen it has, M3P208 has the same source-drain current as M1P204 (using a third current multiplier that depends on the parameters of M1P204 and M3P208). However, the source voltage of M3P208 is V REF instead of V DDD 122. During normal operation without glitches, V DDD >V REF . This means that during normal operation without glitches, M3P208 has a more negative V GS than M1P204, and as a result, a higher current flows through the source-drain path of M3P208 than the I REF flowing through the source-drain path of M1P204. Since M4N218 has the same gate-source voltage (V GS ) as M3N216, the third current mirror 242 reflects the I REF from the drain-source path of the diode-connected M3N216 and passes it through the drain-source path of M4N218 (using a fourth current multiplier that depends on the parameters of M3N216 and M4N218).

[0030] Node B246 is arranged between the drain of M3P208, the drain of M4N218, and the input of the first inverter 224. The first current I1 (mirrored from M1P204) flows through the source-drain path of M3P208 from V DDD 122 towards node B246. I1 depends on a factor that includes I REF , V REF , V DDD 122, and the product of the first current multiplier (for the current through M2N214) and the third current multiplier (for the current through M3P208). The second current 12 (mirrored from M3N216) flows away from node B246 through the drain-source path of M4N218 towards the V DDD domain ground 112. I2 depends on I REF , V REFand depends on a factor that includes the product of a first current multiplier (for the current through M2N214), a second current multiplier (for the current through M2P206), and a fourth current multiplier (for the current through M4N218).

[0031] The product of the first current multiplier (for the current through M2N214) and the third current multiplier (for the current through M3P208) may be equal to or different from the product of the first current multiplier (for the current through M2N214), the second current multiplier (for the current through M2P206), and the fourth current multiplier (for the current through M4N218). In other words, I REF The total current multiplier from I REF 210 to I1 may be equal to or different from the total current multiplier from I GS The V GS of M3P208 is greater than the V DDD of M1P204, so I1 is selected to be greater than I2. Since I1 is greater than I2, the input of the first inverter 224 is charged, and as a result, the input of the first inverter 224 becomes logic 1 and the output of the first inverter 224 becomes logic 0. The logic 0 output of the first inverter 224 represents the normal V REF without glitches. In some examples, the total current multiplier also responds to process, voltage, or temperature (PVT) variations, and the variation of the negative glitch detection threshold is selected to be symmetric about the negative glitch detection threshold set using V

[0032] V DDD When 122 glitches and becomes equal to V REF the V GS of M3P208 becomes equal to the V GS of M1P204, so I1 becomes equal to I2. When V DDD 122 glitches and V REFWhen it becomes smaller than, I1 becomes smaller than I2, and the input of the first inverter 224 discharges. As a result, the input of the first inverter 224 changes from the voltage corresponding to logic 1 to the voltage corresponding to logic 0. Therefore, the voltage at node B246 corresponding to logic 1 becomes V DDD >V REF (normal operation), indicating that I1 > I2, and the voltage at node B246 corresponding to logic 0 is V DDD <V REF (negative glitch), indicating that I1 < I2. Also, as described above, V REF functions as a threshold voltage for detecting negative glitches. This means that the detection threshold voltage can be adjusted by adjusting V REF .

[0033] Logic 0 at the input of the first inverter 224 represents a glitch of V DDD 112, which means that the output of the first inverter 224 providing the set input to the S-R latch 230 is logic 1. As a result, the S-R latch 230 latches and outputs logic 1, and consequently, the data input of the level shifter 234 becomes V DDD the voltage corresponding to logic 1 in voltage domain 124. The level shifter 234 then outputs V DDS the voltage corresponding to logic 1 in voltage domain 116. The CLK input of the D latch 236 recognizes this change from logic 0 to logic 1 as a rising clock edge. As a result, the D latch 236 latches, and the logic 1 (V DDS 114) received by the data input of the D latch 236 is isolated from the voltage glitch injection attack in V DDD voltage domain 124 and stored in V DDS voltage domain 116. In some examples, the output of the D latch 236 indicating a negative glitch is stored in V DDS a memory (such as a non-volatile memory) within voltage domain 116, and the output of the D latch 236 triggers the / MCU104's POR132 (and / or other security circuits).

[0034] In some cases, the negative glitch detector 146 can detect negative supply voltage glitches across various PVT corners. The negative glitch detector 146 is robust across PVT corners for the following reasons, but are not limited to these: Firstly, the programming of the gate voltages of both M3P208 and M4N218 is the same. REF Since is used, the negative glitch detector 148 is I REF It is resistant to fluctuations. Secondly, the bulk voltage of the PMOS transistor remains almost the same during negative glitches. Thirdly, the transient behavior does not depend on small-signal parameters such as the transistor's RDS (small-signal drain-source resistance).

[0035] In one example, V REF The voltage is 1.04 volts (V) and can vary within a range of ±50 millivolts (mV). The temperature can vary from -40°C to 125°C. Normal V DDD The voltage is 1.28V, and the total current multiplier applied to I1 and I2 is 16, allowing the negative glitch detector 146 to detect negative supply voltage glitches with a duration of 1 nanosecond. In some examples, higher current multipliers increase the sensitivity of the negative glitch detector 146, enabling faster glitch detection. In some examples, the first current multiplier (for the current through M2N214) is 1, the second current multiplier (for the current through M2P206) is 8, the third current multiplier (for the current through M3P208) is 12, and the fourth current multiplier (for the current through M4N218) is 16.

[0036] Due to various features of the negative glitch detector 146, the negative glitch detector 146 can respond to negative glitches more quickly. Some examples of these features are described below, but are not limited to these. First, V DDD 122 is capacitively coupled to the gate of M3P208 via the gate-source parasitic capacitance of M3P208. This is V DDDWhen 122 decreases, the voltage at the gate of M2P206 also decreases, increasing the current through M2P206, which is reflected in the increase in I2 (current through M4N242) via M3N216, meaning that negative glitches can be detected more quickly. Secondly, the input voltage (V DDD Due to the relatively small capacitance between 122) and the output voltage (node ​​B246, which is the input to the first inverter 224), the output voltage can respond more quickly to glitch voltages. In some examples, V DDD The capacity between 122 and node B246 is limited to the source-drain capacity of M3P208. Thirdly, normal V DDD The change from 122 to a negative glitch voltage, and the voltage change at node B246 exhibiting a negative glitch, have the same (negative) polarity. This causes the voltage change at node B246 to be rapid, indicating a negative glitch.

[0037] Figure 3 is a schematic diagram providing an alternative figure 300 of a partial example of the negative glitch detector 146 in Figure 2. Alternative figure 300 is V DDD Domain grounding 112 and V DDD 122, differential amplifier 302, first p-type enhancement MOSFET (M1P) 304, second p-type enhancement MOSFET (M2P) 306, third p-type enhancement MOSFET (M3P) 308, current I REF A current source (I REF The circuit includes )310, a first n-type enhancement MOSFET (M1N)312, a second enhancement MOSFET (M2N)314, an inverter316, a buffer318, and an SR latch320.

[0038] The non-inverting input of the differential amplifier 302 is connected to the reference voltage V REF It is configured to receive. The inverting input of differential amplifier 302 is connected to the output of differential amplifier 302, the source of M1P304, and the source of M2P306. The gate and drain of M1P304 are connected to the gate of M2P306, the gate of M3P308, and I REFIt is connected to the first terminal of 310. M1P304, M2P306, and M3P308 together form the first current mirror 322.

[0039] I REF The second terminal of 310 is V DDD The domain ground 112 is connected to the source of M1N312 and the source of M2N314. The drain and gate of M1N312 are connected to the gate of M2N314 and the drain of M2P306. The drain of M2N314 is connected to the drain of M3P308 and the input of the first inverter 316. The source of M3P308 is connected to V DDD It is connected to 122. M1N312 and M2N314 together form the second current mirror 324.

[0040] The output of the first inverter 316 is connected to the input of the buffer 318. The output of the buffer 318 is connected to the configured input of the SR latch 320. The SR latch 320 is otherwise substantially similar to the SR latch 230 in Figure 2, and therefore the output of the SR latch 320 can be coupled to the input of the buffer 232 in Figure 2. REF 310 and the second current mirror 324 replace the current source I of M2N314. REF They can both be modeled as 210. Therefore, the operation of the negative glitch detector 146 in the alternative Figure 300 corresponds to the operation of the negative glitch detector 146 described with respect to Figure 2.

[0041] Figure 4 is a set of graphs 400 showing illustrative signals in the negative glitch detector of Figure 2. The set of graphs 400 includes the first graph 402, the second graph 404, and the third graph 406. The horizontal axis of each graph represents time, and the vertical axis of each graph represents voltage. The first graph 402 is V DDD Curves 408 and V REF The second graph 404 includes curve 410. The third graph 406 includes node B voltage curve 412.

[0042] In T1, V DDDCurve 408 is V REF decreases below a certain level of Curve 410, such that V DDD 122 has a negative glitch voltage. At T2, I1 < I2, and when the node discharges, the node B voltage curve 412 drops to a voltage corresponding to logic 0. At T3, the logic 0 at which the node B voltage curve 412 transitioned at T2 propagates through the S-R latch 230 (as logic 1 through the first inverter 224), and the S-R latch output 414 transitions to a voltage corresponding to logic 1, indicating a negative glitch. At T4, V DDD Curve 408 is V REF rises above Curve 410 and returns to the normal voltage. At T5, V DDD 122 causes I1 > I2, such that the node B voltage curve 412 returns to a level corresponding to logic 1. In some examples, there is a delay between when Curve 408 drops below Curve 410 (the threshold voltage) at T4 and when the node B voltage curve 412 returns to a level corresponding to logic 0 at T5. In some examples, this delay is related to the capacitance of the device or the response time of the device (such as gate response time).

[0043] FIG. 5 is a circuit diagram of an exemplary positive glitch detector 148. The positive glitch detector 148 is similar to the negative glitch detector 146 of FIG. 2. The positive glitch detector 148 has a buffer 502 instead of the first inverter 224, the resistor 220 is the first resistor (R1), and the capacitor 222 is the first capacitor (C1) 222. The positive glitch detector 148 further includes a second resistor (R2) 504, a third resistor (R3) 506, a second capacitor (C2) 508, a fourth resistor (R4) 510, and a third capacitor (C3) 512. Note that the first current mirror 238 refers to M1P204, M2P206, and M3P208, and the connections therebetween (described in relation to FIG. 2). Additional resistive and capacitive elements are incidentally included within the dotted box.

[0044] ​​​​The output of differential amplifier 202 is coupled to the first terminal of R2 504, the source of M1P204, and the source of M2P206. The second terminal of R2 504 is connected to the inverting input of differential amplifier 202 and the first terminal of R3 506. The second terminal of R3 506 is connected to V DDD domain ground 112. Both R2 504 and R3 506 form a voltage divider, and as a result, the threshold voltage V TH is equal to V REF multiplied by the resistance of R3 506 and divided by the sum of the resistances of R2 504 and R3 506. The resistances of R2 504 and R3 506 are selected such that V TH is greater than the voltage of V DDD 122 during normal operation, i.e., as a result, a voltage greater than V TH corresponds to a positive glitch. Therefore, V TH functions as a threshold voltage for detecting positive glitches.

[0045] The gate and drain of M1P204 are connected to the first terminal of C2 508, the gate of M2P206, and the first terminal of R4 510. The second terminal of C2 508 is connected to V DDD 122, the source of M3P208, and the first terminal of R1 220. The second terminal of R4 510 is connected to the first terminal of C3 512 and the gate of M3P208. The second terminal of C3 512 is connected to V DDD domain ground 112.

[0046] The functions of the first, second, and third current mirrors 238, 240, and 242 that generate currents I1 and I2 are similar to the functions described for negative glitch detector 146. For V DDD corresponding to the normal operating voltage of V DDD <V TH [[ID=3)2]], I1 < I2, the input of the first buffer 502 discharges (at node B246), and the set input of S-R latch 230 receives a voltage corresponding to logic 0. For V DDD corresponding to a positive glitch of V DDD > V THIn this case, I1 > I2, the input to the first buffer 502 charges (at node B246), the set input to the SR latch 230 receives the voltage corresponding to logic 1, and the SR latch 230 latches logic 1. The level shifter 234 shifts the resulting logic 1 output of the SR latch 230 (through the second buffer 232) to V DDD Voltage domain 124 to V DDS The voltage shifts to domain 116. This causes the CLK input of D latch 236 to recognize the rising edge, and as a result, D latch 236 latches and outputs logic 1. Thus, as described above, V TH This is the threshold voltage for indicating a positive glitch.

[0047] If there is no RC circuit formed by R4 510 and C3 512, V DDD The increased voltage due to the positive glitch at 122 leaks into the gate of M3P208 through the source-gate capacitance of M3P208. The increased gate voltage of M3P208 decreases I1 or slows down the increase of I1. This causes the positive glitch detector 148 to detect the positive glitch more late, and / or above the effective voltage at which the positive glitch detector 148 indicates a positive glitch. DDD 122 Increase the threshold voltage. The resistor R4 510 and the capacitance C3 512 are selected so that the gate voltage of the M3P208 remains approximately constant for the duration of the positive glitch, which is intended to be sufficient for detection by the positive glitch detector 148.

[0048] C2 508 is V DDD 122 is capacitively coupled to the gate of M2P206. When a positive glitch occurs, the voltage at the gate of M2P206 increases due to the charge leaking through C2 508, and as a result, the source-drain current of M2P206 decreases. This lowers the gate voltage of M3N216, and thereby lowers I2 due to the third current mirror 242. (In some examples, this is because the effective positive glitch detection threshold voltage is V TH This means lower than V. In some examples, the effective threshold voltage is VTH Slightly lower than, for example, V TH (It is several percent lower than.) Therefore, after a positive glitch is initiated, Il increases more rapidly than I2 in response to the positive voltage glitch, which means that C2 508 increases the response speed and sensitivity of the positive glitch detector 148.

[0049] In some cases, increasing the resistance of R4 510 and the capacitances of C2 508 and C3 512 can reduce the minimum glitch duration detectable by the positive glitch detector 148. In some cases, increasing the resistance of R4 510 and the capacitances of C2 508 and C3 512 can increase the sensitivity of the voltage at node B246 to PVT fluctuations, potentially reducing the accuracy of the positive glitch detector 148. Therefore, in some cases, the resistance of R4 510 and the capacitances of C2 508 and C3 512 are selected based on a balance between the detector response speed and the detector accuracy.

[0050] Figure 6 is a schematic diagram providing an alternative diagram 600 of a partial example of the positive glitch detector 148 in Figure 5. The alternative diagram 600 of a partial example of the positive glitch detector 148 is similar to the alternative diagram 300 of a partial example of the negative glitch detector 146 (see Figure 3). In the alternative diagram 600 of the positive glitch detector 148, V REF is V TH Equivalent to . Alternative Figure 600 also includes a first capacitor (Cl) 602, a second capacitor (C2) 604, a third capacitor (C3) 606, and a resistor (R) 608. In some examples, C1 602, C2 604, and C3 606 are polarized capacitors. In some examples, they are different types of capacitors.

[0051] The inverting input and output of differential amplifier 302 are connected to the first terminal of C1 602, the source of M1P304, and the source of M2P306. The gate and drain of M1P304 are connected to the gate of M2P306, and I REFThe first terminal of 310 is connected to the first terminal of C2 604 and the first terminal of R608. The second terminal of C2 604 is connected to V DDD 122 is connected to the source of M3P308. The second terminal of R608 is connected to the first terminal of C3 606 and the gate of M3P308. The second terminal of C3 606 is connected to V DDD It is connected to the domain ground 112. The drain of M3P308 is connected to the drain of M2N314 and to the input of buffer 318, rather than to the input of buffer 318 via inverter 316 (inverter 316 is not included in the positive glitch detector 148 or its alternative in Figure 600).

[0052] The output of buffer 318 is coupled to the configured input of SR latch 320. SR latch 320 may otherwise be substantially similar to SR latch 230 in Figure 5, and therefore the output of SR latch 320 may be coupled to the input of buffer 232 in Figure 5.

[0053] V DDD 122>V TH In this case, I1 > I2. This causes the configured input of SR latch 320 to become high, corresponding to logic 1. The non-inverting output of SR latch 320 also becomes logic 1, indicating a positive glitch.

[0054] Figure 7 is a set of graphs showing illustrative signals in the positive glitch detector of Figure 5. The set of graphs 700 includes the first graph 702, the second graph 704, and the third graph 706. The horizontal axis of each graph represents time, and the vertical axis of each graph represents voltage. The first graph 702 is V DDD Curve 708 and V TH The second graph, 704, includes curve 710. The third graph, 706, includes node B voltage curve 712.

[0055] In T1, V DDD Curve 708 is V THIncreases above the level of a lower effective voltage glitch threshold (not shown) (as described above with respect to C2 508, R4 510, and C3 512). As a result, I1 > I2, and as the node charges, the node B voltage curve 712 rises to a voltage corresponding to logic 1. At T2, V DDD Curve 708 increases above a certain level of V TH Curve 710. At T3, the logic 1 of the node B voltage curve 712 propagates through the S-R latch 230, and the S-R latch output curve 714 transitions to a voltage corresponding to logic 1, indicating a positive glitch. At T4, V DDD Curve 708 falls below V TH Curve 710 and returns to the normal voltage. At T5, V DDD 122 causes I1 < I2, and as a result, the node B voltage curve 712 returns to a level corresponding to logic 0. In some examples, there is a delay between when V DDD Curve 708 falls below V TH Curve 710 (the threshold voltage) at T4 and when the node B voltage curve 712 returns to a level corresponding to logic 0 at T5. In some examples, this delay is related to the capacitance of the device or the response time of the device (e.g., the gate response time).

[0056] Within the scope of the claims, modifications to the described embodiments are possible, and other embodiments are possible.

[0057] In some examples, V DDD The voltage is lower than the intended V DDD Voltage but is used as a threshold voltage for a negative glitch, and if this state persists for a sufficient duration, this state corresponds to an error state other than a negative glitch. In some examples, V REF Is greater than V DDD The voltage is higher than the intended V DDD Voltage but is used as a threshold voltage for a positive glitch, and V THIf the value is smaller than and this condition persists for a sufficient duration, this condition corresponds to an error condition other than a positive glitch. In other words, "normal operation" as used herein refers to operation that does not exhibit a negative or positive glitch, and is not necessarily used to indicate error-free operation.

[0058] In some examples, differential amplifier 202 is an amplified reference buffer. In some examples, the reference voltage does not require amplification.

[0059] In some cases, V DDR 118 is used to supply power to the differential amplifier 202 and the current source 210.

[0060] In some cases, I REF This can be a positive temperature coefficient current (current increases with increasing temperature), a constant current, or a negative temperature coefficient current (current decreases with decreasing temperature).

[0061] In some cases, a latch input that can change the state of the latch upon receiving a logical transition (such as a rising or falling edge) or a certain logical value (for example, one that depends on a rising or falling edge such as a clock edge for a different input) may be called a latch data input.

[0062] In some examples, the RC circuits corresponding to resistor 220 and capacitor 222 (R1 220 and C1 222) can be replaced with low-bandwidth voltage regulators or buffers.

[0063] In some examples, the positive glitch detector 148 does not include C2 508 and / or R4 510 and C3 512.

[0064] In some examples, transistors other than MOSFETs are used.

[0065] In some examples, switches other than transistors are used.

[0066] In some examples, resistive elements other than resistors are used.

[0067] The term “coupled” is used throughout this specification. This term may encompass connections, communications, or signaling paths that enable a functional relationship consistent with the descriptions herein. For example, if device A provides a signal to control control device B to perform a certain action, in the first example, device A is coupled to device B, and in the second example, if intervening component C does not substantially alter the functional relationship between device A and device B, device A is coupled to device B via intervening component C, and device B is controlled by device A via a control signal provided by device A.

[0068] In this description, the term "and / or" (when used in the form of A, B, and / or C, etc.) means any combination or subset of A, B, and C, such as (a) A only, (b) B only, (c) C only, (d) A and B, (e) A and C, (f) B and C, and (g) A, B, and C. Also, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") means an implementation that includes (a) at least one A, (b) at least one B, and (c) any one of at least one A and at least one B.

[0069] A device “configured” to perform a certain task or function may be configured by the manufacturer at the time of manufacture to perform that function (e.g., by programming and / or wiring), or may be configured (or reconfigurable) by a user after manufacture to perform such function and / or other additional or alternative functions. Such configuration may be via the device’s firmware and / or software programming, or via the configuration and / or layout of hardware components, the interconnection of devices, or a combination thereof.

[0070] As used herein, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” are interchangeable. Unless otherwise specified, these terms are generally used to mean interconnections or terminations between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0071] A circuit or device described as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more power sources (such as voltage and / or current power supplies) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), adapted to be coupled to at least some of the passive elements and / or power sources, thereby forming the described structure, either at the time of manufacture or at a later point in time, for example, by an end user and / or a third party.

[0072] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no modification to the remaining circuit elements. For example, metal oxide silicon FETs (MOSFETs) (n-channel MOSFETs, nMOSFETs, p-channel MOSFETs (pMOSFETs), etc.), bipolar junction transistors (BJTs - e.g., NPN or PNP), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used instead of or in conjunction with one or more of the devices described herein. The transistors may be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. The devices may also be mounted in or on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0073] The circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to the functionality available before the replacement of components. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series or parallel to provide the amount of impedance represented by the indicated resistor. For example, a resistor described herein as a single component may instead be multiple resistors or capacitors, each of which may be coupled in parallel between the same nodes. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors, each coupled in parallel between the same nodes, as a single resistor or capacitor. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors, each coupled in series between the same two nodes, each of which may be a single resistor or capacitor.

[0074] In the examples described, some elements may be included in an integrated circuit, while other elements may be outside the integrated circuit, while in other examples, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features shown to be outside the integrated circuit may be included in the integrated circuit, and / or some features shown to be inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term “integrated circuit” means one or more circuits that are (1) incorporated in / on a semiconductor substrate, (2) incorporated in a single semiconductor package, (3) incorporated in the same module, and / or (4) incorporated in / on the same printed circuit board.

[0075] The use of the term "grounding" in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suitable for the teachings described herein. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10 percent of the stated value, and if the value is zero, it means a reasonable range of values ​​around zero. Modifications to the described embodiments are possible within the claims, and other embodiments are possible.

Claims

1. A voltage glitch detector, A current source including first and second terminals, A latch including input and output, A first transistor including a source, drain, and gate, A second transistor including a source, drain, and gate, A third transistor comprising a source, drain, and gate, wherein the source of the third transistor is coupled to the source of the second transistor, and the gate and drain of the third transistor are coupled to the gate of the first transistor, the gate of the second transistor, and the first terminal of the current source, A fourth transistor comprising a source, drain, and gate, wherein the drain of the fourth transistor is coupled to the drain of the first transistor and the input of the latch, A fifth transistor comprising a source, drain, and gate, wherein the source of the fifth transistor is coupled to the source of the fourth transistor and the second terminal of the current source, and the gate and drain of the fifth transistor are coupled to the gate of the fourth transistor and the drain of the second transistor. A voltage glitch detector, including one.

2. A voltage glitch detector according to claim 1, further comprising an inverter having an input and an output, wherein the input of the inverter is coupled to the drains of the first and fourth transistors, and the output of the inverter is coupled to the input of the latch.

3. A voltage glitch detector according to claim 1, A first capacitor including first and second terminals, wherein the first terminal of the first capacitor is coupled to the source of the first transistor, A second capacitor including the first and second terminals, A resistor having first and second terminals, wherein the first terminal of the resistor is coupled to the gate and drain of the third transistor, the second terminal of the first capacitor, and the gate of the second transistor, and the second terminal of the resistor is coupled to the first terminal of the second capacitor and the gate of the first transistor, A voltage glitch detector, which further includes the following.

4. A voltage glitch detector according to claim 1, The input of the latch is a data input, and the latch includes a power input. The voltage glitch detector further includes a filter having an input and an output, wherein the input of the filter is coupled to the source of the first transistor, and the output of the filter is coupled to the power input of the latch. Voltage glitch detector.

5. A voltage glitch detector according to claim 4, The latch is the first latch, The voltage glitch detector, A second latch including input and output, A level shifter including data input, first power input, second power input, and output, It further includes, The data input of the level shifter is coupled to the output of the first latch, the first power input of the level shifter is coupled to the output of the filter, and the output of the level shifter is coupled to the input of the second latch. Voltage glitch detector.

6. A voltage glitch detector according to claim 1, The current source is a first current source, and the first current source includes a sixth transistor and a seventh transistor, each of the sixth and seventh transistors including a source, a drain, and a gate, the drain of the sixth transistor being connected to the first terminal of the first current source, and the sources of the sixth and seventh transistors being connected to the second terminal of the first current source. The voltage glitch detector further includes a second current source having a first terminal and a second terminal, wherein the second terminal of the second current source is coupled to the gate and drain of the seventh transistor and the gate of the sixth transistor. Voltage glitch detector.

7. A voltage glitch detector according to claim 1, wherein the first, second, and third transistors are matched, and the fourth and fifth transistors are matched.

8. A voltage glitch detector, A latch including input and output, A first transistor comprising a source, drain, and gate, wherein the source-drain current of the first transistor responds to a comparison between a reference current and a reference voltage and the voltage at the source of the first transistor. A second transistor comprising a source, drain, and gate, wherein the drain of the first transistor is coupled to the drain of the second transistor and the input of the latch, and the drain-source current of the second transistor responds to the reference current. Includes, The input of the latch is configured to have a voltage that responds to the polarity of the difference between the source-drain current of the first transistor and the drain-source current of the second transistor. Voltage glitch detector.

9. A voltage glitch detector according to claim 8, The source of the first transistor is adapted to be coupled to a voltage source that provides a source voltage. The source of the second transistor is adapted to be coupled to ground. Voltage glitch detector.

10. A voltage glitch detector according to claim 9, The system further includes an inverter coupled between the drains of the first and second transistors and the input of the latch, The reference voltage is a voltage lower than the source voltage. The voltage glitch detector is configured to detect negative glitches. Voltage glitch detector.

11. A voltage glitch detector according to claim 9, The reference voltage is a voltage higher than the source voltage, and the voltage glitch detector is configured to detect a positive glitch. Voltage glitch detector.

12. A processing system, A security circuit configured to perform security functions, A power source configured to provide a source voltage, A processor coupled to the power source, A voltage reference configured to provide a reference voltage, Voltage glitch detector, Includes, The voltage glitch detector, A current source including first and second terminals, A latch including an input and an output, wherein the output of the latch is coupled to the security circuit, A first transistor comprising a source, drain, and gate, wherein the source of the first transistor is coupled to the power source, A second transistor including a source, drain, and gate, A third transistor comprising a source, drain, and gate, wherein the voltage reference is coupled to the source of the third transistor and the source of the second transistor, and the gate and drain of the third transistor are coupled to the gate of the first transistor, the gate of the second transistor, and the first terminal of the current source, A fourth transistor comprising a source, drain, and gate, wherein the drain of the fourth transistor is coupled to the drain of the first transistor and the input of the latch, A fifth transistor comprising a source, drain, and gate, wherein the source of the fifth transistor is coupled to the source of the fourth transistor and the second terminal of the current source, and the gate and drain of the fifth transistor are coupled to the gate of the fourth transistor and the drain of the second transistor, including, Processing system.

13. A processing system according to claim 12, wherein the security circuit includes a power-on reset circuit.

14. A processing system according to claim 12, wherein the voltage glitch detector is located in separate voltage regions that are electrically isolated from each other.

15. A processing system according to claim 12, wherein the voltage glitch detector further includes an inverter having an input and an output, the input of the inverter being coupled to the drains of the first and fourth transistors, and the output of the inverter being coupled to the input of the latch.

16. The processing system of claim 12, The voltage glitch detector is a first capacitor including first and second terminals, wherein the first terminal of the first capacitor is coupled to the source of the first transistor, A second capacitor including the first and second terminals, A resistor having first and second terminals, wherein the first terminal of the resistor is coupled to the gate and drain of the third transistor, the second terminal of the first capacitor, and the gate of the second transistor, and the second terminal of the resistor is coupled to the first terminal of the second capacitor and the gate of the first transistor, A voltage glitch detector, which further includes the following.

17. The processing system of claim 12, The input of the latch is a data input, and the latch includes a power input. The voltage glitch detector further includes a filter having an input and an output, wherein the input of the filter is coupled to the source of the first transistor, and the output of the filter is coupled to the power input of the latch. Voltage glitch detector.

18. The processing system of claim 17, The latch is the first latch, The voltage glitch detector, A second latch including input and output, A level shifter including a data input, a first power input, a second power input, and an output, wherein the data input of the level shifter is coupled to the output of the first latch, the first power input of the level shifter is coupled to the output of the filter, and the output of the level shifter is coupled to the input of the second latch, A voltage glitch detector, which further includes the following.

19. The processing system of claim 12, The current source is a first current source, and the first current source includes a sixth transistor and a seventh transistor, each of the sixth and seventh transistors including a source, a drain, and a gate, the drain of the sixth transistor being connected to the first terminal of the first current source, and the sources of the sixth and seventh transistors being connected to the second terminal of the first current source. The voltage glitch detector further includes a second current source having a first terminal and a second terminal, wherein the second terminal of the second current source is coupled to the gate and drain of the seventh transistor and the gate of the sixth transistor.

20. A processing system according to claim 12, wherein the first, second, and third transistors are matched, and the fourth and fifth transistors are matched, a voltage glitch detector.

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