AC-DC converter with intelligent capacitive energy storage regulator

Abstract

The power converter comprises a first solid-state switch connected between a first node and a second node, a storage capacitor coupled between the second node and a ground node, and a control system configured to control the charging of the storage capacitor. The control system is configured to determine the voltage level across the storage capacitor and, in response to determining that the voltage level across the storage capacitor is below a minimum voltage level, activate the first solid-state switch during a given positive half-cycle of AC power applied to the first node to allow current to flow from the first node to the second node and charge the storage capacitor, and in response to determining that the voltage level across the storage capacitor has reached a maximum voltage level, deactivate the first solid-state switch during a given positive half-cycle of AC power.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims the benefits of U.S. Provisional Application No. 63 / 462,376, filed on 27 April 2023, the disclosure of which is incorporated herein by reference. [Background technology]

[0002] This disclosure generally relates to power conversion techniques, and more specifically, to power conversion techniques for converting alternating current (AC) power to direct current (DC) power. Conventional approaches to converting AC power to DC power employ various analog circuits to achieve AC-DC voltage conversion. For example, one type of conventional AC-DC converter includes a transformer-based linear converter that utilizes a simple diode bridge, capacitors, and a voltage regulator, where the diode bridge is constructed using four independent diodes. Another type of conventional converter implements a switch-mode power supply architecture that utilizes a small high-frequency transformer and switching regulator to provide a DC voltage output. However, such conventional power conversion approaches unnecessarily require many circuit components that can lead to signal processing delays, inaccuracies, and / or increased overall costs for implementing the AC-DC converter. [Overview of the project]

[0003] Exemplary embodiments of this disclosure include power converters and techniques for converting AC power to DC power.

[0004] For example, an exemplary embodiment includes a power converter comprising a first solid-state switch, a storage capacitor, and a control system. The first solid-state switch is connected to an electrical path between a first node and a second node. The storage capacitor is coupled between the second node and a ground node. The control system is configured to control the charging of the storage capacitor, and is configured to determine the voltage level across the storage capacitor and, in response to determining that the voltage level across the storage capacitor is below a minimum voltage level, activate the first solid-state switch during a given positive half-cycle of AC power applied to the first node to allow current to flow from the first node to the second node to charge the storage capacitor, and in response to determining that the voltage level across the storage capacitor has reached a maximum voltage level, deactivate the first solid-state switch during a given positive half-cycle of AC power.

[0005] Another exemplary embodiment includes a power converter comprising a control system configured to control the charging of a storage capacitor using a current drawn from AC power applied to the input terminals of the power converter and to provide DC power to a load coupled to the output terminals of the power converter. The control system is configured to control the charging of the storage capacitor by monitoring the voltage level across the storage capacitor and, in response to determining that the monitored voltage level across the storage capacitor is below a minimum voltage level, causing a charging current to flow through the storage capacitor during a given positive half-cycle of AC power to charge the storage capacitor to a maximum voltage level, and in response to determining that the monitored voltage level across the storage capacitor is below a maximum voltage level and above a minimum voltage level, preventing a charging current from flowing through the storage capacitor during a given positive half-cycle of AC power.

[0006] Another exemplary embodiment includes a method for converting AC power into DC power to be stored in a storage capacitor, the conversion of AC power into DC power including monitoring the voltage level across the storage capacitor, causing a charging current to flow through the storage capacitor during a given positive half-cycle of AC power to charge the storage capacitor to a maximum voltage level in response to determining that the monitored voltage level across the storage capacitor is below a minimum voltage level, and preventing a charging current from flowing through the storage capacitor during a given positive half-cycle of AC power in response to determining that the monitored voltage level across the storage capacitor is below a maximum voltage level and above a minimum voltage level.

[0007] Other embodiments are described in the following "Modes for Carrying Out the Invention," which should be read in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0008] [Figure 1] A schematic representation of a power converter according to an exemplary embodiment of the present disclosure is shown. [Figure 2A] This is a timing diagram illustrating simulated waveforms showing exemplary modes of operation of a power converter according to exemplary embodiments of the present disclosure. [Figure 2B] This is a timing diagram illustrating simulated waveforms showing exemplary modes of operation of a power converter according to exemplary embodiments of the present disclosure. [Figure 2C] This is a timing diagram illustrating simulated waveforms showing exemplary modes of operation of a power converter according to exemplary embodiments of the present disclosure. [Figure 2D] This is a timing diagram illustrating simulated waveforms showing exemplary modes of operation of a power converter according to exemplary embodiments of the present disclosure. [Figure 3] A flowchart of a method for converting AC power to DC power according to an exemplary embodiment of the present disclosure is shown. [Figure 4] A power converter according to another exemplary embodiment of the present disclosure is schematically shown. [Figure 5] An exemplary embodiment of the present disclosure schematically illustrates an intelligent electrical device for implementing a power converter. [Modes for carrying out the invention]

[0009] Embodiments of the present disclosure will be described in further detail here relating to power converters and techniques for converting AC power to DC power. In exemplary embodiments, the power converter comprises a first solid-state switch, a storage capacitor, and a control system. The first solid-state switch is connected to an electrical path between a first node and a second node. The storage capacitor is coupled between the second node and a ground node. The control system is configured to control the charging of the storage capacitor. The control system is configured to determine the voltage level across the storage capacitor and, in response to determining that the voltage level across the storage capacitor is below a minimum voltage level, activate the first solid-state switch during a given positive half-cycle of AC power applied to the first node to allow current to flow from the first node to the second node to charge the storage capacitor, and in response to determining that the voltage level across the storage capacitor has reached a maximum voltage level, deactivate the first solid-state switch during a given positive half-cycle of AC power.

[0010] In another exemplary embodiment, which may be combined with one or more embodiments of the preceding paragraphs, the minimum voltage level and the maximum voltage level are programmable parameters of the control system.

[0011] In another exemplary embodiment, which may be combined with one or more embodiments of the preceding paragraphs, the storage capacitor is configured as a DC power supply that provides DC power to a load coupled to a second node of the power converter.

[0012] In another exemplary embodiment, which may be combined with one or more embodiments of the preceding paragraphs, the control system is configured to keep the first solid-state switch inactive for the entire duration of each negative half-cycle of AC power.

[0013] In another exemplary embodiment, which may be combined with one or more embodiments of the preceding paragraphs, the first solid-state switch includes a high-voltage MOSFET.

[0014] In another exemplary embodiment, which may be combined with one or more embodiments of the preceding paragraphs, the control system comprises a driver circuit configured to generate a regulated control voltage using a current drawn from the AC power during a negative half-cycle of the AC power, and to use the regulated control voltage to drive a first solid-state switch during a positive half-cycle of the AC power.

[0015] In another exemplary embodiment, which may be combined with one or more embodiments of the preceding paragraphs, the control system comprises a voltage sensing circuit, a first comparator, and a second comparator. The voltage sensing circuit is configured to generate a sense voltage proportional to the voltage level across a storage capacitor. The first comparator is configured to compare the sense voltage with a first threshold voltage and generate a first output signal based on the comparison between the sense voltage and the first threshold voltage. The second comparator is configured to compare the sense voltage with a second threshold voltage and generate a second output signal based on the comparison between the sense voltage and the second threshold voltage. The control system is configured to activate a first solid-state switch during a given positive half-cycle of AC power in response to determining, based on the first and second output signals of the first and second comparators, that the sense voltage is less than both the first and second threshold voltages.

[0016] In another exemplary embodiment, which may be combined with one or more embodiments of the preceding paragraphs, the control system further comprises a second solid-state switch and a latch circuit. The second solid-state switch is coupled to the control terminal of the first solid-state switch. The latch circuit comprises a first input port, a second input port, and an output port. The first input port is coupled to the output port of the first comparator and configured to receive a first output signal. The second input port is coupled to the output port of the second comparator and configured to receive a second output signal. The output port is coupled to the control terminal of the second solid-state switch. The latch circuit is configured to output a control signal for controlling the activation and deactivation of the second solid-state switch based on the logic level of the first output signal from the first comparator and the logic level of the second output signal from the second comparator. Activation of the second solid-state switch deactivates the first solid-state switch, and deactivation of the second solid-state switch allows the first solid-state switch to be activated during a positive half-cycle of AC power.

[0017] In another exemplary embodiment, which may be combined with one or more embodiments of the preceding paragraphs, the latch circuit includes a set-reset latch circuit.

[0018] In another exemplary embodiment, which may be combined with one or more embodiments of the preceding paragraphs, at least one of the first threshold voltage and the second threshold voltage is programmable.

[0019] In another exemplary embodiment, which may be combined with one or more embodiments of the preceding paragraphs, the voltage sensing circuit comprises a voltage divider circuit coupled in parallel to a storage capacitor. The voltage divider circuit comprises a sense node coupled to the input terminals of a first comparator and a second comparator. The voltage divider circuit generates a sense voltage on the sense node.

[0020] In another exemplary embodiment, which may be combined with one or more embodiments of the preceding paragraphs, the voltage divider circuit includes a programmable voltage division ratio.

[0021] Another exemplary embodiment includes an intelligent electrical device comprising a power converter according to one or more embodiments of the preceding paragraph, wherein the storage capacitor is configured as a DC power supply that supplies DC power to the control circuit of the intelligent electrical device. The intelligent electrical device may be, for example, an intelligent solid-state circuit breaker device or an intelligent solid-state optical switch device.

[0022] Another exemplary embodiment includes a power converter comprising a control system configured to control the charging of a storage capacitor using a current drawn from AC power applied to the input terminals of the power converter and to provide DC power to a load coupled to the output terminals of the power converter. The control system is configured to control the charging of the storage capacitor by monitoring the voltage level across the storage capacitor and, in response to determining that the monitored voltage level across the storage capacitor is below a minimum voltage level, causing a charging current to flow through the storage capacitor during a given positive half-cycle of AC power to charge the storage capacitor to a maximum voltage level, and in response to determining that the monitored voltage level across the storage capacitor is below a maximum voltage level and above a minimum voltage level, preventing a charging current from flowing through the storage capacitor during a given positive half-cycle of AC power.

[0023] In another exemplary embodiment, which may be combined with one or more embodiments of the preceding paragraphs, the control system is further configured to control the charging of the storage capacitor by preventing charging current from flowing to the storage capacitor during a negative half-cycle of AC power, regardless of the monitored voltage level across the storage capacitor.

[0024] In another exemplary embodiment, which may be combined with one or more embodiments of the preceding paragraphs, DC power is used to power the control circuit of an intelligent electrical device.

[0025] Another exemplary embodiment includes a method for converting AC power into DC power to be stored in a storage capacitor, the conversion of AC power into DC power including monitoring the voltage level across the storage capacitor and, in response to determining that the monitored voltage level across the storage capacitor is below a minimum voltage level, causing a charging current to flow through the storage capacitor during a given positive half-cycle of AC power to charge the storage capacitor to a maximum voltage level, and preventing a charging current from flowing through the storage capacitor during a given positive half-cycle of AC power in response to determining that the monitored voltage level across the storage capacitor is below a maximum voltage level and above a minimum voltage level.

[0026] In another exemplary embodiment, which may be combined with one or more embodiments of the preceding paragraphs, the method further includes preventing a charging current from flowing into the storage capacitor during a negative half-cycle of AC power, regardless of a monitored voltage level across the storage capacitor.

[0027] It should be understood that the various features shown in the attached drawings are schematic diagrams and not drawn to scale. Furthermore, identical or similar reference numerals are used throughout the drawings to indicate identical or similar features, elements, or structures, and therefore, detailed descriptions of identical or similar features, elements, or structures are not repeated for each of the drawings. In addition, the term “exemplary” as used herein means “serving as an example, case, or illustration.” Any embodiment or design described herein as “exemplary” should not be construed as being preferable or advantageous over other embodiments or designs.

[0028] Furthermore, the phrase “configured,” as used in conjunction with circuits, structures, elements, components, etc., that perform one or more functions, or otherwise provide several functions, is intended to encompass embodiments in which circuits, structures, elements, components, etc. are implemented in hardware, software, and / or combinations thereof, and in hardware-based implementations, and it should be understood that hardware may comprise individual circuit elements (e.g., transistors, inverters, etc.), programmable elements (e.g., application-specific integrated circuit (ASIC) devices, field-programmable gate array (FPGA) devices, etc.), processing devices (e.g., central processing unit (CPU) devices, graphical processing unit (GPU) devices, microcontroller devices, etc.), one or more integrated circuits, and / or combinations thereof. Therefore, as a mere example, where circuits, structures, elements, components, etc. are defined to be configured to provide a particular function, the intention is to cover embodiments comprising elements, processing devices, and / or integrated circuits that enable circuits, structures, elements, components, etc. to perform a particular function when they are in an operational state (e.g., connected to a system or otherwise deployed, powered on, receiving input, and / or generating output), as well as embodiments when circuits, structures, elements, components, etc. are in a non-operational state (e.g., not connected to a system or otherwise deployed, not powered on, not receiving input, and / or not generating output) or in a partially operational state.

[0029] Figure 1 schematically shows a power converter 100 according to an exemplary embodiment of the present disclosure. In particular, Figure 1 schematically shows a power converter 100 comprising a first terminal 100-1 (or first power input terminal), a second terminal 100-2 (or second power input terminal), and a third terminal 100-3 (or DC power output terminal). The first terminal 100-1 and the second terminal 100-2 are configured to receive AC power supplied from an AC power supply 10. The power converter 100 is configured to convert the input AC power into DC power to be applied to a DC power supply load circuit 20 (or load circuit 20). Specifically, the power converter 100 converts the input AC power into a regulated DC voltage V that is output to the third terminal 100-3 (DC power output terminal). DC It is configured to convert to

[0030] In some embodiments, the AC power supply 10 includes a utility power supply (e.g., a commercial AC power supply) that provides an AC voltage waveform having a frequency of 60 Hz and a voltage of 120 VRMS (a peak voltage of approximately 170 V). For example, as schematically shown in Figure 1, in some embodiments, a first terminal 100-1 is coupled to the line-hot phase (L) of the AC power supply 10, and a second terminal 100-2 is coupled to the neutral phase (N) of the AC power supply 10. In other embodiments, the AC power supply 10 can be another AC power supply at a different voltage level and / or frequency. The load circuit 20 comprises any type of circuit architecture that utilizes the DC power generated by the power converter 100 to operate the DC power supply circuit and components. For example, in some embodiments, the load circuit 20 includes control circuits for intelligent electrical devices such as intelligent solid-state circuit breakers, intelligent optical switch devices, intelligent outlet devices, and intelligent circuit breaker devices.

[0031] The power converter 100 comprises a first solid-state switch 101, a second solid-state switch 102, a first diode D1, a second diode D2, a resistor R1, a first capacitor C1, a second capacitor C2 (alternatively a storage capacitor), a Zener diode Z1, and an intelligent refresh control system 110. The intelligent refresh control system 110 comprises a first comparator 111, a second comparator 112, a latch circuit 113, and a voltage sensing circuit 114. In some embodiments, the voltage sensing circuit 114 comprises a fixed voltage divider circuit with a fixed voltage division ratio. In other embodiments, as schematically shown in Figure 1, the voltage sensing circuit 114 comprises a programmable voltage divider circuit (electronic / digital potentiometer) with a user-programmable voltage division ratio. The voltage sensing circuit 114 measures the DC voltage V on node N4 (based on the voltage division ratio). DC The sense voltage V on node N5 is proportional to the magnitude of the value. SENSE It is configured to output a DC voltage V. In summary, the second solid-state switch 102, the first diode D1 and the second diode D2, the Zener diode Z1, the resistor R1, the first capacitor C1, and the intelligent refresh control system 110 collectively control the operation of the first solid-state switch 101, thereby supplying a DC voltage V to the output node (node ​​N4) of the power converter 100. DC The current flow (I) charges the storage capacitor C2 to generate the current. Charge It comprises a control system (or control circuit) configured to control (as denoted by), the details of which will be described in more detail below.

[0032] In some embodiments, the first solid-state switch 101 and the second solid-state switch 102 each include a metal-oxide-semiconductor field-effect transistor (MOSFET) device. In some embodiments, the first solid-state switch 101 and the second solid-state switch 102 are N-type MOSFET devices, particularly high-voltage N-type MOSFET devices. The first solid-state switch 101 and the second solid-state switch 102 each include a source terminal (S), a drain terminal (D), a gate terminal (G), and a body terminal, the source terminal (S) and the body terminal being commonly coupled. The first solid-state switch 101 includes an intrinsic body diode 101-1 representing a PN junction between a P-type substrate body and the N-doped drain region of the N-type MOSFET device. Similarly, the second solid-state switch 102 includes an intrinsic body diode 102-1 representing a PN junction between a P-type substrate body and the N-doped drain region of the N-type MOSFET device. By connecting (short-circuiting) the body terminals (e.g., P-type substrate) to the source terminals (S), the intrinsic body diodes 101-1 and 102-1 are maintained in a reverse-biased state when the first solid-state switch 101 and the second solid-state switch 102 are activated (e.g., turned on, in the "ON" state or activated state). In addition, the substrate-specific body-source diodes are short-circuited by the common connection between the source terminals (S) and the body terminals, so they are not shown (or, in other embodiments, the N+ source region and the P-doped substrate body junction are short-circuited through source metallization).

[0033] As schematically illustrated in Figure 1, the first capacitor C1 and Zener diode Z1 are coupled in parallel between nodes N1 and N2. The first diode D1 and resistor R1 are coupled in parallel between nodes N1 and N3. The second diode D2 is coupled between nodes N2 and N4. Furthermore, the gate terminal (G) and source terminal (S) of the first solid-state switch 101 are coupled to nodes N1 and N2, respectively, while the drain terminal (D) of the first solid-state switch 101 is coupled to the first terminal 100-1. As will be explained in detail below, the first capacitor C1 and Zener diode Z1 use the current drawn from the AC power supply 10 to apply a regulated voltage (e.g., regulated gate voltage V) to node N1. G A self-bias driver circuit configured to generate a regulated voltage on node N1 includes a gate voltage used to drive the first solid-state switch 101. More specifically, the first capacitor C1 and Zener diode Z1 drive the first solid-state switch 101 into an active state using a regulated gate-source voltage V across nodes N1 and N2. GS A self-biased driver circuit configured to generate [the specified value] is implemented collectively.

[0034] Furthermore, the gate terminal (G) of the second solid-state switch 102 is coupled to the output of the intelligent refresh control system 110, the drain terminal (D) of the second solid-state switch 102 is coupled to node N3, and the source terminal (S) of the second solid-state switch 102 is coupled to the second terminal 100-2. The intelligent refresh control system 110 is configured to generate a control signal applied to the gate terminal (G) of the second solid-state switch 102 in order to control the activation (turn-on) and deactivation (turn-off) of the second solid-state switch 102. When the second solid-state switch 102 is deactivated, the first solid-state switch 101 charges a current (I Charge A current flows through the AC power supply 102, which is activated to allow charging of the second capacitor C2 during a positive half-cycle of AC power from the AC power supply 10. Meanwhile, when the second solid-state switch 102 is activated, the first solid-state switch 101 is deactivated. As will be described in more detail below, the intelligent refresh control system 110 includes logic for implementing a refresh control protocol to control the operation of the first solid-state switch 101 and the second solid-state switch 102 in order to charge the storage capacitor C2 in an efficient manner across different load conditions.

[0035] In some embodiments, the first comparator 111 and the second comparator 112 each comprise an operational amplifier configured to operate as a voltage comparator. In some embodiments, the latch circuit 113 comprises a set-reset (SR) latch circuit including a first input port (set S input port), a second input port (reset R input port), and an output port (Q output port). The Q output port is coupled to the gate terminal (G) of the second solid state switch 102. The first comparator 111 includes (i) a non-inverting (+) input terminal coupled to a sense node (denoted as N5), (ii) an inverting (−) input terminal coupled to a first threshold voltage node (denoted as N6), and (iii) an output terminal coupled to the set S input port of the latch circuit 113. The second comparator 112 includes (i) a non-inverting (+) input terminal coupled to a second threshold voltage node (denoted as N7), (ii) an inverting (−) input terminal coupled to the sense node N5, and (iii) an output terminal coupled to the reset R input port of the latch circuit 113.

[0036] The voltage sensing circuit 114 comprises a voltage divider circuit configured to generate a sense voltage (denoted as V SENSE as described above) at the sense node N5. As described above, the sense voltage V SENSE is a voltage proportional to the DC voltage V DC across the storage capacitor C2 at the output node N4 of the power converter 100 based on the voltage division ratio of the voltage divider circuit of the voltage sensing circuit 114. In some embodiments, as described above, the voltage sensing circuit 114 comprises a programmable voltage divider circuit that enables the voltage division ratio to be adjusted and then, for a given application, enables adjustment of the correspondence between the sense voltage V SENSE of the power converter 100 and the maximum output voltage V DC as desired. In other embodiments, the voltage sensing circuit 114 comprises a fixed voltage divider circuit that provides a fixed voltage division ratio.

[0037] As schematically illustrated in FIG. 1, a first threshold voltage (denoted as DIS_REF) is applied to a threshold voltage node N6 of an inverting (−) input terminal of a first comparator 111. The first comparator 111 compares a sense voltage V SENSE at (node N5) with the first threshold voltage DIS_REF at (node N6) and is configured to generate an output voltage V OUT1 based on the voltage comparison. More specifically, in the exemplary embodiment of FIG. 1, the first comparator 111 includes a non-inverting comparator topology, and the first comparator 111 outputs a control voltage V SENSE at a logic “1” voltage level when the sense voltage V OUT1 is greater than the first threshold voltage DIS_REF (i.e., when V SENSE >DIS_REF, V OUT1 =logic “1”). On the other hand, the first comparator 111 outputs a control voltage V SENSE at a logic “0” voltage level when the sense voltage V OUT1 is less than the first threshold voltage DIS_REF (i.e., when V SENSE <DIS_REF, V OUT1 =logic “0”).

[0038] Furthermore, a second threshold voltage (denoted as EN_REF) is applied to a threshold voltage node N7 of a non-inverting (+) input terminal of a second comparator 112. The second comparator 112 compares a sense voltage V SENSE at (node N5) with the second threshold voltage EN_REF at (node N7) and is configured to generate an output voltage V OUT2 based on the voltage comparison. In the exemplary embodiment of FIG. 1, the second comparator 112 includes an inverting comparator topology, and the second comparator 112 outputs a control voltage V SENSE at a logic “1” voltage level when the sense voltage V OUT2 is less than the second threshold voltage EN_REF (i.e., when V SENSE <EN_REF, V OUT2 =logic “1”). On the other hand, the second comparator 112 outputs a control voltage V SENSE at a logic “0” voltage level when the sense voltage V OUT2Output at a logic "0" voltage level (i.e., V SENSE >In the case of EN_REF, V OUT2 (Logical "0").

[0039] Output V of the first comparator 111 OUT1 This controls the set S input of the latch circuit 113 and the output V of the second comparator 112. OUT2 This controls the reset R input of the latch circuit 113. The Q output of the latch circuit 113 controls the operation of the second solid-state switch 102 with a control voltage V CON This includes the following truth table, which shows the operation of the latch circuit 113. [Table 1] Q output (V) of latch circuit 113 CON When the first solid-state switch 101 is at the logic level "0" ("reset" state), the second solid-state switch 102 is deactivated (turned off), which allows the first solid-state switch 101 to be activated (turned on). Meanwhile, the Q output (V) of the latch circuit 113 CON When the first solid-state switch 101 is in the logical "1" level ("set" state), the second solid-state switch 102 is activated, which deactivates the first solid-state switch 101.

[0040] Desired maximum DC voltage (V) across storage capacitor C2 DC_MAX (as indicated by) (which is user-programmable for a given application), the first comparator 111 determines when the storage capacitor C2 is at the maximum DC voltage V DC_MAX When charged, the latch circuit 113 is configured to "set" (i.e., the Q output is set to logic "1" level), which activates the second solid-state switch 102 as described above, and then deactivates the first solid-state switch 101. The voltage across the storage capacitor C2 is V DC When it decreases (the charge stored in the storage capacitor C2 decreases, the load current I to the DC power supply load circuit 20 decreases) LOADAs a result of the discharge over time due to the flow, the voltage V of the storage capacitor C2 DC However, the minimum DC voltage (V) that can be user-programmed for a given application is DC_MIN When the voltage of the storage capacitor C2 decreases to (as indicated), the refresh cycle is initiated by the intelligent refresh control system 110. In particular, the voltage of the storage capacitor C2 V DC However, V DC_MIN When it decreases to this level, the second comparator 112 "resets" the latch circuit 113 (i.e., the Q output is set to the logic "0" level), which deactivates the second solid-state switch 102 as described above, and then the first solid-state switch 101 self-generates V GS This allows the capacitor to be activated via voltage, thereby recharging the storage capacitor C2 during a positive half-cycle of the input AC power.

[0041] It should be noted that under heavy load conditions where the voltage of the storage capacitor C2 discharges relatively quickly, a refresh operation can be triggered by the intelligent refresh control system 110 to recharge the storage capacitor C2, and this can occur during every positive half-cycle of the input AC power. On the other hand, under light load conditions where the voltage of the storage capacitor C2 discharges relatively slowly, the voltage of the storage capacitor C2 V DC (by the intelligent refresh control system 110) V DC_MIN The refresh operation does not need to be triggered by the intelligent refresh control system 110 over two or more AC power cycles until it is determined that the load has decreased to a certain level. As a result, the controlled refresh methodology implemented by the intelligent refresh control system 110 helps to improve the overall efficiency of the power converter 100 over various load conditions.

[0042] More specifically, the power converter 100 controls the voltage V across the storage capacitor C2. DC The minimum DC voltage is V DC_MINThe storage capacitor C2 is configured to charge during a given positive half-cycle of AC power applied from the AC power supply 10 to the first terminal 100-1 and the second terminal 100-2 when it decreases to (or below) a certain level. During the positive half-cycle of the input AC power, the second diode D2 is forward-biased, which charges the charging current I when the first solid-state switch 101 is activated. Charge This allows current to flow and charge the storage capacitor C2. On the other hand, during the negative half-cycle of the input AC power, the second diode D2 is reverse-biased, which prevents the storage capacitor C2 from discharging due to the negative phase of the input AC power applied to the first terminal 100-1 and the second terminal 100-2. In particular, in the absence of the second diode D2, the storage capacitor C2 begins to discharge during the negative half-cycle of the input AC power as a result of the current flow from node N4 to the first terminal 100-1 through the forward-bias inherent body diode 101-1 of the first solid-state switch 101.

[0043] As described above, the first capacitor C1 and Zener diode Z1 are configured to implement a self-bias driver circuit that uses the current drawn from the AC power supply 10 to generate a regulated voltage at node N1, and the regulated voltage at node N1 (e.g., V across nodes N1 and N2) GS ) is used to drive the first solid-state switch 101. In particular, during the negative half-cycle of the input AC power, current flows from the second terminal 100-2 to the first terminal 100-1 through an electrical path including the forward bias body diode 102-1 of the second solid-state switch 102, resistor R1, the first capacitor C1, and the forward bias body diode 101-1 of the first solid-state switch 101. This current flow is due to the capacitor voltage being overriding the Zener voltage (V) of the Zener diode Z1. Z Increase the voltage across the first capacitor C1 until it reaches the Zener voltage (e.g., V). Z(equal to or greater than 10V) provides an adjusted gate-source voltage (V GS ) across nodes N1 and N2 to drive the first solid-state switch 101 during the next positive half-cycle of the input AC signal, thereby, if necessary, charging the storage capacitor C2 to the maximum DC voltage V DC_MAX . In this exemplary configuration, the Zener diode Z1 serves to clamp V Z to drive the first solid-state switch 101 to the Zener voltage V GS of the Zener diode Z1.

[0044] At the start (or at some point during) a given positive half-cycle of the input AC power, if the voltage V DC of the storage capacitor C2 is less than the minimum DC voltage V DC_MIN , the first solid-state switch 101 is placed in an activated state to allow the charging current I Charge to flow and charge the storage capacitor C2 to the maximum DC voltage V DC_MAX . In particular, if the voltage V DC of the storage capacitor C2 is less than the minimum DC voltage V DC_MIN , the sense voltage V SENSE at node N5 is less than both the first reference voltage DIS_REF (applied to the first comparator 111) and the second reference voltage EN_REF (applied to the second comparator 112), that is, V SENSE < DIS_REF and V SENSE < EN_REF. In this case, the output V OUT1 of the first comparator 111 goes to the logical "0" level (S = 0), and the output V OUT2 of the second comparator 112 goes to the logical "1" level (R = 1), which causes the Q output (V CON ) of the latch circuit 113 to be in a reset state (Q = 0). The reset state (Q = 0) of the latch circuit 113 deactivates the second solid-state switch 102, which allows the first solid-state switch 101 to be activated and the adjusted V GS voltage across nodes N1 and N2 (e.g., the Zener voltage VZ ) enables it to be driven by, in which case the charging current I Charge However, current flows to charge the storage capacitor C2.

[0045] During a given positive half-cycle of input AC power, the voltage across the storage capacitor C2 is V DC However, V SENSE When it increases to an intermediate level that is less than DIS_REF but greater than EN_REF, the output V of the second comparator 112 OUT2 The signal transitions to the logic "0" level (R=0), while the output V of the first comparator 111 OUT1 It remains at the logic "0" level (S=0). In this case, V (at the reset R input of latch circuit 113) OUT2 The transition to logic level "0" does not cause a change in the state of the latch circuit 113, so the Q output of the latch circuit 113 remains unchanged (NC) and stays at logic level "0". In this way, the second solid-state switch 102 remains in the deactivated state, and the first solid-state switch 101 remains in the activated state, raising the storage capacitor C2 to its maximum voltage. DC It continues to charge.

[0046] At some point during a given positive half-cycle of input AC power, the voltage across the storage capacitor C2 is V DC The maximum DC voltage V DC_MAX When this is reached, the first solid-state switch 101 is deactivated, and the charging current I to the storage capacitor C2 is increased. Charge This interrupts and terminates the flow. In particular, the voltage V across the storage capacitor C2 DC However, the maximum DC voltage V DC_MAX When it reaches this point, the sense voltage V of node N5 SENSE This is greater than both the first and second reference voltages DIS_REF, but greater than EN_REF applied to the first comparator 111 and the second comparator 112, respectively, i.e., V SENSE >DIS_REF and V SENSE >EN_REF. In this case, the output V of the first comparator 111. OUT1transitions to the logical "1" level (S = 1), and the output V of the second comparator 112 OUT2 remains at the logical "0" level (R = 0), which causes the Q output (V CON ) of the latch circuit 113 to transition to the set state (Q = 1). The set state (Q = 1) of the latch circuit 113 causes the second solid-state switch 102 to be placed in the activated state, and then causes the first solid-state switch 101 to be placed in the deactivated state.

[0047] Specifically, when the second solid-state switch 102 is activated, the node N1 is pulled down near the substantially grounded (neutral) potential. In this case, the voltage of the node N1 is below the threshold voltage V T of the first solid-state switch 101, deactivating the first solid-state switch 101. In this case, the deactivation of the first solid-state switch 101 terminates the charging current I Charge flowing to the storage capacitor C2, and then prevents further charging to a voltage greater than the maximum DC voltage V DC_MAX of the storage capacitor C2.

[0048] When the storage capacitor C2 is charged to the maximum DC voltage V DC_MAX and the charging current ends, as a result of the discharge of the storage capacitor C2 by the flow of the load current I LOAD when DC power is supplied to the load circuit 20 connected thereto, the voltage V DC of the storage capacitor C2 begins to decrease. The rate at which the storage capacitor C2 discharges varies depending on the load conditions. In this regard, when the storage capacitor C2 is charged to the maximum DC voltage V DC_MAX in a given positive half-cycle of the input AC power, under specific load conditions, the second capacitor C2 discharges during the remainder of the given positive half-cycle and throughout the subsequent negative half-cycle.

[0049] The voltage V DC of the storage capacitor C2 becomes V SENSEWhen it decreases to an intermediate level that is less than DIS_REF but greater than EN_REF, the output V of the first comparator 111 OUT1 The signal transitions to the logic "0" level (S=0), while the output V of the second comparator 112 OUT2 This remains at the logical "0" level (R=0). In this case, V OUT1 The transition to the logic "0" level (which is applied to the set S input of the latch circuit 113) does not cause a change in the state of the latch circuit 113, therefore the Q output (V) of the latch circuit 113 CON ) remains unchanged (NC) and stays at logic "1". The voltage across storage capacitor C2 is V DC However, the minimum DC voltage level V DC_MIN When it decreases to (where V SENSE (This value is smaller than DIS_REF and also smaller than EN_REF), and the output V of the second comparator 112. OUT2 The signal transitions to logic level "1" (R=1), while the output V of the first comparator 111 OUT1 It remains at the logic "0" level (S=0). In this case, the latch circuit 113 is placed in the reset state, and in this case, the Q output (V) of the latch circuit 113 CON ) transitions to logic "0" level (Q=0). If the Q output of the latch circuit 113 transitions to logic "0" level during a negative half-cycle of input AC power, the first solid-state switch 101 remains inactive (even though the second solid-state switch 102 is inactive) until at least the input AC power transitions to the next positive half-cycle, in which case the first solid-state switch 101 is activated and the charging current I Charge This allows current to flow, enabling the storage capacitor C2 to be charged during the positive half-cycle of the input AC power.

[0050] Next, the voltage across the storage capacitor C2 becomes V as a result of being charged during the positive half-cycle of the input AC power. DC The maximum DC voltage level V DC_MAX When it increases, the voltage at node N5 V SENSEThese values ​​become greater than the first threshold voltage DIS_REF and the second threshold voltage EN_REF of the first comparator 111 and the second comparator 112, respectively. As a result, the output V of the first comparator 111 becomes greater than the first threshold voltage DIS_REF and the second threshold voltage EN_REF of the first comparator 111 and the second comparator 112, respectively. OUT1 The signal transitions to logic level "1" (S=1), and the output V of the second comparator 112 is... OUT2 This results in a logic "0" level (R=0), which causes the latch circuit 113 to be blocked by the Q output (V) of the latch circuit 113. CON This causes the switch to be placed in a set state that transitions to logic level "1" (Q=1). As a result, the second solid-state switch 102 is activated, which deactivates the first solid-state switch 101 and charges the storage capacitor C2 with a current I Charge End the process.

[0051] As described above, the power converter 100 implements an intelligent refresh mechanism for efficiently charging the storage capacitor C2 for different load conditions. It disables and enables the charging of the storage capacitor C2 by setting maximum and minimum DC voltage values ​​(V DC_MAX and V DC_MIN ) is a user-programmable value, which is, for example, a given sense voltage V SENSE The parameters (which can be fixed or programmable as described above) can be adjusted by changing the first threshold voltage DIS_REF and the second threshold voltage EN_REF. The intelligent refresh control system 110 controls the voltage V across the storage capacitor C2. DC However, V DC_MIN When the input AC power falls below VDC, the storage capacitor C2 stores power during the positive half-cycle of the input AC power. _MAX It is configured to initiate a refresh cycle to recharge it. Meanwhile, during a positive half-cycle of input AC power, the voltage across the storage capacitor C2 V DC However, V DC_MAX It is below V DC_MIN When the voltage does not fall below this level, the intelligent refresh control system 110 delays the start of the next refresh cycle, and the voltage of the storage capacitor C2 V DC ga V DC_MINWait until it decreases to [a certain value].

[0052] Furthermore, as described above, the storage capacitor C2 is not charged during the negative half-cycle of the input AC power, and the diode D2 prevents the flow of current from node N4 to node N2 during the negative half-cycle of the input AC power, thereby preventing the discharge of the storage capacitor C2. Instead, during the negative half-cycle of the input AC power, node N1 receives a regulated voltage (i.e., the Zener voltage V of Z1) via the current flowing from the second terminal 100-2 through the intrinsic diode 102-1 of the second solid-state switch 102, through the resistor R1, and into the clamp circuit including capacitor C1 and Zener diode Z1, as considered above. Z ) is pre-charged. In this manner, the first solid-state switch 101 receives the regulated voltage V generated across nodes N1 and N2. GS This allows the system to be put into an activated state, thereby enabling the intelligent refresh control system 110 to activate when it determines it is necessary (for example, when the voltage across the storage capacitor C2 is turned V). DC ga V DC_MIN If it reaches the charging current I Charge This allows the input AC power to flow through and charge the storage capacitor C2 during the next positive half-cycle. In this regard, as mentioned above, the voltage across the storage capacitor C2 V DC Under heavy load conditions where the capacitor discharges relatively quickly, refresh operations can occur during each positive half-cycle of the input AC power. Meanwhile, the voltage across the storage capacitor C2 V DC Under light load conditions where the discharge is relatively slow, the refresh operation may not occur between two or more AC power cycles. As a result, the controlled refresh methodology improves the overall efficiency of the power converter 100, regardless of load conditions such as those shown in 2A to 2D.

[0053] In particular, Figures 2A, 2B, 2C, and 2D are timing diagrams illustrating simulated waveforms showing exemplary operating modes of a power converter according to exemplary embodiments of the present disclosure. For illustrative purposes, Figures 2A, 2B, 2C, and 2D are described in the context of exemplary operating modes of the exemplary power converter 100 of Figure 1. In particular, Figure 2A shows an exemplary AC voltage waveform 210 (e.g., input AC power) applied to the power converter 100, and an exemplary DC voltage waveform 212 (V) generated by the power converter 100 under relatively high DC load conditions. DC Figure 2B shows a timing diagram 200 illustrating the same exemplary AC voltage waveform 210 as in Figure 2A, as well as an exemplary current waveform 214 representing the transient current (or capacitor refresh current) generated through the first solid-state switch 101 in Figure 1.

[0054] As shown in Figure 2A, an example DC voltage waveform 212(V DC ) is approximately 60V (for example, V DC_MAX ) and approximately 30V (for example, V DC_MIN The voltage waveform includes a triangular shape that transitions between ) and ). Figures 2A and 2B show exemplary modes of operation of the power converter 100 under heavy DC load conditions, in which refresh operation is initiated at the start of each positive half-cycle of the AC voltage waveform 210. As shown by the current waveform 214 in Figure 2B, the charging current is generated for a short duration at the start of each positive half-cycle of the AC voltage waveform 210, up to a maximum of V DC (For example, 60V V DC_MAX Recharge the storage capacitor C2 until it reaches )

[0055] Next, Figure 2C shows an exemplary AC voltage waveform 220 (e.g., input AC power) applied to the power converter 100, and an exemplary DC voltage waveform 222 (V) generated by the power converter 100 under relatively low DC load conditions. DCFigure 2D illustrates a timing diagram 203 showing the same exemplary AC voltage waveform 220 in Figure 2C, as well as a corresponding timing diagram 204 showing an exemplary current waveform 224 representing the transient current (or capacitor refresh current) generated through the first solid-state switch 101 in Figure 1 under relatively low DC load conditions.

[0056] As shown in Figure 2C, an example DC voltage waveform 212(V DC ) is approximately 60V (for example, V DC_MAX ) and approximately 30V (for example, V DC_MIN The voltage waveform includes a triangular shape that transitions between ) and ). Figures 2C and 2D illustrate exemplary modes of operation of the power converter 100 under relatively light DC load conditions, where refresh operations are initiated after multiple positive half-cycles of the AC voltage waveform 220. For example, Figures 2C and 2D illustrate an exemplary embodiment in which a first refresh operation R1 is initiated at the start of a positive half-cycle of the AC voltage waveform 220 (at time t1), which is followed by the initiation of a second refresh operation R2 at the start of a positive half-cycle of the AC voltage waveform 220 (at time t2), and the second refresh operation R2 is initiated at the start of the eleventh positive half-cycle of the AC voltage waveform 220 after the first refresh operation R1. As shown in Figure 2D, a charging current is generated for a short duration (as indicated by current spikes) in each positive half-cycle of the AC voltage waveform 220, and refresh operations R1 and R2 are initiated at a maximum of V DC The system is initiated to recharge the storage capacitor C2 to a voltage (for example, approximately 60V). In this exemplary embodiment, as described above, the minimum DC voltage V to trigger the refresh operation is DC_MIN The setting is that, under relatively light DC load conditions, the adjusted DC voltage V across the storage capacitor C2 from one positive half-cycle to the next. DC The maximum DC voltage V DC_MAX If the value falls slightly below this threshold, the refresh operation is prevented from starting every positive half-cycle of the AC voltage waveform 220.

[0057] Figure 3 shows a flowchart of Method 300 for converting AC power to DC power according to an exemplary embodiment of the present disclosure. In some embodiments, Figure 3 shows an exemplary mode of operation of the power converter 100 of Figure 1 for converting AC power to DC power stored in a storage capacitor C2, according to an exemplary embodiment of the present disclosure. Method 300 includes monitoring the voltage level across the storage capacitor C2 (block 301). For example, in some embodiments, as discussed above, the intelligent refresh control system 110 monitors the DC voltage V across the storage capacitor C2 (based on a given voltage division ratio). DC The sense voltage V is proportional to the magnitude of the voltage. SENSE By generating and outputting the voltage V across the storage capacitor C2, DC A voltage sensing circuit 114 is implemented to continuously monitor the voltage.

[0058] The power converter 100 outputs the voltage V across the storage capacitor C2. DC The maximum DC voltage V DC_MAX When it is determined that the voltage does not fall below (a negative determination in block 302), the refresh operation is not initiated, and the control system continues to monitor the voltage level across the storage capacitor C2 (block 301). DC The maximum DC voltage V DC_MAX It is below (positive judgment in block 302), but the minimum DC voltage V DC_MIN If it is determined that the voltage does not fall below a certain level (negative determination in block 303), the refresh operation is not initiated, and the control system continues to monitor the voltage level across the storage capacitor C2 (block 301).

[0059] On the other hand, the power converter 100 controls the voltage V across the storage capacitor C2. DC The maximum DC voltage V DC_MAX It is below (positive determination in block 302), and the minimum voltage V DC_MINIf the value falls below a certain level (positive determination in block 303) but the AC power is not in a positive half-cycle (negative determination in block 304), the refresh operation is not initiated. The control system waits until the next positive half-cycle of AC power (block 305) before initiating the refresh operation. When the next positive half-cycle of AC power is reached (positive determination in block 304), the power converter 100 initiates the refresh operation, allowing a charging current to flow through the storage capacitor C2 during the positive half-cycle of AC power, thereby raising the storage capacitor C2 to the maximum voltage level V DC_MAX The capacitor is charged (block 306). Furthermore, as described above, the power converter 100 prevents the charging current from flowing to the storage capacitor C2 during the negative half-cycle of the AC power, regardless of the monitored voltage level across the storage capacitor C2.

[0060] Figure 4 schematically shows a power converter according to another exemplary embodiment of the present disclosure. In particular, Figure 4 schematically shows a power converter 400 comprising a first terminal 400-1 (or first power input terminal), a second terminal 400-2 (or second power input terminal), and a third terminal 400-3 (or DC power output terminal). The first terminal 400-1 and the second terminal 400-2 are configured to receive AC power supplied from the AC power supply 10. The power converter 400 is configured to convert the input AC power into DC power to be applied to the DC power supply load circuit 20 (or load circuit 20). Specifically, the power converter 400 converts the input AC power into a regulated DC voltage V that is output to the third terminal 400-3 (DC power output terminal). DC It is configured to convert to

[0061] In some embodiments, the AC power supply 10 includes a utility power supply (e.g., AC commercial power) that provides an AC voltage waveform having a frequency of 60 Hz and a voltage of 120 VRMS (peak voltage of approximately 170 V). For example, as schematically shown in Figure 4, in some embodiments, a first terminal 400-1 is coupled to the line-hot phase (L) of the AC power supply 10, and a second terminal 100-2 is coupled to the neutral phase (N) of the AC power supply 10. In other embodiments, the AC power supply 10 can be another AC power supply at a different voltage level and / or frequency. The load circuit 20 comprises any type of circuit architecture that utilizes the DC power generated by the power converter 400 to operate the DC power supply circuit and components. For example, in some embodiments, the load circuit 20 comprises a control circuit for intelligent electrical devices such as an intelligent solid-state circuit breaker, an intelligent optical switch device, an intelligent outlet device, or an intelligent circuit breaker device.

[0062] The power converter 400 comprises a solid-state switch 401, a first diode D1, a second diode D2, a third diode D3, a resistor R1, a first capacitor C1, a second capacitor C2 (alternatively, a storage capacitor), and a Zener diode Z1. Collectively, the solid-state switch 401, the first, second, and third diodes D1, D2, and D3, the Zener diode Z1, the resistor R1, and the first capacitor C1 supply a DC voltage V to the output node (node ​​N4) of the power converter 400. DC A current (I) charges the storage capacitor C2 to generate the current (I Charge It includes a self-regulating power management circuit configured to control the flow (as indicated by ).

[0063] In contrast to the exemplary power converter 100 in Figure 1, which implements a feedback architecture (via an intelligent refresh control system 110 and a second solid-state switch 102) to control the activation and deactivation of the first solid-state switch 101, thereby controlling the charging of the storage capacitor C2, the activation and deactivation of the solid-state switch 401 of the power converter 400 is not controlled by feedback. Instead, a self-bias driver circuit implemented by a first capacitor C1 and a Zener diode Z1 uses the current drawn from the AC power supply 10 during each negative half-cycle of the input AC power to drive the solid-state switch 401 at the start of each positive half-cycle of the input AC power, and uses a gate-source voltage V adjusted across nodes N1 and N2. GS (ii) The input AC power is adjusted at some point during the beginning of each positive half-cycle. GS The solid-state switch 401 is deactivated as a result of dissipating the fumes, before the input AC power reaches its peak level (for example, before the input AC voltage waveform of the AC power reaches a peak voltage of 170V). In this example, the storage capacitor C2 is configured to dissipate the fumes below the peak voltage of the input AC power (for example, 170V). DC It will be charged up to a voltage level (for example, 70V).

[0064] More specifically, during a given negative half-cycle of input AC power, current flows from the second terminal 400-2 to the first terminal 400-1 through an electrical path including a third diode D3 (which is forward-biased), a resistor R1, a first capacitor C1, and the forward-biased intrinsic body diode 401-1 of the solid-state switch 401. This current flow is balanced by the capacitor voltage and the Zener voltage V of the Zener diode Z1. Z Increase the voltage across the first capacitor C1 until it reaches the Zener voltage V. Z This is the adjusted V across node N1 and node N2. GSThis provides the V to drive the solid-state switch 401 during the next positive half-cycle of the input AC signal, thereby charging the storage capacitor C2. In this exemplary configuration, the Zener diode Z1 provides the V to drive the solid-state switch 401. GS The magnitude of the Zener voltage V of the Zener diode Z1 Z It serves to clamp it.

[0065] At the start of a given positive half-cycle of input AC power, the solid-state switch 401 is in the activated state, and the regulated V across nodes N1 and N2 GS It is driven by the charging current I. Charge The current flows from the first terminal 400-1 through the solid-state switch 401 and the second diode D2 (which is forward-biased) through the storage capacitor C2 at a given DC level V DC Charges the capacitor. Following a transition of the input AC power to a given positive half-cycle, the first capacitor C1 charges across nodes N1 and N2. GS The charge current I is initiated and continues to discharge during a given positive half-cycle start until its magnitude falls below the threshold voltage of the solid-state switch 401, which turns off (deactivates) the solid-state switch 401. Deactivating the solid-state switch 401 causes the charge current I to the storage capacitor C2 to begin. Charge This terminates the flow and thereby ends the charging process.

[0066] In this exemplary configuration, the solid-state switch 401 controls the voltage (VV across nodes N1 and N2) between the beginning of each positive half-cycle of the input AC power. GSThe solid-state switch 401 remains activated for a certain period of time (while the voltage remains above the threshold voltage), allowing the storage capacitor C2 to be charged during the beginning of each positive half-cycle of the input AC power. In the exemplary configuration of the power converter 400 in Figure 4, the first capacitor C1 is designed to have a relatively small capacitance so that the first capacitor C1 discharges relatively quickly during the beginning of the positive half-cycle of the AC input power, thereby allowing the voltage V across nodes N1 and N2 to be charged. GS This turns off the solid-state switch 401 and increases the charging current I to the storage capacitor C2. Charge It rapidly reduces the flow to a level that ends it.

[0067] More specifically, in an exemplary embodiment, the first capacitor C1 is designed to have a relatively small capacitance, which then results in a relatively high discharge rate of the first capacitor C1 so that the solid-state switch 401 is turned off at some point during the beginning of each positive half-cycle of the AC power, for example, before reaching the peak voltage. In this exemplary configuration, the capacitance of the first capacitor C1 can be selected to achieve a predetermined discharge rate, thereby, when the input voltage of the input AC power reaches a target voltage level such as 40V, 50V, 60V, 70V, before reaching the peak voltage level (e.g., 170V), the voltage V GS When the voltage drops below the threshold voltage of the solid-state switch 401, the maximum voltage V that charges the storage capacitor C2 is reached. DC Restrict.

[0068] It should be understood that the exemplary power converters 100 and 400 in Figures 1 and 4 can be implemented in a variety of applications. For example, power converters 100 and 400 can be used to generate DC power to control circuits of intelligent electrical devices such as intelligent solid-state circuit breakers, intelligent solid-state optical switch devices (e.g., intelligent dimmer switches), and intelligent circuit breaker devices. For example, Figure 5 schematically shows an intelligent electrical device 500 that implements a power converter according to an exemplary embodiment of the present disclosure. The intelligent electrical device 500 is configured to control AC power supplied from an AC power source 10 (e.g., AC commercial power) to an AC load 50. The intelligent electrical device 500 can be any type of intelligent electrical device configured to switchably connect / disconnect AC power to and from a given load.

[0069] As schematically shown in Figure 5, in some embodiments, the intelligent electrical device 500 comprises a first power input terminal 500-1, a second power input terminal 500-2, a first load terminal 500-3, a second load terminal 500-4, an AC switch 510, and an intelligent switch control system 520. The intelligent switch control system 520 includes various components and circuits such as a controller 521, sensor circuits 522 and 523, one or more memory devices 524, and a power converter 525. The power converter 525 is used to provide a DC supply voltage V for operating the various components 521, 522, 523, and 524 of the intelligent switch control system 520. DC To generate the DC voltage V, as discussed above, it can be implemented using either one of the exemplary power converters 100 or 400. In some embodiments, the power converter 525 may, as needed to operate the various components 521, 522, 523, and 524 of the intelligent switch control system 520, generate the DC voltage V generated by the power converter 100 or 400. DCThe intelligent electrical device 500 and the intelligent switch control system 520 further comprises a DC-DC converter circuit configured to convert the voltage to one or more DC operating voltage levels. Depending on the type of device and a given application (e.g., intelligent circuit breaker, intelligent electrical switch, etc.), the intelligent electrical device 500 and the intelligent switch control system 520 may comprise other types of mechanical and / or electrical components to perform specific functions associated with a given application. The intelligent switch control system 520 may comprise a system-on-chip (SoC) device or a system-in-package (SIP) device that integrates various components 521, 522, 523, 524, and 525 or parts thereof within a package structure.

[0070] In the exemplary embodiment shown in Figure 5, the first power input terminal 500-1 and the second power input terminal 500-2 are coupled to the line (L) phase 11 and the neutral (N) phase 12 of the AC power supply 10, respectively. The first load terminal 500-3 and the second load terminal 500-4 are configured to connect the intelligent electrical device 500 to the load hotline 51 and the load neutral line 52 connected to the AC load 50, respectively. In some embodiments, the intelligent electrical device 500 has only three terminals 500-1, 500-2, and 500-3, in which case the load neutral line 52 of the AC load 50 is directly connected to the neutral (N) phase 12 of the AC power supply 10 (for example, connected to a neutral bar in a switchboard or to a neutral line in a branch circuit, etc.).

[0071] Furthermore, as schematically illustrated in Figure 5, the AC switch 510 is connected between a first node N1 (alternatively a line hot node or license node) and a second node N2 (alternatively a load hot node or load sense node) in the electrical path between a first power input terminal 500-1 and a first load terminal 500-3. In some embodiments, the AC switch 510 comprises a bidirectional solid-state switch device comprising two solid-state switches connected in series in a common source or common drain configuration. The AC switch 510 is controlled by a switch control signal (denoted as S_Control) generated by a controller 521, which causes the AC switch 510 to be placed in one of two states: (i) an activated state (turn-on) that connects AC power to the AC load 50, or (ii) an deactivated state (turn-off) that disconnects AC power from the AC load 50.

[0072] In some embodiments, the controller 521 is implemented using at least one intelligent and programmable hardware processing device, such as a microprocessor, microcontroller, ASIC, FPGA, or CPU, which is configured to execute software routines for intelligently controlling the operation of the AC switch 510 to perform various functions, depending on the device type of the intelligent electrical device 500. In some embodiments, one or more memory devices 524 include non-volatile memory (NVM), such as volatile random access memory (RAM) and flash memory, for storing calibration data, operation data, and executable code for performing various intelligent operations of the intelligent electrical device 500, depending on the device type (e.g., intelligent circuit breaker, intelligent dimming switch, etc.). For example, in some embodiments where the intelligent electrical device 500 is an intelligent electro-optical switch with dimming capability, the controller 521 may perform a PWM (pulse width modulation) process to generate a pulse width modulation switch control signal S_Control to modulate the turn-on time of the AC switch 510 during positive and negative half-cycles of input AC power, thereby modulating the amount of AC power supplied to the AC load 50.

[0073] Sensor circuit 522 includes voltage detection and / or current detection circuits for sensing line voltage and / or line current at node N1 (the line side of AC switch 510). In some embodiments, sensor circuit 522 includes voltage detection and / or current detection circuits for sensing load voltage and / or load current at node N2. The configuration and type of sensors used in sensor circuits 522 and 523 vary depending on the application. For example, for dimming applications, sensor circuit 522 may include a voltage phase detector for determining the zero crossing of the AC supply voltage waveform at node N1 and the direction of the polarity transition of the AC supply voltage waveform at node N1 (e.g., transition from a positive half-cycle to a negative half-cycle or from a negative half-cycle to a positive half-cycle of the AC supply voltage waveform). Zero crossing detection is processed by controller 521 to determine and control the timing of activation and deactivation of AC switch 510 following the detected zero voltage crossing of the AC supply voltage waveform at license node N1.

[0074] In some embodiments, for intelligent circuit breaker applications, the sensor circuit 523 includes a current sensing circuit for sensing the magnitude of the load current at node N2. In this regard, the sensor circuit 523 can be utilized by the controller 521 to detect fault conditions such as overcurrent or short circuit, and if a fault condition is detected, the controller 521 can deactivate the AC switch 510. In some embodiments, the intelligent electrical device 500 includes an intelligent solid-state circuit breaker implemented using exemplary circuit breaker architectures and techniques such as those disclosed in U.S. Patent No. 11,373,831, which is fully incorporated herein by reference by the same applicant.

[0075] The descriptions of the various embodiments of this disclosure have been presented for illustrative purposes only and are not intended to be exhaustive or to limit the embodiments disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments described. The terms used herein have been chosen to best describe the principles of the embodiments, their practical applications or technical improvements to the technology found in the market, and to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A power converter, A first solid-state switch connected to the electrical path between the first node and the second node, A storage capacitor coupled between the second node and the ground node, The system comprises a control system configured to control the charging of the storage capacitor, and the control system is Determine the voltage level across the storage capacitor, In response to determining that the voltage level across the storage capacitor is below a minimum voltage level, the first solid-state switch is activated during a given positive half-cycle of alternating current (AC) power applied to the first node, allowing current to flow from the first node to the second node and charge the storage capacitor. A power converter configured to deactivate the first solid-state switch during a given positive half-cycle of the AC power in response to the determination that the voltage level across the storage capacitor has reached a maximum voltage level.

2. The power converter according to claim 1, wherein the minimum voltage level and the maximum voltage level are programmable parameters of the control system.

3. The power converter according to claim 1, wherein the storage capacitor is configured as a DC power supply that supplies direct current (DC) power to a load connected to the second node of the power converter.

4. The power converter according to claim 1, wherein the control system is configured to keep the first solid-state switch in an inactive state for the entire duration of each negative half-cycle of the AC power.

5. The power converter according to claim 1, wherein the first solid-state switch includes a high-voltage MOSFET.

6. The power converter according to claim 1, wherein the control system comprises a driver circuit configured to generate a regulated control voltage using a current drawn from the AC power during a negative half-cycle of the AC power, and to drive the first solid-state switch during a positive half-cycle of the AC power using the regulated control voltage.

7. The control system, A voltage sensing circuit configured to generate a sense voltage proportional to the voltage level across the storage capacitor, A first comparator is configured to compare the sense voltage with a first threshold voltage and generate a first output signal based on the comparison between the sense voltage and the first threshold voltage. The system includes a second comparator configured to compare the sense voltage with a second threshold voltage and generate a second output signal based on the comparison between the sense voltage and the second threshold voltage, The power converter according to claim 1, wherein the control system is configured to activate the first solid-state switch during a given positive half-cycle of the AC power in response to the control system determining, based on the first and second output signals of the first and second comparators, that the sense voltage is less than both the first and second threshold voltages.

8. The control system, A second solid-state switch coupled to the control terminal of the first solid-state switch, The latch circuit further comprises, A first input port is connected to the output port of the first comparator and configured to receive the first output signal, A second input port is connected to the output port of the second comparator and configured to receive the second output signal, The system comprises an output port coupled to the control terminal of the second solid-state switch, The latch circuit is configured to output a control signal for controlling the activation and deactivation of the second solid-state switch based on the logic level of the first output signal from the first comparator and the logic level of the second output signal from the second comparator. Activation of the second solid-state switch deactivates the first solid-state switch. The power converter according to claim 7, wherein deactivation of the second solid-state switch allows the first solid-state switch to be activated during a positive half-cycle of the AC power.

9. The power converter according to claim 8, wherein the latch circuit includes a set-reset latch circuit.

10. The power converter according to claim 7, wherein at least one of the first threshold voltage and the second threshold voltage is programmable.

11. The voltage sensing circuit includes a voltage divider circuit coupled in parallel with the storage capacitor, The voltage divider circuit includes sense nodes connected to the input terminals of the first comparator and the input terminals of the second comparator, The power converter according to claim 7, wherein the voltage divider circuit generates the sense voltage on the sense node.

12. The power converter according to claim 11, wherein the voltage divider circuit includes a programmable voltage division ratio.

13. An intelligent electrical device comprising a power converter as described in claim 1, wherein the storage capacitor is configured as a DC power supply that supplies direct current (DC) power to the control circuit of the intelligent electrical device.

14. An intelligent solid-state circuit breaker device comprising the power converter described in claim 1.

15. An intelligent solid-state optical switch device comprising the power converter described in claim 1.

16. A power converter, The system includes a control system configured to control the charging of a storage capacitor using a current drawn from alternating current (AC) power applied to the input terminal of the power converter, in order to provide direct current (DC) power to a load coupled to the output terminal of the power converter. The control system, Monitoring the voltage level across the aforementioned storage capacitor, In response to the determination that the monitored voltage level across the storage capacitor is below the minimum voltage level, a charging current flows through the storage capacitor during a given positive half-cycle of the AC power to charge the storage capacitor to the maximum voltage level, A power converter configured to control the charging of a storage capacitor by, in response to determining that the monitored voltage level across the storage capacitor is less than the maximum voltage level and greater than the minimum voltage level, preventing a charging current from flowing to the storage capacitor during a given positive half-cycle of the AC power.

17. The power converter according to claim 16, wherein the control system is further configured to control the charging of the storage capacitor by preventing a charging current from flowing to the storage capacitor during a negative half-cycle of the AC power, regardless of the monitored voltage level across the storage capacitor.

18. An intelligent electrical device comprising a power converter as described in claim 16, wherein the DC power is used to supply power to the control circuit of the intelligent electrical device.

19. It is a method, This includes converting alternating current (AC) power into direct current (DC) power stored in a storage capacitor, and the conversion of AC power into DC power is Monitoring the voltage level across the aforementioned storage capacitor, In response to the determination that the monitored voltage level across the storage capacitor is below the minimum voltage level, a charging current flows through the storage capacitor during a given positive half-cycle of the AC power to charge the storage capacitor to the maximum voltage level, A method comprising: preventing a charging current from flowing through the storage capacitor during a given positive half-cycle of the AC power in response to determining that the monitored voltage level across the storage capacitor is less than the maximum voltage level and greater than the minimum voltage level.

20. The method according to claim 19, further comprising preventing a charging current from flowing to the storage capacitor during a negative half-cycle of the AC power, regardless of the monitored voltage level across the storage capacitor.

Images