Semiconductor devices and methods

Abstract

This disclosure relates to methods, devices, systems, and techniques for high-bandwidth memory (HBM). A typical semiconductor device includes a first layer stacked on top of each other along a first direction, a second layer, a first die between the first and second layers, and a second die. Each of the first and second dies has a conductive layer. The first and second dies are joined via the second layer. The semiconductor device further includes a first contact structure coupled to the conductive layer of the first die and a second contact structure coupled to the conductive layer of the second die. The first contact structure extends along the first direction and contacts the conductive layer of the first die without extending through the second layer. The second contact structure extends through the second layer along the first direction without extending through the second die.

Description

Technical Field

[0001] The present disclosure relates to high bandwidth memory (HBM) systems and devices and methods of manufacturing them.

Background Art

[0002] Semiconductor devices, such as memory devices, can have various structures to increase the density of memory cells and memory lines on a chip. For example, three-dimensional (3D) memory devices are attractive for their ability to increase array density by stacking more layers within the same occupied area. 3D memory devices typically include a memory array of memory cells and peripheral circuits to facilitate the operation of the memory array.

[0003] High bandwidth memory (HBM) uses stacked memory devices to enable efficient data movement and access. While using less power in a smaller form factor, HBM devices can achieve higher bandwidths. HBM devices are applied to high-performance graphics accelerators, network devices, high-performance data centers, artificial intelligence (AI) and machine learning (ML) training, and various supercomputers.

Summary of the Invention

[0004] The present disclosure describes methods, devices, systems, and technologies for high bandwidth memory (HBM).

[0005] One aspect of the present disclosure features a semiconductor device comprising: a first layer stacked on top of each other along a first direction; a second layer; a first die between the first and second layers; and a second die. Each of the first and second dies has a conductive layer. The first and second dies are joined via the second layer. The semiconductor device further includes a first contact structure coupled to the conductive layer of the first die and a second contact structure coupled to the conductive layer of the second die. The first contact structure extends along the first direction and contacts the conductive layer of the first die without extending through the second layer. The second contact structure extends through the second layer along the first direction without extending through the second die. The second contact structure contacts the conductive layer of the second die without extending through the conductive layer of the first die.

[0006] In some implementations, the semiconductor device further includes a base die. The base die, first layer, first die, second layer, and second die are stacked along a first direction. The base die and the first die are joined via the first layer.

[0007] In some implementation configurations, the first edge of the conductive layer of the first die and the first edge of the conductive layer of the second die are offset along a second direction perpendicular to the first direction.

[0008] In some implementations, the second contact structure is located along a second direction between the first end of the conductive layer of the first die and the first end of the conductive layer of the second die.

[0009] In some implementations, the first contact structure and the second contact structure are both continuous structures.

[0010] In some implementation configurations, the second layer includes at least one dielectric material and excludes the conductive bonding contact, while the first layer includes the conductive bonding contact and at least one dielectric material separating the conductive bonding contact.

[0011] In some implementation configurations, the second layer includes an upper and lower bonding layer, each containing a dielectric material and excluding conductive bonding contacts. The dielectric material of the upper bonding layer of the second layer is bonded to the dielectric material of the lower bonding layer of the second layer. The first layer includes an upper and lower bonding layer, each containing conductive bonding contacts and a dielectric material separating the conductive bonding contacts. The dielectric material of the upper bonding layer of the first layer is bonded to the dielectric material of the lower bonding layer of the first layer. The conductive bonding contacts of the upper bonding layer of the first layer are bonded to the conductive bonding contacts of the lower bonding layer of the first layer.

[0012] In some implementation configurations, the base die includes a first via extending along a first direction and coupled to a conductive bonding contact of a first layer. Each of the first and second contact structures is coupled to one of the first vias via one of the conductive bonding contacts of the first layer.

[0013] In some implementations, the semiconductor device further comprises a computing die and an interposer, where the base die and the computing die are integrated at different positions on the interposer along a second direction perpendicular to a first direction.

[0014] In some implementations, the base die includes a first via coupled to the computing die via an interposer, the first via being coupled to a first conductive terminal on the surface of the interposer, and the computing die is coupled to a second conductive terminal on the surface of the interposer, the first and second conductive terminals being coupled via conductive wires within the interposer.

[0015] In some implementations, the semiconductor device further includes a computing die and a third layer between the computing die and the base die. The computing die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along a first direction. The base die and the computing die are joined via the third layer.

[0016] In some implementations, the third layer includes a conductive bonding contact and at least one dielectric material separating the conductive bonding contact.

[0017] In some implementation configurations, the third layer includes an upper bonding layer and a lower bonding layer, each containing a conductive bonding contact and a dielectric material separating the conductive bonding contact. The dielectric material of the upper bonding layer of the third layer is bonded to the dielectric material of the lower bonding layer of the third layer. The conductive bonding contact of the upper bonding layer of the third layer is bonded to the conductive bonding contact of the lower bonding layer of the third layer.

[0018] In some implementations, the base die includes a first via coupled to the computing die. The computing die includes a second via extending along a first direction and coupled to a conductive bonding contact of a third layer. The first via is coupled to the second via via the conductive bonding contact of the third layer.

[0019] In some implementations, the semiconductor device further includes an interposer, and the interposer, computing die, third layer, base die, first layer, first die, second layer, and second die are stacked along a first direction.

[0020] In some implementation configurations, the semiconductor device further includes a first die, a second die, and a third die, the one furthest from the base die, along a first direction, and the thickness of the first die and the thickness of the second die are each smaller than the thickness of the third die along the first direction.

[0021] In some implementation configurations, the thickness of the first die and the thickness of the second die are in the range of 3 micrometers (μm) to 20 μm.

[0022] In some embodiments, the size of the cross-section of the second contact structure in the first die is larger than the size of the cross-section of the second contact structure in the second die. The cross-section of the second contact structure in the first die and the cross-section of the second contact structure in the second die are perpendicular to the first direction.

[0023] In some embodiments, the first contact structure and the second contact structure are formed by the same process.

[0024] In some embodiments, each of the first contact structure and the second contact structure has a critical dimension (CD) within the range of 0.5 μm to 10 μm.

[0025] In some embodiments, at least one of the first die or the second die includes a memory array including an array of memory cells and peripheral circuits coupled to the memory array.

[0026] In some embodiments, at least one of the first die or the second die is a dynamic random access memory (DRAM) device.

[0027] In some embodiments, the base die includes a control circuit configured to control the first die and the second die.

[0028] In some embodiments, the stacked structure of the first die and the second die includes a first device region, a second device region, and a connection region between the first device region and the second device region, along a second direction perpendicular to the first direction. Each of the first die and the second die includes one or more memory arrays within the first device region and the second device region. The first contact structure and the second contact structure are within the connection region.

[0029] In some embodiments, the ratio of the size of the cross-section of the connection region to the sum of the first size of the cross-section of the first device region and the second size of the cross-section of the second device region is within the range of 1 / 6 to 1 / 5. The cross-section of the connection region, the cross-section of the first device region, and the cross-section of the second device region are perpendicular to the first direction.

[0030] Another aspect of the present disclosure features a semiconductor device including a base die, a first layer, a second layer, a first die between the first layer and the second layer, and a second die, which are stacked along a first direction. Each of the base die, the first die, and the second die has a conductive layer. The first die and the second die are joined via the second layer. The base die and the first die are joined via the first layer. The semiconductor device further includes a first contact structure coupled to the conductive layer of the base die and a second contact structure coupled to the conductive layer of the first die. The first contact structure extends along the first direction and contacts the conductive layer of the base die without extending through the first layer. The second contact structure extends along the first direction without extending through the second layer and extends through the first layer. The second contact structure contacts the conductive layer of the first die without extending through the conductive layer of the base die. The semiconductor device further includes a third contact structure coupled to the conductive layer of the second die. The third contact structure extends along the first direction and extends through the first layer and the second layer without extending through the second die. The third contact structure contacts the conductive layer of the second die without extending through the conductive layer of the first die.

[0031] In some embodiments, the first end of the conductive layer of the first die and the first end of the conductive layer of the second die are offset along a second direction perpendicular to the first direction.

[0032] In some embodiments, the third contact structure is between the first end of the conductive layer of the first die and the first end of the conductive layer of the second die along the second direction.

[0033] In some implementations, the first contact structure, the second contact structure, and the third contact structure are each a continuous structure.

[0034] In some implementation configurations, the second layer includes at least one dielectric material and excludes conductive junction contacts, while the first layer includes at least one dielectric material and excludes conductive junction contacts.

[0035] In some implementation configurations, the second layer includes an upper and lower bonding layer, each containing a dielectric material and excluding conductive bonding contacts. The dielectric material of the upper bonding layer of the second layer is bonded to the dielectric material of the lower bonding layer of the second layer. The first layer includes an upper and lower bonding layer, each containing a dielectric material and excluding conductive bonding contacts. The dielectric material of the upper bonding layer of the first layer is bonded to the dielectric material of the lower bonding layer of the first layer.

[0036] In some implementations, the base die includes an interconnection layer extending along a second direction perpendicular to a first direction. Each of the first, second, and third contact structures is coupled to the interconnection layer.

[0037] In some implementations, the semiconductor device further includes a computing die and an interposer. The base die and the computing die are integrated at different positions on the interposer along a second direction. The base die and the computing die are coupled via an interconnection layer and the interposer.

[0038] In some implementations, the interconnection layer is coupled to a first conductive terminal on the surface of the interposer. The computing die is coupled to a second conductive terminal on the surface of the interposer. The first and second conductive terminals are coupled via conductive wires within the interposer.

[0039] In some implementations, the semiconductor device further includes a computing die and a third layer between the computing die and the base die. The computing die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along a first direction. The base die and the computing die are joined via the third layer.

[0040] In some implementations, the third layer includes a conductive bonding contact and at least one dielectric material separating the conductive bonding contact.

[0041] In some implementation configurations, the third layer includes an upper bonding layer and a lower bonding layer, each containing a conductive bonding contact and a dielectric material separating the conductive bonding contact. The dielectric material of the upper bonding layer of the third layer is bonded to the dielectric material of the lower bonding layer of the third layer. The conductive bonding contact of the upper bonding layer of the third layer is bonded to the conductive bonding contact of the lower bonding layer of the third layer.

[0042] In some implementations, the computing die includes vias that extend along a first direction and are coupled to conductive bonding contacts of a third layer. The interconnection layer of the base die is coupled to the vias via conductive bonding contacts of the third layer.

[0043] In some implementations, the semiconductor device further includes an interposer, and the interposer, computing die, base die, first die, and second die are stacked along a first direction.

[0044] In some implementations, the semiconductor device further includes a first die, a second die, and a third die, the one furthest from the base die, along a first direction. Along the first direction, the thickness of the first die and the thickness of the second die are each smaller than the thickness of the third die.

[0045] In some implementation configurations, the thickness of the first die and the thickness of the second die are in the range of 3 μm to 20 μm.

[0046] In some implementations, the cross-sectional size of the second contact structure in the first die is larger than the cross-sectional size of the second contact structure in the second die. The cross-sections of the second contact structure in the first die and the cross-sections of the second contact structure in the second die are perpendicular to the first direction.

[0047] In some implementations, the first and second contact structures are formed by the same process.

[0048] In some implementations, each of the first and second contact structures has a CD in the range of 0.5 μm to 10 μm.

[0049] In some implementations, at least one of the first die or the second die includes a memory array comprising an array of memory cells and peripheral circuits coupled to the memory array.

[0050] In some implementations, at least one of the first die or the second die is a DRAM device.

[0051] In some implementations, the base die includes a control circuit configured to control the first die and the second die.

[0052] In some implementations, the stacked structure of the first and second dies includes a first device region, a second device region, and a connection region between the first and second device regions, along a second direction perpendicular to the first direction. Each of the first and second dies includes one or more memory arrays in the first and second device regions. The first and second contact structures are located within the connection region.

[0053] In some implementations, the ratio of the size of the cross-section of the connection region to the sum of the first size of the cross-section of the first device region and the second size of the cross-section of the second device region is in the range of 1 / 6 to 1 / 5. The cross-sections of the connection region, the first device region, and the second device region are perpendicular to the first direction.

[0054] Another aspect of the present disclosure features a method comprising providing a first die and a second die, the first die comprising a conductive layer and at least a first bonding layer, and the second die comprising a conductive layer and at least a second bonding layer. The method further comprises laminating the second die on the first die along a first direction and bonding the second bonding layer of the second die to the first bonding layer of the first die. The method further comprises forming a first contact structure and a second contact structure extending along a first direction. The first contact structure contacts the conductive layer of the first die. The second contact structure extends through the first bonding layer of the first die and the second bonding layer of the second die. The second contact structure contacts the conductive layer of the second die without contacting the conductive layer of the first die.

[0055] In some implementation configurations, the first bonding layer of the first die and the second bonding layer of the second die each contain a dielectric material and exclude conductive bonding contacts.

[0056] In some implementations, stacking a second die on a first die along a first direction includes aligning the second die with the first die such that the first end of the conductive layer of the first die and the first end of the conductive layer of the second die are offset along a second direction perpendicular to the first direction.

[0057] In some implementation configurations, providing a first die involves thinning the first die by thinning the substrate included in the first die.

[0058] In some implementations, the method further includes stacking a first die on a carrier wafer, wherein the first die is located between the carrier wafer and a second die.

[0059] In some implementations, the first and second contact structures are formed by the same process. The process includes forming the first and second contact holes, forming an insulating layer in each of the first and second contact holes, and forming a conductive structure within the insulating layer in each of the first and second contact holes. The first contact structure includes an insulating layer and a conductive structure within the first contact hole, and the second contact structure includes an insulating layer and a conductive structure within the second contact hole.

[0060] In some implementation configurations, the first and second contact holes are formed during the same etching process.

[0061] In some implementations, the method further includes forming a mask layer on a first die and etching the mask layer to form a first opening and a second opening. The first contact hole extends from the first opening to the conductive layer of the first die, and the second contact hole extends from the second opening to the conductive layer of the second die.

[0062] In some implementations, the method further comprises forming a third bonding layer on a first die, the third bonding layer comprising a conductive bonding contact and a dielectric material separating the conductive bonding contact.

[0063] In some implementations, the method further comprises providing a base die, the base die comprising a lower junction layer including conductive junction contacts and a dielectric material separating the conductive junction contacts.

[0064] In some implementations, the method further includes stacking the base die on the first die by bonding the dielectric material of the lower bonding layer of the base die to the dielectric material of the third bonding layer of the first die, and bonding the conductive bonding contacts of the lower bonding layer of the base die to the conductive bonding contacts of the third bonding layer of the first die.

[0065] Another aspect of the present disclosure features a semiconductor device comprising a first layer stacked on top of each other along a first direction, a second layer, a first die between the first and second layers, and a second die. Each of the first and second dies has a conductive layer. The first and second dies are joined via the second layer. The semiconductor device further includes a first contact structure coupled to the conductive layer of the first die and a second contact structure coupled to the conductive layer of the second die. The first contact structure extends along the first direction and contacts the conductive layer of the first die without extending through the second layer. The second contact structure extends along the first direction, penetrating the conductive layer of the first die and the second layer, and contacts the conductive layer of the second die without extending through the second die.

[0066] In some implementation configurations, the conductive layer of the first die and the conductive layer of the second die are the same size and are located in the same position along the second direction perpendicular to the first direction.

[0067] In some implementations, each of the first and second contact structures includes a conductive layer extending along a first direction and an insulating layer surrounding the conductive layer.

[0068] In some implementation configurations, the first layer includes a conductive bonding contact and at least one dielectric material separating the conductive bonding contact, while the second layer includes at least one dielectric material and excludes the conductive bonding contact.

[0069] In some implementation configurations, the first layer includes an upper and lower bonding layer, each containing conductive bonding contacts and a dielectric material separating the conductive bonding contacts. The dielectric material of the upper bonding layer of the first layer is bonded to the dielectric material of the lower bonding layer of the first layer. The conductive bonding contacts of the upper bonding layer of the first layer are bonded to the conductive bonding contacts of the lower bonding layer of the first layer. The second layer includes an upper and lower bonding layer, each containing a dielectric material but excluding conductive bonding contacts. The dielectric material of the upper bonding layer of the second layer is bonded to the dielectric material of the lower bonding layer of the second layer.

[0070] In some implementations, the semiconductor device further includes a base die bonded to a first die via a first layer, and the base die, the first layer, the first die, the second layer, and the second die are stacked along a first direction.

[0071] In some implementation configurations, the base die includes a first via extending along a first direction and coupled to a conductive bonding contact of a first layer. Each of the first and second contact structures is coupled to one of the first vias via one of the conductive bonding contacts of the first layer.

[0072] In some implementations, the semiconductor device further comprises a computing die and an interposer, where the base die and the computing die are integrated at different positions on the interposer along a second direction perpendicular to a first direction.

[0073] In some implementations, the first via is coupled to a first conductive terminal on the surface of the interposer. The computing die is coupled to a second conductive terminal on the surface of the interposer. The first and second conductive terminals are coupled via conductive wires within the interposer.

[0074] In some implementations, the semiconductor device further includes a computing die bonded to a base die via a third layer, and the computing die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along a first direction.

[0075] In some implementations, the third layer includes a conductive bonding contact and at least one dielectric material separating the conductive bonding contact.

[0076] In some implementation configurations, the third layer includes an upper bonding layer and a lower bonding layer, each containing a conductive bonding contact and a dielectric material separating the conductive bonding contact. The dielectric material of the upper bonding layer of the third layer is bonded to the dielectric material of the lower bonding layer of the third layer. The conductive bonding contact of the upper bonding layer of the third layer is bonded to the conductive bonding contact of the lower bonding layer of the third layer.

[0077] In some implementations, the computing die includes a second via that extends along a first direction and is coupled to a conductive bonding contact of a third layer. The first via is coupled to the second via via the conductive bonding contact of the third layer.

[0078] In some implementations, the semiconductor device further includes an interposer, and the interposer, computing die, third layer, base die, first layer, first die, second layer, and second die are stacked along a first direction.

[0079] In some implementations, the semiconductor device further includes a first die, a second die, and a third die, the one furthest from the base die, along a first direction. Along the first direction, the thickness of the first die and the thickness of the second die are each smaller than the thickness of the third die.

[0080] In some implementation configurations, the thickness of the first die and the thickness of the second die are in the range of 3 μm to 20 μm.

[0081] In some implementations, the cross-sectional size of the second contact structure in the first die is larger than the cross-sectional size of the second contact structure in the second die. The cross-sections of the second contact structure in the first die and the cross-sections of the second contact structure in the second die are perpendicular to the first direction.

[0082] In some implementations, the first contact structure and the second contact structure are both continuous structures.

[0083] In some implementations, the first and second contact structures are formed by the same process.

[0084] In some implementations, each of the first and second contact structures has a CD in the range of 0.5 μm to 10 μm.

[0085] In some implementations, at least one of the first die or the second die includes a memory array comprising an array of memory cells and peripheral circuits coupled to the memory array.

[0086] In some implementations, at least one of the first die or the second die includes a DRAM device.

[0087] In some implementations, the base die includes a control circuit configured to control the first die and the second die.

[0088] In some implementations, the stacked structure of the first and second dies includes a first device region, a second device region, and a connection region between the first and second device regions, along a second direction perpendicular to the first direction. Each of the first and second dies includes one or more memory arrays within the first and second device regions. The first and second contact structures are located within the connection region.

[0089] In some implementations, the ratio of the size of the cross-section of the connection region to the sum of the first size of the cross-section of the first device region and the second size of the cross-section of the second device region is in the range of 1 / 6 to 1 / 5. The cross-sections of the connection region, the first device region, and the second device region are perpendicular to the first direction.

[0090] Another aspect of the present disclosure features a semiconductor device comprising a base die stacked on top of each other along a first direction, a first layer, a second layer, a first die between the first and second layers, and a second die. Each of the base die, the first die, and the second die has a conductive layer. The base die and the first die are joined via the first layer. The first die and the second die are joined via the second layer. The semiconductor device further includes a first contact structure coupled to the conductive layer of the base die and a second contact structure coupled to the conductive layer of the first die. The first contact structure extends along the first direction and contacts the conductive layer of the base die without extending through the first layer. The second contact structure extends along the first direction and contacts the conductive layer of the first die without extending through the second layer. The semiconductor device further includes a third contact structure bonded to the conductive layer of a second die. The third contact structure extends along a first direction through the first layer, the conductive layer of the first die, and the second layer, and contacts the conductive layer of the second die without extending through the second die.

[0091] In some implementation configurations, the conductive layer of the first die and the conductive layer of the second die are the same size and are located in the same position along the second direction perpendicular to the first direction.

[0092] In some implementations, each of the first, second, and third contact structures includes a conductive layer extending along a first direction and an insulating layer surrounding the conductive layer.

[0093] In some implementation configurations, the first layer includes at least one dielectric material and excludes conductive bonding contacts, and the second layer includes at least one dielectric material and excludes conductive bonding contacts.

[0094] In some implementation configurations, the first layer includes an upper and lower bonding layer, each containing a dielectric material and excluding conductive bonding contacts. The dielectric material of the upper bonding layer of the first layer is bonded to the dielectric material of the lower bonding layer of the first layer. The second layer includes an upper and lower bonding layer, each containing a dielectric material and excluding conductive bonding contacts. The dielectric material of the upper bonding layer of the second layer is bonded to the dielectric material of the lower bonding layer of the second layer.

[0095] In some implementations, the base die includes an interconnection layer extending along a second direction perpendicular to a first direction. Each of the first, second, and third contact structures is coupled to the interconnection layer.

[0096] In some implementations, the semiconductor device further includes a computing die and an interposer. The base die and the computing die are integrated at different positions on the interposer along a second direction. The base die and the computing die are coupled via an interconnection layer and the interposer.

[0097] In some implementations, the interconnection layer is coupled to a first conductive terminal on the surface of the interposer. The computing die is coupled to a second conductive terminal on the surface of the interposer. The first and second conductive terminals are coupled via conductive wires within the interposer.

[0098] In some implementations, the semiconductor device further includes a computing die bonded to a base die via a third layer, and the computing die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along a first direction.

[0099] In some implementations, the third layer includes a conductive bonding contact and at least one dielectric material separating the conductive bonding contact.

[0100] In some implementation configurations, the third layer includes an upper bonding layer and a lower bonding layer, each containing a conductive bonding contact and a dielectric material separating the conductive bonding contact. The dielectric material of the upper bonding layer of the third layer is bonded to the dielectric material of the lower bonding layer of the third layer. The conductive bonding contact of the upper bonding layer of the third layer is bonded to the conductive bonding contact of the lower bonding layer of the third layer.

[0101] In some implementations, the computing die includes vias that extend along a first direction and are coupled to conductive bonding contacts of a third layer.

[0102] In some implementations, the semiconductor device further includes an interposer, and the interposer, computing die, third layer, base die, first layer, first die, second layer, and second die are stacked along a first direction.

[0103] In some implementations, the semiconductor device further includes a first die, a second die, and a third die, the one furthest from the base die, along a first direction. Along the first direction, the thickness of the first die and the thickness of the second die are each smaller than the thickness of the third die.

[0104] In some implementations, the cross-sectional size of the second contact structure in the first die is larger than the cross-sectional size of the second contact structure in the second die. The cross-sections of the second contact structure in the first die and the cross-sections of the second contact structure in the second die are perpendicular to the first direction.

[0105] In some implementations, the first contact structure and the second contact structure are both continuous structures.

[0106] In some implementations, the first and second contact structures are formed by the same process.

[0107] In some implementations, each of the first, second, and third contact structures has a CD in the range of 0.5 μm to 10 μm.

[0108] In some implementations, at least one of the first die or the second die includes a memory array comprising an array of memory cells and peripheral circuits coupled to the memory array.

[0109] In some implementations, at least one of the first die or the second die includes a DRAM device.

[0110] In some implementations, the base die includes a control circuit configured to control the first die and the second die.

[0111] In some implementations, the stacked structure of the first and second dies includes a first device region, a second device region, and a connection region between the first and second device regions, along a second direction perpendicular to the first direction. Each of the first and second dies includes one or more memory arrays within the first and second device regions. The first and second contact structures are located within the connection region.

[0112] In some implementations, the ratio of the size of the cross-section of the connection region to the sum of the first size of the cross-section of the first device region and the second size of the cross-section of the second device region is in the range of 1 / 6 to 1 / 5. The cross-sections of the connection region, the first device region, and the second device region are perpendicular to the first direction.

[0113] Another aspect of the present disclosure features a method comprising providing a first die and a second die, the first die comprising a first conductive layer and at least a first bonding layer, and the second die comprising a second conductive layer and at least a second bonding layer. The method further comprises laminating the second die on the first die along a first direction and bonding the second bonding layer to the first bonding layer. The method further comprises forming a first contact structure and a second contact structure extending along a first direction. The first contact structure contacts the first conductive layer without extending through the first bonding layer. The second contact structure extends through the first conductive layer, the first bonding layer, and the second bonding layer, and contacts the second conductive layer without extending through the second die.

[0114] In some implementation configurations, the first and second bonding layers each contain a dielectric material and exclude conductive bonding contacts. Bonding the second bonding layer to the first bonding layer includes bonding the dielectric material of the first bonding layer to the dielectric material of the second bonding layer.

[0115] In some implementations, stacking a second die on a first die along a first direction involves aligning the second die with the first die to position the first and second conductive layers in the same location along a second direction perpendicular to the first direction, wherein the first and second conductive layers are the same size.

[0116] In some implementations, the method further includes thinning the first die by thinning the substrate contained within the first die.

[0117] In some implementations, the method further includes bonding a carrier wafer to the surface of a first die, where the first die is located between the carrier wafer and a second die.

[0118] In some implementation configurations, forming a first contact structure and a second contact structure includes forming a mask layer on a first die, etching the mask layer to form a first opening and a second opening, forming a first contact hole and a second contact hole extending along a first direction, wherein the first contact hole extends from the first opening to a first conductive layer, and the second contact hole extends from the second opening to the first conductive layer, filling the first contact hole with a filler material, deepening the second contact hole until the second contact hole penetrates the first conductive layer and extends to the second conductive layer, removing the filler material from the first contact hole, forming an insulating layer in each of the first and second contact holes, and depositing a conductive material in the first and second contact holes to form a first contact structure in the first contact hole and a second contact structure in the second contact hole.

[0119] In some implementations, forming the first and second contact holes involves etching the separation material in the first die using a first etching gas. Deepening the second contact hole involves etching the conductive material of the first conductive layer using a second etching gas different from the first etching gas.

[0120] In some implementations, the method further comprises forming a third bonding layer on the surface of a first die opposite to the first bonding layer, wherein the third bonding layer includes a conductive bonding contact and a dielectric material separating the conductive bonding contact.

[0121] In some implementations, the method further includes providing a base die, the base die comprising a fourth bonding layer including vias extending along a first direction, conductive bonding contacts coupled to the vias, and a dielectric material separating the conductive bonding contacts. The method further includes bonding the fourth bonding layer of the base die to a third bonding layer on the surface of the first die.

[0122] In some implementation configurations, joining the fourth bonding layer to the third bonding layer includes joining the dielectric material of the fourth bonding layer to the dielectric material of the third bonding layer, and joining the conductive bonding contacts of the fourth bonding layer to the conductive bonding contacts of the third bonding layer.

[0123] In some implementation configurations, the method further includes stacking a base die on a first die, wherein the base die includes a third conductive layer, and forming a third contact structure coupled to the base die. Forming the first, second, and third contact structures involves forming a mask layer on the base die, etching the mask layer to form a first opening, a second opening, and a third opening, and forming a first contact hole, a second contact hole, and a third contact hole extending along a first direction, wherein the first contact hole extends from the first opening to the first conductive layer, the second contact hole extends from the second opening to the first conductive layer, and the third contact hole extends from the third opening to the third conductive layer, and filling the first and third contact holes. The method includes filling with a filler material, deepening the second contact hole until the second contact hole penetrates the first conductive layer and extends to the second conductive layer, removing the filler material from the first and third contact holes, forming an insulating layer in each of the first, second, and third contact holes, and depositing conductive material in the first, second, and third contact holes to form a first contact structure in the first contact hole, a second contact structure in the second contact hole, and a third contact structure in the third contact hole.

[0124] Implementations of the present disclosure may provide one or more of the following technical advantages and / or benefits. For example, a semiconductor device may include multiple memory dies stacked vertically. Note that the terms “dice” and “dies” may be used interchangeably in this disclosure. Multiple memory dies are joined to each other using direct bonding technology. Some of the memory dies can be made thinner, thereby increasing the memory density and capacity of the semiconductor device. One of the memory dies can be made thicker than the others, and therefore can replace a carrier wafer to support the other memory dies during the manufacturing process of the semiconductor device. As a result, the carrier wafer can be used less frequently in the manufacturing process, thereby effectively improving manufacturing efficiency and reducing manufacturing costs. Memory dies may be bonded to each other and to logic devices via contact structures extending within the stacked memory die. The use of direct bonding between memory dies, hybrid bonding between adjacent semiconductor structures (such as between a memory die and a base die, or between a base die and a computing die), and contact structures allows for self-alignment in the manufacturing process of the semiconductor device, thereby effectively improving manufacturing reliability. Furthermore, each contact structure can have a continuous structure and smaller limit dimensions. Therefore, a higher interconnection density can be achieved between different dies within the semiconductor device, thereby increasing the memory bandwidth and data transfer speed of the semiconductor device.

[0125] This technology can be applied, in particular, to various types of semiconductor devices, including volatile memory devices such as DRAM memory devices, non-volatile memory (NVM) devices such as NAND flash memory, NOR flash memory, and resistive random access memory (RRAM), phase-change memory (PCM) such as phase-change random access memory (PCRAM), and spin-transfer torque (STT)-magnetoresistive random access memory (MRAM). This technology can also be applied to charge-trap-based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices, and floating-gate-based memory devices. This technology can be applied to three-dimensional (3D) memory devices. This technology can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices like 2-level cell devices, TLC (triple-level cell) devices, QLC (quad-level cell) devices, or PLC (penta-level cell) devices. Additionally or alternatively, this technology can be applied to various types of devices and systems, including, among others, secure digital (SD) cards, embedded multimedia cards (eMMC), or solid-state drives (SSDs), and embedded systems.

[0126] Details of one or more implementations of the subject matter of this disclosure are described in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. [Brief explanation of the drawing]

[0127] The accompanying drawings incorporated herein and forming part of the disclosure illustrate aspects of the disclosure, and together with the description, illustrate the principles of the disclosure and further enable those skilled in the art to create and use the disclosure. [Figure 1] A block diagram of a typical system having one or more semiconductor devices, according to some aspects of this disclosure, is shown. [Figure 2A]Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 2B] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 2C] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 2D] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 2E] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 3A] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 3B] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 3C] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 3D] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 3E] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 3F] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 3G] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 3H] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 4A] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 4B] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 4C] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 4D] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 4E]This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 4F] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 4G] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 4H] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 4I] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 4J] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 5] A flowchart of a typical process for forming a semiconductor device, according to some aspects of this disclosure, is shown. [Figure 6A] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 6B] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 6C] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 6D] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 6E] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 6F] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 6G] Typical semiconductor devices according to some aspects of this disclosure are shown. [Figure 7A] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 7B] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 7C]This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 7D] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 7E] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 7F] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 7G] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 7H] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 7I] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 7J] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 7K] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 7L] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 7M] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 7N] This disclosure illustrates a typical process for manufacturing semiconductor devices according to several aspects of this disclosure. [Figure 8] A flowchart of a typical process for forming a semiconductor device, according to some aspects of this disclosure, is shown.

[0128] Similar reference numbers and symbols in various drawings indicate the same elements. It should also be understood that the various typical implementation configurations shown in the drawings are merely representative representations and are not necessarily drawn to scale. [Modes for carrying out the invention]

[0129] Figure 1 shows a block diagram of a typical system 100 having one or more semiconductor devices (e.g., memory devices) according to some aspects of the present disclosure. System 100 can be a mobile phone, desktop computer, laptop computer, tablet, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, argument reality (AR) device, or any other suitable electronic device having internal memory. As shown in Figure 1, system 100 may include one or more memory devices 102, a base device 104, a computing device 108, and an external host device 112. In some implementations, each of devices 102, 104, 108, and 112 may be a die stacked on top of each other or multiple dies. Each of devices 102, 104, 108, and 112 can be manufactured by depositing multiple layers of various materials and etching them onto a semiconductor wafer in a complex pattern defined by the chip design. After the wafer manufacturing process is complete, the wafer containing the individual circuits is cut and diced into individual pieces, each of which is a die. Each die may contain a fully functional electronic circuit that can be a microprocessor, memory, sensor, or any other suitable type of integrated circuit. In some embodiments, each die is enclosed in a protective package to provide physical support, protection from environmental factors, and connectivity to an external device or system (e.g., via pins or solder balls).

[0130] The memory die 102 may include any memory device disclosed herein, such as a memory device (e.g., a 3D memory device) based on any one of the semiconductor structures described with respect to Figures 2A-2E, 3A-3D, 4A-4J, 6A-6D, and 7A-7M. In some implementations, the memory die 102 includes one or more dynamic random access memory (DRAM) devices. In some implementations, the memory die 102 includes one or more NAND flash memories. In some implementations, the memory die 102 may include high-bandwidth memory (HBM). In some implementations, the memory dies 102 can be stacked together, for example, as described in more detail with respect to Figures 2A-2E, 3A-3D, and 6A-6D. In some implementations, the memory die 102 may include a combination of one or more HBM devices as described in Figures 2C and 3A to 3D, and one or more HBM devices as described in Figures 2D and 6A to 6D.

[0131] The base die 104 (also called a logic die or buffer die) may include buffer circuits and test logic for the memory device 102. The base die 104 may be configured to provide a physical layer communication protocol (e.g., IEEE-1500) between the memory die 102 and the computing die 108. The base die 104 may be configured to transmit data between the memory die 102 and the computing die 108 based on control commands and addresses from the computing die 108.

[0132] The computing die 108 can be a logic device and may include at least one processor of an electronic device such as a system-on-a-chip (SoC), such as a central processing unit (CPU), graphics processing unit (GPU), application-specific integrated circuit (ASIC), or application processor (AP). The computing die 108 may be configured to send and receive data to and from the memory die 102. The computing die 108 is coupled to the base die 104 via interface 106. Interface 106 may include connections provided by junction contacts (e.g., as described with respect to Figures 3A and 6A) or interposers (e.g., as described with respect to Figures 3D and 6D). In some implementations, interface 106 may include connections provided by any suitable combination of the aforementioned techniques.

[0133] The system 100 may further include an external host die 112 coupled to the computing die 108 via an interface 110. For example, the external host die 112 may be a computer, and the computing die 108 may be the CPU of the computer. In this example, the interface 110 includes connections provided by the computer's mainboard coupled to the CPU. In another example, the external host die 112 may be a graphics card, and the computing die 108 may be the graphics card's GPU, and the interface 110 includes connections provided by the graphics card's printed circuit board (PCB) coupled to the GPU.

[0134] The system 100 may further include a memory controller (also known as a control circuit, not shown in Figure 1) coupled to the memory die 102. In some implementations, the memory controller is located on the computing die 108. Consistent with the implementations of this disclosure, the memory controller may include conductive interconnects via a cover layer in contact with conductive pads in a conductive pad layer, and the memory controller may be coupled to the memory die 102 via at least one of the conductive interconnects. The memory controller is configured to control the memory die 102. For example, the memory controller may be configured to operate a channel structure via word lines. The memory controller can manage data stored on the memory die 102 and communicate with the computing die 108.

[0135] In some implementations, the memory controller is designed / configured to operate in low-duty-cycle environments such as Secure Digital (SD) cards, CompactFlash® (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller is designed / configured to operate in high-duty-cycle environments such as SSDs or embedded multimedia cards (eMMCs) used as data storage devices in mobile devices such as smartphones, tablets, and laptop computers, and in enterprise storage arrays. The memory controller can be configured to control the operation of the memory die 102, such as read, erase, and program (or write) operations. The memory controller can also be configured to manage various functions related to the data stored or to be stored on the memory die 102, including but not limited to bad block management, garbage collection, logical-physical address translation, and wear leveling. In some implementations, the memory controller is further configured to process error correction codes (ECC) with respect to data read from or written to the memory die 102. In some other implementations, the base die 104 is configured to handle ECC instead of the memory controller. Any other appropriate function, such as formatting the memory die 102, can also be performed by the memory controller.

[0136] The memory controller can communicate with an external device (e.g., computing die 108) according to a specific communication protocol. For example, the memory controller can communicate with an external device via at least one of various interface protocols, such as the USB protocol, MMC protocol, Peripheral Interconnect (PCI) protocol, PCI Express (PCTe or PCI-e) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0137] The memory controller and one or more memory dies 102 can be integrated into various types of storage devices, for example, they can be included in the same package, such as a universal flash storage (UFS) package or an eMMC package. In other words, the system 100 can be implemented and packaged in different types of final electronic products. For example, the memory controller and a single memory die 102 may be integrated into a memory card. The memory card may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0138] Figures 2A to 2E show typical semiconductor devices 200 and 200d according to several embodiments of the present disclosure. Semiconductor devices 200 or 200d can be used to form memory devices such as HBM.

[0139] Note that the X, Y, and Z axes (also called the X, Y, and Z directions) are included in Figures 2A to 2E to further illustrate the spatial relationships of the various components within a semiconductor device. The substrate of a semiconductor device includes two sides extending laterally in the XY plane: the top surface of the front of the wafer, which can form the components of the semiconductor device, and the bottom surface of the back of the wafer, opposite the front. The Z direction is perpendicular to both the X and Y directions. As used herein, whether one component of a semiconductor device (e.g., a layer or device) is "above," "upper," or "below" another component of the semiconductor device (e.g., a layer or device) in the Z direction is determined relative to the substrate of the semiconductor device in the Z direction (a vertical direction perpendicular to the XY plane, e.g., the thickness direction of the substrate) when the substrate is located at the bottom surface of the semiconductor device in the Z direction. The same concepts for describing spatial relationships apply throughout this disclosure.

[0140] As shown in Figure 2A, the semiconductor device 200 includes a stack 202 of memory dies 204a to 204d. Each of the memory dies 204a to 204d can be a dynamic random access memory (DRAM) device. The memory dies 204a to 204d are stacked along the vertical direction (e.g., the Z direction) (e.g., sequentially). The stack 202 includes one or more device regions 206 and one or more connection regions 208. Each of the memory dies 204a to 204d can include a memory array and peripheral circuits within each device region 206. The memory array may include an array of memory cells, and peripheral circuits may be coupled to the memory array.

[0141] The semiconductor device 200 further includes contact structures 210 within a connection region 208. Each contact structure 210 may extend into one of the memory dies 204a-204d and may be coupled to an external component outside the stack 202. As will be described in more detail with respect to some other figures of this disclosure, each contact structure 210 may include a conductive material and may be coupled to a conductive layer in one of the memory dies 204a-204d. In some implementations, adjacent memory dies among the memory devices 204a-204d (e.g., memory dies 204a and 204b) are bonded via a corresponding junction layer (not shown in Figure 2A). The semiconductor device 200 may further include a base die 212. The stack 202 may be stacked on the base die 212 along the vertical direction. In some implementations, the memory die 204a and the base die 212 are bonded via another junction layer (not shown in Figure 2A).

[0142] Figure 2B shows a cross-sectional view of a semiconductor device 200 along the cutting line AA' of Figure 2A, according to several embodiments of the present disclosure. The semiconductor device 200 has two device regions 206 arranged horizontally (e.g., in the X direction). The semiconductor device 200 also has a connection region 208 between the two device regions 206 along the X direction. Figure 2B shows a typical arrangement of the device regions 206 and the connection region 208, but any other suitable arrangement is possible. In some implementations, the semiconductor device 200 may include one device region 206 and one connection region 208 adjacent to each other along the X direction. In some implementations, as shown in Figure 2E, the semiconductor device 200 may include two connection regions 208 arranged along the X direction and one device region 206 between the two connection regions 208 along the X direction. In some implementations, the semiconductor device 200 may include a first connection region 208, a second connection region 208, and a device region 206 arranged along the X direction. The first connection region 208 may be in the center of the semiconductor device 200, and the second connection region 208 may be on one side (e.g., the left side) of the first connection region 208. The device region 206 may be on the other side (e.g., the right side) of the first connection region 208. In some implementations, the connection region 208 can exclude the word lines within the memory dies 204a-204d. In this way, the contact structure 210 within the connection region 208 can bypass the conductive material (e.g., metal) of the word lines within the memory dies 204a-204d and extend through the dielectric material (e.g., the insulating layer or substrate of the memory device), thereby making the manufacturing of the semiconductor device 200 cost-effective. The cross-section (e.g., in the XY plane) of the connection region 208 and the cross-section (e.g., in the XY plane) of the device region 206 can be of any appropriate size. For example, in Figure 2B, the ratio of the cross-sectional size of the connection region 208 to the sum of the cross-sectional sizes of the device region 206 (left side) and the device region 206 (right side) can be any appropriate range (e.g., 1 / 6 to 1 / 5). The cross-sections of the connection region 208 and the two device regions 206 can lie in the XY plane.In some implementation configurations, the connection between memory dies 204a to 204d can be made more stable by positioning the device region 206 at the center of the semiconductor device 200 and the connection region 208 along the horizontal direction on one or both sides of the device region 206.

[0143] In some implementations, each of the connection regions 208 can contain more than 1,000 contact structures 210. Each contact structure 210 can have a limiting dimension (CD) within any suitable range (e.g., 0.5 micrometers (μm) to 10 μm).

[0144] Figure 2C shows a cross-sectional view of a semiconductor device 200 along the cutting line BB' of Figure 2A, according to several embodiments of the present disclosure. The memory die 204a includes a substrate 220a extending along the X direction. The substrate 220a can be any suitable semiconductor substrate having any suitable semiconductor material such as monocrystalline, polycrystalline, or single crystalline semiconductors. For example, the substrate 220a may include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. The memory die 204a also includes conductive layers 222a and 224a. Each of the conductive layers 222a and 224a extends from the device region 206 to the connection region 208 and can be coupled to the memory array of the memory die 204a or to the peripheral circuits of the memory array within the device region 206. For example, conductive layers 222a and 224a can be coupled to the input / output ports of the memory die 204a. In some implementations, conductive layers 222a and 224a can be configured to provide one or more of the following to the memory die 204a: power, clock signals, or data path signals. Each of the memory dies 204b to 204d also includes their respective substrates 220b to 220d and conductive layers (e.g., 222b and 224b, 222c and 224c, 222d and 224d). Each of the conductive layers of the memory dies 204b to 204d is also coupled to the corresponding memory array or peripheral circuits of the memory die. Similar to conductive layers 222a and 224a, each conductive layer of memory dies 204b to 204d may also be configured to provide one or more of the following to the memory die: power, clock signals, or data path signals.

[0145] In some implementation configurations, some of the memory dies 204a to 204d can be made thinner (along the Z direction) by thinning their substrates. As shown in Figure 2C, each of the substrates 220a to 220c is thin, while substrate 220d is not. As a result, the thickness of each of the memory dies 204a to 204c is smaller than the thickness of memory die 204d. The thickness of each of the memory dies 204a to 204d can be any suitable range (e.g., 3 μm to 20 μm).

[0146] The semiconductor device 200 includes junction layers 221a to 221c. As shown in Figure 2C, each of the junction layers 221a to 221c lies between two memory dies 204a to 204d. Memory dies 204a and 204b are joined via junction layer 221a. Memory dies 204b and 204c are joined via junction layer 221b. Memory dies 204c and 204d are joined via junction layer 221c. The detailed structure of junction layers 221a to 221c will be described with reference to some other figures of this disclosure (e.g., Figure 3B). In some implementations, the semiconductor device 200 includes a device (not shown) on top of the memory die 204a. The device and the memory die 204a may be joined via another junction layer (not shown) between the device and the memory die 204a.

[0147] The semiconductor device 200 includes contact structures 226a-226d and 228a-228d within a connection region 208. Contact structures 226a-226d and 228a-228d can be examples of contact structures 210 shown in Figures 2A-2B. Contact structure 226a may include an inner layer 230 surrounded by an outer layer 232. In other words, the inner layer 230 lies on the inner surface of the outer layer 232. The inner layer 230 may contain a conductive material (e.g., copper or tungsten), and the outer layer 232 may contain an insulating material (e.g., silicon oxide). Similarly, each of the contact structures 226b-226d and 228a-228d also includes a conductive inner layer and an insulating outer layer. Contact structures 226a-226d and 228a-228d extend along the vertical direction (e.g., the Z direction).

[0148] In some implementations, each of the contact structures 226a-226d and 228a-228d is a continuous structure extending along the Z direction. In other words, each of the contact structures 226a-226d and 228a-228d includes a continuous inner layer and a continuous outer layer both extending along the Z direction.

[0149] In some implementations, each contact structure 226a-226d and 228a-228d can have a cylindrical or truncated cone shape. In some implementations, the size of the first cross-section of the contact structure at a first position along the Z direction is larger than the size of the second cross-section of the contact structure at a second position along the Z direction. The first and second cross-sections may be perpendicular to the Z direction. The first position is further away from the thickest memory die among the memory dies 204a-204d than the second position. For example, contact structure 226d may have a cross-section in memory die 204a and another cross-section in memory die 204b. The size of the cross-section in memory die 204a can be larger than the size of the cross-section in memory die 204b. In some implementations, contact structures 226a-226d and 228a-228d can be formed by the same process (for example, described in more detail in relation to Figures 4G-4I).

[0150] Contact structures 226a and 228a extend within the memory die 204a without penetrating the bonding layer 221a. Contact structures 226a and 228a are connected to the conductive layers 222a and 224a of the memory die 204a, respectively. Contact structures 226b and 228b extend through the memory die 204a (including the substrate 220a) and the bonding layer 221a, but extend within the memory die 204b without penetrating the bonding layer 221b. Contact structures 226b and 228b are connected to the conductive layers 222b and 224b of the memory die 204b, respectively. Contact structure 226b does not extend through the conductive layer 222a, and contact structure 228b does not extend through the conductive layer 224a. The contact structures 226c and 228c extend through the memory die 204a (including the substrate 220a), the bonding layer 221a, the memory die 204b (including the substrate 220b), and the bonding layer 221b, but extend within the memory die 204c without extending through the bonding layer 221c. The contact structures 226c and 228c are connected to the conductive layers 222c and 224c of the memory die 204c, respectively. The contact structure 226c does not extend through the conductive layers 222a and 222b, and the contact structure 228c does not extend through the conductive layers 224a and 224b. The contact structures 226d and 228d extend into the memory die 204d, penetrating the memory die 204a (including the substrate 220a), the bonding layer 221a, the memory die 204b (including the substrate 220b), the bonding layer 221b, the memory die 204c (including the substrate 220c), and the bonding layer 221c. The contact structures 226d and 228d are connected to the conductive layers 222d and 224d of the memory device 204d, respectively. The contact structure 226d does not extend through the conductive layers 222a, 222b, and 222c, and the contact structure 228d does not extend through the conductive layers 224a, 224b, and 224c.

[0151] In some implementations, the conductive layers 222a to 222d can form a stepped structure that allows each of the contact structures 226a to 226d to connect to one of the conductive layers 222a to 222d without extending through the other conductive layers. In some implementations, as shown in Figure 2C, the conductive layers 222a to 222d can have varying lengths. The conductive layers 222a to 222d can extend in the X direction from substantially the same position and extend by different lengths (e.g., to the right) to form a stepped structure. Specifically, the contact structure 226b is located along the X direction between the end 234a of conductive layer 222a (e.g., on the right) and the end 234b of conductive layer 222b (e.g., on the right). That is, the end 234a of conductive layer 222a is located along the X direction between the contact structure 226a and the contact structure 226b. In this way, the contact structure 226b can extend through the memory die 204a and bypass the conductive layer 222a of the memory die 204a (for example, it can not extend through the conductive layer 222a). Similarly, the contact structure 226c is located along the X direction between the end 234b of the conductive layer 222b and the end 234c of the conductive layer 222c (for example, on the right side), and as a result, the contact structure 226c can extend through the memory dies 204a to 204b and bypass the conductive layers 222a to 222b (for example, it can not extend through the conductive layers 222a to 222b). Furthermore, the contact structure 226d is located along the X direction between the end 234c of the conductive layer 222c and the end 234d of the conductive layer 222d (e.g., the right side), and as a result, the contact structure 226d can extend through the memory dies 204a-204c and bypass the conductive layers 222a-222c (e.g., it does not extend through the conductive layers 222a-222c).

[0152] Similarly, the conductive layers 224a to 224d can also form a stepped structure that allows each of the contact structures 228a to 228d to connect to one of the conductive layers 224a to 224d without extending through the other conductive layers. Figure 2C shows an example in which a stepped structure is formed by conductive layers of different lengths, but other suitable methods of arranging the conductive layers are also possible (for example, as will be described in more detail with respect to Figures 3A, 3D, 3E, 3G, and 3H).

[0153] Figure 2D shows a cross-sectional view of a semiconductor device 200d along the cutting line BB' according to several embodiments of the present disclosure. The semiconductor device 200d differs from the semiconductor device 200 in Figure 2C in that the memory dies 204a to 204d of the semiconductor device 200d can include conductive layers of the same length and position along the X direction. As shown in Figure 2D, the memory die 204a includes conductive layers 236a and 238a. Each of the conductive layers 236a and 238a extends from the device region 206 to the connection region 208 and is coupled to the memory array of the memory die 204a or to peripheral circuits of the memory array within the device region 206. For example, the conductive layers 236a and 238a can be coupled to the input / output ports of the memory die 204a. In some implementations, the conductive layers 236a and 238a can be configured to provide one or more of the following to the memory die 204a: power, clock signals, or data path signals. Each of the memory dies 204b to 204d also includes its respective conductive layer (e.g., 236b and 238b, 236c and 238c, 236d and 238d). Each conductive layer of the memory dies 204b to 204d is also coupled to the corresponding memory array or peripheral circuit of each memory die. Similar to conductive layers 236a and 238a, each conductive layer of the memory dies 204b to 204d may also be configured to provide one or more of the following to the memory die: power, clock signals, or data path signals. Conductive layers 236a to 236d have the same length and are located in the same position along the X direction. Similarly, conductive layers 238a to 238d have the same length and are located in the same position along the X direction. In some implementation configurations, conductive layers 236a to 236d have the same shape, and conductive layers 238a to 238d have the same shape. Since the conductive layers within each memory die can be formed using the same mask, manufacturing costs can be reduced.

[0154] The semiconductor device 200d includes contact structures 226a-226d and 228a-228d extending along a vertical direction (e.g., the Z direction). Contact structures 226a and 228a extend within the memory die 204a without penetrating the junction layer 221a. Contact structures 226a and 228a are connected to conductive layers 236a and 238a of the memory die 204a, respectively. Contact structures 226b and 228b extend within the memory die 204b, penetrating the memory die 204a (including the substrate 220a) and the junction layer 221a, but without penetrating the junction layer 221b. Contact structure 226b extends through the conductive layer 236a, and contact structure 228b extends through the conductive layer 238a. Contact structures 226b and 228b are connected to conductive layers 236b and 238b of the memory die 204b, respectively. Contact structures 226c and 228c extend through the memory die 204a (including substrate 220a), bonding layer 221a, memory die 204b (including substrate 220b), and bonding layer 221b, but extend within the memory die 204c without extending through bonding layer 221c. Contact structure 226c extends through conductive layers 236a to 236b, and contact structure 228c extends through conductive layers 238a to 238b. Contact structures 226c and 228c are connected to conductive layers 236c and 238c of the memory die 204c, respectively. The contact structures 226d and 228d do not extend through the memory die 204d, but extend within the memory die 204d by penetrating the memory die 204a (including the substrate 220a), the bonding layer 221a, the memory die 204b (including the substrate 220b), the bonding layer 221b, the memory die 204c (including the substrate 220c), and the bonding layer 221c. The contact structure 226d extends through the conductive layers 236a to 236c, and the contact structure 228d extends through the conductive layers 238a to 238c. The contact structures 226d and 228d are connected to the conductive layers 236d and 238d of the memory die 204d, respectively.

[0155] In some implementation configurations, for each contact structure 226a-226d and 228a-228d, the outer layer of the contact structure is located between the inner layer of the contact structure and the conductive layer through which the contact structure extends. The outer layer can insulate the inner layer from the conductive layer through which the contact structure extends.

[0156] Figures 2A to 2E and several other figures in this disclosure illustrate examples of contact structures being coupled to stacked memory dies, but any other suitable semiconductor devices or dies can be stacked and coupled to contact structures using a similar technique. This technique can be applied, in particular, to various types of semiconductor devices, including volatile memory devices such as DRAM memory devices, non-volatile memory (NVM) devices such as NAND flash memory, NOR flash memory, and resistive random access memory (RRAM), phase-change memory (PCM) such as phase-change random access memory (PCRAM), and spin-transfer torque (STT)-magnetoresistive random access memory (MRAM). This technique can also be applied to charge-trap-based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices, and floating-gate-based memory devices. This technique can be applied to three-dimensional (3D) memory devices. This technology can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices like 2-level cell devices, TLC (triple-level cell) devices, QLC (quad-level cell) devices, or PLC (penta-level cell) devices. Additionally or alternatively, this technology can be applied to various types of devices and systems, including, among others, Secure Digital (SD) cards, Embedded Multimedia Cards (eMMC), or Solid State Drives (SSDs), and embedded systems.

[0157] Figure 3A shows a side view of a semiconductor device 300a according to several embodiments of the present disclosure. The semiconductor device 300a includes memory dies 302a-308a stacked (e.g., sequentially) along a vertical direction (e.g., Z direction), a base die 344a, a computing die 346a, and an interposer 348a. The memory dies 302a-308a can be examples of memory die 102 in Figure 1 and memory dies 204a-204d in Figure 2A (e.g., DRAM). The stack of memory dies 302a-308a includes a device region 301a and a connection region 303a adjacent to each other along a horizontal direction (e.g., X direction). Each of the memory dies 302a-308a includes conductive layers 310a-316a extending along a horizontal direction (e.g., X direction). Each of the conductive layers 310a to 316a has one end coupled to a memory array or peripheral circuit in the corresponding memory die within the device region 301a, and the other end (e.g., ends 318a to 324a) extending away from the device region 301a. Each of the conductive layers 310a to 316a can be coupled to the input / output ports of the corresponding memory die, or can be configured to provide one or more of the following to the corresponding memory die: power, clock signals, or data path signals.

[0158] As shown in Figure 3A, the semiconductor device 300a includes contact structures 326a to 332a within the connection region 303a. The contact structures 326a to 332a can be examples of the contact structure 210 shown in Figures 2A to 2B. The semiconductor device 300a further includes junction layers between adjacent memory dies 302a to 308a (e.g., junction layers 334a, 336a, and 338a), a junction layer 340a between the memory die 302a and the base die 344a, and a junction layer 342a between the base die 344a and the computing die 346a. Each of these junction layers may contain a dielectric material such as silicon oxide.

[0159] Contact structures 326a to 332a extend along the vertical direction (e.g., the Z direction) and are coupled to conductive layers 310a to 316a, respectively. Contact structure 326a extends into memory die 302a and connects to the conductive layer 310a of memory die 302a without extending through the bonding layer 334a. Contact structure 328a extends into memory die 304a, penetrating memory die 302a and bonding layer 334a without extending through bonding layer 336a. Contact structure 328a connects to the conductive layer 310a of memory die 304a without extending through conductive layer 312a. Contact structure 330a extends into memory die 306a, penetrating memory dies 302a to 304a, bonding layers 334a and 336a without extending through bonding layer 338a. The contact structure 330a is connected to the conductive layer 314a of the memory die 306a without extending through the conductive layers 310a and 312a. The contact structure 332a extends into the memory die 308a, penetrating the memory dies 302a to 306a and the bonding layers 334a to 338a, without extending through the memory die 308a. The contact structure 332a is connected to the conductive layer 316a of the memory die 308a without extending through the conductive layers 310a to 314a.

[0160] The conductive layers 310a to 316a can form a stepped structure, allowing each of the contact structures 326a to 332a to connect to one of the conductive layers 310a to 316a without extending through the other conductive layers. In some implementations, as shown in Figure 3A, the conductive layers 310a to 316a can have the same length and be offset along the X direction. In other words, the ends 318a to 324a of the conductive layers 310a to 316a (e.g., the right end) can be offset along the X direction. Specifically, the contact structure 328a is located along the X direction between the end 318a of conductive layer 310a and the end 320a of conductive layer 312a. That is, the end 318a of conductive layer 310a is located along the X direction between the contact structure 326a and the contact structure 328a. In this way, the contact structure 328a extends through the memory die 302a and can bypass the conductive layer 310a of the memory die 302a. Similarly, the contact structure 330a is located along the X direction between the end 320a of the conductive layer 312a and the end 322a of the conductive layer 314a, and as a result, the contact structure 330a extends through the memory dies 302a to 304a and can bypass the conductive layers 310a to 312a. Furthermore, the contact structure 332a is located along the X direction between the end 322a of the conductive layer 314a and the end 324a of the conductive layer 316a, and as a result, the contact structure 332a extends through the memory dies 302a to 306a and can bypass the conductive layers 310a to 314a. The typical stepped structure formed by conductive layers 310a-316a, as shown in Figure 3A, is for illustrative purposes only and should not be interpreted in a restrictive sense. Figure 3H shows a different structure formed by the conductive layers of semiconductor device 300h, which also allows each contact structure of semiconductor device 300h to connect to one of the conductive layers of semiconductor device 300h without extending through other conductive layers.

[0161] In some implementations, junction layers 334a, 336a, and 338a can be called direct junction layers because they are formed by direct dielectric-dielectric junctions. Each of junction layers 334a, 336a, and 338a may include at least one dielectric material and exclude conductive junction contacts. In some implementations, junction layers 340a and 342a can be called hybrid junction layers because they can be formed by hybrid dielectric-dielectric junctions and metal-metal junctions. Each of junction layers 340a and 342a may include junction contacts (e.g., conductive junction contacts) and at least one dielectric material separating the junction contacts. As shown in Figure 3A, junction layer 340a includes a conductive junction contact 354a. The conductive junction contact 354a may be configured to connect the memory die 302a and the base die 344a. In some implementations, the memory die 302a may include an interconnection layer (not shown in Figure 3A) that contacts junction layer 340a. The interconnection layer of the memory die 302a has a structure similar to the interconnection layer 345f described in Figure 3F. Each of the contact structures 326a to 332a can be coupled to the interconnection layer of the memory die 302a. The interconnection layer of the memory die 302a can be coupled to the base die 344a via conductive bonding contacts 354a in the bonding layer 340a. The base die 344a includes vias 350a that extend through the base die 344a along the Z direction and are connected to the conductive bonding contacts 354a. Each of the contact structures 326a to 332a is coupled to each of the vias 350a via the corresponding conductive bonding contacts 354a. The bonding layer 342a includes a conductive bonding contact 356a. The conductive bonding contact 356a can be configured to connect the base die 344a and the computing die 346a. The computing die 346a can be an example of the computing die 108 in Figure 1. The computing die 346a includes vias 352a that extend through the computing die 346a along the Z direction and are connected to the conductive bonding contacts 356a.Each via 350a is coupled to its respective via 352a via a corresponding conductive bonding contact 356a. In some configurations, vias 350a and 352a can be through-silicon vias (TSVs). The structures of the bonding layers 334a, 336a, 338a, 340a, and 342a will be described in more detail with reference to Figures 3B and 3C.

[0162] In some implementations, the base die 344a includes a control circuit configured to control the memory dies 302a to 308a. The control circuit can be coupled to the memory dies 302a to 308a, for example, via contact structures 326a to 332a, the interconnection layer of the memory die 302a, and the conductive junction contact 354a.

[0163] The interposer 348a has a surface 358a and a surface 360a. Surface 358a can be bonded to the computing die 346a. Conductive terminals 362a can be connected to surface 360a. The interposer 348a may include interconnection lines connecting vias 352a of the computing device 346a to conductive terminals 362a. Conductive terminals 362a can be connected to an external device (e.g., the external host die 112 in Figure 1). In some implementations, conductive terminals 362a can be microbumps.

[0164] In some implementation configurations, as shown in Figure 3A, the thickness of the memory dies 302a to 306a can be reduced (along the Z direction) by thinning their substrates. The topmost memory die 308a (for example, the one of the memory dies 302a to 308a furthest from the base die 344a) does not need to be thinned. This allows the thickness of each of the memory dies 302a to 306a to be smaller than the thickness of memory die 308a. The thickness of each of the memory dies 302a to 308a can be within any suitable range (e.g., 3 μm to 20 μm).

[0165] Figure 3B shows Figure 300b, which shows an enlarged view of the bonding layer 334a of Figure 3A according to some aspects of the present disclosure. The bonding layer 334a may include an upper bonding layer 333b and a lower bonding layer 337b bonded at a bonding interface 335b. Each of the upper bonding layer 333b and the lower bonding layer 337b may contain a dielectric material (including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof) and conductive bonding contacts may be excluded. The memory die 304a can be bonded to the memory die 302a in a face-to-face manner via the bonding layer 334a. The bonding interface 335b is located between the upper bonding layer 333b and the lower bonding layer 337b as a result of a direct bonding (e.g., dielectric-dielectric bonding) that forms a bonding between surfaces without using an intermediate layer such as solder or adhesive. In some implementations, for example, when the dielectric material of the upper bonding layer 333b and the dielectric material of the lower bonding layer 337b are different materials, the bonding interface 335b can be a visible layer with a specific thickness that includes the top surface of the lower bonding layer 337b and the bottom surface of the upper bonding layer 333b. In some implementations, for example, when the dielectric material of the upper bonding layer 333b and the dielectric material of the lower bonding layer 337b are the same material, the bonding interface 335b may be invisible and can form a continuous portion with the upper bonding layer 333b and the lower bonding layer 337b. The bonding layers 336a and 338a in Figure 3A can have a structure similar to the bonding layer 334a described in Figure 3B.

[0166] Figure 3C shows Figure 300c, which shows an enlarged view of the bonding layer 340a of Figure 3A according to several aspects of the present disclosure. The bonding layer 340a may include an upper bonding layer 343c and a lower bonding layer 347c bonded at the bonding interface 345c. The upper bonding layer 343c includes a conductive bonding contact 341c and a dielectric material 339c separating the conductive bonding contact 341c. The conductive bonding contact 341c may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The dielectric material 339c may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. Similarly, the lower bonding layer 347c includes a conductive bonding contact 349c and a dielectric material 351c separating the conductive bonding contact 349c. The conductive bonding contact 349c may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The dielectric material 351c may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0167] The conductive bonding contacts 341c and 349c can be examples of the conductive bonding contact 354a in Figure 3A. The conductive bonding contact 341c is in contact with the conductive bonding contact 349c at the bonding interface 345c. The memory die 302a can be bonded to the base die 344a in a face-to-face manner via the bonding layer 340a. The bonding interface 345c is located between the upper bonding layer 343c and the lower bonding layer 347c as a result of a hybrid bonding (e.g., metal-metal / dielectric-dielectric bonding). Hybrid bonding can form a bonding between surfaces without using an intermediate layer such as solder or adhesive, and can simultaneously obtain metal-metal bonding and dielectric-dielectric bonding. In some mounting configurations, for example, if the dielectric material 339c of the upper bonding layer 343c and the dielectric material 351c of the lower bonding layer 347c are different materials, the bonding interface 345c can be a visible layer with a specific thickness that includes the top surface of the lower bonding layer 347c and the bottom surface of the upper bonding layer 343c. In some implementation configurations, for example, if dielectric material 339c and dielectric material 351c are the same material, the bonding interface 345c may not be visible, and a continuous portion can be formed with the upper bonding layer 343c and the lower bonding layer 347c. The bonding layer 342a in Figure 3A can have a structure similar to the bonding layer 340a described in Figure 3C.

[0168] Figure 3D shows a side view of a semiconductor device 300d according to several aspects of the present disclosure. The semiconductor device 300d includes memory dies 302d-308d, a base die 344d, a computing die 346d, and an interposer 348d. The memory dies 302d-308d and the base die 344d are stacked (e.g., sequentially) along the Z direction. The base die 344d and the computing die 346d are integrated at different positions on the interposer 348d along the X direction. The memory dies 302d-308d are similar to the memory dies 302a-308a in Figure 3A. The memory dies 302d-308d can be examples of memory die 102 in Figure 1 and memory dies 204a-204d in Figure 2A (e.g., DRAM). The stack of memory dies 302d to 308d includes a device region 301d and a connection region 303d adjacent to the device region 301d horizontally (e.g., in the X direction). Each of the memory dies 302d to 308d includes conductive layers 310d to 316d extending horizontally (e.g., in the X direction). Each of the conductive layers 310d to 316d has one end coupled to a memory array or peripheral circuit in the corresponding memory die within the device region 301d, and the other end (e.g., end 318d to 324d) extending away from the device region 301d. Each of the conductive layers 310d to 316d can be coupled to the input / output ports of the corresponding memory die, or can be configured to provide one or more of the following to the corresponding memory die: power, clock signals, or data path signals.

[0169] As shown in Figure 3D, the semiconductor device 300d includes contact structures 326d-332d in the connection region 303d. The contact structures 326d-332d can be examples of the contact structure 210 in Figures 2A-2B. The semiconductor device 300d further includes junction layers between adjacent memory dies among the memory dies 302d-308d (e.g., junction layers 334d, 336d, and 338d) and a junction layer 340d between the memory die 302d and the base die 344d. Each of these junction layers may contain a dielectric material such as silicon oxide.

[0170] Contact structures 326d to 332d extend along the vertical direction (e.g., the Z direction) and are coupled to conductive layers 310d to 316d, respectively. Contact structure 326d extends within memory die 302d and connects to the conductive layer 310d of memory die 302d without penetrating the bonding layer 334d. Contact structure 328d extends within memory die 304d, penetrating memory die 302d and bonding layer 334d without penetrating the bonding layer 336d. Contact structure 328d connects to the conductive layer 310d of memory die 304d without penetrating the conductive layer 312d. Contact structure 330d extends within memory die 306d, penetrating memory dies 302d to 304d and bonding layers 334d and 336d without penetrating the bonding layer 338d. The contact structure 330d is connected to the conductive layer 310d of the memory die 306d without extending through the conductive layers 314d and 312d. The contact structure 332d extends through the memory dies 302d to 306d within the memory die 308d without extending through the memory die 308d. The contact structure 332d is connected to the conductive layer 316d of the memory die 308d without extending through the conductive layers 310d to 314d.

[0171] The conductive layers 310d to 316d can form a stepped structure, allowing each of the contact structures 326d to 332d to connect to one of the conductive layers 310d to 316d without extending through the other conductive layers. In some implementations, as shown in Figure 3D, the conductive layers 310d to 316d can have the same length and be offset along the X direction. In other words, the ends 318d to 324d (e.g., the right end) of the conductive layers 310d to 316d can be offset along the X direction. Specifically, the contact structure 328d is located along the X direction between the end 318d of conductive layer 310d and the end 320d of conductive layer 312d. That is, the end 318d of conductive layer 310d is located along the X direction between the contact structure 326d and the contact structure 328d. In this way, the contact structure 328d extends through the memory die 302d and can bypass the conductive layer 310d of the memory die 302d. Similarly, the contact structure 330d is located along the X direction between the end 320d of the conductive layer 312d and the end 322d of the conductive layer 314d, and as a result, the contact structure 330d extends through the memory dies 302d to 304d and can bypass the conductive layers 310d to 312d. Furthermore, the contact structure 332d is located along the X direction between the end 322d of the conductive layer 314d and the end 324d of the conductive layer 316d, and as a result, the contact structure 332d extends through the memory dies 302d to 306d and can bypass the conductive layers 310d to 314d.

[0172] In some implementations, junction layers 334d, 336d, and 338d can be called direct junction layers and may have a structure similar to that of junction layer 334a described in Figure 3B. Each of junction layers 334d, 336d, and 338d may include at least one dielectric material and exclude conductive junction contacts. In some implementations, junction layer 340d can be called a hybrid junction layer and may have a structure similar to that of junction layer 340a described in Figure 3C. Junction layer 340d may include junction contacts (e.g., conductive junction contacts 354d as shown in Figure 3D) and at least one dielectric material separating the junction contacts. The conductive junction contacts 354d may be configured to connect the memory die 302d and the base die 344d. In some implementations, the memory die 302d may include an interconnection layer (not shown in Figure 3D) that contacts junction layer 340d. The interconnection layer of the memory die 302d has a structure similar to the interconnection layer 345f described in Figure 3F. Each of the contact structures 326d to 332d can be coupled to the interconnection layer of the memory die 302d. The interconnection layer of the memory die 302d can be coupled to the base die 344d via conductive bonding contacts 354d within the bonding layer 340d. The base die 344d includes vias 350d that extend through the base die 344d along the Z direction and are connected to the conductive bonding contacts 354d. Each of the contact structures 326d to 332d is coupled to each of the vias 350d via the corresponding conductive bonding contacts 354d. In some implementation configurations, the vias 350d can be TSVs.

[0173] In some implementations, the base die 344d includes a control circuit configured to control the memory dies 302d-308d. The control circuit can be coupled to the memory dies 302d-308d, for example, via contact structures 326d-332d, the interconnection layer of the memory die 302d, and conductive junction contacts 354d.

[0174] The base die 344d can be coupled to the computing die 346d via the interposer 348d. The interposer 348d has a surface 358d and a surface 360d. Vias 350d in the base die 344d can be connected to conductive terminals 364d on surface 358d of the interposer 348d. The computing die 346d can be connected to conductive terminals 366d on surface 358d of the interposer 348d. The semiconductor device 300d may include conductive terminals 362d connected to surface 360d of the interposer 348d. Conductive terminals 364d, 366d, and 362d can be coupled via conductive wires in the interposer 348d (e.g., conductive wire 369d as shown in Figure 3D). Conductive terminal 362d can be coupled to an external device (e.g., an external host die 112 in Figure 1). In some implementation configurations, the conductive terminals 364d, 366d, and 362d can be microbumps. In practice, it is understood that the base die 344d, the computing die 346d, and the interposer 348d can be integrated using any suitable packaging technique, including, for example, Chip-on-Wafer-on-Substrate (CoWoS).

[0175] In some implementation configurations, as shown in Figure 3D, the thickness of the memory dies 302d to 306d can be reduced (along the Z direction) by thinning their substrates. The top memory die 308d (for example, the memory die 302d to 308d furthest from the base die 344d) does not need to be thinned. This allows the thickness of each of the memory dies 302d to 306d to be smaller than the thickness of memory die 308d. The thickness of each of the memory dies 302d to 308d can be within any suitable range (e.g., 3 μm to 20 μm).

[0176] Figure 3E shows a side view of a semiconductor device 300e according to several aspects of the present disclosure. The semiconductor device 300e includes memory dies 302e-308e stacked (e.g., sequentially) along a vertical direction (e.g., Z direction), a base die 344e, a computing die 346e, and an interposer 348e. The memory dies 302e-308e are similar to the memory dies 302a-308a in Figure 3A. The memory dies 302e-308e can be examples of memory die 102 in Figure 1 and memory dies 204a-204d in Figure 2A (e.g., DRAM). The stack of memory dies 302e-308e includes a device region 301e and a connection region 303e adjacent to the device region 301e along a horizontal direction (e.g., X direction). Each of the memory dies 302e to 308e includes conductive layers 310e to 316e extending horizontally (e.g., in the X direction). Each of the conductive layers 310e to 316e has one end coupled to a memory array or peripheral circuit in the corresponding memory die within the device region 301e, and the other end (e.g., ends 318e to 324e) extending away from the device region 301e. Each of the conductive layers 310e to 316e can be coupled to the input / output ports of the corresponding memory die, or can be configured to provide one or more of the following to the corresponding memory die: power, clock signals, or data path signals.

[0177] As shown in Figure 3E, the semiconductor device 300e includes contact structures 326e-332e in the connection region 303e. Contact structures 326e-332e can be examples of contact structure 210 in Figures 2A-2B. The semiconductor device 300e further includes junction layers between adjacent memory dies among memory dies 302e-308e (e.g., junction layers 334e, 336e, and 338e) and a junction layer 340e between memory die 302e and base die 344e. Each of these junction layers may contain the dielectric material silicon oxide. The base die 344e includes a surface 365e and another surface 367e. Surface 365e is bonded to memory die 302e via junction layer 340e. The base die 344e further includes a conductive layer 368e and a contact structure 370e connected to the conductive layer 368e. The contact structure 370e extends into the base die 344e along the Z direction. The conductive layer 368e includes an end 372e coupled to the circuit of the base die 344e and the other end 374e closer to the contact structure 370e. In some configurations, the junction layers 334e, 336e, 338e, and 340e can be called direct junction layers and may have a structure similar to that of junction layer 334a described in Figure 3B. Each of the junction layers 334e, 336e, 338e, and 340e may include at least one dielectric material and exclude conductive junction contacts. In some configurations, the junction layer 342e can be called a hybrid junction layer and may have a structure similar to that of junction layer 340a described in Figure 3C. The junction layer 342e may include a junction contact (e.g., a conductive junction contact 356e as shown in Figure 3E) and at least one dielectric material separating the junction contact.

[0178] Contact structures 370e and 326e-332e extend along the vertical direction (e.g., the Z direction) and are coupled to conductive layers 368e and 310e-316e, respectively. Specifically, contact structure 370e extends into the base die 344e without penetrating the bonding layer 340e. Contact structure 326e extends into the memory die 302e by penetrating the bonding layer 340e without penetrating the bonding layer 334e. Contact structure 326e is connected to the conductive layer 368e of the memory die 302e without penetrating the conductive layer 310e. Contact structure 328e extends into the memory die 304e by penetrating the memory die 302e and bonding layers 340e and 334e without penetrating the bonding layer 336e. The contact structure 328e is connected to the conductive layer 312e of the memory die 304e without extending through the conductive layers 368e and 310e. The contact structure 330e extends into the memory die 306e, penetrating the memory dies 302e to 304e and the bonding layers 340e, 334e, and 336e, without extending through the bonding layer 338e. The contact structure 330e is connected to the conductive layer 314e of the memory die 306e without extending through the conductive layers 368e, 310e, and 312e. The contact structure 332e extends into the memory die 308e, penetrating the memory dies 302e to 306e and the bonding layers 340e, 334e, 336e, and 338e, without extending through the memory die 308e. The contact structure 332e is connected to the conductive layer 316e of the memory die 308e without extending through the conductive layers 368e, 310e, 312e, and 314e.

[0179] The conductive layers 368e and 310e-316e can form a stepped structure, allowing each of the contact structures 370e and 326e-332e to connect to one of the conductive layers 368e and 310e-316e without penetrating the other conductive layers. In some configurations, as shown in Figure 3E, the conductive layers 368e and 310e-316e are offset along the X direction. In some configurations, the conductive layers 310e-316e can have the same length. Specifically, the ends 374e and 318e-324e (e.g., the right end) of the conductive layers 368e and 310e-316e can be offset along the X direction. The contact structure 326e is located along the X direction between the end 374e of conductive layer 368e and the end 318e of conductive layer 310e. In other words, the end 374e of the conductive layer 368e is located between the contact structure 370e and the contact structure 326e along the X direction. In this way, the contact structure 326e can extend through the base die 344e and bypass the conductive layer 368e of the base die 344e. The contact structure 328e is located between the end 318e of the conductive layer 310e and the end 320e of the conductive layer 312e along the X direction. In other words, the end 318e of the conductive layer 310e is located between the contact structure 326e and the contact structure 328e along the X direction. In this way, the contact structure 328e can extend through the memory die 302e and bypass the conductive layer 310e of the memory die 302e. Similarly, the contact structure 330e is located along the X direction between the end 320e of the conductive layer 312e and the end 322e of the conductive layer 314e, and as a result, the contact structure 330e extends through the memory dies 302e to 304e and can bypass the conductive layers 310e to 312e. Furthermore, the contact structure 332e is located along the X direction between the end 322e of the conductive layer 314e and the end 324e of the conductive layer 316e, and as a result, the contact structure 332e extends through the memory dies 302e to 306e and can bypass the conductive layers 310e to 314e.

[0180] The base die 344e may include an interconnection layer (not shown in Figure 3E) that contacts the bonding layer 342e. Each of the contact structures 326e-332e and 370e can be coupled to the interconnection layer of the base die 344e. An example of the interconnection layer of the base die 344e is described in more detail later with reference to Figure 3F. The interconnection layer of the base die 344e can be coupled to the computing die 346e via conductive bonding contacts 356e within the bonding layer 342e. The conductive bonding contacts 356e can be configured to couple the base die 344e and the memory dies 302e-308e to the computing die 346e. The computing die 346e may be an example of the computing die 108 in Figure 1. The computing die 346e includes vias 352e that penetrate the computing die 346e and extend along the Z direction, connected to the conductive bonding contacts 356e. Each of the contact structures 370e and 326e-332e can be coupled to one of the vias 352e via the interconnection layer of the base die 344e and the corresponding conductive bonding contact 356e. In some implementations, the vias 352e can be TSVs.

[0181] In some implementations, the base die 344e includes a control circuit configured to control the memory dies 302e-308e. The control circuit can be coupled to the memory dies 302e-308e, for example, via contact structures 370e and 326e-332e, the interconnection layer of the base die 344e, and conductive junction contacts 356e.

[0182] The interposer 348e has surfaces 358e and 360e. Surface 358e can be bonded to the computing die 346e. Conductive terminals 362e can be connected to surface 360e. The interposer 348e may include interconnection lines connecting vias 352e of the computing die 346e to conductive terminals 362e. Conductive terminals 362e can be coupled to an external device (e.g., the external host die 112 in Figure 1). In some implementations, conductive terminals 362e can be microbumps.

[0183] In some implementation configurations, as shown in Figure 3E, the thickness of the memory dies 302e to 306e can be reduced (along the Z direction) by thinning their substrates. The topmost memory die 308e (for example, the memory die 302e to 308e furthest from the base die 344e) does not need to be thinned. This allows the thickness of the memory dies 302e to 306e to be thinner than the thickness of memory die 308e. The thickness of each of the memory dies 302e to 308e can be any suitable range (e.g., 3 μm to 20 μm).

[0184] Figure 3F shows Figure 300f, which shows an enlarged view of the interconnection layer 345f within the base die 344e of Figure 3E, according to some aspects of the present disclosure. The interconnection layer 345f is located between the contact structures 326e-332e and 370e and the bonding layer 342e along the Z direction. The interconnection layer 345f may include interconnections (also referred to herein as “contacts”), including lateral interconnection lines 347f and vertical interconnection access (VIA) contacts (not shown). The contact structures 326e-332e and 370e of the bonding layer 342e and the conductive bonding contact 356e can be coupled to interconnections within the interconnection layer 345f. As used herein, the term “interconnection” can broadly include any suitable type of interconnection, such as middle end-of-line (MEOL) interconnections and back-end-of-line (BEOL) interconnections. The interconnection layer 345f may further include one or more interlayer insulating (ILD) layers (also known as “intermetallic dielectric (IMD) layers”) on which interconnection lines 347f and via contacts can be formed. That is, the interconnection layer 345f may include interconnection lines 347e and via contacts within a plurality of ILD layers. The interconnection lines 347f and via contacts within the interconnection layer 345f may include, but are not limited to, conductive materials such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers within the interconnection layer 345f may include, but are not limited to, dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0185] Figure 3G shows a side view of a semiconductor device 300g according to several embodiments of the present disclosure. The semiconductor device 300g includes memory dies 302g to 308g, a base die 344g, a computing die 346g, and an interposer 348g. The memory dies 302g to 308g and the base die 344g are stacked sequentially along the Z direction. The base die 344g and the computing die 346g are integrated at different positions on the interposer 348g along the X direction. The memory dies 302g to 308g are similar to the memory dies 302a to 308a in Figure 3A. The memory dies 302g to 308g can be examples of memory die 102 in Figure 1 and memory dies 204a to 204d in Figure 2A (e.g., DRAM). The stack of memory devices 302g to 308g includes a device region 301g and a connection region 303g adjacent to the device region 301g in a horizontal direction (e.g., the X direction). Each of the memory dies 302g to 308g includes conductive layers 310g to 316g extending horizontally (e.g., the X direction). Each of the conductive layers 310g to 316g has one end coupled to a memory array or peripheral circuit in the corresponding memory die within the device region 301g, and the other end (e.g., end 318g to 324g) extending away from the device region 301g. Each of the conductive layers 310g to 316g can be coupled to the input / output ports of the corresponding memory die, or can be configured to provide one or more of the following to the corresponding memory die: power, clock signals, or data path signals.

[0186] As shown in Figure 3G, the semiconductor device 300g includes contact structures 326g to 332g in the connection region 303g. Contact structures 326g to 332g can be examples of contact structure 210 in Figures 2A to 2B. The semiconductor device 300g further comprises junction layers between adjacent memory dies from memory dies 302g to 308g (e.g., junction layers 334g, 336g, and 338g) and a junction layer 340g between memory die 302g and base die 344g. Each of these junction layers may contain silicon oxide. The base die 344g includes a surface 365g and another surface 367g. Surface 365g is bonded to memory die 302g via junction layer 340g. The base die 344g further includes a conductive layer 368g and a contact structure 370g connected to the conductive layer 368g. The contact structure 370g extends into the base die 344g along the Z direction. The conductive layer 368g includes an end 372g coupled to the circuit of the base die 344g and the other end 374g closer to the contact structure 370g. In some mounting configurations, the junction layers 334g, 336g, 338g, and 340g can be called direct junction layers and may have a structure similar to that of junction layer 334a described in Figure 3B. Each of the junction layers 334g, 336g, 338g, and 340g may contain at least one dielectric material and exclude conductive junction contacts.

[0187] Contact structures 370g and 326g-332g extend along the vertical direction (e.g., the Z direction) and are coupled to conductive layers 368g and 310g-316g, respectively. Specifically, contact structure 370g extends within the base die 344g without penetrating the bonding layer 340g. Contact structure 326g extends within the memory die 302g by penetrating the bonding layer 334g without penetrating the bonding layer 340g. Contact structure 326g is connected to the conductive layer 368g of the memory die 302g without penetrating the conductive layer 310g. Contact structure 328g extends within the memory die 304g by penetrating the memory die 302g and bonding layers 340g and 334g without penetrating the bonding layer 336g. The contact structure 328g is connected to the conductive layer 312g of the memory die 304g without extending through the conductive layers 368g and 310g. The contact structure 330g extends into the memory die 306g, penetrating the memory dies 302g to 304g and the bonding layers 340g, 334g, and 336g, without extending through the bonding layer 338g. The contact structure 330g is connected to the conductive layer 368g of the memory die 306g without extending through the conductive layers 314g, 310g, and 312g. The contact structure 332g extends into the memory die 308g, penetrating the memory dies 302g to 306g and the bonding layers 340g, 334g, 336g, and 338g, without extending through the memory die 308g. The contact structure 332g is connected to the conductive layer 368g of the memory die 308g without extending through the conductive layers 316g, 310g, 312g, and 314g.

[0188] The conductive layers 368g and 310g-316g can form a stepped structure, allowing each of the contact structures 370g and 326g-332g to connect to one of the conductive layers 368g and 310g-316g without penetrating the other conductive layers. In some configurations, as shown in Figure 3G, the conductive layers 368g and 310g-316g are offset along the X direction. In some configurations, the conductive layers 310g-316g can have the same length. Specifically, the ends 374g and 318g-324g (e.g., the right end) of the conductive layers 368g and 310g-316g can be offset along the X direction. The contact structure 326g is located along the X direction between the end 374g of conductive layer 368g and the end 318g of conductive layer 310g. In other words, the end 374g of the conductive layer 368g lies between the contact structure 370g and the contact structure 326g along the X direction. In this way, the contact structure 326g extends through the base die 344g and can bypass the conductive layer 368g of the base die 344g. The contact structure 328g lies between the end 318g of the conductive layer 310g and the end 320g of the conductive layer 312g along the X direction. In other words, the end 318g of the conductive layer 310g lies between the contact structure 326g and the contact structure 328g along the X direction. In this way, the contact structure 328g lies through the memory die 302g and can bypass the conductive layer 310g of the memory die 302g. Similarly, the contact structure 330g is located along the X direction between the end 320g of conductive layer 312g and the end 322g of conductive layer 314g, and as a result, the contact structure 330g extends through the memory dies 302g to 304g and can bypass the conductive layers 310g to 312g. Furthermore, the contact structure 332g is located along the X direction between the end 322g of conductive layer 314g and the end 324g of conductive layer 316g, and as a result, the contact structure 332g extends through the memory dies 302g to 306g and can bypass the conductive layers 310g to 314g.

[0189] The base die 344g may include an interconnection layer (not shown in Figure 3G). The interconnection layer of the base die 344g has a structure similar to the interconnection layer 345f described in Figure 3F. Each of the contact structures 326g-332g and 370g can be coupled to the interconnection layer of the base die 344g. The base die 344g can be coupled to the computing die 346g via the interconnection layer and the interposer 348g. The interposer 348g has a surface 358g and a surface 360g. The interconnection in the interconnection layer of the base die 344g can be connected to the conductive terminal 364g on the surface 358g of the interposer 348g. The computing die 346g can be connected to the conductive terminal 366g on the surface 358g of the interposer 348g. The semiconductor device 300g may include a conductive terminal 362g connected to the surface 360g of the interposer 348g. Conductive terminals 364g, 366g, and 362g can be coupled via conductive wires within the interposer 348g (e.g., conductive wire 369g as shown in Figure 3G). Conductive terminal 362g can be coupled to an external device (e.g., the external host die 112 in Figure 1). In some implementations, conductive terminals 364g, 366g, and 362g can be microbumps. In practice, it is understood that the base die 344g, the computing die 346g, and the interposer 348g can be integrated using any suitable packaging technique, including, for example, Chip-on-Wafer-on-Substrate (CoWoS).

[0190] In some implementations, the base die 344g includes a control circuit configured to control the memory dies 302g to 308g. The control circuit can be coupled to the memory dies 302g to 308g, for example, via the interconnection layers of the contact structures 370g and 326g to 332g and the base die 344g.

[0191] In some implementation configurations, as shown in Figure 3G, the thickness of memory dies 302g to 306g can be reduced (along the Z direction) by thinning the substrate. The top memory die 308g (for example, the one of memory dies 302g to 308g furthest from the base die 344g) does not need to be thinned. This allows the thickness of memory dies 302g to 306g to be thinner than the thickness of memory die 308g. The thickness of each of the memory dies 302g to 308g can be any suitable range (e.g., 3μm to 20μm).

[0192] Figure 3H shows a side view of a semiconductor device 300h according to several embodiments of the present disclosure. The semiconductor device 300h includes memory dies 302h-308h, a base die 344h, a computing die 346h, and an interposer 348h. The memory dies 302h-308h and the base die 344h are stacked sequentially along the Z direction. The base die 344h and the computing die 346h are integrated at different positions on the interposer 348h along the X direction. The memory dies 302h-308h are similar to the memory dies 302a-308a in Figure 3A. The memory dies 302h-308h can be examples of memory die 102 in Figure 1 and memory dies 204a-204d in Figure 2A (e.g., DRAM). The stack of memory devices 302h to 308h includes a device region 301h and a connection region 303h adjacent to the device region 301h horizontally (e.g., in the X direction). Each of the memory dies 302h to 308h includes conductive layers 310h to 316h extending horizontally (e.g., in the X direction). Each of the conductive layers 310h to 316h can be coupled (e.g., via one of its ends) to a memory array or peripheral circuit in the corresponding memory die within the device region 301h. In some implementations, each of the conductive layers 310h to 316h can be coupled to the input / output ports of the corresponding memory die, or can be configured to provide one or more of the following to the corresponding memory die: power, clock signals, or data path signals.

[0193] As shown in Figure 3H, the semiconductor device 300h has contact structures 326h to 332h in the connection region 303h. The contact structures 326h to 332h can be examples of the contact structure 210 in Figures 2A to 2B. The semiconductor device 300h further includes junction layers between adjacent memory dies among the memory dies 302h to 308h (e.g., junction layers 334h, 336h, and 338h) and a junction layer 340h between the memory die 302h and the base die 344h. Each of these junction layers may contain silicon oxide. The base die 344h has a surface 365h and another surface 367h. Surface 365h is bonded to the memory die 302h via the junction layer 340h. The base die 344h further includes a conductive layer 368h and a contact structure 370h connected to the conductive layer 368h. The contact structure 370h extends into the base die 344h along the Z direction. The conductive layer 368h includes an end 372h coupled to the circuit of the base die 344h and the other end 374h closer to the contact structure 370h. In some mounting configurations, the junction layers 334h, 336h, 338h, and 340h can be called direct junction layers and may have a structure similar to that of junction layer 334a described in Figure 3B. Each of the junction layers 334h, 336h, 338h, and 340h may contain at least one dielectric material and exclude conductive junction contacts.

[0194] Contact structures 370h and 326h-332h extend along the vertical direction (e.g., the Z direction) and are coupled to conductive layers 368h and 310h-316h, respectively. Specifically, contact structure 370h extends within the base die 344h without penetrating the bonding layer 340h. Contact structure 326h extends within the memory die 304h, penetrating the memory die 302h and bonding layers 340h and 334h, without penetrating the bonding layer 336h. Contact structure 326h is connected to conductive layer 312h of memory die 304h without penetrating the conductive layers 310h, 314h, 316h, and 368h. The contact structure 328h extends within the memory die 308h, penetrating the memory dies 302h to 306h and the bonding layers 340h, 334h, 336h, and 338h, without penetrating the memory die 308h. The contact structure 328h connects to the conductive layer 316h of the memory die 308h without penetrating the conductive layers 310h, 312h, 314h, and 368h. The contact structure 330h extends within the memory die 306h, penetrating the memory dies 302h to 304h and the bonding layers 340h, 334h, and 336h, but without penetrating the bonding layer 338h. The contact structure 330h connects to the conductive layer 314h of the memory die 306h without penetrating the conductive layers 310h, 312h, 316h, and 368h. The contact structure 332h extends into the memory die 302h by penetrating the bonding layer 340h, without penetrating the bonding layer 334h. The contact structure 332h is connected to the conductive layer 310h of the memory die 302h without penetrating the conductive layers 312h, 314h, 316h, and 368h.

[0195] As shown in Figure 3H, conductive layers 368h and 310h-316h form a different structure from the stepped structure in some other figures (e.g., Figures 3A, 3D, 3E, and 3G), although each of the contact structures 370h and 326h-332h can still connect to one of the conductive layers 368h and 310h-316h without extending through other conductive layers. In some implementations, as shown in Figure 3H, conductive layers 368h and 310h-316h are offset along the X direction. In some implementations, conductive layers 310h-316h have the same length, and their ends can be offset along the X direction. Specifically, contact structure 326h is located along the X direction between the end 374h of conductive layer 368h and the end 318h of conductive layer 312h. The contact structure 328h is located along the X direction between the end 318h of the conductive layer 312h and the end 320h of the conductive layer 314h. The contact structure 330h is located along the X direction between the end 320h of the conductive layer 314h and the end 322h of the conductive layer 310h. The end 322h is located along the X direction between the contact structure 330h and the contact structure 332h.

[0196] The base die 344h may include an interconnection layer (not shown in Figure 3H). The interconnection layer of the base die 344h has a structure similar to the interconnection layer 345f described in Figure 3F. Each of the contact structures 326h-332h and 370h can be coupled to the interconnection layer of the base die 344h. The base die 344h can be coupled to the computing die 346h via the interconnection layer and the interposer 348h. The interposer 348h has surfaces 358h and 360h. The interconnection in the interconnection layer of the base die 344h can be connected to conductive terminals 364h on surface 358h of the interposer 348h. The computing die 346h can be connected to conductive terminals 366h on surface 358h of the interposer 348h. The semiconductor device 300h may include conductive terminals 362h connected to surface 360h of the interposer 348h. Conductive terminals 364h, 366h, and 362h can be coupled via conductive wires within the interposer 348h (e.g., conductive wire 369h as shown in Figure 3H). Conductive terminal 362h can be coupled to an external device (e.g., the external host die 112 in Figure 1). In some implementations, conductive terminals 364h, 366h, and 362h can be microbumps. In practice, it is understood that the base die 344h, the computing die 346h, and the interposer 348h can be integrated using any suitable packaging technique, including, for example, Chip-on-Wafer-on-Substrate (CoWoS).

[0197] In some implementations, the base die 344h includes a control circuit configured to control the memory dies 302h to 308h. The control circuit can be coupled to the memory dies 302h to 308h, for example, via the contact structures 370h and 326h to 332h and the interconnection layer of the base die 344h.

[0198] In some implementation configurations, as shown in Figure 3H, the thickness of memory dies 302h to 306h can be reduced (along the Z direction) by thinning the substrate. The topmost memory die 308h (for example, the memory die 302h to 308h furthest from the base die 344h) does not need to be thinned. This allows the thickness of memory dies 302h to 306h to be thinner than the thickness of memory die 308h. The thickness of each of the memory dies 302h to 308h can be within any suitable range (e.g., 3 μm to 20 μm).

[0199] Figures 4A to 4J illustrate typical processes for manufacturing semiconductor devices according to several aspects of this disclosure. In some implementation configurations, any suitable semiconductor device, such as semiconductor device 200, 300a, or 300d, can be manufactured using the processes described herein.

[0200] Figure 4A shows that the process can begin by providing semiconductor structures 400 and 402, both extending horizontally (e.g., along the X-direction). Semiconductor structure 400 can be a carrier wafer. Semiconductor structure 402 can be a semiconductor device or semiconductor die (e.g., memory die 204a in Figure 2C or memory die 302a in Figure 3A) including a conductive layer 410 (e.g., conductive layer 310a in Figure 3A). Semiconductor structure 402 can be stacked on semiconductor structure 400 along the vertical direction (e.g., along the Z-direction) and bonded to semiconductor structure 400 via a junction layer 401. Semiconductor structures 400 and 402 can be bonded using any suitable bonding technique (e.g., direct bonding technique). For example, a first dielectric layer (e.g., silicon oxide) can be deposited on the surface 403 of semiconductor structure 400, and a second dielectric layer (e.g., silicon oxide) can be deposited on the surface 405 of semiconductor structure 402. By applying pressure and heat, the first dielectric layer and the second dielectric layer can be joined together to form a junction layer 401 between semiconductor structures 400 and 402. Semiconductor structure 400 can function as a support for semiconductor structure 402. Semiconductor structures 400 and 402 can have any suitable thickness along the Z direction. In some mounting configurations, the thickness of semiconductor structure 402 can be in the range of 40 μm to 50 μm.

[0201] As shown in Figure 4B, the semiconductor structure 402 is thinned. Thinning the semiconductor structure 402 involves removing the top of the semiconductor structure 402 (for example, the part furthest from the semiconductor structure 400 along the Z direction). For example, the thickness of the semiconductor structure 402 can be thinned from about 40-50 μm to 3-20 μm. In some packaging configurations, the semiconductor structure 402 includes a substrate at its bottom and is inverted before being bonded to the semiconductor structure 400. That is, the substrate of the semiconductor structure 402 becomes the top of the semiconductor structure 402 after inversion. Therefore, by thinning the top of the semiconductor structure 402, a portion of the substrate of the semiconductor structure 402 is removed. In some packaging configurations, after thinning, the semiconductor structure 402 can still maintain its shape without substantial strain or deformation due to the support provided by the semiconductor structure 400 (e.g., the carrier wafer).

[0202] As shown in Figure 4C, a semiconductor structure 404 is provided. The semiconductor structure 404 (e.g., memory die 304a in Figure 3A) includes a conductive layer 412 (e.g., conductive layer 312a in Figure 3A). In some mounting configurations, the semiconductor structure 404 includes a substrate on top of it, similar to the semiconductor structure 402 described with respect to Figure 4B. The semiconductor structure 404 can be aligned with the semiconductor structure 402 such that the edges 420 of the conductive layer 412 and the edges 418 of the conductive layer 410 are offset along the X direction. In this way, the conductive layers 412 and 410 can form a stepped structure (e.g., a stepped structure as described with respect to Figures 2C and 3A-3D), and as a result, a contact structure formed in a later step can be connected to the conductive layer 412 without extending through the conductive layer 410. A dielectric layer can be deposited on the bottom surface of the semiconductor structure 404, and a dielectric layer can be deposited on the top surface of the semiconductor structure 402. The semiconductor structure 404 can be stacked and bonded to the semiconductor structure 402 along the Z direction, similar to the example where the semiconductor structure 402 and the semiconductor structure 400 are bonded, as described with respect to Figure 4A.

[0203] As shown in Figure 4D, the dielectric layer of semiconductor structure 404 and the dielectric layer of semiconductor structure 402 can form a junction layer 407. Semiconductor structure 404 is thinned by removing the top (for example, a portion of the substrate of semiconductor structure 404).

[0204] Figure 4E shows that the semiconductor structure comprises a semiconductor structure 406 (e.g., memory die 306a in Figure 3A) including a conductive layer 414 (e.g., conductive layer 314a in Figure 3A) and a semiconductor structure 408 (e.g., memory die 308a in Figure 3A) including a conductive layer 416 (e.g., conductive layer 316a in Figure 3A). The semiconductor structure 406 is aligned, stacked, and bonded with the semiconductor structure 404 in a manner similar to the examples described with reference to Figures 4A to 4D. The semiconductor structure 406 can also be thinned. Similarly, the semiconductor structure 408 is aligned, stacked, and bonded with the semiconductor structure 406. In some mounting configurations, the semiconductor structure 408 is not thinned, thereby providing support due to its thickness when the stack of semiconductor structures 404 to 408 is inverted in a later step. The conductive layers 410 to 416 can form a stepped structure as described with reference to Figures 2C, 3A, and 3D. In some implementation configurations, the conductive layers 410-416 can have varying lengths. For example, as shown in Figure 4E, the conductive layers 410-416 can extend in the X direction from substantially the same position (e.g., the right side) and extend for different lengths (e.g., toward the left side). In other words, the ends 418-424 of the conductive layers 410-416 are offset along the X direction. In some implementation configurations, the semiconductor structures 404-408 are labeled based on the position and length of the conductive layers 410-416. The semiconductor structures 404-408 can be stacked in the correct order based on their labels.

[0205] In this example, the semiconductor device may include four semiconductor structures 402-408 stacked on top of each other, but the techniques disclosed herein can be applied to stack any suitable number of semiconductor structures (e.g., 2, 5, or 8). The number of semiconductor structures can be determined based on factors including technical constraints, thermal considerations, signal integrity and interference, physical size and application, cost and yield, and reliability concerns. In these cases, the last semiconductor structure furthest from semiconductor structure 400 (not the fourth, as shown in Figure 4E) can be made thicker along the Z direction than the other semiconductor structures. For example, the last semiconductor structure is not made thinner, while the other semiconductor structures are. In this way, the last semiconductor structure can provide support due to its thickness when the stacked structure is inverted in a later step.

[0206] As shown in Figure 4F, semiconductor structure 400 can be removed by a delamination process. The stack of semiconductor structures 402-408 is inverted. As it is the thickest of the semiconductor structures 402-408, semiconductor structure 408 is at the bottom here, supporting the other semiconductor structures.

[0207] Figure 4G shows that a mask layer 411 is formed on the semiconductor structure 402. The mask layer 411 has openings 413, 415, 417, and 419. In some packaging configurations, the mask layer 411 contains a photoresist material, and the openings 413, 415, 417, and 419 can be formed by etching the mask layer 411. The positions of the openings 413, 415, 417, and 419 can be determined such that each contact hole extending along the Z direction (e.g., contact holes 425, 427, 429, and 431 in Figure 4H) can extend from one of the openings 413, 415, 417, and 419 to the corresponding one of the conductive layers 410-416 without extending through the other of the conductive layers 410-416.

[0208] Figure 4H shows that contact holes 425, 427, 429, and 431 are formed extending within semiconductor structures 402-408 along the Z direction. Contact hole 425 extends within semiconductor structure 402 and reaches the conductive layer 410. Contact hole 427 penetrates semiconductor structure 402 and extends within semiconductor structure 404 and reaches the conductive layer 412. Contact hole 429 penetrates semiconductor structures 402 and 404 and extends within semiconductor structure 406 and reaches the conductive layer 414. Contact hole 431 penetrates semiconductor structures 402, 404, and 406 and extends within semiconductor structure 408 and reaches the conductive layer 416. In some mounting configurations, contact holes 425, 427, 429, and 431 can be formed by etching away one or more dielectric materials within semiconductor structures 402-408 through openings 413, 415, 417, and 419. The stepped structure formed by the conductive layers 410-416 allows each of the contact holes 425, 427, 429, and 431 to connect to one of the semiconductor structures 402-408 and bypass the other. Specifically, contact hole 427 is located between the end 418 of conductive layer 410 and the end 420 of conductive layer 412, contact hole 429 is located between the end 420 of conductive layer 412 and the end 422 of conductive layer 414, and contact hole 431 is located between the end 422 of conductive layer 414 and the end 424 of conductive layer 416. Removal of the mask layer 411 can be performed, for example, using chemical mechanical planarization (CMP) after the contact holes 425, 427, 429, and 431 have been formed. In some configurations, the contact holes 425, 427, 429, and 431 are formed during the same etching process.

[0209] Figure 4I shows that contact structures 426, 428, 430, and 432 are formed in contact holes 425, 427, 429, and 431. Each of the contact structures 426, 428, 430, and 432 may include an outer layer (e.g., outer layer 433) and an inner layer (e.g., inner layer 435) on the inner surface of the outer layer 433. The inner layer may contain a conductive material (e.g., copper or tungsten) and may be called a conductive structure. The outer layer may contain an insulating material (dielectric material such as silicon oxide) and may be called an insulating layer. The contact structures 426, 428, 430, and 432 can be formed by first depositing a dielectric material into the contact holes 425, 427, 429, and 431 to form an insulating layer on the inner surface of the contact holes 425, 427, 429, and 431. Subsequently, the bottom of the insulating layer can be etched away to expose the conductive layers 410, 412, 414, and 416 within the contact holes 425, 427, 429, and 431. Then, by depositing conductive material into the contact holes 425, 427, 429, and 431, the inner layers of the contact structures 426, 428, 430, and 432 can be formed. In some mounting configurations, after deposition, excess material such as metal and dielectric can be polished using CMP, leaving a flat surface with metal within the contact holes.

[0210] Figure 4J shows that semiconductor structure 444 is stacked and bonded on semiconductor structure 402. Semiconductor structure 444 can be a base die (e.g., base die 212 in Figure 2A, base die 344a in Figure 3A, or base die 344d in Figure 3D). Semiconductor structure 444 includes vias 450 extending along the Z direction. Semiconductor structure 444 can be bonded to semiconductor structure 402 using any suitable bonding technique. In some implementations, semiconductor structure 444 and semiconductor structure 402 can be bonded via conductive bonding contacts and dielectric material. Specifically, a bonding layer 443 can be formed on the upper surface of semiconductor structure 402. The bonding layer 443 may include conductive bonding contacts 442 and dielectric material separating the conductive bonding contacts 442. Contact structures 426, 428, 430, and 432 are connected to the corresponding bonding contacts of the conductive bonding contacts 442. In some implementations, an interconnection layer is formed within the semiconductor structure 402 before the junction layer 443 is formed. The interconnection layer can be coupled to contact structures 426, 428, 430, and 432. A junction layer 445 can be formed on the bottom surface of the semiconductor structure 444. The junction layer 445 may include conductive junction contacts 446 and a dielectric material separating the conductive junction contacts 446. The conductive junction contacts 446 are connected to vias 450 of the semiconductor structure 444. Conductive junction contacts 442 and 446 may include the same conductive material, such as a metal (e.g., copper). Junction layers 443 and 445 may include the same dielectric material (e.g., silicon oxide). The semiconductor structure 444 is stacked on the semiconductor structure 402 such that the junction layer 445 is in contact with the junction layer 443 and each conductive junction contact 446 is in contact with the corresponding conductive junction contact 442. By applying pressure and heat, the bonding layer 445 is bonded to the bonding layer 443.

[0211] In some implementations, the process described with reference to Figures 4A to 4J can be modified to form a semiconductor device having a contact structure that extends through the semiconductor structure 444 (for example, a stack of memory dies and base dies as described with reference to Figures 3E, 3G, and 3H). For example, before forming the mask layer 411 on the semiconductor structure 402 (as shown in Figure 4G), the semiconductor structure 444 can be stacked and bonded on the semiconductor structure 402 via a dielectric junction layer. Then, the mask layer 411 can be formed on the semiconductor structure 444. Thus, similar to the process described with reference to Figures 4G to 4I, the mask layer 411 can be etched to form openings, contact holes extending from the openings to the conductive layers 410 to 416 can be formed, and the contact structure can be formed within the contact holes to form a contact structure that extends through the semiconductor structure 444.

[0212] In some implementations, semiconductor structures 402, 404, 406, 408, and 444 can be manufactured separately such that limitations in manufacturing one of them (e.g., thermal budget) do not restrict the process for manufacturing the others. In some implementations, semiconductor structures 402, 404, 406, 408, and 444 can be manufactured in parallel.

[0213] In some implementations, each of the semiconductor structures 402, 404, 406, 408, and 444 includes a semiconductor die (e.g., a memory die or a base die). Each semiconductor die may contain a fully functional electronic circuit (e.g., a microprocessor, memory, sensor, or any other suitable type of integrated circuit) and may be enclosed in a protective package.

[0214] In some implementations, each of the semiconductor structures 402, 404, 406, 408, and 444 includes a semiconductor wafer. The semiconductor wafer may contain multiple semiconductor devices or dies manufactured by depositing multiple layers of various materials and etching them onto the semiconductor wafer in a complex pattern defined by the chip design. The process described with respect to Figures 4A to 4J is performed at the wafer level and applied to multiple semiconductor wafers to form a stack of semiconductor wafers joined together. After the process is complete, the stack of semiconductor wafers is cut and diced into individual pieces. Each of the individual pieces (also called dies) contains a fully functional electronic circuit which may be a microprocessor, HBM, sensor, or any other suitable type of integrated circuit. In some embodiments, each of the individual pieces is enclosed in a protective package to provide physical support, protection from environmental factors, and connectivity to an external device or system (e.g., via pins or solder balls).

[0215] Figure 5 shows a flowchart of a typical process 500 for forming a semiconductor device according to several aspects of this disclosure. The semiconductor device may be semiconductor device 200, 300a, 300d, 300e, 300g, or 300h, or a part thereof, or a structure in an intermediate manufacturing process of such semiconductor devices. Process 500 can be described with reference to Figures 4A to 4J. Process 500 may include a manufacturing process for forming the semiconductor structures shown in Figures 4A to 4J. Process 500 includes steps that can be performed in any suitable order and / or any combination.

[0216] In step 502, a first die and a second die are provided. The first die includes a conductive layer and at least a first junction layer. The second die includes a conductive layer and at least a second junction layer. The first die may be, for example, the semiconductor structure 402 of Figure 4D, and the second die may be, for example, the semiconductor structure 404 of Figure 4D. In some packaging configurations, the first junction layer of the first die and the second junction layer of the second die each include a dielectric material and exclude conductive junction contacts. In some packaging configurations, providing the first die includes thinning the first die by thinning the substrate included in the first die (for example, thinning the semiconductor structure 402 as described with respect to Figure 4B).

[0217] In step 504, the second die is stacked on the first die along the first direction (e.g., the Z direction). In some mounting configurations, stacking the second die on the first die along the first direction includes aligning the second die with the first die such that the first edge of the conductive layer of the first die (e.g., edge 418 in Figure 4C) and the first edge of the conductive layer of the second die (e.g., edge 420 in Figure 4C) are offset along the second direction (e.g., the X direction) perpendicular to the first direction.

[0218] In step 506, the second junction layer of the second die is bonded to the first junction layer of the first die. For example, as described with respect to Figure 4C, the second junction layer can be a dielectric layer deposited on the bottom surface of the semiconductor structure 404, and the first junction layer can be a dielectric layer deposited on the top surface of the semiconductor structure 402.

[0219] In step 508, a first contact structure and a second contact structure are formed extending along the first direction. The first contact structure (e.g., contact structure 426 in Figure 4I) extends into the first die (e.g., semiconductor structure 402) and contacts the conductive layer of the first die (e.g., conductive layer 410). The second contact structure (e.g., contact structure 428 in Figure 4I) extends into the second die (e.g., semiconductor structure 404) through the first junction layer of the first die and the second junction layer of the second die. The second contact structure contacts the conductive layer of the second die (e.g., conductive layer 412) without contacting the conductive layer of the first die.

[0220] In some implementations, process 500 further includes stacking a first die on a carrier wafer (e.g., the semiconductor structure 400 in Figures 4A to 4E). The first die may be stacked on the carrier wafer before the second die is stacked on top of the first die. The first die lies between the carrier wafer and the second die.

[0221] In some implementations, the first and second contact structures are formed by the same process (as described, for example, with respect to Figures 4H and 4I). The process includes forming a first contact hole (e.g., contact hole 425 in Figure 4H) and a second contact hole (e.g., contact hole 427 in Figure 4H). The first and second contact holes can be formed during the same etching process (as described, for example, with respect to Figure 4H). The process further includes forming an insulating layer (e.g., an outer layer 433 in Figure 4I) in each of the first and second contact holes. The process further includes forming a conductive structure within the insulating layer of each of the first and second contact holes (e.g., by depositing a conductive material such as copper or tungsten in the first and second contact holes). The first contact structure includes an insulating layer and a conductive structure within the first contact hole, and the second contact structure includes an insulating layer and a conductive structure within the second contact hole.

[0222] In some implementations, forming the first and second contact structures further includes etching the bottom of the insulating layer to expose the conductive layer of the first die and the conductive layer of the second die within the first and second contact holes, respectively.

[0223] In some implementations, process 500 further includes forming a mask layer (e.g., mask layer 411 in Figure 4G) on a first die, and etching the mask layer to form a first opening (e.g., opening 413 in Figure 4G) and a second opening (e.g., opening 415 in Figure 4G). The first contact hole extends from the first opening to the conductive layer of the first die, and the second contact hole extends from the second opening to the conductive layer of the second die.

[0224] In some implementation configurations, process 500 further includes forming a third bonding layer (e.g., bonding layer 443 in Figure 4J) on the first die. The third bonding layer includes a conductive bonding contact (e.g., conductive bonding contact 442 in Figure 4J) and a dielectric material separating the conductive bonding contact. The first and second contact structures can be coupled to the conductive bonding contact.

[0225] In some implementations, process 500 further includes providing a base die (e.g., semiconductor structure 444 in Figure 4J). The base die includes a lower junction layer (e.g., junction layer 445 in Figure 4J) which includes conductive junction contacts (e.g., conductive junction contacts 446 in Figure 4J) and a dielectric material separating the conductive junction contacts. As described with respect to Figure 4J, process 500 may further include stacking the base die on a first die and bonding the lower junction layer of the base die to a third junction layer of the first die. The lower junction layer and the third junction layer can be bonded by bonding the dielectric material of the lower junction layer to the dielectric material of the third junction layer and bonding the conductive junction contacts of the lower junction layer to the conductive junction contacts of the third junction layer.

[0226] Figure 6A shows a side view of a semiconductor device 600a according to several embodiments of the present disclosure. The semiconductor device 600a includes memory dies 602a-608a stacked (e.g., sequentially) along a vertical direction (e.g., Z direction), a base die 644a, a computing die 646a, and an interposer 648a. The memory dies 602a-608a may be examples of memory die 102 in Figure 1 and memory dies 204a-204d in Figure 2A (e.g., DRAM). The stack of memory dies 602a-608a includes a device region 601a and a connection region 603a adjacent to each other along a horizontal direction (e.g., X direction). Each of the memory dies 602a-608a includes conductive layers 610a-616a extending along a horizontal direction (e.g., X direction). Each of the conductive layers 610a to 616a is coupled to a memory array or peripheral circuit in the corresponding memory die within the device region 301a. Each of the conductive layers 610a to 616a can be coupled to the input / output ports of the corresponding memory die, or can be configured to provide one or more of the following to the corresponding memory die: power, clock signals, or data path signals.

[0227] As shown in Figure 6A, the semiconductor device 600a includes contact structures 626a to 632a within the connection region 603a. The contact structures 626a to 632a can be examples of the contact structure 210 shown in Figures 2A to 2B. The semiconductor device 600a further includes junction layers between adjacent memory dies 602a to 608a (e.g., junction layers 634a, 636a, and 638a), a junction layer 640a between the memory die 602a and the base die 644a, and a junction layer 642a between the base die 644a and the computing die 646a. Each of these junction layers may contain a dielectric material such as silicon oxide.

[0228] Contact structures 626a to 632a extend along the vertical direction (e.g., the Z direction) and are coupled to conductive layers 610a to 616a, respectively. Contact structure 626a extends within the memory die 602a and contacts the conductive layer 610a of the memory die 602a without penetrating the bonding layer 634a. Contact structure 628a extends through the conductive layer 610a and bonding layer 634a of the memory die 602a. Contact structure 628a further extends within the memory die 604a and contacts the conductive layer 612a of the memory die 604a without penetrating the bonding layer 636a. Contact structure 630a extends through the conductive layer 610a, bonding layer 634a, memory die 604a, conductive layer 612a, and bonding layer 636a of the memory die 602a. The contact structure 630a extends further into the memory die 606a and contacts the conductive layer 614a of the memory die 606a without penetrating the bonding layer 638a. The contact structure 632a extends through the conductive layer 610a, bonding layer 634a, memory die 604a, conductive layer 612a, bonding layer 636a, memory die 606a, conductive layer 614a, and bonding layer 638a of the memory die 602a. The contact structure 632a extends further into the memory die 608a and contacts the conductive layer 616a of the memory die 608a without penetrating the memory die 608a.

[0229] In some implementation configurations, the conductive layers 610a to 616a may be the same size and can be positioned at the same location along the X direction. That is, the conductive layers 610a to 616a can be aligned along the Z direction. Each contact structure 626a to 632a may include a conductive structure (inner layer) extending along the Z direction and an insulating layer (outer layer) surrounding the conductive structure. The insulating layer can insulate the conductive structure from one or more conductive layers through which the contact structure extends.

[0230] In some implementations, junction layers 634a, 636a, and 638a can be called direct junction layers because they are formed by direct dielectric-dielectric junctions. Each of junction layers 634a, 636a, and 638a may include at least one dielectric material and exclude conductive junction contacts. In some implementations, junction layers 640a and 642a can be called hybrid junction layers because they can be formed by hybrid dielectric-dielectric junctions and metal-metal junctions. Each of junction layers 640a and 642a may include junction contacts (e.g., conductive junction contacts) and at least one dielectric material separating the junction contacts. As shown in Figure 6A, junction layer 640a includes a conductive junction contact 654a. The conductive junction contact 654a may be configured to connect the memory die 602a and the base die 644a. In some implementations, the memory die 602a may include an interconnection layer (not shown in Figure 6A) that contacts junction layer 640a. The interconnection layer of the memory die 602a has a structure similar to the interconnection layer 645f described in Figure 6F. Each of the contact structures 626a to 632a can be coupled to the interconnection layer of the memory die 602a. The interconnection layer of the memory die 602a can be coupled to the base die 644a via conductive junction contacts 654a in the junction layer 640a. The base die 644a includes vias 650a that extend through the base die 644a along the Z direction and are connected to the conductive junction contacts 654a. Each of the contact structures 626a to 632a is coupled to each of the vias 350a via the corresponding conductive junction contacts 654a. The junction layer 642a includes a conductive junction contact 656a. The conductive junction contact 656a can be configured to connect the base die 644a and the computing die 646a. The computing die 646a can be an example of the computing die 108 in Figure 1. The computing die 646a includes vias 652a that extend through the computing die 646a along the Z direction and are connected to conductive bonding contacts 656a.Each via 650a is coupled to its respective via 652a via a corresponding conductive bonding contact 656a. In some configurations, vias 650a and 652a can be through-silicon vias (TSVs). The structures of the bonding layers 634a, 636a, 638a, 640a, and 642a will be described in more detail with reference to Figures 6B and 6C.

[0231] In some implementations, the base die 644a includes a control circuit configured to control the memory dies 602a to 608a. The control circuit can be coupled to the memory dies 602a to 608a, for example, via contact structures 626a to 632a, the interconnection layer of the memory die 602a, and the conductive junction contact 654a.

[0232] The interposer 648a has a surface 658a and a surface 660a. Surface 658a can be bonded to the computing die 646a. Conductive terminals 662a can be connected to surface 660a. The interposer 648a may include interconnection lines connecting vias 652a of the computing device 646a to conductive terminals 662a. Conductive terminals 662a can be coupled to an external device (e.g., the external host die 112 in Figure 1). In some implementations, conductive terminals 662a can be microbumps.

[0233] In some implementation configurations, as shown in Figure 6A, the thickness of the memory dies 602a to 606a can be reduced (along the Z direction) by thinning their substrates. The top memory die 608a (for example, the memory die 602a to 608a furthest from the base die 644a) does not need to be thinned. This allows the thickness of each of the memory dies 602a to 606a to be smaller than the thickness of memory die 608a. The thickness of each of the memory dies 602a to 608a can be within any suitable range (e.g., 3 μm to 20 μm).

[0234] Figure 6B shows Figure 600b, which shows an enlarged view of the bonding layer 634a of Figure 6A according to some aspects of the present disclosure. The bonding layer 634a may include an upper bonding layer 633b and a lower bonding layer 637b bonded at a bonding interface 635b. Each of the upper bonding layer 633b and the lower bonding layer 637b may contain a dielectric material (including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof) and conductive bonding contacts may be excluded. The memory die 604a may be bonded to the memory die 602a in a face-to-face manner via the bonding layer 634a. The bonding interface 635b is located between the upper bonding layer 633b and the lower bonding layer 637b as a result of a direct bonding (e.g., dielectric-dielectric bonding) that forms a bonding between surfaces without using an intermediate layer such as solder or adhesive. In some implementations, for example, when the dielectric material of the upper bonding layer 633b and the dielectric material of the lower bonding layer 637b are different materials, the bonding interface 635b can be a visible layer with a specific thickness that includes the top surface of the lower bonding layer 637b and the bottom surface of the upper bonding layer 633b. In some implementations, for example, when the dielectric material of the upper bonding layer 633b and the dielectric material of the lower bonding layer 637b are the same material, the bonding interface 635b may be invisible and can form a continuous portion with the upper bonding layer 633b and the lower bonding layer 637b. The bonding layers 636a and 638a in Figure 6A can have a structure similar to the bonding layer 634a described in Figure 6B.

[0235] Figure 6C shows Figure 600c, which shows an enlarged view of the bonding layer 640a of Figure 6A according to several embodiments of the present disclosure. The bonding layer 640a may include an upper bonding layer 643c and a lower bonding layer 647c bonded at the bonding interface 645c. The upper bonding layer 643c includes a conductive bonding contact 641c and a dielectric material 639c separating the conductive bonding contact 641c. The conductive bonding contact 641c may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The dielectric material 639c may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. Similarly, the lower bonding layer 647c includes a conductive bonding contact 649c and a dielectric material 651c separating the conductive bonding contact 649c. The conductive bonding contact 649c may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The dielectric material 651c may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0236] The conductive bonding contacts 641c and 649c can be examples of the conductive bonding contact 654a in Figure 6A. The conductive bonding contact 641c is in contact with the conductive bonding contact 649c at the bonding interface 645c. The memory die 602a can be bonded to the base die 644a in a face-to-face manner via the bonding layer 640a. The bonding interface 645c is located between the upper bonding layer 643c and the lower bonding layer 647c as a result of a hybrid bonding (e.g., metal-metal / dielectric-dielectric bonding). Hybrid bonding can form a bonding between surfaces without using an intermediate layer such as solder or adhesive, and can obtain both metal-metal and dielectric-dielectric bonding simultaneously. In some mounting configurations, for example, if the dielectric material 639c of the upper bonding layer 643c and the dielectric material 651c of the lower bonding layer 647c are different materials, the bonding interface 645c can be a visible layer with a specific thickness that includes the top surface of the lower bonding layer 647c and the bottom surface of the upper bonding layer 643c. In some implementation configurations, for example, if dielectric material 639c and dielectric material 651c are the same material, the bonding interface 645c may not be visible, and a continuous portion can be formed with the upper bonding layer 643c and the lower bonding layer 647c. The bonding layer 642a in Figure 6A can have a structure similar to the bonding layer 640a described in Figure 6C.

[0237] Figure 6D shows a side view of a semiconductor device 600d according to several embodiments of the present disclosure. The semiconductor device 600d includes memory dies 602d-608d, a base die 644d, a computing die 646d, and an interposer 648d. The memory dies 602d-608d and the base die 644d are stacked (e.g., sequentially) along the Z direction. The base die 644d and the computing die 646d are integrated at different positions on the interposer 648d along the X direction. The memory dies 602d-608d are similar to the memory dies 602a-608a in Figure 6A. The memory dies 602d-608d can be examples of memory die 102 in Figure 1 and memory dies 204a-204d in Figure 2A (e.g., DRAM). The stack of memory dies 602d-608d includes a device region 601d and a connection region 603d adjacent to the device region 601d horizontally (e.g., in the X direction). Each of the memory dies 602d-608d includes conductive layers 610d-616d extending horizontally (e.g., in the X direction). Each of the conductive layers 610d-616d is coupled to a memory array or peripheral circuit in the corresponding memory die within the device region 601d. Each of the conductive layers 610d-616d can be coupled to the input / output ports of the corresponding memory die, or can be configured to provide one or more of the following to the corresponding memory die: power, clock signals, or data path signals.

[0238] As shown in Figure 6D, the semiconductor device 600d includes contact structures 626d to 632d in the connection region 603d. The contact structures 626d to 632d can be examples of the contact structure 210 in Figures 2A to 2B. The semiconductor device 600d further includes junction layers between adjacent memory dies among the memory dies 602d to 608d (e.g., junction layers 634d, 636d, and 638d) and a junction layer 640d between the memory die 602d and the base die 644d. Each of these junction layers may contain a dielectric material such as silicon oxide.

[0239] Contact structures 626d to 632d extend along the vertical direction (e.g., the Z direction) and are coupled to conductive layers 610d to 616d, respectively. Contact structure 626d extends within the memory die 602d and contacts the conductive layer 610d of the memory die 602d without penetrating the bonding layer 634d. Contact structure 628d extends through the conductive layer 610d and bonding layer 634d of the memory die 602d. Contact structure 628d further extends within the memory die 604d and contacts the conductive layer 612d of the memory die 604d without penetrating the bonding layer 636d. Contact structure 630d extends through the conductive layer 610d, bonding layer 634d, memory die 604d, conductive layer 612d, and bonding layer 636d of the memory die 602d. The contact structure 630d extends further into the memory die 606d and contacts the conductive layer 614d of the memory die 606d without penetrating the bonding layer 638d. The contact structure 632d extends through the conductive layer 610d, bonding layer 634d, memory die 604d, conductive layer 612d, bonding layer 636d, memory die 606d, conductive layer 614d, and bonding layer 638d of the memory die 602d. The contact structure 632d extends further into the memory die 608d and contacts the conductive layer 616d of the memory die 608d without penetrating the memory die 608d.

[0240] In some implementation configurations, the conductive layers 610d to 616d may be the same size and can be positioned at the same location along the X direction. That is, the conductive layers 610d to 616d can be aligned along the Z direction. Each contact structure 626d to 632d may include a conductive structure (inner layer) extending along the Z direction and an insulating layer (outer layer) surrounding the conductive structure. The insulating layer can insulate the conductive structure from one or more conductive layers through which the contact structure extends.

[0241] In some implementations, junction layers 634d, 636d, and 638d can be called direct junction layers and may have a structure similar to that of junction layer 634a described in Figure 6B. Each of junction layers 634d, 636d, and 638d may include at least one dielectric material and exclude conductive junction contacts. In some implementations, junction layer 640d can be called a hybrid junction layer and may have a structure similar to that of junction layer 640a described in Figure 6C. Junction layer 640d may include junction contacts (e.g., conductive junction contacts 654d as shown in Figure 6D) and at least one dielectric material separating the junction contacts. The conductive junction contacts 654d may be configured to connect the memory die 602d and the base die 644d. In some implementations, the memory die 602d may include an interconnection layer (not shown in Figure 6D) that contacts junction layer 640d. The interconnection layer of the memory die 602d has a structure similar to the interconnection layer 645f described in Figure 6F. Each of the contact structures 626d to 632d can be coupled to the interconnection layer of the memory die 602d. The interconnection layer of the memory die 602d can be coupled to the base die 644d via conductive junction contacts 654d within the junction layer 640d. The base die 644d includes vias 650d that extend through the base die 644d along the Z direction and are connected to the conductive junction contacts 654d. Each of the contact structures 626d to 632d is coupled to each of the vias 650d via the corresponding conductive junction contacts 654d. In some implementations, the vias 650d can be TSVs.

[0242] In some implementations, the base die 644d includes a control circuit configured to control the memory dies 602d-608d. The control circuit can be coupled to the memory dies 602d-608d, for example, via contact structures 626d-632d, the interconnection layer of the memory die 602d, and conductive junction contacts 654d.

[0243] The base die 644d can be coupled to the computing die 646d via the interposer 648d. The interposer 648d has a surface 658d and a surface 660d. Vias 650d in the base die 644d can be connected to conductive terminals 664d on surface 658d of the interposer 648d. The computing die 646d can be connected to conductive terminals 666d on surface 658d of the interposer 648d. The semiconductor device 600d may include conductive terminals 662d connected to surface 660d of the interposer 648d. Conductive terminals 664d, 666d, and 662d can be coupled via conductive wires in the interposer 648d (e.g., conductive wire 669d as shown in Figure 6D). Conductive terminal 662d can be coupled to an external device (e.g., an external host die 112 in Figure 1). In some implementations, the conductive terminals 664d, 666d, and 662d can be microbumps. In practice, it is understood that the base die 644d, the computing die 646d, and the interposer 648d can be integrated using any suitable packaging technique, including, for example, Chip-on-Wafer-on-Substrate (CoWoS).

[0244] In some implementation configurations, as shown in Figure 6D, the thickness of the memory dies 602d to 606d can be reduced (along the Z direction) by thinning their substrates. The top memory die 608d (for example, the one of the memory dies 602d to 608d furthest from the base die 644d) does not need to be thinned. This allows the thickness of the memory dies 602d to 606d to be thinner than the thickness of memory die 608d. The thickness of each of the memory dies 602d to 608d can be any suitable range (e.g., 3 μm to 20 μm).

[0245] Figure 6E shows a side view of a semiconductor device 600e according to several aspects of the present disclosure. The semiconductor device 600e includes memory dies 602e-608e stacked (e.g., sequentially) along the vertical direction (e.g., Z direction), a base die 644e, a computing die 646e, and an interposer 648e. The memory dies 602e-608e are similar to the memory dies 602a-608a in Figure 6A. The memory dies 602e-608e can be examples of memory die 102 in Figure 1 and memory dies 204a-204d in Figure 2A (e.g., DRAM). The stack of memory dies 602e-608e includes a device region 601e and a connection region 603e adjacent to the device region 601e along the horizontal direction (e.g., X direction). Each of the memory dies 602e to 608e includes conductive layers 610e to 616e extending horizontally (e.g., in the X direction). Each of the conductive layers 610e to 616e is coupled to a memory array or peripheral circuit in the corresponding memory die within the device region 601e. Each of the conductive layers 610e to 616e can be coupled to the input / output ports of the corresponding memory die, or can be configured to provide one or more of the following to the corresponding memory die: power, clock signals, or data path signals.

[0246] As shown in Figure 6E, the semiconductor device 600e includes contact structures 626e to 632e in the connection region 603e. The contact structures 626e to 632e can be examples of the contact structure 210 in Figures 2A to 2B. The semiconductor device 600e further includes junction layers between adjacent memory dies among the memory dies 602e to 608e (e.g., junction layers 634e, 636e, and 638e) and a junction layer 640e between the memory die 602e and the base die 644e. Each of these junction layers may contain the dielectric material silicon oxide. The base die 644e includes a surface 665e and another surface 667e. Surface 665e is bonded to the memory die 602e via the junction layer 640e. The base die 644e further includes a conductive layer 668e and a contact structure 670e connected to the conductive layer 668e. The contact structure 670e extends within the base die 644e along the Z direction. The conductive layer 668e can be coupled between the circuit of the base die 644e and the contact structure 370e. In some implementations, the junction layers 634e, 636e, 638e, and 640e can be called direct junction layers and may have a structure similar to that of junction layer 634a described in Figure 6B. Each of the junction layers 634e, 636e, 638e, and 640e may include at least one dielectric material and exclude conductive junction contacts. In some implementations, the junction layer 642e can be called a hybrid junction layer and may have a structure similar to that of junction layer 640a described in Figure 6C. The junction layer 642e may include junction contacts (e.g., conductive junction contacts 656e as shown in Figure 6E) and at least one dielectric material separating the junction contacts.

[0247] Contact structures 626e-632e and 670e extend along the vertical direction (e.g., the Z direction) and are coupled to conductive layers 610e-616e and 668e, respectively. Contact structure 670e extends into the base die 644e and contacts the conductive layer 668e of the base die 644e without extending through the bonding layer 640e. Contact structure 626e extends into the memory die 602e through the bonding layer 640e and contacts the conductive layer 610e of the memory die 602e without extending through the bonding layer 634e. Contact structure 628e extends through the bonding layer 640e, the conductive layer 610e of the memory die 602e, and the bonding layer 634e. The contact structure 628e extends further into the memory die 604e and contacts the conductive layer 612e of the memory die 604e without penetrating the bonding layer 636e. The contact structure 630e extends through the bonding layer 640e, the conductive layer 610e of the memory die 602e, the bonding layer 634e, the memory die 604e, the conductive layer 612e, and the bonding layer 636e. The contact structure 630e extends further into the memory die 606e and contacts the conductive layer 614e of the memory die 606e without penetrating the bonding layer 638e. The contact structure 632e extends through the junction layer 640e, the conductive layer 610e of the memory die 602e, the junction layer 634e, the memory die 604e, the conductive layer 612e, the junction layer 636e, the memory die 606e, the conductive layer 614e, and the junction layer 638e. The contact structure 632e further extends into the memory die 608e and contacts the conductive layer 616e of the memory die 608e without extending through the memory die 608e. Figure 6E shows an example in which the contact structures 626e to 632e do not extend through the conductive layer 668e, but it is understood that in some other implementation configurations, one or more of the contact structures 626e to 632e may extend through the conductive layer 668e.

[0248] In some implementation configurations, the conductive layers 610e to 616e may be the same size and can be positioned at the same location along the X direction. That is, the conductive layers 610e to 616e can be aligned along the Z direction. Each contact structure 626e to 632e may include a conductive structure (inner layer) extending along the Z direction and an insulating layer (outer layer) surrounding the conductive structure. The insulating layer can insulate the conductive structure from one or more conductive layers through which the contact structure extends.

[0249] The base die 644e may include an interconnection layer (not shown in Figure 6E) that contacts the bonding layer 642e. Each of the contact structures 626e-632e and 670e can be coupled to the interconnection layer of the base die 644e. An example of the interconnection layer of the base die 644e is described in more detail later with reference to Figure 6F. The interconnection layer of the base die 644e can be coupled to the computing die 646e via conductive bonding contacts 656e within the bonding layer 642e. The conductive bonding contacts 656e can be configured to couple the base die 644e and memory dies 602e-608e to the computing die 646e. The computing die 646e may be an example of the computing die 108 in Figure 1. The computing die 646e includes vias 652e that extend through the computing die 646e along the Z direction and are connected to the conductive bonding contacts 656e. Each of the contact structures 670e and 626e-632e can be coupled to each of the vias 652e via the interconnection layer of the base die 644e and the corresponding conductive junction contact 656e. In some implementation configurations, the vias 652e can be TSVs.

[0250] In some implementations, the base die 644e includes a control circuit configured to control the memory dies 602e-608e. The control circuit can be coupled to the memory dies 602e-608e, for example, via contact structures 670e and 626e-632e, the interconnection layer of the base die 644e, and conductive junction contacts 656e.

[0251] The interposer 648e has surfaces 658e and 660e. Surface 658e can be bonded to the computing die 646e. Conductive terminal 662e can be connected to surface 660e. The interposer 648e may include interconnection lines connecting via 652e of the computing die 646e to conductive terminal 662e. Conductive terminal 662e can be coupled to an external device (e.g., the external host die 112 in Figure 1). In some implementations, conductive terminal 662e can be a microbump.

[0252] In some implementation configurations, as shown in Figure 6E, the thickness of the memory dies 602e to 606e can be reduced (along the Z direction) by thinning their substrates. The top memory die 608e (for example, the memory die 602e to 608e furthest from the base die 644e) does not need to be thinned. This allows the thickness of the memory dies 602e to 606e to be thinner than the thickness of the memory die 608e. The thickness of each of the memory dies 602e to 608e can be any suitable range (e.g., 3 μm to 20 μm).

[0253] Figure 6F shows Figure 600f, which shows an enlarged view of the interconnection layer 645f within the base die 644e of Figure 6E, according to some aspects of the present disclosure. The interconnection layer 645f is located between the contact structures 626e-632e and 670e and the bonding layer 642e along the Z direction. The interconnection layer 645f may include interconnections (also referred to herein as “contacts”), including lateral interconnection lines 647f and VIA contacts (not shown). The contact structures 626e-632e and 670e and the conductive bonding contact 656e of the bonding layer 642e can be coupled to interconnections within the interconnection layer 645f. The interconnection layer 645f may further include one or more ILD layers (also known as IMD layers) on which interconnection lines 647f and VIA contacts can be formed. That is, the interconnection layer 645f may include interconnection lines 647e and VIA contacts within a plurality of ILD layers. The interconnection lines 647f and VIA contacts within the interconnection layer 645f may include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer within the interconnection layer 645f may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0254] Figure 6G shows a side view of a semiconductor device 600g according to several embodiments of the present disclosure. The semiconductor device 600g includes memory dies 602g to 608g, a base die 644g, a computing die 646g, and an interposer 648g. The memory dies 602g to 608g and the base die 644g are stacked sequentially along the Z direction. The base die 644g and the computing die 646g are integrated at different positions on the interposer 648g along the X direction. The memory dies 602g to 608g are similar to the memory dies 602a to 608a in Figure 3A. The memory dies 602g to 608g can be examples of memory die 102 in Figure 1 and memory dies 204a to 204d in Figure 2A (e.g., DRAM). The stack of memory devices 602g to 608g includes a device region 601g and a connection region 603g adjacent to the device region 601g horizontally (e.g., in the X direction). Each of the memory dies 602g to 608g includes conductive layers 610g to 616g extending horizontally (e.g., in the X direction). Each of the conductive layers 610g to 616g is coupled to a memory array or peripheral circuit in the corresponding memory die within the device region 601g. Each of the conductive layers 610g to 616g can be coupled to the input / output ports of the corresponding memory die, or can be configured to provide one or more of the following to the corresponding memory die: power, clock signals, or data path signals.

[0255] As shown in Figure 6G, the semiconductor device 600g includes contact structures 626g to 632g in the connection region 603g. Contact structures 626g to 632g can be examples of contact structure 210 in Figures 2A to 2B. The semiconductor device 600g further includes junction layers between adjacent memory dies from memory dies 602g to 608g (e.g., junction layers 634g, 636g, and 638g) and a junction layer 640g between memory die 602g and base die 644g. Each of these junction layers may contain silicon oxide. The base die 644g includes a surface 665g and another surface 667g. Surface 665g is bonded to memory die 602g via junction layer 640g. The base die 644g further includes a conductive layer 668g and a contact structure 670g connected to the conductive layer 668g. The contact structure 670g extends within the base die 644g along the Z direction. The conductive layer 668g can be coupled between the circuit of the base die 644g and the contact structure 670g. In some implementation configurations, the junction layers 634g, 636g, 638g, and 640g can be called direct junction layers and may have a structure similar to that of junction layer 634a described in Figure 6B. Each of the junction layers 634g, 636g, 638g, and 640g may contain at least one dielectric material and exclude conductive junction contacts.

[0256] Contact structures 626g-632g and 670g extend along the vertical direction (e.g., the Z direction) and are coupled to conductive layers 610g-616g and 668g, respectively. Contact structure 670g extends into the base die 644g and contacts the conductive layer 668g of the base die 644g without penetrating the bonding layer 640g. Contact structure 626g extends into the memory die 602g through the bonding layer 640g and contacts the conductive layer 610g of the memory die 602g without penetrating the bonding layer 634g. Contact structure 628g extends through the bonding layer 640g, the conductive layer 610g of the memory die 602g, and the bonding layer 634g. The contact structure 628g extends further into the memory die 604g and contacts the conductive layer 612g of the memory die 604g without penetrating the bonding layer 636g. The contact structure 630g extends through the bonding layer 640g, the conductive layer 610g of the memory die 602g, the bonding layer 634g, the memory die 604g, the conductive layer 612g, and the bonding layer 636g. The contact structure 630g extends further into the memory die 606g and contacts the conductive layer 614g of the memory die 606g without penetrating the bonding layer 638g. The contact structure 632g extends through the junction layer 640g, the conductive layer 610g of the memory die 602g, the junction layer 634g, the memory die 604g, the conductive layer 612g, the junction layer 636g, the memory die 606g, the conductive layer 614g, and the junction layer 638g. The contact structure 632g further extends into the memory die 608g and contacts the conductive layer 616g of the memory die 608g without extending through the memory die 608g. Figure 6G shows an example in which the contact structures 626g to 632g do not extend through the conductive layer 668g, but it is understood that in some other mounting configurations, one or more of the contact structures 626g to 632g may extend through the conductive layer 668g.

[0257] In some implementation configurations, the conductive layers 610g to 616g may be the same size and can be positioned at the same location along the X direction. That is, the conductive layers 610g to 616g can be aligned along the Z direction. Each contact structure 626g to 632g may include a conductive structure (inner layer) extending along the Z direction and an insulating layer (outer layer) surrounding the conductive structure. The insulating layer can insulate the conductive structure from one or more conductive layers through which the contact structure extends.

[0258] The base die 644g may include an interconnection layer (not shown in Figure 6G). The interconnection layer of the base die 644g has a structure similar to the interconnection layer 645f described in Figure 6F. Each of the contact structures 626g-632g and 670g can be coupled to the interconnection layer of the base die 644g. The base die 644g can be coupled to the computing die 646g via the interconnection layer and the interposer 648g. The interposer 648g has a surface 658g and a surface 660g. The interconnection in the interconnection layer of the base die 644g can be connected to the conductive terminal 664g on the surface 658g of the interposer 648g. The computing die 646g can be connected to the conductive terminal 666g on the surface 658g of the interposer 648g. The semiconductor device 600g may include a conductive terminal 662g connected to the surface 660g of the interposer 648g. Conductive terminals 664g, 666g, and 662g can be coupled via conductive wires within the interposer 648g (e.g., conductive wire 669g as shown in Figure 6G). Conductive terminal 662g can be coupled to an external device (e.g., the external host die 112 in Figure 1). In some implementations, conductive terminals 664g, 666g, and 662g can be microbumps. In practice, it is understood that the base die 644g, computing die 646g, and interposer 648g can be integrated using any suitable packaging technique, including, for example, Chip-on-Wafer-on-Substrate (CoWoS).

[0259] In some implementations, the base die 644g includes a control circuit configured to control the memory dies 602g to 608g. The control circuit can be coupled to the memory dies 602g to 608g, for example, via the contact structures 670g and 626g to 632g and the interconnection layer of the base die 644g.

[0260] In some implementation configurations, as shown in Figure 6G, the thickness of memory dies 602g to 606g can be reduced (along the Z direction) by thinning their substrates. The top memory die 608g (for example, the memory die 602g to 608g furthest from the base die 644g) does not need to be thinned. This allows each of the memory dies 602g to 606g to be thinner than the thickness of memory die 608g. The thickness of each of the memory dies 602g to 608g can be within any suitable range (e.g., 3μm to 20μm).

[0261] Figures 7A to 7N illustrate typical processes for manufacturing semiconductor devices according to several embodiments of this disclosure. In some packaging configurations, any suitable semiconductor device, such as semiconductor devices 200d, 600a, and 600d, can be manufactured using the processes described herein.

[0262] Figure 7A shows that the process can begin by providing semiconductor structures 700 and 702, both extending horizontally (e.g., along the X-direction). Semiconductor structure 700 can be a carrier wafer. Semiconductor structure 702 can be a semiconductor device or semiconductor die (e.g., memory die 204a in Figure 2D or memory die 602a in Figure 6A) including a conductive layer 710 (e.g., conductive layer 610a in Figure 6A). Semiconductor structure 702 can be stacked on semiconductor structure 700 along the vertical direction (e.g., along the Z-direction) and bonded to semiconductor structure 700 via a bonding layer 701. Semiconductor structures 700 and 702 can be bonded using any suitable bonding technique (e.g., direct bonding technique). For example, a first dielectric layer (e.g., silicon oxide) can be deposited on the surface 703 of semiconductor structure 700, and a second dielectric layer (e.g., silicon oxide) can be deposited on the surface 705 of semiconductor structure 702. By applying pressure and heat, the first dielectric layer and the second dielectric layer can be joined together to form a junction layer 701 between the semiconductor structures 700 and 702. The semiconductor structure 700 can function as a support for the semiconductor structure 702. The semiconductor structures 700 and 702 can have any suitable thickness along the Z direction. In some mounting configurations, the thickness of the semiconductor structure 702 can be in the range of 40 μm to 50 μm.

[0263] As shown in Figure 7B, the semiconductor structure 702 is thinned. Thinning the semiconductor structure 702 involves removing the top of the semiconductor structure 702 (for example, the part furthest from the semiconductor structure 700 along the Z direction). For example, the thickness of the semiconductor structure 702 can be thinned from approximately 40-50 μm to 3-20 μm. In some packaging configurations, the semiconductor structure 702 includes a substrate at its bottom and is inverted before being bonded to the semiconductor structure 700. That is, the substrate of the semiconductor structure 702 becomes the top of the semiconductor structure 702 after inversion. Therefore, by thinning the top of the semiconductor structure 702, a portion of the substrate of the semiconductor structure 702 is removed. In some packaging configurations, after thinning, the semiconductor structure 702 can still maintain its shape without substantial strain or deformation due to the support provided by the semiconductor structure 700 (e.g., carrier wafer).

[0264] As shown in Figure 7C, a semiconductor structure 704 is provided. The semiconductor structure 704 (e.g., memory die 604a in Figure 6A) includes a conductive layer 712 (e.g., conductive layer 612a in Figure 6A). In some mounting configurations, the semiconductor structure 704 includes a substrate on top of it, similar to the semiconductor structure 702 described with reference to Figure 7B. The semiconductor structure 704 can be aligned with the semiconductor structure 702 so that the conductive layers 712 and 710 are in the same position along the X direction. This allows the conductive layers 712 and 710 to be aligned along the Z direction. In some mounting configurations, the conductive layers 712 and 710 may be the same size. A dielectric layer can be deposited on the bottom surface of the semiconductor structure 704, and a dielectric layer can be deposited on the top surface of the semiconductor structure 702. The semiconductor structure 704 can be stacked and bonded to the semiconductor structure 702 along the Z direction, similar to the example of bonding the semiconductor structure 702 and the semiconductor structure 700 as described with reference to Figure 7A.

[0265] As shown in Figure 7D, the dielectric layer of semiconductor structure 704 and the dielectric layer of semiconductor structure 702 can form a junction layer 707. Semiconductor structure 704 is thinned by removing the top (for example, a part of the substrate of semiconductor structure 704).

[0266] FIG. 7E shows a semiconductor structure 706 (e.g., memory die 606a of FIG. 6A) including a conductive layer 714 (e.g., conductive layer 614a of FIG. 6A) and a semiconductor structure 708 (e.g., memory die 608a of FIG. 6A) including a conductive layer 716 (e.g., conductive layer 616a of FIG. 6A). The semiconductor structure 706 is aligned, stacked, and bonded to the semiconductor structure 704 in a similar manner as described in the examples with reference to FIGS. 7A-7D. The semiconductor structure 706 can also be thinned. Similarly, the semiconductor structure 708 is aligned, stacked, and bonded to the semiconductor structure 706. In some implementations, the semiconductor structure 708 is not thinned, such that when the stack of semiconductor structures 704-708 is flipped upside down in a later step, it supports other semiconductor structures due to its thickness. The conductive layers 710-716 can be of the same length and can be aligned along the Z direction. In some implementations, the semiconductor structures 704-708 (e.g., before thinning) can have the same structure. Thus, the order in which the semiconductor structures 704-708 are stacked may not affect the manufacturing process. In other words, it is not necessarily required to label the semiconductor structures 704-708.

[0267] In this example, the semiconductor device can include four semiconductor structures 702-708 stacked on top of each other, but the techniques disclosed herein can be applied to stack any suitable number of semiconductor structures (e.g., 2, 5, or 8). The number of semiconductor structures can be determined based on factors including technical constraints, thermal considerations, signal integrity and interference, physical size and application, cost and yield, reliability concerns, etc. In these cases, the last semiconductor structure farthest from the semiconductor structure 700 (not the fourth one as shown in FIG. 7E) can be made thicker than other semiconductor structures along the Z direction. For example, the last semiconductor structure is not thinned while the other semiconductor structures are thinned. In this way, the last semiconductor structure can provide support due to its thickness when the stacked structure is flipped upside down in a later step.

[0268] As shown in Figure 7F, semiconductor structure 700 can be removed by a delamination process. The stack of semiconductor structures 702-708 is inverted. As it is the thickest of the semiconductor structures 702-708, semiconductor structure 708 is at the bottom here, supporting the other semiconductor structures.

[0269] Figure 7G shows that a mask layer 711 is formed on the semiconductor structure 702. The mask layer 711 has openings 713, 715, 717, and 719. In some packaging configurations, the mask layer 711 contains a photoresist material, and the openings 713, 715, 717, and 719 can be formed by etching the mask layer 711. The positions of the openings 713, 715, 717, and 719 can be determined such that each contact hole extending along the Z direction (e.g., contact holes 725, 727, 729, and 731 in Figure 7H) extends from one of the openings 713, 715, 717, and 719 to reach the conductive layer 710.

[0270] Figure 7H shows that contact holes 725, 727, 729, and 731 are formed extending within the semiconductor structure 702 along the Z direction. The contact holes 725, 727, 729, and 731 extend from openings 713, 715, 717, and 719 and reach the conductive layer 710. In some implementations, the contact holes 725, 727, 729, and 731 are formed by etching a separation material (e.g., silicon oxide) within the semiconductor structure 702 (e.g., using a first etching gas).

[0271] Figure 7I shows the state in which the contact hole 725 is filled with filler material 718. In some mounting configurations, the filler material 718 may include any suitable material such as dielectric material or photoresist material in the mask layer 711.

[0272] Figure 7J shows that the contact holes 727, 729, and 731 can be deepened, and that the deepened contact holes 727, 729, and 731 penetrate the conductive layer 710 and reach the conductive layer 712. The contact holes 727, 729, and 731 can be deepened by etching the conductive layer 710 (e.g., using a second etching gas) and etching the material (e.g., silicon oxide) between the conductive layer 710 and the conductive layer 712 (e.g., using a first etching gas). The second etching gas may have a faster etching rate than the first etching gas for conductive material (e.g., metal) within the conductive layers (e.g., conductive layers 710-716).

[0273] Figure 7K shows that the contact holes 729 and 731 can be made deeper. The contact hole 727, extending from the opening 715 to the conductive layer 712, is filled with a filler material (e.g., filler material 718). The contact holes 729 and 731 can be made deeper by etching the conductive layer 712 (e.g., using a second etching gas) and etching the material between the conductive layer 712 and the conductive layer 714 (e.g., silicon oxide) (e.g., using a first etching gas). The deepened contact holes 729 and 731 penetrate the conductive layers 710 and 712 to reach the conductive layer 714. The deepened contact hole 729 can then be filled with a filler material (e.g., filler material 718). The contact hole 731 can be further deepened by etching the conductive layer 714 (for example, using a second etching gas) and the material between the conductive layer 714 and the conductive layer 716 (for example, silicon oxide) (for example, using a first etching gas). The deepened contact hole 731 can extend from the opening 719 to the conductive layer 716.

[0274] Figure 7L shows the state after the filler material has been removed from contact holes 725, 727, and 729. The mask layer 411 can also be removed, for example, by chemical mechanical planarization (CMP).

[0275] Figure 7M shows that contact structures 726, 728, 730, and 732 are formed in contact holes 725, 727, 729, and 731. Each of the contact structures 726, 728, 730, and 732 may include an outer layer (e.g., outer layer 733) and an inner layer (e.g., inner layer 735) on the inner surface of the outer layer 733. The inner layer may contain a conductive material (e.g., copper or tungsten) and may be called a conductive structure. The outer layer may contain an insulating material (dielectric material such as silicon oxide) and may be called an insulating layer. The contact structures 726, 728, 730, and 732 can be formed by first depositing a dielectric material into the contact holes 725, 727, 729, and 731 to form an insulating layer on the inner surface of the contact holes 725, 727, 729, and 731. Subsequently, the bottom of the insulating layer can be etched away to expose the conductive layers 710, 712, 714, and 716 within the contact holes 725, 727, 729, and 731. Then, by depositing conductive material into the contact holes 725, 727, 729, and 731, the inner layers of the contact structures 726, 728, 730, and 732 can be formed. As a result, the contact structures 726, 728, 730, and 732 are bonded to the conductive layers 710, 712, 714, and 716, respectively, and their respective outer layers 733 can insulate each conductive structure from one or more conductive layers that the contact structures penetrate and extend through. In some mounting configurations, after deposition, excess material such as metal and dielectric can be polished using CMP, leaving a flat surface with metal within the contact holes.

[0276] Figure 7N shows that semiconductor structure 744 is stacked and bonded on semiconductor structure 702. Semiconductor structure 744 can be a base die (e.g., base die 212 in Figure 2A, base die 644a in Figure 6A, or base die 644d in Figure 6D). Semiconductor structure 744 includes vias 750 extending along the Z direction. Semiconductor structure 744 can be bonded to semiconductor structure 702 using any suitable bonding technique. In some implementations, semiconductor structure 744 and semiconductor structure 702 can be bonded via conductive bonding contacts and dielectric material. Specifically, a bonding layer 743 can be formed on the upper surface of semiconductor structure 702. The bonding layer 743 may include conductive bonding contacts 742 and dielectric material separating the conductive bonding contacts 742. Contact structures 726, 728, 730, and 732 are connected to the corresponding bonding contacts of the conductive bonding contacts 742. In some implementations, an interconnection layer is formed within the semiconductor structure 702 before the junction layer 743 is formed. The interconnection layer can be coupled to contact structures 726, 728, 730, and 732. A junction layer 745 can be formed on the bottom surface of the semiconductor structure 744. The junction layer 745 may include conductive junction contacts 746 and a dielectric material separating the conductive junction contacts 746. The conductive junction contacts 746 are connected to vias 750 of the semiconductor structure 744. Conductive junction contacts 742 and 746 may include the same conductive material, such as a metal (e.g., copper). Junction layers 743 and 745 may include the same dielectric material (e.g., silicon oxide). The semiconductor structure 744 is stacked on the semiconductor structure 702 such that the junction layer 745 is in contact with the junction layer 743 and each conductive junction contact 746 is in contact with the corresponding conductive junction contact 742. By applying pressure and heat, the bonding layer 745 is bonded to the bonding layer 743.

[0277] In some implementations, the process described with reference to Figures 7A to 7N can be modified to form a semiconductor device having a contact structure that extends through the semiconductor structure 744 (for example, a stack of memory dies and base dies as described with reference to Figures 6E and 6G). For example, before forming the mask layer 711 on the semiconductor structure 702 (as shown in Figure 7G), the semiconductor structure 744 can be stacked on the semiconductor structure 702 via a dielectric junction layer and bonded to the semiconductor structure. Then, the mask layer 711 can be formed on the semiconductor structure 744. Thus, similar to the process described with reference to Figures 7G to 7M, the mask layer 711 can be etched to form openings, contact holes extending from the openings to the conductive layers 710 to 716 can be formed, and the contact structure can be formed within the contact holes to form a contact structure that extends through the semiconductor structure 744.

[0278] In some implementations, semiconductor structures 702, 704, 706, 708, and 744 can be manufactured separately such that limitations in manufacturing one of them (e.g., thermal budget) do not restrict the process for manufacturing the others. In some implementations, semiconductor structures 702, 704, 706, 708, and 744 can be manufactured in parallel.

[0279] In some implementations, each of the semiconductor structures 702, 704, 706, 708, and 744 includes a semiconductor die (e.g., a memory die or a base die). Each semiconductor die may contain a fully functional electronic circuit (e.g., a microprocessor, memory, sensor, or any other suitable type of integrated circuit) and may be enclosed in a protective package.

[0280] In some implementations, each of the semiconductor structures 702, 704, 706, 708, and 744 includes a semiconductor wafer. The semiconductor wafer may contain multiple semiconductor devices or dies manufactured by depositing multiple layers of various materials and etching them onto the semiconductor wafer in a complex pattern defined by the chip design. The process described with respect to Figures 7A to 7N is performed at the wafer level and applied to multiple semiconductor wafers to form a stack of semiconductor wafers joined together. After the process is complete, the stack of semiconductor wafers is cut and diced into individual pieces. Each of the individual pieces (also called dies) contains a fully functional electronic circuit which may be a microprocessor, HBM, sensor, or any other suitable type of integrated circuit. In some embodiments, each of the individual pieces is enclosed in a protective package to provide physical support, protection from environmental factors, and connectivity to an external device or system (e.g., via pins or solder balls).

[0281] Figure 8 shows a flowchart of a typical process 800 for forming a semiconductor device according to several aspects of this disclosure. The semiconductor device may be semiconductor devices 200d, 600a, 600d, 600e, and 600g, or a part thereof, or a structure in an intermediate manufacturing process for such semiconductor devices. Process 800 can be described with reference to Figures 7A to 7N. Process 800 may include a manufacturing process for forming the semiconductor structures shown in Figures 7A to 7N. Process 800 includes steps that can be performed in any suitable order and / or any combination.

[0282] In step 802, a first die and a second die are prepared. The first die includes a first conductive layer and at least a first junction layer. The second die includes a second conductive layer and at least a second junction layer. The first die may be, for example, the semiconductor structure 702 of Figure 7D, and the second die may be, for example, the semiconductor structure 704 of Figure 7D. In some packaging configurations, the first junction layer of the first die and the second junction layer of the second die each include a dielectric material and exclude conductive junction contacts. In some packaging configurations, providing the first die includes thinning the first die by thinning the substrate included in the first die (for example, thinning the semiconductor structure 702 as described with respect to Figure 7B).

[0283] In step 804, the second die is stacked on the first die along the first direction (e.g., the Z direction). In some configurations, stacking the second die on the first die along the first direction includes aligning the second die with the first die in order to position the second conductive layer and the first conductive layer in the same location along the second direction (e.g., the X direction) perpendicular to the first direction.

[0284] In step 806, the second junction layer of the second die is bonded to the first junction layer of the first die. For example, as described with reference to Figure 7C, the second junction layer can be a dielectric layer deposited on the bottom surface of the semiconductor structure 704, and the first junction layer can be a dielectric layer deposited on the top surface of the semiconductor structure 702.

[0285] In step 808, a first contact structure and a second contact structure are formed extending along the first direction. The first contact structure (e.g., contact structure 726 in Figure 7M) extends into the first die (e.g., semiconductor structure 702) and contacts the first conductive layer of the first die (e.g., conductive layer 710) without extending through the first junction layer. The second contact structure (e.g., contact structure 728 in Figure 7M) extends into the second die (e.g., semiconductor structure 704) through the first conductive layer, the first junction layer of the first die, and the second junction layer of the second die. The second contact structure contacts the second conductive layer of the second die (e.g., conductive layer 712) without extending through the second die.

[0286] In some implementations, process 800 further includes stacking a first die on a carrier wafer (e.g., the semiconductor structure 700 in Figures 7A to 7N). The first die may be stacked on the carrier wafer before the second die is stacked on top of the first die. The first die is located between the carrier wafer and the second die.

[0287] In some embodiments, the first contact structure and the second contact structure are formed by the following process (as described, for example, with respect to FIGS. 7H to 7M). The process includes forming a mask layer (e.g., mask layer 711 in FIG. 7G) on the first die, and etching the mask layer to form a first opening (e.g., opening 713 in FIG. 7G) and a second opening (e.g., opening 715 in FIG. 7G). Next, a first contact hole (e.g., contact hole 725 in FIG. 7H) and a second contact hole (e.g., contact hole 727 in FIG. 7H) extending along the first direction are formed. The first contact hole extends from the first opening to the first conductive layer, and the second contact hole extends from the second opening to the first conductive layer. The process further includes filling the first contact hole with a filling material (e.g., filling material 718 in FIG. 7I). The second contact hole is deepened until the second contact hole extends through the first conductive layer to the second conductive layer. The filling material in the first contact hole is removed. The process further includes forming respective insulating layers (e.g., outer layer 733 in FIG. 7M) in each of the first contact hole and the second contact hole. The process further includes forming a conductive structure in each of the insulating layers of the first contact hole and the second contact hole (e.g., by depositing a conductive material such as copper or tungsten on the first contact hole and the second contact hole). The first contact structure includes an insulating layer and a conductive structure in the first contact hole, and the second contact structure includes an insulating layer and a conductive structure in the second contact hole.

[0288] In some embodiments, forming the first contact structure and the second contact structure further includes etching the bottom of the insulating layer to expose the first conductive layer of the first die and the second conductive layer of the second die in the first contact hole and the second contact hole, respectively.

[0289] In some implementations, forming a first contact hole and a second contact hole involves etching the separation material in the first die using a first etching gas, and deepening the second contact hole involves etching the conductive material of the first conductive layer using a second etching gas different from the first etching gas.

[0290] In some implementation configurations, process 800 further includes forming a third bonding layer (e.g., bonding layer 743 in Figure 7N) on the upper surface of the first die opposite to the first bonding layer. The third bonding layer includes a conductive bonding contact (e.g., conductive bonding contact 742 in Figure 7N) and a dielectric material separating the conductive bonding contact. The first and second contact structures can be coupled to the conductive bonding contact.

[0291] In some implementations, process 800 further includes providing a base die (e.g., semiconductor structure 744 in Figure 7N). The base die includes a lower junction layer (e.g., junction layer 745 in Figure 7N) which includes conductive junction contacts (e.g., conductive junction contacts 746 in Figure 7N) and a dielectric material separating the conductive junction contacts. The base die may further include vias extending along a first direction. As described with respect to Figure 7N, process 800 may further include stacking the base die on a first die and bonding the lower junction layer of the base die to a third junction layer of the first die. The lower junction layer and the third junction layer can be bonded by bonding the dielectric material of the lower junction layer to the dielectric material of the third junction layer and bonding the conductive junction contacts of the lower junction layer to the conductive junction contacts of the third junction layer.

[0292] The subject matter and implementations of the actions and operations described in this disclosure may be implemented in digital electronic circuits, tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this disclosure and their structural equivalents, or one or more combinations thereof. The implementations of the subject matter described in this disclosure may be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier, for execution by a data processing device or for controlling the operation of a data processing device. The carrier may be a tangible, non-temporary computer storage medium. Alternatively or additionally, the carrier may be an artificially generated propagating signal, such as a machine-generated electrical signal, optical signal, or electromagnetic signal, generated to encode information for transmission to a suitable receiving device for execution by a data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage board, a random-access or serial-access memory device, or one or more combinations thereof, or a part thereof. The computer storage medium is not a propagating signal.

[0293] References in this disclosure such as “one embodiment,” “an embodiment,” “an example embodiment,” “some implementation,” and “some implementation” should be noted as indicating that while the described embodiments may include certain features, structures, or characteristics, not all embodiments may necessarily include those features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, where certain features, structures, or characteristics are described in relation to an embodiment, it is within the knowledge of those skilled in the art that such features, structures, or characteristics will be affected in relation to other implementations, whether explicitly stated or not.

[0294] In general, terms can be understood at least partially from their use in context. For example, the term “one or more” as used herein can be used, at least partially depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” can be understood, at least partially depending on the context, to convey either a singular or plural usage. Furthermore, the term “based on” may be understood not necessarily to convey an exclusive set of factors, but rather, at least partially depending on the context, to allow for the presence of additional factors that are not necessarily explicitly described.

[0295] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted most broadly, with “on” meaning not only “directly on” something, but also “on” something that has an intermediate feature or layer between them. Furthermore, “above” or “over” may mean not only “above” or “over” something, but also “above” or “over” something that has no intermediate feature or layer between them (i.e., directly on something).

[0296] Furthermore, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to facilitate explanations of the relationship between one element or feature and another, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or process steps, in addition to the orientation shown in the figures. The device may be oriented in other directions (it may be rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0297] As used herein, the term “substrate” refers to a material on which subsequent material layers are added. A substrate includes a “top” surface and a “bottom” surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise specified, semiconductor devices are formed on the upper side of the substrate. The bottom surface is opposite the top surface, and therefore, the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. Materials added onto the substrate may or may not be patterned. Furthermore, the substrate can include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, and indium phosphide. Alternatively, the substrate can be made from electrically noN+ conductive materials such as glass, plastic, or sapphire wafers.

[0298] As used herein, the term “layer” refers to a portion of a material that includes a region having thickness. A layer has an upper and a lower side, with the bottom of the layer being relatively close to the substrate and the upper side being relatively far from the substrate. A layer may extend over the entirety of a structure below or above it, or may have a smaller extent than the extent of the structure below or above it. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any set of horizontal surfaces between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along tapered surfaces. A substrate may be a layer, may contain one or more layers within it, and / or have one or more layers above, above, and / or below it. A layer may contain multiple layers. For example, an interconnection layer may include one or more conductive layers and contact layers (on which contacts, interconnection lines, and / or vertical interconnection accesses (VIA) are formed) and one or more dielectric layers.

[0299] As used herein, the term “nominal” refers to a desired or target value of a characteristic or parameter of a component or process step, set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. As used herein, the range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term “approximately” indicates a value of a given quantity that may vary based on a specific technology node related to the semiconductor device in question. Based on a specific technology node, “approximately” may indicate a value of a given quantity that varies within a range of, for example, 10 to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0300] In this disclosure, the terms “horizontal” mean nominally parallel to the side of the substrate, and the terms “perpendicular” or “perpendicular” mean nominally perpendicular to the side of the substrate.

[0301] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” such as NAND strings) on a laterally oriented substrate, such that the memory strings extend perpendicularly to the substrate.

[0302] This disclosure provides many different implementations or examples for implementing different features of the subject matter provided. For the sake of brevity of this disclosure, specific examples of components and arrangements are described below. Naturally, these are merely examples and are not intended to be limiting. For example, the formation of a first feature on a second feature in the following description may include implementations in which the first and second features can be in direct contact, and may also include implementations in which an additional feature can be formed between the first and second features so that the first and second features do not come into direct contact. Furthermore, this disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplification and clarity and does not in itself presuppose any relationships between the various implementations and / or configurations described.

[0303] The foregoing descriptions of specific implementations can be readily modified and / or adapted to various applications. Therefore, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementations, based on the teachings and guidance presented herein.

[0304] While this disclosure includes details of many specific implementations, these should not be interpreted as limitations on the scope of what is claimed as defined by the claims themselves, but rather as descriptions of features that may be specific to a particular implementation of a particular invention. Certain features described in this disclosure in the context of separate implementations may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may be implemented separately or in any suitable secondary combination in multiple implementations. Furthermore, features may be described above as acting in a particular combination and may be initially claimed as such, but one or more features from a claimed combination may, in some cases, be removed from the combination, and the claims may cover secondary combinations or variations of secondary combinations.

[0305] Similarly, while the operations are shown in the drawings and described in the claims in a specific order, this should not be understood as requiring that such operations be performed in a specific order shown, or in a sequential order, or that all illustrated operations be performed, in order to achieve the desired result. In certain circumstances, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described implementations should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged in multiple software products.

[0306] This document describes a specific implementation of the subject matter. Other implementations are also within the scope of the following claims. For example, the actions described in the claims can be performed in a different order, and the desired results can still be achieved. As an example, the process shown in the attached drawings does not necessarily require the specific order or sequence shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

[0307] The scope and width of this disclosure should not be limited by any of the typical implementations described above, but should be defined solely in accordance with the following claims and their equivalents.

Claims

1. It is a semiconductor device, A first layer, a second layer, a first die between the first layer and the second layer, and a second die, stacked on top of each other along a first direction, Each of the first die and the second die has a conductive layer. The first die and the second die are joined via the second layer, the first layer, the second layer, the first die between the first layer and the second layer, and the second die, A first contact structure bonded to the conductive layer of the first die, wherein the first contact structure extends along the first direction and contacts the conductive layer of the first die without extending through the second layer, A second contact structure bonded to the conductive layer of the second die, The second contact structure extends through the second layer along the first direction without extending through the second die, The second contact structure is a second contact structure that contacts the conductive layer of the second die without extending through the conductive layer of the first die, A semiconductor device equipped with the following features.

2. Equipped with an additional base die, The base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction. The semiconductor device according to claim 1, wherein the base die and the first die are joined via the first layer.

3. The semiconductor device according to claim 1 or 2, wherein the first end of the conductive layer of the first die and the first end of the conductive layer of the second die are offset along a second direction perpendicular to the first direction.

4. The semiconductor device according to any one of claims 1 to 3, wherein the second contact structure is located between the first end of the conductive layer of the first die and the first end of the conductive layer of the second die, along the second direction.

5. The semiconductor device according to any one of claims 1 to 4, wherein each of the first contact structure and the second contact structure is a continuous structure.

6. The second layer comprises at least one dielectric material and excludes conductive bonding contacts. The semiconductor device according to claim 2, wherein the first layer comprises a conductive bonding contact and at least one dielectric material separating the conductive bonding contact.

7. The second layer comprises an upper bonding layer and a lower bonding layer, each containing a dielectric material and excluding conductive bonding contacts. The dielectric material of the upper bonding layer of the second layer is bonded to the dielectric material of the lower bonding layer of the second layer. The first layer comprises an upper bonding layer and a lower bonding layer, each including a conductive bonding contact and a dielectric material separating the conductive bonding contact. The dielectric material of the upper bonding layer of the first layer is bonded to the dielectric material of the lower bonding layer of the first layer. The semiconductor device according to claim 6, wherein the conductive bonding contact of the upper bonding layer of the first layer is bonded to the conductive bonding contact of the lower bonding layer of the first layer.

8. The base die comprises a first via extending along the first direction and coupled to the conductive bonding contact of the first layer, The semiconductor device according to claim 6, wherein each of the first contact structure and the second contact structure is coupled to one of the first vias of the first layer via one of the conductive bonding contacts of the first layer.

9. Further equipped with a computing die and interposer, The semiconductor device according to claim 2, wherein the base die and the computing die are integrated at different positions of the interposer along a second direction perpendicular to the first direction.

10. The base die includes a first via coupled to the computing die via the interposer, The first via is coupled to a first conductive terminal on the surface of the interposer, The computing die is coupled to the second conductive terminal on the surface of the interposer, The semiconductor device according to claim 9, wherein the first conductive terminal and the second conductive terminal are coupled via conductive wires in the interposer.

11. The system includes a computing die and a third layer between the computing die and the base die. The computing die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction. The semiconductor device according to claim 2, wherein the base die and the computing die are joined via the third layer.

12. The semiconductor device according to claim 11, wherein the third layer includes a conductive bonding contact and at least one dielectric material separating the conductive bonding contact.

13. The third layer comprises an upper bonding layer and a lower bonding layer, each including a conductive bonding contact and a dielectric material separating the conductive bonding contact. The dielectric material of the upper bonding layer of the third layer is bonded to the dielectric material of the lower bonding layer of the third layer. The semiconductor device according to claim 12, wherein the conductive bonding contact of the upper bonding layer of the third layer is bonded to the conductive bonding contact of the lower bonding layer of the third layer.

14. The base die includes a first via coupled to the computing die, The computing die includes a second via that extends along the first direction and is coupled to the conductive bonding contact of the third layer, The semiconductor device according to claim 12, wherein the first via is coupled to the second via via the conductive bonding contact of the third layer.

15. The semiconductor device according to claim 11, further comprising an interposer, wherein the interposer, the computing die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction.

16. The semiconductor device according to claim 2, further comprising the first die, the second die, and the third die, the one furthest from the base die, along the first direction, wherein the thickness of the first die and the thickness of the second die are each smaller than the thickness of the third die along the first direction.

17. The semiconductor device according to claim 16, wherein the thickness of the first die and the thickness of the second die are each in the range of 3 micrometers (μm) to 20 μm.

18. The semiconductor device according to any one of claims 1 to 17, wherein the size of the cross-section of the second contact structure in the first die is larger than the size of the cross-section of the second contact structure in the second die, and the cross-section of the second contact structure in the first die and the cross-section of the second contact structure in the second die are perpendicular to the first direction.

19. The semiconductor device according to any one of claims 1 to 18, wherein the first contact structure and the second contact structure are formed by the same process.

20. The semiconductor device according to any one of claims 1 to 19, wherein each of the first contact structure and the second contact structure has a limiting dimension (CD) in the range of 0.5 μm to 10 μm.

21. At least one of the first die or the second die is A memory array comprising an array of memory cells, A semiconductor device according to any one of claims 1 to 20, comprising a peripheral circuit coupled to the memory array.

22. The semiconductor device according to claim 21, wherein at least one of the first die or the second die is a dynamic random access memory (DRAM) device.

23. The semiconductor device according to claim 2, wherein the base die comprises a control circuit configured to control the first die and the second die.

24. The stacked structure of the first die and the second die comprises a first device region, a second device region, and a connection region between the first device region and the second device region, along a second direction perpendicular to the first direction. Each of the first die and the second die comprises one or more memory arrays within the first device area and the second device area. The semiconductor device according to any one of claims 1 to 23, wherein the first contact structure and the second contact structure are located within the connection region.

25. The ratio of the size of the cross-section of the connection region to the sum of the first size of the cross-section of the first device region and the second size of the cross-section of the second device region is in the range of 1 / 6 to 1 / 5. The semiconductor device according to claim 24, wherein the cross-section of the connection region, the cross-section of the first device region, and the cross-section of the second device region are perpendicular to the first direction.

26. It is a semiconductor device, A base die, a first layer, a second layer, a first die between the first layer and the second layer, and a second die stacked on top of each other along a first direction, Each of the base die, the first die, and the second die has a conductive layer. The first die and the second die are joined together via the second layer. The base die and the first die are joined via the first layer, and the base die, first layer, second layer, first die between the first layer and the second layer, and second die, A first contact structure bonded to the conductive layer of the base die, wherein the first contact structure extends along the first direction and does not extend through the first layer, and contacts the conductive layer of the base die, A second contact structure bonded to the conductive layer of the first die, The second contact structure extends through the first layer along the first direction without extending through the second layer, The second contact structure is a second contact structure that contacts the conductive layer of the first die without extending through the conductive layer of the base die, A third contact structure bonded to the conductive layer of the second die, The third contact structure extends through the first layer and the second layer along the first direction, without extending through the second die. The third contact structure is a third contact structure that contacts the conductive layer of the second die without extending through the conductive layer of the first die, A semiconductor device equipped with the following features.

27. The semiconductor device according to claim 26, wherein the first end of the conductive layer of the first die and the first end of the conductive layer of the second die are offset along a second direction perpendicular to the first direction.

28. The semiconductor device according to claim 27, wherein the third contact structure is located along the second direction between the first end of the conductive layer of the first die and the first end of the conductive layer of the second die.

29. The semiconductor device according to any one of claims 26 to 28, wherein each of the first contact structure, the second contact structure, and the third contact structure is a continuous structure.

30. The second layer comprises at least one dielectric material and excludes conductive bonding contacts. The semiconductor device according to any one of claims 26 to 29, wherein the first layer comprises at least one dielectric material and excludes conductive junction contacts.

31. The second layer comprises an upper bonding layer and a lower bonding layer, each containing a dielectric material and excluding conductive bonding contacts. The dielectric material of the upper bonding layer of the second layer is bonded to the dielectric material of the lower bonding layer of the second layer. The first layer comprises an upper bonding layer and a lower bonding layer, each containing a dielectric material and excluding conductive bonding contacts. The semiconductor device according to claim 30, wherein the dielectric material of the upper junction layer of the first layer is bonded to the dielectric material of the lower junction layer of the first layer.

32. The base die includes an interconnection layer extending along a second direction perpendicular to the first direction, The semiconductor device according to claim 26, wherein each of the first contact structure, the second contact structure, and the third contact structure is coupled to the interconnection layer.

33. Further equipped with a computing die and interposer, The base die and the computing die are integrated at different positions of the interposer along the second direction, The semiconductor device according to claim 32, wherein the base die and the computing die are coupled via the interconnection layer and the interposer.

34. The interconnection layer is coupled to a first conductive terminal on the surface of the interposer. The computing die is coupled to the second conductive terminal on the surface of the interposer, The semiconductor device according to claim 33, wherein the first conductive terminal and the second conductive terminal are coupled via conductive wires in the interposer.

35. The system includes a computing die and a third layer between the computing die and the base die. The computing die, the third layer, the base die, the first layer, the first die, the second layer, and the second die are stacked along the first direction. The semiconductor device according to claim 32, wherein the base die and the computing die are joined via the third layer.

36. The semiconductor device according to claim 35, wherein the third layer includes a conductive bonding contact and at least one dielectric material separating the conductive bonding contact.

37. The third layer comprises an upper bonding layer and a lower bonding layer, each including a conductive bonding contact and a dielectric material separating the conductive bonding contact. The dielectric material of the upper bonding layer of the third layer is bonded to the dielectric material of the lower bonding layer of the third layer. The semiconductor device according to claim 36, wherein the conductive bonding contact of the upper bonding layer of the third layer is bonded to the conductive bonding contact of the lower bonding layer of the third layer.

38. The computing die includes vias that extend along the first direction and are coupled to the conductive bonding contacts of the third layer, The semiconductor device according to claim 36, wherein the interconnection layer of the base die is coupled to the vias of the third layer via the conductive bonding contacts.

39. The semiconductor device according to claim 35, further comprising an interposer, wherein the interposer, the computing die, the base die, the first die, and the second die are stacked along the first direction.

40. The semiconductor device according to claim 26, further comprising the first die, the second die, and the third die, the one furthest from the base die, along the first direction, wherein the thickness of the first die and the thickness of the second die are each smaller than the thickness of the third die along the first direction.

41. The semiconductor device according to claim 40, wherein the thickness of the first die and the thickness of the second die are each in the range of 3 micrometers (μm) to 20 μm.

42. The semiconductor device according to any one of claims 26 to 41, wherein the size of the cross-section of the second contact structure in the first die is larger than the size of the cross-section of the second contact structure in the second die, and the cross-section of the second contact structure in the first die and the cross-section of the second contact structure in the second die are perpendicular to the first direction.

43. The semiconductor device according to any one of claims 26 to 42, wherein the first contact structure and the second contact structure are formed by the same process.

44. The semiconductor device according to any one of claims 26 to 43, wherein each of the first contact structure and the second contact structure has a limiting dimension (CD) in the range of 0.5 μm to 10 μm.

45. At least one of the first die or the second die is A memory array comprising an array of memory cells, A semiconductor device according to any one of claims 26 to 44, comprising a peripheral circuit coupled to the memory array.

46. The semiconductor device according to claim 45, wherein at least one of the first die or the second die is a dynamic random access memory (DRAM) device.

47. The semiconductor device according to any one of claims 26 to 46, wherein the base die comprises a control circuit configured to control the first die and the second die.

48. The stacked structure of the first die and the second die comprises a first device region, a second device region, and a connection region between the first device region and the second device region, along a second direction perpendicular to the first direction. Each of the first die and the second die comprises one or more memory arrays within the first device area and the second device area. The semiconductor device according to any one of claims 26 to 47, wherein the first contact structure and the second contact structure are located within the connection region.

49. The ratio of the size of the cross-section of the connection region to the sum of the first size of the cross-section of the first device region and the second size of the cross-section of the second device region is in the range of 1 / 6 to 1 / 5. The semiconductor device according to claim 48, wherein the cross-section of the connection region, the cross-section of the first device region, and the cross-section of the second device region are perpendicular to the first direction.

50. It is a method, To provide a first die and a second die, wherein the first die comprises a conductive layer and at least a first bonding layer, and the second die comprises a conductive layer and at least a second bonding layer. The second die is stacked on the first die along a first direction, Bonding the second bonding layer of the second die to the first bonding layer of the first die, To form a first contact structure and a second contact structure extending along the first direction, The first contact structure contacts the conductive layer of the first die, The second contact structure extends through the first bonding layer of the first die and the second bonding layer of the second die, The second contact structure contacts the conductive layer of the second die without contacting the conductive layer of the first die, Methods that include...

51. The method according to claim 50, wherein the first bonding layer of the first die and the second bonding layer of the second die each contain a dielectric material and exclude conductive bonding contacts.

52. Laminating the second die on the first die along the first direction is, The method according to claim 50 or 51, comprising aligning the second die with the first die such that the first end of the conductive layer of the first die and the first end of the conductive layer of the second die are offset along a second direction perpendicular to the first direction.

53. To provide the first die, The method according to any one of claims 50 to 52, comprising thinning the first die by thinning the substrate contained in the first die.

54. The method according to claim 52, further comprising stacking the first die on a carrier wafer, wherein the first die is located between the carrier wafer and the second die.

55. The first contact structure and the second contact structure are formed by the same process, the process is To form a first contact hole and a second contact hole, An insulating layer is formed in each of the first and second contact holes, The method according to any one of claims 50 to 54, comprising forming a first contact structure and a second contact structure by forming a conductive structure within the insulating layer of each of the first contact hole and the second contact hole, wherein the first contact structure includes the insulating layer and the conductive structure within the first contact hole, and the second contact structure includes the insulating layer and the conductive structure within the second contact hole.

56. The method according to claim 55, wherein the first contact hole and the second contact hole are formed during the same etching process.

57. Forming a mask layer on the first die, The mask layer is etched to form a first opening and a second opening, wherein the first contact hole extends from the first opening to the conductive layer of the first die, and the second contact hole extends from the second opening to the conductive layer of the second die. The method according to claim 55, further comprising:

58. The method according to any one of claims 50 to 57, further comprising forming a third bonding layer on the first die, wherein the third bonding layer comprises a conductive bonding contact and a dielectric material separating the conductive bonding contact.

59. The method according to claim 58, further comprising providing a base die, the base die comprising a lower bonding layer including a conductive bonding contact and a dielectric material separating the conductive bonding contact.

60. The method according to claim 59, further comprising bonding the dielectric material of the lower bonding layer of the base die to the dielectric material of the third bonding layer of the first die, and bonding the conductive bonding contact of the lower bonding layer of the base die to the conductive bonding contact of the third bonding layer of the first die, thereby stacking the base die on the first die.

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