Loop index set merging optimization for program instructions

Abstract

A computer implementation method for merging loops. Multiple processor units identify loops in computer code. A loop is a sequence of instructions that is repeated until a condition about the loop is met. Multiple processor units create a tree containing nodes representing loops and edges representing the relationships between nodes. Multiple processor units use the tree to identify candidate loop pairs from sibling nodes. In response to whether a candidate loop pair is eligible for merging, multiple processor units create a new loop from the candidate loop pair using an expanded iteration space based on the iteration space of the candidate loop pair.

Description

Technical Field

[0001] The present disclosure generally relates to improved computer systems, and more specifically to loop optimization of program instructions.

[0002] Loop optimization is used in computer programming to improve the performance of loops in program instructions. A loop is a repetitive block of program instructions and can be used to operate on data a certain number of times. These operations can include performing calculations, conversions, or other operations on the data.

[0003] Prior to compiling program instructions to form executable code, various optimizations can be performed on loops in the program instructions. These optimizations can be performed to obtain code size reduction, reduce the execution time for the loop, reduce memory access, improve code efficiency, and improve other performance.

[0004] Loop optimization techniques include loop fusion, loop distribution, loop unrolling and jam, and other types of loop optimization techniques. Loop fusion involves combining two or more loops into a single loop that stores instructions from both loops. Loop distribution involves breaking down a single loop into multiple loops that can be executed in parallel. Loop unrolling and jam involves unrolling the loop body multiple times, with each unrolled version executing a subset of the original iterations in the loop. These unrolled loops can then be combined into a single loop.

[0005] These types of loop optimization techniques can yield improved performance for many traditional workloads, including performance computing and scientific computer programs. However, these different types of loop optimization may not provide the desired optimization of loops in program instructions in all situations. [Overview of the project]

[0006] According to one exemplary embodiment, a computer implementation method merges loops. Multiple processor units identify loops in computer code. A loop is a sequence of instructions that is repeated until a condition about the loop is met. Multiple processor units create a tree containing nodes representing loops and edges representing the relationships between nodes. Multiple processor units use the tree to identify candidate loop pairs from sibling nodes. In response to whether a candidate loop pair is eligible for merging, multiple processor units create a new loop from the candidate loop pair using an expanded iteration space based on the iteration space for the candidate loop pair.

[0007] According to other exemplary embodiments, computer systems and computer program products for merging loops are provided. As a result, exemplary embodiments offer the technical benefit of reducing code size.

[0008] In exemplary embodiments, a plurality of processor units can, permissibly, determine whether a pair of candidate loops is eligible for merging using eligibility factors that include: both loops follow a structured control flow principle; both loops are monotonically variable; and there is no intervening code between the candidate loop pair, or, if intervening code exists, the intervening code has no dependency on either loop in the candidate loop pair. As a result, exemplary embodiments can provide the technical benefit of improved performance when identifying candidate loops for merging to reduce code size.

[0009] In an exemplary embodiment, multiple processor units can, permissibly, determine whether or not to merge pairs of candidate loops and form a new loop using the desired set. As a result, the exemplary embodiment provides the technical effect of improving performance by identifying candidate loops that offer greater code size reduction.

[0010] An exemplary embodiment can, to some extent, parse the tree and use reverse breadth-first traversal to identify candidate loop pairs from sibling nodes, where the candidate loop pairs are eligible for merging. As a result, the exemplary embodiment provides the technical effect of improving performance by identifying a larger number of candidate loops for merging, which leads to a greater reduction in code size.

[0011] According to another exemplary embodiment, a computer implementation method merges loops. Multiple processor units identify loops in computer code. A loop is a sequence of instructions that is repeated until a defined condition is met. Multiple processor units create a tree containing nodes for each loop, where each loop represents the structure of the loop in an intermediate representation. Multiple processor units parse the tree to identify pairs of candidate loops containing adjacent sibling loops that are eligible to merge. Multiple processor units parse the loop bodies for the candidate loops to identify isomorphic pairs of operations stored within the candidate loops. Multiple processor units create a new loop from the candidate loops, where the loop body of the new loop contains isomorphic operations taken from the candidate loops.

[0012] According to another exemplary embodiment, a computer system for merging loops is provided. As a result, the exemplary embodiment provides the technical benefit of reducing code size. [Brief explanation of the drawing]

[0013] [Figure 1] This is a block diagram of a computing environment according to an exemplary embodiment.

[0014] [Figure 2] This is a block diagram of a loop optimization environment according to an exemplary embodiment.

[0015] [Figure 3] This is a flowchart illustrating the generation of a tree from computer code according to an exemplary embodiment.

[0016] [Figure 4] This is a flowchart of the process for merging loops using a loop tree representation, according to an exemplary embodiment.

[0017] [Figure 5] A flowchart of a process for applying rewrite mapping rules to create new operations for the loop body of a new loop according to an exemplary embodiment.

[0018] [Figure 6] A flowchart of a process for determining whether merging a pair of candidate loops meets the objective according to an exemplary embodiment.

[0019] [Figure 7] A flowchart of a process for merging loops according to an exemplary embodiment.

[0020] [Figure 8] A flowchart of a process for merging loops according to an exemplary embodiment.

[0021] [Figure 9] A flowchart of a process for analyzing loops according to an exemplary embodiment.

[0022] [Figure 10] A flowchart of a process for determining whether a pair of candidate loops is eligible for merging according to an exemplary embodiment.

[0023] [Figure 11] A flowchart of a process for creating a new loop according to an exemplary embodiment.

[0024] [Figure 12] A flowchart of a process for determining whether a pair of candidate loops should be merged according to an exemplary embodiment.

[0025] [Figure 13]This is a flowchart for determining whether or not to merge candidate loop pairs, according to an exemplary embodiment.

[0026] [Figure 14] This is a flowchart of a process for analyzing a tree, according to an exemplary embodiment.

[0027] [Figure 15] This is a flowchart of the process for merging loops according to an exemplary embodiment.

[0028] [Figure 16] This is a diagram of a process flow for creating a new loop from a pair of candidate loops, according to an exemplary embodiment.

[0029] [Figure 17] This is a diagram of a process flow for creating a new loop from a pair of candidate loops, according to an exemplary embodiment.

[0030] [Figure 18] This is a diagram of a process flow for creating a new loop from a pair of candidate loops without using an inducement variable in operation, according to an exemplary embodiment.

[0031] [Figure 19] This is a diagram of a process flow for creating a new loop from a pair of candidate loops having a contiguous iterative space, according to an exemplary embodiment.

[0032] [Figure 20] This diagram illustrates a process flow for creating a new loop from a pair of candidate loops that include both isomorphic and non-isomorphic operations, according to an exemplary embodiment.

[0033] [Figure 21]This is a diagram of a process flow for creating a new loop from a loop that includes isomorphic operation without an inductive variable, according to an exemplary embodiment.

[0034] [Figure 22] This is a diagram of a process flow for creating a new loop from a pair of candidate loops, including an induction variable and an isomorphic operation having a continuous iterative space, according to an exemplary embodiment.

[0035] [Figure 23] This is a diagram of a process flow for creating a new loop from a pair of candidate loops, including isomorphic operation with different inducers and consecutive iteration spaces, according to an exemplary embodiment.

[0036] [Figure 24] This is a diagram of a process flow for generating pairs of candidate loops having contiguous iteration spaces by shifting the iteration space of candidate loops, according to an exemplary embodiment.

[0037] [Figure 25] This is a block diagram of a data processing system according to an exemplary embodiment. [Modes for carrying out the invention]

[0038] Various aspects of this disclosure are described by explanatory text, flowcharts, block diagrams of computer systems and / or block diagrams of machine logic included in computer program product (CPP) embodiments. With respect to any flowchart, depending on the technology involved, operations may be performed in a different order than those shown in a given flowchart. For example, again depending on the technology involved, two operations shown in consecutive flowchart blocks may be performed in reverse order, as a single integrated stage, simultaneously, or with at least partial time overlap.

[0039] Computer program product embodiment ("CPP embodiment" or "CPP") is a term used in this disclosure to describe any set of one or more storage media (also called "mediums") that collectively comprise a set of one or more storage devices that collectively comprise machine-readable code corresponding to instructions and / or data for performing computer operations specified in a given CPP claim. A "storage device" is any tangible device capable of holding and storing instructions for use by a computer processor. Computer-readable storage media may be, without limitation, electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, mechanical storage media, or any suitable combination of those described above. Some known types of storage devices, including these media, include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices (such as pits / lands formed on the main surface of a punch card or disk), or any suitable combination of the foregoing. When the term "computer-readable storage medium" is used in this disclosure, it shall not be interpreted as storage in the form of a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, optical pulses passing through optical fiber cables, electrical signals communicated through wires, and / or other transmission media.As those skilled in the art will understand, data is typically moved at several intermittent points during the normal operation of a storage device, such as during access, defragmentation, or garbage collection; however, data is not transient while it is stored, and therefore, a storage device is not transient.

[0040] Referring here to the figures, and in particular to Figure 1, a block diagram of a computing environment according to an exemplary embodiment is shown. The computing environment 100 includes an example of an environment for executing at least a portion of the computer code involved in executing the methods of the present invention, such as a loop optimizer 190. In this exemplary example, the loop optimizer 190 can optimize program instructions by merging loops that are candidates for merging into the loop optimizer 190, and the computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end user device (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, the computer 101 includes a processor set 110 (including processing circuits 120 and cache 121), a communication fabric 111, volatile memory 112, persistent storage 113 (including an operating system 122 and a loop optimizer 190 as identified above), a peripheral device set 114 (including a user interface (UI) device set 123, storage 124, and an Internet of Things (IoT) sensor set 125), and a network module 115. The remote server 104 includes a remote database 130. The public cloud 105 includes a gateway 140, a cloud orchestration module 141, a host physical machine set 142, a virtual machine set 143, and a container set 144.

[0041] Computer 101 may take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device currently known or to be developed in the future that is capable of running programs, accessing networks, or querying databases such as remote database 130. As is well understood in the field of computer technology, and depending on the technology, the execution of the computer implementation method may be distributed among multiple computers and / or across multiple locations. On the other hand, in this presentation of the computing environment 100, in order to keep the presentation as concise as possible, the detailed discussion focuses on a single computer, specifically computer 101. Computer 101 is not shown in the cloud in Figure 1, but it may be located in the cloud. On the other hand, computer 101 is not required to be located in the cloud, except to any extent that can be definitively shown.

[0042] The processor set 110 includes one or more computer processors of any type currently known or to be developed in the future. The processing circuitry 120 may be distributed across multiple packages, for example, multiple coordinated integrated circuit chips. The processing circuitry 120 may implement multiple processor threads and / or multiple processor cores. The cache 121 is memory located within the processor chip package and is typically used for data or code that should be available for high-speed access by threads or cores running on the processor set 110. The cache memory is typically organized into multiple levels, depending on its relative proximity to the processing circuitry. Alternatively, some or all of the cache for the processor set may be located "off-chip". In some computing environments, the processor set 110 may function using qubits and be designed to perform quantum computing.

[0043] Computer-readable program instructions typically cause the processor set 110 of computer 101 to execute a series of operational steps, thereby loading them onto computer 101 to implement a computer implementation method, and thereby the instructions thus executed instantiate the methods specified in the flowcharts and / or descriptions of the computer implementation methods contained herein (collectively referred to as the "Methods of the Invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as a cache 121 and other storage media discussed below. The program instructions and associated data are accessed by the processor set 110 to control and direct the execution of the Methods of the Invention. In the computing environment 100, at least some of the instructions for executing the Methods of the Invention may be stored in a loop optimizer 190 in persistent storage 113.

[0044] The communication fabric 111 is a signal conduction path that enables various components of the computer 101 to communicate with one another. Typically, this fabric is made up of switches and conductive paths, such as buses, bridges, physical input / output ports, and similar switches and conductive paths. Other types of signal communication paths, such as optical fiber communication paths and / or wireless communication paths, may be used.

[0045] The volatile memory 112 is any type of volatile memory currently known or to be developed in the future. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, the volatile memory 112 is characterized by random access, but this is not required unless explicitly stated. In computer 101, the volatile memory 112 is located in a single package and resides inside computer 101, but alternatively or in addition, the volatile memory may be distributed across multiple packages and / or located externally to computer 101.

[0046] The persistent storage 113 is any form of non-volatile storage for a computer, currently known or to be developed in the future. The non-volatility of this storage means that the stored data is maintained whether or not power is directly supplied to the computer 101 and / or the persistent storage 113. The persistent storage 113 may be read-only memory (ROM), but typically, at least a portion of the persistent storage allows for writing, deleting, and rewriting of data. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. The operating system 122 may take several forms, such as various known proprietary operating systems or open-source portable operating system interface (CSI) type operating systems employing a kernel. The code included in the loop optimizer 190 includes at least a portion of the computer code involved in performing the method of the present invention.

[0047] The peripheral device set 114 includes a set of peripheral devices of the computer 101. Data communication connections between the peripheral devices of the computer 101 and other components may be implemented in various ways, such as Bluetooth connections, near-field communication (NFC) connections, connections made by cables (such as universal serial bus (USB) type cables), insert-type connections (e.g., secure digital (SD) cards), connections made via local area communication networks, and even connections made via wide area networks such as the internet. In various embodiments, the UI device set 123 may include components such as a display screen, speaker, microphone, wearable devices (such as goggles and smartwatches), keyboard, mouse, printer, touchpad, game controller, and haptic device. Storage 124 is external storage such as an external hard drive, or insertable storage such as an SD card. Storage 124 may be persistent and / or volatile. In some embodiments, storage 124 may take the form of a quantum computing memory device for storing data in the form of qubits. In embodiments where computer 101 is required to have a large amount of storage (for example, computer 101 locally stores and manages a large database), this storage may be provided by peripheral storage devices designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 125 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another may be a motion detector.

[0048] The network module 115 is a collection of computer software, hardware, and firmware that enables computer 101 to communicate with other computers via the WAN 102. The network module 115 may include hardware such as a modem or Wi-Fi signal transceiver, software for packetizing and / or depacketizing data for transmission over a communication network, and / or web browser software for communicating data over the internet. In some embodiments, the network control and network forwarding functions of the network module 115 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN)), the control and forwarding functions of the network module 115 are performed on physically separate devices, such that the control function manages several different network hardware devices. Computer-readable program instructions for performing the method of the present invention can typically be downloaded from an external computer or external storage device to computer 101 through a network adapter card or network interface included in the network module 115.

[0049] WAN102 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances by any currently known or future-developed technology for transmitting computer data. In some embodiments, WAN102 may be replaced and / or supplemented by a local area network (LAN), such as a Wi-Fi network, designed to transmit data between devices located in a local area. WANs and / or LANs typically include computer hardware such as copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0050] The end-user device (EUD) 103 is any computer system used and controlled by an end-user (e.g., a customer of the company operating computer 101) and can take any of the forms discussed above in relation to computer 101. Typically, EUD 103 receives useful and valuable data from the operation of computer 101. For example, in a hypothetical case where computer 101 is designed to provide recommendations to the end-user, these recommendations would typically be communicated from the network module 115 of computer 101 to EUD 103 via WAN 102. In this way, EUD 103 can display or otherwise present the recommendations to the end-user. In some embodiments, EUD 103 may be a client device such as a thin client, heavy client, mainframe computer, or desktop computer.

[0051] The remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. The remote server 104 may be controlled and used by the same entity that operates computer 101. The remote server 104 represents a machine that collects and stores useful and valuable data for use by other computers, such as computer 101. For example, in the hypothetical case where computer 101 is designed and programmed to provide recommendations based on historical data, this historical data may be provided to computer 101 from the remote database 130 of the remote server 104.

[0052] The public cloud 105 is any computer system available for use by multiple entities, providing on-demand availability of computer system resources and / or other computing capabilities, particularly data storage (cloud storage) and computing power, without direct active management by the user. Cloud computing typically leverages resource sharing to achieve coherence and economies of scale. Direct active management of the computing resources of the public cloud 105 is performed by the computer hardware and / or software of the cloud orchestration module 141. The computing resources provided by the public cloud 105 are typically implemented by virtual computing environments running on various computers that make up the computers of the host physical machine set 142, which is the universe of physical computers available in and / or to the public cloud 105. The virtual computing environment (VCE) typically takes the form of virtual machines from the virtual machine set 143 and / or containers from the container set 144. These VCEs may be stored as images and are understood to be transferable either as images or after instantiation of the VCE, among and between various physical machine hosts. The cloud orchestration module 141 manages the transfer and storage of images, deploys new VCE instances, and manages active instances of the VCE deployment. The gateway 140 is a collection of computer software, hardware, and firmware that enables the public cloud 105 to communicate over the WAN 102.

[0053] Here, some further explanation of virtualized computing environments (VCEs) is provided. A VCE can be stored as an "image." A new active instance of a VCE can be instantiated from an image. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature in which the kernel allows for the existence of multiple isolated user-space instances called containers. These isolated user-space instances typically behave as actual computers from the perspective of the programs running in them. Computer programs running on a normal operating system can utilize all of that computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running inside a container can only use the contents of the container and the devices allocated to the container; this feature is known as containerization.

[0054] The private cloud 106 is similar to the public cloud 105, except that its computing resources are available only for use by a single enterprise. While the private cloud 106 is shown as communicating with the WAN 102, in other embodiments, the private cloud may be completely isolated from the internet and accessible only via a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types), often implemented by different vendors. Each of the multiple clouds remains a separate discrete entity, but the larger hybrid cloud architecture is coupled by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the multiple configuration clouds. In this embodiment, both the public cloud 105 and the private cloud 106 are part of a larger hybrid cloud.

[0055] The exemplary embodiments, as described herein, recognize and take into account several different considerations. For example, there is growing emphasis and popularity in areas such as artificial intelligence (AI), domain-specific programming, and domain-specific language (DSL).

[0056] Using these types of languages, compilers of program instructions encounter new instruction patterns that may require further optimizations to achieve better performance. An exemplary example is the use of loop index set merging (LISM) techniques to reduce code size and create many other significant optimization opportunities in computer programs. These optimizations may be particularly useful for programs expressed in AI-DSL. This type of loop index set optimization may be a further technique useful for both existing types of programs and technologies such as artificial intelligence.

[0057] In one exemplary example, the Loop Set Index Merging (LSIM) technique identifies loops in computer code. A loop is a sequence of instructions that is repeated until a condition about the loop is met. The process creates a tree containing nodes representing loops and edges representing the relationships between nodes. The process parses the tree to identify candidate loop pairs among sibling nodes. In response to whether a candidate loop pair is eligible for merging, the process creates a new loop from the candidate loop pair using an expanded iteration space based on the iteration space of the candidate loop pair. In this example, the expanded iteration space is the iteration space that encompasses the iterations of the two candidate loops being merged into the new loop. The expanded iteration space contains all combinations of loop index values ​​that can be nested within the two candidate loops being merged into the new loop.

[0058] Referring now to Figure 2, a block diagram of a loop optimization environment according to an exemplary embodiment is shown. In this example, the loop optimization environment 200 includes components that may be implemented in hardware such as the hardware shown in the computing environment 100 of Figure 1.

[0059] In this exemplary example, the loop processing system 202 in the loop optimization environment 200 can optimize loop 203 in computer code 204. Computer code 204 includes a set of instructions or commands written in a programming language. In this example, computer code 204 can be compiled to form executable code for a program or application.

[0060] The loop processing system 202 can combine loop 203 and computer code 204 by implementing a stage for the Loop Index Set Merging (LISM) process. As shown, the loop processing system 202 includes a computer system 212 and a loop optimizer 214. In this example, computer code 204 can be compiled and executed on computer system 212 or on another computer system.

[0061] The loop optimizer 214 can be implemented in software, hardware, firmware, or a combination thereof. When software is used, the operations performed by the loop optimizer 214 can be implemented in program instructions configured to run on hardware such as a processor unit. When firmware is used, the operations performed by the loop optimizer 214 can be implemented in program instructions and data and stored in persistent memory for execution on a processor unit. When hardware is employed, the hardware may include circuits that operate to perform the operations of the loop optimizer 214.

[0062] In exemplary examples, hardware can take the form of at least one of the following: a circuit system, an integrated circuit, an application-specific integrated circuit (ASIC), a programmable logic device, or any other suitable type of hardware configured to perform multiple operations. With programmable logic devices, the device can be configured to perform multiple operations. The device can be reconfigured at a later point in time, or it can be permanently configured to perform multiple operations. Programmable logic devices include, for example, programmable logic arrays, programmable array logic, field-programmable logic arrays, field-programmable gate arrays, and other suitable hardware devices. In addition, processes can be implemented in organic components integrated with inorganic components, or entirely composed of organic components excluding human elements. For example, a process can be implemented as a circuit within an organic semiconductor.

[0063] As used herein, “multiple” means one or more items when used in reference to an item. For example, “multiple actions” means one or more actions.

[0064] Furthermore, the phrase "at least one of" when used with a list of items means that one or more different combinations of the listed items can be used, and that only one of each item in the list may be required. In other words, "at least one of" means that any combination and number of items can be used from the list, but not all items in the list are required. An item can be a specific object, thing, or category.

[0065] For example, without limitation, “at least one of item A, item B, or item C” may include item A, item A and item B, or item B. This example may also include item A, item B and item C, or item B and item C. Naturally, any combination of these items is possible. In some exemplary examples, “at least one of ~” could be, for example, two item A; one item B; and ten item C; four item B and seven item C; or any other suitable combination.

[0066] The computer system 212 is a physical hardware system and includes one or more data processing systems. If there are more than one data processing systems in the computer system 212, those data processing systems communicate with each other using a communication medium. The communication medium can be a network. The data processing systems can be selected from at least one of the following: computers, server computers, tablet computers, or any other suitable data processing system.

[0067] As shown, the computer system 212 includes a plurality of processor units 216 capable of executing program instructions 218 that implement the process in the exemplary example. In other words, the program instructions 218 are computer-readable program instructions.

[0068] As used herein, a processor unit in a plurality of processor units 216 is a hardware device and consists of hardware circuits, such as those on an integrated circuit, that respond to and process program instructions that operate the computer. A processor unit can be implemented using the processor set 110 in Figure 1. When a plurality of processor units 216 execute program instructions 218 for a process, the plurality of processor units 216 can be one or more processor units located in the same computer or in different computers. In other words, a process can be distributed among processor units 216 on the same or different computers in the computer system 212.

[0069] Furthermore, the multiple processor units 216 can be of the same type or different types. For example, the multiple processor units 216 can be at least one of the following: single-core processors, dual-core processors, multi-processor cores, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), or any other type of processor unit.

[0070] In one exemplary example, the loop optimizer 214 can improve the performance of the computer code 204 by merging loops 203. When optimizing the computer code 204, the loop optimizer 214 can identify loops 203 in the computer code 204. In this example, loop 203 is a sequence of instructions that are repeated until a condition for loop 203 is met. One loop in loop 203 can also be a nested loop in which the data flow contains another loop. The loop contained within the nested loop may be called the inner loop.

[0071] The loop optimizer 214 creates a tree 220 containing nodes 222 representing loops 203 and edges 224 representing the relationships between nodes 222. The tree 220 can be a tree abstraction created from an intermediate representation (IR) 230 of computer code 204. This intermediate representation can be a form of computer code 204 that is closer to machine code that can be executed by the processor unit 216. Using the intermediate representation (IR) can make the analysis of computer code 204 in the tree 220 easier to perform.

[0072] In this example, node 222 may represent structure 232 for loop 203. For example, a node may contain information representing the structure of the loop represented by the node. A structure may contain, for example, identification information for an index variable and a set of values ​​for an index value variable. In some illustrative examples, a structure may contain or point to program instructions for a loop.

[0073] In this illustrative example, the loop optimizer 214 analyzes the tree 220. For example, the loop optimizer 214 analyzes the tree 220 to identify pairs of candidate loops 226 from sibling nodes 228 at node 222 in the tree 220. Furthermore, in this illustrative example, sibling node 228 is node 222, which shares the same parent node. Sibling nodes 228 can be at the same level or depth in the tree 220.

[0074] The loop optimizer 214 can evaluate pairs of candidate loops 226 to determine whether they are eligible for merging to form a new loop 234. In this exemplary example, the loop optimizer 214 can perform this evaluation using an eligibility factor 231. In this example, the eligibility factor 231 for a pair of candidate loops 226 to be eligible for merging includes: (1) both loops follow the structured control flow principle; (2) both loops are monotonically variable; and (3) there is no intervening code between the pair of candidate loops 226, or, if there is intervening code between the pair of candidate loops 226, the intervening code has no dependency on either loop in the pair of candidate loops 226.

[0075] In this example, the structured control flow principle is the principle that loops should follow. These principles can be based on rules or best practices in the field of computer programming. The principle can be based on the concept that the structure of code should be easy to read, understand, and maintain. For example, a pair of loops 203 can be considered to follow the structured control flow principle 233 if the pair of loops 203 is a natural loop with a single exit. Monotonically changing can mean that the value of an inducer variable is always increasing or always decreasing. These inducer variables can also be called index variables or indices for the loop.

[0076] In this example, the absence of intervening code means that there is no code between the bodies of the candidate loop pair 226. Furthermore, in this example, the absence of dependency means that the intervening code does not depend on any of the loop's behaviors.

[0077] Other eligibility factors in eligibility factor 231 may include whether the upper limit of the merged loop overflows the loop count register of the target hardware. The overflow can be detected at compile time, when the two candidate loops have static trip counts. In other words, these factors may include determining whether a runtime error could occur by merging the pair of candidate loops 226 together.

[0078] When identifying pairs of candidate loops 226 using sibling nodes 228, the loop optimizer 214 can perform this analysis by starting from the bottom of tree 220 using inverse width-first traversal.

[0079] In response to the fact that the pair of candidate loops 226 is eligible for merging, the loop optimizer 214 creates a new loop 234 from the pair of candidate loops 226 using the expanded iteration space 236, based on the iteration space 239 for the pair of candidate loops 226. The new loop 234 replaces the pair of candidate loops 226 in loop 203 in the computer code 204.

[0080] In this illustrative example, the iteration space for one loop in loop 203 refers to the set of all possible values ​​that one or more inductive variables can take during the execution of that loop. In other words, the iteration space can include values ​​for the set of inductive variables in a nested loop. The extended iteration space 236 for the new loop 234 includes all values ​​for the inductive variables in the pair of candidate loops 226. The inductive variables are used to track the iteration count in the loop.

[0081] The loop optimizer 214 can analyze the tree 220 to find additional pairs of sibling nodes 228 and repeat this process. For example, the loop optimizer 214 can repeatedly analyze the tree 220 to identify pairs of candidate loops 226, and for each pair of sibling nodes 228 in the tree 220, create a new loop 234 from the candidate loop 226 pair.

[0082] When creating a new loop 234, the loop optimizer 214 can analyze pairs of candidate loops 226. For example, the loop optimizer 214 can analyze the loop body 238 for a pair of candidate loops 226 to identify pairs of isomorphic actions 242 stored in the loop body 238 for a pair of candidate loops 226. In this exemplary example, an action is isomorphic if it can be performed with another action in the merged loop unconditionally with respect to the new values ​​of the loops into which the actions are merged. In other words, an action is isomorphic if, when performed in the expanded iterative space of the merged loop, it can produce a semantically equivalent effect without requiring it to be guarded based on which set of indices it belongs to.

[0083] Another way to describe isomorphic behavior is when both actions produce the same value and / or side effects. For example, calling a function at the beginning of each loop body (without side effects) using the same loop invariant arguments in both loops is considered isomorphic. Another example is when both actions read from a single memory buffer filled by an external process synchronized with each load in the compiled program.

[0084] In this exemplary example, the loop optimizer 214 creates a new loop 234 having a loop body 240 containing isomorphic actions 242 from pairs of isomorphic actions 242 identified in the pair of candidate loops 226.

[0085] In addition, the non-isomorphic operation 246 may exist in the loop body 238. In this example, the loop optimizer 214 can apply the rewrite mapping rule 248 to create a new operation 250 for the loop body 240 in the new loop 234 using the non-isomorphic operation 246 and the loop body 238 from the candidate loop 226. In some cases, the loop optimizer 214 can also apply the rewrite mapping rule 248 to create a new operation 250 from the isomorphic operation 242.

[0086] In another exemplary example, once it is determined that a pair of candidate loops 226 are eligible for merging, an additional analysis can be performed using a set of objectives 252 to determine whether the pair of candidate loops 226 should be merged. The set of objectives may include at least one of the following: code size reduction, parallelism granularity, full loop nesting, service level objectives for computer code, isomorphic vs. non-isomorphic behavior thresholds, or other objectives.

[0087] For example, the loop optimizer 214 can determine the ratio of isomorphic actions 242 to non-isomorphic actions 246 for a pair of candidate loops 226. Based on whether the ratio of isomorphic actions 242 to non-isomorphic actions 246 is higher than a threshold, the loop optimizer 214 can decide whether or not to create a new loop 234 from the pair of candidate loops 226.

[0088] In one exemplary example, there exists one or more technical solutions to overcome the technical problem of optimizing the code that stores loops. As a result, one or more technical solutions may provide a technical effect that provides a way to merge loops in a manner that reduces code size. In one or more exemplary examples, candidate loops are identified from sibling nodes in a tree where the nodes represent loops and the edges represent their nesting and relationships with other loops. Candidate loops are evaluated to determine whether they are eligible to be merged. Candidate loops that are eligible to be merged may also be evaluated to determine whether merging those loops would satisfy a desired set.

[0089] When a decision is made to merge candidate loops, a new loop is created using an expanded iteration space that encompasses the iteration spaces of each of the loops being merged into the new loop. In addition, pairs of isomorphic behaviors are identified in the candidate loop pairs. These behaviors are included in the body of the new loop, and in some cases, this may involve some rewriting. If non-isomorphic behaviors exist, these are rewritten in the body of the new loop using rewrite mapping rules. The old loop is removed, and the new loop is added to the code.

[0090] Similar modifications can be made to the tree representing loops in the code. This updated tree can then be further analyzed to determine whether sibling nodes exist, which can be used to decide whether another pair of candidate loops can be merged. This process can significantly increase the reduction in code size.

[0091] Computer system 212 can be configured using software, hardware, firmware, or a combination thereof to perform at least one of the steps, operations, or actions described in different exemplary examples. As a result, computer system 212 operates as a dedicated computer system, where loop merging is possible due to the loop optimizer 214 in computer system 212, thereby reducing code size. In particular, the loop optimizer 214 transforms computer system 212 into a dedicated computer system compared to a typical computer system currently available that does not have a loop optimizer 214.

[0092] In an exemplary example, the use of the loop optimizer 214 in computer system 212 integrates the process into a practical application for a method of merging loops in a way that reduces code size, resulting in improved performance of computer system 212. In other words, the loop optimizer 214 in computer system 212 targets the practical application of the process integrated into the loop optimizer 214 in computer system 212. For example, the loop optimizer 214 in computer system 212 provides a practical application of the stage of merging loops so that the functionality of computer system 212 is improved. Computer system 212 can optimize computer code running on computer system 212 using the loop optimizer 214 to merge loops in computer code. With the reduction in code size, resource availability in computer system 212 may improve. At least one of the following may occur: reduced memory usage, improved code execution speed, or other improvements.

[0093] The diagram of the loop optimization environment 200 in Figure 2 is not intended to imply any physical or architectural limitations on how the exemplary embodiment may be implemented. Other components may be used in addition to or instead of those shown. Some components may be unnecessary. Also, the blocks are presented to show several functional components. One or more of these blocks may be combined, separated, or combined and separated into different blocks when implemented in the exemplary embodiment.

[0094] For example, the loop optimizer 214 can perform loop optimization on additional computer code in addition to the computer code 204, where the additional computer code is in a different source language. In another exemplary example, the computer code 204 may already be an intermediate representation of the code.

[0095] Referring now to Figure 3, a flowchart illustrating the generation of a tree from computer code according to an exemplary embodiment is shown. As shown, code 300 is an example of an intermediate representation of computer code, such as computer code 204 in Figure 2. As shown, code 300 is for a function in a program or application. Code 300 contains loops that can be used to create the tree 320.

[0096] In this exemplary example, the loops in code 300 have different depths. Loop depth is the level of loop nesting. As shown, loops i2 302, i3 303, and i4 304 are nested within loop i1 301. Loop i6 306 is nested within loop i5 305. In this example, loops i1 301 and i5 305 are at the same depth. Furthermore, loops i2 302, i3 303, i4 304, and i6 306 are at the same depth.

[0097] As shown, loops in Code 300 can have parent-child and sibling relationships. For example, a parent-child relationship exists when a child loop is nested within its parent. As for sibling relationships, both loops are at the same depth and, at the same nesting level within Code 300. Two loops are at the same level of hierarchy within the Code 300 structure and are enclosed by the same pair of curly braces: "{" and "}" in this example, then those two loops are at the same nesting level within Code 300.

[0098] For example, loops i1 301 and i5 305 are siblings because they are at the same hierarchical level and both are enclosed by the function f(). In addition, loops i2 302, i3 303, and i4 304 are siblings because all three of these loops are nested within loop i1 301 at the same depth.

[0099] In this example, loop i6 306 does not have a sibling relationship with loops i2 302, i3 303, and i4 304 because loop i6 306 is nested within a different loop. In this example, loop i1 301 has a parent-child relationship with loops i2 302, i3 303, and i4 304 because these loops are child loops nested within their parent loop, loop i1 301. As shown, loop i5 305 has a parent-child relationship with loop i6 306 because loop i6 306 is a child loop nested within its parent loop, loop i5 305.

[0100] As shown, tree 320 is created using code 300. Tree 320 has nodes that represent the loop structure in code 300. Tree 320 has a root node 322 that indicates that tree 320 is a tree about code 300. The nodes under the root node 322 in tree 320 are representations of the loops in code 300.

[0101] These nodes are comprised of multiple levels of edges that identify the relationships between the nodes in code 300. In terms of levels, nodes i1 331 and i5 335 are at the same level below the root node 322. As shown, nodes i2 332, i3 333, i4 334, and i6 336 are at the same level.

[0102] In this example, edges represent relationships between nodes. These edges, along with the node levels, can be used to identify parent-child and sibling relationships between nodes in tree 320. For example, edge 340 connects node i1 331 and node i5 335. In this example, these two nodes are also at the same level. As a result, nodes i1 331 and i5 335 are sibling nodes.

[0103] As shown, edge 342 connects node i2 332 to node i3 333; edge 344 connects node i3 333 to node i4 334. These three nodes are at the same level. As a result, these nodes are siblings to one another. These nodes are also child nodes of node i1 331, based on the connection of node i1 331 to node i2 332 by edge 347, and the location of these nodes at a lower level than node i1 331 within tree 320.

[0104] Node i6 336 is at the same level as nodes i2 332, i3 333, and i4 334, but node i6 336 does not have a sibling relationship with these nodes because it has no connection to them. Node i5 335 is connected to node i6 336 by edge 346. This connection means that node i5 335 is the parent node of node i6 336, and node i6 336 is the child node of this parent node.

[0105] In this example, the tree 320 can be analyzed to identify sibling nodes correlated with pairs of loops that can be considered for merging. In this exemplary example, the tree traversal is performed breadth-first, upward from the bottom level. While the tree 320 can be traversed in different ways, bottom-up breadth-first can offer increased opportunities for merging loops compared to other techniques for traversing the tree 320.

[0106] Referring now to Figure 4, a flowchart of a process for merging loops using a loop tree representation, according to an exemplary embodiment, is shown. The process in Figure 4 can be implemented in hardware, software, or both. When implemented in software, the process can take the form of program instructions executed by one or more processor units located in one or more hardware devices in one or more computer systems. For example, the process can be implemented in the loop optimizer 214 in the computer system 212 of Figure 4.

[0107] The process begins by creating a tree from the code that stores the loops (step 400). This code can be an application, program, function, subroutine, or other computer code. Furthermore, the code used can be source code or an intermediate representation of source code.

[0108] The process uses reverse breadth-first traversal to identify pairs of sibling nodes (stage 402). In stage 402, the traversal starts from the bottom of the tree and proceeds upwards.

[0109] The process determines whether a candidate loop represented by a pair of sibling nodes is eligible for merging (stage 404). In stage 404, this decision can be made in several different ways. For example, a decision for eligibility may be made if (1) both loops follow the structured control flow principle; (2) both loops are either monotonically increasing or decreasing; and (3) there is no intervening code between the two candidate loops, or the intervening code is not dependent on either of the candidate loops.

[0110] If the candidate loop is not eligible for merging, a decision is made as to whether additional sibling nodes exist in the tree for analysis (stage 406). If no additional sibling nodes exist, the process terminates. If additional sibling nodes exist, the process returns to stage 402.

[0111] Referring again to step 404, if the candidate loop is eligible for merging, pairs of operations from the candidate loop are analyzed and identified as isomorphic or non-isomorphic operations (step 408). In step 408, the decision of whether an operation is isomorphic can be made by determining whether the opcodes or instructions match, and then recursively checking whether their operands are isomorphic.

[0112] The process determines whether merging the loops satisfies a set of objectives (stage 410). In stage 410, these objectives could be, for example, whether the merge would sufficiently reduce the code size. One way to make this determination is to analyze multiple actions that are isomorphic actions between the two loops. For example, if all of the actions in a pair are isomorphic, then the two loops are perfectly isomorphic and the objective is satisfied. In another example, the ratio of isomorphic to non-isomorphic actions can be calculated. If this ratio is higher than a threshold, this objective is similarly satisfied.

[0113] If the set of objectives is not met, the process returns to stage 406. Otherwise, the set of objectives is met, and the process creates a new loop using the expanded iteration space (stage 412). In stage 412, the new loop has an expanded iteration space with an empty body. In this example, the expanded iteration space is an iteration space that encompasses the iteration spaces from the two candidate nodes that are being merged to form a new node. The iteration space of each candidate loop can be represented as the range of values ​​that the loop's inducer variable can take during the runtime execution of that loop. The inducer variable is an integer variable that can be incremented or decremented by a constant count in each iteration of the loop. This variable may also be called an index or index variable. The range of values ​​that the inducer variable can take is called the loop's index set.

[0114] In step 412, the process can use an index mapping function to convert the use of the original loop's index to an equivalent value based on the new derived variable. Such a function takes into account the stride and the differences in the lower and upper bounds of the merged loops. A loop can have multiple derived variables, in which case the index mapping can be applied to each derived variable as well.

[0115] The process applies rewrite mapping rules to populate the new loop body (stage 414). In stage 414, rewrite mapping rules can be applied to guard non-isomorphic behavior so that these types of behavior are performed only in the merged index set corresponding to their original loops. When applying rewrite mapping rules, the process can also modify any use of the induced variables through mappings that transform them to the correct values ​​based on the new induced variables. The mappings can be provided as functions that take the new induced variables as input and calculate the resulting index based on the lower bound, upper bound, and stride of the original loop.

[0116] In the case of a completely isomorphic loop, index mapping is either unnecessary (for example, if the inductive variable is not used for anything other than counting iterations) or it is a direct mapping from the old inductive variable to the corresponding new inductive variable. In the case of a loop with multiple inductive variables, direct mapping can also be applied to each pair of inductive variables, as long as the strides match for pairs of inductive variables that map to each other.

[0117] The process deletes the original loop (step 416). The process updates the tree (step 418). The process then returns to step 404, as described above. In step 418, the process removes two sibling nodes and replaces these two sibling nodes with a new node. Thus, the process in this flowchart can merge loop pairs one at a time until no further candidate loops exist for consideration.

[0118] Referring to Figure 5, a flowchart of a process for creating new behavior for the loop body of a new loop by applying a rewrite mapping rule, according to an exemplary embodiment, is shown. The process in Figure 5 can be implemented in hardware, software, or both. When implemented in software, the process can take the form of program instructions executed by one or more processor units located in one or more hardware devices in one or more computer systems. For example, the process can be implemented in the loop optimizer 214 in the loop processing system 202 of Figure 2. The process in Figure 5 is an example of one implementation for step 414 in Figure 4.

[0119] The process begins by selecting a pair of actions from a pair of candidate loops to write the loop body of a new loop (stage 500). In stage 500, the process compares the actions in the loop body from the two candidate loops with each other. The process determines whether the selected pair of actions is isomorphic (stage 502).

[0120] If the selected pair of actions is an isomorphic action, the process generates a new action using the selected pair of actions (step 504). The new action created in step 504 may be a copy of the selected pair of actions. For example, if the selected pair of actions includes an isomorphic action A() and an isomorphic action B(), the actions created for the loop body of the new loop may be A() and B().

[0121] The process determines whether the new action will use an inducement variable (step 506). In step 506, the inducement variable is an index used to track the number of iterations performed by the loop. For example, an action that does not use an inducement variable can be A(), and an action that does use an inducement variable can be A(i). In this example, A() is the action that will be performed in the loop, and "i" is the inducement variable that tracks the number of iterations performed by the loop.

[0122] If the new operation uses an inducement variable, the process determines whether the candidate loop pair has the same stride (step 508). In step 508, the stride is the value added to or removed from the inducement variable in the loop after each iteration.

[0123] If the candidate loop pairs have the same stride, the process performs a direct mapping to replace existing induce variables used in the new behavior with new induce variables (step 510). In step 510, the direct mapping can be performed by renaming the induce variables used in the behavior created for the loop body of the new loop.

[0124] For example, if a pair of actions from a candidate loop includes isomorphic action A(i) from the first loop in the candidate loop pair and isomorphic action A(j) from the second loop in the candidate loop pair, the process can rename the induced variables "i" and "j" to induced variable "k", where k is the induced variable of the new (merged) loop. In this example, the old induced variables are replaced by the induced variables of the new loop.

[0125] This rewrite can be used with loops that store isomorphic operations using induced variables, where the two loops have a set of indexes that are disjoint but continuous. In this example, direct mapping of induced variables converts the induced variables used in the operation to the correct values, ensuring that the new operation in the new loop is executed correctly.

[0126] The process places the new action into the loop body of a new loop (step 522). Referring again to step 506, if the new action does not use an inducer variable, the process proceeds to step 522 again. The process determines whether there are any other pairs of actions from the candidate loop pair for selection (step 524). If there are any other pairs of actions from the candidate loop pair, the process returns to step 500 and repeats steps 500 through 524 until all pairs of actions from the candidate loop pair are selected. If there are no other pairs of actions, the process then terminates.

[0127] Referring again to step 502, if the selected pair of actions is a non-isomorphic action, the process generates a guarded action using the selected pair of actions, conditionally based on the iteration space of the candidate loop pair (step 512). In step 512, the guarded action is executed only in the portion of the merged index set corresponding to the original loop on which the guarded action is based. In other words, the guarded action is executed conditionally based on the iteration space of the corresponding loops of the non-isomorphic action in the candidate loop pair.

[0128] For example, if the selected pair of actions is non-isomorphic, and each involves actions A() and B() from the first and second loops respectively, with the index values ​​of the first loop ranging from 0 to n-1 and the index values ​​of the second loop ranging from n to m, then the guarded action includes A(), which is executed only if the induced variable in the new loop is less than n, because the induced variable is repeated only between 0 and n-1 in the first loop. In addition, the guarded action also includes action B(), which is executed only if the induced variable in the new loop is greater than n-1 and less than m, because the induced variable is repeated only between n and m in the second loop.

[0129] The process determines whether the guarded action uses the induced variable (step 514). If the guarded action uses the induced variable, the process calculates the induced variable based on the lower bound, upper bound, and stride from the iteration space for the pair of candidate loops (step 516). Referring again to step 508, if the pair of candidate loops do not have the same stride, the process also proceeds to step 516.

[0130] The process replaces existing induced variables in the new and guarded actions with the calculated induced variables (step 518). The process places the new and guarded actions into the loop body of the new loop (step 520). Referring again to step 514, if the guarded action does not use induced variables, the process proceeds to step 520 again. The process then proceeds to step 524, as described above.

[0131] Referring to Figure 6, a flowchart of the process for determining whether merging candidate loop pairs satisfies the objective, according to an exemplary embodiment, is shown. The process in Figure 6 is an example of an implementation for step 410 in Figure 4.

[0132] The process begins by selecting a pair of candidate loops for processing (stage 600). The process identifies all pairs of isomorphic and all pairs of non-isomorphic operations from the selected pair of candidate loops (stage 602).

[0133] The process calculates the ratio of isomorphic versus non-isomorphic behavior for a selected pair of candidate loops (step 604). The process calculates a code size score based on the ratio of isomorphic versus non-isomorphic behavior for a selected pair of candidate loops (step 606). In step 606, the code size score is a measure used to determine the potential reduction in the size of the computer code that may result from merging the pair of candidate loops. In this example, since the isomorphic behaviors are identical in at least one of their structures or forms, merging the pair of candidate loops that have isomorphic behavior may result in a reduction in the size of the computer code.

[0134] The process calculates a parallelism coarseness score for selected pairs of candidate loops (step 608). The parallelism coarseness score is a measure of the potential performance improvement of computer code. Parallelism coarseness is a technique for combining multiple tasks or operations into larger units that can be executed in parallel. In other words, a higher parallelism coarseness score for a pair of candidate loops indicates that the pair of candidate loops has higher parallelism coarseness potential and therefore can benefit from merging the pair of candidate loops into a single new loop.

[0135] In step 608, the parallelism coarseness score can be determined based on the estimated trip count, the estimated computation cycles for instructions in the loop body, and the estimated parallelization overhead. In this example, the trip count is the number of times the loop is executed, and the computation cycles for instructions in the loop body is the number of clock cycles used to execute the instructions in the loop body. In addition, the parallelization overhead is the extra time and resources required to break down the loop into smaller tasks so that different parts of the loop can be executed simultaneously on different processor units.

[0136] The process determines whether the selected pair of candidate loops is nested within another loop (step 610). If the selected pair of candidate loops is nested within another loop, the process determines a full nesting opportunity score for each optimization made possible through full loop nesting (step 612). In step 612, full loop nesting is a nested loop where all operations are contained within the innermost loop. In this exemplary example, full loop nesting is a loop nesting where all useful computations (computations other than loop overhead) are performed inside the innermost loop. In other words, there is no intervening code between any two loops. Referring again to step 610, if the selected pair of candidate loops is not nested within another loop, the process proceeds directly to step 614, as described below.

[0137] The process calculates the final score as a weighted sum of the code size score, the parallelism coarsening score, and all perfect nesting opportunity scores (step 614). In step 614, the final score can be determined as follows: final score = code-size-score * w1 + parallelism-coarsening-score * w2 + perfect-nest-op1 * w3 + perfect-nest-op2 * w4 + .... In this example, weights such as w1, w2, w3, w4, etc. can be applied to different scores to adjust the influence of each score on the final result.

[0138] The process indicates whether the objective has been met based on comparing the final score to a threshold (stage 616). The process then terminates. In stage 616, if the final score is higher than the threshold, the process indicates that the objective has been met in terms of improved execution speed, reduced code size, or both. In this example, the threshold can have a value of 1. Otherwise, the process indicates that the objective has not been met.

[0139] Referring now to Figure 7, a flowchart of a process for merging loops according to an exemplary embodiment is shown. The process in Figure 7 can be implemented in hardware, software, or both. When implemented in software, the process can take the form of program instructions executed by one or more processor units located in one or more hardware devices in one or more computer systems. For example, the process can be implemented in the loop optimizer 214 in the computer system 212 of Figure 2.

[0140] The process begins by identifying loops in computer code, which are sequences of instructions that are repeated until a condition for the loop is met (stage 700). The process creates a tree containing nodes representing loops and edges representing the relationships between nodes (stage 702). In stage 702, the nodes in the tree can represent the structure for the loop in the intermediate representation.

[0141] The process analyzes the tree to identify candidate loop pairs from sibling nodes (stage 704). In response to the candidate loop pairs being eligible for merging, the process creates new loops from the candidate loop pairs using an expanded iteration space based on the iteration space for the candidate loop pairs (stage 706). The process then terminates.

[0142] Referring to Figure 8, a flowchart of the process for merging loops according to an exemplary embodiment is shown. The process shown in Figure 8 is an example of additional steps that can be performed in conjunction with the steps in Figure 7.

[0143] The process involves repeatedly analyzing the tree to identify candidate loop pairs and creating new loops from each candidate loop pair for every pair of sibling nodes in the tree (stage 800). The process then terminates.

[0144] Next, Figure 9 shows a flowchart of the process for analyzing the loop according to an exemplary embodiment. The process in this figure is an example of additional steps that can be performed in conjunction with the steps in Figure 7.

[0145] The process analyzes the loop body for the candidate loop pair to identify the isomorphic action pair stored in the candidate loop pair, and the loop body of the new loop contains the isomorphic action from the isomorphic action pair identified in the candidate loop pair (step 900). The process then terminates.

[0146] Referring now to Figure 10, a flowchart of the process for determining whether a pair of candidate loops is eligible for merging, according to an exemplary embodiment, is shown. The process in this figure is an example of additional steps that can be performed in conjunction with the steps in Figure 7.

[0147] The process determines whether a pair of candidate loops is eligible for merging using eligibility factors that include: both loops follow the structured control flow principle; both loops are monotonically variable; and there is no intervening code between the candidate loop pair, or, if there is intervening code, the intervening code has no dependency on either loop in the candidate loop pair (step 1000). The process then terminates.

[0148] Next, referring to Figure 11, a flowchart of the process for creating a new loop is shown according to an exemplary embodiment. The process in Figure 11 is an example of an implementation for step 706 in Figure 7.

[0149] The process applies rewrite mapping rules to create new behavior for the loop body for the new loop (stage 1100). The process then terminates. Index mapping may still be required for some isomorphic behaviors. These mappings are usually simpler than non-isomorphic behaviors. For example, the mapping can be a direct mapping.

[0150] Referring now to Figure 12, a flowchart of the process for determining whether or not to merge candidate loop pairs, according to an exemplary embodiment, is shown. The process in Figure 12 is an example of additional steps that can be performed in conjunction with the steps in Figure 7.

[0151] The process determines whether or not to merge candidate loop pairs and forms a new loop using the desired set (stage 1200). The process then terminates.

[0152] Next, referring to Figure 13, a flowchart is shown for determining whether or not a pair of candidate loops should be merged, according to an exemplary embodiment. The process in this flowchart is an example of additional steps that can be performed in conjunction with the steps in Figure 7.

[0153] The process begins by determining the isomorphic versus non-isomorphic operation ratio for a pair of candidate loops (step 1300). Based on whether the isomorphic versus non-isomorphic operation ratio is above a threshold, the process decides whether to create a new loop from the pair of candidate loops (step 1302). The process then terminates.

[0154] Figure 14 shows a flowchart of a process for analyzing a tree according to an exemplary embodiment. The process in this figure is an example of an implementation for step 704 in Figure 7.

[0155] The process parses the tree and uses reverse breadth-first traversal to identify candidate loop pairs from sibling nodes that are eligible to merge (stage 1400). The process then terminates.

[0156] Referring now to Figure 15, a flowchart of a process for merging loops according to an exemplary embodiment is shown. The process in Figure 7 can be implemented in hardware, software, or both. When implemented in software, the process can take the form of program instructions executed by one or more processor units located in one or more hardware devices in one or more computer systems. For example, the process can be implemented in the loop optimizer 214 in the computer system 212 of Figure 2.

[0157] The process begins by identifying loops in computer code, which are sequences of instructions that are repeated until a defined condition is met (Step 1500). The process then creates a tree containing nodes for each loop, with each loop representing the structure of the loop in an intermediate representation (Step 1502).

[0158] The process analyzes the tree to identify candidate loop pairs containing adjacent sibling loops that are eligible for merging (step 1504). The process analyzes the loop bodies of the candidate loops to identify isomorphic pairs of operations stored within the candidate loops (step 1506).

[0159] The process creates a new loop from the candidate loop, and the loop body of the new loop contains the isomorphic behavior obtained from the candidate loop (step 1508). The process then terminates. This process can be performed for each pair of sibling nodes identified in the tree if the loop is perfectly isomorphic.

[0160] The flowcharts and block diagrams in different shown embodiments illustrate the architecture, functionality, and operation of several possible implementations of the apparatus and method in the exemplary embodiments. In this regard, each block in the flowchart or block diagram may represent at least one of a module, segment, function, or part of an operation or stage. For example, one or more of these blocks may be implemented as program instructions, hardware, or a combination of program instructions and hardware. When implemented in hardware, the hardware may take the form of an integrated circuit, for example, manufactured or configured to perform one or more operations in the flowchart or block diagram. When implemented as a combination of program instructions and hardware, the implementation may take the form of firmware. Each block in the flowchart or block diagram may be implemented using dedicated hardware and a dedicated hardware system that performs different operations or combinations of program instructions executed by this dedicated hardware.

[0161] In some alternative implementations of the exemplary embodiments, the one or more functions described in the blocks may be performed in an order other than that shown in the diagram. For example, in some cases, depending on the functions involved, two consecutively shown blocks may be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. In addition, other blocks may be added in addition to those shown in the flowchart or block diagram.

[0162] Next, Figures 16–24 show process flows for merging and refining candidate loops. These illustrative process flows are provided only as examples for different characteristics of the exemplary examples and are not intended to limit the exemplary examples to any particular example shown in these figures.

[0163] First, referring to Figure 16, a process flow for creating a new loop from a pair of candidate loops is shown according to an exemplary embodiment. In this exemplary example, the pair of candidate loops 1600 includes loops 1602 and 1604 which are eligible for merging to create a new loop 1612.

[0164] As shown, loop 1602 contains the derived variable "i" for action block A(i) and action B(i). Loop 1602 has an iterative space containing values ​​in the range of lower bound "lb1" to upper bound "ub1-1". In addition, loop 1602 increments by the value "s1" with each iteration.

[0165] In this example, loop 1604 has an induced variable "j" for action block A(j) and action block C(j). Loop 1604 has an iterative space containing values ​​in the range of lower bound "lb2" to upper bound "ub2-1". In addition, loop 1602 increments by the value "s2" with each iteration.

[0166] As shown, computer code 1606 defines an upper bound "ub3" in the extended iteration space for the new loop 1612. Computer code 1608 defines an index mapping function to convert the derived variable "i" from loop 1602 to a new derived variable that will be used in the new loop 1612. Similarly, computer code 1610 defines an index mapping function to convert the derived variable "j" from loop 1604 to a new derived variable that will be used in the new loop 1612.

[0167] First, referring to Figure 17, a process flow for creating a new loop from a pair of candidate loops is shown according to an exemplary embodiment. In this exemplary example, the pair of candidate loops 1700 includes loops 1704 and 1706 which are eligible for merging to create a new loop 1702.

[0168] As shown, loops 1704 and 1706 are normalized loops. In this exemplary example, a loop is normalized if it has an iteration space with a lower bound of zero and an inductive variable that increments by 1 with each iteration. The inductive variable is an index used to track the number of iterations performed by the loop. The iteration space is the set of values ​​that one or more inductive variables can take during execution in the loop.

[0169] As shown, loop 1704 has an iterative space containing the derived variable "i" and values ​​from 0 to n-1. In another example, loop 1706 has an iterative space containing the derived variable "j" and values ​​from 0 to m-1. A new loop 1702 is created by merging loops 1704 and 1706. Furthermore, in this example, the new loop 1702 has an extended iterative space containing all values ​​for the derived variables in loops 1704 and 1706. As shown, the derived variable "i" from loop 1704 and the derived variable "j" from loop 1706 are replaced with the derived variable "k" in the new loop 1702 using index mapping as described above.

[0170] Referring to Figure 18, a process flow for creating a new loop from a pair of candidate loops without using an inducement variable in operation is shown in an exemplary embodiment. In this exemplary example, the pair of candidate loops 1800 includes loops 1804 and 1806 that are eligible for merging.

[0171] Loops 1804 and 1806 are examples of loops that can be merged without using the induced variables in their operation. Merging loops 1804 and 1806 creates a new loop 1802. The new loop 1802 has an extended iteration space that contains all the values ​​for the induced variables in loops 1804 and 1806.

[0172] In this example, the inducer variable is not used in action block A() and action block B(), so it is not necessary to transform the inducer variable using index mapping. In this example, index mapping is the process of using the index mapping function. In this example, the index mapping function transforms the value for the inducer variable in the candidate loop pair to its equivalent value for the inducer variable in the new loop.

[0173] Referring to Figure 19, a process flow for creating a new loop from a pair of candidate loops having a contiguous iteration space is shown according to an exemplary embodiment. In this exemplary example, the pair of candidate loops 1900 includes loops 1904 and 1906 that are eligible for merging.

[0174] In this example, loop 1904 has an iteration space containing the value lb ~ n-1, and loop 1906 has an iteration space containing the value n ~ o-1, so the iteration spaces for loop 1904 and loop 1906 are continuous. In this example, lb is the lower bound. A new loop 1902 is created by merging loops 1904 and 1906.

[0175] As shown, the new loop 1902 has an extended iterative space containing lb~o-1 values ​​that cover all the values ​​for the derived variables in loops 1904 and 1906. In this example, the derived variable "i" from loop 1904 and the derived variable "j" from loop 1906 are replaced with the derived variable "k" in the new loop 1902 using index mapping as described above.

[0176] Referring to Figure 20, a process flow for creating a new loop from a pair of candidate loops containing both isomorphic and non-isomorphic operations is shown according to an exemplary embodiment. In one exemplary example, isomorphic operations can be identified by analyzing the loop bodies for the pair of candidate loops. The analysis can be performed by determining whether any of the code in the operation matches in the pair of candidate loops and recursively checking whether the operands for the code in the operation in the pair of candidate loops are similar.

[0177] In this exemplary example, candidate loop pair 2000 includes loops 2004 and 2006 that are eligible for merging. In candidate loop pair 2000, operation blocks A() and D() in loops 2004 and 2006 are isomorphic. In this example, operation block A() in loop 2004 is isomorphic to operation block A() in loop 2006. Similarly, operation block D() in loop 2004 is isomorphic to operation block D() in loop 2006. On the other hand, operation blocks B() and C() in loop 2004, and operation block E() in loop 2006 are non-isomorphic. There is no corresponding operation block in loop 2004 for operation block E(), and there is no corresponding operation block in loop 2006 for operation block B() or operation block C().

[0178] In this example, a new loop 2002 is created by merging loops 2004 and 2006. The new loop 2002 has an expanded iteration space that includes all the values ​​for the induced variables in 2004 and loops 2006. In this example, isomorphic operation is performed for all iterations in the new loop 2002, and non-isomorphic operation is performed conditionally based on the iteration space for the corresponding loops of the non-isomorphic operation before the merge.

[0179] For example, isomorphic actions such as action block A() and action block D() are executed for every iteration in the new loop 2002. On the other hand, non-isomorphic actions such as action block B() and action block C() are executed only when the induced variable is less than n, because action blocks B() and C() belong to loop 2004, which has an iteration space containing values ​​from 0 to n-1. In this example, the induced variable "i" from loop 2004 and the induced variable "j" from loop 2006 are replaced with the induced variable "k" in the new loop 2002 using index mapping as described above.

[0180] Referring to Figure 21, a process flow for creating a new loop from a loop containing isomorphic operation without an inductive variable is shown in an exemplary embodiment. In this exemplary example, loop 2100 includes loops 2104, 2106, and 2108 which are eligible for merging.

[0181] In this example, loops 2104, 2106, and 2108 have an isomorphic action block A(), and the execution of isomorphic action block A() does not utilize the induced variables. In other words, the induced variables "i" and "j" in loop 2100 are not used as inputs to action block A() when the loop in loop 2100 iterates.

[0182] A new loop 2102 is created by merging loops 2104, 2106, and 2108. In this example, the new loop 2102 has an expanded iteration space containing all the values ​​for the derived variables in loops 2104, 2106, and 2108. In this example, the derived variable "i" from loop 2104 and the derived variable "j" from loops 2106 and 2108 are replaced with the derived variable "k" in the new loop 2102 using index mapping as described above.

[0183] Referring to Figure 22, a process flow for creating a new loop from a pair of candidate loops, including an isomorphic operation with an induced variable and a contiguous iteration space, is shown according to an exemplary embodiment. As shown, the pair of candidate loops 2200 includes loops 2204 and 2206 that are eligible for merging.

[0184] The new loop 2202 is created by merging loops 2204 and 2206. In this example, the iteration spaces for loop 2204 and loop 2206 are continuous, since loop 2204 has an iteration space containing values ​​from 0 to n-1 and loop 2206 has an iteration space from n to m-1. The new loop 2202 has an extended iteration space containing all values ​​for the derived variable in loops 2204 and 2206. In this example, the derived variable "i" from loop 2204 and the derived variable "j" from loop 2206 are replaced with the derived variable "k" in the new loop 2202 using index mapping as described above.

[0185] Referring to Figure 23, a process flow for creating a new loop from a pair of candidate loops containing isomorphic operations with different inductive variables and a continuous iteration space is shown according to an exemplary embodiment. In this exemplary example, the pair of candidate loops 2300 includes loops 2304 and 2306 that are eligible for merging. The iteration spaces for loop 2304 and loop 2306 are continuous, since loop 2304 has an iteration space containing values ​​from 0 to n-1 and loop 2306 has an iteration space containing values ​​from n to m-1. The pair of candidate loops 2300 contains multiple inductive variables. For example, loop 2304 contains the inductive variable "i" for operation block A(i) and operation block B(i). In addition, loop 2304 contains the inductive variable "s" for operation block C(s). Similarly, loop 2306 contains the inductive variable "i" for operation block A(i) and operation block B(i). In addition, loop 2306 includes an induced variable "s" for the operation block C(s).

[0186] In this example, the new loop 2302 is created by merging loops 2304 and 2306. The new loop 2302 has an expanded iteration space that contains all the values ​​for the derived variables in loops 2304 and 2306. In this example, the derived variable "i" from loop 2304 and the derived variable "j" from loop 2306 are replaced with the derived variable "k" in the new loop 2302 using index mapping as described above. Similarly, the derived variable "s" from loops 2304 and 2306 is replaced with the derived variable "h" in the new loop 2302.

[0187] Referring to Figure 24, a process flow for generating a pair of candidate loops having a contiguous iteration space by shifting the iteration space of the candidate loops is shown according to an exemplary embodiment. In this exemplary example, the pair of candidate loops 2400 includes loops 2404 and 2406.

[0188] As shown, loop 2404 has an iteration space containing values ​​from 0 to 999, and loop 2406 has an iteration space containing values ​​from 2000 to 4999. Since the iteration spaces for loop 2404 and loop 2406 are not contiguous, loops 2404 and 2406 in candidate loop 2400 are not mergeable.

[0189] In this exemplary example, loop 2406 contains an operational block A(i-1000) which can be transformed into block A(i). By performing such a transformation, the iteration space for loop 2406 can be shifted to a set of values ​​containing values ​​from 1000 to 3999, as shown by loop 2408. After the shift, loops 2404 and 2408 in the candidate loop pair 2402 are eligible for merging because the iteration spaces for loop 2404 and loop 2408 are now contiguous.

[0190] Referring now to Figure 25, a block diagram of a data processing system according to an exemplary embodiment is shown. The data processing system 2500 can be used to implement the computer and computing devices in the computing environment 100 of Figure 1. The data processing system 2500 can also be used to implement the computer system 212 in Figure 2. In this exemplary example, the data processing system 2500 includes a communication framework 2502 that provides communication between a processor unit 2504, memory 2506, persistent storage 2508, a communication unit 2510, an input / output (I / O) unit 2512, and a display 2514. In this example, the communication framework 2502 takes the form of a bus system.

[0191] The processor unit 2504 functions to execute instructions for software that can be loaded into memory 2506. The processor unit 2504 includes one or more processors. For example, the processor unit 2504 can be selected from at least one of the following: a multicore processor, a central processing unit (CPU), a graphics processing unit (GPU), a physics processing unit (PPU), a digital signal processor (DSP), a network processor, or any other suitable type of processor. Furthermore, the processor unit 2504 can be implemented using one or more heterogeneous processor systems in which the main processor resides together with secondary processors on a single chip. As another exemplary example, the processor unit 2504 can be a symmetrical multiprocessor system containing multiple processors of the same type on a single chip.

[0192] Memory 2506 and persistent storage 2508 are examples of storage devices 2516. A storage device is any number of hardware capable of storing information, such as, for example, data, program instructions in a functional form, or at least one of other suitable information, temporarily, permanently, or both temporarily and permanently. In these exemplary examples, storage devices 2516 may also be referred to as computer-readable storage devices. Memory 2506 in these examples can be, for example, random-access memory or any other suitable volatile or non-volatile storage device. Persistent storage 2508 may take various forms depending on the particular implementation.

[0193] For example, persistent storage 2508 may include one or more components or devices. For example, persistent storage 2508 may be a hard drive, a solid-state drive (SSD), flash memory, a rewritable optical disk, a rewritable magnetic tape, or any combination of the above. The medium used by persistent storage 2508 may also be removable. For example, a removable hard drive can be used for persistent storage 2508.

[0194] In these exemplary examples, the communication unit 2510 provides communication with other data processing systems or devices. In these exemplary examples, the communication unit 2510 is a network interface card.

[0195] The input / output unit 2512 enables data input and output with other devices that can be connected to the data processing system 2500. For example, the input / output unit 2512 may provide a connection for user input through at least one of a keyboard, mouse, or any other suitable input device. Furthermore, the input / output unit 2512 may send output to a printer. The display 2514 provides a mechanism for displaying information to the user.

[0196] Instructions for at least one of an operating system, application, or program may reside in a storage device 2516 that communicates with the processor unit 2504 through a communication framework 2502. Processes of different embodiments may be executed by the processor unit 2504 using computer implementation instructions that may reside in memory such as memory 2506.

[0197] These instructions are referred to as program instructions, computer-readable program instructions, or computer-readable program instructions, which can be read and executed by the processor in the processor unit 2504. In different embodiments, the program instructions may be implemented on different physical or computer-readable storage media, such as memory 2506 or persistent storage 2508.

[0198] The program instruction 2518 is located in a functional form on a selectively removable computer-readable medium 2520 and can be loaded into or transferred to a data processing system 2500 for execution by a processor unit 2504. The program instruction 2518 and the computer-readable medium 2520 form a computer program product 2522 in these exemplary examples. In the exemplary examples, the computer-readable medium 2520 is a computer-readable storage medium 2524.

[0199] The computer-readable storage medium 2524 is a physical or tangible storage device used to store the program instructions 2518, and not a medium for propagating or transmitting the program instructions 2518. When used herein, the computer-readable storage medium 2524 shall not be construed as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through optical fiber cables), or electrical signals transmitted through wires.

[0200] Alternatively, program instructions 2518 can be transmitted to the data processing system 2500 using a computer-readable signal medium. The computer-readable signal medium is a signal, and can be, for example, a propagating data signal containing program instructions 2518. For example, the computer-readable signal medium can be at least one of electromagnetic signals, optical signals, or any other suitable type of signal. These signals can be transmitted via connections such as wireless connections, fiber optic cables, coaxial cables, wires, or any other suitable type of connection.

[0201] Furthermore, as used herein, “computer-readable medium 2520” can be singular or plural. For example, program instructions 2518 may reside in computer-readable medium 2520 in the form of a single storage device or system. In another example, program instructions 2518 may reside in computer-readable medium 2520 distributed across multiple data processing systems. In other words, some instructions in program instructions 2518 may reside in one data processing system, while other instructions in program instructions 2518 may reside in one data processing system. For example, a portion of program instructions 2518 may reside in computer-readable medium 2520 in a server computer, while another portion of program instructions 2518 may reside in computer-readable medium 2520 located in a set of client computers.

[0202] The different components shown for the data processing system 2500 are not intended to impose architectural limitations on how different embodiments may be implemented. In some exemplary examples, one or more of the components may be incorporated into another component or otherwise form part of another component. For example, memory 2506, or a portion thereof, may be incorporated into processor unit 2504 in some exemplary examples. Different exemplary embodiments may be implemented in a data processing system including components in addition to, or instead of, those shown for the data processing system 2500. Other components shown in Figure 25 may be modified from the exemplary examples shown. Different embodiments may be implemented using any hardware device or system capable of executing program instructions 2518.

[0203] Therefore, exemplary embodiments of the present disclosure provide a computer implementation method, a computer system, and a computer program product for merging loops. Multiple processor units identify loops in computer code. A loop is a sequence of instructions that is repeated until a condition for the loop is met. Multiple processor units create a tree containing nodes representing loops and edges representing relationships between nodes. Multiple processor units use the tree to identify candidate loop pairs from sibling nodes. In response to whether a candidate loop pair is eligible for merging, multiple processor units create a new loop from the candidate loop pair using an expanded iteration space based on the iteration space for the candidate loop pair.

[0204] The descriptions of different exemplary embodiments are presented for illustrative and explanatory purposes and are not intended to be exhaustive or to limit to embodiments of the disclosed form. Different exemplary examples describe components that perform actions or operations. In exemplary embodiments, components may be configured to perform the described actions or operations. For example, a component may have a configuration or design for a structure that provides the component with the ability to perform the actions or operations described in the exemplary examples as being performed by the component. Furthermore, to the extent that the terms “includes,” “including,” “has,” and “contains” and their variations are used herein, such terms are intended to be comprehensive in the same manner as the term “comprises” as an open transitional term, without excluding any additional or other elements.

[0205] The descriptions of the various embodiments of this disclosure have been presented for illustrative purposes only and are not intended to be exhaustive or limitful to the disclosed embodiments. Not all embodiments will include all the features described in the exemplary examples. Furthermore, different exemplary embodiments may offer different features compared to other exemplary embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best describe the principles of the embodiments, their practical applications, or technical improvements to the art found in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A computer implementation method for merging loops, The step involves multiple processor units identifying loops in computer code, where the loop is a sequence of instructions that are repeated until a condition for the loop is met; The step of creating a tree using the aforementioned multiple processor units, which includes nodes representing the loop and edges representing the relationships between the nodes; The steps include: analyzing the tree using the plurality of processor units to identify candidate loop pairs from sibling nodes; and The step of the plurality of processor units, in response to the candidate loop pair being eligible for merging, creating a new loop from the candidate loop pair using an expanded iteration space based on the iteration space for the candidate loop pair. A computer implementation method comprising the following features.

2. The computer implementation method according to claim 1, further comprising the step of repeatedly analyzing the tree using the plurality of processor units to identify candidate loop pairs and creating new loops from the candidate loop pairs for each pair of sibling nodes in the tree.

3. The computer implementation method according to claim 1 or 2, further comprising the step of analyzing the loop body for the candidate loop pair with the plurality of processor units to identify a pair of isomorphic operations stored within the candidate loop pair, wherein the loop body of the new loop includes the isomorphic operations from the pair of isomorphic operations identified in the candidate loop pair.

4. The computer implementation method according to any one of claims 1 to 3, further comprising the step of determining whether a pair of candidate loops is eligible for merging using eligibility factors that include, if the pair of candidate loops is present, that both loops follow a structured control flow principle; both loops are monotonically variable; and there is no intervening code between the pair of candidate loops, or, if the intervening code is present between the pair of candidate loops, that the intervening code has no dependency on either loop in the pair of candidate loops.

5. The computer implementation method according to any one of claims 1 to 4, wherein the step of creating the new loop by the plurality of processor units further comprises the step of applying rewrite mapping rules by the plurality of processor units to create new operations for the loop body of the new loop.

6. The computer implementation method according to any one of claims 1 to 5, further comprising the step of determining whether or not to merge the candidate loop pairs using the plurality of processor units, and forming the new loop using the desired set.

7. The step of determining whether or not the candidate loop pair should be merged by the multiple processor units is as follows: A step of determining the ratio of isomorphic operation to non-isomorphic operation for the candidate loop pair using the plurality of processor units; and The step involves the plurality of processor units determining whether or not to create the new loop from the candidate loop pair based on whether or not the ratio of isomorphic operation to non-isomorphic operation is higher than a threshold. The computer implementation method according to claim 6, further comprising the above.

8. The computer implementation method according to any one of claims 1 to 7, wherein the step of analyzing the tree by the plurality of processor units further comprises the step of analyzing the tree by the plurality of processor units and identifying the candidate loop pairs from sibling nodes using reverse breadth-first traversal, the candidate loop pairs being eligible to merge.

9. A computer implementation method for merging loops, The step involves multiple processor units identifying loops in computer code, where a loop is a sequence of instructions that is repeated until a defined condition is met; The step of creating a tree containing nodes for the loop using the plurality of processor units, where each of the loops represents the structure of the loop in the intermediate representation; A step in which the plurality of processor units analyze the tree and identify candidate loop pairs that include adjacent sibling loops that are eligible to merge; The steps include: analyzing the loop body of the candidate loop using the plurality of processor units to identify isomorphic pairs of operations stored within the candidate loop; and The step of creating a new loop from the candidate loop using the plurality of processor units, wherein the loop body of the new loop includes the isomorphic operation obtained from the candidate loop. A computer implementation method comprising the following features.

10. The computer implementation method according to claim 9, further comprising the steps of: analyzing the tree using the plurality of processor units to identify candidate loop pairs; analyzing the loop body for each candidate loop pair; and repeatedly creating the new loop from each candidate loop pair for each pair of sibling nodes in the tree.

11. The computer implementation method according to claim 9 or 10, wherein the step of creating the new loop by the plurality of processor units further comprises the step of applying rewrite mapping rules by the plurality of processor units to create new operations for the loop body for the new loop.

12. The computer implementation method according to any one of claims 9 to 11, further comprising the step of performing a profitability evaluation using the plurality of processor units to determine whether the transformation of the candidate loop pair satisfies a desired set.

13. A computer system, It comprises multiple processor units, and the multiple processor units are A procedure for identifying a loop in computer code, wherein the loop is a sequence of instructions that are repeated until a condition for the loop is met; A procedure for creating a tree that includes nodes representing the aforementioned loops and edges representing the relationships between nodes; A procedure for analyzing the aforementioned tree to identify candidate loop pairs from sibling nodes; and A procedure to create a new loop from the pair of candidate loops using an expanded iteration space, based on the iteration space for the pair of candidate loops, in response to the pair of candidate loops being eligible for merging. A computer system that executes program instructions to perform a specific action.

14. The computer system according to claim 13, wherein the plurality of processor units further execute the program instructions which repeatedly perform the procedure of analyzing the tree to identify the candidate loop pair and creating the new loop from the candidate loop pair for each pair of sibling nodes in the tree.

15. The computer system according to claim 13 or 14, wherein the plurality of processor units further execute the program instructions which perform a procedure for analyzing the loop body for the candidate loop pair to identify a pair of isomorphic operations stored in the candidate loop pair, and the loop body of the new loop includes the isomorphic operations from the pair of isomorphic operations identified in the candidate loop pair.

16. The computer system according to any one of claims 13 to 15, wherein the plurality of processor units further execute the program instruction which performs a procedure to determine whether the pair of candidate loops is eligible for merging, using eligibility factors which include either both loops follow a structured control flow principle; both loops are monotonically variable; and there is no intervening code between the pair of candidate loops, or, if there is intervening code between the pair of candidate loops, the intervening code has no dependency on either loop in the pair of candidate loops.

17. The computer system according to any one of claims 13 to 16, wherein in the procedure for creating the new loop, the plurality of processor units further execute the program instructions that perform a procedure for creating new operations for the loop body for the new loop by applying rewrite mapping rules.

18. The computer system according to any one of claims 13 to 17, wherein the plurality of processor units further execute the program instructions that perform the procedure of determining whether or not to merge the candidate loop pairs and forming the new loop using the desired set.

19. In the procedure for determining whether or not to merge the candidate loop pair, the plurality of processor units, A procedure for determining the ratio of isomorphic operation to non-isomorphic operation for the candidate loop pair; and A procedure for determining whether to create the new loop from the candidate loop pair based on whether the ratio of isomorphic operation to non-isomorphic operation is higher than a threshold. The computer system according to claim 18, further executing the program instruction that performs the above.

20. The computer system according to any one of claims 13 to 19, wherein in the procedure for analyzing the tree, the plurality of processor units further execute the program instructions which perform the procedure of analyzing the tree and identifying the candidate loop pairs from sibling nodes using reverse width-first traversal, the candidate loop pairs being eligible to merge.

21. A computer system, It comprises multiple processor units, and the multiple processor units are A procedure for identifying a loop in computer code, where the loop is a sequence of instructions that are repeated until a defined condition is met; A procedure for creating a tree containing nodes for the aforementioned loops, wherein each of the aforementioned loops represents the structure of the loop in the intermediate representation; A procedure for analyzing the aforementioned tree to identify candidate loop pairs containing adjacent sibling loops that are eligible for merging; A procedure for analyzing the loop body of the candidate loop and identifying isomorphic pairs of operations stored within the candidate loop; and A procedure for creating a new loop from the candidate loop, wherein the loop body of the new loop includes the isomorphic operation obtained from the candidate loop. A computer system that executes program instructions to perform a specific action.

22. The computer system according to claim 21, wherein the plurality of processor units further execute the program instructions which repeatedly perform the procedure of analyzing the tree to identify the candidate loop pair and creating the new loop from the candidate loop pair for each pair of sibling nodes in the tree.

23. A computer program product for merging loops, wherein the computer program product comprises a computer-readable storage medium in which program instructions are embodied, and the program instructions are provided to a computer system. A procedure for identifying a loop in computer code, wherein the loop is a sequence of instructions that are repeated until a condition for the loop is met; A procedure for creating a tree that includes nodes representing the aforementioned loops and edges representing the relationships between nodes; A procedure for analyzing the aforementioned tree to identify candidate loop pairs from sibling nodes; and A procedure to create a new loop from the pair of candidate loops using an expanded iteration space, based on the iteration space for the pair of candidate loops, in response to the pair of candidate loops being eligible for merging. A computer program product that is executable by the aforementioned computer system in order to perform the following.

24. The computer program product according to claim 23, wherein the program instructions are further executable by the computer system to cause the computer system to repeatedly perform the procedure of analyzing the tree to identify the candidate loop pair and creating the new loop from the candidate loop pair for each pair of sibling nodes in the tree.

25. The computer program product according to claim 23 or 24, wherein the program instruction is further executable by the computer system to cause the computer system to perform a procedure to analyze the loop body for the candidate loop pair and identify a pair of isomorphic operations stored within the candidate loop pair, the loop body of the new loop includes the isomorphic operations from the pair of isomorphic operations identified in the candidate loop pair.

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