Indication device

Abstract

In the display device provided in this disclosure, X gate drive circuits are separated between two cascaded gate drive circuits, the phase difference of the first clock signals corresponding to the two cascaded gate drive circuits is (X+1)H, and in at least one subpixel, the phase difference between the effective level of the second gate control signal corresponding to the data transistor and one of the two first effective levels of the first clock signal applied to the gate drive circuit corresponding to the compensation transistor is greater than 0 and less than (X+1)H.

Description

Technical Field

[0001] This application claims the priority of Chinese Patent Application No. 202410502505.1 filed on April 24, 2024, and hereby incorporates by reference in its entirety the content disclosed in the above Chinese patent application as part of this application.

[0002] This application relates to the field of display technology, and specifically to display devices.

Background Art

[0003] By controlling the frequency of the gate control signals generated by each stage of the gate driver circuit in the display driving circuit, it is possible to control the frequency of refreshing display data with sub-pixels corresponding to different display areas of the display panel, so as to achieve a partitioned frequency division design with different display frequencies for different display areas corresponding to the display panel. On the other hand, the plurality of gate control signals output by the multi-stage gate driver circuit switch from the output of the gate control signal with valid pulses to the output of the gate control signal without valid pulses, or from the output of the gate control signal without valid pulses to the output of the gate control signal with valid pulses, that is, corresponding to the switching of the frequencies of the plurality of gate control signals.

[0004] A multi-story cascaded gate drive circuit generates voltages corresponding to the effective levels of multiple gate control signals based on the voltage supplied from the constant power terminal. However, when the gate drive circuit needs to output a gate control signal with an effective pulse, the constant power terminal acts on the gate drive circuit, instantaneously increasing the load corresponding to the constant power terminal in the first amplification. As a result, the voltage supplied from the constant power terminal decreases (i.e., a pumping load), the effective level of the gate control signal generated by the gate drive circuit decreases, and a voltage drop problem occurs in the gate control signal output by the gate drive circuit. On the other hand, when the gate drive circuit needs to output a gate control signal without an effective pulse, the load amplification corresponding to the constant power terminal is smaller than that of the first amplification. Therefore, a gate drive circuit that needs to output a gate control signal with an effective pulse has a different load formed at the constant power terminal than a gate drive circuit that needs to output a gate control signal without an effective pulse. Consequently, when the display panel employs frequency division display, the load formed at the constant power terminal before and after frequency division of the multi-story gate drive circuit differs due to the switching of the frequencies of multiple gate control signals. As a result, there is a difference in the change in the voltage drop of the gate control signal applied to subpixels near the corresponding frequency division position. Furthermore, the change in the voltage drop of the gate control signal is due to the periodic conversion of the clock signal used in the gate drive circuit.

[0005] As shown in Figure 1, before the corresponding frequency division (i.e., when the frequency division control signal NLF is at a low level), the voltage drop problem in multiple gate control signals is more severe (for example, the change in the multi-level gate control signal Nscan shown within the dashed box in Figure 1). In contrast, after the corresponding frequency division (i.e., when the frequency division control signal NLF is at a high level), the severity of the voltage drop problem in some gate control signals decreases. Therefore, near the corresponding frequency division position, when refreshing the display data in some subpixels (the tw stage in Figure 1 is the stage where the display data is refreshed in the subpixels), the voltage fluctuation of the corresponding gate control signal is large, while when refreshing the display data in some subpixels, the voltage fluctuation of the corresponding gate control signal is small. This results in a charging difference among multiple subpixels, causing differences in display brightness and display unevenness. [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] The embodiment of the present invention provides a display device that can improve the problem of display unevenness. [Means for solving the problem]

[0007] A display device provided in an embodiment of the present disclosure includes a display panel and a display driving circuit. The display panel includes a plurality of subpixels, each of which includes a light-emitting element, a driving transistor, a data transistor, and a compensation transistor, wherein the driving transistor is configured to drive the light emission of the light-emitting element, and the data transistor and the compensation transistor are configured to transmit data signals to the control terminals of the driving transistor. The display driving circuit is electrically connected to the display panel and is configured to output a plurality of first gate control signals to the control terminals of the compensation transistors of the plurality of subpixels, and to output a plurality of second gate control signals to the control terminals of the data transistors of the plurality of subpixels. The display driving circuit includes a plurality of gate driving circuits and a plurality of frequency division control lines, wherein the plurality of frequency division control lines are configured to transmit frequency division control signals to the plurality of gate driving circuits so as to control at least one level of the plurality of the first gate control signals, and each of the plurality of gate driving circuits is configured to generate the first gate control signal based on a corresponding start signal and a first clock signal. Here, X gate drive circuits are separated between two cascaded gate drive circuits, the phase difference of the first clock signal corresponding to the two cascaded gate drive circuits is (X+1)H, in at least one subpixel the effective level of the first gate control signal corresponding to the compensation transistor and the effective level of the second gate control signal corresponding to the data transistor overlap at least partially, the effective level of the second gate control signal corresponding to the data transistor lies between two first effective levels of the first clock signal applied to the gate drive circuit corresponding to the compensation transistor, the phase difference between the effective level of the second gate control signal corresponding to the data transistor and one of the two first effective levels is greater than 0 and less than (X+1)H, where X≧1 and H represents unit time. [Brief explanation of the drawing]

[0008] [Figure 1] This is a timing chart of gate control signals corresponding to some subpixels at the frequency division positions of the display panel provided in the embodiment of the present invention.

[0009] [Figure 2] This is a schematic diagram of a cascade connection structure for a multi-story gate drive circuit in related technologies.

[0010] [Figure 3] This is a timing chart of the gate control signals output in accordance with the cascade connection structure shown in Figure 2.

[0011] [Figure 4] This is a schematic diagram of the structure of the display device provided in the embodiment of the present application.

[0012] [Figure 5A] This is a schematic diagram of the subpixel structure provided in the embodiment of the present application. [Figure 5B] This is a schematic diagram of the subpixel structure provided in the embodiment of the present application.

[0013] [Figure 6] This is a schematic diagram of a cascade connection structure of a multi-story gate drive circuit provided in an embodiment of the present invention.

[0014] [Figure 7] This is a timing chart of a plurality of first gate control signals and a plurality of second gate control signals provided in the embodiment of the present application.

[0015] [Figure 8] This is a schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present application.

[0016] [Figure 9A] This is a timing chart of the gate drive circuit provided in the embodiment of the present invention. [Figure 9B] This is a timing chart of the gate drive circuit provided in the embodiment of the present invention.

[0017] [Figure 10] This is the timing chart of the sub-pixels provided in the embodiments of the present application.

[0018] [Figure 11] This is a schematic diagram of the high-frequency and low-frequency screen display principles provided in the embodiments of the present application.

Embodiments for Carrying out the Invention

[0019] In order to make the object, technical solution and effect of the present application clearer and more definite, the following will refer to the drawings to give examples of embodiments and explain the present application in more detail. It should be understood that the specific embodiments described in this specification are only used to explain the present application and not to limit the present application.

[0020] This invention provides a display device in which, in a display drive circuit, X gate drive circuits are separated between two cascaded gate drive circuits, so that the phase difference of the first clock signal corresponding to the two cascaded gate drive circuits becomes (X+1)H, and the period in which a change in voltage drop occurs in the first gate control signal output by each gate drive circuit is changed from XH to (X+1)H, thereby increasing the time interval in which a change in voltage drop occurs in the first gate control signal. In at least one subpixel, the effective level of the first gate control signal corresponding to the compensation transistor and the effective level of the second gate control signal corresponding to the data transistor overlap at least partially, so that there is a stage in which the data transistor and compensation transistor of at least one subpixel conduct simultaneously, thereby realizing charging of the subpixel. By positioning the effective level of the second gate control signal corresponding to the data transistor between the two first effective levels of the first clock signal applied to the gate drive circuit corresponding to the compensation transistor, and by setting the phase difference between the effective level of the second gate control signal corresponding to the data transistor and one of the two first effective levels to be greater than 0 and less than (X+1)H, the timing of the voltage drop of the effective level of the second gate control signal corresponding to the data transistor and the first gate control signal corresponding to the compensation transistor do not overlap in the same subpixel. As a result, in the same subpixel, the effective level of the second gate control signal corresponding to the data transistor is within the time interval in which a change in the voltage drop of the first gate control signal corresponding to the compensation transistor occurs. Consequently, the data transistor conducts within the interval in which the degree of change in the voltage drop of the first gate control signal applied to the compensation transistor is small, reducing the charge difference between multiple subpixels at the corresponding frequency division position and improving the problem of display unevenness.

[0021] Specifically, the purpose of a display panel employing partitioned frequency division display is to enable display by applying frequencies corresponding to different display modes to different display areas of the same display screen. For example, in a video playback interface environment, video content is displayed in the central area of ​​the screen, while still images are displayed in the upper and lower areas of the screen. Partitioned frequency division display technology achieves power saving and low power consumption by displaying the video area at a high refresh rate of 120Hz and the areas displaying still images at the top and bottom at a low refresh rate of 1Hz, compared to the UI screen processing methods in the above category.

[0022] Partitioned frequency division display technology can be realized by controlling the level state of the gate control signals received by the compensation transistor and reset transistor in the subpixel. Therefore, at the positions corresponding to frequency division (i.e., the intersection of high and low frequencies), the levels of the multiple gate control signals received by the compensation transistor and reset transistor of the corresponding subpixel are converted from a state with an effective level to a state without an effective level. On the other hand, the effective level output of this gate control signal is supplied by a constant power supply terminal, and at the level output stage, the constant power supply terminal is connected to the output terminal that outputs this gate control signal. From the perspective of a resistive capacitive load, the load on the constant power supply terminal is thought to increase instantaneously, and as a result, a voltage drop occurs in the level of the gate control signal output by the gate drive circuit of the current stage. When switching between high and low frequencies, the levels of the multiple gate control signals are converted from having an effective level to not having an effective level, so the change in voltage drop indicated by the gate control signal does not match, and consequently, when refreshing the display data at the corresponding data writing stage in the subpixel at the corresponding frequency division position, a fixed-width display unevenness occurs.

[0023] The inventors found that the change in voltage drop of the gate control signal received by the transistor and reset transistor is further caused by the periodic conversion of the clock signal used in the gate drive circuit that generates this gate signal, and that the period of the clock signal used in the gate drive circuit affects the period of the change in voltage drop of the generated gate control signal. Figure 2 is a schematic diagram of a multi-level gate drive circuit cascade structure in the related technology. Figure 3 is a timing chart of the gate control signals output corresponding to the cascade connection structure shown in Figure 2. Here, Nscana is the gate control signal generated before the frequency division of the gate drive circuit, and Nscanb is the gate control signal generated after the frequency division of the gate drive circuit. If the period of the clock signal used in the gate drive circuit is 4H, the gate control signal generated by the gate drive circuit has a period of 1H with a change in voltage drop. Therefore, a charge difference occurs in each subpixel of each row near the corresponding frequency division position, which causes display unevenness in subpixels of multiple rows.

[0024] Therefore, this application provides a display device to improve the aforementioned problem of display unevenness.

[0025] Figure 4 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. The present application provides a display device including a display panel DP and a display driving circuit Dc.

[0026] The display panel DP includes a plurality of subpixels Spi, a plurality of scan lines, and a plurality of data lines DL, wherein the plurality of scan lines are electrically connected between the display driver circuit Dc and the plurality of subpixels Spi, the plurality of data lines DL are configured to transmit a plurality of data signals, the plurality of data lines DL are electrically connected between the source pole driver circuit SDC and the plurality of subpixels Spi, and the source pole driver circuit SDC is configured to generate a plurality of data signals.

[0027] Figures 5A and 5B are schematic diagrams of the structure of a subpixel Spi provided in an embodiment of the present application. Each of the subpixels Spi includes a light-emitting element Di and a pixel driving circuit that drives the light-emitting element Di to emit light.

[0028] Selectively, the light-emitting element Di includes organic light-emitting diodes, sub-millimeter light-emitting diodes, micro-light-emitting diodes, and the like.

[0029] The pixel driving circuit includes at least a driving transistor Tdr, a data transistor Tda, and a compensation transistor Tc.

[0030] The drive transistor Tdr and the light-emitting element Di are connected in series between the first voltage terminal Vdd and the second voltage terminal Vss. The drive transistor Tdr is configured to generate a drive current based on the data signal transmitted from the corresponding data line DL, thereby driving the light-emitting element Di to emit light.

[0031] The data transistor Tda and the compensation transistor Tc are configured to transmit data signals to the control terminal of the drive transistor Tdr.

[0032] Selectively, the control terminal of the compensation transistor Tc is configured to receive the corresponding first gate control signal Nscan1, the input terminal of the compensation transistor Tc is electrically connected to the output terminal of the drive transistor Tdr, and the output terminal of the compensation transistor Tc is electrically connected to the control terminal of the drive transistor Tdr.

[0033] The control terminal of the data transistor Tda is configured to receive the corresponding second gate control signal Pscan1, the input terminal of the data transistor Tda is electrically connected to the corresponding data line DL, the input terminal of the data transistor Tda is configured to receive the corresponding data signal, and the output terminal of the data transistor Tda is electrically connected to the input terminal of the drive transistor Tdr.

[0034] Selectively, the compensating transistor Tc includes either an oxide transistor or a silicon transistor.

[0035] Selectively, the compensating transistor Tc is either a P-type or N-type transistor, and the data transistor Tda is either a P-type or N-type transistor.

[0036] Referring to Figures 5A and 5B, the pixel driving circuit for at least one subpixel Spi includes a reset transistor Tr, the control terminal of the reset transistor Tr is configured to receive a third gate control signal Nscan2, the input terminal of the reset transistor Tr is electrically connected to a reset line, the input terminal of the reset transistor Tr is configured to receive a reset signal Vr, and the output terminal of the reset transistor Tr is electrically connected to the control terminal of the driving transistor Tdr.

[0037] Selectively, the reset transistor Tr includes either an oxide transistor or a silicon transistor. Selectively, the reset transistor Tr is either a P-type transistor or an N-type transistor.

[0038] In the same subpixel Spi, the effective level of the first gate control signal Nscan1 received by the control terminal of the compensation transistor Tc and the effective level of the third gate control signal Nscan2 received by the control terminal of the reset transistor Tr partially overlap, so that the potential of the output terminal and control terminal of the drive transistor Tdr is selectively reset using the reset signal Vr.

[0039] Referring to Figures 5A and 5B, each pixel driving circuit of a plurality of subpixels Spi further includes a first initial transistor Ti1, the control terminal of the first initial transistor Ti1 is configured to receive a first scan signal Pscan2, the input terminal of the first initial transistor Ti1 is configured to receive a first reset signal Vi1, and the output terminal of the first initial transistor Ti1 is electrically connected to the anode of the light-emitting element Di.

[0040] Selectively, each pixel driving circuit of a plurality of subpixels Spi further includes a light emission control transistor, which is electrically connected between the input terminal of the driving transistor Tdr and a first voltage terminal Vdd, and / or between the output terminal of the driving transistor Tdr and the light-emitting element Di.

[0041] Selectively, referring to Figures 5A to 5B, the light emission control transistor includes a first light emission control transistor Te1 and a second light emission control transistor Te2, the input and output terminals of the first light emission control transistor Te1 are electrically connected between a first voltage terminal Vdd and the input terminal of the drive transistor Tdr, the input and output terminals of the second light emission control transistor Te2 are electrically connected between a light-emitting element Di and the output terminal of the drive transistor Tdr, and the control terminals of the first light emission control transistor Te1 and the second light emission control transistor Te2 are configured to receive a light emission control signal EM.

[0042] Referring to Figures 5A and 5B, each pixel driving circuit of multiple subpixels Spi further includes a first memory capacitor Cst1, which is connected in series between the first voltage terminal Vdd and the control terminal of the driving transistor Tdr.

[0043] Selectively, continuing with Figure 5B, each pixel driver circuit of a plurality of subpixels Spi further includes a second memory capacitor Cst2, the second memory capacitor Cst2 being connected in series between the control terminal of the driver transistor Tdr and the control terminal of the data transistor Tda.

[0044] Selectively, continuing with Figure 5B, each pixel driving circuit of a plurality of subpixels Spi further includes a second initial transistor Ti2, the control terminal of the second initial transistor Ti2 is electrically connected to the corresponding fourth scan line SL4, the input terminal of the second initial transistor Ti2 is configured to receive a second reset signal Vi2, and the output terminal of the second initial transistor Ti2 is electrically connected to the input terminal of the driving transistor Tdr.

[0045] Selectively, the first initial transistor Ti1 and the second initial transistor Ti2 are controlled by the same first scanning signal Pscan2, and the control terminal of the first initial transistor Ti1 is electrically connected to the control terminal of the second initial transistor Ti2 in order to achieve a synchronous reset of the anode potential of the light-emitting element Di and the potential of the input terminal of the drive transistor Tdr.

[0046] Referring to Figures 4 and 5A to 5B, the display drive circuit Dc is configured to output multiple first gate control signals Nscan1 to the control terminals of the compensation transistors Tc of multiple subpixels Spi, and to output multiple second gate control signals Pscan1 to the control terminals of the data transistors Tda of multiple subpixels Spi.

[0047] Selectively, continuing with Figure 4, the scan lines include a plurality of first scan lines SL1 and a plurality of second scan lines SL2, a plurality of first gate control signals Nscan1 are output to the control terminals of the compensation transistors Tc of the plurality of subpixels Spi via the plurality of first scan lines SL1, and a plurality of second gate control signals Pscan1 are output to the control terminals of the data transistors Tda of the plurality of subpixels Spi via the plurality of second scan lines SL2.

[0048] Selectively, the scan lines include multiple third scan lines SL3 and multiple fourth scan lines SL4, and the display panel DP includes multiple light emission control lines EML. The multiple third scan lines SL3 are configured to transmit multiple third gate control signals Nscan2, the multiple fourth scan lines SL4 are configured to transmit multiple first scan signals Pscan2, and the multiple light emission control lines EML are configured to transmit multiple light emission control signals EM. Here, the control terminal of the reset transistor Tr is electrically connected to the corresponding third scan line SL3, the control terminal of the first initial transistor Ti1 is electrically connected to the corresponding fourth scan line SL4, and the control terminal of the light emission control transistor is electrically connected to the corresponding light emission control line EML.

[0049] Figure 6 is a schematic diagram of a cascaded configuration of a multi-story gate drive circuit provided in an embodiment of the present invention. The display drive circuit Dc includes a first gate drive unit, which is configured to generate a plurality of first gate control signals Nscan1, and the first gate drive unit includes a plurality of frequency division control lines FL and a plurality of gate drive circuits GA.

[0050] Multiple frequency division control lines FL are electrically connected to multiple gate drive circuits GA, and the multiple frequency division control lines FL are configured to transmit divided frequency control signals to the multiple gate drive circuits GA so as to control the level of at least one of the multiple first gate control signals Nscan1, thereby enabling control of the conduction status of the compensation transistor Tc of multiple subpixels Spi via the frequency division control signals applied to the multiple gate drive circuits GA, and consequently controlling whether or not the content of the corresponding subpixel Spi display changes, thereby realizing partitioned frequency division display of the display panel DP.

[0051] Each gate drive circuit GA is configured to generate multiple first gate control signals Nscan1 based on the corresponding start signal STV and first clock signal XCK.

[0052] Referring to Figure 6, X gate drive circuits GA are separated between two cascaded gate drive circuits GA, and the phase difference of the first clock signal XCK corresponding to the two cascaded gate drive circuits GA is (X+1)H. This changes the period during which a change in voltage drop occurs in the first gate control signal Nscan1 output by each gate drive circuit GA from XH in related technologies to (X+1)H, thereby lengthening the time interval during which a change in voltage drop occurs in the first gate control signal Nscan1.

[0053] Note that in Figure 6, when X=1, only a schematic diagram of the cascade connection relationship of multiple gate drive circuits GA is shown, but this is not used to limit X=1. In other words, in some embodiments, X may be greater than 1.

[0054] In at least one subpixel Spi, the effective level of the first gate control signal Nscan1 corresponding to the compensation transistor Tc and the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda overlap at least partially, the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda lies between two first effective levels of the first clock signal XCK applied to the gate drive circuit GA corresponding to the compensation transistor Tc, and the phase difference between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and one of the two first effective levels is greater than 0 and less than (X+1)H, thereby enabling charging of the subpixel Spi by having a stage in which the data transistor Tda and compensation transistor Tc of at least one subpixel Spi conduct simultaneously. Furthermore, since the period of the voltage drop change due to the first gate control signal Nscan1 is (X+1)H and the first clock signal XCK applied to the gate drive circuit GA has an effective level, the first gate control signal Nscan1 generated by the gate drive circuit GA also causes a voltage drop problem accordingly. Therefore, the time at which a voltage drop problem occurs in the first gate control signal Nscan1 corresponds to the position where the phase difference when the first clock signal XCK applied to the gate drive circuit GA that generates the first gate control signal Nscan1 begins to have an effective level is (X+1)H, provided that the first clock signal XCK applied to the gate drive circuit GA that generates the first gate control signal Nscan1 has an effective level. Thus, by controlling the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and the phase difference between it and one of the two first effective levels to be greater than 0 and less than (X+1)H, the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda can be positioned within the interval at which a voltage drop change occurs in the first gate control signal Nscan1 corresponding to the compensation transistor Tc in the same subpixel Spi. This causes the data transistor Tda to conduct within an interval at which the degree of change in the voltage drop of the first gate control signal Nscan1 applied to the compensation transistor Tc is small, thereby reducing the charge difference of multiple subpixels Spi at the corresponding frequency division position and ultimately improving the problem of display unevenness.X ≥ 1, and H represents the unit time. Selectively, H can correspond to the period of a row.

[0055] This corresponds to selectively cascading the (X+1)r+1th order gate drive circuit GA, then the (X+1)r+2nd order gate drive circuit GA, ..., until the (X+1)r+(X+1)th order gate drive circuit GA is cascaded. Here, r≧0.

[0056] Figure 7 is a timing chart of multiple first gate control signals and multiple second gate control signals provided in the embodiment of the present application. Referring to Figures 6 and 7, the explanation will continue, with X=1 as an example. When X=1, one gate drive circuit GA is separated between two cascaded gate drive circuits GA, and the phase difference of the first clock signal XCK corresponding to the two cascaded gate drive circuits GA is 2H. That is, multiple odd-numbered gate drive circuits GA are cascaded, and multiple even-numbered gate drive circuits GA are cascaded, and the time difference between the intervals in which a change in voltage drop occurs in the first gate control signal Nscan1 output by each gate drive circuit GA is 2H, and the phase difference between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and one of the two first effective levels is greater than 0 and less than 2H.

[0057] The first gate control signal received by the control terminal of the compensation transistor Tc is the third-order first gate control signal Nscan1(3) generated by the third-order gate drive circuit GA(3), the first clock signal XCK corresponding to the third-order gate drive circuit GA(3) is the third-order clock signal CK3, and the first clock signal XCK corresponding to the first-order gate drive circuit GA(1) and the fifth-order gate drive circuit GA(5) is the first-order clock signal CK1. Then, the second gate control signal Pscan1 corresponding to the data transistor Tda may be the second-order second gate control signal Pscan1(2) generated by the second-order gate drive circuit GA(2), or the fourth-order second gate control signal Pscan1(4) generated by the fourth-order gate drive circuit GA(4). The two first effective levels of the first clock signal XCK applied to the third-order gate drive circuit GA(3) correspond to the ta and tb stages shown in Figure 7. Therefore, if the second gate control signal Pscan1 corresponding to the data transistor Tda is a second-order second gate control signal Pscan1(2), the phase difference between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and the first effective level corresponding to the ta stage is greater than 0 and less than 2H. If the second gate control signal Pscan1 corresponding to the data transistor Tda is a fourth-order second gate control signal Pscan1(4), the phase difference between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and the first effective level corresponding to the tb stage is greater than 0 and less than 2H.

[0058] Selectively, the phase difference between the activation signal STV corresponding to the nth-th gate drive circuit GA and the activation signal STV corresponding to the (n+1)th-th gate drive circuit GA is 1H, such that the odd-numbered and even-numbered gate drive circuits GA sequentially output the first gate control signal Nscan1 to multiple subpixels Spi. Here, n is an odd number.

[0059] Selectively, referring to Figure 6, the activation signal STV corresponding to the first-order gate drive circuit GA is the first activation signal stv1, the activation signal STV corresponding to the second-order gate drive circuit GA is the second activation signal stv2, the activation signal STV corresponding to the u-th order gate drive circuit GA is the first gate control signal Nscan1 output by the uv-th order gate drive circuit GA, or the activation signal STV corresponding to the u-th order gate drive circuit GA is the signal from the second node Q2 of the uv-th order gate drive circuit GA. Here, u≧2, v≧1, and the uv-th order gate drive circuit GA is cascaded before the u-th order gate drive circuit GA, and the difference in the order number between it and the u-th order gate drive circuit GA is v.

[0060] Selectively, the activation signal STV corresponding to the third-order gate drive circuit GA is either the first gate control signal Nscan1 output by the first-order gate drive circuit GA or the activation signal from the second node Q2 of the first-order gate drive circuit GA, and the activation signal STV corresponding to the fourth-order gate drive circuit GA is either the first gate control signal Nscan1 output by the second-order gate drive circuit GA or the signal from the second node Q2 of the second-order gate drive circuit GA.

[0061] Selectively, the activation signal STV corresponding to the u-th gate drive circuit GA is the signal from the second node Q2 of the uv-th gate drive circuit GA. This enables the first gate control signal Nscan1 output by the multi-layer gate drive circuit GA to switch from an output without an effective level to an output with an effective level, and enables the refresh rate corresponding to the multiple display areas of the display panel DP to switch between a high refresh rate and a low refresh rate.

[0062] Selectively, the phase difference between the first activation signal stv1 and the second activation signal stv2 is 1H such that the phase difference between the activation signal STV corresponding to the nth-th order gate drive circuit GA and the activation signal STV corresponding to the (n+1)th-th order gate drive circuit GA is 1H.

[0063] Selectively, X may be greater than 1. When X=2, the first-order gate drive circuit GA(1), the fourth-order gate drive circuit GA(4), the seventh-order gate drive circuit GA(7), etc. are cascaded, the second-order gate drive circuit GA(2), the fifth-order gate drive circuit GA(5), the eighth-order gate drive circuit GA(8), etc. are cascaded, and the third-order gate drive circuit GA(3), the sixth-order gate drive circuit GA(6), the ninth-order gate drive circuit GA(9), etc. are cascaded.

[0064] Correspondingly, the activation signal STV corresponding to the first-floor gate drive circuit GA(1) is the first activation signal stv1, the activation signal STV corresponding to the second-floor gate drive circuit GA(2) is the second activation signal stv2, the activation signal STV corresponding to the third-floor gate drive circuit GA(3) is the third activation signal, the activation signal STV corresponding to the fourth-floor gate drive circuit GA(4) is the signal from the second node Q2 of the first-floor gate drive circuit GA(1), the start signal STV corresponding to the fifth-floor gate drive circuit GA(5) is the signal from the second node Q2, which is the second activation signal of the second-floor gate drive circuit GA(2), and the activation signal STV corresponding to the sixth-floor gate drive circuit GA(6) is the signal from the second node Q2 of the third-floor gate drive circuit GA(3). By sequentially inferring, the cascaded connection relationship of multiple-floor gate drive circuits GA can be obtained.

[0065] Two gate drive circuits GA are separated from each other by two cascaded gate drive circuits GA, and the phase difference of the first clock signal XCK corresponding to the two cascaded gate drive circuits GA is 3H. The phase difference between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and one of the two first effective levels is greater than 0 and less than 3H.

[0066] Similarly, when X > 2, the cascading relationship of the multi-level gate drive circuit GA, and the relationship between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and the phase difference between it and one of the two first effective levels can also be obtained. This is omitted here.

[0067] Selectively, multiple gate drive circuits GA are electrically connected to Y clock lines, and the Y clock lines are configured to transmit the corresponding first clock signal XCK to the multiple gate drive circuits GA, where Y = 2(X + 1).

[0068] Selectively, referring to Figure 6, X=1, and multiple gate drive circuits GA are electrically connected to 4 (Y=4) clock lines, the Y clock lines including a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, and a fourth clock line CKL4. Here, the first clock line CKL1 transmits the corresponding first clock signal XCK to the 4K+1th order gate drive circuit GA, the second clock line CKL2 transmits the corresponding first clock signal XCK to the 4K+2nd order gate drive circuit GA, the third clock line CKL3 transmits the corresponding first clock signal XCK to the 4K+3rd order gate drive circuit GA, and the fourth clock line CKL4 transmits the corresponding first clock signal XCK to the 4K+4th order gate drive circuit GA, and K≧0.

[0069] Selectively, X=2, and multiple gate drive circuits GA are electrically connected to six (Y=6) clock lines, the Y clock lines including a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, a fourth clock line CKL4, a fifth clock line, and a sixth clock line. Here, the first clock line CKL1 transmits the corresponding first clock signal XCK to the 6K+1th order gate drive circuit GA, the second clock line CKL2 transmits the corresponding first clock signal XCK to the 6K+2nd order gate drive circuit GA, the third clock line CKL3 transmits the corresponding first clock signal XCK to the 6K+3rd order gate drive circuit GA, the fourth clock line CKL4 transmits the corresponding first clock signal XCK to the 6K+4th order gate drive circuit GA, the fifth clock line transmits the corresponding first clock signal XCK to the 6K+5th order gate drive circuit GA, and the sixth clock line transmits the corresponding first clock signal XCK to the 6K+6th order gate drive circuit GA, and K≧0.

[0070] In some selective embodiments, in order to further reduce power consumption and decrease the layout space occupied by the display drive circuit Dc, each gate drive circuit GA can be configured to output a first gate control signal Nscan1 as well as a second gate control signal Pscan1. That is, each gate drive circuit GA is configured to generate a plurality of second gate control signals Pscan1 based on the corresponding start signal STV, the first clock signal XCK, and the second clock signal CK.

[0071] Selectively, each gate drive circuit GA includes a first output terminal Nout and a second output terminal Pout, the first output terminal Nout is configured to output a first gate control signal Nscan1, and the second output terminal Pout is configured to output a second gate control signal Pscan1. Here, multiple first scan lines SL1 are electrically connected between the first output terminal Nout of the multiple gate drive circuits GA and the control terminals of the compensation transistors Tc of the multiple subpixels Spi, and multiple second scan lines SL2 are electrically connected between the second output terminal Pout of the multiple gate drive circuits GA and the control terminals of the data transistors Tda of the multiple subpixels Spi.

[0072] To selectively improve display differences, the phase difference between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and one of the two first effective levels is greater than 0 and less than (X+1)H, thereby allowing the first gate control signal Nscan1 and the second gate control signal Pscan1 corresponding to the same subpixel Spi to be generated from gate drive circuits GA at different levels.

[0073] Selectively, in multiple subpixels Spi located in the m-th row, the control terminal of the compensation transistor Tc is electrically connected to the p-th-order gate drive circuit GA(p) so as to receive the p-th-order first gate control signal Nscan1(p) output from the p-th-order gate drive circuit GA(p), and the control terminal of the data transistor Tda is electrically connected to the p+1-th-order gate drive circuit GA(p+1) so as to receive the p+1-th-order second gate control signal Pscan1(p+1) output from the p+1-th-order gate drive circuit GA(p+1), where m≧1 and p≧1.

[0074] In the same subpixel Spi, by making the number of stages of the gate drive circuit GA corresponding to the data transistor Tda greater than the number of stages of the gate drive circuit GA corresponding to the compensation transistor Tc, the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda can be positioned within the interval period in which the voltage drop of the first gate control signal Nscan1 changes, thereby improving the display differences between multiple subpixels Spi.

[0075] Selectively, in some embodiments, in multiple subpixels Spi located in the m-th row, the control terminal of the compensation transistor Tc is electrically connected to the first output terminal Nout of the p-th order gate drive circuit GA(p), and the control terminal of the data transistor Tda is electrically connected to the second output terminal Pout of the p-1-th order gate drive circuit GA(p-1), and the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda can be located within an interval period in which a voltage drop change occurs in the corresponding first gate control signal Nscan1.

[0076] In a selective, identical subpixel Spi, the gate drive circuit GA corresponding to the data transistor Tda and the gate drive circuit GA corresponding to the compensation transistor Tc are not cascaded. This allows the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda to be positioned at a corresponding time interval where a voltage drop change occurs in the first gate control signal Nscan1.

[0077] Referring to Figures 6 and 7, and taking X=1 as an example, in multiple subpixels Spi located in the mth row, the control terminal of the compensation transistor Tc is electrically connected to the 7th-order gate drive circuit GA(7), and the control terminal of the data transistor Tda may be electrically connected to the second output terminal Pout of the 8th-order gate drive circuit GA(8), the second output terminal Pout of the 6th-order gate drive circuit GA(6), the second output terminal Pout of the 4th-order gate drive circuit GA(4), or the second output terminal Pout of the 2nd-order gate drive circuit GA(2). Here, the effective level of the first gate control signal Nscan1 output by the 7th-order gate drive circuit GA(7) partially overlaps with the effective level of the second gate control signal Pscan1 output by the 8th-order gate drive circuit GA(8), the 6th-order gate drive circuit GA(6), the 4th-order gate drive circuit GA(4), and the 2nd-order gate drive circuit GA(2). Similarly, when X≧2, the rank of the gate drive circuit GA that can match the compensation transistor Tc and data transistor Tda in the same subpixel Spi can also be obtained.

[0078] Selectively, continuing with reference to Figure 6, a plurality of gate drive circuits GA are electrically connected to Z clock lines, and the Z clock lines are configured to transmit the corresponding second clock signal CK to the plurality of gate drive circuits GA, where Z = 2(X+1).

[0079] Selectively, Y clock lines may be shared by Z clock lines, thereby reducing the number of clock lines used by the display driver circuit Dc and is advantageous for reducing the bezel size of the display panel DP.

[0080] For example, X=1, and the Z clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, and a fourth clock line CKL4. Here, the third clock line CKL3 transmits the corresponding second clock signal CK to the 4K+1th order gate drive circuit GA, the fourth clock line CKL4 transmits the corresponding second clock signal CK to the 4K+2th order gate drive circuit GA, the first clock line CKL1 transmits the corresponding second clock signal CK to the 4K+3rd order gate drive circuit GA, and the second clock line CKL2 transmits the corresponding second clock signal CK to the 4K+4th order gate drive circuit GA.

[0081] As another example, X=2, and the Z clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, a fourth clock line CKL4, a fifth clock line, and a sixth clock line. Here, the fourth clock line CKL4 transmits the corresponding second clock signal CK to the 6K+1th order gate drive circuit GA, the fifth clock line transmits the corresponding second clock signal CK to the 6K+2nd order gate drive circuit GA, the sixth clock line transmits the corresponding second clock signal CK to the 6K+3rd order gate drive circuit GA, the first clock line CKL1 transmits the corresponding second clock signal CK to the 6K+4th order gate drive circuit GA, the second clock line CKL2 transmits the corresponding second clock signal CK to the 6K+5th order gate drive circuit GA, and the third clock line CKL3 transmits the corresponding second clock signal CK to the 6K+6th order gate drive circuit GA.

[0082] Similarly, when X > 2, the matching relationship between a multi-level gate drive circuit GA and Z clock lines can also be obtained.

[0083] It can be understood that the first gate control signal Nscan1 and the second gate control signal Pscan1 may be provided by different gate drive units. That is, in the display drive circuit Dc, the number of gate drive units can be set to multiple, and the gate drive circuit GA can be set to output only the first gate control signal Nscan1 or the second gate control signal Pscan1. For example, a display device may include two gate drive units. Here, multiple first output terminals Nout of one gate drive unit output multiple first gate control signals Nscan1, and multiple first output terminals Nout of the other gate drive unit output multiple second gate control signals Pscan1.

[0084] Selectively, the first gate control signal Nscan1 generated by multiple gate drive circuits GA can become the third gate control signal Nscan2, which is output to the control terminals of the reset transistors Tr of multiple subpixels Spi via multiple third scan lines SL3. Here, the first gate control signal Nscan1 received by the reset transistor Tr and the first gate control signal Nscan1 received by the compensation transistor Tc in the same subpixel Spi are generated by gate drive circuits GA of different ranks. Selectively, the control terminal of the reset transistor Tr of the subpixel Spi located in the mth row receives the first gate control signal Nscan1(pD) of the pDth rank, and the control terminal of the compensation transistor Tc of the subpixel Spi located in the mth row receives the first gate control signal Nscan1(p+E) of the p+E rank. Here, D≧1 and E≧1. In multiple subpixels Spi located in the mth row, the control terminal of the compensation transistor Tc is electrically connected to the first output terminal Nout of the p+1th order gate drive circuit GA(p+1), and the control terminal of the reset transistor Tc is electrically connected to the first output terminal Nout of the p-2nd order gate drive circuit GA.

[0085] In multiple subpixels Spi located in the 8th row, the control terminal of the compensation transistor Tc is electrically connected to the first output terminal Nout of the 9th-order gate drive circuit GA(9), and the control terminal of the reset transistor Tr is electrically connected to any of the second output terminals Pout of the 1st-order gate drive circuit GA(1) to the second output terminal Pout of the 7th-order gate drive circuit GA(7).

[0086] In some embodiments, selectively, the first gate control signal Nscan1 received by the compensation transistor Tc and the third gate control signal Nscan2 received by the reset transistor Tr in the same subpixel Spi are generated by a gate drive circuit GA which includes gate drive units of different levels. One gate drive unit in the display device generates multiple first gate control signals Nscan1 and outputs them to the control terminals of the compensation transistors Tc of multiple subpixels Spi, while another gate drive unit in the display drive circuit Dc generates multiple third gate control signals Nscan2 and outputs them to the control terminals of the reset transistors Tr of multiple subpixels Spi. It can be understood that the design of a gate drive unit electrically connected to the control terminals of the reset transistors Tr of multiple subpixels Spi can refer to the design of a gate drive unit electrically connected to the control terminals of the compensation transistors Tc of multiple subpixels Spi.

[0087] In some embodiments, selectively, the second gate control signal Pscan1 generated by multiple gate drive circuits GA can be the first scan signal Pscan2, which is output to the control terminal of the first initial transistor Ti1 of multiple subpixels Spi via multiple fourth scan lines SL4.

[0088] In some embodiments, a gate drive unit may be provided separately to provide the first scan signal Pscan2 required for the first initial transistor Ti1 of multiple subpixels Spi.

[0089] It can be understood that the display driver circuit Dc may have a separate gate driver unit to provide the light emission control signal EM required for the light emission control transistors of multiple subpixels Spi.

[0090] Figure 8 is a schematic diagram of the structure of a gate drive circuit provided by an embodiment of the present invention, in which each gate drive circuit GA includes a node control module 10, a first output module 20, and a first frequency division module 30.

[0091] The node control module 10 is electrically connected to the first node Q1 and the second node Q2 of the gate drive circuit GA on that floor, and is configured to control the signals transmitted to the first node Q1 and the second node Q2 based on the corresponding first clock signal XCK and the start signal STV.

[0092] The first output module 20 is electrically connected to the first node Q1 and is configured to output a first gate control signal Nscan1 based on the corresponding frequency division control signal and the signal from the first node Q1.

[0093] The first frequency division module 30 is electrically connected to the first node Q1, the second node Q2, and the first output module 20, and is configured to control signal transmission between the first node Q1 and the first output module 20 based on the corresponding frequency division control signal and the signal from the second node Q2.

[0094] Selectively, continuing with reference to Figure 8, the node control module 10 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.

[0095] The control terminal of the first transistor T1 is configured to receive the corresponding startup signal STV, and the input terminal of the first transistor T1 is electrically connected to the first power supply terminal NVGL.

[0096] The control terminal of the second transistor T2 is electrically connected to the control terminal of the first transistor T1, the input terminal of the second transistor T2 is electrically connected to the second power supply terminal PVGH, and the output terminal of the second transistor T2 is electrically connected to the output terminal of the first transistor T1.

[0097] The control terminal of the third transistor T3 is configured to receive the corresponding first clock signal XCK, the input terminal of the third transistor T3 is electrically connected to the output terminal of the first transistor T1, and the output terminal of the third transistor T3 is electrically connected to the first node Q1.

[0098] The control terminal of the fourth transistor T4 is electrically connected to the first node Q1, the input terminal of the fourth transistor T4 is electrically connected to the third power supply terminal PVGL, and the output terminal of the fourth transistor T4 is electrically connected to the second node Q2.

[0099] The control terminal of the fifth transistor T5 is electrically connected to the first node Q1, the input terminal of the fifth transistor T5 is electrically connected to the second power supply terminal PVGH, and the output terminal of the fifth transistor T5 is electrically connected to the second node Q2.

[0100] Selectively, the first transistor T1 has two control terminals, and the fourth transistor T4 has two control terminals. The first and second control terminals of the first transistor T1 are configured to receive the corresponding start signal STV, and the first and second control terminals of the fourth transistor T4 are electrically connected to the first node Q1.

[0101] Selectively, at least one node control module 10 of the gate drive circuit GA includes a sixth transistor T6. The control terminal of the sixth transistor T6 is electrically connected to the second node Q2, the input terminal of the sixth transistor T6 is electrically connected to the first power supply terminal NVGL, and the output terminal of the sixth transistor T6 is electrically connected to the first node Q1.

[0102] Selectively, the sixth transistor T6 has two control terminals, and the first and second control terminals of the sixth transistor T6 are electrically connected to the second node Q2.

[0103] Selectively, the node control module 10 of at least one gate drive circuit GA includes a seventh transistor T7 and an eighth transistor T8.

[0104] The control terminal of the seventh transistor T7 is configured to receive the corresponding first clock signal XCK, and the output terminal of the seventh transistor T7 is electrically connected to the first node Q1.

[0105] The control terminal of the 8th transistor T8 is electrically connected to the 2nd node Q2, the input terminal of the 8th transistor T8 is electrically connected to the 2nd power supply terminal PVGH, and the output terminal of the 8th transistor T8 is electrically connected to the input terminal of the 7th transistor T7.

[0106] Selectively, the seventh transistor T7 has two control terminals, and the first and second control terminals of the seventh transistor T7 are configured to receive the corresponding first clock signal XCK.

[0107] Referring to Figure 8, the first frequency division module 30 includes a first frequency division transistor Tf1, a second frequency division transistor Tf2, and a first capacitor C1.

[0108] The control terminal of the first frequency division transistor Tf1 is electrically connected to the second node Q2 of the gate drive circuit GA on that floor, and the input terminal of the first frequency division transistor Tf1 is configured to receive the corresponding frequency division control signal.

[0109] The control terminal of the second frequency division transistor Tf2 is electrically connected to the output terminal of the first frequency division transistor Tf1, the input terminal of the second frequency division transistor Tf2 is electrically connected to the first node Q1, and the output terminal of the second frequency division transistor Tf2 is electrically connected to the first output module 20 through the third node Q3.

[0110] The first terminal of the first capacitor C1 is electrically connected to the control terminal of the second frequency division transistor Tf2, and the second terminal of the first capacitor C1 is electrically connected to the third node Q3.

[0111] To selectively reduce the number of frequency division control lines FL used in the display drive circuit Dc, multiple first frequency division modules 30 may be electrically connected to the same frequency division control line FL so that the level control of multiple first gate control signals Nscan1 is achieved by frequency division control signals transmitted over a single frequency division control line FL.

[0112] Selectively, multiple frequency division control lines FL include a first frequency division control line FL1, the first frequency division control line FL1 is electrically connected to a first frequency division module 30 of a multi-story gate drive circuit GA, and the first frequency division control line FL1 provides a first frequency division control signal NLF to the first frequency division module 30 of the multi-story gate drive circuit GA.

[0113] As can be understood, the multiple first frequency division modules 30 may be electrically connected to the multiple frequency division control lines FL so as to achieve level control of the multiple first gate control signals Nscan1 by the multiple frequency division control signals transmitted on the multiple frequency division control lines FL.

[0114] Referring to Figure 8, the first output module 20 includes a first output transistor To1 and a second output transistor To2.

[0115] The control terminal of the first output transistor To1 is electrically connected to the third node Q3, and the input terminal of the first output transistor To1 is electrically connected to the fourth power supply terminal NVGH.

[0116] The control terminal of the second output transistor To2 is electrically connected to the first node Q1, the input terminal of the second output transistor To2 is electrically connected to the first power supply terminal NVGL, and the output terminal of the second output transistor To2 and the output terminal of the first output transistor To1 are electrically connected to the first output terminal Nout of the gate drive circuit GA of that floor.

[0117] Selectively, the second output transistor To2 may have two control terminals, namely the first and second control terminals of the second output transistor To2 are electrically connected to the first node Q1.

[0118] Selectively, continuing with reference to Figure 8, at least one gate drive circuit GA further includes a first control module 40, the first control module 40 including a first switching transistor Ts1 and a second switching transistor Ts2, thereby ensuring that the first gate control signal Nscan1 output by the gate drive circuit GA has relatively good stability.

[0119] The control terminal of the first switching transistor Ts1 is configured to receive the corresponding first clock signal XCK, and the output terminal of the first switching transistor Ts1 is electrically connected to the third node Q3.

[0120] The control terminal of the second switching transistor Ts2 is electrically connected to the second node Q2 of the gate drive circuit GA on that floor, the input terminal of the second switching transistor Ts2 is electrically connected to the second power supply terminal PVGH, and the output terminal of the second switching transistor Ts2 is electrically connected to the input terminal of the first switching transistor Ts1.

[0121] Selectively, the first switching transistor Ts1 has two control terminals, and the first and second control terminals of the first switching transistor Ts1 are configured to receive the corresponding first clock signal XCK.

[0122] If, selectively, the gate drive circuit GA outputs both a first gate control signal Nscan1 and a second gate control signal Pscan1, the gate drive circuit GA may further include a second output module 50 for outputting the second gate control signal Pscan1. That is, at least one gate drive circuit GA includes a second output module 50, which is electrically connected to a first node Q1 and a second node Q2 and configured to output a second gate control signal Pscan1 based on a corresponding second clock signal CK and the signals from the first node Q1 and the second node Q2.

[0123] Selectively, continuing with reference to Figure 8, the second output module 50 includes a third output transistor To3, a fourth output transistor To4, and a second capacitor C2.

[0124] The control terminal of the third output transistor To3 is electrically connected to the first node Q1, and the input terminal of the third output transistor To3 is configured to receive the corresponding second clock signal CK.

[0125] The control terminal of the fourth output transistor To4 is electrically connected to the second node Q2, the input terminal of the fourth output transistor To4 is electrically connected to the second power supply terminal PVGH, and the output terminal of the fourth output transistor To4 and the output terminal of the third output transistor To3 are electrically connected to the second output terminal Pout of the gate drive circuit GA on that floor.

[0126] The first terminal of the second capacitor C2 is electrically connected to the control terminal of the third output transistor To3, and the second terminal of the second capacitor C2 is electrically connected to the second output terminal Pout of the gate drive circuit GA of that floor.

[0127] In some embodiments, selectively, the second output module 50 of at least one gate drive circuit GA includes a third switch transistor Ts3, the control terminal of the third switch transistor Ts3 is configured to receive a switch control signal SC, the input terminal of the third switch transistor Ts3 is electrically connected to a first node Q1, and the output terminal of the third switch transistor Ts3 is electrically connected to the control terminal of a third output transistor To3.

[0128] Selectively, the switch control signal SC received by the control terminal of the third switch transistor Ts3 of the p-th order gate drive circuit GA(p) corresponds to the signal at the second node Q2 of the pC-th order gate drive circuit GA(pC). Here, C≧1.

[0129] The switch control signal SC received by the control terminal of the 11th transistor T11 of the first-floor gate drive circuit GA(1) to the fourth-floor gate drive circuit GA(4) corresponds to the low-level signal VGL, and the control terminal of the 11th transistor T11 of each gate drive circuit GA after the fourth-floor gate drive circuit GA(4) is electrically connected to the second node Q2 of the gate drive circuit GA of the previous three or four floors. The switch control signal SC corresponding to the fifth-floor gate drive circuit GA(5) corresponds to the signal of the second node Q2 of the second-floor gate drive circuit GA(2), the switch control signal SC corresponding to the sixth-floor gate drive circuit GA(6) corresponds to the signal of the second node Q2 of the third-floor gate drive circuit GA(3), or the switch control signal SC corresponding to the fifth-floor gate drive circuit GA(5) corresponds to the signal of the second node Q2 of the first-floor gate drive circuit GA(1). The switch control signal SC corresponding to the sixth-order gate drive circuit GA(6) corresponds to the signal at the second node Q2 of the second-order gate drive circuit GA(2). Similarly, the switch control signal SC corresponding to the gate drive circuits GA of the remaining orders can also be obtained.

[0130] In some embodiments, the gate drive circuit GA may also be equipped with a second frequency division module 60 to control the levels of multiple second gate control signals Pscan1.

[0131] Referring to Figure 8, at least one gate drive circuit GA includes a second frequency division module 60, which is electrically connected to a first node Q1, a second node Q2, and a second output module 50, and is configured to control signal transmission between the first node and the corresponding second output module 50 based on the corresponding frequency division control signals and the signals from the second node Q2. Accordingly, a plurality of frequency division control lines FL are configured to transmit frequency division control signals to a plurality of gate drive circuits GA so as to control the level of at least one of a plurality of second gate control signals.

[0132] Selectively, the second frequency division module 60 includes a third frequency division transistor Tf3, a fourth frequency division transistor Tf4, and a third capacitor C3.

[0133] The control terminal of the third frequency division transistor Tf3 is electrically connected to the second node Q2 of the gate drive circuit GA on that floor, and the input terminal of the third frequency division transistor Tf3 is configured to receive the corresponding frequency division control signal.

[0134] The control terminal of the fourth frequency division transistor Tf4 is electrically connected to the output terminal of the third frequency division transistor Tf3, the input terminal of the fourth frequency division transistor Tf4 is electrically connected to the first node Q1, and the output terminal of the fourth frequency division transistor Tf4 is electrically connected to the second output module 50.

[0135] The first terminal of the third capacitor is electrically connected to the control terminal of the fourth frequency division transistor Tf4, and the second terminal of the third capacitor is electrically connected to the output terminal of the fourth frequency division transistor Tf4.

[0136] Selectively, the output terminal of the fourth frequency division transistor Tf4 is electrically connected to the input terminal of the third switch transistor Ts3, controlling the transmission of signals between the second output module 50 and the first node Q1 via the fourth frequency division transistor Tf4 and the third switch transistor Ts3.

[0137] To selectively reduce the number of frequency division control lines FL used in the gate control unit, the second frequency division modules of multiple gate drive circuits GA can be electrically connected to the same frequency division control line FL.

[0138] It can be understood that the second frequency division modules of multiple gate drive circuits GA may be electrically connected to different frequency division control lines FL so that the second frequency division modules of multiple gate drive circuits GA can be controlled independently.

[0139] Selectively, in order to allow the levels of multiple first gate control signals Nscan1 and multiple second gate control signals Pscan1 to be controlled independently, the first frequency division module 30 and the second frequency division module of the same gate drive circuit GA are electrically connected to different frequency division control lines FL. Selectively, the multiple frequency division control lines FL include a first frequency division control line FL1 and a second frequency division control line. Here, the first frequency division control line FL1 is electrically connected to the first frequency division module 30 of the multi-story gate drive circuit GA, and the second frequency division control line FL2 is electrically connected to the second frequency division module 60 of the multi-story gate drive circuit GA, and the second frequency division control line FL2 transmits the second frequency division control signal PLF to the second frequency division module 60 of the multi-story gate drive circuit GA.

[0140] Selectively, in some embodiments, at least one gate drive circuit GA further includes a second control module 70, the second control module 70 including a fourth switch transistor Ts4 and a fifth switch transistor Ts5.

[0141] The control terminal of the fourth switching transistor Ts4 is configured to receive the corresponding first clock signal XCK, and the output terminal of the fourth switching transistor Ts4 is electrically connected to the input terminal of the third switching transistor Ts3.

[0142] The control terminal of the fifth switching transistor Ts5 is electrically connected to the second node Q2 of the gate drive circuit GA on that floor, the input terminal of the second switch transistor Ts5 is electrically connected to the second power supply terminal PVGH, and the output terminal of the second switch transistor Ts5 is electrically connected to the input terminal of the first switch transistor Ts4.

[0143] Selectively, a fourth switching transistor Ts4 has two control terminals, and the first and second control terminals of the fourth switching transistor Ts4 are configured to receive the corresponding first clock signal XCK.

[0144] Selectively, continuing with reference to Figure 8, at least one gate drive circuit GA further includes a reset module 80, which is electrically connected to a first node Q1 and configured to control signal transmission between a second power supply terminal PVGH and the first node Q1 based on a reset control signal Ctl.

[0145] Selectively, the clear module 80 includes a clear transistor Tre, the control terminal of the clear transistor Tre is configured to receive a reset control signal Ctl, the input terminal of the clear transistor Tre is electrically connected to a second power supply terminal PVGH, and the output terminal of the clear transistor Tre is electrically connected to a first node Q1.

[0146] Selectively, when the display driver circuit Dc is applied to the display device, the clear module 80 is configured to be active when the display device is powered on and / or during the blanking interval.

[0147] Selectively, in some embodiments, the voltage corresponding to the third power supply terminal PVGL is smaller than the voltage corresponding to the second power supply terminal PVGH, and the voltage corresponding to the first power supply terminal NVGL is smaller than the voltage corresponding to the fourth power supply terminal NVGH.

[0148] Figures 9A and 9B are timing charts corresponding to the gate drive circuit provided in the embodiment of the present application. The second transistor T2, third transistor T3, fifth transistor T5, eighth transistor T8, second switch transistor Ts2, third switch transistor Ts3, fifth switch transistor Ts5, first output transistor To1, third output transistors To3 to fourth output transistors To4, and first frequency division transistors Tf1 to fourth frequency division transistors Tf4 are P-type transistors, and the first transistor T1, fourth transistor T4, sixth transistor T6, seventh transistor T7, first switch transistor Ts1, fourth switch transistor Ts4, and second output transistor To2 are N-type transistors, X=1, and the third clock line CKL3 corresponds to the first clock signal XCK in the p-th gate drive circuit G The operating principle of multiple gate drive circuits GA will be explained using the example of a signal being transmitted to A, the fourth clock line CKL4 transmitting the corresponding first clock signal XCK to the (p+1)th-order gate drive circuit GA, the first clock line CKL1 transmitting the corresponding first clock signal XCK to the (p+3)th-order gate drive circuit GA, the first clock line CKL1 transmitting the corresponding second clock signal CK to the p-th-order gate drive circuit GA, the second clock line CKL2 transmitting the corresponding second clock signal CK to the (p+1)th-order gate drive circuit GA, the third clock line CKL3 transmitting the corresponding second clock signal CK to the (p+2)th-order gate drive circuit GA, and the fourth clock line CKL4 transmitting the corresponding second clock signal CK to the (p+3)th-order gate drive circuit GA. Here, p is an odd number.

[0149] For the first stage t1, the first clock signal CK1 transmitted by the first clock line CKL1 is in a high level state, the second clock signal CK2 transmitted by the second clock line CKL2 is in a high level state, the third clock signal CK3 transmitted by the third clock line CKL3 is in a low level state, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is in a high level state. The second node Q2 of the p-2th order gate drive circuit GA(p-2) to the second node Q2 of the p-1st order gate drive circuit GA(p-1) are in a high level state. The first frequency division control signal NLF and the second frequency division control signal PLF are in a low level state.

[0150] In the p-th order gate drive circuit GA(p), the first transistor T1, third transistor T3, fifth transistor T5, sixth transistor T6, second frequency division transistor Tf2, fourth frequency division transistor Tf4, and first output transistor To1 conduct, while the second transistor T2, fourth transistor T4, eighth transistor T8, first switch transistor Ts1, second switch transistor Ts2, third switch transistor Ts3, fourth switch transistor Ts4, fifth switch transistor Ts5, first frequency division transistor Tf1, third frequency division transistor Tf3, and second to fourth output transistors To2 to To4 are turned off. The first gate control signal Nscan1(p) and the second gate control signal Pscan1(p) of the p-th order have high levels.

[0151] In a gate drive circuit GA that follows the p-th order gate drive circuit GA(p) and where the first clock signal XCK is not supplied from the third clock line CKL3, the third transistor T3 is turned off. In a gate drive circuit GA that follows the p-th order gate drive circuit GA(p) and where the first clock signal XCK is supplied from the third clock line CKL3, the second transistor T2 and the third transistor T3 conduct. Therefore, the first gate control signals Nscan1(p+1) of the (p+1)th order to the first gate control signals Nscan1(p+11) of the (p+1)th order remain at a low level, and the second gate control signals Pscan1(p+1) of the (p+1)th order to the second gate control signals Pscan1(p+11) of the (p+1)th order have a high level.

[0152] In the second stage t2, the first clock signal CK1 transmitted by the first clock line CKL1 is in a high-level state, the second clock signal CK2 transmitted by the second clock line CKL2 is in a high-level state, the third clock signal CK3 transmitted by the third clock line CKL3 is in a high-level state, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is in a low-level state. The second node Q2 of the p-2th order gate drive circuit GA(p-2) to the second node Q2 of the p-1st order gate drive circuit GA(p-1) are in a high-level state. The first frequency division control signal NLF and the second frequency division control signal PLF are in a low-level state.

[0153] In the p-th order gate drive circuit GA(p), the third transistor T3 is turned off, and the first gate control signal Nscan1(p) and the second gate control signal Pscan1(p) of the p-th order are at a high level.

[0154] The operation performed by the (p+1)th-order gate drive circuit GA(p+1) in the second stage t2 is similar to that performed by the p-th-order gate drive circuit GA(p) in the first stage t1. The operation performed by the (p+2)th-order gate drive circuit GA(p+2) in the second stage t2 is similar to that performed by the (p+1)th-order gate drive circuit GA(p+1) in the first stage t1. By sequential analogy, the steps performed by the (p+3)th-order gate drive circuit GA(p+3) to the (p+11th-order) gate drive circuit GA(p+11) in the second stage t2 are obtained. Therefore, the first gate control signal Nscan1(p+1) at the (p+1)th level has a high level, the first gate control signals Nscan1(p+2) at the (p+2)th level to the first gate control signals Nscan1(p+11) at the (p+11th) level have a low level, and the second gate control signals Pscan1(p+1) at the (p+1)th level to the second gate control signals Pscan1(p+11) at the (p+11th) level have a high level.

[0155] In the third stage t3, the first clock signal CK1 transmitted by the first clock line CKL1 is in a low level state, the second clock signal CK2 transmitted by the second clock line CKL2 is in a high level state, the third clock signal CK3 transmitted by the third clock line CKL3 is in a high level state, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is in a high level state. The second node Q2 of the p-2th order gate drive circuit GA(p-2) to the second node Q2 of the p-1st order gate drive circuit GA(p-1) are in a high level state. The first frequency division control signal NLF and the second frequency division control signal PLF are in a low level state.

[0156] In the p-th order gate drive circuit GA(p), the third transistor T3 is turned off, and the first gate control signal Nscan1(p) and the second gate control signal Pscan1(p) of the p-th order are at a high level. The start signal STV corresponding to the p+2-th order gate drive circuit GA(p+2) is provided by the p-th order gate drive circuit GA(p), and the operation performed by the p+2-th order gate drive circuit GA(p+2) in the third stage t3 is similar to that performed by the p-th order gate drive circuit GA(p) in the first stage t1. Therefore, in the third stage t3, the first output terminal Nout of the p+2-th order gate drive circuit GA(p+2) is electrically connected to the fourth power supply terminal NVGH, resulting in an increase in the load corresponding to the fourth power supply terminal NVGH, and furthermore, the first gate control signal Nscan1(p) of the p-th order shows a voltage drop.

[0157] The operation performed by the (p+1)th-order gate driver circuit GA(p+1) in the third stage t3 is similar to that performed by the p-th-order gate driver circuit GA(p) in the second stage t2. The operation performed by the (p+2)th-order gate driver circuit GA(p+2) in the third stage t3 is similar to that performed by the (p+1)th-order gate driver circuit GA(p+1) in the second stage t2. By sequential analogy, the steps performed by the (p+3)th-order gate driver circuit GA(p+3) to the (p+11th-order gate driver circuit GA(p+11) in the third stage t3 are obtained. Therefore, the (p+1)th-order first gate control signal Nscan1(p+1) to the (p+2)th-order first gate control signal Nscan1(p+2) have a high level. The first gate control signals Nscan1(p+3) at the p+3rd level to the first gate control signals Nscan1(p+11) at the p+11th level have a low level, while the second gate control signals Pscan1(p+1) at the p+1st level to the second gate control signals Pscan1(p+11) at the p+11th level have a high level.

[0158] In the fourth stage t4, the first clock signal CK1 transmitted by the first clock line CKL1 is in a high level state, the second clock signal CK2 transmitted by the second clock line CKL2 is in a high level state, the third clock signal CK3 transmitted by the third clock line CKL3 is in a low level state, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is in a high level state. The second node Q2 of the p-2th order gate drive circuit GA(p-2) to the second node Q2 of the p-1st order gate drive circuit GA(p-1) are in a high level state. The first frequency division control signal NLF and the second frequency division control signal PLF are in a low level state.

[0159] The operation performed by the p-th order gate drive circuit GA(p) in the fourth stage t4 is similar to that performed by the p-th order gate drive circuit GA(p) in the first stage t1. Furthermore, the activation signal STV corresponding to the p+4th order gate drive circuit GA(p+4) is provided by the p+2th order gate drive circuit GA(p+2), and the operation performed by the p+4th order gate drive circuit GA(p+4) in the fourth stage t4 is similar to that performed by the p-th order gate drive circuit GA(p) in the first stage t1. Therefore, in the fourth stage t4, the first output terminal Nout of the p+4th order gate drive circuit GA(p+4) is electrically connected to the fourth power supply terminal NVGH. As a result, the load corresponding to the fourth power supply terminal NVGH increases, and consequently, the p-th order first gate control signal Nscan1(p) shows a voltage drop.

[0160] In a gate drive circuit GA that follows the p-th order gate drive circuit GA(p) and where the first clock signal XCK is not supplied from the third clock line CKL3, the third transistor T3 is turned off. In a gate drive circuit GA that follows the p-th order gate drive circuit GA(p) and where the first clock signal XCK is supplied from the third clock line CKL3, the second transistor T2 and the third transistor T3 conduct. Therefore, the first gate control signals Nscan1(p+1) to the p+4th order first gate control signals Nscan1(p+4) have a high level, the first gate control signals Nscan1(p+5) to the p+11th order first gate control signals Nscan1(p+11) have a low level, and the second gate control signals Pscan1(p+1) to the p+11th order second gate control signals Pscan1(p+11) have a high level.

[0161] In the fifth stage t5, the first clock signal CK1 transmitted by the first clock line CKL1 is in a high level state, the second clock signal CK2 transmitted by the second clock line CKL2 is in a high level state, the third clock signal CK3 transmitted by the third clock line CKL3 is in a high level state, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is in a low level state. The second node Q2 of the p-2th order gate drive circuit GA(p-2) to the second node Q2 of the p-1st order gate drive circuit GA(p-1) are in a high level state. The first frequency division control signal NLF and the second frequency division control signal PLF are in a low level state.

[0162] In the p-th order gate drive circuit GA(p), the third transistor T3 is turned off, and the first gate control signal Nscan1(p) and the second gate control signal Pscan1(p) of the p-th order are at a high level.

[0163] The operation performed by the (p+1)th-order gate driver circuit GA(p+1) in the fifth stage t5 is similar to that performed by the p-th-order gate driver circuit GA(p) in the fourth stage t4. The operation performed by the (p+2)th-order gate driver circuit GA(p+2) in the fifth stage t5 is similar to that performed by the (p+1)th-order gate driver circuit GA(p+1) in the fourth stage t4. By sequential analogy, the steps performed by the (p+3)th-order gate driver circuit GA(p+3) to the (p+11th-order gate driver circuit GA(p+11) in the fifth stage t5 are obtained. Therefore, the first gate control signals Nscan1(p+1) of the (p+1)th-order to the first gate control signals Nscan1(p+5) of the (p+5th-order) have a high level. The first gate control signals Nscan1(p+6) at the p+6th level to the first gate control signals Nscan1(p+11) at the p+11th level have a low level, while the second gate control signals Pscan1(p+1) at the p+1st level to the second gate control signals Pscan1(p+11) at the p+11th level have a high level.

[0164] In the sixth stage t6, the first clock signal CK1 transmitted by the first clock line CKL1 is in a low level state, the second clock signal CK2 transmitted by the second clock line CKL2 is in a high level state, the third clock signal CK3 transmitted by the third clock line CKL3 is in a high level state, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is in a high level state. The second node Q2 of the p-2th order gate drive circuit GA(p-2) is in a low level state, and the second node Q2 of the p-1st order gate drive circuit GA(p-1) is in a high level state. The first frequency division control signal NLF and the second frequency division control signal PLF are in a low level state.

[0165] In the p-th gate drive circuit GA(p), the second switch transistor Ts2 and the third output transistor To3 conduct, the first gate control signal Nscan1(p) of the p-th stage has a high level, and the second gate control signal Pscan1(p) of the p-th stage has a low level. The start signal STV corresponding to the p+6th gate drive circuit GA(p+6) is provided by the p+4th gate drive circuit GA(p+4), and the operation performed by the p+6th gate drive circuit GA(p+6) in the sixth stage t6 is similar to that performed by the p-th gate drive circuit GA(p) in the first stage t1. Therefore, in the sixth stage t6, the first output terminal Nout of the p+6th gate drive circuit GA(p+6) is electrically connected to the fourth power supply terminal NVGH. As a result, the load corresponding to the fourth power supply terminal NVGH increases, and consequently, the first gate control signal Nscan1(p) of the p-th stage shows a voltage drop.

[0166] The operation performed by the (p+1)th-order gate driver circuit GA(p+1) in the 6th stage t6 is similar to that performed by the p-th-order gate driver circuit GA(p) in the 5th stage t5. The operation performed by the (p+2)th-order gate driver circuit GA(p+2) in the 6th stage t6 is similar to that performed by the (p+1)th-order gate driver circuit GA(p+1) in the 5th stage t5. By sequential analogy, the steps performed by the (p+3)th-order gate driver circuit GA(p+3) to the (p+11th-order gate driver circuit GA(p+11) in the 6th stage t6 are obtained. Therefore, the first gate control signals Nscan1(p+1) of the (p+1)th-order to the first gate control signals Nscan1(p+6) of the (p+6th-order) order have a high level. The first gate control signals Nscan1(p+7) at the p+7th level to the first gate control signals Nscan1(p+11) at the p+11th level have a low level, while the second gate control signals Pscan1(p+1) at the p+1st level to the second gate control signals Pscan1(p+11) at the p+11th level have a high level.

[0167] In the seventh stage t7, the first clock signal CK1 transmitted by the first clock line CKL1 is in a high level state, the second clock signal CK2 transmitted by the second clock line CKL2 is in a high level state, the third clock signal CK3 transmitted by the third clock line CKL3 is in a low level state, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is in a high level state. The second node Q2 of the p-2th order gate drive circuit GA(p-2) and the second node Q2 of the p-1st order gate drive circuit GA(p-1) are in a low level state. The first frequency division control signal NLF and the second frequency division control signal PLF are in a low level state.

[0168] In the p-th order gate drive circuit GA(p), the second transistor T2, the third transistor T3, the fourth transistor T4, the second switch transistor Ts2, the first frequency division transistors Tf1 to the fourth frequency division transistors Tf4, the second output transistor To2, and the fourth output transistor To4 conduct. The first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the first switch transistor Ts1, the second switch transistor Ts2, the fourth switch transistor Ts4, the fifth switch transistor Ts5, the first frequency division transistor, and the third frequency division transistor To3 are turned off. The first gate control signal Nscan1(p) of the p-th order has a low level, and the second gate control signal Pscan1(p) of the p-th order has a high level.

[0169] The operation performed by the (p+1)th-order gate driver circuit GA(p+1) in the 7th stage t7 is similar to that performed by the p-th-order gate driver circuit GA(p) in the 4th stage t4. The operation performed by the (p+2)th-order gate driver circuit GA(p+2) in the 7th stage t7 is similar to that performed by the (p+2)th-order gate driver circuit GA(p+2) in the 4th stage t4. By sequential analogy, the steps performed by the (p+3)th-order gate driver circuit GA(p+3) to the (p+11th-order gate driver circuit GA(p+11) in the 7th stage t7 are obtained. Therefore, the first gate control signals Nscan1(p+1) of the (p+1)th-order to the first gate control signals Nscan1(p+8) of the (p+8th-order) have a high level. The first gate control signals Nscan1(p+9) at the p+9th level to the first gate control signals Nscan1(p+11) at the p+11th level have low levels, the second gate control signal Pscan1(p+1) at the p+1st level, the second gate control signals Pscan1(p+3) at the p+3rd level to the second gate control signals Pscan1(p+11) at the p+11th level have high levels, and the second gate control signal Pscan1(p+2) at the p+2nd level have low levels.

[0170] Continuing with Figure 9A, in the eighth stage t8, the first clock signal CK1 transmitted by the first clock line CKL1 is in a low level state, the second clock signal CK2 transmitted by the second clock line CKL2 is in a high level state, the third clock signal CK3 transmitted by the third clock line CKL3 is in a low level state, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is in a high level state. The first frequency division control signal NLF is in a high level state, and the second frequency division control signal PLF is in a low level state.

[0171] The first gate control signals Nscan1(p) of the p-th order to the first gate control signals Nscan1(p+2) of the p+2th order have a low level, the first gate control signals Nscan1(p+3) of the p+3rd order to the first gate control signals Nscan1(p+9) of the p+9th order have a high level, the second gate control signal Pscan1(p+4) of the p+4th order has a low level, the second gate control signals Nscan1(p) of the p-th order to the second gate control signals Pscan1(p+3) of the p+3rd order and the second gate control signals Pscan1(p+5) of the p+5th order to the first gate control signals Nscan1(p+9) of the p+9th order have a high level.

[0172] In the p+10th gate drive circuit GA, the first transistor T1, third transistor T3, fifth transistor T5, sixth transistor T6, and fourth frequency division transistor Tf4 conduct, while the second transistor T2, fourth transistor T4, eighth transistor T8, first switch transistor Ts1, fourth switch transistor Ts4, second switch transistor Ts2, third switch transistor Ts3, fifth switch transistor Ts5, first frequency division transistor Tf1, second frequency division transistor Tf2, third frequency division transistor Tf3, and first to fourth output transistors To1 to To4 turn off. The first gate control signal Nscan1(p+10) of the p+10th order has a low level, and the second gate control signal Pscan1(p+10) of the p+10th order has a high level.

[0173] In the p+11th order gate drive circuit GA, the third transistor T3 is turned off, the first gate control signal Nscan1(p+11) of the p+11th order has a low level, and the second gate control signal Pscan1(p+11) of the p+11th order has a high level.

[0174] Referring to Figure 9A, in the ninth stage t9, the first clock signal CK1 transmitted by the first clock line CKL1 is in a high level state, the second clock signal CK2 transmitted by the second clock line CKL2 is in a low level state, the third clock signal CK3 transmitted by the third clock line CKL3 is in a high level state, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is in a high level state. The first frequency division control signal NLF is in a high level state, and the second frequency division control signal PLF is in a low level state.

[0175] The first gate control signals Nscan1(p) of the p-th order to the first gate control signals Nscan1(p+3) of the p+3-th order have a low level, the first gate control signals Nscan1(p+4) of the p+4-th order to the first gate control signals Nscan1(p+9) of the p+9-th order have a high level, the second gate control signal Pscan1(p+5) of the p+5-th order has a low level, and the second gate control signals Nscan1(p) of the p-th order to the second gate control signals Pscan1(p+4) of the p+4-th order and the second gate control signals Pscan1(p+6) of the p+6-th order to the second gate control signals Nscan1(p+9) of the p+9-th order have a high level.

[0176] In the p+10th gate drive circuit GA, the third transistor T3 is turned off, the first gate control signal Nscan1(p+10) of the p+10th order has a low level, and the second gate control signal Pscan1(p+10) of the p+10th order has a high level.

[0177] The operation performed by the p+11th gate drive circuit GA(p+11) in the 9th stage t9 is similar to that performed by the p+10th gate drive circuit GA(p+10) in the 8th stage t8. Therefore, the first gate control signal Nscan1(p+11) of the p+11th stage has a low level, and the second gate control signal Pscan1(p+11) of the p+11th stage has a high level.

[0178] Referring to Figure 9B, in the eighth stage t8, the first clock signal CK1 transmitted by the first clock line CKL1 is in a low level state, the second clock signal CK2 transmitted by the second clock line CKL2 is in a high level state, the third clock signal CK3 transmitted by the third clock line CKL3 is in a high level state, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is in a high level state. The first frequency division control signal NLF is in a low level state, and the second frequency division control signal PLF is in a high level state.

[0179] The first gate control signals Nscan1(p) of the p-th order to the first gate control signals Nscan1(p+2) of the p+2th order have a low level, the first gate control signals Nscan1(p+3) of the p+3rd order to the first gate control signals Nscan1(p+9) of the p+9th order have a high level, the second gate control signal Pscan1(p+4) of the p+4th order has a low level, the second gate control signals Nscan1(p) of the p-th order to the second gate control signals Pscan1(p+3) of the p+3rd order and the second gate control signals Pscan1(p+5) of the p+5th order to the second gate control signals Nscan1(p+9) of the p+9th order have a high level.

[0180] In the p+10th gate drive circuit GA, the first transistor T1, third transistor T3, fifth transistor T5, sixth transistor T6, second frequency division transistor Tf2, and first output transistor To1 conduct, while the second transistor T2, fourth transistor T4, eighth transistor T8, first switch transistor Ts1, fourth switch transistor Ts4, second switch transistor Ts2, third switch transistor Ts3, fifth switch transistor Ts5, first frequency division transistor Tf1, third frequency division transistor Tf3, fourth frequency division transistor Tf4, and second to fourth output transistors To2 to To4 are turned off. The p+10th first gate control signal Nscan1(p+10) has a high level, and the p+10th second gate control signal Pscan1(p+10) also has a high level.

[0181] In the p+11th order gate drive circuit GA, the third transistor T3 is turned off, the first gate control signal Nscan1(p+11) of the p+11th order has a low level, and the second gate control signal Pscan1(p+11) of the p+11th order has a high level.

[0182] Referring to Figure 9B, in the ninth stage t9, the first clock signal CK1 transmitted by the first clock line CKL1 is in a high level state, the second clock signal CK2 transmitted by the second clock line CKL2 is in a high level state, the third clock signal CK3 transmitted by the third clock line CKL3 is in a low level state, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is in a high level state. The first frequency division control signal NLF is in a low level state, and the second frequency division control signal PLF is in a high level state.

[0183] The first gate control signals Nscan1(p) of the p-th order to the first gate control signals Nscan1(p+8) of the p+8th order have a low level, the first gate control signals Nscan1(p+9) of the p+9th order to the first gate control signals Nscan1(p+11) of the p+11th order have a high level, and the second gate control signals Pscan1(p) of the p-th order to the second gate control signals Nscan1(p+4) of the p+9th order and the second gate control signals Pscan1(p+11) of the p+11th order have a high level.

[0184] In the p+10th order gate drive circuit GA, the fourth frequency division transistor Tf4 is turned off, and the p+10th order second gate control signal Pscan1(p+10) has a high level.

[0185] Continuing with Figure 9B, in the 10th stage t10, the first clock signal CK1 transmitted by the first clock line CKL1 is in a high level state, the second clock signal CK2 transmitted by the second clock line CKL2 is in a high level state, the third clock signal CK3 transmitted by the third clock line CKL3 is in a high level state, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is in a low level state. The first frequency division control signal NLF is in a low level state, and the second frequency division control signal PLF is in a high level state.

[0186] The first gate control signals Nscan1(p) of the p-th order to the first gate control signals Nscan1(p+9) of the p+9th order have a low level, the first gate control signals Nscan1(p+10) of the p+10th order to the first gate control signals Nscan1(p+11) of the p+11th order have a high level, and the second gate control signals Pscan1(p) of the p-th order to the second gate control signals Pscan1(p+10) of the p+10th order have a high level.

[0187] In the p+11th order gate drive circuit GA, the fourth frequency division transistor Tf4 is turned off, and the p+11th order second gate control signal Pscan1(p+11) has a high level.

[0188] Therefore, by controlling the level of the first frequency division control signal NLF, the levels of multiple first gate control signals Nscan1 can be controlled, and by controlling the level of the second frequency division control signal PLF, the levels of multiple second gate control signals Pscan1 can be controlled.

[0189] Similarly, the operating principle of a multi-level gate drive circuit GA can be obtained when the first frequency division control signal NLF and the second frequency division control signal PLF jump from a high level to a low level.

[0190] Selectively, the hopping timing between the high and low levels of the first frequency division control signal NLF and the second frequency division control signal PLF may be the same or different.

[0191] Figure 10 is a timing chart of the corresponding subpixels provided in the embodiment of the present invention. The operating principle of the subpixel Spi located in the mth row will be explained using an example in which the compensation transistor Tc and reset transistor Tr are N-type transistors, and the drive transistor Tdr, first initial transistor Ti1, second initial transistor Ti2, first light emission control transistor Te1, and second light emission control transistor Te2 are P-type transistors. Here, the first gate control signal Nscan1 received by the control terminal of the compensation transistor Tc of the subpixel Spi in the mth row corresponds to the output from the first output terminal Nout of the gate drive circuit GA at the (p+1)th order, and the second gate control signal Pscan1 received by the control terminal of the data transistor Tda of the subpixel Spi in the mth row corresponds to the output from the second output terminal Pout of the gate drive circuit GA at the (p+2)th order. The third gate control signal Nscan2 received by the control terminal of the reset transistor Tr of the subpixel Spi in the mth row corresponds to the output from the first output terminal Nout of the gate drive circuit GA at the (p-2)th order. The gate drive circuit GA corresponding to the reset transistor Tr and the gate drive circuit GA corresponding to the compensation transistor Tc can be classified into different gate drive units, the gate drive circuit GA corresponding to the data transistor Tda and the gate drive circuit GA corresponding to the compensation transistor Tc can belong to the same gate drive unit, and / or the gate drive circuit GA corresponding to the data transistor Tda and the gate drive circuit GA corresponding to the reset transistor Tr can belong to the same gate drive unit.

[0192] In the first reset stage Si1, the light emission control signal EM corresponding to the m-th row subpixel Spi is at a high level, the first scan signal Pscan2 corresponding to the m-th row subpixel Spi is at a low level, the first gate control signal Nscan1 corresponding to the m-th row subpixel Spi is at a low level, the second gate control signal Pscan1 corresponding to the m-th row subpixel Spi is at a high level, and the third gate control signal Nscan2 corresponding to the m-th row subpixel Spi is at a low level. The first initial signal Vi1 transmitted by the first initial line is transmitted to the anode of the light-emitting element Di to reset its anode potential, and the second initial signal Vi2 transmitted by the second initial line is transmitted to the input and output terminals of the drive transistor Tdr to reset their potentials.

[0193] In the second reset stage Si2, the light emission control signal EM corresponding to the m-th row subpixel Spi is at a high level, the first scan signal Pscan2 corresponding to the m-th row subpixel Spi is at a high level, the first gate control signal Nscan1 corresponding to the m-th row subpixel Spi is at a low level, the second gate control signal Pscan1 corresponding to the m-th row subpixel Spi is at a high level, and the third gate control signal Nscan2 corresponding to the m-th row subpixel Spi is at a high level. The reset transistor Tr conducts, and the reset signal Vr is transmitted to the gate of the drive transistor Tdr to reset the potential of the control terminal of the drive transistor Tdr.

[0194] During the data writing phase Sw, the light emission control signal EM corresponding to the m-th row subpixel Spi is at a high level, the first scan signal Pscan2 corresponding to the m-th row subpixel Spi is at a high level, the first gate control signal Nscan1 corresponding to the m-th row subpixel Spi is at a high level, the second gate control signal Pscan1 corresponding to the m-th row subpixel Spi is at a low level, and the third gate control signal Nscan2 corresponding to the m-th row subpixel Spi is at a low level. The data transistor Tda and the compensation transistor Tc conduct, and the data signal is transmitted to the control terminal of the drive transistor Tdr.

[0195] Here, between the second reset stage Si2 and the data writing stage Sw, there may be a further step of controlling and simultaneously conducting the reset transistor Tr and the compensation transistor Tc in order to transmit a reset signal Vr to the output and input terminals of the drive transistor Tdr and to reset the potentials of the output and input terminals of the drive transistor Tdr.

[0196] In the third reset stage Si3, the light emission control signal EM corresponding to the m-th row subpixel Spi is at a high level, the first scan signal Pscan2 corresponding to the m-th row subpixel Spi is at a low level, the first gate control signal Nscan1 corresponding to the m-th row subpixel Spi is at a low level, the second gate control signal Pscan1 corresponding to the m-th row subpixel Spi is at a high level, and the third gate control signal Nscan2 corresponding to the m-th row subpixel Spi is at a low level. The first initial signal Vi1 is transmitted to the anode of the light-emitting element Di, and the second initial signal Vi2 is transmitted to the input and output terminals of the drive transistor Tdr.

[0197] In the light emission stage Sd, the light emission control signal EM corresponding to the m-th row subpixel Spi is low level, the first scan signal Pscan2 corresponding to the m-th row subpixel Spi is high level, the first gate control signal Nscan1 corresponding to the m-th row subpixel Spi is low level, the second gate control signal Pscan1 corresponding to the m-th row subpixel Spi is high level, and the third gate control signal Nscan2 corresponding to the m-th row subpixel Spi is low level. The first light emission control transistor Te1 and the second light emission control transistor Te2 conduct, and the drive transistor Tdr generates a drive current to drive the corresponding light-emitting element Di.

[0198] In the fourth reset stage Si4 and the fifth reset stage Si5, the light emission control signal EM corresponding to the m-th row subpixel Spi is at a high level, the first scan signal Pscan2 corresponding to the m-th row subpixel Spi is at a low level, the first gate control signal Nscan1 corresponding to the m-th row subpixel Spi is at a low level, the second gate control signal Pscan1 corresponding to the m-th row subpixel Spi is at a high level, and the p-2th order third gate control signal Nscan2 is at a low level. The first initial signal is transmitted to the anode of the light-emitting element Di, and the second initial signal is transmitted to the input and output terminals of the drive transistor Tdr.

[0199] Here, the write frame WF includes a first reset stage Si1, a second reset stage Si2, a data write stage Sw, a third reset stage Si3, and an emission stage Sd, while the hold frame HF includes a fourth reset stage Si4, a fifth reset stage Si5, and an emission stage Sd.

[0200] In some embodiments, selectively, the invalid level pulse width of the light emission control signal EM in the write frame WF is 60H, the effective level pulse width of the first scan signal Pscan2 is 4H, the effective level pulse width of the first gate control signal Nscan1 and the third gate control signal Nscan2 is 24H, and the effective level pulse width of the second gate control signal Pscan1 is 1H. The phase difference between the point in time when the light emission control signal EM begins to have an invalid level corresponding to the write frame WF and the start of the first reset stage Si1 is 8H, the phase difference between the first reset stage Si1 and the second reset stage Si2 is 8H, and the phase difference between the third gate control signal Nscan2 and the first gate control signal Nscan1 is 3H. The phase difference between the timing when the first gate control signal Nscan1 jumps from the active level to the inactive level in response to the write frame WF and the start timing of the third reset stage Si3 is 2H. The phase difference between the timing when the third gate control signal Nscan2 jumps from the active level to the inactive level and the timing when the second gate control signal Pscan1 begins to have an active level is 2H. The phase difference between the timing when the second gate control signal Pscan1 begins to have an active level and the timing when the first gate control signal Nscan1 jumps from the active level to the inactive level is 1H. The phase difference between the end timing of the third reset stage Si3 and the timing when the light emission control signal EM jumps from the inactive level to the active level is 7H.

[0201] As can be seen from the analysis in Figures 9A to 9B and Figure 10, when each of the multiple subpixels Spi corresponds to refresh the display data, it is within the interval time difference in which a voltage drop change occurs in the first gate control signal Nscan1 applied to each of them. Therefore, by improving the charge difference of the subpixels Spi at the corresponding frequency division position, the problem of display unevenness is improved.

[0202] Figure 11 is a schematic diagram of the high-frequency and low-frequency screen display principles provided in the embodiment of the present application. The writing frame WF and the holding frame HF will be explained using still image display by the display panel DP as an example.

[0203] When the display panel DP displays at a high frequency (such as 60Hz), the display panel DP needs to perform a refresh operation of the display data 60 times per second, that is, it contains 60 frames per second, and the display data is refreshed after each frame is displayed. Correspondingly, the subpixel Spi matches the time-series data of the write frame WF shown in Figure 10 for each frame.

[0204] On the other hand, when the display panel DP is displayed at a low frequency (such as 1 Hz), the display panel DP includes a screen with 60 frames per second, but only the first frame of the screen undergoes a refresh operation of the display data. Correspondingly, the subpixel Spi only matches the time-series data of the write frame WF shown in Figure 10 for the first frame F1, and for the 59 consecutive frames after the first frame F1, it holds the screen data signal of the first frame without performing a refresh operation of the display data. Correspondingly, the subpixel Spi matches the time-series data of the hold frame HF shown in Figure 10 for the 59 consecutive frames after the first frame F1.

[0205] Here, frames that refresh the display data can be described as write frames WF, and frames that do not refresh the display data can be described as hold frames HF.

[0206] Therefore, in the write frame WF, if the first gate control signal Nscan1 corresponding to the compensation transistor Tc, the third gate control signal Nscan2 corresponding to the reset transistor Tr, and the second gate control signal Pscan1 corresponding to the data transistor Tda all need to have an effective level, the existing data signal stored at the control terminal of the drive transistor Tdr can be overwritten with the newly written data signal, thereby displaying the subpixel Spi based on the newly written data signal in the write frame WF.

[0207] On the other hand, in the retained frame HF, the first gate control signal Nscan1 corresponding to the compensation transistor Tc of some subpixels Spi and the third gate control signal Nscan2 corresponding to the reset transistor Tr are kept at an inactive level, turning off the compensation transistor Tc and the reset transistor Tr, so that the control terminal of the drive transistor Tdr is not stored in a new data signal. In the retained frame HF, the second gate control signal Pscan1 corresponding to the data transistor Tda can maintain the same frequency as the written frame WF. Alternatively, in the retained frame HF, the second gate control signal Pscan1 corresponding to the data transistor Tda can be kept at an inactive level such that the frequency of the second gate control signal Pscan1 corresponding to the data transistor Tda in the retained frame HF is lower than the frequency of the written frame WF.

[0208] By combining the analyses in Figures 9A-9B, 10, and 11, the principle of frequency division display using a display panel DP with a display drive circuit Dc applied will be explained.

[0209] In the first frame F1 of one display period, it is necessary to control the first frequency division control signal NLF and the second frequency division control signal PLF to maintain the effective level state so that the control terminals of the drive transistor Tdr of multiple subpixels Spi are all written to new data signals, and each of the multiple rows of subpixels Spi in the display panel DP goes through the write frame WF stage shown in Figure 10. Here, one display period is 1 A frame may be included, or it may include multiple frames. If a display period includes one frame, this frame is, i.e., a write frame WF of multiple lines of subpixel Spi. If a display period includes multiple frames, the first frame F1 is, i.e., a write frame WF of multiple lines of subpixel Spi.

[0210] In the second frame F2 of one display period, if the subpixels Spi of the first row to the L-1 row of the display panel DP are displayed at a high frequency, and one Spi of the L row and the subpixels Spi of subsequent rows are displayed at a low frequency, then the first gate control signal Nscan1, the second gate control signal Pscan1, and the third gate control signal Nscan2 applied to the subpixels Spi of the first row to the L-1 row must all have active pulses, so that the subpixels Spi of the first row to the L row all go through the write frame WF stage shown in Figure 10. On the other hand, the first gate control signal Nscan1, the second gate control signal Pscan1, and the third gate control signal Nscan2 applied to the subpixels Spi of the L row and the subpixels Spi of subsequent rows do not need to have active pulses, so that the subpixels Spi of the L row and the subpixels Spi of subsequent rows all go through the hold frame HF stage shown in Figure 10. Here, the second frame, F2, is positioned after the first frame, F1.

[0211] Therefore, for the subpixels Spi in the first row to the subpixels Spi in the (L-1)th row, the second frame F2 is still the write frame WF, while for the subpixels Spi in the (L)th row and subsequent rows of subpixels Spi, the second frame F2 is the hold frame HF. Consequently, corresponding to the second frame F2, the control terminal of the drive transistor Tdr for the subpixels Spi in the first row to the subpixels Spi in the (L-1)th row has data signal writing capabilities, while the control terminal of the drive transistor Tdr for the subpixels Spi in the (L)th row and subsequent rows of subpixels Spi does not have data signal writing capabilities. Thus, the subpixels Spi in the first row to the subpixels Spi in the (L-1)th row and the subpixels Spi in the (L)th row and subsequent rows of subpixels Spi are distinguished by the fresh rate corresponding to the second frame F2, enabling the display panel DP to implement a frequency division display function.

[0212] In each of the multiple subpixels Spi, the effective level of the second gate control signal Pscan1 received by the data transistor Tda is within the time interval difference at which a change in voltage drop occurs in the first gate control signal Nscan1 received by the compensation transistor Tc. As a result, the charge difference of the subpixels Spi is improved in some rows of subpixels Spi from the first row to the L-1 row that are close to the frequency division position, and the problem of display unevenness is improved.

[0213] This specification has described the principles and embodiments of the present invention using specific examples, but the above description of embodiments is merely intended to aid in understanding the method and core concept of the present application. Furthermore, those skilled in the art will know that there are modifications in the specific embodiments and scope of application based on the concept of the present application. Thus, the contents of this specification should not be understood as limiting the present application. [Explanation of Symbols]

[0214] 10: Node control module 20: First output module 30: First frequency division module 40: First control module 50: Second output module 60: Second frequency division module 70: Second control module

Claims

1. A display device, It includes a display panel and a display driver circuit, The display panel includes a plurality of subpixels, each of which includes a light-emitting element, a drive transistor, a data transistor, and a compensation transistor, wherein the drive transistor is configured to drive the light emission of the light-emitting element, and the data transistor and the compensation transistor are configured to transmit a data signal to the control terminal of the drive transistor. The display drive circuit is electrically connected to the display panel and configured to output a plurality of first gate control signals to the control terminals of the compensation transistors of a plurality of subpixels, and to output a plurality of second gate control signals to the control terminals of the data transistors of a plurality of subpixels, and the display drive circuit includes a plurality of gate drive circuits and a plurality of frequency division control lines, wherein the plurality of frequency division control lines are configured to transmit frequency division control signals to the plurality of gate drive circuits so as to control the level of at least one of the plurality of first gate control signals, and each of the plurality of gate drive circuits is configured to generate the first gate control signal based on a corresponding start signal and a first clock signal, X gate drive circuits are separated between two cascaded gate drive circuits, the phase difference of the first clock signal corresponding to the two cascaded gate drive circuits is (X+1)H, in at least one subpixel the effective level of the first gate control signal corresponding to the compensation transistor and the effective level of the second gate control signal corresponding to the data transistor overlap at least partially, the effective level of the second gate control signal corresponding to the data transistor lies between the two first effective levels of the first clock signal applied to the gate drive circuit corresponding to the compensation transistor, the phase difference between the effective level of the second gate control signal corresponding to the data transistor and one of the two first effective levels is greater than 0 and less than (X+1)H, where X≧1 and H represents unit time. A display device characterized by the following features.

2. X = 1, and multiple gate drive circuits on odd-numbered floors are cascaded, and multiple gate drive circuits on even-numbered floors are cascaded, The phase difference between the activation signal corresponding to the nth gate drive circuit and the activation signal corresponding to the (n+1)th gate drive circuit is 1H, and n is an odd number. The display device according to feature 1.

3. Multiple gate drive circuits are electrically connected to Y clock lines, and the Y clock lines are configured to transmit the corresponding first clock signal to the multiple gate drive circuits, where Y = 2(X + 1). The display device according to feature 1.

4. X = 1, and the Y clock lines include a first clock line, a second clock line, a third clock line, and a fourth clock line. The first clock line transmits the corresponding first clock signal to the gate drive circuit at the 4K+1th order, the second clock line transmits the corresponding first clock signal to the gate drive circuit at the 4K+2nd order, the third clock line transmits the corresponding first clock signal to the gate drive circuit at the 4K+3rd order, and the fourth clock line transmits the corresponding first clock signal to the gate drive circuit at the 4K+4th order, where K≧0. The display device according to feature 3.

5. Each of the multiple gate drive circuits is configured to generate a plurality of second gate control signals based on the corresponding activation signal, the first clock signal, and the second clock signal. The first gate control signal and the second gate control signal corresponding to the same subpixel are generated by the gate drive circuits at different levels. The display device according to any one of claims 1 to 4.

6. In a plurality of subpixels located in the m-th row, the control terminal of the compensation transistor is electrically connected to the p-th The display device according to feature 5.

7. Multiple gate drive circuits are electrically connected to Z clock lines, and the Z clock lines are configured to transmit the corresponding second clock signal to the multiple gate drive circuits, where Z = 2(X + 1). The display device according to feature 5.

8. X = 1, and the Z clock lines include a first clock line, a second clock line, a third clock line, and a fourth clock line. The third clock line transmits the corresponding second clock signal to the gate drive circuit at the 4K+1th floor, the fourth clock line transmits the corresponding second clock signal to the gate drive circuit at the 4K+2nd floor, the first clock line transmits the corresponding second clock signal to the gate drive circuit at the 4K+3rd floor, and the second clock line transmits the corresponding second clock signal to the gate drive circuit at the 4K+4th floor. The display device according to feature 7.

9. Each of the multiple gate drive circuits includes a node control module, a first output module, and a first frequency division module. The node control module is electrically connected to the first node and the second node of the gate drive circuit on that floor, and is configured to control the signals transmitted to the first node and the second node based on the corresponding first clock signal and the activation signal. The first output module is electrically connected to the first node and configured to output the first gate control signal based on the corresponding frequency division control signal and the signal of the first node. The first frequency division module is electrically connected to the first node, the second node, and the first output module, and is configured to control signal transmission between the first node and the first output module based on the corresponding frequency division control signal and the signal of the second node. The display device according to feature 5.

10. At least one of the gate drive circuits includes a second output module, The second output module is electrically connected to the first node and the second node and is configured to output the corresponding second clock signal and the second gate control signal based on the signals of the first node and the second node. The display device according to feature 9.

11. Multiple frequency division control lines are configured to transmit the frequency division control signals to multiple gate drive circuits such that they control the level of at least one of the multiple second gate control signals. At least one of the gate drive circuits includes a second frequency division module, The second frequency division module is electrically connected to the first node, the second node, and the second output module, and is configured to control signal transmission between the first node and the corresponding second output module based on the corresponding frequency division control signal and the signal of the second node. The display device according to feature 10.

12. The plurality of frequency division control lines include a first frequency division control line and a second frequency division control line, The first frequency division control line is electrically connected to the first frequency division module of the gate drive circuit on multiple floors, and the second frequency division control line is electrically connected to the second frequency division module of the gate drive circuit on multiple floors. The display device according to feature 11.

13. The node control module includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The control terminal of the first transistor is configured to receive the corresponding startup signal, and the input terminal of the first transistor is electrically connected to the first power supply terminal. The control terminal of the second transistor is electrically connected to the control terminal of the first transistor, the input terminal of the second transistor is electrically connected to the second power supply terminal, and the output terminal of the second transistor is electrically connected to the output terminal of the first transistor. The control terminal of the third transistor is configured to receive the corresponding first clock signal, the input terminal of the third transistor is electrically connected to the output terminal of the first transistor, and the output terminal of the third transistor is electrically connected to the first node. The control terminal of the fourth transistor is electrically connected to the first node, the input terminal of the fourth transistor is electrically connected to the third power supply terminal, and the output terminal of the fourth transistor is electrically connected to the second node. The control terminal of the fifth transistor is electrically connected to the first node, the input terminal of the fifth transistor is electrically connected to the second power supply terminal, and the output terminal of the fifth transistor is electrically connected to the second node. The display device according to feature 9.

14. The first frequency division module includes a first frequency division transistor, a second frequency division transistor, and a first capacitor. The control terminal of the first frequency division transistor is electrically connected to the second node, and the input terminal of the first frequency division transistor is configured to receive the corresponding frequency division control signal. The control terminal of the second frequency division transistor is electrically connected to the output terminal of the first frequency division transistor, the input terminal of the second frequency division transistor is electrically connected to the first node, and the output terminal of the second frequency division transistor is electrically connected to the first output module through the third node. The first terminal of the first capacitor is electrically connected to the control terminal of the second frequency division transistor, and the second terminal of the first capacitor is electrically connected to the third node. The display device according to feature 9.

15. The first output module includes a first output transistor and a second output transistor, The control terminal of the first output transistor is electrically connected to the third node, and the input terminal of the first output transistor is electrically connected to the fourth power supply terminal. The control terminal of the second output transistor is electrically connected to the first node, the input terminal of the second output transistor is electrically connected to the first power supply terminal, and the output terminal of the second output transistor and the output terminal of the first output transistor are electrically connected to the first output terminal of the gate drive circuit of that floor. The display device according to feature 14.

16. The second output module includes a third output transistor, a fourth output transistor, and a second capacitor. The control terminal of the third output transistor is electrically connected to the first node, and the input terminal of the third output transistor is configured to receive the corresponding second clock signal. The control terminal of the fourth output transistor is electrically connected to the second node, the input terminal of the fourth output transistor is electrically connected to the second power supply terminal, and the output terminal of the fourth output transistor and the output terminal of the third output transistor are electrically connected to the second output terminal of the gate drive circuit of that floor. The first terminal of the second capacitor is electrically connected to the control terminal of the third output transistor, and the second terminal of the second capacitor is electrically connected to the second output terminal of the gate drive circuit of that floor. The display device according to feature 10.

17. The second output module of at least one of the gate drive circuits includes a third switch transistor, The control terminal of the third switch transistor is configured to receive a switch control signal, the input terminal of the third switch transistor is electrically connected to the first node, and the output terminal of the third switch transistor is electrically connected to the control terminal of the third output transistor. The display device according to feature 16.

18. The second frequency division module includes a third frequency division transistor, a fourth frequency division transistor, and a third capacitor. The control terminal of the third frequency division transistor is electrically connected to the second node, and the input terminal of the third frequency division transistor is configured to receive the corresponding frequency division control signal. The control terminal of the fourth frequency division transistor is electrically connected to the output terminal of the third frequency division transistor, the input terminal of the fourth frequency division transistor is electrically connected to the first node, and the output terminal of the fourth frequency division transistor is electrically connected to the second output module. The first terminal of the third capacitor is electrically connected to the control terminal of the fourth frequency division transistor, and the second terminal of the third capacitor is electrically connected to the output terminal of the fourth frequency division transistor. The display device according to feature 11.

19. At least one of the subpixels includes a reset transistor, the input terminal of the reset transistor is electrically connected to a reset line, and the output terminal of the reset transistor is electrically connected to the control terminal of the drive transistor. In the same subpixel, the effective level of the first gate control signal received by the control terminal of the compensation transistor and the effective level of the third gate control signal received by the control terminal of the reset transistor partially overlap. The display device according to feature 1.

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