Display boards and display devices

Abstract

A display substrate and a display device, wherein the display substrate includes a display area and a bezel area located around the display area, the display area includes a plurality of subpixels installed on a base, the subpixels include light-emitting elements, the light-emitting elements include a first electrode, a light-emitting functional layer, and a second electrode layer sequentially stacked along a direction away from the base, at least one heat dissipation structure is installed in the bezel area, the heat dissipation structure includes a first heat dissipation groove, and a first heat dissipation metal layer and a second heat dissipation metal layer installed within the first heat dissipation groove, the second heat dissipation metal layer is stacked on the side of the first heat dissipation metal layer away from the base, and the second heat dissipation metal layer is installed on the same layer as the second electrode layer.

Description

Technical Field

[0001] This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on April 28, 2023, with an application number of 202310485396.2 and an invention title of "Display Substrate and Display Device", and its content should be understood to be incorporated herein by reference.

[0002] The embodiments of the present disclosure relate to the field of display technology, but are not limited thereto. Specifically, they relate to display substrates and display devices.

Background Art

[0003] Currently, in the field of display technology, the Gate Driver on Array (GOA) technology is widely applied because it can simplify the process and reduce costs. The GOA technology integrates a gate drive circuit including a plurality of thin film transistors (TFTs) on the array substrate to form a scanning drive for sub-pixels. Since the channel width aspect ratio of the output transistor in the gate drive circuit is generally large, the output transistor generates a large amount of heat during operation. When this heat is dissipated, the threshold voltage of the thin film transistor in the pixel drive circuit of the sub-pixels around the display area drifts negatively, and as a result, the sub-pixels around the display area become brighter, affecting the display effect.

Summary of the Invention

[0004] The following is an overview of the subject matter to be described in detail in the text. This overview is not intended to limit the scope of protection of the claims.

[0005] Embodiments of the present disclosure provide a display substrate comprising a display area and a bezel area located around the display area, wherein the display area comprises a plurality of subpixels installed on a base, the subpixels comprising light-emitting elements, the light-emitting elements comprising a first electrode, a light-emitting functional layer, and a second electrode layer sequentially stacked along a direction away from the base, and at least one heat dissipation structure provided in the bezel area, the heat dissipation structure comprising a first heat dissipation groove and a first heat dissipation metal layer and a second heat dissipation metal layer installed within the first heat dissipation groove, the second heat dissipation metal layer being stacked on the side of the first heat dissipation metal layer away from the base, and the second heat dissipation metal layer being installed on the same layer as the second electrode layer.

[0006] The embodiments of this disclosure further provide a display device including the display substrate.

[0007] After reading and understanding the drawings and detailed explanations, other aspects can also be understood. [Brief explanation of the drawing]

[0008] The drawings are intended to provide a better understanding of the technical proposal of this disclosure and constitute part of the specification, and are used in conjunction with the embodiments of this disclosure to interpret the technical proposal of this disclosure, and are not intended to limit the technical proposal of this disclosure. The shapes and sizes of the parts in the drawings are for illustrative purposes only and do not reflect actual proportions. [Figure 1] This is a schematic diagram of the planar structure of a display board according to several exemplary embodiments. [Figure 2] This is a schematic diagram of a partial planar structure of a display board according to several exemplary embodiments. [Figure 3] These are equivalent circuit diagrams of pixel driving circuits according to several exemplary embodiments. [Figure 4] This is a schematic diagram of a partial cross-sectional structure of a display substrate according to several exemplary embodiments. [Figure 5] This is a schematic diagram of a partial cross-sectional structure of a display board relating to several other exemplary embodiments. [Figure 6]These are schematic diagrams of partial cross-sectional structures of a display substrate according to several further exemplary embodiments. [Figure 7] These are schematic diagrams of partial cross-sectional structures of a display substrate according to several further exemplary embodiments. [Figure 8] These are schematic diagrams of partial cross-sectional structures of a display substrate according to several further exemplary embodiments. [Figure 9] These are schematic diagrams of partial cross-sectional structures of a display substrate according to several further exemplary embodiments. [Figure 10] This is a schematic diagram of a partial planar structure of a display board according to several other exemplary embodiments. [Figure 11] This is a schematic diagram of a partial planar structure of a display board according to several further exemplary embodiments. [Figure 12] This is a schematic diagram of a partial planar structure of a display board according to several further exemplary embodiments. [Figure 13] This is a schematic diagram of a partial planar structure of a display board according to several exemplary embodiments. [Figure 14] This is a schematic diagram of a partial planar structure of a display board according to several exemplary embodiments. [Explanation of symbols]

[0009] 10, Base, 20, Drive structure layer, 21, Buffer layer, 22, Gate insulating layer, 23, Interlayer insulating layer, 24, Passivation layer, 25, Flat layer, 30, Light-emitting structure layer, 31, First electrode, 32, Pixel definition layer, 33, Organic light-emitting layer, 34, Second electrode layer, 41, Black matrix, 42, Color filter layer, 70, Heat-insulating groove, 71, Second signal line, 80, Heat dissipation structure, 81, First heat-dissipating metal layer, 82, Second heat-dissipating metal layer, 83, Third heat-dissipating metal layer, 84, Fourth heat-dissipating metal layer, 85, Filling layer, 87, First heat-dissipating groove, 88, Second heat-dissipating groove, 100, display area, 200, bezel area, 210, transistor, 211, active layer, 212, gate electrode, 213, source electrode, 214, drain electrode, 220, gate drive circuit, 221, gate drive unit, 231, light shielding block, 232, data line, 240, gate connection line, 241, first connection line, 242, second connection line, 243, via, 421, filter unit T, 801, First heat dissipation structure, 802, Second heat dissipation structure, 803, Third heat dissipation structure, 804, Fourth heat dissipation structure, 805, Fifth heat dissipation structure, 806, Sixth heat dissipation structure, 807, Seventh heat dissipation structure, 808, Eighth heat dissipation structure, 809, Ninth heat dissipation structure, 831, First sub-heat dissipation metal layer, 832, Second sub-heat dissipation metal layer, 851, First sub-filled layer, 852, Second sub-filled layer, 853, Third sub-filled layer, 2211, input module; 2212, output transistor; 2213, output capacitor; 2214, pull-down transistor; 2402, second gate connection line; 2403, third gate connection line. [Modes for carrying out the invention]

[0010] Those skilled in the art should understand that they may modify or change to an equivalent degree the technical inventions of the embodiments of this disclosure without departing from the gist and scope of the technical inventions of this disclosure, and that all such modifications should fall within the scope of the patent protection of this disclosure.

[0011] In the drawings, the size of components, layer thickness, or area may be exaggerated for clarity. Therefore, embodiments of this disclosure are not necessarily limited to these sizes, and the shapes and sizes of components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate several examples, and embodiments of this disclosure are not limited to the shapes, numerical values, etc., shown in the drawings.

[0012] In the text, "parallel" refers to a state where the angle between two straight lines is -10° or greater and 10° or less, and therefore also includes a state where the angle is -5° or greater and 5° or less. Also, "perpendicular" refers to a state where the angle between two straight lines is 80° or greater and 100° or less, and therefore also includes a state where the angle is 85° or greater and 95° or less.

[0013] In this text, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positions of components with reference to the drawings. This is for the purpose of explaining and simplifying this specification, and does not indicate or imply that the devices or elements to be described must have a specific orientation and must be configured and operated in a specific orientation. Therefore, it cannot be understood as a limitation to the present disclosure. The positional relationship of the components should be appropriately changed according to the direction of each component to be described. Therefore, it is not limited to the terms described in the specification and can be appropriately changed in some cases.

[0014] In the description of this text, unless there are other clear regulations and limitations, terms such as "connection", "direct connection", "indirect connection", "fixed connection", "attachment", "assembly" should be understood in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integrated connection. The terms "attachment", "connection", "fixed connection" may be a direct connection, or an indirect connection through an intermediate medium, or may be in communication within two elements. Those skilled in the art can understand the meaning of the above terms in the embodiments of the present disclosure according to the situation.

[0015] The ordinal numbers such as "first", "second", "third", etc. in this text are for the purpose of avoiding confusion of components and do not limit in terms of quantity.

[0016] In this text, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region or drain electrode) and the source electrode (source electrode terminal, source region or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this text, the channel region refers to the region where current mainly flows.

[0017] In this text, the first electrode of a transistor may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. When using transistors with opposite polarity, or when the direction of current changes during operation in the circuit, the functions of the "source electrode" and "drain electrode" may be converted to each other. Therefore, in this text, the "source electrode" and "drain electrode" may be converted to each other.

[0018] As shown in Figures 1 and 2, Figure 1 is a schematic diagram of the planar structure of a display substrate according to several exemplary embodiments, and Figure 2 is a schematic diagram of a partial planar structure of a display substrate according to several exemplary embodiments, wherein the display substrate includes a display area 100 and a bezel area 200 located around the display area 100.

[0019] The display area 100 includes a plurality of subpixels arranged in an array on the base, and each subpixel includes a light-emitting element and a pixel driving circuit connected to the light-emitting element. The display area 100 also includes a plurality of gate lines (Figure 2 shows six gate lines G1 to G6) extending along a first direction and a plurality of data lines (not shown) extending along a second direction (vertical direction in the figure), and the pixel driving circuit of each subpixel is electrically connected to the gate lines and data lines.

[0020] The plurality of subpixels may include a plurality of first subpixels P1 that emit light of a first color, a plurality of second subpixels P2 that emit light of a second color, and a plurality of third subpixels P3 that emit light of a third color. For example, the first subpixels P1 may emit red light, the second subpixels P2 may emit green light, and the third subpixels P3 may emit blue light. In some other examples, the plurality of subpixels of the display area 100 may further include a plurality of fourth subpixels P4 that emit light of a fourth color, and the fourth subpixels P4 may emit white light or yellow light, etc. The embodiments of this disclosure do not limit the type or arrangement of the plurality of subpixels of the display area 100.

[0021] The light-emitting element may be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LEDs or micro-LEDs). For example, the light-emitting element may be an OLED, and the OLED light-emitting element may consist of a stacked anode, a light-emitting functional layer, and a cathode, and the anode of the light-emitting element may be electrically connected to the corresponding pixel driving circuit.

[0022] The pixel driving circuit may include a plurality of transistors and at least one memory capacitor. For example, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure, where T refers to a thin-film transistor and C refers to a memory capacitor. The embodiments of this disclosure do not limit the structure of the pixel driving circuit. Exemplarily, as shown in Figure 3, Figure 3 is an equivalent circuit diagram of a pixel driving circuit according to several exemplary embodiments, where the pixel driving circuit may have a 3T1C structure, and the pixel driving circuit comprises a first transistor T1, a second transistor T2, a third transistor T3, and a memory capacitor C STThis includes the following. The light-emitting element may be an OLED light-emitting element. The pixel driving circuit is connected to the data signal line Dn of the display area, the first scan signal line Gn, the second scan signal line Sn, the compensation signal line Se, the first power line VDD, and the second power line VSS. The data signal line Dn is, in other words, a data line, and the first scan signal line Gn and the second scan signal line Sn may be the same gate line, or they may be two different gate lines. The first scan signal line Gn and the second scan signal line Sn may extend along the first direction, and the data signal line Dn, the compensation signal line Se, the first power line VDD, and the second power line VSS may all extend along the second direction. The first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor. The gate electrode of the first transistor T1 is connected to the first scan line Gn, the first electrode of the first transistor T1 is connected to the data line Dn, and the second electrode of the first transistor T1 is connected to the gate electrode of the second transistor T2. The first transistor T1 receives a data signal transmitted from the data line Dn under the control of the first scan line Gn, and the gate electrode of the second transistor T2 receives the data signal. The gate electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is connected to the first power line VDD, and the second electrode of the second transistor T2 is connected to the first electrode (anode) of the OLED. The second transistor T2 is used to generate a current corresponding to the second electrode under the control of the data signal received at its gate electrode. The gate electrode of the third transistor T3 is connected to the second scan line Sn, the first electrode of the third transistor T3 is connected to the compensation signal line Se, and the second electrode of the third transistor T3 is connected to the second electrode of the second transistor T2. The third transistor T3 is used to compensate the threshold voltage Vth by extracting the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing. The first electrode of the OLED is connected to the second electrode of the second transistor T2, and the second electrode (cathode) of the OLED is connected to the second power line VSS. The OLED is used to emit light of a corresponding brightness in accordance with the current of the second electrode of the second transistor T2. Memory capacitor C STThe first electrode is connected to the gate electrode of the second transistor T2, and the memory capacitor C ST The second electrode of is connected to the second electrode of the second transistor T2, and the memory capacitor C ST This is used to store the potential of the gate electrode of the second transistor T2. The signal on the first power line VDD is a continuously supplied high-level signal, and the signal on the second power line VSS is a low-level signal. The maximum voltage of the data signal transmitted by the data line Dn may be less than the maximum voltage of the first scan line Gn and may be less than the voltage of the first power line VDD. The first to third transistors T1 to T3 may be P-type transistors or N-type transistors.

[0023] The bezel region 200 includes a first bezel region and a second bezel region located on opposite sides of the display region 100, and a gate drive circuit 220 is installed in the first bezel region and / or the second bezel region, and the gate drive circuit 220 includes a plurality of cascaded gate drive units 221 (which may be called GOA units) configured to supply drive signals to a plurality of gate lines. Each gate drive unit 221 may be connected to one or more gate lines. The gate drive unit 221 may include a plurality of transistors and at least one memory capacitor, and the configuration of the gate drive unit 221 is not limited in the embodiments of this disclosure.

[0024] A gate connection line 240 is further provided in the bezel area 200, and the gate line of the display area 100 is connected to the gate drive unit 221 via the gate connection line 240. The gate connection line 240 includes a first connection line 241 and a second connection line 242 connected via via 243, the first connection line 241 being connected integrally with the gate line, and the second connection line 242 being connected to the gate drive unit 221. The direction in which the first connection line 241 extends may be the same as the direction in which the gate line extends, or the first connection line 241 may include a first line segment and a second line segment to be connected, the direction in which the first line segment extends may be the same as the direction in which the gate line extends, and the direction in which the second line segment extends may be perpendicular to the direction in which the gate line extends.

[0025] One or more heat dissipation structures 80 are further installed in the bezel region 200, and exemplary, the orthographic projection of at least one of the heat dissipation structures 80 on the base 10 may be located between the display region 100 and the orthographic projection of the gate drive circuit 220 on the base 10, that is, in a direction parallel to the base 10, at least one of the heat dissipation structures 80 may be located between the display region 100 and the gate drive circuit 220. This allows the heat generated by the gate drive unit 221 to be conducted through the heat dissipation structure, reducing heat conduction to the display region 100, thereby reducing the effect of heat generated by the gate drive unit 221 (output transistor) on the subpixels at the edges of the display region 100, and further improving the problem of display abnormalities (peripheral subpixels becoming brighter) caused by the heat generated by the gate drive unit 221 on the subpixels around the display region 100.

[0026] In some exemplary embodiments, as shown in Figure 2, the multiple heat dissipation structures 80 may include one or more of at least one first heat dissipation structure 801, at least one second heat dissipation structure 802, at least one third heat dissipation structure 803, and at least one fourth heat dissipation structure 804.

[0027] Each gate drive unit 221 may be connected to N gate lines, where N may be an integer greater than 1, for example, N may be 4, 5, or 6 (in the example in Figure 2, N is 4). The length of the first heat dissipation structure 801 along the second direction (the direction parallel to the data lines, i.e., the vertical direction in the figure) is L1, the length of the second heat dissipation structure 802 along the second direction is L2, and the length of the third heat dissipation structure 803 along the second direction is L3, which may be set as follows.

[0028] N*L1 > L3 ≥ (N-1)*L1, for example, 3*L1 is approximately equal to L3, and L3 may be approximately 600 μm, or / and N*L2 > L1 ≥ (N / 2)*L2.

[0029] In this text, the length along a certain direction of the heat dissipation structure refers to the length along the direction of the first heat dissipation groove (described later) of the heat dissipation structure.

[0030] In some exemplary embodiments, as shown in Figure 2, the distance between the second heat dissipation structure 802 and the gate drive unit 221 in a direction parallel to the base 10 may be smaller than the distance between the second heat dissipation structure 802 and the display area 100. Positioning the second heat dissipation structure 802 closer to the gate drive unit 221 is advantageous for conducting heat from the output transistors of the gate drive unit 221.

[0031] In some exemplary embodiments, as shown in Figure 2, the display area 100 includes at least one reference subpixel, the size of the effective light-emitting region of the reference subpixel (i.e., the region limited by the pixel aperture of the subpixel) in a second direction is a, and the distance between the effective light-emitting region of a subpixel adjacent to the reference subpixel in the second direction and the effective light-emitting region of the reference subpixel is b, and a+b≧L1>a may be set.

[0032] In some exemplary embodiments, as shown in Figure 2, a second signal line extending in a second direction is provided within the bezel region 200 between the display region 100 and the gate drive circuit 220, and the second signal line is provided close to the edge of the display region 100. Exemplarily, the second signal line may be a frame start signal line STV, a third power line VGH, a second power line VSS (connected to the second electrode layer), etc.

[0033] In a direction parallel to the base 10, the multiple heat dissipation structures may be located between the second signal line and the gate drive circuit 220, and there is a relief of the second signal line (the second signal line is relatively less affected by changes in thermal resistance and has less interference to the signal) between the display area 100 and the gate drive circuit 220, which is advantageous in mitigating the conduction of heat from the gate drive unit 221 to the display area 100.

[0034] In some exemplary embodiments, as shown in Figure 2, the multiple first heat dissipation structures 801 may be installed close to the edges of the display area 100, or they may be installed between multiple gate connection lines 240. The multiple first heat dissipation structures 801 are uniformly installed in the second direction, which is advantageous for uniform heat conduction to the subpixels of each row.

[0035] The orthographic projections of the multiple second heat dissipation structures 802 on the base 10 are located between the orthographic projections of the multiple first heat dissipation structures 801 on the base 10 and the orthographic projection of the gate drive circuit 220 on the base 10.

[0036] The orthographic projection of at least one third heat dissipation structure 803 on the base 10 lies between the orthographic projections of the plurality of first heat dissipation structures 801 on the base 10 and the orthographic projection of the gate drive circuit 220 on the base 10.

[0037] The fourth heat dissipation structure 804 may be installed between two adjacent gate drive units 221. In some exemplary embodiments, as shown in Figure 4, Figure 4 is a schematic diagram of a partial cross-sectional structure of a display substrate according to some exemplary embodiments, and in a direction perpendicular to the base 10, the display area 100 includes a drive structure layer 20 and a light-emitting structure layer 30 that are sequentially stacked on the base 10.

[0038] The drive structure layer 20 includes a plurality of pixel drive circuits, each of which includes a plurality of transistors 210 and at least one memory capacitor. Exemplarily, in a direction perpendicular to the base 10, the drive structure layer 20 includes a first metal layer, a buffer layer 21, a semiconductor layer, a gate insulating layer 22, a second metal layer, a passivation layer 24, and a planar layer 25, which are sequentially installed on the base 10. The first metal layer may include data lines 232 and a light-shielding block 231 (the light-shielding block 231 shields the active layer 211 of the transistor 210, preventing external light from irradiating the active layer 211 and affecting the performance of the transistor 210), and the semiconductor layer is a transistor The second metal layer may include an active layer 211 of transistor 210, and may include a gate electrode 212, a source electrode 213, and a drain electrode 214 of transistor 210. The source electrode 213 is connected to one end of the active layer 211 via a first via placed in the gate insulating layer 22, and the source electrode 213 is further connected to a data line 232 via a second via that penetrates the gate insulating layer 22 and the buffer layer 21. The drain electrode 214 is connected to the other end of the active layer 211 via a third via placed in the gate insulating layer 22. A fourth via is placed in the flat layer 25, and the fourth via penetrates the passivation layer 24 to expose the drain electrode 214. The fourth via is configured such that a subsequently formed first electrode 31 is connected to the drain electrode 214 via the fourth via.

[0039] The base 10 may be a flexible base or a rigid base. The rigid base may be one or more types of glass or quartz, but is not limited to these. The flexible base may be one or more types of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, or woven fibers. The buffer layer 21, gate insulating layer 22, and passivation layer 24 may be inorganic insulating layers, such as silicon oxide (SiO2). X ), silicon nitride (SiN X ) and silicon oxide nitride (SiO X N Y) may be one or more of the above, and may be a single-layer structure or a multilayer composite structure. The flat layer 25 may be an organic insulating layer, or a resin material may be used. The material of the first metal layer and the second metal layer may be one or more of the following: silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), or the alloy material of the above metals may be, for example, an aluminum neodymium alloy (AlNd) or a molybdenum niobium alloy (MoNb), and may be a single-layer structure or a multilayer composite structure such as Mo / Cu / Mo.

[0040] The light-emitting structural layer 30 includes a plurality of light-emitting elements, each of which is connected to a corresponding pixel driving circuit. Exemplarily, in a direction perpendicular to the base 10, the light-emitting structural layer 30 may include a first electrode layer, a pixel definition layer 32, a light-emitting functional layer, and a second electrode layer 34, which are sequentially installed. The first electrode layer includes a plurality of first electrodes 31, the pixel definition layer is installed on the side of the plurality of first electrodes 31 away from the base 10, and has a plurality of pixel apertures, which expose the first electrodes 31, and the light-emitting functional layer and the second electrode layer 34 are sequentially stacked on the side of the first electrodes 31 away from the base 10. The first electrode 31, the light-emitting functional layer, and the second electrode layer 34 form a light-emitting element. The light-emitting functional layer includes an organic light-emitting layer 33 and may further include one or more film layers of any one of a hole injection layer, a hole transport layer, and an electron blocking layer located between the first electrode 31 and the organic light-emitting layer 33, and one or more film layers of any one of a hole injection layer, an electron transport layer, and a hole blocking layer located between the second electrode layer 34 and the organic light-emitting layer 33. The plurality of subpixels include a plurality of subpixels of a plurality of types, each subpixel emitting light of a set color (a plurality of subpixels emitting light of the same color are of the same type), and the organic light-emitting layer 33 of each subpixel may be configured to emit light of a set color under the action of the voltage between the first electrode 31 and the second electrode layer 34. For example, the organic light-emitting layer 33 of the light-emitting element of the first subpixel P1 can emit light of a first color (e.g., red) under the action of the voltage between the first electrode 31 and the second electrode layer 34. The organic light-emitting layer 33 of the light-emitting element of the second subpixel P2 can emit light of a second color (e.g., green) under the action of the voltage between the first electrode 31 and the second electrode layer 34. The organic light-emitting layer 33 of the light-emitting element of the third subpixel P3 can emit light of a third color (e.g., blue) under the action of the voltage between the first electrode 31 and the second electrode layer 34.

[0041] For example, the material of the first electrode 31 includes a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the first electrode 31 may have a single-layer structure or a multilayer composite structure such as ITO / Ag / ITO. The material of the pixel definition layer 32 may be polyimide, acrylic, polyethylene terephthalate, etc. The material of the second electrode layer 34 may be one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy consisting of multiple of the above metal layers may be used.

[0042] At least one heat dissipation structure 80 is provided in the bezel region 200, and the heat dissipation structure 80 includes a first heat dissipation groove 87, and a first heat dissipation metal layer 81 and a second heat dissipation metal layer 82 provided within the first heat dissipation groove 87, wherein the second heat dissipation metal layer 82 is laminated on the side of the first heat dissipation metal layer 81 away from the base 10, and the second heat dissipation metal layer 82 is provided on the same layer as the second electrode layer 34. The second heat dissipation metal layer 82 does not have to be connected to the second electrode layer 34, or the second heat dissipation metal layer 82 and the second electrode layer 34 may be an integrated connection structure.

[0043] In the embodiments of this disclosure, by providing the heat dissipation structure 80, heat generated from the electronic components in the bezel region 200 can be dissipated, heat conduction to the display region 100 can be reduced, and the problem of display abnormalities caused by the subpixels around the display region 100 being affected by the heat of the bezel region 200 can be reduced. In some embodiments, the heat dissipation structure 80 may be installed between the display region 100 and the gate drive circuit 220. In this way, when the heat generated by the gate drive unit 221 is conducted to the first heat dissipation groove 87, it is conducted to the second heat dissipation metal layer 82 via the first heat dissipation metal layer 81, and then conducted from the second heat dissipation metal layer 82, thereby reducing heat conduction to the display region 100. This reduces the effect of the heat generated by the gate drive unit 221 on the subpixels around the display region 100, and further improves the problem of display abnormalities (peripheral subpixels becoming brighter) caused by the heat generated by the gate drive unit 221 on the subpixels around the display region 100.

[0044] In this text, "A and B are placed in the same layer" may be understood as simultaneously forming A and B in the same patterning process on the same thin film, or simultaneously forming A' and B' in the same patterning process on the same thin film, obtaining A after further processing (e.g., etching) on ​​A', and obtaining B after further processing (e.g., etching) on ​​B'.

[0045] In some exemplary embodiments, as shown in Figure 4, the first heat dissipation metal layer 81 may be installed on the same layer as the first electrode 31.

[0046] In some exemplary embodiments, as shown in Figure 4, the orthographic projection of the first heat dissipation metal layer 81 on the base 10 may include the orthographic projection of the first heat dissipation groove 87 on the base 10. In this way, the effect of heat conduction can be improved.

[0047] The size of the first heat dissipation metal layer 81 in the direction parallel to the base 10 should not be too small, but should be large enough to cover the first heat dissipation groove 87, and should not be too large, as this would easily cause a short circuit with the gate drive circuit 220 or the second signal line.

[0048] In some exemplary embodiments, as shown in Figure 4, the heat dissipation structure 80 may include a third heat dissipation metal layer 83, the first heat dissipation groove 87 exposing at least a portion of the surface of the third heat dissipation metal layer 83 away from the base 10, and the first heat dissipation metal layer 81 is laminated on the surface of the third heat dissipation metal layer 83 away from the base 10.

[0049] Exemplary, as shown in Figure 4, the third heat dissipation metal layer 83 may be a single heat dissipation metal layer, or it may be installed on the same layer as any one of the metal layers or conductive structures (e.g., metal electrodes, metal signal lines, etc.) in the drive structure layer 20. For example, the third heat dissipation metal layer 83 may be installed on the same layer as the gate electrode 212, the source electrode 213, and the drain electrode 214 (the second metal layer). Alternatively, the third heat dissipation metal layer 83 may be installed on the same layer as the data line 232 and the light shielding block 231 (the first metal layer).

[0050] In some exemplary embodiments, as shown in Figure 4, the first heat dissipation groove 87 includes a first recess and a second recess located at the bottom of the first recess, wherein the orthographic projection of the first recess on the base 10 is larger than the orthographic projection of the second recess on the base 10, and a stepped surface is formed between the side surface of the first recess and the side surface of the second recess. In this embodiment, the first and second recesses may be formed by different patterning processes via different masks.

[0051] The included angle of the side surface of the first concave groove is β, the included angle of the side surface of the second concave groove is α, the length of the first concave groove in the third direction is d2, the length of the second concave groove in the third direction is d1, the depth of the first concave groove in the direction perpendicular to the base 10 is h2, the depth of the second concave groove in the direction perpendicular to the base 10 is h1, the length of the first heat dissipation metal layer 81 in the third direction is S, d1 < d2, and it may be set as follows.

[0052] d1 ≤ S ≤ 1.4 * d2, or d1 + (h1 / tanα + h2 / tanβ) ≤ S ≤ 1.4 * d2.

[0053] In this text, the third direction is a direction parallel to the base. For example, the third direction may be the first direction (the direction parallel to the gate line), or the second direction (the direction parallel to the data line), or other directions.

[0054] In an example of this embodiment, the length of the third heat dissipation metal layer 83 in the third direction is d3, and it may be set that d1 < d3 < d2, or d1 ≤ d3 ≤ d1 + (h1 / tanα + h2 / tanβ) ≤ S. In this way, the step of the first heat dissipation metal layer 81 can be increased, the first heat dissipation metal layer 81 and the second heat dissipation metal layer 82 can be made to contact better, and the heat dissipation effect can be improved.

[0055] In an example of this embodiment, β > α, for example, it may be set that β = 2α.

[0056] In some exemplary embodiments, as shown in FIG. 4, the bezel region 200 includes a composite insulating layer installed on the base 10, the composite insulating layer may include at least one organic insulating layer and at least one inorganic insulating layer, and the first heat dissipation groove 87 is installed through the composite insulating layer.

[0057] In some examples of this embodiment, as shown in Figure 4, the bezel region 200 includes a buffer layer 21, a gate insulating layer 22, a third heat dissipation metal layer 83, a passivation layer 24 (inorganic insulating layer), and a flat layer 25 (organic insulating layer) which are sequentially stacked on the base 10 in a direction perpendicular to the base 10, the first heat dissipation groove 87 is installed through the flat layer 25 and the passivation layer 24, exposing at least a portion of the surface of the third heat dissipation metal layer 83, the first heat dissipation metal layer 81 is installed on the side of the flat layer 25 away from the base 10 and is installed within the first heat dissipation groove 87 and may also be connected to the third heat dissipation metal layer 83, and the second heat dissipation metal layer 82 is installed on the surface of the first heat dissipation metal layer 81 away from the base 10 and is at least partially located within the first heat dissipation groove 87. For example, the first groove is provided in the flat layer 25, and the second groove is provided in the passivation layer 24.

[0058] For example, the thickness of the passivation layer 24 may be approximately 3700 Å, the thickness of the second metal layer on which the gate electrode 212, the source electrode 213, and the drain electrode 214 are located may be approximately 5100 Å, the total thickness of the passivation layer 24, the gate insulating layer 22, and the buffer layer 21 may be approximately 8900 Å, and the thickness of the first metal layer on which the data line 232 and the light shielding block 231 are located may be approximately 6300 Å. When the third heat dissipation metal layer 83 is installed on the same layer as the gate electrode 212, the source electrode 213, and the drain electrode 214 (second metal layer), the heat from the passivation layer 24 can be efficiently conducted from the heat dissipation structure 80. When the third heat dissipation metal layer 83 is installed on the same layer as the data line 232 and the light shielding block 231 (first metal layer), it can efficiently conduct heat from the passivation layer 24, the gate insulation layer 22, and the buffer layer 21 through the heat dissipation structure 80.

[0059] In some exemplary embodiments, as shown in Figure 4, an insulating groove 70 may be provided in the bezel region 200, and the orthographic projection of the insulating groove 70 on the base 10 is located between the display region 100 and the orthographic projection of the gate drive circuit on the base 10.

[0060] For example, the heat insulation groove 70 may be installed close to the edge of the display area 100, or it may be located on the side of the multiple heat dissipation structures 80 facing the display area 100. The second signal line 71 may be installed within the heat insulation groove 70. For example, the second signal line 71 may be a second power line VSS, which is electrically connected to the second electrode layer 34 and supplies a common voltage VSS signal to the second electrode layer 34. The second signal line 71 may be installed on the same layer as the drain electrode 214.

[0061] In this embodiment, the heat-insulating groove 70 can block the conduction of heat generated by the gate drive circuit 220 to the display area 100, thereby reducing the effect of heat generated by the gate drive circuit 220 on the subpixels surrounding the display area 100.

[0062] In some exemplary embodiments, as shown in Figure 5, which is a schematic diagram of a partial cross-sectional structure of a display substrate according to some other exemplary embodiments, the bezel region 200 is provided with at least one heat dissipation structure 80, the heat dissipation structure 80 includes a first heat dissipation groove 87, and a first heat dissipation metal layer 81 and a second heat dissipation metal layer 82 installed within the first heat dissipation groove 87, the second heat dissipation metal layer 82 being laminated on the side of the first heat dissipation metal layer 81 away from the base 10, and the second heat dissipation metal layer 82 being installed on the same layer as the second electrode layer 34.

[0063] The first heat dissipation groove 87 has an inverted trapezoidal cross-section in a direction perpendicular to the base 10, and the side surface of the first heat dissipation groove 87 is sloped. The first heat dissipation groove 87 may be formed in a single patterning process via a single mask. The slope angle of the side surface of the first heat dissipation groove 87 is θ, the length of the groove opening of the first heat dissipation groove 87 in the third direction is d5, the length of the bottom surface of the first heat dissipation groove 87 in the third direction is d4, and d5 > d4, and the length of the first heat dissipation metal layer 81 in the third direction is S, and d4 ≤ S ≤ 1.4 * d5 may be set.

[0064] In one example of this embodiment, the heat dissipation structure 80 may further include a third heat dissipation metal layer 83, the first heat dissipation groove 87 exposing at least a portion of the surface of the third heat dissipation metal layer 83 away from the base 10, and the first heat dissipation metal layer 81 is laminated on the surface of the third heat dissipation metal layer 83 away from the base 10. The length of the third heat dissipation metal layer 83 in the third direction is d3, and may be set to d4 ≤ d3 ≤ d5 ≤ S. In this way, the step height of the first heat dissipation metal layer 81 can be increased, allowing the first heat dissipation metal layer 81 and the second heat dissipation metal layer 82 to make better contact and improve the heat dissipation effect.

[0065] In some exemplary embodiments, as shown in Figure 6, Figure 6 is a schematic diagram of a partial cross-sectional structure of a display substrate according to some further exemplary embodiments, wherein at least one heat dissipation structure 80 is provided in the bezel region 200, and the heat dissipation structure 80 includes a first heat dissipation groove 87, and a first heat dissipation metal layer 81 and a second heat dissipation metal layer 82 provided within the first heat dissipation groove 87, wherein the second heat dissipation metal layer 82 is laminated on the side of the first heat dissipation metal layer 81 away from the base 10, and the second heat dissipation metal layer 82 is provided on the same layer as the second electrode layer 34. The second heat dissipation metal layer 82 does not have to be connected to the second electrode layer 34, or the second heat dissipation metal layer 82 and the second electrode layer 34 may be an integrated connection structure.

[0066] The heat dissipation structure 80 may further include a third heat dissipation metal layer 83, the first heat dissipation groove 87 exposing at least a portion of the surface of the third heat dissipation metal layer 83 that is away from the base 10, and the first heat dissipation metal layer is laminated on the surface of the third heat dissipation metal layer 83 that is away from the base 10.

[0067] The third heat dissipation metal layer 83 may include a plurality of sub-heat dissipation metal layers that are stacked, and any one of the sub-heat dissipation metal layers may be installed on the same layer as the metal layer or conductive structure (e.g., metal electrodes, metal signal lines, etc.) in the drive structure layer 20.

[0068] Exemplary, as shown in Figure 6, the third heat dissipation metal layer 83 may include a first sub-heat dissipation metal layer 831 and a second sub-heat dissipation metal layer 832 that are sequentially stacked along the direction away from the base 10, with the first heat dissipation metal layer 81 stacked on the surface of the second sub-heat dissipation metal layer 832 that is away from the base 10.

[0069] Exemplary, as shown in Figure 6, the heat dissipation structure 80 may further include a second heat dissipation groove 88, the second heat dissipation groove 88 which at least partially exposes the surface of the first sub-heat dissipation metal layer 831 away from the base 10, and the second sub-heat dissipation metal layer 832 is installed within the second heat dissipation groove 88 and laminated on the surface of the first sub-heat dissipation metal layer 831 away from the base 10.

[0070] The film layer structure of the drive structure layer 20 of the display area 100 in this example may be the same as the film layer structure of the drive structure layer 20 of the display area 100 in the example of Figure 4. In this case, the first sub-heat dissipation metal layer 831 may be installed on the same layer as the data line 232 and the light shielding block 231 (first metal layer), and the second sub-heat dissipation metal layer 832 may be installed on the same layer as the gate electrode 212, the source electrode 213 and the drain electrode 214 (second metal layer). The first heat dissipation metal layer 81 may be installed on the same layer as the first electrode 31.

[0071] Exemplarily, as shown in FIG. 6, in the direction perpendicular to the base 10, the bezel region 200 may include a first sub-heat dissipation metal layer 831, a buffer layer 21, a gate insulating layer 22, a second sub-heat dissipation metal layer 832, a passivation layer 24, and a planarization layer 25 that are sequentially stacked on the base 10. The second heat dissipation groove 88 is installed through the gate insulating layer 22 and the buffer layer 21 to expose at least a part of the surface of the first sub-heat dissipation metal layer 831. The second sub-heat dissipation metal layer 832 is installed on the surface of the gate insulating layer 22 away from the base 10 and is partially installed in the second heat dissipation groove 88 to contact the first sub-heat dissipation metal layer 831. The first heat dissipation groove 87 is installed through the planarization layer 25 and the passivation layer 24 to expose at least a part of the surface of the second sub-heat dissipation metal layer 832. The first heat dissipation metal layer 81 is installed on the side of the planarization layer 25 away from the base 10 and is installed in the first heat dissipation groove 87 to contact the second sub-heat dissipation metal layer 832. The second heat dissipation metal layer 82 is installed on the surface of the first heat dissipation metal layer 81 away from the base 10 and is at least partially located in the first heat dissipation groove 87.

[0072] Exemplarily, as shown in FIG. 6, the first heat dissipation groove 87 includes a first concave groove and a second concave groove installed on the bottom surface of the first concave groove. The orthographic projection of the first concave groove on the base 10 is larger than the orthographic projection of the second concave groove on the base 10, and a stepped surface is formed between the side surface of the first concave groove and the side surface of the second concave groove. In this embodiment, the first concave groove and the second concave groove may be formed by different patterning processes through different masks.

[0073] The length of the first concave groove in the third direction is d2, the length of the second concave groove in the third direction is d1, the length of the first sub-heat dissipation metal layer 831 in the third direction is d6, and the length of the second sub-heat dissipation metal layer 832 in the third direction is d7. It may be set that d1 < d7 < d6 < d2. In this way, the step of the first heat dissipation metal layer 81 can be increased, the first heat dissipation metal layer 81 and the second heat dissipation metal layer 82 can be made to contact better, and the heat dissipation effect can be improved.

[0074] In some exemplary embodiments, as shown in Figure 6, the heat dissipation structure 80 may further include a fourth heat dissipation metal layer 84, which is laminated on the side of the second heat dissipation metal layer 82 away from the base 10. By installing the fourth heat dissipation metal layer 84, heat can be conducted more quickly, improving the heat dissipation effect of the heat dissipation structure 80. Exemplarily, a metal layer may be installed on the side of the second electrode layer 34 of the display area 100 away from the base 10, and this metal layer may be connected to the fourth heat dissipation metal layer 84 to form an integrated structure. Alternatively, the fourth heat dissipation metal layer 84 may be an independently installed metal layer.

[0075] In some exemplary embodiments, as shown in Figure 6, the edge corners of any one of the sub-heat dissipation metal layers among the first heat dissipation metal layer 81, the second heat dissipation metal layer 82, and the third heat dissipation metal layer 83, and any one or more of the heat dissipation metal layers among the fourth heat dissipation metal layer 84, are provided with a chamfered structure. In this way, it is possible to avoid static electricity accumulating due to the corners of the heat dissipation metal layers being too sharp.

[0076] In some exemplary embodiments, as shown in Figure 7, Figure 7 is a schematic diagram of a partial cross-sectional structure of a display substrate according to some further exemplary embodiments, wherein, in a direction perpendicular to the base 10, the display area 100 includes a drive structure layer 20 and a light-emitting structure layer 30 that are sequentially stacked on the base 10.

[0077] The drive structure layer 20 includes a plurality of pixel drive circuits, each of which includes a plurality of transistors 210 and at least one memory capacitor. Exemplarily, in a direction perpendicular to the base 10, the drive structure layer 20 includes a first metal layer, a buffer layer 21, a semiconductor layer, a gate insulating layer 22, a second metal layer, an interlayer insulating layer 23, a third metal layer, a passivation layer 24, and a flat layer 25, which are sequentially installed on the base 10. The first metal layer may include a light-shielding block 231, the semiconductor layer may include the active layer 211 of the transistor 210, the second metal layer may include the gate electrode 212 of the transistor 210, and the third metal layer may include the source electrode 213 and drain electrode 214 of the transistor 210. The source electrode 213 is connected to one end of the active layer 211 via a first via installed in the interlayer insulating layer 23, and the drain electrode 214 is connected to the other end of the active layer 211 via a third via installed in the interlayer insulating layer 23. A fourth via is installed in the flat layer 25, and the fourth via penetrates the passivation layer 24 to expose the drain electrode 214. The fourth via is configured such that the first electrode 31, which is formed subsequently, is connected to the drain electrode 214 via the fourth via.

[0078] The display substrates in the examples shown in Figures 4 to 6 above schematically represent the film layer structure of the drive structure layer 20. In this embodiment, Figure 7 shows another film layer structure of the drive structure layer 20, and the film layer structure of the drive structure layer 20 is not limited in the embodiments of this disclosure.

[0079] As shown in Figure 7, the light-emitting structural layer 30 includes a plurality of light-emitting elements. Exemplarily, in a direction perpendicular to the base 10, the light-emitting structural layer 30 may include a first electrode layer, a pixel definition layer 32, a light-emitting functional layer, and a second electrode layer 34 which are sequentially installed. The first electrode layer includes a plurality of first electrodes 31, the pixel definition layer 32 is installed on the side of the plurality of first electrodes 31 away from the base 10 and has a plurality of pixel apertures installed, the pixel apertures exposing the first electrodes 31, and the light-emitting functional layer and the second electrode layer 34 are sequentially stacked on the side of the first electrodes 31 away from the base 10. The first electrodes 31, the light-emitting functional layer, and the second electrode layer 34 form a light-emitting element.

[0080] In one example of this embodiment, as shown in Figure 7, the heat dissipation structure 80 may include the first heat dissipation metal layer 81, the second heat dissipation metal layer 82, and the third heat dissipation metal layer 83. The first heat dissipation metal layer 81 may be installed on the same layer as the first electrode 31. The third heat dissipation metal layer 83 may be a single heat dissipation metal layer, or it may be installed on the same layer as any one of the conductive structures (e.g., metal electrode, metal signal line, etc.) in the drive structure layer 20. For example, the third heat dissipation metal layer 83 may be installed on the same layer as the source electrode 213 and the drain electrode 214 (the third metal layer), or the third heat dissipation metal layer 83 may be installed on the same layer as the gate electrode 212 (the second metal layer), or the third heat dissipation metal layer 83 may be installed on the same layer as the light shielding block 231 (the first metal layer).

[0081] In some exemplary embodiments, the heat dissipation structure may further include a packing layer installed in the first heat dissipation groove, wherein the packing layer is installed on the side of the second heat dissipation metal layer away from the base, or the packing layer is installed between the first heat dissipation metal layer and the second heat dissipation metal layer. In this embodiment, by installing the packing layer, the heat dissipation structure can be made to maintain as much flatness as possible with respect to the display area.

[0082] In one example of this embodiment, as shown in Figure 8, Figure 8 is a schematic diagram of a partial cross-sectional structure of a display substrate according to several further exemplary embodiments, wherein the heat dissipation structure 80 may further include a packing layer 85 installed in the first heat dissipation groove 87, the packing layer 85 being installed on the side of the second heat dissipation metal layer 82 away from the base 10.

[0083] Exemplary, as shown in Figure 8, the display area 100 may further include a color filter layer 42 and a black matrix 41 installed on the side of the light-emitting structure layer 30 away from the base 10, wherein the black matrix 41 has a plurality of light-transmitting holes, the color filter layer 42 includes a plurality of filter units 421, the plurality of filter units 421 are installed within the plurality of light-transmitting holes, and the filter units 421 are installed facing the pixel aperture area of ​​a subpixel and transmit light of a set color.

[0084] The plurality of filter units 421 may include multiple types of filter units 421 that transmit light of different colors (filter units 421 of the same type transmit light of the same color), and each type of filter unit 421 transmits light of a set color. The color of the light transmitted by the filter unit 421 is the color of the light emitted by the corresponding subpixel. For example, the multiple subpixels of the display area 100 include a plurality of first subpixels P1 that emit light of a first color, a plurality of second subpixels P2 that emit light of a second color, and a plurality of third subpixels P3 that emit light of a third color, and the plurality of filter units 421 include a plurality of first filter units 421 that transmit light of a first color, a plurality of second filter units 421 that transmit light of a second color, and a plurality of third filter units 421 that transmit light of a third color, and the first filter units 421 are installed facing the pixel aperture area of ​​the first subpixel P1, the second filter units 421 are installed facing the pixel aperture area of ​​the second subpixel P2, and the third filter units 421 are installed facing the pixel aperture area of ​​the third subpixel P3.

[0085] The packed layer 85 may be a single film layer, and the packed layer 85 may be installed on the same layer as any one of the multiple types of filter units 421. Alternatively, the packed layer 85 may include multiple subpacked layers, and each subpacked layer may be installed on the same layer as one of the multiple types of filter units 421. The multiple subpacked layers may be stacked in a direction perpendicular to the base 10, or the multiple subpacked layers may be installed at intervals in a direction parallel to the base 10.

[0086] In one example of this embodiment, as shown in Figure 9, Figure 9 is a schematic diagram of a partial cross-sectional structure of a display substrate according to several further exemplary embodiments, wherein the heat dissipation structure 80 may further include a packing layer 85 installed in the first heat dissipation groove 87, and the packing layer 85 may be installed between the first heat dissipation metal layer 81 and the second heat dissipation metal layer 82.

[0087] The plurality of subpixels may include multiple types of subpixels, each type of subpixel emitting light of a set color (multiple subpixels emitting light of the same color are of the same type of subpixel), and the organic light-emitting layer 33 of each type of subpixel may be configured to emit light of a set color under the action of the voltage of the first electrode 31 and the second electrode layer 34. For example, the organic light-emitting layer 33 of the light-emitting element of the first subpixel P1 can emit light of a first color (e.g., red) under the action of the voltage of the first electrode 31 and the second electrode layer 34. The organic light-emitting layer 33 of the light-emitting element of the second subpixel P2 can emit light of a second color (e.g., green) under the action of the voltage of the first electrode 31 and the second electrode layer 34. The organic light-emitting layer 33 of the light-emitting element of the third subpixel P3 can emit light of a third color (e.g., blue) under the action of the voltage of the first electrode 31 and the second electrode layer 34.

[0088] The packing layer 85 may be a single film layer, or it may be installed on the same layer as the organic light-emitting layer 33 of any one type of subpixel, or the packing layer 85 may include a plurality of sub-packing layers, each of which may be installed on the same layer as the organic light-emitting layer 33 of one type of subpixel. The plurality of sub-packing layers may be stacked in a direction perpendicular to the base 10, or the plurality of sub-packing layers may be installed with gaps between them in a direction parallel to the base 10.

[0089] Exemplary, as shown in Figure 9, the packing layer 85 may include a first sub-packing layer 851, a second sub-packing layer 852, and a third sub-packing layer 853 that are spaced apart in a direction parallel to the base 10, the first sub-packing layer 851 may be installed on the same layer as the organic light-emitting layer 33 of the first sub-pixel P1, the second sub-packing layer 852 may be installed on the same layer as the organic light-emitting layer 33 of the second sub-pixel P2, and the third sub-packing layer 853 may be installed on the same layer as the organic light-emitting layer 33 of the third sub-pixel P3.

[0090] In some exemplary embodiments, as shown in Figure 10, which is a schematic diagram of a partial planar structure of a display substrate according to some other exemplary embodiments, one or more heat dissipation structures 80 are installed in the bezel region 200, and the orthographic projection of at least one of the heat dissipation structures 80 on the base 10 is located between the display region 100 and the orthographic projection of the gate drive circuit 220 on the base 10. The multiple heat dissipation structures 80 may include one or more of at least one first heat dissipation structure 801, at least one second heat dissipation structure 802, at least one third heat dissipation structure 803, and at least one fourth heat dissipation structure 804. In this embodiment, the distribution method of the multiple heat dissipation structures 80 may be the same as the distribution method in the example of Figure 2. The multiple first heat dissipation structures 801 may be installed close to the edge of the display region 100.

[0091] In some examples of this embodiment, the cross-sectional shape of the first heat dissipation groove 87 of the heat dissipation structure 80 in the direction parallel to the base 10 may be a regular shape such as a rectangle, trapezoid, circle, or ellipse, or it may be an irregular shape. The cross-sectional shapes of the first heat dissipation groove 87 of different heat dissipation structures in the direction parallel to the base 10 may be the same or different.

[0092] In some examples of this embodiment, the cross-sectional shape of the first heat dissipation groove 87 of the first heat dissipation structure 801 in the direction parallel to the base 10 may be irregular, and the side surface of the first heat dissipation groove 87 of the first heat dissipation structure 801 that is close to the display area 100 may be curved or sloped, thereby increasing the area of ​​the side surface of the first heat dissipation groove 87 of the first heat dissipation structure 801 that is close to the display area 100, and allowing more heat to be conducted to the area close to the display area 100.

[0093] In some examples of this embodiment, the cross-sectional shape of the first heat dissipation groove 87 of at least one heat dissipation structure 80 in a direction parallel to the base 10 may be the same as the shape of any one type of filter unit 421. Thus, it is advantageous to fill the first heat dissipation groove 87 with any one type of filter unit 421 as the packing layer 85.

[0094] In some exemplary embodiments, as shown in Figure 11, Figure 11 is a schematic diagram of a partial planar structure of a display substrate according to some further exemplary embodiments, wherein gate connection lines 240 are provided in the bezel region 200, the gate lines are connected to the gate drive unit 221 via the gate connection lines 240, and the first heat dissipation metal layers 81 of at least two of the heat dissipation structures 80 are connected to form a single structure and overlap with at least two adjacent gate connection lines 240 connected to the same one gate drive unit 221. In other embodiments, the first heat dissipation metal layers 81 of different heat dissipation structures 80 do not need to be connected.

[0095] The first heat dissipation metal layers 81 of at least two of the heat dissipation structures 80 are connected to form a single integrated structure, and the connected, integrated first heat dissipation metal layers 81 can completely cover the first heat dissipation grooves 87 of the at least two of the heat dissipation structures 80. The first heat dissipation grooves 87 do not have to overlap with the gate connection lines 240.

[0096] In this embodiment, the first heat dissipation metal layers 81 of multiple heat dissipation structures 80 corresponding to the same single gate drive unit 221 are connected to form an integrated structure, enabling uniform heat dissipation of the heat generated by the same single gate drive unit 221.

[0097] In this embodiment, if a break occurs in any one of the at least two adjacent gate connection lines 240 connected to the same gate drive unit 221, repair may be performed using the first heat dissipation metal layer 81 which is connected to form an integrated structure. Specifically, the first heat dissipation metal layer 81 which is connected to form an integrated structure is connected to the gate connection line 240 that has broken (e.g., by laser hole repair), and also connected to the gate connection line 240 which has not broken (e.g., by laser hole repair). That is, by connecting the gate connection line 240 that has broken and the gate connection line 240 which has not broken via the first heat dissipation metal layer 81 which is connected to form an integrated structure, the signal from the gate drive unit 221 can be transmitted to the gate line connected to the gate connection line 240 that has broken in the display area 100 via the gate connection line 240 which has not broken, the first heat dissipation metal layer 81 which is integrated structure, and the gate connection line 240 that has broken. Furthermore, in this embodiment, it is advantageous to conduct the heat from the gate connection wire 240 to the first heat dissipation groove 87 via the first heat dissipation metal layer 81 of the integrated structure for heat dissipation.

[0098] For example, the first heat dissipation metal layers 81 of at least two first heat dissipation structures 801 are connected to form a single integrated structure and overlap with the adjacent second gate connection line 2402 (connected to the second gate line G2 of the display area 100) and the third gate connection line 2403 (connected to the third gate line G3 of the display area 100), and both the second gate connection line 2402 and the third gate connection line 2403 are connected to the first gate drive unit 221. In this way, for example, if a break occurs in the second gate connection line 2402, the first heat dissipation metal layers 81, which are connected to form a single integrated structure, can be connected to the second gate connection line 2402 and the third gate connection line 2403, respectively, thereby allowing the signal from the first gate drive unit 221 to be transmitted to the second gate line G2 of the display area 100 via the third gate connection line 2403, the integrated first heat dissipation metal layer 81, and the second gate connection line 2402.

[0099] In some exemplary embodiments, as shown in Figures 2 and 12, Figure 12 is a schematic diagram of a partial planar structure of a display board according to some further exemplary embodiments, wherein a gate drive circuit 220 is installed in the bezel region 200, and the gate drive circuit 220 includes a plurality of cascaded gate drive units 221 configured to supply drive signals to a plurality of gate lines (shown as six lines, G1 to G6), each gate drive unit 221 may be connected to a plurality of gate lines (exemplarily four). Each gate drive unit 221 may include an input module 2211 and a plurality of output modules, each output module may include an output transistor 2212 and an output capacitor 2213, the output transistor 2212 of each output module is connected to a corresponding gate connection line 240, and the gate connection line 240 is connected to a corresponding gate line, i.e., the output transistor 2212 is connected to a corresponding gate line. The multiple output modules of each gate drive unit 221 may be located on the side of the input module 2211 facing the display area 100, and each gate drive unit 221 may be connected to a first clock signal line CA and a second clock signal line CB located on the side of the input module 2211 away from the display area 100.

[0100] Exemplary, the bezel region 200 may be provided with a plurality of heat dissipation structures, which may include at least one first heat dissipation structure 801, at least one second heat dissipation structure 802, at least one third heat dissipation structure 803, at least one fourth heat dissipation structure 804, and at least one fifth heat dissipation structure 805.

[0101] The multiple first heat dissipation structures 801 may be installed close to the edges of the display area 100, or they may be installed uniformly in a second direction. The orthographic projection of the multiple second heat dissipation structures 802 on the base 10 is located between the orthographic projection of the multiple first heat dissipation structures 801 on the base 10 and the orthographic projection of the gate drive circuit 220 on the base 10. The orthographic projection of at least one third heat dissipation structure 803 on the base 10 is located between the orthographic projection of the multiple first heat dissipation structures 801 on the base 10 and the orthographic projection of the gate drive circuit 220 on the base 10. The fourth heat dissipation structure 804 may be installed between two adjacent gate drive units 221, and exemplary, the fourth heat dissipation structure 804 may be installed between the output transistors 2212 of two adjacent gate drive units 221. The fifth heat dissipation structure 805 may be installed between multiple output capacitors 2213 of multiple output modules of the gate drive unit 221.

[0102] The cross-sectional shape of the first heat dissipation groove 87 of the plurality of heat dissipation structures 80 in the direction parallel to the base 10 may be one or more of the following: rectangle, trapezoid, circle, ellipse, etc. In some examples, the cross-sectional shape of the first heat dissipation groove 87 of the first heat dissipation structure 801, the second heat dissipation structure 802, the third heat dissipation structure 803, and the fourth heat dissipation structure 804 in the direction parallel to the base 10 may be rectangular. The cross-sectional shape of the first heat dissipation groove 87 of the fifth heat dissipation structure 805 in the direction parallel to the base 10 may be square, circle, or ellipse.

[0103] In some exemplary embodiments, as shown in Figure 13, which is a schematic diagram of a partial planar structure of a display board according to some exemplary embodiments, the display board includes a display area 100 and a bezel area 200 located around the display area 100, the bezel area 200 is equipped with a gate drive circuit 220, the gate drive circuit 220 includes a plurality of cascaded gate drive units configured to supply drive signals to a plurality of gate lines of the display area 100, and each gate drive unit may be equipped with a plurality of gate drive signal output terminals so as to be connected to the plurality of gate lines. Each gate drive unit may include an input module, a plurality of output modules and a pull-down module, the output module may include an output transistor 2212 and an output capacitor 2213, and the pull-down module includes at least one pull-down transistor 2214.

[0104] The bezel area 200 is provided with a first low-level signal line VGL1, a second low-level signal line VGL2, and a plurality of clock signal lines, etc., extending along a second direction (the vertical direction in the figure). The first low-level signal line VGL1 and the second low-level signal line VGL2 may be located between the gate drive circuit 220 and the display area 100, and the first low-level signal line VGL1 may be installed closer to the gate drive circuit 220 than the second low-level signal line VGL2.

[0105] One gate drive signal output terminal of the gate drive unit may correspond to one output transistor 2212. Exemplarily, the first electrode of the output transistor 2212 is connected to the corresponding clock signal line, and the second electrode of the output transistor 2212 is connected to the corresponding gate drive signal output terminal, and the output transistor 2212 is configured to control the on or off of the electrical connection between the corresponding gate drive signal output terminal and the clock signal line under the control of a signal received by its control terminal.

[0106] One gate drive signal output terminal of the gate drive unit may correspond to at least one pull-down transistor 2214. Exemplarily, the first electrode of the pull-down transistor 2214 is connected to the corresponding gate drive signal output terminal, and the second electrode of the pull-down transistor 2214 is connected to a second low-level signal line VGL2, and the pull-down transistor 2214 is configured to control the on or off of the electrical connection between the corresponding gate drive signal output terminal and the second low-level signal line VGL2 under the control of a signal received at its control terminal.

[0107] A plurality of heat dissipation structures are further installed in the bezel region 200, and the orthographic projection of the heat dissipation structure 80 on the base 10 is located between the display region 100 and the orthographic projection of the gate drive circuit 220 on the base 10. The plurality of heat dissipation structures may include one or more of at least one sixth heat dissipation structure 806, at least one seventh heat dissipation structure 807, and at least one eighth heat dissipation structure 808.

[0108] Exemplary, the multiple heat dissipation structures 80 may include multiple sixth heat dissipation structures 806, which are installed close to the edges of the display area 100 and sequentially in the second direction, and the sixth heat dissipation structures 806 may be installed between adjacent gate connection lines 240.

[0109] The multiple heat dissipation structures 80 may include multiple seventh heat dissipation structures 807, which may be located between the second low-level signal line VGL2 and the multiple sixth heat dissipation structures 806, and which may be installed sequentially in the second direction. The multiple seventh heat dissipation structures 807 may be the same size or different in size. For example, some seventh heat dissipation structures 807 may have a length of approximately 60 μm in the first direction (parallel to the gate line, i.e., the horizontal direction in the figure) and a length of approximately 35 μm in the second direction (parallel to the data line, i.e., the vertical direction in the figure), while some seventh heat dissipation structures 807 may have a length of approximately 65 μm in the first direction and a length of approximately 155 μm in the second direction.

[0110] The multiple heat dissipation structures 80 may include multiple eighth heat dissipation structures 808, which may be located between the first low-level signal line VGL1 and the gate drive circuit 220, which may be installed sequentially in the second direction, which may be installed in close proximity to the output transistor 2212 and the pull-down transistor 2214. The sizes of the multiple eighth heat dissipation structures 808 may be the same or different, and exemplary, some eighth heat dissipation structures 808 may have a length of about 150 μm in the first direction and a length of about 30 μm in the second direction, while some eighth heat dissipation structures 808 may have a length of about 150 μm in the first direction and a length of about 15 μm in the second direction.

[0111] In some exemplary embodiments, as shown in Figure 14, which is a schematic diagram of a partial planar structure of a display board according to some exemplary embodiments, each gate drive unit 221 may be equipped with four output modules, each output module may include an output transistor 2212 and an output capacitor 2213.

[0112] The heat dissipation structure may include at least one ninth heat dissipation structure 809. The orthographic projection of the ninth heat dissipation structure 809 on the base 10 may overlap with the orthographic projection of the output capacitor 2213 on the base 10. The ninth heat dissipation structure 809 may be located on the side of the output capacitor 2213 away from the base 10.

[0113] Alternatively, the orthographic projection of the first heat dissipation groove 87 of the ninth heat dissipation structure 809 on the base 10 may be surrounded by the orthographic projection of the output capacitor 2213 on the base 10. Openings may be provided on the two plates of the output capacitor 2213, and the orthographic projection of these openings on the base 10 may include the orthographic projection of the first heat dissipation groove 87 of the ninth heat dissipation structure 809 on the base 10, and may also include the orthographic projection of the first heat dissipation metal layer 81 of the ninth heat dissipation structure 809 on the base 10.

[0114] The four output capacitors 2213 of each gate drive unit 221 may be arranged in a 2x2 grid and be close to each other, and two of the four output transistors 2212 of each gate drive unit 221 may be located on the side of the four output capacitors 2213 closer to the display area 100, while the remaining two output transistors 2212 may be located on the side of the four output capacitors 2213 further away from the display area 100. The second electrode layer of the display area may be integrally connected with the second heat dissipation metal layer of the heat dissipation structure of the bezel area. The edge L0 of the second electrode layer of the display area may extend to the bezel area and may be located between two of the gate drive unit 2213 and the remaining two output capacitors 2213 in a direction parallel to the base.

[0115] Embodiments of this disclosure further provide a display device, including a display board described in any one of the embodiments described above. The display device may be any product or component having a display function, such as a mobile phone, tablet device, television, display, notebook computer, digital photo frame, navigator, etc.

Claims

1. A display substrate comprising a display area and a bezel area located around the display area, wherein the display area comprises a plurality of subpixels installed on a base, the subpixels comprising light-emitting elements, and the light-emitting elements comprising a first electrode, a light-emitting functional layer, and a second electrode layer sequentially stacked along a direction away from the base, A display substrate wherein at least one heat dissipation structure is provided in the bezel region, the heat dissipation structure includes a first heat dissipation groove, and a first heat dissipation metal layer and a second heat dissipation metal layer provided in the first heat dissipation groove, the second heat dissipation metal layer is laminated on the side of the first heat dissipation metal layer away from the base, and the second heat dissipation metal layer is provided in the same layer as the second electrode layer.

2. The display substrate according to claim 1, wherein the first heat dissipation metal layer is installed on the same layer as the first electrode.

3. The display substrate according to claim 1, wherein the orthographic projection of the first heat dissipation metal layer on the base includes the orthographic projection of the first heat dissipation groove on the base.

4. The display substrate according to claim 1, wherein the heat dissipation structure further includes a third heat dissipation metal layer, the first heat dissipation groove exposes at least a portion of the surface of the third heat dissipation metal layer that is separated from the base, and the first heat dissipation metal layer is laminated on the surface of the third heat dissipation metal layer that is separated from the base.

5. In a direction perpendicular to the base, the display area includes a drive structure layer and a light-emitting structure layer that are sequentially stacked on the base. The drive structure layer includes a plurality of pixel drive circuits, the light-emitting structure layer includes a plurality of light-emitting elements, the light-emitting elements are connected to the pixel drive circuits, and the drive structure layer includes a plurality of metal layers that are sequentially installed along a direction away from the base. The display substrate according to claim 4, wherein the third heat dissipation metal layer is installed on the same layer as any one of the metal layers in the drive structure layer, or the third heat dissipation metal layer includes a plurality of sub-heat dissipation metal layers that are stacked and installed, and any one of the sub-heat dissipation metal layers is installed on the same layer as the metal layer in the drive structure layer.

6. The display substrate according to claim 1, wherein the first heat dissipation groove includes a first recess and a second recess installed on the bottom surface of the first recess, the orthographic projection of the first recess on the base is larger than the orthographic projection of the second recess on the base, and a stepped surface is formed between the side surface of the first recess and the side surface of the second recess.

7. The gradient angle of the side surface of the first groove is β, the gradient angle of the side surface of the second groove is α, the length of the first groove in the third direction is d2, the length of the second groove in the third direction is d1, the depth of the first groove in the direction perpendicular to the base is h2, the depth of the second groove in the direction perpendicular to the base is h1, the length of the first heat dissipation metal layer in the third direction is S, the third direction is parallel to the base, d1 < d2, S is as follows The display substrate according to claim 6, satisfying the relationship d1 ≤ S ≤ 1.4 * d2, or d1 + (h1 / tanα + h2 / tanβ) ≤ S ≤ 1.4 * d2.

8. The heat dissipation structure further includes a third heat dissipation metal layer, the first heat dissipation groove exposes at least a portion of the surface of the third heat dissipation metal layer that is away from the base, and the first heat dissipation metal layer is laminated on the surface of the third heat dissipation metal layer that is away from the base. The display substrate according to claim 7, wherein the length of the third heat dissipation metal layer in the third direction is d3, and d3 satisfies the relationship d1 < d3 < d2, or d1 ≤ d3 ≤ d1 + (h1 / tanα + h2 / tanβ) ≤ S.

9. The heat dissipation structure further includes a third heat dissipation metal layer, and the first heat dissipation groove exposes at least a portion of the surface of the third heat dissipation metal layer that is separated from the base. The third heat dissipation metal layer includes a first sub-heat dissipation metal layer and a second sub-heat dissipation metal layer that are sequentially stacked along the direction away from the base, the first heat dissipation metal layer being stacked on the surface of the second sub-heat dissipation metal layer away from the base, The display substrate according to claim 6, wherein the length of the first groove in the third direction is d2, the length of the second groove in the third direction is d1, the length of the first sub-heat dissipation metal layer in the third direction is d6, the length of the second sub-heat dissipation metal layer in the third direction is d7, the third direction is parallel to the base, and d1 < d7 < d6 < d2.

10. The display substrate according to claim 1, wherein the length of the groove opening of the first heat dissipation groove in the third direction is d5, the length of the bottom surface of the first heat dissipation groove in the third direction is d4, the length of the first heat dissipation metal layer in the third direction is S, the third direction is parallel to the base, and d5 > d4, d4 ≤ S ≤ 1.4 * d5.

11. The heat dissipation structure further includes a third heat dissipation metal layer, the first heat dissipation groove exposes at least a portion of the surface of the third heat dissipation metal layer that is separated from the base, and the first heat dissipation metal layer is laminated on the surface of the third heat dissipation metal layer that is separated from the base. The display substrate according to claim 10, wherein the length of the third heat dissipation metal layer in the third direction is d3, and d4 ≤ d3 ≤ d5 ≤ S.

12. The display substrate according to claim 1, wherein the heat dissipation structure further includes a fourth heat dissipation metal layer, the fourth heat dissipation metal layer being laminated on the side of the second heat dissipation metal layer away from the base.

13. The display substrate according to claim 1, wherein the heat dissipation structure further includes a packing layer installed in the first heat dissipation groove, the packing layer being installed on the side of the second heat dissipation metal layer away from the base, or the packing layer being installed between the first heat dissipation metal layer and the second heat dissipation metal layer.

14. The aforementioned packing layer is a single film layer, or The display substrate according to claim 13, wherein the filling layer includes a plurality of sub-filling layers, the plurality of sub-filling layers are stacked in a direction perpendicular to the base, or the plurality of sub-filling layers are spaced apart in a direction parallel to the base.

15. In a direction perpendicular to the base, the display area includes a drive structure layer and a light-emitting structure layer sequentially stacked on the base, the drive structure layer includes a plurality of pixel drive circuits, and the light-emitting structure layer includes a plurality of light-emitting elements. The display area further includes a color filter layer and a black matrix installed on the side of the light-emitting structure layer away from the base, the black matrix is ​​provided with a plurality of light-transmitting holes, the color filter layer includes a plurality of filter units, the plurality of filter units are installed within the plurality of light-transmitting holes, the plurality of filter units include a plurality of types of filter units that transmit light of different colors, and the various types of filter units transmit light of a set color. The display substrate according to claim 14, wherein the packed layer is a single film layer and is installed on the same layer as any one of the plurality of types of filter units, or the packed layer includes a plurality of subpacked layers and each subpacked layer is installed on the same layer as any one of the plurality of types of filter units.

16. The light-emitting functional layer includes an organic light-emitting layer, the plurality of subpixels include a plurality of subpixels, each subpixel emits light of a set color, and the organic light-emitting layer of each subpixel is configured to emit light of a set color under the action of the voltage of the first electrode and the second electrode layer. The display substrate according to claim 14, wherein the packed layer is a single film layer and is installed on the same layer as the organic light-emitting layer of any one type of subpixel, or the packed layer includes a plurality of subpacking layers and each subpacking layer is installed on the same layer as the organic light-emitting layer of one type of subpixel.

17. The display area further includes a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, and the bezel area further includes a gate drive circuit, the gate drive circuit includes a plurality of cascaded gate drive units configured to supply drive signals to the plurality of gate lines, The display substrate according to claim 1, wherein the orthographic projection of at least one of the heat dissipation structures on the base is located between the display area and the orthographic projection of the gate drive circuit on the base.

18. The aforementioned at least one heat dissipation structure includes at least one first heat dissipation structure, at least one second heat dissipation structure, and at least one third heat dissipation structure. The display board according to claim 17, wherein the gate drive unit is connected to N gate lines, where N is an integer greater than 1, the length of the first heat dissipation groove of the first heat dissipation structure along the second direction is L1, the length of the first heat dissipation groove of the second heat dissipation structure along the second direction is L2, the length of the first heat dissipation groove of the third heat dissipation structure along the second direction is L3, and N*L1 > L3 ≥ (N-1)*L1, and / or N*L2 > L1 ≥ (N / 2)*L2.

19. The display board according to claim 17, wherein a second signal line extending in the second direction is provided between the display area and the gate drive circuit within the bezel area, the second signal line is provided close to the edge of the display area, and the plurality of heat dissipation structures are located between the second signal line and the gate drive circuit in a direction parallel to the base.

20. A gate connection line is further installed in the bezel region, and the gate line is connected to the gate drive unit via the gate connection line. The display board according to claim 17, wherein the first heat dissipation metal layers of at least two of the heat dissipation structures are connected to form an integrated structure and overlap with at least two adjacent gate connection lines connected to the same gate drive unit.

21. The gate drive unit includes a plurality of output modules, each output module includes an output transistor and an output capacitor. The display board according to claim 17, wherein the at least one heat dissipation structure includes at least one fourth heat dissipation structure and at least one fifth heat dissipation structure, the fourth heat dissipation structure is installed between two adjacent stages of the gate drive unit, and the fifth heat dissipation structure is installed between a plurality of the output capacitors of the gate drive unit.

22. The display substrate according to claim 17, wherein the bezel region is further provided with heat insulating grooves, and the orthographic projection of the heat insulating grooves on the base is located between the display region and the orthographic projection of the gate drive circuit on the base.

23. A display device comprising a display board according to any one of claims 1 to 22.

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