Computing systems with graphics processing unit (GPU) overlay using quantum processing units (QPUs)

Abstract

This patent document provides the design of an efficient quantum-classical hybrid computing system capable of information processing based on both quantum computing, which uses different quantum states of qubits, and classical digital computing, which uses a digital processor including one or more graphics processing unit (GPU) processors. The present invention provides a computing system with a graphics processing unit (GPU) overlay using a quantum processing unit (QPU).

Description

Technical Field

[0001] (Claims of Priority and Cross - References to Related Applications) This patent document claims the priority and benefit of U.S. Patent Application No. 63 / 497,685, filed on April 21, 2023, entitled "COMPUTING SYSTEM WITH GRAPHICS PROCESSING UNIT (GPU) OVERLAY WITH QUANTUM PROCESSING UNIT (QPU)".

[0002] This patent document relates to a computing or information processing system that includes a quantum computing module that performs information processing or computing using the quantum state of a quantum mechanical device or circuit.

Background Art

[0003] Classical digital computers are designed to perform calculations based on Boolean logic. Computing technologies based on Boolean logic have revolutionized a wide range of industries and technologies over the past few decades. However, they also have limitations when performing very complex or numerous calculations, such as modeling the molecular structure and properties of chemical compounds or biological structures, encryption, or modeling complex systems related to weather forecasting, climate change, and others. Various new calculation techniques have been investigated to complement or replace Boolean - logic - based digital computing.

[0004] Quantum mechanical systems can be used to construct new computational systems for complex information processing. A suitable quantum system for quantum computing has an ensemble of subsystems that exhibit different quantum states that are correlated with each other, or "entangled," due to quantum coherence, including long-range quantum coherence. In various implementations for quantum computers, each subsystem in the ensemble of subsystems may be a quantum system that exhibits two or more different quantum states to act as a fundamental quantum device, and information can be represented, stored, processed, and transmitted by the superposition and correlation of the quantum states of different fundamental quantum devices. One embodiment of such a fundamental quantum device is a two-state device, known as a qubit. Some examples of qubit implementations include superconducting qubits based on superconducting Josephson junctions, developed by IBM, Google, Intel, and other companies; ion trapping devices based on laser beam electromagnetic trapping fields, developed by Honeywell and IonQ; semiconductor-based quantum dots; and other devices capable of quantum computing operation. [Overview of the Initiative] [Means for solving the problem]

[0005] This patent document provides the design of an efficient quantum-classical hybrid computing system capable of information processing, based on both quantum computing, which uses different quantum states of qubits, and classical digital computing, which uses digital processors including one or more superconducting digital processors and one or more graphics processing unit (GPU) processors.

[0006] For example, in some embodiments, the technology disclosed in this patent document can be implemented to provide a method for computing based on both quantum computing, which uses different quantum states of qubits, and classical digital computing, which uses a digital processor including one or more graphics processing unit (GPU) processors. The method includes operating a quantum computing module, which includes different qubit circuits exhibiting different quantum states, to perform quantum computing operations; generating readout signals indicating the quantum states of the qubit circuits of the quantum computing module; and operating a hierarchical quantum error correction decoding and quantum classical hybrid co-processing circuit module, which exhibits different processing latency and different decoding complexity levels in processing the readout signals of the qubit circuits of the quantum computing module; and operating a graphics processing unit (GPU) overlay module, which includes one or more graphics processing unit (GPU) processors and a decoding module, coupled to communicate with the hierarchical quantum error correction decoding and quantum classical hybrid co-processing circuit module, to perform quantum error correction decoding and quantum classical hybrid co-processing and GPU processing operations based on the quantum error correction decoding operations performed by the hierarchical circuit module.

[0007] For example, in other embodiments, the technology disclosed in this patent document can be implemented to provide a quantum-classical hybrid computing system including a cryogenic holding system structured to include different cryogenic stages that are operable to provide lower and higher cryogenic temperatures. A quantum computing module is encapsulated by the cryogenic holding system at lower cryogenic temperatures and structured to include different qubit circuits that exhibit different quantum states and perform quantum computing operations. A qubit management circuit module is provided adjacent to the quantum computing module and encapsulated by the cryogenic holding system, including a qubit control circuit that generates and directs control signals for controlling the qubit circuits of the quantum computing module, and a qubit readout circuit that interacts with the qubit circuits respectively and outputs readout signals from the qubit circuits, respectively, indicating the quantum states of the qubit circuits. The system also includes a hierarchical circuit module, which is encapsulated by a cryogenic holding system at higher cryogenic temperatures and structured to communicate with a qubit management circuit module in association with control signals and read signals, the hierarchical circuit module being structured to include a hierarchical quantum error correction decoding and quantum classical hybrid co-processing circuit module, which exhibits increasing processing latency and increasing decoding complexity levels along the direction of different cryogenic stages as different higher cryogenic temperatures increase. The system further includes a graphics processing unit (GPU) overlay module, which includes one or more graphics processing unit (GPU) processors and a decoding module, coupled to communicate with the final hierarchical circuit module, which is encapsulated by a cryogenic holding system at the highest temperature of higher cryogenic temperatures. The GPU overlay module is configured to perform GPU processing operations, including quantum error correction decoding and quantum classical hybrid co-processing, based on the quantum error correction decoding operations performed by the hierarchical circuit module encapsulated by the cryogenic holding system.

[0008] In some implementations of the above system, at least a portion of the GPU overlay module and hierarchical circuit module includes a classical digital processor designed to perform certain calculations based on Boolean logic. In some implementations, a GPU-optimized decoder may also be implemented to provide neural network-type decoding behavior. In another embodiment, a CPU / FPGA-optimized decoder may be implemented to provide decoding behavior based on Union Find and Minimum Weight Perfect Matching. In yet another embodiment, CPU-optimized decoding may run on the GPU to provide efficient decoding behavior.

[0009] The above and other embodiments, associated features, and specific implementations thereof are described in detail in the drawings, description, and claims. [Brief explanation of the drawing]

[0010] [Figure 1A] Figures 1A, 1B, 1C, 1D, and 1E illustrate an example of a quantum-classical hybrid computing system. [Figure 1B] Figures 1A, 1B, 1C, 1D, and 1E illustrate an example of a quantum-classical hybrid computing system. [Figure 1C] Figures 1A, 1B, 1C, 1D, and 1E illustrate an example of a quantum-classical hybrid computing system. [Figure 1D] Figures 1A, 1B, 1C, 1D, and 1E illustrate an example of a quantum-classical hybrid computing system. [Figure 1E] Figures 1A, 1B, 1C, 1D, and 1E illustrate an example of a quantum-classical hybrid computing system.

[0011] [Figure 2]Figures 2, 3, and 4 illustrate an example of a GPU overlay using a quantum processing unit system that enables efficient computing operations using one or more graphics processing unit (GPU) processors. [Figure 3] Figures 2, 3, and 4 illustrate an example of a GPU overlay using a quantum processing unit system that enables efficient computing operations using one or more graphics processing unit (GPU) processors. [Figure 4] Figures 2, 3, and 4 illustrate an example of a GPU overlay using a quantum processing unit system that enables efficient computing operations using one or more graphics processing unit (GPU) processors. [Modes for carrying out the invention]

[0012] Detailed explanation The technology disclosed in this patent document can be implemented to provide a scalable quantum-classical hybrid computing system for various computing applications by leveraging both the quantum computing capabilities of a quantum computing system or quantum processing unit (QPU) system and the digital computing capabilities of a classical digital computer processor. In particular, the classical digital computer processor may include a GPU processor for leveraging parallel processing within the GPU processor to provide graphics processing unit (GPU) enhanced or accelerated quantum-classical hybrid computing processing within the disclosed scalable quantum-classical hybrid computing system.

[0013] Figures 1A, 1B, 1C, 1D, and 1E illustrate an embodiment of the QPU system and certain features. Figures 2, 3, and 4 illustrate an embodiment of a computing system with a GPU overlay using a QPU system, enabling efficient computing operation by using one or more GPU processors in the graphics processing unit (GPU) overlay.

[0014] The computing systems disclosed in this patent document include quantum processing unit (QPU) systems that perform computations by using the quantum states of an ensemble of subsystems, each exhibiting two or more different quantum states, to act as a fundamental quantum device, such that information can be represented, stored, processed, and transmitted by the superposition and correlation of quantum states of different fundamental quantum devices. Such fundamental quantum devices can be qubit circuits in various configurations, including superconducting circuits, that are capable of operating at cryogenic temperatures low enough to exhibit two or more different quantum states.

[0015] In general, QPU systems can be based on a variety of QPU technologies, including, for example, superconducting Josephson junctions, ion trapping devices based on electromagnetic trapping fields using laser beams, or semiconductor-based quantum dots. The following embodiments of QPU systems are implemented by using superconducting-based quantum computing modules (e.g., superconducting Josephson junctions) and by combining quantum computing modules or devices with classical digital computing modules or devices in a manner that enables the system to be scalable for complex computing applications. One of the features of the disclosed scalable quantum-classical hybrid computing system is the strategic partitioning of the system into different quantum and classical digital computing modules, devices, or components at various cryogenic stages at different cryogenic temperatures. Such implementations of the disclosed technology can be used to simplify and reduce the complex and bulky cryogenic systems commonly used in various quantum computer systems using superconducting quantum computing devices, and to reduce the use, or level of use, of complex superconducting cabling systems for linking different computing or processing modules. Implementations of the disclosed technology can be designed to enable commercially scalable fabrication using integrated circuit (IC) fabrication processes and equipment when manufacturing critical modules or devices for quantum computer systems based on superconducting Josephson junctions. The technology disclosed in this patent document can be implemented to provide a special interconnection design for connecting hardware components in a multi-stage cryogenic system to provide high-speed communication between quantum computing modules, their controllers, and classical digital computing modules, including GPUs, while enabling efficient management of wiring with other modules.

[0016] Figures 1A, 1B, 1C, 1D, and 1E illustrate an example of a hybrid system for implementing a scalable quantum-classical hybrid computing system by connecting different hardware modules within a multi-stage cryogenic system.

[0017] Figure 1A shows an embodiment of a quantum computing system 110 for producing a scalable quantum-classical hybrid computing system for various computing applications. As its name implies, the quantum computing system 110 includes a plurality of qubit circuits, performs computing operations based on the quantum states of the qubit circuits, and communicates with an external computer or computing system 130 via a communication link or network 120. The communication link and network 120 may include circuits to which signals are transmitted in the form of electromagnetic signals, including electrical signals carried, for example, by conductive wires and / or optical signals. During operation, the quantum computing system 110 receives computation requests or tasks from one or more external computers or computing systems 130, performs the requested computation operations, and returns the computation results to one or more requesting external computers or computing systems 130. The communication and / or interaction between the quantum computing system 110 and the external computers or computing systems 130 is via the communication link or network 120, which can constitute the longest communication cycle in time in the operation of the quantum computing system 110 and is labeled as a long communication link or loop. As will be further explained below, the quantum computing system 110 is structured to partition different internal computing modules, and so these internal computing modules communicate via shorter internal communication links or loops, such as medium communication links or loops with moderate time delays, and high-speed communication links or loops with the shortest time delays.

[0018] The quantum computing system 110 includes a multi-stage cryogenic system to provide different cryogenic stages at different locations and maintain different modules or devices at different cryogenic temperatures to keep them at their respective desired temperatures (e.g., T1, T2, T3, and T4, as shown). In some implementations, the different cryogenic stages may be designed to produce temperatures of millikelvin to tens of kelvin. The exemplary system 110 includes one or more quantum computing modules 102, each quantum computing module 102 including multiple qubit circuits or devices as a quantum qubit ensemble to perform desired quantum computing operations through their respective qubit states. In many implementations, the quantum computing module 102 is engaged or coupled to a cryogenic stage at a low cryogenic temperature T1 to ensure that the qubit circuits or devices are under acceptable quantum computing operating conditions, such as desired superconducting conditions and sufficiently low noise and interference levels. The qubit management circuit module 104 communicates with the quantum computing module 102, provides control signals to individual qubit circuits or devices of the quantum computing module 102, and provides signals for reading from individual qubit circuits or devices, and may be implemented by using a non-quantum mechanical processing network such as a digital network, an analog network, or a combination of digital and analog networks. The qubit management circuit module 104 may also be implemented using a superconducting network, and in some implementations, it is coupled to a cryogenic stage at a cryogenic temperature T2, which may be different from a low cryogenic temperature T1, or in other implementations, which may be the same as temperature T1. In some designs, as will be further described below, the quantum computing module 102 and the qubit management circuit module 104 may engage to share a common cryogenic stage so that both modules are kept at the same cryogenic temperature.The qubit management circuit module 104 can be structured to include (1) a qubit control circuit, each of which directs control signals to the qubit circuits in order to control them, and (2) a qubit readout circuit, each of which outputs a readout signal from the qubit circuits. In this embodiment, since the quantum computing operation is partially performed within the quantum computing module 102 based on control signals from the qubit management circuit module 104 to the qubit circuits, and the readout of the qubit circuits is performed by the qubit management circuit module 104, the quantum computing module 102 and the qubit management circuit module 104 together form the "heart" or "core" of the quantum computing system 110. Communication between the quantum computing module 102 and the qubit management circuit module 104 is essential to the quantum computing operation in terms of the quality and speed of such communication. Therefore, in the implementation, the quantum computing module 102 and the qubit management circuit module 104 can be installed or positioned physically close to or adjacent to each other to shorten the signal path between the two modules 102 and 104 and reduce any interference or noise to such communication. In addition, the function or operation of the qubit management circuit module 104 may be limited by intentional design to certain core functions or operations in relation to quantum computation performed by the quantum computing module 102, and thus the qubit management circuit module 104 can achieve short or fast response or processing times and ensure fast input / output signal transmission in the quantum computing module 102.The intentionally reduced functional design considerations for the qubit management circuit module 104 are also based on the need to reduce power consumption and energy dissipation by the qubit management circuit module 104 and its surroundings, given its proximity to the quantum computing module 102, the desire to reduce noise or interference from the qubit management circuit module 104 to the quantum computing module 102, and the need to maintain appropriate cryogenic conditions for both the qubit management circuit module 104 and the adjacent quantum computing module 102. Based on the above and other considerations, the interconnection and signal paths between the two modules 102 and 104 are designed to form a high-speed communication link or loop with the shortest possible time delay with respect to the quantum computing system 110. For example, in some implementations, the quantum computing module 102 may include at least one integrated chip supporting one or more qubit circuits, and the qubit management circuit module 104 may be formed on another integrated chip that is mechanically and electrically directly coupled to the integrated chip with the qubit circuits as a multi-chip module via superconducting bumps, capacitive coupling, or magnetic coupling over a vacuum, and control and read signals may be transferred between them. The multi-chip module formed by the two modules 102 and 104 can be coupled to the same cryogenic stage at low cryogenic temperatures T1. The design may be commercially important because the chip fabrication for the multi-chip module formed by the two modules 102 and 104 is a scalable platform that allows a wide range of qubit circuits to be fabricated and included within the quantum computing module 102, and similarly, the qubit management circuit module 104 can also be scaled based on the number of qubit circuits present.

[0019] The quantum computing system 110 in Figure 1A further includes a digital processing module 108 that provides certain signal and data processing functions or operations related to the quantum computing system 110 in relation to quantum computations performed by the quantum computing module 102 via a qubit management circuit module 104. In this regard, the digital processing module 108 forms the core processing module for non-quantum computation and / or processing functions within the quantum computing system 110 and is therefore designed with a much more complex network and higher processing power than the qubit management circuit module 104. Specifically, certain functions and / or processing operations that may not be created in the qubit management circuit module 104 may be included in the network of the digital processing module 108. In addition, the digital processing module 108 also functions as an interface between the quantum computing system 110 and one or more external computers or computing systems 130 via a communication link or network 120. Therefore, the digital processing module 108 is designed to further include processing functions associated with communication and interaction between the quantum computing system 110 and the external computers or computing systems 130. Therefore, unlike the installation and design of the qubit management circuit module 104, the digital processing module 108 is designed to be complex and capable of being a classical counterpart and coprocessor to the quantum computing module 102 of the quantum computing system 110. The increased functionality and / or processing operations and processing power contained within the digital processing module 108 increases the complexity and size of the circuitry of the digital processing module 108, further increasing the power consumption and energy dissipation of the digital processing module 108.Therefore, in order to reduce the noise and interference that the digital processing module 108 may impose on the quantum computing module 102, it is desirable to install the digital processing module 108 physically separated from the quantum computing module 102 and its adjacent neighboring qubit management circuit module 104. The digital processing module 108 may be designed with various functions and capabilities, including, for example, error correction functions for the quantum computing system 110, and non-quantum computation and / or processing functions within the quantum computing system 110, including functions related to the control and reading of the quantum computing module 102, performed, for example by the qubit management circuit module 104, as well as data management for quantum computations, performed by the quantum computing module 102. In some implementations, the digital processing module 108 may be coupled to a cryogenic stage at a higher temperature T4 than that for the quantum computing module 102 (at T1) and the qubit management circuit module 104 (at T1 or T2). The digital processing module 108 may be designed to include a superconducting circuit network and be enclosed within a multi-stage cryogenic system of the quantum computing system 110.

[0020] The intentional design to place the digital processing module 108 separately from the qubit management circuit module 104 leads to a longer signal path or connection between the digital processing module 108 and the qubit management circuit module 104. Such a signal path or connection may be formed within the enclosure of the multi-stage cryogenic system by using superconducting wires or cables. It should be noted that the long length of such a signal path or connection may cause a certain degree of signal degradation, and one option to address this is to add one or more interconnect repeaters or signal conditioning circuits 106 between the digital processing module 108 and the qubit management circuit module 104 to condition the signal. Similar to other modules within the multi-stage cryogenic system, each interconnect repeater or signal conditioning circuit 106 may be engaged or coupled to the cryogenic stage at a temperature T3 that is higher than the temperature of the qubit management circuit module 104 (at T1 or T2) and lower than the temperature of the digital processing module 108 (at T4). For example, the digital signal conditioning circuit module 106 may include a superconducting circuit that conditions a control signal or a readout signal.

[0021] In some implementations, the quantum computing system 110 may further include a digital processing subsystem 109 outside the multi-stage cryogenic system or the cryostat system, which communicates with the digital processing module 108 and is associated with performing operations related to the execution of quantum or quantum-classical algorithms and / or communication with one or more other computers or networks 130. This is shown in the embodiments of FIGS. 1C and 1D. This digital processing subsystem 109, which is outside the cryostat system, may include one or more CMOS digital processors, one or more field-programmable gate arrays (FPGAs), or one or more application-specific integrated circuits (ASICs), or one or more central processing units (CPUs).

[0022] The quantum processing performed by the quantum computing module 102 is the core of the quantum computing system 110, and signal transmission and communication between the quantum computing module 102 and the rest of the system 110 play a crucial role in the overall computing speed and performance of the system 110. Latency in signal transmission and communication between the quantum computing module 102 and the rest of the system 110 is a critical parameter to optimize in order to achieve a scalable quantum-classical hybrid computing system for commercial applications. During operation, information is passed between the quantum computing module 102, other processing modules, and computing entities involved in the computations performed in the quantum computing system 110. As illustrated, different communication links and / or feedback loops are formed between the quantum computing module 102, non-quantum modules, and other components within the system 110. The fastest link / loop, labeled as a short loop in Figure 1A, is between the quantum computing module 102 and the qubit management circuit module 104. This link / loop can be compared to a communication link / loop formed between the quantum computing module 102 and the digital processing module 108, because 1) communication between these modules must traverse a longer distance, including passing through the qubit management module 104, which can perform its own operation on the data circulation between the quantum computing module 102 and the digital processing module 108, and 2) the digital processing module 108 generally incurs longer latency because it performs more complex processing operations. Therefore, in Figure 1A, the communication between 102 and 108 is labeled as a medium communication link / loop.An even longer waiting time occurs between the quantum computing module 102 and an external computer or computing system 130, and again, as compared to the medium link / loop, due to the increased distance (including the communication link or network 120, as well as the communication path and the operations considered as possibilities for short and medium loops) and the complexity of the processing operations, it is labeled as a long communication link / loop in FIG. 1A.

[0023] Thus, the embodiment of the quantum computing system 110 in FIG. 1A includes special design features, providing a hybrid computing environment that combines the processing functions and / or operations by a quantum computing part (e.g., the quantum computing module 102) and a non - quantum classical processing part (e.g., the qubit management circuit module 104 and the digital processing module 108). While installing the qubit management circuit module 104 to be physically close to the quantum computing module 102, in light of the intentional design to space the quantum computing module 102 from the digital processing module 108, different amounts and types of processing functions and / or operations of the non - quantum classical processing part are strategically partitioned and distributed between the qubit management circuit module 104 and the digital processing module 108.

[0024] In some implementations, the digital processing module 108 may be designed to include two or more different processing modules to optimize the computation speed and performance of the digital processing module 108. For example, the digital processing module 108 may be further divided into a series of modules, as shown in Figure 1B, and different temperature stages of the cryogenic system may house one or more such modules. In general, the design of the quantum computing system 110 in Figure 1A allows for the optimization of the placement of each module within the cryogenic system to balance its particular need for short latency (which works favorably for proximity to the quantum module 102) with the ability to manipulate dissipation between processing operations (which works favorably for higher temperature stages, which are placed further away from the quantum module 102) and to efficiently utilize the volume of the cryogenic system.

[0025] Figure 1C shows an embodiment for performing a certain processing operation in different modules within the system 110 of Figure 1A, specifically, a processing operation in the digital processing module 108, a processing operation in the additional digital processing module 109 which operates at a higher temperature than that of the digital processing module 108, and a processing operation in the qubit management circuit module 104. In a specific embodiment, Figure 1C shows that, in light of qubit readout from the qubit management circuit module 104, a desired quantum gate sequence generated by the additional digital processing module 109 based on information from the digital processing module 108 is transmitted to the digital processing module 108, processed thereto, and generates an SFQ control pulse pattern. The qubit management circuit module 104 receives such an SFQ control pulse pattern and applies the received SFQ control pulse pattern and / or magnetic flux bias to the quantum module 102, setting the relevant qubits in the quantum gate sequence. This is one embodiment for implementing communication between the quantum computing module 102 and the digital processing module 108, including the communication loop in Figure 1A, i.e., a link with the qubit management module 104, or an arbitrary interconnection module 106 between modules 102 and 108. Figure 1C further shows one embodiment for implementing a short communication loop between the qubit management module 104 and the quantum computing module 102, where qubit readouts obtained from reading the quantum computing module 102 are digitally processed by the qubit management module 104, and the processed information is further used by the qubit management circuit module 104 to apply an SFQ control pulse pattern and / or magnetic flux bias to the quantum module 102.

[0026] In various implementations, the quantum computing module 102 and the non-quantum classical processing parts (e.g., the qubit management circuit module 104 and the digital processing module 108) are structured to include superconducting circuits or devices coupled to different cryogenic stages of a multistage cryogenic system, and superconducting interconnect wires 112, 114, and 116 are provided and maintained at different temperatures in different locations for transferring signals between different modules or stages. The multistage cryogenic system for the quantum computing system 110 may be implemented in various configurations, including a multistage dilution refrigerator based on a mixture of helium-3 and helium-4 to provide different cryogenic stages at different graded cryogenic temperatures, the operating principle of which is to provide different cryogenic stages. In some implementations, the cryogenic holding device system may include a nuclear demagnetizing refrigerator or an adiabatic demagnetizing refrigerator.

[0027] Modules within the quantum computing system 110 may be implemented in various configurations. For example, each qubit circuit for a qubit in the quantum computing module 102 may include a superconducting Josephson junction circuit or a switching superconducting circuit different from a Josephson junction circuit. For example, the qubit management circuit module 104 may be implemented to include a superconducting Josephson junction circuit or a single-flux quantum (SFQ) logic circuit or a quantum flux parametron circuit such as an adiabatic quantum flux parametron circuit, or a nanowire switch, or a superconducting ferromagnetic transistor, or a superconducting spintronic device, or a field-effect superconducting device. The digital processing module 108 may be implemented to include an SFQ network, a field-programmable gate array (FPGA), or one or more application-specific integrated circuits (ASICs).

[0028] In the system of Figure 1A, an optical communication link may be used for signal transmission, either as a replacement for a conductive wire or cable, or as an additional link in combination with a conductive wire or cable. The optical communication link can provide faster data transmission and increase communication bandwidth. For example, optical communication can be used between a cryogenic stage (e.g., module 108 in Figure 1A) with a highest temperature stage and a room temperature stage. In implementations, optical transmitter and receiver devices are provided in such stages or circuit modules to enable the transmission and reception of optical signals between the cryogenic stage, which is installed at the highest temperature of the cryogenic holding device system, and room temperature electronic equipment, to provide communication between them. In some implementations, such an optical communication link may be implemented between module 108 and a CMOS FPGA subsystem.

[0029] Figure 1D shows an embodiment of a quantum computing system capable of information processing based on quantum computing using the quantum states of qubits, at least in part, based on the design of Figure 1A. The cryogenic holding system in this embodiment is structured and operable to provide different cryogenic stages at different temperatures of 20 mK, 0.1 K, 0.7 K, and 3 K. Different circuit modules in the different cryogenic stages are interconnected by superconducting wires such as NbTi / Kapton (i.e., NbTi / polyamide) strips. The quantum computing module enclosed by the cryogenic holding system includes a first integrated chip structured to support qubit circuits. Each qubit circuit is structured as a superconducting circuit, exhibits a different quantum state as a qubit, and interacts quantum mechanically with other qubit circuits via quantum entanglement, causing superposition or correlation of different quantum states of the qubit circuits. A qubit management circuit module 104 is located adjacent to the quantum computing module 102 and coupled to be maintained at the same low cryogenic temperature as the quantum computing module. The qubit management circuit includes a second integrated chip, a qubit control circuit supported by the second integrated chip and structured to directly send control signals to the qubit circuit for controlling the qubit circuit, and a qubit readout circuit supported by the second integrated chip and structured to output readout signals from the qubit circuit. During operation, the readout signals each represent the quantum state of the qubit circuit, and the qubit control circuit and qubit readout circuit include superconducting circuits and are structured to operate using the control signals and readout signals in a non-quantum classical manner based on digital processing. Notably, the second integrated chip engages with the first integrated chip to form a multi-chip module (MCM) that transfers the control signals and readout signals.

[0030] Figure 1E shows an embodiment for implementing an interconnection that links different hardware components of classical and quantum circuits in the embodiments of Figures 1A, 1C, or 1D. The system embodiment in Figure 1E includes at least one classical non-quantum digital processing module 108 labeled as a "Classical Processor Chip," at least one SFQ repeater as part of an interconnection network or module 106, and at least one classical superconducting controller as part of a qubit management circuit module 104 that controls a quantum computing processor or module 102 with a plurality of qubit circuits or devices.

[0031] The interconnection in Figure 1E is designed to include superconducting connection nodes or pads 140 and superconducting connection cables 150 for connecting classical circuits 104, 106, and 108 to the quantum computing processor or module 102. As illustrated, the superconducting connection nodes or pads 140 may be implemented as superconducting bumps that are in direct contact with one or more hardware components (102, 104, 106, 108) to be connected and can be used to provide connections between the hardware components and the superconducting cables. As described with reference to Figure 1A, the quantum computing module 102 and the qubit management circuit module 104 can be installed adjacent to each other, enabling short connection paths between them for high-speed inter-module communication and can be thermally coupled to the same cryogenic stage at the same low cryogenic temperature. Of particular note is that the communication link or loop between the classical superconducting controller as part of the qubit management circuit module 104 and the quantum processor chip 102 should be a high-speed communication link or loop, and superconducting bumps can be used to interconnect the two modules 102 and 104 to enable high-speed exchange of information for quantum computing operation and readout. In some implementations, the qubit management circuit module 104, including the classical controller chip, is positioned on a cryogenic cooler's cold plate directly above or below the quantum computing module 102, which can reduce noise and interference to quantum computing operation from qubit circuits or devices inside the quantum computing module 102. In some implementations, superconducting bumps can be configured or used in the form of strips or microstrip lines, or other on-chip transmission lines, as well as fences or walls that create compartments to isolate qubits or systems of multiple qubits from one another, in order to reduce mutual crosstalk between superconducting elements or systems and to improve the quality coefficient of the resonator.

[0032] In addition to the direct electrical connection between the quantum computing module 102 and the qubit management circuit module 104, non-contact connections, including, for example, differential capacitive coupling and magnetic coupling between qubits and passive transmission lines, may be used to achieve high-speed communication, both of which provide a communication link without direct connection and allow for compensation of geometric mismatches between modules 102 and 104 and other components as a result of the manufacturing process.

[0033] In the embodiment of the two-state qubit circuit, the quantum computing operation by the qubit circuit or device inside the quantum computing module 102, unlike deterministic Turing machines and classical computers based on boolean bits with binary qubit states of "0" and "1", uses quantum mechanical phenomena such as the superposition of binary "0" and "1" qubit states, entanglement between qubits, and interference between the probability amplitudes of non-deterministic measurement results to perform computing operations. The superconducting qubit inside the quantum computing module 102 can be implemented by a superconducting Josephson junction. A Josephson junction is a system of weakly coupled superconductors that exhibit correlated or coherent states and behaves like a nonlinear inductor, enabling the creation of a quantum non-harmonic oscillator. Two discrete energy level states of this non-harmonic oscillator and their quantum superposition are used to create a qubit. Using a Josephson junction, several versions of superconducting qubits such as transmon, exmon, quantronium, and fluxonium can be constructed.

[0034] The state of a qubit is controlled by applying a microwave signal to it. In various implementations, the microwave signal generator may be a room-temperature device, while the quantum circuit containing the qubit operates at very low cryogenic temperatures to reduce undesirable decoherence of the qubit. Specifically, the wiring required to provide microwave signals to the qubit circuit may involve different compartments maintained at different temperatures, from room temperature to the lowest temperature in the cryogenic stage where the quantum circuit is installed, and thus may cause or introduce undesirable electrical noise or excessive thermal load. Such wiring for a significant number of qubit circuits can occupy a lot of space. These factors can lead to undesirable decoherence of the qubit quantum state, posing a significant problem for scaling up quantum computers.To overcome this problem, various techniques may be used to control qubits within a fully integrated cryogenic quantum-classical hybrid processor, such as those shown in Figures 1A-1E, for example, the integration of superconducting qubits with classical superconducting digital logic families such as inverse quantum logic (RQL) disclosed by Quentin P. Herr and Anna Y. Herr in "Ultra-low-power superconductor logic" J. Appl. Phys. 109, 103903 (2011), the use of adiabatic quantum flux parametrons (AQFP) by O. Chen, R. Cai, Y. Wang, F. Ke, T. Yamae, R. Saito, N. Takeuchi, and N. Yoshikawa in "Adiabatic Quantum-Flux-Parametron: Towards Building Extremely Energy-Efficient Circuits and Systems" Sci. Rep. 9, 10514 (2019), or "Energy-Efficient Single Flux This includes the use of single-flux quantum (SFQ) technology, as described by OA Mukhanov in "Quantum Technology" IEEE Trans. Appl. Supercond. 21, 760 (2011). As part of the interconnection design for the system in Figures 1A–1E, qubit control can be implemented via an SFQ system for controlling the qubit state by applying a sequence of SFQ pulses, without the conventional use of microwave signals as disclosed in U.S. Patent No. 9,425,804. Techniques for applying magnetic flux to quantum coherent superconducting circuits, as disclosed in U.S. Patent Application Publication No. US 2015 / 0263736A1, may also be implemented. Qubit readout may be implemented by quantum electrodynamic measurements, as disclosed in U.S. Patent No. 9,692,423. Cryogenic CMOS (cryoCMOS) techniques may also be implemented within the system in Figures 1A–1E, for example, to control superconducting qubits."Cryo-CMOS for quantum computing", Technical Digest - International Electron Devices Meeting, IEDM (2017), pp. 1-13. doi: 10.1109 / IEDM.2016.7838410, and JC Bardin, E. Jeffrey, E. Lucero, T. Huang, O. Naaman, R. Barends, T. White, M. Giustina, D. Sank, P. Roushan, K. Arya, B. Chiaro, J. Kelly, J. Chen, B. Burkett, Y. Chen, A. Dunsworth, A. Fowler, B. Foxen, C. Gidney, R. Graff, P. Klimov, J. Mutus, M. McEwen, A. See Megrant, M. Neeley, C. Neill, C. Quintana, A. Vainsencher, H. Neven, and J. Martinis, “A 28nm Bulk-CMOS 4-to-8GHz 2mW Cryogenic Pulse Modulator for Scalable Quantum Computing,” IEEE J. Solid-St. Circuits 54, 3043-3060 (2019). Those references are incorporated by reference as part of the disclosure of this patent document.

[0035] Practical implementation of the system in Figures 1A-1E requires careful design of the interconnection or interface between the quantum circuits of the quantum computing module 102, which is installed at low cryogenic temperatures (e.g., a certain millikelvin temperature), and the classical processing circuits, which are installed at higher temperatures (including liquid helium temperature). The interconnection in the embodiment of Figure 1E involves installing the quantum computing module 102 and the qubit management circuit module 104 adjacent to each other on the same cryogenic stage of a dilution refrigerator, without using any superconducting cables or wires 150 between modules 102 and 104. Instead, superconducting bumps or pads 140 are used to physically join or bind the two modules 102 and 104 together. The signal path between the two modules 102 and 104 can be implemented in various ways, including signal transmission via a conductive path formed through the superconducting bumps or pads 140 between modules 102 and 104, or signal transmission via capacitive and / or magnetic coupling between modules 102 and 104. The signal path between the two modules 102 and 104 is designed to minimize signal transmission time (for example, by reducing or eliminating the amount of wiring between modules 102 and 104) and to form a high-speed communication link or loop within the system, as described above with respect to Figure 1A.

[0036] In an implementation where two modules 102 and 104 are supported by two IC chips, the two chips may be stacked and bonded across each other to form a multi-chip module (MCM) where modules 102 and 104 are coupled as an integrated unit to the same low cryogenic stage, so that both modules 102 and 104 operate under the same low cryogenic conditions. Superconducting bumps or pads 140 may be used as part of the binding of the two IC chips or modules 102 and 104. The interconnection in the embodiment of Figure 1E also implements a combination of superconducting bumps or pads 140 and superconducting cables or wires 150, where the superconducting bumps or pads 140 are used at the terminals of the superconducting cables or wires 150 to connect the wire terminals to the device. For example, in Figure 1E, a qubit management circuit module 104 is shown to be connected to an interconnection network or module 106, such as a digital signal conditioning circuit module, via a superconducting cable or wire 150, with two sets of superconducting bumps or pads 140 used to splice the two end terminals of each superconducting cable or wire 150 to contact points on the qubit management circuit module 104 and the corresponding interconnection network or module 106. This use of superconducting bumps or pads 140 and superconducting cables or wires 150 can be applied to connections between other modules, such as connections between a digital processing module 108 and the corresponding interconnection network or module 106, and connections between different stages of the interconnection network or module 106 or between digital signal conditioning circuit modules. As shown, such superconducting cables or wires 150 with superconducting bumps or pads 140 form part of the intermediate communication links and loops, as described above with respect to Figure 1A.

[0037] In the above embodiment of the quantum-classical hybrid computing system shown in Figure 1A-1E, the classical digital processing modules 108 and 109 may be implemented to include various classical digital processors, such as a central processing unit (CPU) processor, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), and a graphics processing unit (GPU) processor, in order to share and cooperate with quantum computing within the quantum computing module 102 of the QPU system.

[0038] When a GPU processor is present, a hierarchical stepwise GPU overlay system can be implemented to enable GPU processing in the quantum-classical hybrid computing system shown in Figures 1A-1E. Figures 2, 3, and 4 show examples of hybrid systems with GPU overlays using QPU systems, where the GPU processor can be deployed in addition to other classical digital processors such as CPUs, FPGAs, and ASICs.

[0039] In some implementations of the system in Figures 2, 3, and 4, based on the system design in Figure 1A-1E, the QPU system itself may include cryogenic and room-temperature controllers, and functional components to support QPU control, readout, active reset, multiplexing, and cooperative processing and fault-tolerant operation. Fault-tolerant operation of the QPU system requires, in addition to other components, a quantum error correction architecture, a controller for addressing and reading qubits, and a decoding coprocessor. To achieve efficient fault-tolerant operation, it is desirable to minimize or reduce latency. In addition, to achieve efficient quantum-classical hybrid computation, it is desirable to minimize or reduce latency. In this regard, low-latency and high-speed QPU system operation, including qubit readout, qubit reset, qubit feedback, or calibration functions, can be realized or facilitated in a GPU overlay for the QPU system by utilizing a special SFQ system for an efficient and functional quantum error correction architecture.

[0040] The GPU overlays in Figures 2, 3, and 4 provide hierarchical or stepwise decoding operations based on the recognition that decoding is generally mathematically challenging and, in some approaches, NP-hard. The GPU overlays in the QPU system here utilize high-speed qubit controller functionality, which is integrated with the qubits. Referring to Figure 2, the fault-tolerant decoding functionality of the entire system is split across two or more hierarchical or stepwise levels or stages to improve the accuracy of the decoding operation or increase its speed and reduce latency.

[0041] In addition, this decoder hierarchy, which involves two or more stages, is designed to reduce the bandwidth of data transmitted across different levels of QPU and GPU overlays.

[0042] The decoder hierarchy is designed so that the first stage is computationally simpler than the second and later stages, which are more complex decoders, and is programmatically closest to the QPU qubits to support the shortest latency, while the last stage operates as a global decoder with the highest computational complexity of all stages.

[0043] The systems with GPU overlays in Figures 2, 3, and 4 include a qubit controller and two or more hierarchical layers of classical coprocessors to support various fault-tolerant operations of the QPU, including quantum-classical hybrid computation. The system may include multiple hierarchical layers of cooperative processing and decoding, with the lowest layer co-located at the same temperature as the qubit to provide the shortest possible interface latency, and the middle to top layers providing increasing levels of computational power to support fault-tolerant operation and cooperative processing, where the interface latency increases as the hierarchical level of the QPU and the temperature increases.

[0044] One of the key functions of the hierarchical collaborative processing layer is to assist decoding, thereby splitting the decoding calculation across the hierarchical levels. This design is further illustrated in Figure 3. Larger decoding logic blocks are assisted at higher levels. The QPU system would include lower and intermediate hierarchical levels of collaborative processing at desired low temperatures, e.g., 4K or below 4K. Additional hierarchical levels may be integrated into the QPU system at temperatures above the desired low temperature (e.g., 4K). These levels would assist pre-decoding and / or local decoding type decoders, used in conjunction with a GPU overlay, which would assist global decoding operations.

[0045] Referring to Figures 2 and 4, the GPU overlay system includes a GPU processor architecture (with one or more GPU processors) and other CMOS-based processor architectures to support integrated system functionality, including fault-tolerant QPU operation. The GPU overlay can support the highest-level global decoder and pre-decoding. In some implementations, the global decoder and pre-decoder may include neural network type decoders or other GPU-optimized error-corrected decoding functionality. To support the QPU's full quantum error-corrected decoding, the global decoder and pre-decoder may, in some implementations, include CPU, FPGA, or ASIC-optimized decoding functionality, including decoding algorithms such as Union Find and minimum-weighted perfect match. These decoding methods may be optimized to run on the GPU. The GPU system also includes hardware components and packaging, as well as software and firmware layers, to support the GPU system functionality. Referring to Figure 1A-1E in relation to Figures 2 and 4, the GPU processor in the GPU overlay design may be deployed in module 109, which is outside the cryogenic system or module 108, enclosed within the cryogenic system, or it may be deployed in both modules 109 and 108, in addition to other classical digital processors such as CPUs, FPGAs, and ASICs.

[0046] In one implementation, the QPU system comprises qubits, an SFQ, and a custom CMOS processor architecture, arranged in proximity across various operating temperatures of a QPU cryogenic support system, forming the first and additional hierarchical stages of the decoder and quantum-classical hybrid processor. The SFQ and CMOS processor architecture are optimized to support local and greedy decoding, which can be implemented with different types of neural networks or Boolean lookup tables, in addition to pre-decoding and other functions and cooperative processing. The QPU system also includes hardware components and packaging, as well as software and firmware layers, to support the functionality of the QPU system.

[0047] The GPU overlay for QPU is created through hardware and firmware interfaces optimized for high bandwidth and low latency. This entire GPU overlay of the QPU system includes an integrated software layer and a firmware layer to support system functionality, enabling the system to operate as a single node within data centers and other computing systems or infrastructure.

[0048] An example of a hierarchical function is further illustrated in Figure 3. The hierarchical structure of this system is designed so that larger computational complexities can be integrated into the system at higher hierarchical levels by taking advantage of the increased cooling output at higher hierarchical levels.

[0049] The lowest tier level will support quantum information processing using classical logic with the lowest complexity and shortest latency, limited by the QPU and available cooling output. This classical logic is used to support QPU management functions, including limited cooperative processing such as qubit control, qubit readout, (but not limited to) conditional qubit reset, control sequence updates, multiplexing / demultiplexing, and qubit readout result storage. These management functions are intended to support qubit superposition, entanglement, and interference related to quantum information processing. This shortest latency classical cooperative processing can also implement limited quantum-classical hybrid algorithm support and quantum error correction functions to support physical and logic quantum circuit operation and analysis. In addition, this lowest tier level will support the lowest level and shortest latency of hierarchical quantum error correction decoders. The limited computational complexity integrated at this tier level will support local error correction decoding, such as a binary logic lookup table decoder or a stored short-range lookup table.

[0050] At the intermediate hierarchical level, higher temperature cooling output enables more complex calculations, which can support more complex cooperative processing logic and larger memory capacities, such as random access memory. This includes higher complexity quantum management functions that support quantum circuit operation and analysis, such as qubit calibration, control pattern generation, multiplexing / demultiplexing, classical cooperative processing for quantum classical hybrid algorithm logic, and more. The intermediate hierarchical level may also be configured to support intermediate-level hierarchical quantum error correction pre-decoding, which supports more complex decoding logic, such as belief decoders and smaller neural network decoders on custom logic circuits. The intermediate hierarchical level may also include classical cooperative processing for quantum error correction functions, such as logic compilation, logic qubit encoding, logic Clifford gate execution, magic state distillation, and T gates, which support logic quantum circuit operation.

[0051] At the highest tier level, i.e., the GPU overlay, the available high computational complexity supports advanced quantum-classical hybrid co-processing for application support, including GPU-optimized features such as neural networks, tensor networks, and large-scale matrix multiplication. See Figure 3. The highest tier level also supports high-latency quantum management support features, including qubit and global system calibration. This highest tier level can be used to support the highest tier level of quantum error correction decoding. This includes GPU-optimized pre-decoders, including large-scale neural network or tensor network type decoders and combined global decoders, such as Union Find or minimum-weighted perfect match decoders, which would run on a CPU or custom CMOS processor (FPGA or ASIC) or a combined decoder, optimized for GPU operation. A GPU overlay interface system may be incorporated at this highest tier level to provide interface functions and logic that provide an optimized and minimized latency interface between the QPU system and the GPU overlay system.

[0052] Additional classical co-processing for quantum error correction functions may be included to support intermediate and lower-level functions.

[0053] The collaborative processing and decoding used at each hierarchical level may be optimized to take advantage of the shortest possible latency available between that level and the QPU.

[0054] Some technical features of the above-disclosed embodiments are described in a 2001 publication by Kai Meinerz, Chae-Yeun Park, and Simon Trebst, entitled "Scalable Neural Decoder for Topological Surface Codes" (available at https: / / arxiv.org / pdf / 2101.07285.pdf), which discloses certain aspects of a neural network decoder that can be optimally launched on a GPU or an optimized cryogenic SFQ-based neural network, as discussed above. In addition, further embodiments of the technical features are disclosed in a 2022 publication by Nicolas Delfosse, entitled "Hierarchical decoding to reduce hardware requirements for quantum computing" (available at https: / / arxiv.org / pdf / 2001.11427.pdf), concerning general hierarchical decoding in quantum computing.

[0055] This patent document contains many details, which should be interpreted not as limitations on the scope of any subject matter or claimed, but rather as descriptions of features that may be specific to particular embodiments of a particular technique. Certain features described in this patent document in the context of a separate embodiment may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any preferred secondary combination in multiple embodiments. Furthermore, features described above as acting in a combination, and even initially claimed as such, may, in some cases, be removed from the claimed combination, and the claimed combination may be subject to secondary combinations or variations of secondary combinations.

[0056] Only a few embodiments of the disclosed technology and their implementations and examples are described, but enhancements or modifications of the disclosed embodiments and other embodiments may also be made based on those described and illustrated in this patent document.

Claims

1. A system capable of information processing based on both quantum computing, which uses different quantum states of qubits, and classical digital computing, which uses a digital processor including one or more graphics processing unit (GPU) processors, wherein the system is A cryogenic holding device system structured to include different cryogenic stages that are operable to provide lower and higher cryogenic temperatures, A quantum computing module enclosed by the cryogenic holding device system at the aforementioned low cryogenic temperature, wherein the quantum computing module is structured to include different qubit circuits that exhibit different quantum states and perform quantum computing operations, A qubit management circuit module enclosed by the low-temperature holding device system, the qubit management circuit module includes a qubit control circuit located adjacent to the quantum computing module and directly sending control signals for controlling the qubit circuits of the quantum computing module, and a qubit readout circuit that interacts with the qubit circuits and outputs readout signals from the qubit circuits indicating the quantum state of the qubit circuits, A hierarchical circuit module enclosed by the cryogenic holding system at the above-mentioned higher cryogenic temperatures, wherein the hierarchical circuit module is structured to communicate with the qubit management circuit module in relation to the control signals and read signals, and the hierarchical circuit module is structured to include a hierarchical quantum error correction decoding and quantum-classical hybrid co-processing circuit module that exhibits increasing processing latency and increasing decoding complexity levels along the direction of the different cryogenic stages as the different higher cryogenic temperatures increase, A graphics processing unit (GPU) overlay module, the GPU overlay module comprising one or more graphics processing unit (GPU) processors coupled to communicate with a final hierarchical circuit module enclosed by a cryogenic holding system at the highest cryogenic temperature, and a decoding module, the GPU overlay module configured to perform quantum error correction decoding and quantum classical hybrid co-processing and GPU processing operations based on quantum error correction decoding operations performed by the hierarchical circuit module enclosed by the cryogenic holding system. A system that includes these features.

2. The system according to claim 1, wherein the GPU overlay module is located outside the cryogenic holding device system.

3. The system according to claim 1, wherein the GPU overlay module includes a portion that is enclosed inside the cryogenic holding device system.

4. The system according to claim 1, wherein the GPU overlay module includes a portion enclosed inside the cryogenic holding device system and another portion located outside the cryogenic holding device system.

5. The system according to claim 1, wherein the GPU overlay module is configured to provide GPU optimization functions associated with a neural network.

6. The system according to claim 1, wherein the GPU overlay module is configured to provide GPU optimization functionality associated with the tensor network.

7. The system according to claim 1, wherein the GPU overlay module is configured to provide GPU optimization functionality.

8. The system according to claim 1, wherein the GPU overlay module is configured to provide GPU optimization functions associated with complex matrix multiplication operations.

9. The system according to claim 1, wherein the GPU overlay module includes one or more GPU-optimized pre-decoders.

10. The system according to claim 1, wherein the GPU overlay module includes one or more GPU-optimized large-scale neural network or tensor network type decoders.

11. The system according to claim 1, wherein the GPU overlay module includes one or more GPU-optimized combination decoders.

12. The system according to claim 11, wherein the one or more GPU-optimized combination decoders include a Union Find or a minimum-weighted perfect match decoder.

13. The system according to claim 1, wherein the GPU overlay module includes one or more CPUs, FPGAs, or ASIC-optimized combination decoders, including Union Find or minimum-weighted perfect match decoders.

14. The system according to claim 1, wherein some of the hierarchical circuit modules sealed by the cryogenic holding device system at a temperature between the lower cryogenic temperature and the higher cryogenic temperature maximum temperature are configured to provide quantum error correction functions, including logic compilation, logic qubit encoding, logic Cliffford gate execution, magic state distillation, or T gates.

15. The quantum computing module includes a first integrated chip structured to support the qubit circuits, each qubit circuit being structured as a superconducting circuit at the low cryogenic temperatures, exhibiting different quantum states as a quantum mechanical system, interacting quantum mechanically with other qubit circuits via quantum entanglement, causing superposition or correlation of the different quantum states of the qubit circuits. The system according to claim 1, wherein the qubit management circuit module is supported by a second integrated chip, the second integrated chip engaging with the first integrated chip to form a multi-chip module for transferring control signals and read signals between the first integrated chip and the second integrated chip.

16. The system according to claim 1, further comprising one or more additional quantum computing modules sealed by the cryogenic holding device system at the low cryogenic temperature, each quantum computing module being structured to include a different qubit circuit that performs quantum computing operations.

17. A method for computing based on both quantum computing, which uses different quantum states of qubits, and classical digital computing, which uses a digital processor including one or more graphics processing unit (GPU) processors, wherein the method is This involves operating a quantum computing module containing different qubit circuits exhibiting different quantum states, and performing quantum computing operations. To generate a readout signal indicating the quantum state of the qubit circuit of the quantum computing module, In processing the readout signals of the qubit circuit of the quantum computing module, a hierarchical quantum error correction decoding and quantum-classical hybrid co-processing circuit module is operated which exhibits different processing latency and different decoding complexity levels. A graphics processing unit (GPU) overlay module is operated, which includes one or more graphics processing unit (GPU) processors coupled to communicate with the aforementioned hierarchical quantum error correction decoding and quantum classical hybrid co-processing circuit module, and a decoding module, and performs quantum error correction decoding and quantum classical hybrid co-processing and GPU processing operations based on the quantum error correction decoding operation performed by the hierarchical circuit module. Methods that include...

18. The method according to claim 17, further comprising operating the GPU overlay module to provide GPU optimization capabilities associated with a neural network.

19. The method according to claim 17, further comprising operating the GPU overlay module to provide GPU optimization capabilities associated with a tensor network.

20. The method according to claim 17, further comprising operating the GPU overlay module to provide GPU optimization capabilities associated with complex matrix multiplication operations.

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