Display panels and display devices

Abstract

This application discloses a display panel and a display device, and belongs to the field of display technology. The display panel includes a substrate, a plurality of pixel circuit groups, a plurality of first signal lines of a plurality of types, and a plurality of light-emitting units. The substrate has a first display area, the first display area includes a plurality of pixel circuit areas and a light-transmitting area, the plurality of pixel circuit groups are located in the pixel circuit areas, the pixel circuit groups include a plurality of pixel circuits, the minimum distance between adjacent pixel circuit groups is greater than the minimum distance between adjacent pixel circuits within a pixel circuit group, some of the plurality of first signal lines include metallic signal lines, the remaining types of first signal lines include transparent signal lines, and the orthographic projection of at least some of the plurality of light-emitting units onto the substrate overlaps with the orthographic projection of at least some of the line segments of the plurality of first signal lines onto the substrate. According to this application, via defects around the first display area are reduced, and the uniformity of the display panel is improved.

Claims

1. A display panel comprising a substrate board, a plurality of pixel circuit groups, a plurality of first signal lines of a plurality of types, and a plurality of light-emitting units, The substrate has a first display area, and the first display area includes a plurality of pixel circuit areas and a light-transmitting area. The plurality of pixel circuit groups are located in the plurality of pixel circuit regions, and each pixel circuit group includes a plurality of pixel circuits, and the minimum distance between adjacent pixel circuit groups is greater than the minimum distance between adjacent pixel circuits within the pixel circuit group. The plurality of first signal lines are connected to the plurality of pixel circuits, some of the plurality of first signal lines include metallic signal lines, the remaining types of first signal lines include transparent signal lines, and at least some of the line segments in the plurality of first signal lines are located in the light-transmitting region. The plurality of light-emitting units are located in the first display area, the plurality of pixel circuit groups are arranged to drive the light emission of the plurality of light-emitting units, and the orthographic projection of at least some of the plurality of light-emitting units onto the substrate substrate coincides with the orthographic projection onto the substrate substrate of at least some of the line segments of the plurality of types of first signal lines located in the light-transmitting area. Display panel.

2. At least a portion of the line segments in the metal signal line are located in the light-transmitting region, and the orthographic projection of at least a portion of the light-emitting units among the plurality of light-emitting units onto the substrate substrate coincides with the orthographic projection of at least a portion of the line segments in the metal signal line onto the substrate substrate. The display panel according to claim 1.

3. At least a portion of the line segments in the transparent signal line are located in the light-transmitting region, and the orthographic projection of at least a portion of the light-emitting units among the plurality of light-emitting units onto the substrate substrate coincides with the orthographic projection of at least a portion of the line segments in the transparent signal line onto the substrate substrate. The display panel according to claim 1.

4. The plurality of pixel circuit groups includes a plurality of first pixel circuit groups and a plurality of second pixel circuit groups, the plurality of first pixel circuit groups exhibiting a plurality of row arrangements, the plurality of second pixel circuit groups exhibiting a plurality of row arrangements, one row of second pixel circuit groups is placed between any two adjacent rows of first pixel circuit groups, and in any one row of first pixel circuit groups and one row of second pixel circuit groups adjacent to the arbitrary one row of first pixel circuit groups, the position of the spacing region between any two adjacent first pixel circuit groups corresponds to the position of one second pixel circuit group. The display panel according to claim 1.

5. Each pixel circuit group includes at least one pixel circuit unit, the pixel circuit unit includes one first pixel circuit, one second pixel circuit, and one third pixel circuit, the second pixel circuit is located between the first pixel circuit and the third pixel circuit, The light-emitting unit includes one first light-emitting element, two second light-emitting elements, and one third light-emitting element. The first light-emitting element is connected to the first pixel circuit, and the orthographic projection of the anode of the first light-emitting element onto the substrate substrate overlaps at least partially with the orthographic projection of the group of pixel circuits on which the first pixel circuit is located onto the substrate substrate. Both of the second light-emitting elements are connected to the second pixel circuit, and the orthographic projections of the anodes of the two second light-emitting elements onto the substrate are located on opposite sides of the orthographic projection of the second pixel circuit onto the substrate. The third light-emitting element is connected to the third pixel circuit, and the orthographic projection of the anode of the third light-emitting element onto the substrate substrate at least partially overlaps with the orthographic projection of the group of pixel circuits on which the third pixel circuit is located onto the substrate substrate. The display panel according to claim 4.

6. The orthographic projection of the anode of the first light-emitting element onto the substrate is located within the orthographic projection of the group of pixel circuits on the substrate in which the first pixel circuit is located. The orthographic projection of the anodes of the two second light-emitting elements onto the substrate does not overlap with the orthographic projection of the group of pixel circuits on which the second pixel circuits are located onto the substrate. The orthographic projection of the anode of the third light-emitting element onto the substrate is located within the orthographic projection of the group of pixel circuits on the substrate in which the third pixel circuit is located. The display panel according to claim 5.

7. The first light-emitting element, the second light-emitting element, and the third light-emitting element are a blue light-emitting element, a green light-emitting element, and a red light-emitting element, respectively, and the first pixel circuit, the second pixel circuit, and the third pixel circuit of the pixel circuit unit of the first pixel circuit group are a pixel circuit that drives the blue light-emitting element, a pixel circuit that drives the green light-emitting element, and a pixel circuit that drives the red light-emitting element, respectively. The first pixel circuit, second pixel circuit, and third pixel circuit of the pixel circuit unit of the second pixel circuit group are, respectively, a pixel circuit that drives the blue light-emitting element, a pixel circuit that drives the green light-emitting element, and a pixel circuit that drives the red light-emitting element, or, The first pixel circuit, second pixel circuit, and third pixel circuit of the pixel circuit unit of the second pixel circuit group are, respectively, a pixel circuit for driving the red light-emitting element, a pixel circuit for driving the green light-emitting element, and a pixel circuit for driving the blue light-emitting element. The display panel according to claim 5.

8. The metal signal wire in the first signal line includes a first part, a second part, and a third part, the third part being located between the first part and the second part, and both ends of the third part being connected to the first part and the second part, respectively. The first and second portions are each connected to the pixel circuits in two adjacent groups of pixel circuits, and the orthogonal projection of the third portion onto the substrate substrate overlaps at least partially with the orthogonal projection of the anode of the second light-emitting element onto the substrate substrate. The display panel according to claim 5.

9. The orthographic projection of the anode of one second light-emitting element onto the substrate substrate each at least partially overlaps with the orthographic projection of the third portion of at least two of the metal signal lines onto the substrate substrate, and the overlapping portions of the third portion of at least two of the metal signal lines and the anode of the second light-emitting element are symmetrically positioned based on the axis of symmetry of the anode of the second light-emitting element. The display panel according to claim 8.

10. The anodes of the first light-emitting element, the second light-emitting element, and the third light-emitting element are all circular in shape. The display panel according to claim 5.

11. The anodes of the two second light-emitting elements are connected by a first connecting line, and the first connecting line is connected to the second pixel circuit. The display panel according to claim 5.

12. The first signal line type includes a first reset signal line, a second reset signal line, a first reset power line, a second reset power line, a third reset power line, a first gate signal line, a second gate signal line, a data signal line, a light emission control line, and a drive power line. The pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a storage capacitor. The gate of the first transistor is connected to the first reset signal line, the first pole of the first transistor is connected to the first reset power line, and the second pole of the first transistor is connected to the first node. The gate of the second transistor is connected to the first gate signal line, the first pole of the second transistor is connected to the first node, and the second pole of the second transistor is connected to the second node. The gate of the third transistor is connected to the second node, the first pole of the third transistor is connected to the first node, and the second pole of the third transistor is connected to the third node. The gate of the fourth transistor is connected to the second gate signal line, the first pole of the fourth transistor is connected to the data signal line, and the second pole of the fourth transistor is connected to the third node. The gate of the fifth transistor is connected to the light emission control line, the first pole of the fifth transistor is connected to the third node, and the second pole of the fifth transistor is connected to the drive power line. The gate of the sixth transistor is connected to the light emission control line, the first pole of the sixth transistor is connected to the first node, and the second pole of the sixth transistor is connected to the anode of the light-emitting element. The gate of the seventh transistor is connected to the second reset signal line, the first pole of the seventh transistor is connected to the second reset power line, and the second pole of the seventh transistor is connected to the anode of the light-emitting element. The gate of the eighth transistor is connected to the second reset signal line, the first pole of the eighth transistor is connected to the third reset power line, and the second pole of the eighth transistor is connected to the third node. The ends of the storage capacitor are connected to the drive power line and the second node, respectively. The display panel according to claim 5.

13. The second transistor is an N-type transistor, and the first, third, fourth, fifth, sixth, seventh, and eighth transistors are all P-type transistors. The display panel according to claim 12.

14. The second transistor is an oxide thin-film transistor, and the first, third, fourth, fifth, sixth, seventh, and eighth transistors are all low-temperature polysilicon thin-film transistors. The display panel according to claim 13.

15. Each pixel circuit unit corresponds to two first reset power lines, three second reset power lines, and one third reset power line, respectively. With respect to each of the aforementioned pixel circuit units, the orthographic projections of the two first reset power lines onto the substrate board overlap at least partially with the orthographic projection of the first pixel circuit onto the substrate board and the orthographic projection of the third pixel circuit onto the substrate board, respectively, and the two first reset power lines are connected to the first pixel circuit and the third pixel circuit, respectively, and the two first reset power lines are connected by a second connecting line, and the second connecting line is connected to the second pixel circuit, and the direction of extension of the second connecting line is perpendicular to the direction of extension of the first reset power lines. The orthographic projections of the three second reset power lines onto the substrate board each overlap at least partially with the orthographic projection of the first pixel circuit onto the substrate board, the orthographic projection of the second pixel circuit onto the substrate board, and the orthographic projection of the third pixel circuit onto the substrate board, and the three second reset power lines are connected to the first pixel circuit, the second pixel circuit, and the third pixel circuit, respectively. The orthographic projection of the third reset power line onto the substrate board at least partially overlaps with the orthographic projection of the second pixel circuit onto the substrate board, and the third reset power line is connected to the second pixel circuit, and the third reset power line is connected to the first pixel circuit by a third connecting line, and is connected to the third pixel circuit, and the direction of extension of the third connecting line is perpendicular to the direction of extension of the third reset power line. The display panel according to claim 12.

16. The three second reset power lines are connected by a fourth connecting line, and the direction of extension of the fourth connecting line is perpendicular to the direction of extension of the second reset power lines. The display panel according to claim 15.

17. In the arrangement direction of the first pixel circuit, the second pixel circuit, and the third pixel circuit, the orientation of the first pixel circuit and the orientation of the second pixel circuit are arranged opposite each other. Each pixel circuit unit corresponds to two drive power lines. For each of the aforementioned pixel circuit units, the orthographic projection of one drive power line onto the substrate board at least partially overlaps with the orthographic projection of the first pixel circuit onto the substrate board and the orthographic projection of the second pixel circuit onto the substrate board, and is connected to the first pixel circuit and the second pixel circuit, respectively. The orthographic projection of another drive power line onto the substrate board at least partially overlaps with the orthographic projection of the third pixel circuit onto the substrate board and is connected to the third pixel circuit. The display panel according to claim 12.

18. The two drive power lines are connected by a fifth connecting line, and the direction of extension of the fifth connecting line is perpendicular to the direction of extension of the drive power lines. The display panel according to claim 12.

19. The first signal line type includes at least two of the following: gate signal line, light emission control line, first reset signal line, second reset signal line, data signal line, reset power line, and drive power line. The display panel according to claim 1.

20. The aforementioned first signal line of some type includes at least one of a data signal line, a gate signal line, and a light emission control signal line. The display panel according to claim 1.

21. Each of the aforementioned types of first signal lines is a metal signal line. The display panel according to claim 1.

22. Each of the aforementioned types of first signal lines includes a metal signal line and a transparent signal line connected in parallel. The display panel according to claim 1.

23. The substrate further includes a second display area, the second display area being adjacent to the first display area, The display panel further includes a plurality of types of second signal lines located in the second display area, For each type of first reset signal line, second reset signal line, first reset power line, second reset power line, third reset power line, first gate signal line, second gate signal line, data signal line, light emission control line, and drive power line, at least one end of each second signal line of the aforementioned type is connected to one first signal line of the aforementioned type, the second signal line is a metal signal line, and the width of the metal signal line included in the first signal line is smaller than the width of the second signal line. The display panel according to claim 22.

24. The aforementioned metal signal line is located in the gate layer or the source / drain layer. The display panel according to claim 1.

25. A display panel comprising a substrate board, a plurality of pixel circuit groups, a plurality of first signal lines, and a plurality of light-emitting units, The substrate has a first display area, and the first display area includes a plurality of pixel circuit areas and a light-transmitting area. The plurality of pixel circuit groups are located in the plurality of pixel circuit regions, and each pixel circuit group includes a first number of pixel circuits arranged along a first direction, and the minimum distance between adjacent pixel circuit groups is greater than the minimum distance between adjacent pixel circuits within the pixel circuit group. The plurality of first signal lines extend along a second direction, the first direction intersects the second direction, at least one of the plurality of pixel circuit groups is connected to a second number of first signal lines, the second number of first signal lines are electrically connected by connecting lines, for each pixel circuit group in the at least one pixel circuit group, each of the second number of first signal lines is connected to at least one pixel circuit in the pixel circuit group, at least a portion of the line segments of the first signal lines are located in the light-transmitting region, the connecting lines are located in the pixel circuit region, and the second number is less than or equal to the first number. The plurality of light-emitting units are located in the first display area, the plurality of pixel circuit groups are arranged to drive the light emission of the plurality of light-emitting units, and the orthographic projection of at least some of the plurality of light-emitting units onto the substrate substrate coincides with the orthographic projection of at least some of the line segments of the first signal line onto the substrate substrate. Display panel.

26. The plurality of pixel circuit groups includes a plurality of first pixel circuit groups and a plurality of second pixel circuit groups, the plurality of first pixel circuit groups exhibiting a plurality of row arrangements, the plurality of second pixel circuit groups exhibiting a plurality of row arrangements, one row of second pixel circuit groups is placed between any two adjacent rows of first pixel circuit groups, and in any one row of first pixel circuit groups and one row of second pixel circuit groups adjacent to the arbitrary one row of first pixel circuit groups, the position of the spacing region between any two adjacent first pixel circuit groups corresponds to the position of one second pixel circuit group. The display panel according to claim 25.

27. Each pixel circuit group includes at least one pixel circuit unit, the pixel circuit unit includes one first pixel circuit, one second pixel circuit, and one third pixel circuit, the second pixel circuit is located between the first pixel circuit and the third pixel circuit, The light-emitting unit includes one first light-emitting element, two second light-emitting elements, and one third light-emitting element. The first light-emitting element is connected to the first pixel circuit, and the orthographic projection of the anode of the first light-emitting element onto the substrate substrate overlaps at least partially with the orthographic projection of the group of pixel circuits on which the first pixel circuit is located onto the substrate substrate. Both of the second light-emitting elements are connected to the second pixel circuit, and the orthographic projections of the anodes of the two second light-emitting elements onto the substrate are located on opposite sides of the orthographic projection of the second pixel circuit onto the substrate. The third light-emitting element is connected to the third pixel circuit, and the orthographic projection of the anode of the third light-emitting element onto the substrate substrate at least partially overlaps with the orthographic projection of the group of pixel circuits on which the third pixel circuit is located onto the substrate substrate. The display panel according to claim 26.

28. The first signal line includes a first reset power line, the connection line includes a second connection line, each pixel circuit unit in the pixel circuit group is connected to two first reset power lines, and the two first reset power lines are electrically connected by the second connection line. With respect to each of the aforementioned pixel circuit units, the orthographic projections of the two first reset power lines onto the substrate board overlap at least partially with the orthographic projection of the first pixel circuit onto the substrate board and the orthographic projection of the third pixel circuit onto the substrate board, respectively, and the two first reset power lines are connected to the first pixel circuit and the third pixel circuit, respectively. The second connecting line is connected to the second pixel circuit. The display panel according to claim 27.

29. The first signal line includes a second reset power line, the connection line includes a fourth connection line, each pixel circuit unit in the pixel circuit group is connected to three second reset power lines, and the three second reset power lines are electrically connected by the fourth connection line. For each of the aforementioned pixel circuit units, the orthographic projections of the three second reset power lines onto the substrate board overlap at least partially with the orthographic projections of the first pixel circuit, the second pixel circuit, and the third pixel circuit, respectively, and the three second reset power lines are connected to the first pixel circuit, the second pixel circuit, and the third pixel circuit, respectively. The display panel according to claim 27.

30. The first signal line includes a third reset power line, the connection line includes a third connection line, each pixel circuit unit in the pixel circuit group is connected to one third reset power line, and the third reset power line is connected to the third connection line. With respect to each of the aforementioned pixel circuit units, the orthographic projection of the third reset power line onto the substrate board overlaps at least partially with the orthographic projection of the second pixel circuit onto the substrate board, and the third reset power line is connected to the second pixel circuit. The third connection line is connected to the first pixel circuit and the third pixel circuit. The display panel according to claim 27.

31. The first signal line includes a drive power line, the connection line includes a fifth connection line, each pixel circuit unit in the pixel circuit group is connected to two drive power lines, and the two drive power lines are electrically connected by the fifth connection line. For each of the aforementioned pixel circuit units, the orthographic projection of one drive power line onto the substrate board at least partially overlaps with the orthographic projection of the first pixel circuit onto the substrate board and the orthographic projection of the second pixel circuit onto the substrate board, and is connected to the first pixel circuit and the second pixel circuit, respectively; and the orthographic projection of another drive power line onto the substrate board at least partially overlaps with the orthographic projection of the third pixel circuit onto the substrate board and is connected to the third pixel circuit. The display panel according to claim 27.

32. The optical sensor and the display panel according to any one of claims 1 to 31 are included. The orthographic projection of the optical sensor onto the display panel overlaps at least partially with the first display area on the display panel. Display device.

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