Semiconductor structure in three-dimensional memory devices

Abstract

Methods, devices, and systems are provided for managing the layout of semiconductor structures in a three-dimensional (3D) memory device. In one embodiment, the memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first memory array in a first array region, a second memory array in a second array region, and word lines coupled to memory cells in the first memory array and memory cells in the second memory array. The second semiconductor structure includes a row decoder. The first and second semiconductor structures are stacked along a second direction perpendicular to a first direction. At least a portion of the row decoder overlaps with at least one of the first memory array in the first array region and the second memory array in the second array region in a plan view perpendicular to the second direction.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices such as 3D memory devices.

Background Art

[0002] Semiconductor devices, such as memory devices, can have various structures to increase the density of memory cells and wires on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuits to facilitate the operation of the memory array.

Summary of the Invention

[0003] The present disclosure describes the management of the layout of semiconductor structures in three-dimensional (3D) memory devices.

[0004] One aspect of the present disclosure features a memory device including a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first memory array in a first array region, a second memory array in a second array region, a contact structure in a connection region between the first array region and the second array region along a first direction, and word lines coupled to memory cells in the first memory array and memory cells in the second memory array. The second semiconductor structure includes a row decoder. The first semiconductor structure and the second semiconductor structure are stacked along a second direction perpendicular to the first direction. At least a portion of the row decoder overlaps at least one of the first memory array in the first array region and the second memory array in the second array region in a plan view perpendicular to the second direction.

[0005] In some embodiments, the second semiconductor structure further includes string drivers. One of the string drivers is coupled to a corresponding word line via a contact structure in a connection region. The string driver is also coupled to a corresponding row decoder. At least a first portion of the string driver overlaps, in plan view, with at least one of a first memory array in a first array region and a second memory array in a second array region.

[0006] In some embodiments, the second portion of the string driver overlaps with the contact structure within the connection region in a plan view.

[0007] In some embodiments, the row decoder is located adjacent to the string driver along a first direction.

[0008] In some embodiments, the row decoder is located on one side of the string driver.

[0009] In some embodiments, the row decoder includes a first group of row decoders and a second group of row decoders. The first group of row decoders is located on the first side of the string driver, and the second group of row decoders is located on the second side of the string driver.

[0010] In some embodiments, the first semiconductor structure includes N memory blocks numbered from 0 to N-1. The first group of row decoders includes a first row decoder coupled to a first string driver coupled to a word line in the first memory block associated with odd numbers. The second group of row decoders includes a second row decoder coupled to a second string driver coupled to a word line in the second memory block associated with even numbers.

[0011] In some embodiments, the first string driver and the second string driver are located between the first row decoder and the second row decoder along the first direction, and odd and even numbers are adjacent integers.

[0012] In some embodiments, the second semiconductor structure further includes a first group of page buffers and a second group of page buffers. The row decoder and string driver are located between the first group of page buffers and the second group of page buffers along a first direction.

[0013] In some embodiments, the first semiconductor structure further includes bit lines coupled to memory cells in a first memory array. The bit lines are coupled to corresponding page buffers in a first group of page buffers. At least a first portion of one of the bit lines is spaced apart from the corresponding page buffer along a first direction in a plan view.

[0014] In some embodiments, one of the bit lines is coupled to a corresponding page buffer via a first connection line in a first semiconductor structure and a second connection line in a second semiconductor structure. The second connection line comprises a first portion overlapping with at least one of a row decoder or a string driver, a second portion overlapping with a first group of page buffers, and a third portion connecting the ends of the first and second portions.

[0015] In some embodiments, the first semiconductor structure includes a first junction layer comprising a first conductive structure insulated by a first insulating material. The second semiconductor structure includes a second junction layer comprising a second conductive structure insulated by a second insulating material. The first and second semiconductor structures are joined to each other with the first conductive structure in contact with the second conductive structure.

[0016] In some embodiments, the memory device includes a NAND memory device.

[0017] Another aspect of the present disclosure features a method for forming a memory device, comprising the steps of forming a first semiconductor structure and forming a second semiconductor structure. The first semiconductor structure includes a first memory array in a first array region, a second memory array in a second array region, a contact structure in a connection region between the first and second array regions along a first direction, and word lines coupled to memory cells in the first memory array and memory cells in the second memory array. The second semiconductor structure includes a row decoder. The method further includes the step of stacking the first semiconductor structure and the second semiconductor structure along a second direction perpendicular to the first direction. At least a portion of the row decoder overlaps with at least one of the first memory array in the first array region and the second memory array in the second array region in a plan view perpendicular to the second direction.

[0018] In some embodiments, the second semiconductor structure further includes string drivers. One of the string drivers is coupled to a corresponding word line via a contact structure in a connection region. The string driver is also coupled to a corresponding row decoder. At least a first portion of the string driver overlaps, in plan view, with at least one of a first memory array in a first array region and a second memory array in a second array region.

[0019] In some embodiments, the second portion of the string driver overlaps with the contact structure within the connection region in a plan view.

[0020] In some embodiments, the row decoder includes a first group of row decoders and a second group of row decoders. The first group of row decoders is located on the first side of the string driver, and the second group of row decoders is located on the second side of the string driver.

[0021] In some embodiments, the first semiconductor structure includes N memory blocks numbered from 0 to N-1. The first group of row decoders includes a first row decoder coupled to a first string driver coupled to a word line in the first memory block associated with odd numbers. The second group of row decoders includes a second row decoder coupled to a second string driver coupled to a word line in the second memory block associated with even numbers.

[0022] In some embodiments, the first string driver and the second string driver are located between the first row decoder and the second row decoder along the first direction, and odd and even numbers are adjacent integers.

[0023] In some embodiments, the second semiconductor structure further includes a first group of page buffers and a second group of page buffers. The row decoder and string driver are located between the first group of page buffers and the second group of page buffers along a first direction. The first semiconductor structure further includes bit lines coupled to memory cells in a first memory array. The bit lines are coupled to the corresponding page buffers of the first group of page buffers. At least a portion of the bit lines are spaced apart from the corresponding page buffers along a first direction in a plan view.

[0024] Another aspect of the present disclosure features a system including a memory device and a controller coupled to the memory device and configured to control the memory device. The memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first memory array in a first array region, a second memory array in a second array region, a contact structure in a connection region between the first array region and the second array region along a first direction, and word lines coupled to memory cells in the first memory array and memory cells in the second memory array. The second semiconductor structure includes a row decoder. The first semiconductor structure and the second semiconductor structure are stacked along a second direction perpendicular to the first direction. At least a portion of the row decoder overlaps at least one of the first memory array in the first array region and the second memory array in the second array region in a plan view perpendicular to the second direction.

[0025] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification text, the drawings, and the claims.

Brief Description of the Drawings

[0026] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate aspects of the disclosure and, together with the specification text, further serve to explain the principles of the disclosure so that one skilled in the art can make and use the disclosure. [Figure 1A] A schematic cross-sectional view of an example of a 3D memory device is shown. [Figure 1B] A schematic cross-sectional view of an example of a 3D memory device is shown. [Figure 2] An example of a schematic circuit diagram of an example of a memory device including peripheral circuits is shown. [Figure 3] Examples of peripheral circuits are shown. [Figure 4] A schematic circuit diagram of an example of the word line driver and page buffer of FIG. 3 is shown. [Figure 5] A top view of an example of the first semiconductor structure is shown. [Figure 6A] A plan view of an example of a second semiconductor structure is shown. [Figure 6B] Figure 6A shows a plan view of an example of a 3D memory device having the second semiconductor structure. [Figure 7A] A plan view of another example of the second semiconductor structure is shown. [Figure 7B] Figure 7A shows a plan view of an example of a 3D memory device having the second semiconductor structure. [Figure 8A] A plan view of another example of the second semiconductor structure is shown. [Figure 8B] Figure 8A shows a plan view of an example of a 3D memory device having the second semiconductor structure. [Figure 9] This is a flowchart illustrating an example of the process for forming a memory device. [Figure 10] A block diagram of an example system having one or more memory devices is shown. [Figure 11A] A diagram of a memory card with an example of a memory device is shown. [Figure 11B] A diagram of a solid-state drive (SSD) with an example of a memory device is shown.

[0027] Similar reference numbers and symbols in various drawings indicate similar elements. It should also be understood that the various typical embodiments shown in the drawings are merely illustrative and not necessarily drawn to scale. [Modes for carrying out the invention]

[0028] As the memory cell density of a three-dimensional (3D) memory device increases, the 3D memory device may have an increased number of string drivers, which can occupy a larger area on the chip. The 3D memory device may be a junction chip comprising a first semiconductor structure and a second semiconductor structure, which are separately formed on different substrates and then stacked together to form a junction chip. The first semiconductor structure may include a first memory array in a first array region, a second memory array in a second array region, and a connection region located between the first and second array regions. The second semiconductor structure may include peripheral circuits, including a first group of page buffers, a second group of page buffers, string drivers, and row decoders.

[0029] Embodiments of this disclosure provide techniques for managing the layout of semiconductor structures (e.g., a first semiconductor structure and a second semiconductor structure) within a 3D memory device. For example, to balance chip size and program speed, a string driver and a row decoder may be located between a first group of page buffers and a second group of page buffers within a second semiconductor structure of the 3D memory device.

[0030] In some cases, the string driver and row decoder are located outside the first and second memory arrays. That is, in a plan view along the stacking direction, the string driver and row decoder of the second semiconductor structure do not overlap with the first or second memory array of the first semiconductor structure. At least one of the string driver and row decoder overlaps with the connection region of the first semiconductor structure. Because the string driver and row decoder occupy a larger area than the connection region, some areas within the first semiconductor structure may be wasted due to the potential to accommodate more memory cells.

[0031] With advances in CMOS technology, the widths (e.g., length along the word line direction) of the first and second groups of page buffers can be reduced. In some embodiments, the string driver or row decoder is located below the first or second memory array. That is, in a plan view along the stacking direction, the string driver or row decoder of the second semiconductor structure overlaps at least partially with the first or second memory array of the first semiconductor structure.

[0032] In some embodiments, the row decoders are positioned symmetrically on either side of the string driver. For example, row decoders associated with even-numbered memory blocks are located on the first side of the string driver, and row decoders associated with odd-numbered memory blocks are located on the second side of the string driver.

[0033] Embodiments of this disclosure can provide one or more of the following technical advantages. For example, all areas within the first semiconductor structure, excluding the connection area, can be used to accommodate memory cells, thereby increasing the memory cell density of the 3D memory device. Furthermore, by symmetrically positioning the row decoders on both sides of the string driver, fewer metal layers are used to connect the row decoders to the string driver, thereby leaving more metal layers to connect the bit lines in the first semiconductor structure to the corresponding page buffers in the second semiconductor structure. In addition, by employing a layout structure in which the string driver or row decoder is located below the memory array, the size of the first and second semiconductor structures can be reduced, thereby reducing the chip size of the 3D memory device.

[0034] This technology can be applied, in particular, to various types of semiconductor devices, or non-volatile memory (NVM) devices, such as NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) such as PCRAM, spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), or volatile memory devices such as DRAM memory devices. This technology can also be applied to charge trap-based memory devices, such as silicon oxide nitride (SONOS) memory devices, and floating gate-based memory devices. This technology can be applied to three-dimensional (3D) memory devices. This technology can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices such as 2-level cell devices, TLC (triple-level cell) devices, QLC (quad-level cell) devices, or PLC (penta-level cell) devices. In addition to or instead of the above, this technology can be applied to various types of devices and systems, including, in particular, secure digital (SD) cards, embedded multimedia cards (eMMC), or solid-state drives (SSDs), and embedded systems.

[0035] Figure 1A shows a schematic cross-sectional view of an example of a 3D memory device 100 according to one or more embodiments of the present disclosure. The 3D memory device 100 corresponds to an example of a bonded chip. The components of the 3D memory device 100 (e.g., memory arrays and peripheral circuits) can be formed separately on different substrates and then bonded together to form a bonded chip. The 3D memory device 100 may include a first semiconductor structure 102 which includes an array of memory cells (memory array). In some embodiments, the memory array includes an array of NAND flash memory cells. For ease of explanation, a NAND flash memory array may be used as an example to illustrate the memory array in this disclosure. However, it should be understood that the memory array is not limited to a NAND flash memory array and may include any other suitable type of memory array, such as, to give some examples, a dynamic random access memory (DRAM) cell array, a static random access memory (SRAM) cell array, a NOR flash memory array, a phase-change memory (PCM) cell array, a resistive memory array, a magnetic memory array, a spin-transfer torque (STT) memory array, or any combination thereof.

[0036] The first semiconductor structure 102 can be a NAND flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings and / or an array of two-dimensional (2D) NAND memory cells. The NAND memory cells can be organized into pages or fingers, which are then organized into blocks in which each NAND memory cell is electrically connected to a separate line called a bit line (BL). All cells with the same vertical position within a NAND memory block may be electrically connected via a control gate by a word line (WL). In some embodiments, a plane contains a certain number of blocks electrically connected via the same bit line. The first semiconductor structure 102 may contain one or more planes, and the peripheral circuits necessary to perform all read / program (write) / erase operations may be included in the second semiconductor structure 104.

[0037] In some embodiments, an array of NAND memory cells is an array of 2D NAND memory cells, each containing a floating-gate transistor. According to some embodiments, an array of 2D NAND memory cells includes a plurality of 2D NAND memory strings, each of which contains a plurality of memory cells (e.g., 32 to 128 memory cells) connected in series (similar to NAND gates) and two selection transistors. According to some embodiments, each 2D NAND memory string is located in the same plane (in 2D) on the substrate. In some embodiments, an array of NAND memory cells is an array of 3D NAND memory strings, each of which extends vertically (in 3D) above the substrate through a stack structure, e.g., a memory stack. Depending on the 3D NAND technology (e.g., the number of layers / hierarchies in the memory stack), a 3D NAND memory string generally contains 32 to 256 NAND memory cells, each containing a floating-gate transistor or a charge trap transistor.

[0038] As shown in Figure 1A, the 3D memory device 100 may also include a second semiconductor structure 104 which includes peripheral circuits for the memory array of the first semiconductor structure 102. The peripheral circuits (also known as control and sensing circuits) may include any suitable digital, analog, and / or mixed-signal circuits used to facilitate the operation of the memory array. For example, the peripheral circuits may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), I / O circuits, charge pumps, voltage sources or voltage generators, current or voltage references, any part of the aforementioned functional circuits (e.g., subcircuits), or any active or passive components of the circuits (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits in the second semiconductor structure 104 may use CMOS technology, which can be implemented using, for example, logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, etc.). As described in detail above and below, in accordance with the scope of this disclosure, the technology node used to manufacture peripheral circuits within the second semiconductor structure 104 is greater than 22nm in order to reduce leakage current, maintain a specific voltage level (e.g., 1.2V or higher), and reduce costs.

[0039] As shown in Figure 1A, the 3D memory device 100 further includes a junction interface 106 perpendicularly (e.g., along the Z direction) between the first semiconductor structure 102 and the second semiconductor structure 104. In some embodiments, the first and second semiconductor structures 102 and 104 can be manufactured separately (in some embodiments, in parallel) such that the thermal history of manufacturing one of the first and second semiconductor structures 102 and 104 does not restrict the process of manufacturing the other of the first and second semiconductor structures 102 and 104. Furthermore, a number of interconnections can be formed via the junction interface 106 to provide direct short-range (e.g., micron level) electrical connections between the first semiconductor structure 102 and the second semiconductor structure 104, in contrast to long-range (e.g., millimeter or centimeter level) interchip data buses on circuit boards such as printed circuit boards (PCBs), thereby eliminating chip interface delay and achieving high-speed I / O throughput with reduced power consumption. Data transfer between the memory array in the first semiconductor structure 102 and the peripheral circuit in the second semiconductor structure 104 can be performed via interconnects that cross the junction interface 106. By vertically integrating the first and second semiconductor structures 102 and 104, the chip size can be reduced and the memory cell density can be increased.

[0040] It is understood that the relative positions of the stacked first and second semiconductor structures 102, 104 are not limited. Figure 1B shows a schematic cross-sectional view of an example of a 3D memory device 101 according to one or more embodiments of the present disclosure. Unlike the 3D memory device 100 of Figure 1A, in which the second semiconductor structure 104, including peripheral circuits, is above the first semiconductor structure 102, including the memory array, in the 3D memory device 101 of Figure 1B, the first semiconductor structure 102, including the memory array, is above the second semiconductor structure 104, including the peripheral circuits. Nevertheless, according to some embodiments, a junction interface 106 is formed perpendicularly between the first semiconductor structure 102 and the second semiconductor structure 104 in the 3D memory device 101, and the first semiconductor structure 102 and the second semiconductor structure 104 are perpendicularly coupled via a junction (e.g., a hybrid junction). Hybrid junctions, also known as "metal / dielectric hybrid junctions," are direct bonding techniques (e.g., forming a junction between surfaces without using an intermediate layer such as solder or adhesive) and can simultaneously provide metal-metal (e.g., Cu-Cu) and dielectric-dielectric (e.g., SiO2-SiO2) junctions. Data transfer between a memory array in a first semiconductor structure 102 and peripheral circuits in a second semiconductor structure 104 can be performed via interconnects crossing the junction interface 106. In some embodiments, the junction interface 106 may include a first junction layer in the first semiconductor structure 102 and a second junction layer in the second semiconductor structure 104. The first junction layer may include a first conductive structure insulated by a first insulating material (e.g., SiO2 or other dielectric material). The second junction layer may include a second conductive structure insulated by a second insulating material (e.g., SiO2 or other dielectric material). The first and second insulating materials may be the same or different, for example, according to actual manufacturing needs. Each of the second conductive structures can correspond to one of the first conductive structures. In this way, when the first semiconductor structure 102 and the second semiconductor structure 104 are stacked on top of each other, the second conductive structures can come into contact with the corresponding first conductive structures to form a conductive junction (e.g., a metal-to-metal junction) via the junction interface 106.

[0041] Figure 2 shows an example schematic circuit diagram of an example of a memory device 200 including peripheral circuits (e.g., 3D memory device 100 in Figure 1A, 3D memory device 101 in Figure 1B) according to one or more embodiments of the present disclosure. The memory device 200 may include a memory array 201 and peripheral circuits 202 coupled to the memory array 201. The memory array 201 may be a NAND flash memory array in which memory cells 206 are provided in the form of an array of NAND memory strings 208, each extending vertically over a substrate (not shown), such as a semiconductor substrate such as a wafer. In some embodiments, each NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically (e.g., in the Z direction). Each memory cell 206 may hold a continuous analog value, such as voltage or charge, which depends on the number of electrons trapped in the memory layer of the memory cell 206. The logical state (i.e., data) of each memory cell 206 in block 204 may be determined based on the threshold voltage of the memory cell 206. Each memory cell 206 can be a floating-gate type memory cell including a floating-gate transistor, or a charge-trap type memory cell including a charge-trap transistor.

[0042] In some embodiments, each memory cell 206 is a single-level cell (SLC) with two possible memory states capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 206 is a multi-level cell (MLC) capable of storing more than one bit of data in three or more memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to support a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erase state to one of three possible programming levels by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0043] As shown in Figure 2, each NAND memory string 208 may include a source selection gate (SSG) transistor 210 at its source end and a drain selection gate (DSG) transistor 212 at its drain end. The SSG 210 and DSG 212 can be configured to activate the selected NAND memory string 208 (a column of the array) during read and program operations. In some embodiments, the sources of NAND memory strings 208 within the same block 204 are coupled via the same source line (SL) 214, e.g., a common SL. In other words, according to some embodiments, NAND memory strings 208 within the same block 204 have an array common source (ACS). According to some embodiments, the DSG 212 of each NAND memory string 208 is coupled to its respective bit line 216, and data can be read or written from its respective bit line 216 via an output bus (not shown). In some embodiments, the bit line 216 may extend horizontally (e.g., in the Y direction) to couple multiple memory strings 208. In some embodiments, each NAND memory string 208 is configured to be selected or deselected by applying a selection voltage (e.g., exceeding the threshold voltage of the transistor having the DSG212) or a deselection voltage (e.g., 0V) to each DSG212 via one or more DSG lines 213, and / or by applying a selection voltage (e.g., exceeding the threshold voltage of the transistor having the SSG210) or a deselection voltage (e.g., 0V) to each SSG210 via one or more SSG lines 215.

[0044] As shown in Figure 2, the NAND memory string 208 can be organized into multiple blocks 204, each having a common source line 214 to which it is coupled to the ACS. In some embodiments, each block 204 can function as a basic data unit for an erase operation, thereby erasing all memory cells 206 on the same block 204 simultaneously. To erase the memory cells 206 in a selected block 204, the source lines 214 coupled to the selected block 204 and the unselected blocks in the same plane can be biased with an erase voltage. For example, the erase voltage can be a high positive voltage (e.g., 20V or higher). In some embodiments, the erase operation can be performed at a half-block level, a quarter-block level, or at a level with any appropriate number of blocks or parts of blocks.

[0045] Memory cells 206 of adjacent NAND memory strings 208 can be joined via word lines 218. In some embodiments, the word lines 218 can extend horizontally (e.g., in the X direction). The word lines 218 can select which rows of memory cells 206 are affected by read and program operations. In some embodiments, memory cells 206 are SLC, and each word line 218 is joined to a page of memory cell 206, which is the basic data unit for program operations. If memory cells 206 are MLC, storing 2 bits of data per cell, each word line 218 can correspond to 2 pages. If memory cells 206 are TLC, each word line 218 can correspond to 3 pages. If memory cells 206 are QLC, each word line 218 can correspond to 4 pages. The size of a page in bits is associated with the number of NAND memory strings 208 joined by the word lines 218 in block 204. Each word line 218 may include gate lines coupled to multiple control gates (gate electrodes) of multiple memory cells 206 within each page. An exemplary word line shown in Figure 2 includes dummy WLs, WL1, WL2, WL3, WL4, and WL5 between one or more DSG lines 213 and one or more SSG lines 215.

[0046] Figure 3 shows an exemplary peripheral circuit 202 relating to one or more embodiments of the present disclosure. The peripheral circuit 202 may be coupled to the memory array 201 via bit lines 216, word lines 218, source lines 214, SSG lines 215, and DSG lines 213. As previously stated, the peripheral circuit 202 may include any suitable analog, digital, and mixed-signal circuits to facilitate the operation of the memory array 201 by applying voltage and / or current signals to each target memory cell 206 via bit lines 216, word lines 218, source lines 214, SSG lines 215, and DSG lines 213 and sensing voltage and / or current signals from each target memory cell 206. The peripheral circuit 202 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. Exemplary peripheral circuits include a page buffer / sense amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, registers 314, an interface 316, and a data bus. Some examples may also include additional peripheral circuits not shown in Figure 3.

[0047] The page buffer / sense amplifier 304 may be configured to read and program (write) data to and from the memory array 201 according to control signals from the control logic 312. In one example, the page buffer / sense amplifier 304 may store one page of program data (write data) to be programmed in one page of the memory array 201. In another example, the page buffer / sense amplifier 304 may perform a program verification operation to ensure that the data is properly programmed into the memory cell 206 coupled to the selected word line 218. In yet another example, the page buffer / sense amplifier 304 may also sense a low-power signal from the bit line 216 representing the data bits stored in the memory cell 206 and amplify small voltage fluctuations to a logic level that is recognizable in the read operation. The column decoder / bit line driver 306 may be controlled by the control logic 312 and configured to select one or more NAND memory strings 208 by applying bit line voltages generated from the voltage generator 310.

[0048] The row decoder / word line driver 308 is controlled by control logic 312 and may be configured to select / deselect block 204 of the memory array 201 and select / deselect word lines 218 of block 204. The row decoder / word line driver 308 may be further configured to drive word lines 218 using word line voltages generated from voltage generator 310. In some embodiments, the row decoder / word line driver 308 can also select / deselect and drive SSG lines 215 and DSG lines 213. As will be described in detail below, the row decoder / word line driver 308 is configured to apply a program voltage to the selected word line 218 during program operation on the memory cell 206 coupled to the selected word line 218.

[0049] The voltage generator 310 may be configured to generate word line voltages (e.g., read voltage, program voltage, path voltage, local voltage, and verification voltage), bit line voltages, and source line voltages, which are controlled by the control logic 312 and supplied to the memory array 201.

[0050] The control logic 312 can be coupled to each of the aforementioned peripheral circuits 202 and may be configured to control the operation of each peripheral circuit 202. The register 314 can be coupled to the control logic 312 and may include a state register, a command register, and an address register for storing state information, command arithmetic codes, and command addresses for controlling the operation of each peripheral circuit.

[0051] Interface 316 can be coupled to control logic 312 and can function as a control buffer for buffering control commands received from a host (not shown) and relaying them to control logic 312, and for buffering state information received from control logic 312 and relaying it to the host. Interface 316 can also be coupled to column decoder / bit line driver 306 via a data bus and can function as a data buffer for buffering and relaying data between the data input / output (I / O) interface and memory array 201.

[0052] Figure 4 shows schematic circuit diagrams of exemplary word line driver 308 and page buffer 304 of Figure 3 according to one or more embodiments of the present disclosure. In some embodiments, the page buffer 304 includes a plurality of page buffer circuits 402, each coupled to a 3D NAND memory string 208 via a bit line 216. That is, the memory device 200 may include bit lines 216 each coupled to a 3D NAND memory string 208, and the page buffer 304 may include bit lines 216 and page buffer circuits 402 coupled to the 3D NAND memory string 208, respectively. Each page buffer circuit 402 may include one or more latches, switches, power supplies, nodes (e.g., data nodes and I / O nodes), current mirrors, verification logic, sense circuits, etc. In some embodiments, each page buffer circuit 402 is configured to store sense data, such as sensed current, received from the respective bit line 216 corresponding to the read data. Each page buffer circuit 402 may also be configured to output the stored sensed data during a read operation. Each page buffer circuit 402 can be further configured to store program data and to output the stored program data to its respective bit line 216 when the program is running.

[0053] In some embodiments, a word line driver includes a plurality of string drivers 404 (also known as drive elements), each coupled to a word line 218. A word line driver 308 may also include a plurality of local word lines 406 (LWLs), each coupled to a string driver 404. Each string driver 404 may include a gate coupled to a row decoder 408, a source / drain coupled to its respective local word line 406, and another source / drain coupled to its respective word line 218. In some embodiments, the gates of two or more string drivers 404 are coupled to the same row decoder 408. For example, each memory block may have its corresponding row decoder 408. String drivers 404 coupled to a word line 218 within a single memory block may be coupled to the same row decoder 408. In some memory operations, a row decoder 408 can select or deselect its corresponding memory block. For example, the row decoder 408 may apply a selection voltage (e.g., a voltage higher than the threshold voltage of the string driver 404) to the gate of the string driver 404 of the corresponding memory block so that the corresponding memory block is selected. Conversely, the row decoder 408 may apply a deselection voltage (e.g., a voltage lower than the threshold voltage of the string driver 404) to the gate of the string driver 404 of the corresponding memory block so that the corresponding memory block is deselected. In some embodiments, the peripheral circuitry may include other circuits configured to select one or more specific string drivers 404 of the selected memory block and apply a voltage (e.g., a program voltage, a pass voltage, or an erase voltage) to each local word line 406 so that a voltage is applied to each word line 218 by each selected string driver 404.

[0054] Figure 5 shows a top view of an example of a first semiconductor structure 102 according to one or more embodiments of the present disclosure. The first semiconductor structure 102 can be used to form a memory device, for example, the 3D NAND memory device 200 in Figure 2. In some embodiments, the first semiconductor structure 102 includes one or more array regions and connection regions configured to provide conductive connections to one or more array regions. In some examples, the first semiconductor structure 102 includes two array regions 500A, 500C and a connection region 500B between the two array regions along a first horizontal direction (e.g., the X direction). Each array region 500A, 500C includes an array of channel structures 540. The channel structures 540 can be used to form a string of memory cells (e.g., the memory string 208 in Figure 2) that can be coupled in series along a vertical direction (e.g., the Z direction) perpendicular to the first horizontal direction. Contact structures 560 can be formed within the connection region 500B. The contact structure 560 may be configured to connect corresponding layers of conductive layers within array region 500A and / or array region 500C. The contact structure 560 may also be configured to connect the conductive layer of the first semiconductor structure 102 to the control circuit of the second semiconductor structure 104.

[0055] In some embodiments, one or more first slit structures 550A can be formed in the array region 500A in a first horizontal direction (e.g., the X direction) to divide the first semiconductor structure 102 into multiple memory blocks. Similarly, one or more second slit structures 550B can be formed in the connection region 500B in a first horizontal direction to divide the first semiconductor structure 102 into multiple memory blocks. Corresponding first slit structures 550A and second slit structures 550B can be coupled to each other along the first horizontal direction (e.g., the X direction). In some embodiments, along the second horizontal direction (e.g., the Y direction), the width of the first slit structure 550A is smaller than the width of the second slit structure 550B. For example, the width of the second slit structure 550B can be about 1.5 to 2 times the width of the first slit structure 150A. In some embodiments, the width of the first slit structure 550A is the same as the width of the second slit structure 550B. Each of the first slit structure 550A and / or the second slit structure 550B may extend in a vertical direction (e.g., the Z direction) perpendicular to the first horizontal direction and the second horizontal direction.

[0056] Figure 6A shows a plan view (e.g., in the XY plane) of a second semiconductor structure 600 (e.g., the second semiconductor structure 104 in Figures 1A and 1B) relating to one or more embodiments of the present disclosure. The second semiconductor structure 600 may include a first group 602 of page buffers, a second group 604 of page buffers, a string driver 606, and a row decoder 608.

[0057] The first group 602 of page buffers may each include page buffer circuits (e.g., page buffer circuit 402 in Figure 4) coupled to the bit lines of a first memory array in a first array region of a first semiconductor structure, such as the first semiconductor structure 102 in Figure 1A or Figure 1B (e.g., array region 500A in Figure 5). The second group 604 of page buffers may each include page buffer circuits (e.g., page buffer circuit 402 in Figure 4) coupled to the bit lines of a second memory array in a second array region of the first semiconductor structure 102 (e.g., array region 500C in Figure 5). In some examples, both the first and second memory arrays of the first semiconductor structure are 8K wide memory arrays. That is, the first and second memory arrays have 8K memory cells along the X direction. Thus, each of the first and second memory arrays has 8K bit lines distributed along the X direction. In such cases, the first group 602 of the page buffer and the second group 604 of the page buffer can each contain 8K page buffer circuits. In some embodiments, bit lines in the first semiconductor structure 102 overlap with corresponding page buffer circuits in the second semiconductor structure 104 in a plan view.

[0058] The string drivers 606 may include string drivers (e.g., string driver 404 in Figure 4) each coupled to a word line in the first semiconductor structure 102. The row decoders 608 may include row decoders (e.g., row decoder 408 in Figure 4) each coupled to a group of string drivers. The string drivers 606 and row decoders 608 can be positioned along the X direction between the first group 602 and the second group 604 of the page buffer. The remaining circuitry 610 of the second semiconductor structure 600 may include the column decoder / bit line driver 306, the voltage generator 310, and other peripheral circuits.

[0059] In some embodiments, the width (e.g., length along the X direction) of the first group 602 of the page buffer is equal to the width 622 of the first memory array of the first semiconductor structure 102. The width of the second group 604 of the page buffer is equal to the width 624 of the second memory array of the first semiconductor structure 102. In other words, when the first semiconductor structure 102 and the second semiconductor structure 600 are stacked along the Z direction, in a plan view along the Z direction, the first group 602 of the page buffer overlaps with the first memory array of the first semiconductor structure 102, the second group 604 of the page buffer overlaps with the second memory array of the first semiconductor structure 102, while the string driver 606 and row decoder 608 do not overlap with the first or second memory array, or are offset from the first or second memory array.

[0060] In some embodiments, the width 625 of the connection region between the first array region and the second array region in the first semiconductor structure 102 (e.g., connection region 500B in Figure 5) is smaller than the combined width of the row decoder 608 and the string driver 606. Thus, the first semiconductor structure 102 has unused regions between the connection region and each array region. For example, the unused region between the first array region and the connection region may have a width of 626, and the unused region between the second array region and the connection region may have a width of 628. In some embodiments, the unused regions do not contain memory cells, which may limit the memory cell density of the first semiconductor structure 102. In some embodiments, the unused regions may include dummy memory cells that are not used to store data.

[0061] Figure 6B shows a plan view (e.g., in the XY plane) of an example of a 3D memory device (e.g., 3D memory device 100 in Figure 1A or 3D memory device 101 in Figure 1B) having the second semiconductor structure 600 of Figure 6A, relating to one or more embodiments of the present disclosure. Bit lines of a memory array in a first array region of the first semiconductor structure 102 may be coupled to the corresponding page buffer circuits of a first group 602 of page buffers via first connection lines (not shown) and second connection lines 612. In some embodiments, the first connection lines are located within the first semiconductor structure 102, and the second connection lines 612 are located within the second semiconductor structure 104. For example, the first connection lines may connect the bit lines to a first conductive structure in a first junction layer of the first semiconductor structure 102. The second connecting line 612 can connect the second conductive structure within the second junction layer of the second semiconductor structure 104 (for example, a conductive structure that comes into contact with the first conductive structure when the first semiconductor structure 102 and the second semiconductor structure 104 are stacked) to the corresponding page buffer circuit.

[0062] In some embodiments, the second connection lines 612 are straight along the Y direction and spaced apart from each other along the X direction. In some embodiments, each of the second connection lines 612 overlaps with the corresponding page buffer circuit of the first group 602 of the page buffer in a plan view. The second connection lines 612 do not overlap with the string driver 606 and row decoder 608 in a plan view (they are offset from the string driver 606 and row decoder 608).

[0063] Similarly, bit lines of the memory array in the second array region may be coupled to the corresponding page buffer circuits of the second group 602 of the page buffers via first connection lines (not shown) in the first semiconductor structure 102 and second connection lines 614 in the second semiconductor structure 104. In some embodiments, each of the second connection lines 614 overlaps with the corresponding page buffer circuits of the second group 604 of the page buffers in plan view.

[0064] In some embodiments, the row decoder 608 is located on one side of the string driver 606 along the X direction. The row decoder 608 may include N row decoders, each corresponding to one of N memory blocks in a first semiconductor structure 102, each numbered from 0 to N-1, where N is an integer greater than 1. Each of the N row decoders is located adjacent to the string driver coupled to the word line in the corresponding memory block. For example, as shown in Figure 6B, the string driver 606 may include a string driver 636 coupled to the word line in the nth memory block in the first semiconductor structure 102, a string driver 646 coupled to the word line in the (n+1)th memory block, a string driver 656 coupled to the word line in the (n+2)th memory block, and a string driver 666 coupled to the word line in the (n+3)th memory block, where n is an integer. The row decoder 638 coupled to the string driver 636 is located adjacent to the string driver 636. A row decoder 648 coupled to string driver 646 is located adjacent to string driver 646. A row decoder 658 coupled to string driver 656 is located adjacent to string driver 656. A row decoder 668 coupled to string driver 666 is located adjacent to string driver 666.

[0065] Figure 7A shows a plan view (e.g., in the XY plane) of a second semiconductor structure 700 (e.g., a second semiconductor structure 104 in Figure 1A or Figure 1B) relating to one or more embodiments of the present disclosure. The second semiconductor structure 700 may include a first group 702 of page buffers, a second group 704 of page buffers, a string driver 706, and a row decoder 708.

[0066] The first group 702 of page buffers may each include page buffer circuits (e.g., page buffer circuit 402 in Figure 4) coupled to the bit lines of a first memory array in a first array region (e.g., array region 500A in Figure 5) of the first semiconductor structure 102. The second group 604 of page buffers may each include page buffer circuits (e.g., page buffer circuit 402 in Figure 4) coupled to the bit lines of a second memory array in a second array region (e.g., array region 500C in Figure 5) of the first semiconductor structure 102. In some examples, both the first and second memory arrays of the first semiconductor structure 102 are 8K wide memory arrays. That is, the first and second memory arrays have 8K memory cells along the X direction. Thus, the first and second memory arrays have 8K bit lines distributed along the X direction. In such cases, the first group 702 and the second group 704 of page buffers may each include 8K page buffer circuits. In some embodiments, at least a portion of the bit lines within the first semiconductor structure 102 are spaced apart from the corresponding page buffer circuits of the first and second groups 702, 704 of the page buffer along the X direction in a plan view.

[0067] The string driver 706 may include string drivers (e.g., string driver 404 in Figure 4) each coupled to a word line in the first semiconductor structure 102. The row decoder 708 may include row decoders (e.g., row decoder 408 in Figure 4) each coupled to a group of string drivers. The string driver 706 and row decoder 708 can be positioned along the X direction between the first group 702 and the second group 704 of the page buffer. In some embodiments, the row decoder 708 may include a first group of row decoders located on one side of the string driver 706 and a second group of row decoders located on the other side of the string driver 706. The remaining circuitry 710 of the second semiconductor structure 700 may include a column decoder / bit line driver 306, a voltage generator 310, and other peripheral circuits.

[0068] In some embodiments, the width of the first group of the page buffer 702 (e.g., the length along the X direction) is smaller than the width 722 of the first memory array of the first semiconductor structure 102. The width of the second group 704 of the page buffer is smaller than the width 724 of the second memory array of the first semiconductor structure 102. The width 725 of the connection region between the first array region and the second array region in the first semiconductor structure 102 (e.g., the connection region 500B in Figure 5) is smaller than the combined width of the row decoder 708 and the string driver 706. The sum of widths 722, 724, and 725 is equal to or substantially identical to the sum of the widths of the first group 702 of the page buffer, the second group 704 of the page buffer, the string driver 706, and the row decoder 708. As used herein, the term “substantially” is intended to correspond to manufacturing tolerances. In other words, when the first semiconductor structure 102 and the second semiconductor structure 700 are stacked along the Z direction, in a plan view along the Z direction, the first group 702 of the page buffer overlaps with the first memory array of the first semiconductor structure 102, the second group 704 of the page buffer overlaps with the second memory array of the first semiconductor structure 102, and at least one of the string driver 706 or the row decoder 708 overlaps with the first or second memory array of the first semiconductor structure 102 at least partially. In some embodiments, all of the row decoder 708 and the first portion of the string driver 706 overlap with the first or second memory array. The second portion of the string driver overlaps with the connection region. In this way, since there can be no unused region between the connection region and either the first or second array region, the memory cell density of the first semiconductor structure 102 can be increased.

[0069] Figure 7B shows a plan view (e.g., in the XY plane) of an example of a 3D memory device (e.g., 100 in Figure 1A or 101 in Figure 1B) having a second semiconductor structure 700 according to one or more embodiments of the present disclosure.

[0070] In some embodiments, bit lines of a memory array within a first array region of a first semiconductor structure 102 can be coupled to corresponding page buffer circuits of a first group 702 of page buffers via first connection lines (not shown) and second connection lines 712, 712a. The first connection lines are located within the first semiconductor structure 102, and the second connection lines 712, 712a are located within the second semiconductor structure 104. For example, the first connection lines can connect bit lines to a first conductive structure within a first junction layer of the first semiconductor structure 102. The second connection lines 712, 712a can connect a second conductive structure within a second junction layer of the second semiconductor structure 104 (for example, a conductive structure that contacts the first conductive structure when the first semiconductor structure 102 and the second semiconductor structure 104 are stacked) to the corresponding page buffer circuits. In some embodiments, unlike the second connection line 612 in Figure 6B where the second connection line 612 is a straight line, the second connection lines 712, 712a may have multiple portions offset from each other. In some embodiments, the second connection line 712 may include a first portion 716 and a second portion 717, both extending along the Y direction, and a third portion 718 connecting the ends of the first portion 716 and the second portion 717. The first portion 716 and the second portion 717 are spaced apart from each other along the X direction. For example, the first portion 716 of the second connection line 712 may overlap with either the string driver 706 or the row decoder 708 in a plan view. The second portion 717 of the second connection line 712 may overlap with the corresponding page buffer circuit of the first group 702 of the page buffer in a plan view. In some embodiments, as shown in Figure 7B, for example, the offset between the first portion 716 and the second portion 717 increases along the X direction from the first array region to the connection region, or the length of the third portion 718 along the X direction increases. For example, the second connection line 712a is located further from the string driver 706 and row decoder 708 than the second connection line 712. The second connection line 712a has a first portion 716a and a second portion 717a that extend along the Y direction.The offset between the first portion 716a and the second portion 717a along the X direction is smaller than the offset between the first portion 716 and the second portion 717 along the X direction.

[0071] In some embodiments, the bit lines of the memory array in the second array region of the first semiconductor structure 102 can be coupled to the corresponding page buffer circuits of the second group 704 of the page buffer via first connection lines (not shown) in the first semiconductor structure 102 and second connection lines 714, 714a in the second semiconductor structure 104. In some embodiments, the second connection lines 714, 714a, like the second connection lines 712, 712a, may have multiple offset portions.

[0072] In this way, the second connecting lines 712, 712a, 714, and 714a can utilize a larger space in the second semiconductor structure 104 than the second groups 702 and 704 of the first and page buffers, without creating unused areas in the first semiconductor structure 104. Therefore, the size of the first and second semiconductor structures 102 and 104 along the X direction can be reduced.

[0073] In some embodiments, the row decoder 708 may include N row decoders corresponding to one of N memory blocks in a first semiconductor structure 102, each numbered from 0 to N-1. The row decoder 708 may include two groups of row decoders, each positioned on one side of the string driver 706 along the X direction, as shown, for example, in Figure 7A or Figure 7B. In some embodiments, the row decoder 708 is positioned symmetrically on both sides of the string driver 706. For example, row decoders associated with even-numbered memory blocks may be positioned on one side of the string driver 706, and row decoders associated with odd-numbered memory blocks may be positioned on the other side of the string driver 706. As shown in Figure 7B, the string driver 706 may include a string driver 736 coupled to a word line in the nth memory block within the first semiconductor structure 102, a string driver 746 coupled to a word line in the (n+1)th memory block, a string driver 756 coupled to a word line in the (n+2)th memory block, and a string driver 766 coupled to a word line in the (n+3)th memory block. The row decoder 738 coupled to string driver 736 is located on the first side of string driver 736. The row decoder 748 coupled to string driver 746 is located on the second side of string driver 746. The row decoder 758 coupled to string driver 756 is located on the first side of string driver 756. The row decoder 768 coupled to string driver 766 is located on the second side of string driver 766. In some embodiments, the length of the row decoder 738 (e.g., length along the Y direction) is no more than twice the length of string driver 736.

[0074] Figure 8A shows a plan view (e.g., in the XY plane) of an example of a second semiconductor structure 800 (e.g., the second semiconductor structure 104 in Figure 1A or Figure 1B) relating to one or more embodiments of the present disclosure. The second semiconductor structure 800 may include a first group 802 of page buffers, a second group 804 of page buffers, a string driver 806, and a row decoder 808.

[0075] The first group 802 of page buffers may each include page buffer circuits (e.g., page buffer circuit 402 in Figure 4) coupled to the bit lines of a first memory array in a first array region (e.g., array region 500A in Figure 5) of the first semiconductor structure 102. The second group 604 of page buffers may each include page buffer circuits (e.g., page buffer circuit 402 in Figure 4) coupled to the bit lines of a second memory array in a second array region (e.g., array region 500C in Figure 5) of the first semiconductor structure 102. In some examples, both the first and second memory arrays of the first semiconductor structure 102 are 8K wide memory arrays. That is, the first and second memory arrays have 8K memory cells along the X direction. Thus, the first and second memory arrays have 8K bit lines distributed along the X direction. In such cases, the first group 802 and the second group 804 of page buffers may each include 8K page buffer circuits. In some embodiments, at least a portion of the bit lines within the first semiconductor structure 102 are spaced apart from the corresponding page buffer circuits of the first and second groups 802, 804 of the page buffer along the X direction in a plan view.

[0076] The string drivers 806 may include string drivers (e.g., string driver 404 in Figure 4) each coupled to a word line in the first semiconductor structure 102. The row decoders 808 may include row decoders (e.g., row decoder 408 in Figure 4) each coupled to a group of string drivers. The string drivers 806 and row decoders 808 can be positioned along the X direction between the first group 802 and the second group 804 of the page buffer. The remaining circuits 809, 810 of the second semiconductor structure 800 may include a column decoder / bit line driver 306, a voltage generator 310, and other peripheral circuits. In some embodiments, the row decoders 808 are located on one side of the string drivers 806, and the remaining circuits 809 are located on the other side of the string drivers 806. The remaining circuits 809 may include driver circuits associated with the page buffer.

[0077] In some embodiments, the width (e.g., length along the X direction) of the first group 802 of the page buffer is smaller than the width 822 of the first memory array of the first semiconductor structure 102. The width of the second group 804 of the page buffer is smaller than the width 824 of the second memory array of the first semiconductor structure 102. The width 825 of the connection region (e.g., connection region 500B in Figure 5) between the first and second array regions in the first semiconductor structure 102 is smaller than the combined width of the string driver 806, the row decoder 808, and the remaining circuitry 809. The sum of widths 822, 824, and 825 is equal to the sum of the widths of the first group 802 of the page buffer, the second group 804 of the page buffer, the string driver 806, the row decoder 808, and the remaining circuitry 809. In other words, when the first semiconductor structure 102 and the second semiconductor structure 800 are stacked along the Z direction, in a plan view along the Z direction, the first group 802 of the page buffer overlaps with the first memory array of the first semiconductor structure 102, the second group 804 of the page buffer overlaps with the second memory array of the first semiconductor structure 102, and at least one of the string driver 806 or row decoder 808 overlaps with the first or second memory array of the first semiconductor structure 102 at least partially. In some embodiments, all of the row decoder 808, all of the remaining circuitry 809, and the first portion of the string driver 806 overlap with the first or second memory array. The second portion of the string driver 706 overlaps with the connection region. In this way, since there can be no unused region between the connection region and either array region, the memory cell density of the first semiconductor structure 102 can be increased.

[0078] Figure 8B shows a plan view (e.g., in the XY plane) of an example of a 3D memory device 100, 101 having a second semiconductor structure 800 according to one or more embodiments of the present disclosure.

[0079] In some embodiments, bit lines of a memory array within a first array region of a first semiconductor structure 102 can be coupled to corresponding page buffer circuits of a first group 802 of page buffers via first connection lines (not shown) and second connection lines 812. The first connection lines are located within the first semiconductor structure 102, and the second connection lines 812 are located within the second semiconductor structure 104. For example, the first connection lines can connect bit lines to a first conductive structure within a first junction layer of the first semiconductor structure 102. The second connection lines 712, 712a can connect a second conductive structure within a second junction layer of the second semiconductor structure 104 (for example, a conductive structure that contacts the first conductive structure when the first semiconductor structure 102 and the second semiconductor structure 104 are stacked) to the corresponding page buffer circuits. In some embodiments, the second connection lines 812 can have multiple offset portions, similar to the second connection lines 712, 712a in Figure 7B. In some embodiments, the second connection line 812 may include a first portion 816 and a second portion 817, both extending along the Y direction, and a third portion 818 connecting the ends of the first portion 816 and the second portion 817. The first portion 816 and the second portion 817 are spaced apart from each other along the X direction. For example, the first portion 816 of the second connection line 812 may overlap with either the string driver 806 or the row decoder 808 in a plan view. The second portion 817 of the second connection line 812 may overlap with the corresponding page buffer circuit of the first group 802 of the page buffer in a plan view. In some embodiments, as shown, for example in Figure 8B, the offset between the first portion 816 and the second portion 817 may increase along the X direction from the first array region to the connection region, or the length of the third portion 818 along the X direction may increase.

[0080] In some embodiments, bit lines of a memory array in a second array region of a first semiconductor structure 102 can be coupled to the corresponding page buffer circuit of a second group 804 of page buffers via a first connection line (not shown) in the first semiconductor structure 102 and a second connection line 814 in the second semiconductor structure 104. In some embodiments, the second connection line 814, like the second connection line 812, may have multiple offset portions. For example, the second connection line 814 may include a first portion 826 that overlaps with either the string driver 806 or the remaining circuit 809, a second portion 827 that overlaps with the corresponding page buffer circuit of the second group 804 of page buffers, and a third portion 828 that connects the ends of the first portion 826 and the second portion 827.

[0081] In some embodiments, the row decoder 808 is located on one side of the string driver 806 along the X direction. The row decoder 808 can include N row decoders, each corresponding to one of N memory blocks in a first semiconductor structure 102, each numbered from 0 to N-1. Each of the N row decoders is located adjacent to a string driver coupled to a word line in the corresponding memory block. For example, as shown in Figure 8B, the string driver 806 can include a string driver 836 coupled to a word line in the nth memory block in the first semiconductor structure 102, a string driver 846 coupled to a word line in the (n+1)th memory block, a string driver 856 coupled to a word line in the (n+2)th memory block, and a string driver 866 coupled to a word line in the (n+3)th memory block. The row decoder 838 coupled to the string driver 836 is located on the first side of the string driver 836. The row decoder 848 coupled to the string driver 846 is located on the first side of the string driver 846. The row decoder 858 coupled to the string driver 856 is located on the first side of the string driver 856. The row decoder 868 coupled to the string driver 866 is located on the first side of the string driver 866.

[0082] Figure 9 is a flowchart of an exemplary process 900 for forming a memory device. The memory device may be the 3D memory device 100 in Figure 1A, or the 3D memory device 101 in Figure 1B. Process 900 includes steps (or processes) that can be performed in any appropriate order and / or any combination.

[0083] In step 902, a first semiconductor structure (for example, the first semiconductor structure 102 in Figure 1A or Figure 1B, or the first semiconductor 500 in Figure 5) is formed. The first semiconductor structure includes a first memory array in a first array region (for example, array region 500A in Figure 5), a second memory array in a second array region (for example, array region 500C in Figure 5), and a contact structure in a connection region (for example, connection region 500B in Figure 5). The connection region is located between the first array region and the second array region along a first direction (for example, the X direction). The first memory array and the second memory array can each be a memory array 201 in Figure 2, which includes NAND memory cells.

[0084] In step 904, a second semiconductor structure (for example, the second semiconductor structure 104 in Figures 1A-1B, the second semiconductor structure 600 in Figure 6A, the second semiconductor structure 700 in Figure 7A, or the second semiconductor structure 800 in Figure 8A) is formed. The second semiconductor structure includes a string driver (for example, the string driver 404 in Figure 4, the string driver 606 in Figures 6A-6B, the string driver 706 in Figures 7A-7B, or the string driver 806 in Figures 8A-8B). The second semiconductor structure further includes a row decoder (for example, the row decoder 408 in Figure 4, the row decoder 608 in Figures 6A-6B, the row decoder 708 in Figures 7A-7B, or the row decoder 808 in Figures 8A-8B) positioned adjacent to the string driver along a first direction.

[0085] In some embodiments, the row decoder is located on one side of the string driver, as shown, for example, in Figures 6A-6B and 8A-8B. In some embodiments, the row decoder includes a first group of row decoders located on the first side of the string driver and a second group of row decoders located on the second side of the string driver, as shown, for example, in Figures 7A-7B. For example, the first semiconductor structure may include N memory blocks numbered from 0 to N-1. Row decoders coupled to a string driver coupled to word lines in memory blocks associated with even numbers (e.g., row decoders 738, 758) can be located on the first side of the string driver. Row decoders coupled to a string driver coupled to word lines in memory blocks associated with odd numbers (e.g., row decoders 748, 768) can be located on the second side of the string driver.

[0086] In step 906, the first and second semiconductor structures are stacked along a second direction (e.g., the Z direction) perpendicular to the first direction. At least a portion of the row decoder or a portion of the string driver overlaps with at least one of the first memory array and the second memory array in a plan view (e.g., the XY plane) perpendicular to the second direction. In some embodiments, as shown, for example, in Figures 7A-7B and 8A-8B, in a plan view, all of the row decoder and the first portion of the string driver overlap with the first memory array and / or the second memory array. The second portion of the string driver overlaps with the connection area in a plan view.

[0087] Figure 10 shows a block diagram of a system 1000 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure. System 1000 may be a mobile phone, desktop computer, laptop computer, tablet, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, argument reality (AR) device, or any other suitable electronic device having internal storage. As shown in Figure 10, system 1000 may include a host device 1008 and a memory system 1002 having one or more 3D memory devices 1004 and a memory controller 1006. The host device 1008 may include an electronic device processor such as a central processing unit (CPU) or a system-on-a-chip (SoC) such as an application processor (AP). The host device 1008 may be configured to transmit or receive data to or from one or more 3D memory devices 1004.

[0088] The 3D memory device 1004 can be any 3D memory device disclosed herein, such as the 3D memory device depicted in any one of Figures 1 to 9. In some embodiments, the 3D memory device 1004 includes NAND flash memory. A memory controller 1006 (also known as a controller circuit) is coupled to the 3D memory device 1004 and the host device 1008. Consistent with embodiments of this disclosure, the 3D memory device 1004 may include a plurality of conductive interconnects via a cover layer in contact with conductive pads in a conductive pad layer, and the memory controller 1006 may be coupled to the 3D memory device 1004 via at least one of the plurality of conductive interconnects. The memory controller 1006 is configured to control the 3D memory device 1004. For example, the memory controller 1006 may be configured to operate a plurality of channel structures via word lines. The memory controller 1006 can manage the data stored in the 3D memory device 1004 and communicate with the host device 1008.

[0089] In some embodiments, the memory controller 1006 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, CompactFlash® (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 1006 is designed / configured to operate in high-duty-cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage for mobile devices such as smartphones, tablets, and laptop computers, and for enterprise storage arrays. The memory controller 1006 may be configured to control the operation of the 3D memory device 1004, such as read operations, erase operations, and program operations. The memory controller 1006 may also be configured to manage various functions relating to data stored or to be stored in the 3D memory device 1004, including but not limited to bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the memory controller 1006 is further configured to process error correction codes (ECC) with respect to data read from or written to the 3D memory device 1004. Any other suitable function, such as formatting the 3D memory device 1004, may also be performed by the memory controller 1006.

[0090] The memory controller 1006 can communicate with an external device (e.g., a host device 1008) according to a specific communication protocol. For example, the memory controller 1006 can communicate with an external device via at least one of various interface protocols, such as the USB protocol, MMC protocol, Peripheral Interconnection (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Extended Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0091] The memory controller 1006 and one or more 3D memory devices 1004 can be incorporated into various types of storage devices, for example, in the same package such as a Universal Flash Storage (UFS) package or an eMMC package. In one example shown in Figure 11A, the memory controller 1006 and a single memory device 1004 may be incorporated into a memory card 1102. The memory card 1102 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1102 may further include a memory card connector 1104 that connects the memory card 1102 to a host (for example, the host 1008 in Figure 10). In another example shown in Figure 11B, the memory controller 1006 and multiple memory devices 1004 may be incorporated into an SSD 1106. The SSD 1106 may further include an SSD connector 1108 for connecting the SSD 1106 to a host (for example, host 1008 in Figure 10). In some embodiments, the storage capacity and / or operating speed of the SSD 1106 is greater than the storage capacity and / or operating speed of the memory card 1102.

[0092] The subject matter and embodiments of acts and operations described in this disclosure may be implemented in digital electronic circuits, tangibly embodied computer software or firmware, computer hardware including structures disclosed in this disclosure and their structural equivalents, or one or more combinations thereof. Embodiments of the subject matter described in this disclosure may be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier, for execution by a data processing device or for controlling the operation of a data processing device. The carrier may be a tangible, non-temporary computer storage medium. Alternatively or additionally, the carrier may be an artificially generated propagating signal, such as a machine-generated electrical signal, optical signal, or electromagnetic signal, generated to encode information for transmission to a suitable receiving device for execution by a data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random-access or serial-access memory device, or one or more combinations thereof, or a part thereof. The computer storage medium is not a propagating signal.

[0093] In this disclosure, references such as “one embodiment,” “a certain embodiment,” “an example of an embodiment,” “several embodiments,” and “several embodiments” should be noted as indicating that while the described embodiments may include certain features, structures, or characteristics, not all embodiments necessarily include those features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, where certain features, structures, or characteristics are described in relation to an embodiment, it is within the knowledge of those skilled in the art that such features, structures, or characteristics will be affected in relation to other embodiments, whether explicitly stated or not.

[0094] In general, terms can be understood at least partially from their use in context. For example, the term “one or more” as used herein may, at least partially depending on the context, be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” may, at least partially depending on the context, be understood to convey either a singular or plural usage. Furthermore, the term “based on” may be understood not necessarily to convey an exclusive set of factors, but instead, at least partially depending on the context, may allow for the presence of additional factors that are not necessarily explicitly described.

[0095] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted most broadly, with “on” meaning not only “directly on” something, but also “on” something that has an intermediate feature or layer between them. Furthermore, “above” or “over” may mean not only “above” or “over” something, but also “above” or “over” something that has no intermediate feature or layer between them (i.e., directly on something).

[0096] Furthermore, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to facilitate descriptions of the relationship between one element or feature and another, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or process steps, in addition to the orientation shown in the figures. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0097] As used herein, the term “substrate” refers to the material on which subsequent material layers are added. A substrate includes an “upper” surface and a “lower” surface. The upper surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise specified, semiconductor devices are formed on the upper side of the substrate. The lower surface is on the opposite side of the upper surface, and therefore, the lower side of the substrate is on the opposite side of the upper side of the substrate. The substrate itself can be patterned. Materials added to the substrate may or may not be patterned. Furthermore, the substrate can include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, and indium phosphide. Alternatively, the substrate can be made from non-conductive materials such as glass, plastic, or sapphire wafers.

[0098] As used herein, the term “layer” refers to a portion of a material that includes a region having thickness. A layer has an upper and lower end, with the lower end of the layer adjacent to the substrate and the upper end relatively away from the substrate. A layer may extend over the entirety of a structure below or above it, or may have a smaller extent than the extent of the structure below or above it. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the upper and lower end faces of a continuous structure, or between any set of horizontal faces at the upper and lower end faces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, which may contain one or more layers, and / or have one or more layers above, above, and / or below it. A layer may contain multiple layers. For example, an interconnection layer may include one or more conductive layers and contact layers (on which contacts, interconnection lines, and / or vertical interconnection accesses (VIA) are formed) and one or more dielectric layers.

[0099] As used herein, the term “nominal” refers to a desired or target value of a characteristic or parameter of a component or process step, set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. As used herein, the range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term “approximately” indicates a value of a given quantity that may vary based on a specific technology node related to the semiconductor device in question. Based on a specific technology node, the term “approximately” may indicate a value of a given quantity that varies within a range of, for example, 10 to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0100] In this disclosure, the terms “horizontal” mean nominally parallel to the side of the substrate, and the terms “perpendicular” or “perpendicular” mean nominally perpendicular to the side of the substrate. The terms “operation” and “step” can be used interchangeably to describe a process.

[0101] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” such as NAND strings) on a laterally oriented substrate, such that the memory strings extend perpendicularly to the substrate.

[0102] This disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. For the sake of brevity of this disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature on or above a second feature in the following description may include embodiments in which the first and second features can be in direct contact, and embodiments in which an additional feature may be formed between the first and second features so that the first and second features do not come into direct contact. Furthermore, this disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplification and clarity and does not in itself define relationships between the various embodiments and / or configurations described.

[0103] The foregoing description of specific embodiments may be readily modified and / or adapted for various uses. Such adaptations and modifications are therefore intended to be within the meaning and scope of equivalents of the disclosed embodiments, based on the teachings and guidance presented herein.

[0104] While this disclosure includes many specific implementation details, these should not be interpreted as limitations on the scope of what is claimed as defined by the claims themselves, but rather as descriptions of features that may be specific to a particular embodiment. Certain features described in this disclosure in the context of a separate embodiment may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable subcombination in multiple embodiments. Furthermore, features may be described as acting in a particular combination and may be initially claimed as such, but one or more features from a claimed combination may, in some cases, be removed from the combination, and the claims may cover a subcombination or a variation of a subcombination.

[0105] Similarly, while the operations are shown in the drawings and described in the claims in a specific order, this should not be understood as requiring that such operations be performed in a specific order shown, or in a sequential order, or that all illustrated operations be performed, in order to achieve the desired result. In certain circumstances, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged in multiple software products.

[0106] Specific embodiments of this subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the operations described in the claims can be performed in a different order and still achieve the desired results. As an example, the processes shown in the accompanying drawings do not necessarily require the specific order or sequence shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

[0107] The breadth and scope of this disclosure should not be limited by any of the typical embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A first semiconductor structure comprising a first memory array in a first array region, a second memory array in a second array region, a contact structure in a connection region between the first array region and the second array region along a first direction, and a word line coupled to a memory cell in the first memory array and a memory cell in the second memory array, A second semiconductor structure equipped with a row decoder, Equipped with, The first semiconductor structure and the second semiconductor structure are stacked on top of each other along a second direction perpendicular to the first direction. A memory device wherein at least a portion of the row decoder overlaps with at least one of the first memory array in the first array region or the second memory array in the second array region in a plan view perpendicular to the second direction.

2. The second semiconductor structure further comprises a string driver, One of the string drivers is coupled to the corresponding word line via a contact structure within the connection area and is also coupled to the corresponding row decoder. The memory device according to claim 1, wherein at least a first portion of the string driver overlaps with at least one of the first memory array in the first array region or the second memory array in the second array region in the plan view.

3. The memory device according to claim 2, wherein the second portion of the string driver overlaps with the contact structure in the connection region in the plan view.

4. The memory device according to claim 2 or 3, wherein the row decoder is located adjacent to the string driver along the first direction.

5. The memory device according to claim 4, wherein the row decoder is located on one side of the string driver.

6. The aforementioned row decoder is A first group of row decoders located on the first side of the string driver, A second group of row decoders located on the second side of the string driver, The memory device according to claim 4, comprising:

7. The first semiconductor structure comprises N memory blocks numbered from 0 to N-1, The first group of row decoders comprises a first row decoder coupled to a first string driver coupled to a word line in a first memory block associated with an odd number, The memory device according to claim 6, wherein the second group of row decoders comprises a second row decoder coupled to a second string driver coupled to a word line in a second memory block associated with an even number.

8. The first string driver and the second string driver are located between the first row decoder and the second row decoder along the first direction, The memory device according to claim 7, wherein the odd number and the even number are adjacent integers.

9. The second semiconductor structure further comprises a first group of page buffers and a second group of page buffers, The row decoder and the string driver are located between the first group of the page buffer and the second group of the page buffer along the first direction. A memory device according to any one of claims 2 to 8.

10. The first semiconductor structure further comprises bit lines coupled to the memory cells in the first memory array, The bit line is coupled to the corresponding page buffer of the first group of page buffers. The memory device according to claim 9, wherein at least one first portion of the bit lines is spaced apart from the corresponding page buffer along the first direction in the plan view.

11. One of the bit lines is coupled to the corresponding page buffer via a first connection line in the first semiconductor structure and a second connection line in the second semiconductor structure. The memory device according to claim 10, wherein the second connection line comprises a first portion that overlaps with at least one of the row decoder or the string driver, a second portion that overlaps with the first group of page buffers, and a third portion that connects the ends of the first portion and the second portion.

12. The first semiconductor structure comprises a first junction layer having a first conductive structure insulated by a first insulating material, The second semiconductor structure comprises a second junction layer having a second conductive structure insulated by a second insulating material, The memory device according to any one of claims 1 to 11, wherein the first semiconductor structure and the second semiconductor structure are joined to each other with the first conductive structure in contact with the second conductive structure.

13. In a method for forming a memory device, A step of forming a first semiconductor structure, wherein the first semiconductor structure comprises a first memory array in a first array region, a second memory array in a second array region, a contact structure in a connection region between the first array region and the second array region along a first direction, and word lines coupled to memory cells in the first memory array and memory cells in the second memory array. The steps include forming a second semiconductor structure equipped with a row decoder, A step of stacking the first semiconductor structure and the second semiconductor structure along a second direction perpendicular to the first direction, Includes, A method wherein at least a portion of the row decoder overlaps with at least one of the first memory array in the first array region or the second memory array in the second array region in a plan view perpendicular to the second direction.

14. The second semiconductor structure further comprises a string driver, The method according to claim 13, wherein one of the string drivers is coupled to a corresponding word line via a contact structure in the connection area and is also coupled to a corresponding row decoder, and at least a first portion of the string driver overlaps in the plan view with at least one of the first memory array in the first array area or the second memory array in the second array area.

15. The method according to claim 14, wherein the second portion of the string driver overlaps with the connection region in the plan view.

16. The aforementioned row decoder is A first group of row decoders located on the first side of the string driver, A second group of row decoders located on the second side of the string driver, The method according to claim 14 or 15, comprising:

17. The first semiconductor structure comprises N memory blocks numbered from 0 to N-1, The first group of row decoders comprises a first row decoder coupled to a first string driver coupled to a word line in a first memory block associated with an odd number, The method according to claim 16, wherein the second group of row decoders comprises a second row decoder coupled to a second string driver coupled to a word line in a second memory block associated with an even number.

18. The method according to claim 17, wherein the first string driver and the second string driver are located between the first row decoder and the second row decoder along the first direction, and the odd and even numbers are adjacent integers.

19. The second semiconductor structure further comprises a first group of page buffers and a second group of page buffers, The row decoder and the string driver are located between the first group of the page buffer and the second group of the page buffer along the first direction. The first semiconductor structure further comprises bit lines coupled to the memory cells in the first memory array, The bit line is coupled to the corresponding page buffer of the first group of page buffers. The method according to any one of claims 14 to 18, wherein at least one portion of the bit lines is spaced apart from the corresponding page buffer along the first direction in the plan view.

20. A memory device, A first semiconductor structure comprising a first memory array in a first array region, a second memory array in a second array region, a contact structure in a connection region between the first array region and the second array region along a first direction, and a word line coupled to a memory cell in the first memory array and a memory cell in the second memory array, A second semiconductor structure equipped with a row decoder, Equipped with, The first semiconductor structure and the second semiconductor structure are stacked on top of each other along a second direction perpendicular to the first direction. At least a portion of the row decoder overlaps with at least one of the first memory array in the first array region or the second memory array in the second array region in a plan view perpendicular to the second direction, A controller configured to be coupled to the memory device and to control the memory device, A memory system equipped with the following features.

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