Formation and structure of OLED subpixel circuits

Abstract

Embodiments of the present disclosure provide a method for forming a subcircuit (e.g., a subpixel circuit). One exemplary subcircuit generally includes a backplane layer disposed on a substrate, a pixel defining layer (PDL) disposed on the backplane layer, the PDL exposing an anode disposed on the backplane layer and the substrate, and a plurality of walls disposed on the PDL, the plurality of walls defining a plurality of gaps, the plurality of walls and the plurality of gaps defining one or more unit pixels, and each of the one or more unit pixels comprises a subpixel. Each subpixel may include an anode defined by the PDL, an organic light-emitting diode (OLED) material disposed on the anode, and a cathode disposed on the OLED material and the plurality of walls.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 505,084, filed on May 31, 2023, which has been assigned to the assignee of this application and is hereby expressly incorporated by reference in its entirety herein for all applicable purposes as if fully set forth below.

[0002] The embodiments described herein generally relate to displays. More particularly, the embodiments described herein relate to sub - pixel circuits and methods of forming sub - pixel circuits that can be used in displays such as organic light - emitting diode (OLED) displays.

Background Art

[0003] Input devices including display devices may be used in various electronic systems. An organic light - emitting diode (OLED) is a light - emitting diode (LED) in which a light - emitting electroluminescent layer is a film of an organic compound that emits light in response to an electric current. An OLED device is classified as a bottom - emission device when the emitted light passes through a transparent or semi - transparent bottom electrode and the substrate on which the panel is manufactured. A top - emission device is classified based on whether the light emitted from the OLED device exits through a lid added after the device is manufactured. OLEDs are currently used to fabricate display devices for many electronic devices. An OLED device includes a plurality of sub - pixels (e.g., sub - pixel circuits) defined by adjacent pixel - defining layer (PDL) structures. Each sub - pixel has an anode, an OLED material disposed on the anode, and a cathode disposed on the OLED material. Many extended reality, virtual reality, and mixed reality applications require the use of OLED devices with high pixel density. However, current fine metal mask (FMM) and lithography techniques may not be suitable for forming OLED devices with high pixel density.

[0004] Therefore, what is needed in this field is an improved subpixel circuit and a method for forming it, which increases pixel density and improves OLED performance. [Overview of the Initiative]

[0005] Embodiments of the present disclosure provide a subcircuit. The subcircuit generally includes a backplane layer disposed on a substrate, a pixel definition layer (PDL) disposed on the backplane layer, the PDL exposing an anode disposed on the backplane layer and the substrate, and a plurality of walls disposed on the PDL, the plurality of walls defining a plurality of gaps, the plurality of walls and the plurality of gaps defining one or more unit pixels, and each of the one or more unit pixels includes a subpixel. Each subpixel may include an anode defined by the PDL, an organic light-emitting diode (OLED) material disposed on the anode, and a cathode disposed on the OLED material and the plurality of walls.

[0006] Embodiments of the present disclosure provide a method. The method generally includes the step of positioning a substrate having one or more unit pixels, wherein each of the one or more unit pixels includes a subpixel opening, each subpixel opening includes an anode defined by a plurality of PDL structures, each of the one or more unit pixels is partially surrounded by a plurality of walls, the plurality of walls define a plurality of gaps, and the plurality of walls and the plurality of gaps define one or more unit pixels. The method also generally includes the steps of: depositing a first portion of an OLED material in a first orientation on a first portion of one or more unit pixels, wherein the first orientation is formed by a first position on the substrate and a first orientation of the deposition source; depositing a second portion of an OLED material in a second orientation on a second portion of one or more unit pixels, wherein the second orientation is formed by a second position on the substrate and a second orientation of the deposition source; depositing a third portion of an OLED material in a third orientation on a third portion of one or more unit pixels, wherein the third orientation is formed by a third position on the substrate and a third orientation of the deposition source; and arranging a cathode on the first portion of the OLED material, the second portion of the OLED material, and the third portion of the OLED material.

[0007] Embodiments of the present disclosure provide a subcircuit. The subcircuit generally includes a substrate, a PDL disposed on the substrate, which exposes an anode disposed on the substrate, and a Y-shaped wall disposed on the PDL. The Y-shaped wall partially surrounds a unit pixel, which includes three subpixels.

[0008] Embodiments of the present disclosure provide a method. The method generally includes the step of positioning a substrate including a unit pixel, wherein the unit pixel comprises three subpixel apertures, each subpixel aperture comprising an anode defined by a plurality of PDL structures, and the unit pixel is partially surrounded by a Y-shaped wall. The method also generally includes the step of depositing an OLED material on three portions of the unit pixel, wherein the OLED material is deposited in three orientations, each orientation corresponding to a deposit at one of the three subpixel apertures.

[0009] To enable a more detailed understanding of the above-mentioned features of this disclosure, a more specific description of this disclosure, which has been briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only exemplary embodiments and should not be considered limiting in scope, as other equally valid embodiments may be recognized. [Brief explanation of the drawing]

[0010] [Figure 1A] This is a schematic cross-sectional view of a subpixel circuit according to one or more embodiments described herein. [Figure 1B] This is a schematic top view of a subpixel circuit according to one or more embodiments described herein. [Figure 2] This is a flowchart illustrating an exemplary method for forming a subpixel circuit according to one or more embodiments described herein. [Figure 3A] This is a schematic cross-sectional view of a subpixel circuit being formed according to one or more embodiments described herein. [Figure 3B] This is a schematic cross-sectional view of a subpixel circuit being formed according to one or more embodiments described herein. [Figure 3C]This is a schematic cross-sectional view of a subpixel circuit being formed according to one or more embodiments described herein. [Figure 3D] This is a schematic cross-sectional view of a subpixel circuit being formed according to one or more embodiments described herein. [Figure 3E] This is a schematic cross-sectional view of a subpixel circuit being formed according to one or more embodiments described herein. [Figure 3F] This is a schematic cross-sectional view of a subpixel circuit being formed according to one or more embodiments described herein. [Figure 3G] This is a schematic cross-sectional view of a subpixel circuit being formed according to one or more embodiments described herein. [Figure 3H] This is a schematic cross-sectional view of a subpixel circuit being formed according to one or more embodiments described herein. [Figure 3I] This is a schematic cross-sectional view of a subpixel circuit being formed according to one or more embodiments described herein. [Figure 3J] This is a schematic cross-sectional view of a subpixel circuit being formed according to one or more embodiments described herein. [Figure 4A] This is a schematic top view of a subpixel circuit during a deposition process according to one or more embodiments described herein. [Figure 4B] This is a schematic top view of a subpixel circuit during a deposition process according to one or more embodiments described herein. [Figure 4C] This is a schematic top view of a subpixel circuit during a deposition process according to one or more embodiments described herein. [Modes for carrying out the invention]

[0011] For ease of understanding, the same reference numerals are used to indicate identical elements common to the drawings, where possible. It is intended that elements and features of one embodiment can be usefully incorporated into other embodiments without further detail.

[0012] Embodiments of this disclosure generally relate to displays including organic light-emitting diodes (OLEDs) and methods for forming the same. More specifically, embodiments provided herein generally relate to subpixel circuits and methods for forming subpixel circuits that can be used in OLED displays. OLED displays disclosed herein can be used in any device including a display, including augmented reality, virtual reality, and mixed reality devices, as well as other devices with displays, including mobile phones and televisions.

[0013] In some embodiments, a subpixel circuit may include several unit pixels, each unit pixel containing several subpixels arranged in a triangular array. Each subpixel may have an OLED material configured to emit white, red, green, blue, or other colored light when energized. For example, the OLED material of the first subpixel may emit red light when energized, the OLED material of the second subpixel may emit green light when energized, and the OLED material of the third subpixel may emit blue light when energized. That is, each of the three subpixels may be configured to emit a different color when energized. Each unit cell may be partially surrounded by several walls, each wall partially separating adjacent unit pixels and forming some gaps between adjacent unit pixels. In some embodiments, one or more walls may be Y-shaped self-masks. One or more walls may not be literally Y-shaped. One or more of the walls may be of various other shapes and / or include various curves. The shape and / or curves of the walls may be manipulated to allow the formation of a desired subpixel circuit. In some embodiments, one or more walls may include walls having different shapes and / or curves. Gaps between adjacent walls allow the current path of the subpixel circuit to be continuous through the cathode of the subpixel circuit. In addition, the subpixel circuit may be formed using oblique deposition for the deposition of red, green, and blue light-emitting material (EML) layers. The deposition process may include a vapor deposition process. As a result, the thickness of the deposited OLED material may not increase material consumption. Furthermore, the deposition angles (including emission angles and vapor deposition angles) used during the deposition of the OLED material may be carefully controlled during the formation of subpixels in the subpixel circuit. Controlling the deposition angle results in the formation of more stable aperture regions (e.g., regions where OLED material is deposited) and shadow regions (e.g., regions where OLED material is not deposited as a result of walls).

[0014] Embodiments of the present disclosure can result in subpixel circuits formed without using conventional fine metal masks (FMM) and lithography techniques. Additionally, displays utilizing the formation and structure of the subpixel circuits disclosed herein also benefit from an improvement in pixel density (PPI).

[0015] FIG. 1A is a schematic cross-sectional view of a subpixel circuit 100 according to one or more embodiments described herein. The subpixel circuit 100 can represent an active region of a panel. The subpixel circuit 100 includes a substrate 102 and a metal layer 104 disposed on the substrate 102. The metal layer 104 is implemented as a backplane layer and / or may be referred to as a backplane layer. The backplane layer can control the amount of current required for subpixel emission. FIG. 1B is a schematic top view of the subpixel circuit 100 according to one or more embodiments described herein. The arrows labeled 1A in FIG. 1A correspond to the arrows labeled 1A in FIG. 1B. Accordingly, FIGS. 1A and 1B are described together for clarity.

[0016] The substrate 102 can include, but is not limited to, silicon (Si), silicon dioxide (SiO2), fused silica, quartz, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), indium phosphide (InP), gallium arsenide (GaAs), gallium nitride (GaN), silicon nitride (Si3N4), or a sapphire-containing material. The metal layer 104 may be implemented as a thin film transistor (TFT) layer. The metal layer 104 can include, but is not limited to, chromium, titanium, gold, silver, copper, aluminum, indium tin oxide (ITO), combinations thereof, or other suitable conductive materials. The metal layer 104 may be transparent or reflective depending on whether the subpixel circuit 100 is utilized as a bottom emission display or a top emission display.

[0017] In some embodiments, the pixel definition layer (PDL) structure 106 may be disposed on the metal layer 104 and the substrate 102. The opening of the PDL structure 106 exposes the anode 114 of the metal layer 104. In some embodiments, the PDL structure 106 includes an inorganic insulator material. The inorganic insulator material can include, but is not limited to, SiO2, Si3N4, silicon oxynitride (Si2N2O), magnesium fluoride (MgF2), or combinations thereof. The sub-pixel circuit 100 includes one or more unit pixels 118. Each of the one or more unit pixels 118 includes an anode 114 of the metal layer 104 defined by an adjacent PDL structure 106. In some cases, the PDL structure 106 can include one or more tapered surfaces 322 (having corresponding taper angles), as shown in FIG. 3A. Although the tapered surface 322 is shown only in FIG. 3A, the tapered surface 322 may be included in the PDL structure 106 of any other figure and embodiment in the present application.

[0018] As shown in FIGS. 1A and 1B, the sub-pixel circuit 100 can include some walls (e.g., self-mask walls) 121 disposed at the boundaries between adjacent unit pixels 118. In some embodiments, the walls 121 are disposed on the PDL structure 106. In other embodiments, the walls 121 are disposed on the metal layer 104 and the substrate 102. In embodiments where the walls 121 are disposed on the metal layer 104 and the substrate 102, the sub-pixel circuit 100 does not include the PDL structure 106.

[0019] The wall 121 may be a Y-shaped wall, as shown in the figure. The wall 121 may not be literally Y-shaped. The wall 121 may be of various other shapes and / or may include various curves. The shape and / or curves of the wall 121 may be manipulated to allow the formation of a desired subpixel circuit. In some embodiments, the wall 121 may include walls having different shapes and / or curves. The aspect ratio of the wall 121 can be defined as the ratio of the height of the wall 121 to the width of the wall 121, and may be between 1:1 and 10:1. For example, the aspect ratio (height to width) may be 6:1. The wall 121 may partially surround each unit pixel 118, leaving a gap 125 between adjacent walls, as also shown in Figure 1B. Each unit pixel 118 may contain multiple subpixels 119. For example, each unit pixel 118 may contain three subpixels 119A, 119B, and 119C, as shown in Figure 1B. In some embodiments, the integrated subpixels 119A, 119B, and 119C of each unit pixel 118 may be arranged in a triangular array. Each subpixel 119A, 119B, and 119C may be diamond-shaped to maximize the resulting aperture ratio.

[0020] One or more of the hole injection layer (HIL), hole transport layer (HTL), electron injection layer (EIL), and electron transport layer (ETL) may be located on at least a portion of the subpixel circuit 100. In the examples shown in Figures 1A and 3A-3J, the subpixel circuit 100 includes one or both of the HIL and HTL, indicated as the anode delimiting layer (ADL) 108. The ADL 108 is also called the common layer. The ADL 108 may include one or more of the hole injection layer (HIL) and hole transport layer (HTL). In this example, the ADL 108 is located on each unit pixel 118 and each wall 121 of the subpixel circuit 100 by using a common metal mask 302.

[0021] Each unit pixel 118 may contain organic light-emitting diode (OLED) material 120. The OLED material 120 may be placed on top of an ADL 108 (including one or both of the HIL and HTL). In some embodiments, the OLED material 120 is also placed on an adjacent PDL structure 106. The OLED material 120 can be deposited via an oblique deposition process. In some embodiments, the oblique deposition process may include a vapor deposition process. The deposition angle set by the wall 121 and the deposition source 304 defines the deposition angle (for example, the wall 121 provides a shadowing effect during the deposition of the OLED material 120 at the deposition angle set by the deposition source 304). To deposit at a specific angle, the deposition source 304 is configured to emit the OLED material 120 at a specific angle relative to the wall 121. By manipulating the orientation of one or both of the deposition source 304 and the subpixel circuit 100, the deposition angle can be adjusted so that the deposition source 304 deposits the OLED material 120 at different angles, thereby adjusting where the OLED material 120 is positioned on the subpixel circuit 100.

[0022] The OLED material 120 is configured to emit white, red, green, blue, or other colored light when energized. For example, the OLED material 120 of each subpixel 119A, 119B, 119C of a unit pixel 118 is configured to emit one of the red light colors, or green light, or blue light, or white light when energized. That is, each of the three subpixels may be configured to emit a different color when energized. In the examples shown in Figures 1A, 1B, and 3A-3J, each unit pixel 118 in the subpixel circuit 100 includes a subpixel 119A configured to emit red light when energized, a subpixel 119B configured to emit green light, and a subpixel 119C configured to emit blue light when energized. However, the OLED material 120 of each subpixel 119A, 119B, 119C of each unit pixel 118 may be configured to emit light of any color when energized, if necessary.

[0023] One or more of the EIL and ETL may be placed on top of the OLED material 120. In the examples shown in Figures 1A and 3A to 3J, the subpixel circuit includes one or both of the EIL and ETL, indicated as layer 109. In this example, layer 109 is placed on each unit pixel 118 and each wall 121 of the subpixel circuit 100 by using a common metal mask 302. In some embodiments, one or more of the EIL and ETL may be included in the OLED material 120.

[0024] The cathode 124 may be located on top of layer 109 (including one or both of ETL and EIL). The cathode 124 comprises a conductive material such as a metal. For example, the cathode 124 may include, but is not limited to, chromium, titanium, aluminum, ITO, or a combination thereof. In some embodiments, the cathode 124 may include a mixture of silver (Ag) and magnesium (Mg). In this configuration, the cathode 124 contacts the busbar 127 outside the active region of the subpixel circuit 100.

[0025] The subpixel circuit 100 may include a first encapsulation layer 126 (e.g., a thin-film encapsulation (TFE) layer) positioned on the cathode 124. The first encapsulation layer 126 may be a local passivation layer or equivalent. The first encapsulation layer 126 for each unit pixel 118 is positioned on the cathode 124 (and OLED material 120) and the PDL structure 106. The first encapsulation layer 126 includes a non-conductive inorganic material such as a silicon-containing material. The silicon-containing material may include a Si3N4-containing material.

[0026] The subpixel circuit 100 may include plugs 122 positioned on the first encapsulation layer 126. The plugs 122 may include a photoresist, a color filter, or a photosensitive monomer. The plugs 122 have a plug transmittance that matches or substantially matches the OLED transmittance of the OLED material 120. Each plug 122 may be made of the same material and can match the OLED transmittance. The plugs 122 may be made of different materials to match the OLED transmittance of each of the subpixels 119A, 119B, and 119C. The matching or substantially matching of the resist transmittance and the OLED transmittance allows the plugs 122 to remain on the subpixels 119A, 119B, and 119C without obstructing the light emitted from the OLED material 120. The plugs 122 can remain in place and therefore do not require a lift-off procedure for removal from the subpixel circuit 100. In some embodiments, the plugs 122 may be an inkjet layer. The inkjet layer may include an acrylic material.

[0027] The subpixel circuit 100 may include a second encapsulation layer 130 positioned on top of the plug 122. The second encapsulation layer 130 may be a local passivation layer or equivalent. The second encapsulation layer 130 for each unit pixel 118 is positioned on top of the cathode 124 (and OLED material 120) and the PDL structure 106. The second encapsulation layer 130 includes a non-conductive inorganic material such as a silicon-containing material. The silicon-containing material may include a Si3N4-containing material. In some embodiments, the subpixel circuit 100 further includes a source / drain (S / D) pad 129. The S / D pad 129 may represent a representative electrode for signal input.

[0028] An example of current flow for activating multiple subpixels 119A, 119B, and 119C within the subpixel circuit 100 is shown by line 123 in Figure 1B. As shown in Figure 1B, the current flows through the gap 125 in the subpixel circuit 100, which allows for a continuous current path through the cathode 124. The current flows from the cathode 124, which is positioned along the subpixel circuit 100, to the busbar 127. Thus, the current is operable to flow through the subpixel circuit 100. The current also flows from the cathode 124 to the OLED material 120 and into the metal layer 104 of the subpixel circuit 100. The current supplied to the metal layer 104 enables the activation of the subpixels 119A, 119B, and 119C within the subpixel circuit 100.

[0029] The subpixels 119A, 119B, and 119C of the unit pixel 118 are operable to emit light. The subpixel circuit 100 is operable to activate each unit pixel 118 individually and independently. In some embodiments, the subpixels 119A, 119B, and 119C of each unit pixel 118 are monochromatic. In other embodiments, each of the subpixels 119A, 119B, and 119C of the unit pixel 118 is operable to emit light of a different color.

[0030] Figure 2 is a flowchart showing an exemplary method 200 for forming a subpixel circuit 100 according to one or more embodiments described herein. Figures 3A to 3J are schematic cross-sectional views of one or more subpixel circuits 100 in the process of being formed as shown in Figure 2, according to one or more embodiments described herein. Therefore, Figures 2 and 3A to 3J are described together herein for clarity. It is assumed that the metal layer 104 is pre-disposed on the substrate 102 and that the PDL structure 106 is also pre-disposed on the metal layer 104. The metal layer 104 may be patterned on the substrate 102. In some embodiments, the metal layer 104 is pre-patterned on the substrate 102. For example, the substrate 102 is a pre-patterned ITO glass substrate. In addition, it is assumed that a plurality of walls (e.g., self-mask walls) 121 are pre-formed on the boundaries between adjacent unit pixels 118, and that the openings of the PDL structure 106 expose the anodes 114 of the metal layer 104. The openings in the PDL structure 106 that expose the anode 114 of the metal layer 104 may be called subpixel openings before the deposition of the OLED material 120 (e.g., operations 206, 208, 210). In some cases, the PDL structure 106 may include one or more tapered surfaces 322 (having corresponding taper angles), as shown in Figure 3A. Although the tapered surfaces 322 are shown only in Figure 3A, the tapered surfaces 322 may be included in the PDL structure 106 of any other figures and embodiments in this application. The wall 121 may include dielectric material and / or may be Y-shaped, as shown in Figure 1B. As stated above, the wall 121 does not have to be literally Y-shaped. The wall 121 may be of various other shapes and / or may include various curves. The shape and / or curve of the wall 121 may be manipulated to allow the formation of a desired subpixel circuit (e.g., for deposition of the OLED material 120 and having a continuous current path, as described herein). In some embodiments, the wall 121 may include walls having different shapes and / or curves. The aspect ratio of the wall 121 can be defined as the ratio of the height of the wall 121 to the width of the wall 121, and may be between 1:1 and 10:1.For example, the aspect ratio (height to width) may be 6:1. The subpixel circuit 100 also already includes a busbar 127 and an S / D pad 129.

[0031] In operation 202, a plasma pretreatment is performed on the subpixel circuit 100, as shown in Figure 3A. The plasma treatment conditions may vary depending on the desired subpixel circuit 100. The plasma treatment may include two steps. The first step may include the use of a mixture of nitrogen (N2) and oxygen (O2) gases. The second step may include the use of a mixture of N2 and hydrogen (H2).

[0032] In operation 204, the ADL 108 is placed on the substrate 102 and the multiple metal layers 104, as shown in Figure 3B. In some embodiments, the ADL 108 is placed on the substrate 102 and the multiple metal layers 104 using a common metal mask 302. In some embodiments, the ADL 108 is further patterned to expose the anodes 114 of the multiple metal layers 104. In other embodiments, the ADL 108 exposes the anodes 114 of the multiple metal layers 104. Each of the anodes 114 is associated with a discrete unit pixel 118 that is formed, such as the multiple unit pixels 118 shown in Figure 1A. The ADL 108 can be patterned by patterning a photoresist coating and then etching it. As described above, the ADL 108 may include one or more of the hole injection layers (HILs) and hole transport layers (HTLs). In some embodiments, one or more of the HILs and HTLs may be included in the OLED material 120.

[0033] In operation 206, as shown in Figure 3C, a first portion of the OLED material 120 can be deposited on at least a portion of the ADL 108 in a first orientation. The first orientation may be formed by a first position on the substrate 102 and a first orientation of the deposition source 304 relative to the wall 121. At least a portion of the ADL 108 may be associated with at least a portion of the unit pixels 118 (e.g., unit cells). The first portion of the OLED material 120 can be deposited via a deposition process. In some embodiments, the deposition may include an oblique deposition process. When using an oblique deposition process, material conservation (e.g., oblique deposition does not increase material consumption) may mean that, assuming the same scanning speed, the thickness of the deposited OLED material 120 may not depend on the deposition angle. The oblique deposition process may include using the position of the wall 121 and the orientation of the deposition source (e.g., deposition nozzle) 304, as well as the position of the subpixel circuit 100. The deposition angle (including the emission angle 306 and deposition angle 308) set by the wall 121 and the deposition source 304 defines the deposition angle (for example, the wall 121 provides a shadowing effect during the deposition of the first portion of the OLED material 120 at the deposition angle set by the deposition source 304). To deposit at a specific angle, the deposition source 304 is configured to emit the first portion of the OLED material 120 at a specific angle relative to the wall 121. By adjusting the deposition angle by manipulating the orientation of one or both the deposition source 304 and the subpixel circuit 100, the deposition source 304 can deposit the first portion of the OLED material 120 at different angles, thereby adjusting where the first portion of the OLED material 120 is positioned on the subpixel circuit 100.

[0034] In some embodiments, the deposition process used to deposit a first portion of the OLED material 120 may include a number of suboperations, and the deposition source 304 and / or subpixel circuit 100 may be oriented differently during various suboperations of operation 206 so that the first portion of the OLED material 120 can be deposited at the desired position on each unit pixel 118. In addition, arranging the subpixels 119A of each unit pixel 118 in a triangular array may also help to deposit the first portion of the OLED material 120 at the desired position. In some cases, the deposition process may create a shadow on the portion of the unit pixel 118 being formed, so that the first portion of the OLED material 120 can be deposited on the portion of the unit pixel 118 that is not covered by the shadow. For example, the first portion of the OLED material 120 can be deposited on the formed subpixel 119A of the unit pixel 118 rather than on the formed subpixels 119B and 119C, as shown in Figure 3C. The first OLED material 120 can also be deposited on some portions of the unit pixel 118 as a result of the gaps 125 in the wall 121. In this example, the first portion of the placed OLED material 120 is configured to emit red light when energized. A common metal mask 302 may be used during the deposition of the first portion of the OLED material 120.

[0035] Figures 4A, 4B, and 4C are schematic top views of the subpixel circuit 100 during the deposition process of operations 206, 208, and 210 according to one or more embodiments described herein. The arrows labeled 3C, 3D, and 3E in Figures 4A, 4B, and 4C correspond to the arrows labeled 4A, 4B, and 4C in Figures 3C, 3D, and 3E, respectively. In some embodiments, by placing a first portion of the OLED material 120 on at least a portion of the ADL 108, the formation of a stable aperture region 402 (e.g., a region where the OLED material is deposited) and a stable shadow region 404 (e.g., a region where the OLED material is not deposited as a result of a wall) is brought about, as shown in Figure 4A. Between the aperture region 402 and the shadow region 404, there may be a region (e.g., a process margin) where the first portion of the deposited OLED material 120 forms a gradient (not shown). The deposition of the second and third portions of the OLED material 120 also results in the formation of stable aperture regions 402 (e.g., regions where the OLED material is deposited) and stable shadow regions 404 (e.g., regions where the OLED material is not deposited as a result of walls), as shown in Figures 4B and 4C, respectively. Between the aperture regions 402 and the shadow regions 404, there may be regions (e.g., process margins) where the deposited OLED material 120 forms a gradient (not shown). The orientation of the deposition source 304 and the position of the subpixel circuits 100 can be controlled throughout operations 206, 208, and 210 to achieve a favorable process margin.

[0036] In operation 208, as shown in Figure 3D, a second portion of the OLED material 120 may be positioned in a second orientation on at least a portion of the ADL 108. The second orientation may be formed by a second position of the substrate 102 and a second orientation of the deposition source 304 relative to the wall 121. In some embodiments, operation 208 is the same as or substantially the same as operation 206 described above. In some cases, the deposition process can create a shadow over the portion of the unit pixel 118 that is formed, and the second portion of the OLED material 120 can be deposited on the portion of the unit pixel 118 that is not covered by the shadow. For example, the second portion of the OLED material 120 can be deposited on the subpixel 119B of the unit pixel 118 that is formed, rather than on the subpixels 119A and 119C that are formed, as shown in Figure 3D. The second portion of the OLED material 120 can also be deposited on a portion of the unit pixel 118 as a result of the gap 125 in the wall 121. In some embodiments, there may be some overlap between the first portion of the OLED material 120 and the second portion of the OLED material 120 (not shown). Furthermore, the placed second portion of the OLED material 120 is configured to emit green light when energized. A common metal mask 302 may be used during the deposition of the second portion of the OLED material 120.

[0037] In operation 210, as shown in Figure 3E, a third portion of the OLED material 120 may be positioned in a third orientation on at least a portion of the ADL 108. The third orientation may be formed by a third position of the substrate 102 and a third orientation of the deposition source 304 relative to the wall 121. In some embodiments, operation 210 is the same as or substantially the same as operation 206 described above. In some cases, the deposition process can create a shadow over the portion of the unit pixel 118 that is formed, and the third portion of the OLED material 120 can be deposited on the portion of the unit pixel 118 that is not covered by the shadow. For example, the third portion of the OLED material 120 can be deposited on the subpixel 119C of the unit pixel 118 that is formed, rather than on the subpixels 119A and 119B that are formed, as shown in Figure 3E. The third OLED material 120 can also be deposited on a portion of the unit pixel 118 as a result of the gap 125 in the wall 121. In some embodiments, there may be some overlap between the first portion of the OLED material 120 and the second portion of the OLED material 120 (not shown). Furthermore, the placed third portion of the OLED material 120 is configured to emit blue light when energized. A common metal mask 302 may be used during the deposition of the third portion of the OLED material 120.

[0038] In operation 212, one or more of the EIL and ETL (indicated as layer 109) may be placed on top of the OLED material 120, as shown in Figure 3F. In some embodiments, one or more of the EIL and ETL may be included in the OLED material 120. A common metal mask 302 may be used during the deposition of layer 109.

[0039] In operation 214, the cathode 124 may be placed on top of layer 109 (including one or both of ETL and EIL), as shown in Figure 3G. As described above, the cathode 124 includes a conductive material such as a metal. For example, the cathode 124 may include, but is not limited to, chromium, titanium, aluminum, ITO, or a combination thereof. A cathode opening mask 312 may be used during the deposition of the cathode 124.

[0040] In operation 216, a first encapsulation layer 126 (e.g., a thin film encapsulation (TFE) layer) may be placed on top of the cathode 124, as shown in Figure 3H. As described above, the first encapsulation layer 126 may be a local passivation layer or equivalent. The first encapsulation layer 126 for each unit pixel 118 is placed on top of the cathode 124 (and OLED material 120) and the PDL structure 106. The first encapsulation layer 126 contains a non-conductive inorganic material such as a silicon-containing material. The silicon-containing material may include a Si3N4-containing material. An encapsulation layer mask 314 may be used during the deposition of the first encapsulation layer 126.

[0041] In operation 218, the plug 122 may be placed on the first encapsulation layer 126, as shown in Figure 3I. As described above, the plug 122 may include a photoresist, a color filter, or a photosensitive monomer. The plug 122 has a plug transmittance that matches or substantially matches the OLED transmittance of the OLED material 120. The plugs 122 may each be made of the same material and can match the OLED transmittance. The plugs 122 may be made of different materials that match the OLED transmittance of each of the subpixels 119A, 119B, 119C. The matching or substantially matching of the resist transmittance and the OLED transmittance allows the plug 122 to remain on the subpixels 119A, 119B, 119C without obstructing the light emitted from the OLED material 120. The plug 122 can remain in place and therefore does not require a lift-off procedure to remove it from the subpixel circuit 100. In some embodiments, the plug 122 may be an inkjet layer. The inkjet layer may contain acrylic material.

[0042] In operation 220, a second encapsulation layer 130 (e.g., a thin-film encapsulation (TFE) layer) may be placed on top of the plug 122, as shown in Figure 3J. As described above, the second encapsulation layer 130 may be a local passivation layer or equivalent. The second encapsulation layer 130 for each unit pixel 118 is placed on top of the cathode 124 (and OLED material 120) and the PDL structure 106. The second encapsulation layer 130 contains a non-conductive inorganic material such as a silicon-containing material. The silicon-containing material may include a Si3N4-containing material. An encapsulation layer mask 314 may be used during the deposition of the second encapsulation layer 130.

[0043] In summary, by forming subpixel circuits 100 using shadowing effects resulting from the position of the walls 121, the orientation of the deposition source 304 used to deposit the OLED material 120, and the position of the substrate 102, the formation of more stable aperture regions (e.g., regions where the OLED material 120 is deposited) and shadow regions (e.g., regions where the OLED material 120 is not deposited as a result of the walls 121) can be achieved. In addition, the gaps 125 between adjacent walls 121 of the subpixel circuits can enable continuous current paths through subpixels 119A, 119B, and 119C along the cathodes 124 of the subpixel circuits 100. The subpixel circuits 100 can also be formed without using conventional fine metal masks (FMMs) and lithography techniques, and the pixel density (PPI) can be increased.

[0044] While the above applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure can be devised without departing from its basic scope, the scope of which is determined by the following claims.

Claims

1. A backplane layer placed on the substrate, A plurality of walls arranged on the backplane layer, wherein the plurality of walls define a plurality of gaps, the plurality of walls and the plurality of gaps define one or more unit pixels, and each of the one or more unit pixels comprises a subpixel, each subpixel is anode, An organic light-emitting diode (OLED) material disposed on the anode, and The OLED material and the cathodes arranged on the plurality of walls Equipped with, Multiple walls, A sub-circuit equipped with this.

2. The subcircuit according to claim 1, wherein the plurality of walls include at least one Y-shaped wall.

3. The subcircuit according to claim 1, wherein the plurality of gaps are configured to allow a continuous current path through each subpixel of the one or more unit pixels.

4. The subcircuit according to claim 3, wherein each subpixel of the one or more unit pixels comprises a encapsulation layer disposed on the cathode.

5. The subcircuit according to claim 1, wherein each of the one or more unit pixels includes three subpixels, and the three subpixels are arranged in a triangular array.

6. The subcircuit according to claim 5, wherein each of the three subpixels is configured to emit a different color when energized.

7. A step of positioning a substrate including one or more unit pixels, wherein each of the one or more unit pixels includes a subpixel opening, each subpixel opening includes an anode, each of the one or more unit pixels is partially surrounded by a plurality of walls, the plurality of walls define a plurality of gaps, and the plurality of walls and the plurality of gaps define the one or more unit pixels; A step of depositing a first portion of an OLED material on a first portion of one or more unit pixels in a first orientation, wherein the first orientation is formed by a first position on the substrate and a first orientation of the deposition source, A step of depositing a second portion of an OLED material on a second portion of one or more unit pixels in a second orientation, wherein the second orientation is formed by a second position on the substrate and a second orientation of the deposition source, A step of depositing a third portion of an OLED material on a third portion of one or more unit pixels in a third orientation, wherein the third orientation is formed by a third position on the substrate and a third orientation of the deposition source, The steps include placing a cathode on the first part of the OLED material, the second part of the OLED material, and the third part of the OLED material, Methods that include...

8. The method according to claim 7, wherein the first portion of the OLED material, the second portion of the OLED material, and the third portion of the OLED material are deposited using an oblique deposition process.

9. The method according to claim 7, wherein the ratio of the height of the plurality of walls to the width of the plurality of walls is between 1:1 and 10:

1.

10. The method according to claim 7, wherein the plurality of walls include at least one Y-shaped wall.

11. The method according to claim 10, wherein the first orientation is formed by the first position of the substrate and the first orientation of the deposition source with respect to the at least one Y-shaped wall.

12. circuit board and A pixel definition layer (PDL) disposed on the substrate, the PDL exposing the anodes disposed on the substrate, A Y-shaped wall positioned on the PDL, wherein the Y-shaped wall partially surrounds a unit pixel, and the unit pixel contains three subpixels. A sub-circuit equipped with this.

13. The subcircuit according to claim 12, wherein a first portion of an organic light-emitting diode (OLED) material is arranged on a first portion of the unit pixel, and the first portion of the OLED material arises from a first position of the substrate during deposition and a first orientation of the deposition source with respect to the Y-shaped wall.

14. The subcircuit according to claim 12, wherein the three subpixels are arranged in a triangular array.

15. The subcircuit according to claim 12, wherein the Y-shaped wall is configured to allow a continuous current path through each subpixel of the unit pixel.

16. The subcircuit according to claim 12, wherein each of the three subpixels is configured to emit a different color when energized.

17. A step of positioning a substrate containing a unit pixel, wherein the unit pixel contains three subpixel openings, each subpixel opening contains an anode defined by a plurality of pixel definition layer (PDL) structures, and the unit pixel is partially surrounded by a Y-shaped wall; A step of depositing OLED material on three parts of the unit pixel, wherein the OLED material is deposited in three orientations, and each orientation corresponds to the deposition at one of the three subpixel openings. Methods that include...

18. The method according to claim 17, wherein one of the three orientations is formed by the first position of the substrate and the first orientation of the deposition source with respect to the Y-shaped wall.

19. The method according to claim 17, wherein the OLED material is deposited using an oblique deposition process.

20. The method according to claim 17, wherein the ratio of the height of the Y-shaped wall to the width of the Y-shaped wall is between 1:1 and 10:1.

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