Method for measuring the resistance and capacitance of a thin film during deposition.

Abstract

The present invention relates to a method for producing a chip (40) for depositing a thin film, a) - A step of forming a plurality of measuring electrodes (2) on a substrate (4) of an insulating or semiconductor material, wherein each electrode has a central portion and an end portion that is inclined toward the surface of the substrate (4). b) - A step of forming a deposition mask (6) that defines a deposition window (8), wherein the mask includes notches (10) in the vicinity of the substrate and the window. This includes methods.

Claims

1. A method for fabricating a chip (40) for depositing a thin film, a) - A step of forming a plurality of measuring electrodes (2) on an insulating or semiconductor substrate (4), wherein each electrode has a central portion and an end portion (2) that is inclined toward the surface of the substrate (4). 1 , 2 2 ) a process having b) - A step of forming a non-conductive deposition mask (6) that defines a deposition window (8) between the edges of the resin mask (6) above the electrode (2) and on the surface of the substrate (4), wherein the mask includes a notch (10) near the substrate and the deposition window. Methods that include...

2. The method according to claim 1, further comprising the step of fabricating a protective electrode (12) between a mask (6) and a substrate (4).

3. The method according to claim 2, wherein the protective electrode has a resistance greater than 1 MΩ.

4. The method according to claim 2 or 3, wherein the protective electrode is made of chromium and / or has a thickness of 3 nm to 100 nm.

5. The method according to any one of claims 1 to 4, wherein the substrate (4) is made of silicon, quartz, or sapphire.

6. The substrate has a surface roughness R of 0.01 nm to 1 nm. A The method according to any one of claims 1 to 5, comprising:

7. The method according to any one of claims 1 to 6, wherein the measuring electrode (2) is made of Ti / Au.

8. The method according to any one of claims 1 to 5, further comprising the step of manufacturing a protective layer (30) for a substrate.

9. The method according to any one of claims 1 to 8, wherein the deposition window (8) has an orientation perpendicular to the orientation of at least a portion of the measuring electrode (2).

10. The method according to any one of claims 1 to 9, wherein the electrode (2) is produced by evaporation at a certain angle.

11. The electrode (2) has an end (2) that forms a lateral slope at an angle of less than 80° with respect to the surface of the substrate, for example, 15° to 60°. 1 , 2 2 The method according to any one of claims 1 to 10, having )

12. The method according to any one of claims 1 to 11, comprising a preceding step of planarizing the surface of a substrate (4).

13. A chip (40) for depositing thin films, a) Substrate made of insulating or semiconductor material (4) b) A plurality of measuring electrodes (2) on the substrate (4), each electrode having a central portion and an end portion (2) that is inclined toward the surface of the substrate (4). 1 , 2 2 Multiple measuring electrodes (2) having ) c) A nonconductive deposition mask (6) that defines a deposition window (8) located above the electrode (2) and on the surface of the substrate (4) between the edges of the resin mask (6), wherein the mask includes a notch (10) near the substrate and the deposition window. Including, tips.

14. The chip according to claim 13, further comprising a protective electrode (12) between the mask (6) and the substrate (4).

15. The chip according to claim 14, wherein the protective electrode has a resistance greater than 1 MΩ.

16. The chip according to claim 14 or 15, wherein the protective electrode is made of chromium and / or has a thickness of 3 nm to 10 nm.

17. The chip according to any one of claims 13 to 16, wherein the substrate (4) is made of silicon, chromium, or sapphire.

18. The chip according to any one of claims 13 to 17, wherein the measuring electrode (2) is made of Ti / Au.

19. The chip according to any one of claims 13 to 18, further comprising a protective layer (30) for the substrate.

20. The tip according to any one of claims 13 to 19, wherein the deposition window (8) has an orientation perpendicular to the orientation of at least a portion of the measuring electrode (2).

21. The electrode (2) has an end portion (2 1 , 2 2 ) that forms a lateral slope with an angle of less than 80°, for example 15° to 60°, for the chip according to any one of claims 13 to 20.

22. A method for depositing a so-called thin layer, comprising the steps of depositing a layer in a deposit window (8) of a chip according to any one of claims 13 to 21, and measuring at least one electric quantity at the terminals of at least two measuring electrodes (2).

23. The method according to claim 22, wherein a layer obtained by sputtering, chemical vapor deposition, electron gun, co-evaporation, or co-sputtering is deposited.

24. The deposited layers, - A metallic layer formed from elements selected from gold, silver, copper, platinum, iridium, titanium, vanadium, niobium, tantalum, chromium, etc. - Or, for example, granular aluminum (Al + O 2 ), or a metallic layer formed from elements in the presence of a reactive gas (oxygen and / or nitrogen and / or hydrogen), such as aluminum nitride, titanium nitride, niobium nitride, or silicon hydride. - Or deposition of niobium-silicon, yttrium-silicon, or nickel-chromium alloy, - Or a tunnel junction containing two metal deposits separated by an insulating barrier, e.g., Al-AlO x -Al, or Nb-Al-AlO x -Al-Nb Josephson junction, - Alternatively, an insulating or semiconducting layer such as Si, Si-O, Si-H, or Ge can be used, in which case the capacitance and resistance of the layer can be measured simultaneously. The method according to claim 22 or 23, which forms

25. The method according to any one of claims 22 to 24, wherein the deposited layer has a thickness of 1 nm to 200 nm.

26. The method according to any one of claims 22 to 24, wherein the deposited layer has a thickness of 1 nm to 60 nm.

27. A method for preparing a sample comprising multiple films or layers, comprising performing the method according to any one of claims 22 to 26 simultaneously with the deposition of each film or layer.

28. A method for etching a layer fabricated in a window (8) of a chip according to any one of claims 13 to 21, comprising the steps of etching the layer and measuring at least one electric quantity at the terminals of at least two measuring electrodes (2).

29. The method according to any one of claims 22 to 29, wherein when the amount of electricity reaches a target value, the deposition or etching of the layer is stopped.

30. The method according to any one of claims 22 to 29, wherein the measurement of at least one electrical quantity is performed using a micro connector, for example, a micro USB connector.

31. The method according to any one of claims 22 to 30, wherein at least one electric quantity to be measured is the conductivity or electrical resistance of a layer produced by depositing or etching it partially on a substrate (4) and partially on an electrode (2).

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