3D NAND mixed word line contacts and through array via regions

Abstract

Systems, apparatus, and methods may provide techniques for arranging word line access structures for memory devices. A memory device includes a memory array and memory blocks coupled to the memory array. Each memory block includes multiple word lines that penetrate multiple decks of a non-volatile memory structure. Multiple through-array vias penetrate multiple decks, and the multiple through-array vias and multiple word lines are intermingled within a shared word line access structure region. Additionally or alternatively, memory devices are manufactured based on word line contact patterning, forming multi-level via holes that penetrate multiple decks of the non-volatile memory structure of the memory device. Metal films are deposited to fill the via holes and form word line contacts.

Claims

1. Memory array and, A memory device comprising a memory block coupled to the memory array, wherein the memory block is Multiple word lines that penetrate multiple decks of non-volatile memory structure, A memory device comprising a plurality of through array vias penetrating the plurality of decks, wherein the plurality of through array vias and the plurality of word lines are mixed within a shared word line access structure region.

2. The memory device according to claim 1, wherein the plurality of through array vias and the plurality of word lines are mixed such that a first word line among the plurality of word lines is located between a first through array via and a second through array via in the shared word line access structure region.

3. The memory device according to claim 1, wherein the plurality of through array vias and the plurality of word lines are mixed such that the first row of the plurality of word lines is located between the first row of the through array vias and the second row of the through array vias in the shared word line access structure region.

4. The memory device according to claim 1, wherein the plurality of word lines penetrate the plurality of decks within a variable depth pattern, while the plurality of through array vias penetrate the plurality of decks at a common depth.

5. The memory device according to claim 1, wherein the shared word line access structure region does not have a 3D NAND staircase structure.

6. The memory device according to claim 1, wherein the memory device comprises a 3D NAND.

7. The memory controller, A system comprising a multi-deck non-volatile memory structure coupled to the memory controller, the multi-deck non-volatile memory structure including a plurality of decks, wherein the multi-deck non-volatile memory structure is Multiple word line contacts that penetrate multiple decks, A system comprising a plurality of through array vias penetrating the plurality of decks, wherein the plurality of through array vias and the plurality of word line contacts are mixed within a shared word line access structure region.

8. The system according to claim 7, wherein the plurality of through array vias and the plurality of word line contacts are mixed such that the first word line contact among the plurality of word line contacts is located between the first through array via and the second through array via in the shared word line access structure region.

9. The system according to claim 7, wherein the plurality of through array vias and the plurality of word line contacts are mixed such that the first row of the plurality of word line contacts is located between the first row of the through array vias and the second row of the through array vias in the shared word line access structure region.

10. The system according to claim 7, wherein the plurality of word line contacts penetrate the plurality of decks within a variable depth pattern, while the plurality of through array vias penetrate the plurality of decks at a common depth.

11. The system according to claim 7, wherein the shared word line access structure region does not have a 3D NAND staircase structure.

12. The system according to claim 7, wherein the multi-deck non-volatile memory structure comprises 3D NAND.

13. The steps include forming multi-level via holes that penetrate multiple decks of the non-volatile memory structure of a memory device based on word line contact patterning, A method comprising the steps of depositing a metal film to fill the via hole and forming a word line contact.

14. The method according to claim 13, further comprising the step of depositing an insulating liner in the multilevel via hole before depositing the metal film.

15. The method according to claim 14, further comprising the step of removing the bottom of the insulating liner.

16. Before forming the multi-level via holes, the steps include depositing hard masks on the multiple decks of the non-volatile memory structure, The steps include: engraving a word line cavity in the hard mask corresponding to the position for forming the word line contact; The method according to claim 13, further comprising the steps of performing a multi-mask patterning process to form the multi-level via holes, wherein the multi-mask pattern covers the variation portion of the word line cavity at each masking stage of the multi-mask patterning process.

17. The multimask patterning process further includes performing the multimask patterning process a number of times determined by the number of word lines that need to be accessed, and the multimask patterning process Forming a first process resist that covers a first half of the word line cavity, wherein the first process resist has a first pattern that covers only every other word line cavity. Etching the first uncovered half of the word line cavity, Removing the first process resist, Forming a second process resist that covers a second half of the word line cavity, wherein the second process resist has a second pattern that covers only every other pair of the word line cavities. Etching the second uncovered half of the word line cavity, Removing the second process resist, Forming a third process resist that covers a third half of the word line cavity, wherein the third process resist has a third pattern that covers only every other quarter of the word line cavity. Etching the third uncovered half of the word line cavity, The method according to claim 16, further comprising removing the third process resist.

18. The method according to claim 13, further comprising the step of forming a plurality of through array vias that penetrate the plurality of decks, wherein the plurality of through array vias and the word line contacts are mixed within a shared word line access structure region.

19. The method according to claim 18, wherein the plurality of through array vias and the word line contacts are mixed such that the first word line of the word line contact is located between the first through array via and the second through array via in the shared word line access structure region.

20. The method according to claim 18, wherein the plurality of through array vias and the word line contacts are mixed such that the first row of the word line contacts is located between the first row of the through array vias and the second row of the through array vias in the shared word line access structure region.

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