Plasma jet etching of substrates

Abstract

Techniques and apparatus for processing semiconductor substrates are provided. In some embodiments, the technique includes the steps of: receiving at least an edge portion of a semiconductor substrate into a region between a first electrode and a second electrode, wherein the region comprises one or more shelf features, each configured to prevent plasma from diffusing from the region; receiving a process gas and an inert gas from one or more inlets; using the first and second electrodes and the process gas to generate a point plasma confined in the region between the first and second electrodes by the one or more shelf features; and etching the edge portion of the semiconductor substrate using an etchant generated on the edge portion by the point plasma while the semiconductor substrate rotates between the first and second electrodes relative to the first and second electrodes.

Description

Technical Field

[0001] Incorporation by Reference The PCT application is filed simultaneously with this specification as part of this application. Each application for which this application claims benefit or priority and which is identified in the PCT application filed simultaneously is hereby incorporated by reference in its entirety for all purposes into this specification.

Background Art

[0002] Semiconductor manufacturing processes may create layers of film on a semiconductor substrate or wafer during fabrication, which can result in unwanted materials or metals on the substrate, particularly on the edges. Some processes, such as edge bevel removal (EBR), can substantially process the edges of the wafer to remove materials. EBR can be performed by applying reactive species (e.g., etching agents) generated by a plasma source in a reduced pressure environment to remove materials at desired locations such as the edges of the wafer. However, conventional EBR under reduced pressure has reached its performance limits because of increasing requirements for etching rate, yield, and accuracy of the etching profile.

[0003] The descriptions of the background and context included herein are provided only for the purpose of generally presenting the context of the present disclosure. Many of the disclosures herein present the research of the inventors, and it does not mean that such research is recognized as prior art merely because it is described in the background art section or presented as context elsewhere in this specification.

Summary of the Invention

Means for Solving the Problems

[0004] One aspect of the present disclosure discloses a method for processing a semiconductor substrate. In some embodiments, the method includes: receiving at least an edge portion of a semiconductor substrate into a region between a first electrode and a second electrode, wherein the region comprises one or more shelf features, each configured to prevent plasma from diffusing from the region; receiving a process gas and an inert gas through one or more inlets; generating a point plasma confined in the region between the first electrode and the second electrode by one or more shelf features using the first and second electrodes and the process gas, wherein the point plasma has a pressure of at least 200 Torre; and etching the edge portion of the semiconductor substrate using an etchant generated on the edge portion by the point plasma while the semiconductor substrate is rotating between the first and second electrodes relative to the first and second electrodes.

[0005] In some embodiments, the method may include receiving an edge portion of a semiconductor substrate into a region between a first electrode and a second electrode, wherein the region comprises one or more containment shelves; generating an etching agent having a pressure of at least 200 Torr using a reaction gas and the first electrode; transporting the etching agent toward an edge portion of a semiconductor substrate positioned in close proximity to the first electrode using a carrier gas; and etching a portion of the semiconductor substrate using the etching agent while the semiconductor substrate rotates between the first electrode and the second electrode, wherein the etching agent is contained within the region by one or more containment shelves.

[0006] In another aspect of the present disclosure, an apparatus configured for processing a semiconductor substrate is disclosed. In some embodiments, the apparatus comprises a first electrode and a second electrode positioned opposite the first electrode to form a region sized to receive at least a portion of a semiconductor substrate between the first and second electrodes, wherein the first and second electrodes are configured to be coupled to a power supply; one or more confinement racks adjacent to the region and configured to confine gas and plasma; a first gas inlet, a second gas inlet, the first and second electrodes, and a controller configured to be coupled to the power supply, wherein the controller is coupled to the first and second electrodes, and to the power supply. The system may further include a controller configured to apply power from a power source to the first and second electrodes to generate plasma within a region using the first and second electrodes, at least based on a process gas received through a first gas inlet, the process gas being delivered into the region using a carrier gas from a second gas inlet, the plasma being at least partially confined within the region by one or more confinement racks having a pressure of at least 200 Torr, and etching at least a portion of the semiconductor substrate using the generated plasma while the semiconductor substrate is rotating.

[0007] These and other features of embodiments of the present disclosure are described in detail below with reference to the relevant drawings. [Brief explanation of the drawing]

[0008] [Figure 1A] This is a simplified diagram of a hardware configuration for removing material from a semiconductor substrate using a plasma source, according to several embodiments. [Figure 1B] This is a simplified diagram of a hardware configuration for removing material from a semiconductor substrate using a plasma source, according to several embodiments. [Figure 2] This is a schematic diagram of the hardware configuration of a material removal system configured to supply a pressurized jet of plasma toward a semiconductor substrate, according to several embodiments. [Figure 2A] Figure 2 is a cross-sectional view of the schematic hardware configuration of the material removal system. [Figure 2B] Figure 2 is a cross-sectional view of a part of the material removal system, showing the components of the system and the containment racks useful for implementing the system. [Figure 2C] Figure 2 is a cross-sectional view of a part of the material removal system, showing the components of the system and the containment racks useful for implementing the system. [Figure 2D] This figure shows indirect and direct plasma generation that may be used in conjunction with the material removal system described herein. [Figure 2E] This figure shows indirect and direct plasma generation that may be used in conjunction with the material removal system described herein. [Figure 2F] This figure shows three factors that may be involved in processing wafer edges using a plasma source, including radical generation, transport, and surface reactions. [Figure 2G] This is an enlarged view of the hardware configuration of a material removal system according to several embodiments. [Figure 2H] This is a cross-sectional view of a plasma source having a confinement shelf. [Figure 2I] This is a cross-sectional view of a plasma source having multiple confinement shelves. [Figure 3] This is a flowchart illustrating a method for processing a semiconductor substrate according to several embodiments. [Figure 4] This is a flowchart illustrating another method for processing semiconductor substrates according to several embodiments. [Figure 5] This is a simplified block diagram of the system or apparatus described herein. [Modes for carrying out the invention]

[0009] The following terms will be used throughout this specification.

[0010] As used herein, “semiconductor device fabrication operation” refers to an operation performed during the fabrication of a semiconductor device. As referred to herein, such fabrication operation may also be simply called a “process” or “treatment.” Examples of treatments include the deposition of material onto a substrate, the selective etching of material from a substrate, and the ashing of photoresist on a substrate. Typically, an overall fabrication process includes multiple semiconductor device fabrication operations, each performed using its own semiconductor fabrication tools, such as plasma reactors, electroplating cells, chemical mechanical planarization tools, and wet etching tools. Categories of semiconductor device fabrication operations include subtractive processes such as etching and planarization processes, as well as material addition processes such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of etching processes, a substrate etching process includes a process of etching a mask layer, or more generally, a process of etching any layer of material previously deposited on and / or present on the substrate surface. Such an etching process may also etch a stack of layers within the substrate.

[0011] In this disclosure, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. Those skilled in the art will understand that the term “partially fabricated integrated circuit” may refer to a semiconductor wafer at any of the many stages of integrated circuit fabrication thereon. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, 300 mm, or 450 mm. Examples of semiconductor substrate materials include silicon (Si), gallium arsenide (GaAs), and silicon germanium (SiGe).

[0012] In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include a variety of articles such as magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices, or components of pixelated display devices, flat panel displays, and micromechanical devices. The workpieces may vary in shape, size, and material.

[0013] This disclosure generally relates to processing semiconductor substrates to remove unwanted material from a portion of the substrate, such as the edges of the substrate. Improved methods that are cost-effective and reduce the system footprint are desirable. Furthermore, the embodiments disclosed herein can eliminate the need for manual system redesign and the long time required to optimize the hardware configuration.

[0014] Such improved techniques, according to some embodiments of the present disclosure, may utilize so-called atmospheric pressure plasma jet (APPJ) techniques for edge bevel removal (EBR) techniques in recipe-controlled etching to remove material (e.g., one or more existing layers) from a portion of a semiconductor substrate, which in some embodiments may involve operating one or more nozzles under atmospheric conditions to supply a pressurized jet of plasma radicals toward the substrate. The present disclosure is not necessarily limited to etching, as APPJ may be used to deposit material using a particular configuration. That is, a material removal system may be used for deposition despite its name, and its function is not limited to material removal. However, the following description will focus primarily on material removal using etching to improve EBR.

[0015] The components of a system that uses APPJ for EBR will be described with reference to FIGS. 1A to 2I. Such a system may be configured to emit plasma radicals that process specific locations on a semiconductor substrate, for example, to remove material from the edge of the substrate. Using the hardware of such a system, a wafer may spin on an aligner hardware through a controlled plasma emission region, and a plasma source (e.g., a plasma jet) may be configured to etch (or in some configurations deposit) material on the wafer, including the front side, edge, and / or back side of the wafer. More specifically, the chemical properties of the plasma may be able to etch regions near the wafer edge (or other parts of the wafer). In some embodiments of the present disclosure, instead of using a single jet, an arc-shaped jet that may consist of a single jet region or an array of jets may be utilized. In some implementations, such an array may be as simple as jets distributed across the wafer radius. As suggested above, or instead of etching, an appropriate selection of the plasma feed gas may induce plasma-enhanced chemical vapor deposition of the material.

[0016] Edge Bevel Removal (EBR) Using an Atmospheric Pressure Plasma Jet (APPJ) Figure 1A shows an exemplary diagram of plasma radicals applied to a semiconductor substrate 102 in several implementations of the material removal system 100 described herein. In some embodiments, the system 100 may include one or more source subassemblies 101, including an upper subassembly 104, a lower subassembly 106, and a plasma source 108. As described elsewhere, the plasma source 108 may include at least one plasma jet or at least one nozzle. In some embodiments, the upper subassembly 104 may include an electrode or electrode assembly. In some embodiments, the upper subassembly 104 may provide a hydrostatic bearing or an aerodynamic bearing. In some embodiments, the lower subassembly 106 may include an electrode or electrode assembly separate from the electrode or electrode assembly of the upper subassembly 104. In some embodiments, the lower subassembly 106 may provide a load capacity for a hydrostatic gas bearing or a hydrodynamic gas bearing. A hydrostatic gas bearing uses a layer of pressurized gas that provides a low friction load-bearing interface between surfaces. A hydrodynamic gas bearing can form its load capacity through the relative velocity of the moving gas between a stationary surface and a moving surface (e.g., between the surface of a subassembly and the surface of a spin substrate). Hydrodynamic gas bearing capacity is beneficial because it allows for reduced gas consumption and enables some operations to be performed without the necessary flow of gas supplied from an external source.

[0017] In some embodiments, the semiconductor substrate 102 may be positioned or disposed in a plasma emission region between an upper subassembly 104 and a lower subassembly 106, or when the substrate rotates along a selected direction 111 around the central axis 114 of the substrate, components (including the plasma source 108) may substantially process the edge 102-e of the semiconductor substrate 102. More specifically, in some configurations, by disposing the substrate edge 102-e in proximity to the tip associated with the nozzle or jet of the plasma source 108, the plasma source 108 may be substantially confined to the edge of the semiconductor substrate 102. The plasma source 108 may be positioned along the upper subassembly 104 (for example, the tip of the plasma source 108 may be coplanar with the surface of the upper subassembly 104). In some embodiments, a portion of the semiconductor substrate 102 proximate to the plasma may be sandwiched between one or more surfaces of the upper and lower assemblies 104, 106 for precise gap control. For example, the upper subassembly 104 may include an opening for a hydrostatic gas bearing gas to flow over the upper surface of the semiconductor substrate 102. The proximity may be at the micron level (for example, in the range of microns to tens of microns, or less than about 100 microns). Advantageously, the resulting micron-level gap between the semiconductor substrate 102 and the hydrostatic gas bearing surface provides advantages in plasma confinement (for example, away from the inner portion or center of the substrate), edge purge (for example, removal of residues from the etched portion), stability of rotation of the semiconductor substrate 102, and efficient processing. Advantageously, the plasma source 108 enables processing of the wafer edge with a short transition from the etched edge to the unprocessed film over a defined distance. The edge of the processed semiconductor substrate 102 may have a substantially vertical cut where the thickness transitions abruptly. The vertical cut may help prevent the flow of plasma radicals towards the inner portion or center of the substrate.

[0018] During processing (e.g., etching), the semiconductor substrate 102 may be spun in a selected direction 111 (e.g., counterclockwise or clockwise) around an axis 114 while being held in place by other hardware such as aligner hardware 110. Optionally, the aligner hardware 110 may be configured to translate, traverse, and / or spin (e.g., act in the XY or R-θ-Z directions). Optionally, the aligner hardware 110 may be configured to control another device, causing the other device to translate, traverse, and / or spin. The semiconductor substrate 102 may be held in place via its back side, for example, by a vacuum chuck (optionally, an electrostatic chuck or clamp) with the aligner hardware 110. Optionally, the source subassembly 101 may have a stage 112 coupled to it to actuate at least a portion of the source subassembly 101 (e.g., in the XYZ directions).

[0019] In some implementations, the aligner hardware 110 may be activated (e.g., moved in the XYZ directions) and / or the spin rate may be adjusted, while optionally, the radio frequency (RF) power associated with the plasma source 108 may be modulated to stop or start etching. An exemplary range of RF power frequencies may be between approximately 10 kilohertz (kHz) and approximately 100 megahertz (MHz). Abrupt transitions may increase the area on the wafer that results in an operating die, while a specified diameter ensures material removal at the desired location. Further details regarding material removal using the components of assemblies 104, 106 (e.g., electrodes) and the plasma source 108 are described below in detail with respect to Figures 2 to 2I.

[0020] Figure 1B shows an exemplary diagram of plasma radicals directed to the edge 102-e of a semiconductor substrate 102, according to several implementations of the system 100 described herein. In this configuration, the plasma source 108 may be configured to emit a first gas (e.g., plasma radicals) and a second gas (e.g., shielding gas) through the first and second openings of the plasma source 108, respectively. In some implementations, the first and second gases may be emitted from openings other than the openings of the plasma source 108. The second gas may act as a shield, enabling concentrated application of radicals to a specific location (e.g., the edge) of the semiconductor substrate 102. The shielding gas also prevents the plasma radicals from dispersing or recombining with the surrounding air (e.g., as illustrated with respect to Figure 2F (recombination 221)), enabling concentrated application of plasma radicals to the substrate edge 102-e. In the exemplary operation shown, as the substrate 102 rotates around axis 114, various portions of the substrate edge 102-e may be exposed to plasma radicals.

[0021] In some operations, the system configuration may be used to deposit layers on one or more portions of the substrate 102 (e.g., on the front side) on the inner portion 102-i or the substrate edge 102-e, for example, when the substrate 102 rotates.

[0022] Generally speaking, since the deposited film or component remains undisturbed, plasma radicals reaching areas other than the substrate edge 102-e (such as the inner portion 102-i) are undesirable. Therefore, in some configurations, the plasma source 108 (e.g., its nozzle) may be positioned or angled toward or away from the inner portion 102-i of the substrate 102. The example shown in Figure 1B shows the nozzle oriented away from the center of the substrate 102, which can help remove edge material and prevent radical accumulation in other parts of the substrate 102. For further assistance, in some configurations, a third gas, such as a purge gas and / or a hydrostatic bearing gas, may be supplied through a third opening adjacent to the surface of the substrate 102, received through a third channel 137 defined adjacent to or otherwise in close proximity to the plasma source 108 (e.g., another part of the upper subassembly 104). However, in some configurations, the third channel 137 may be part of the plasma source 108 (e.g., within the same housing). The third gas may be supplied with sufficient force to guide the plasma radicals away from the center of the substrate 102 toward the substrate edge 102-e and to sufficiently expose the substrate edge 102-e to the plasma radicals. In some cases, the purge gas and the hydrostatic bearing gas may be supplied through separate third and fourth openings. In other configurations, further inlets and openings may be present.

[0023] Advantageously, when used with relatively high-pressure gases (e.g., nearly atmospheric pressure or a specific proportion thereof) compared to conventional methods in a reduced-pressure environment, the material removal system 100 can yield a higher reaction product density than possible in low-pressure processes. The disclosed concept offers advantages and benefits such as high process controllability, extremely high throughput due to extremely high etching (or deposition) rates, much lower costs, the ability to easily integrate with etching (or deposition) tools, and direct writing capability for a much smaller product footprint when pursued as a standalone implementation. Thus, the topologies shown in Figures 1A and 1B, based in part on small component volumes, can result in significant hardware cost reductions compared to current technologies.

[0024] Another advantage of using APPJ with EBR is that while wafer rotation can be fast (e.g., 60-120 rotations / minute), the modulation of RF power to the plasma jet associated with the plasma source 108 can be performed much faster. In addition to controlling plasma generation and transfer, the synchronization of power and substrate angle or position can generate a range of different film characteristics to tune the net etching profile as desired, for example, using on / off or high / low RF power modulation.

[0025] Figure 2 shows a schematic diagram of the hardware configuration of the material removal system 200 according to several embodiments. In some embodiments, the system 200 may include an upper electrode subassembly 202, a lower electrode assembly 204, a plasma source (not shown), a stage 206 configured to actuate the upper and / or lower electrode assemblies (e.g., in the XYZ directions), and an aligner 212 configured to actuate the semiconductor substrate 210 (e.g., in the XY or R-θ-Z directions). In some implementations, the upper subassembly 104 in Figure 1 may correspond to or include the upper electrode subassembly 202, and the lower subassembly 106 in Figure 1 may correspond to or include the lower electrode subassembly 204. However, the system 200 as shown in Figure 2 does not have to rely on hydrostatic gas bearings depending on the implementation.

[0026] In some embodiments, the plasma source may be located together with the upper electrode subassembly 202 (e.g., adjacent, internal, or in close proximity). In some embodiments, the plasma source may be located together with the lower electrode subassembly 204 (additionally or alternatively). The plasma source may generate chemical reaction species, such as an etchant, which can be supplied to a portion of the semiconductor substrate 210 (e.g., an edge or other location) in a controlled manner as the semiconductor substrate 210 spins. The spatial distribution of the plasma (i.e., the etching profile) can be controlled by the electrode configuration and gas flow. For example, the RF power modulation of the upper electrode subassembly 202 and / or the lower electrode subassembly 204 may be controlled. Furthermore, as described with respect to Figure 1B, the first, second, and / or third gas flows may be controlled. Controlling these parameters with respect to the electrodes and gas flow can result in a desired etching profile on the wafer.

[0027] As background, plasma can be generated by applying an RF field to a gas (e.g., through one or more electrodes). The plasma generates reactive species, which may include electrons, ions, radicals, and neutral species. Ionization of the gas by the RF field ignites the plasma, creating free electrons in the plasma discharge region (e.g., within the plasma source). These electrons are accelerated by the RF field and can collide with gas-phase reactant molecules. These collisions between electrons and reactant molecules can form radical species involved in etching or deposition processes.

[0028] As the semiconductor substrate 210 spins (e.g., via the aligner 212) while being positioned between the upper and / or lower electrode assemblies 202, 204, a portion of the substrate (e.g., the edge) may be exposed to the etchant generated by the plasma source, thereby allowing the chemical properties of the plasma, as well as the modulation of the RF power applied to the upper and / or lower electrode assemblies 202, 204, to etch a portion of the substrate 210. In some cases, the interior of the semiconductor substrate 210 from which material should not be removed may be protected by a solid object (e.g., a cover) to prevent the diffusion of the etchant into the inner area of ​​the wafer. An example of such a solid object may be a containment shelf, as described with respect to Figures 2H and 2I. Thus, at least partially based on physical obstructions (and / or purge gas), even if the plasma-generated etchant fills the process volume, the material may only be removed at the wafer edge.

[0029] However, as mentioned above, industry demands for etching speed are increasing, and the required precision of the etching profile is becoming increasingly narrow. Considering this, the positioning of the semiconductor substrate 210 relative to the lower surface of the upper electrode subassembly 202 and the upper surface of the lower electrode subassembly 204 can be precisely controlled. More specifically, the gap between the two assemblies can be defined. In some cases, this requires a highly skilled operator or engineer and can take a considerable amount of time to optimize the hardware configuration. Solid objects or covers may also need to be redesigned to alter the etching profile. Once the hardware is set up and the chamber is closed, it becomes difficult to adjust the etching profile and etching width without opening the chamber.

[0030] Therefore, this disclosure can take advantage of the fact that gas diffusivity is low at high pressures. For example, for gases at high pressures such as atmospheric pressure, gas diffusivity is 760 times lower than under typical low-pressure operating conditions. Thus, the etching profile can be adjusted by controlling the gas curtain rather than by mechanical hardware. Furthermore, the point source may be selected to use a wafer spinner rather than a ring-shaped source with a fixed pedestal. This can reduce or minimize non-uniform etching around the wafer bevel because wafer rotation smooths out spatial and temporal plasma fluctuations. Moreover, atmospheric pressure EBR does not require a vacuum pump, which can reduce the machine's footprint and cost. Thus, the configuration of system 200 advantageously allows the etching material to be applied only to the wafer edge without a vacuum system, which can reduce cost and system footprint.

[0031] However, it will be recognized that system 200 may also be configured to apply the etchant to various parts of the wafer (e.g., non-edges) for desired etching profiles for other applications, such as compensating for existing wafer curvature. For example, the gap between electrode assembly 202 and electrode assembly 204 may be extended, and / or a protective solid object (e.g., a cover) may be absent or positioned so that the aligner 212 can move the wafer "deeper" into the assembly, allowing etching on non-edge parts (e.g., inner part 102-i shown in Figure 1B).

[0032] Figure 2A shows a schematic cross-sectional view of the hardware configuration of the material removal system 200 according to several embodiments. In some embodiments, the upper electrode subassembly 202, the lower electrode subassembly 204, and the stage 206 may be configured to receive a semiconductor substrate 210 actuated via an aligner 212, which may be used as described above with respect to Figure 2. In some embodiments, the upper electrode subassembly 202, the lower electrode subassembly 204, and the stage 206 may be part of the source subassembly 101 described with respect to Figure 1A. In some embodiments, the aligner 212 may include a chuck 213, one or more pins 214, and / or an alignment sensor 215.

[0033] The aligner 212 may include various components configured to firmly hold the semiconductor substrate 210 and actuate to insert it vertically, for example, within the source subassembly 101 (e.g., between the upper electrode subassembly 202 and the lower electrode subassembly 204). In some configurations, the aligner 212 may be used to adjust the position of the substrate 210 on the chuck 213 so that the wafer spins with minimal eccentricity. For example, if the substrate 210 spins with measured eccentricity to minimize edge movement of the upper electrode assembly substrate 202 under the plasma jet, the substrate 210 may also be servo-driven or actuated (e.g., to move away in the x or y direction toward the direction perpendicular to the upper and lower electrode subassemblies 202, 204).

[0034] Those skilled in the art will recognize various configurations for securing the substrate 210 to the chuck 213. In some embodiments, the chuck may be a vacuum chuck 213. That is, the aligner 212 can use the suction of the vacuum chuck to firmly hold the substrate 210 with sufficient holding force. Vacuum chucks are easy to implement, convenient, and cost-effective. In fact, vacuum chucks may be particularly suitable for processing performed at atmospheric pressure according to this disclosure, because a vacuum chamber, where the pressure is already dramatically lower than atmospheric pressure, would not be able to vacuum chuck the substrate 210. Other types of chucks may be used in vacuum or atmospheric environments, such as the following:

[0035] In alternative embodiments, the chuck 213 may be an electrostatic chuck (ESC) capable of securely holding the substrate 210 using electrostatic force. In some cases, such an ESC may be a bipolar ESC having a pair of complementary, coplanar clamp electrodes (which may be embedded within a pedestal structure) that generate an electrostatic force. In some cases, the ESC may be a unipolar ESC having one clamp electrode, the one electrode having a voltage applied to it, or opposite charges may be induced in the substrate 210 using, for example, a counter electrode above the substrate 210 (or, in certain mounting configurations, for example, plasma generated above the substrate 210 if it is in a processing chamber).

[0036] In some embodiments, the chuck may be configured to move with multiple degrees of freedom. One example of a degree of freedom is translation. Another example is rotation. The chuck may be configured to translate along the x, y, and / or z axes using, for example, an actuator, to move the substrate 210 in the corresponding direction. Furthermore, the chuck may be configured to rotate around the z axis, rotating the fixed substrate 210 at the same rotational speed (e.g., 60-120 revolutions / minute, e.g., 100 revolutions / minute). In some implementations, the chuck may be fixed to a separate stage (or separate actuator), e.g., a stage (not shown), configured to translate (along the x, y, and / or z axes) and / or spin or rotate (around the z axis), or to translate, spin, and / or rotate the chuck. Spinning around the z axis allows the nozzle to cover the entire circumference of the substrate 210 (e.g., along its outer edge), and by controlling the nozzle state (high / low or on / off), various etching patterns can be formed. In some configurations, the nozzle housing or nozzle may be configured to rotate, tilt, or angle around the x and / or y axes, so that when the substrate 210 is positioned on the nozzle, the nozzle can cover a large portion of the substrate 210. In some configurations, the position of the nozzle may be varied relative to the nozzle housing. For example, the nozzle may be repositioned along the x, y, z axes, radial (r) direction, and / or angular (θ) direction. Angle repositioning may result in the nozzle tilting relative to the nozzle housing, while the nozzle housing may remain at the same angular position or tilt.

[0037] In some embodiments, the pins 214 may be ceramic, metal, or elastomer pads or raised platforms configured to hold the semiconductor substrate 210 when the substrate is not secured by the chuck 213. For example, the semiconductor substrate 210 may be placed on the pins 214. In some cases, the substrate may be positioned at a specific location (e.g., relative to the chuck), or in a particular orientation or direction, according to a wafer notch or marker on the substrate and / or position detection by the alignment sensor 215. By properly positioning the semiconductor substrate 210 on the pins 214, it is possible to secure the chuck 213 to the semiconductor substrate 210 using, for example, the techniques described above (e.g., vacuum chucking or ESC). The central axis of the semiconductor substrate 210 may coincide with the central axis of the chuck 213 when the substrate 210 is properly aligned. In some implementations, the alignment sensor 215 may use one or more optical sensors (e.g., lasers) for imaging (e.g., cameras) or vision sensors for the position detection described above or for measuring wafer eccentricity. The alignment sensor may be used to detect the position of the wafer notch, and this information may be used to consider various process conditions and / or wafer positioning that may be required in proximity to the notch in order to obtain the desired etching result.

[0038] Further details regarding the related systems and components outlined above will follow.

[0039] Figure 2B shows an enlarged vertical cross-sectional view of the nozzle of a plasma source 208 that may be used in system 200 in several implementation configurations. The plasma source 208 may be an example of the plasma source 108. The plasma source 208 may include a first electrode 233 defined approximately in the center of the nozzle. A dielectric material 238 may be arranged to surround the first electrode 233, thereby defining a first channel 235 between the first electrode 233 and the dielectric material 238. The first channel 235 may be connected to a first gas source (Figure 1B) through a first inlet 231 defined at a first end, and to a first opening 242 at a second end defined near the top of the nozzle. The first channel 235 may be configured to receive a first gas from a first gas source through the first inlet 231. The second electrode 234 may be embedded in the dielectric material 238 and surround the first electrode 233. The dielectric material 238 may act as a barrier to the metal surface to prevent arc discharge and metal contamination when RF power is applied.

[0040] In some implementations, the first gas may be an etching agent gas. In some cases, the first gas may be a reaction gas or a mixture of gases, for example, an oxygen-based, fluorine-based, hydrogen-based, chlorine-based chemical, or another etching agent precursor, and / or an inert carrier gas such as argon, neon, or helium. The inert gas may be used to carry the plasma radicals of the etching agent through the first opening 242. It should be noted that the above examples of gases are provided as examples only and should not be considered limiting. When the system 200 is used for edge bevel removal, depending on the type of film (i.e., residue) on the edge of the substrate to be removed, the carrier gas may be any stable inert gas such as argon, neon, or helium, and the etching agent gas may contain oxygen, fluorine, chlorine, or any other halogen, or hydrogen. In some cases, when deposition is desired in the APPJ system, the first gas may be a mixture of the deposition gas and the carrier gas.

[0041] As described above, the RF power is modulated to alter the emission of plasma radicals as the substrate 210 spins, thereby creating, for example, a desired etching pattern on the front side of the substrate 210. Such modulation may be performed based on signals generated by the plasma source, controllers coupled to the upper electrode subassembly 202 and / or lower electrode subassembly 204, logic, differential drive units, etc.

[0042] Furthermore, the controller or logic may further control one or any combination of the following parameters: the rotational speed of the substrate, the nozzle position relative to the substrate (e.g., in the x, y, and / or z axes), and plasma parameters (such as plasma power, RF frequency, gas flow rate, gas composition, and / or gas pressure). In some implementations, the plasma power may vary between on and off. In some implementations, the plasma power may vary between high RF power and low RF power, rather than being on / off. Other parameters affecting etching may include the residence time of the nozzle jet emission at any location on the wafer. Any of these parameters may affect the etching of one or more layers, for example, at the edges or other parts of the substrate 210. These parameters may be controlled while the substrate 210 is rotating or at the location where the nozzle is positioned relative to the substrate 210 (in the radial and azimuthal directions in XYZ space). In some implementations where multiple nozzles are used or included in an assembly (e.g., upper electrode subassembly 202), each of the multiple nozzles may be controlled separately.

[0043] The dielectric material 238 placed inside the nozzle may further define a second channel 236 between the dielectric material 238 and the outer wall of the nozzle 239. The second channel 236 may be coupled to a second gas source (Figure 1B) through a second inlet 232 defined at the first end to receive a second gas, or a second opening 243 may be defined at the second end defined at the bottom of the nozzle. The second opening 243 may be defined adjacent to the first opening 242 and surround the first opening. The second opening 243 may be a single opening or multiple openings (two are shown in Figure 2B) surrounding the first opening 242. The second gas may be an inert gas such as argon, neon, or helium. The second gas may be a curtain gas such as nitrogen or air. The second channel 236 may create a separate gas path for the second gas, or the second opening 243 at the top of the nozzle may guide the second gas upward without disturbing the plasma radicals flowing through the first opening 242. The second gas exiting from the second opening 243 may act as a shield for the plasma radicals mixed with the carrier gas exiting from the first opening 242 by surrounding the mixture of plasma radicals and carrier gas.

[0044] It will be understood that an additional third inlet or channel (not shown) adjacent to the first inlet 231 and / or second inlet 232 may supply a third gas, such as a purge gas and / or a hydrostatic bearing gas, through a third opening (not shown). The third channel 137 in Figure 1B may be an example of a third inlet or channel. In some implementations, the third gas may be supplied with sufficient force to guide plasma radicals away from the center of the substrate 210 toward the substrate edge and to sufficiently expose the substrate edge to plasma radicals. In some cases, the purge gas and hydrostatic bearing gas may be supplied through separate third and fourth inlets and openings. In other configurations, further inlets and openings may be present.

[0045] Referring again to Figure 2B, in some implementations, the second electrode 234 embedded in the dielectric material 238 may be oriented parallel to the first electrode 233, which is positioned approximately in the center of the nozzle. In some alternative implementations, the second electrode 234 embedded in the dielectric material 238 may be oriented at least partially perpendicular to the first electrode 233. Further alternative implementations may be molded to conform to the contour of the dielectric material 238, or oriented parallel to the first electrode 233. Regardless of orientation, the second electrode 234 may be positioned at a predetermined distance from the first electrode 233, and the predetermined distance may be determined to allow for the generation of plasma of the first gas received in the first channel 235. In some implementations, the first electrode 233 may be made of metal. In some implementations, the first electrode 233 and the second electrode 234 may be made of the same material. In some implementations, the first electrode 233 may be made of a different material than the second electrode 234. The material used for the second electrode 234 may be selected to withstand high temperatures. In some methods, the material used for the second electrode 234 may be selected to have a coefficient of thermal expansion (CTE) that matches the CTE of the dielectric material 238 in which the second electrode 234 is embedded. In some methods, the first and second electrodes 233,234 may be made of tungsten, molybdenum, iridium, rhenium, or platinum, and the dielectric material 238 may be made of aluminum nitride, aluminum oxynitride, silicon nitride, aluminum oxide, or yttrium oxide. In some implementations, the dielectric material 238 and / or the first electrode 233 may be cooled using one or more cooling elements (not shown). In some cases, the cooling elements may be placed in a region adjacent to the second electrode 234.

[0046] In some implementations, the first electrode 233, positioned close to the center of the nozzle, may be coupled to the aforementioned RF power supply, and the second electrode 234 may be grounded via a match network. In some other implementations, the first electrode 233 may be grounded, and the second electrode 234 may be coupled to the RF power supply via a match network. In yet another implementation, both the first electrode 233 and the second electrode 234 may be coupled to the RF power supply via a match network, and neither the first electrode 233 nor the second electrode 234 may be grounded.

[0047] In some configurations, a differential voltage may be applied to the first electrode 233 and the second electrode 234. For example, with an input voltage of 200 volts (V), the voltage applied to the first electrode would be +100V and the voltage applied to the second electrode would be -100V (i.e., each electrode may be supplied with half the input voltage). In some cases, a differential drive (not shown) may be coupled to the RF power supply and used to switch the RF power input between the two electrodes (first electrode 233, second electrode 234). In some implementations, the differential drive may be an isolation transformer having a secondary winding used to provide the differential voltage.

[0048] The nozzle topology may be defined to supply high-density plasma radicals to the substrate 210 in order to achieve high-precision etching (or, in certain cases, deposition). In some exemplary implementations, the flow rate of the reaction gas in the first gas may be defined as between about 100 standard cubic centimeters / minute (sccm) and about 300 sccm, and the flow rate of the carrier gas stream may be defined as between about 1,000 sccm and about 30,000 sccm. In some embodiments, the pressure of the plasma generated in the region between the upper electrode assembly and the lower electrode assembly may exceed a threshold, e.g., at least 200 torr. In some implementations, the plasma pressure may be about 760 torr (atmospheric pressure). In some implementations, the plasma pressure may be any other percentage of atmospheric pressure.

[0049] The nozzle topology can result in an efficient and effective method of processing the substrate 210 using a simple processing chamber with minimal hardware. Plasma can be generated remotely and supplied to the edges or other parts of the substrate 210. In addition to the first and second gases being applied to the substrate 210, a third gas may be supplied from a third channel defined adjacent to the nozzle. The third gas can act as a gas curtain, pushing the first gas, contained within the second gas, away from the center of the wafer, resulting in a concentrated application of plasma radicals, whether at the wafer edge or at a radius defined from the center. The simple design makes it possible to keep the processing chamber lightweight and compact, and the processing chamber can be stacked on other existing modules (e.g., load locks) without leaving additional footprint.

[0050] In some configurations, there may be "n" nozzles (where "n" is an integer) within the nozzle housing, and at least some of the n nozzles simultaneously supply plasma radicals to cover a large area of ​​the substrate 210 or its edge. In some configurations, the nozzle housing may contain 3, 5, 7, or 9 nozzles arranged in close proximity to each other. In some configurations, the "n" nozzles may be arranged along an arc defined within the nozzle housing. The arc may be defined to coincide with the curvature of the substrate edge. In some configurations, the "n" nozzles may be arranged substantially linearly rather than along an arc coinciding with the curvature of the substrate edge. In some cases, linear nozzles may extend radially to allow etching at various radial positions along the substrate. Although various configurations have been described herein with reference to the system 200 using nozzles, the configurations are not limited to nozzle operation, and other non-nozzle tools or components may also be engaged to process the substrate 210.

[0051] In certain embodiments, the nozzle housing and / or the nozzle itself may be configured to actuate in the z-axis (e.g., vertical) and / or radially depending on the distance to a portion of the semiconductor substrate, such as the edge of the semiconductor substrate 210. For example, the housing may actuate within the upper electrode subassembly 202, and / or the nozzle may actuate within the housing. The distance to a portion of the semiconductor substrate 210 may be measured, for example, using one or more optical sensors (e.g., lasers). Based on any variation in the distance between the housing or nozzle and the semiconductor substrate 210 (which may occur due to non-uniformity, curvature, eccentricity, etc., of the substrate), the housing or nozzle may be actuated in accordance with the measured distance (e.g., by a controller) to keep the distance constant.

[0052] Figure 2C is a cross-sectional view showing an upper electrode subassembly 202, a semiconductor substrate 210 (e.g., a wafer), and a lower electrode subassembly 204 according to several embodiments. As can be seen from the figure, the wafer is positioned (e.g., inserted) between the surfaces of the upper and lower electrode assemblies 202, 204, and the edge of the semiconductor substrate 210 (wafer edge) is positioned below the plasma source 208.

[0053] The plasma source 208 can generate radicals. In some configurations, the generated radicals may be transported to the wafer edge. Radical generation may include the application of RF power only to the upper electrode subassembly 202. This technique is sometimes called “indirect” plasma generation. However, in some configurations, radicals may be generated directly at the edge of the semiconductor substrate 210 by, for example, applying RF power to both the upper and lower electrode assemblies. This technique is sometimes called “direct” plasma generation.

[0054] Figure 2D shows indirect plasma generation and transport, where RF power may be applied to the upper electrode subassembly 202, thereby generating radicals within the plasma source 208. In some embodiments, an inductively coupled plasma (ICP) source may be used, which is one type of plasma source in which energy is supplied by electromagnetic induction, i.e., by a current generated by a time-varying magnetic field. Plasma radicals are generated remotely from the material being processed (e.g., a layer or film on the semiconductor substrate 210). The generated radicals are then emitted from the plasma source 208 and can be transported together with a carrier gas through the nozzle of the plasma source 208. A portion of the semiconductor substrate 210 (e.g., a wafer edge) may be processed (e.g., etched) using the radicals transported thereto.

[0055] Figure 2E shows direct plasma generation, where RF power may be applied to the upper electrode subassembly 202 and the lower electrode subassembly 204, thereby generating radicals directly on a portion of the semiconductor substrate 210 (e.g., the wafer edge). In some embodiments, a capacitively coupled plasma (CCP) source may be used. Since the etchant is generated directly on the wafer edge, there is no transport, which favorably reduces the loss of radicals due to radical recombination 221 (e.g., O + O2 → O3), as shown in Figure 2F, thereby increasing etching. Such recombination and loss can still occur during indirect plasma generation and transport, particularly during transport, as radical oxygen atoms may react with molecular oxygen.

[0056] As shown in Figure 2F, examples of factors involved when processing wafer edges using plasma source 208 include (1) radical generation, (2) radical transport, and (3) surface reactions. Radical generation may include the decomposition of gas species such as molecular oxygen (O2 → O+O).

[0057] Factors influencing radical generation may include the O2 concentration (including in the carrier gas), plasma density and electron temperature, and the carrier gas used. In some implementations, the O2 concentration in the carrier gas may be less than 10%. High-pressure ICP may be used to create optimal plasma density and electron temperature. The gas pressure in the reactor can be atmospheric pressure (about 760 Torre) or lower, i.e., a percentage of atmospheric pressure (e.g., about 200 Torre or higher). In some embodiments, the process gas and carrier gas may be introduced together, and the process gas and inert gas may have a total pressure of at least about 200 Torre. Higher pressure can contribute to higher etching rates in EBR. The process gas may include, for example, a reaction gas or etching agent gas that generates plasma radicals. The carrier gas may be an inert gas, such as helium (He), neon (Ne), or argon (Ar).

[0058] Factors influencing radical transport may include distance to the wafer, gas flow, and recombination conditions. In some implementations, the distance to the wafer edge is virtually zero, and a CCP source may be used to avoid transport. For example, the direct plasma generation technique described with respect to Figure 2E may be used. A high gas flow rate may be used (for example, to prevent etching of areas that should not be etched). For recombination, for example, an O2 pressure of less than 10% in an inert gas may be specified.

[0059] Surface reactions may include etching of the wafer edge. Factors influencing surface reactions may include temperature, which may be used to achieve etching. Gas composition may also affect the etching rate; high O2 concentrations in the purge gas and / or low O2 concentrations in the process gas have been found to result in high etching rates.

[0060] Figure 2G shows an enlarged view of the hardware configuration of the material removal system 200 according to several embodiments. The semiconductor substrate 210 may be supported and fixed by an aligner 212 (e.g., including a chuck) and inserted into the gap between the upper electrode subassembly 202 and the lower electrode subassembly 204. In some embodiments, the plasma source may include, for example, a tip 250 in the nozzle of the plasma source. Or, in some configurations, the material of the tip may include tungsten, and in some configurations, other metals such as molybdenum, iridium, rhenium, or platinum. In some embodiments, the edges of the semiconductor substrate 210 may be at least partially confined by a solid object such as a confinement shelf 252. The confinement shelf 252 may be configured, positioned, and molded to confine and / or at least partially prevent the diffusion of etchants, materials, gases, plasma, etc., into the inner area of ​​the wafer.

[0061] In some embodiments, the system 200, in particular the aligner 212, may further include a chuck or be configured to interact with a chuck. In some embodiments, the chuck may comprise a stem portion and a chuck portion that interfaces with the substrate 210. The stem portion may be sufficiently narrow to accommodate the movement of the chuck into the gap between the upper electrode assembly 202 and the lower electrode assembly 204 (for example, the diameter of the stem portion is significantly smaller than the diameter of the substrate 210, e.g., less than half). An example of a chuck diameter may be 10 inches.

[0062] Returning to Figure 2G, one or more process gases 254 may be supplied to the plasma source. In different implementations, the process gases 254 may include a reactive gas or etching agent gas such as oxygen, and a carrier gas (e.g., an inert gas such as helium, neon, or argon). The process gases 254 may be excited to a plasma state (e.g., via RF power application using upper and / or lower electrodes) for direct or indirect plasma generation and transfer. The generated plasma radicals may be confined in a vacuum or process volume 255, at least partially based on the confinement shelf 252 and other components of the system (e.g., walls present across the confinement shelf 252).

[0063] The process gas 254 may be used to generate plasma at a specific pressure in the plasma source and discharge it through the tip 250. In some embodiments, the plasma may be atmospheric pressure plasma (also known as normal pressure plasma) having a pressure approximately equal to the pressure of the ambient atmosphere. In some embodiments, the plasma may have a pressure of at least about 200 Torr, or at least about 300 Torr. This is in contrast to some conventional EBR applications where the etchant is generated by a low-pressure plasma. However, the performance limits of low-pressure etchants (e.g., low etching rate, high diffusivity) and the width of the etching profile (e.g., control of etchant delivery, precision and location of where the etchant is delivered) can be improved by using a high-pressure plasma. Nevertheless, the plasma pressure may be modified depending on the implementation of the system disclosed herein and its intended use. In fact, adjusting the plasma pressure is easily done by the user or operator, and there is no need to optimize or redesign the hardware configuration when adjustment of the etching profile and etching width is desired.

[0064] Furthermore, one or more purge gases 256 may be supplied through the opening 257 to remove etched edge products from the EBR operation. Examples of purge gases 256 may include various ratios of etchant and carrier gas or inert gas. In some cases, the purge gas 256 may include nitrogen or air. The upper gap 259 may be designed to be small enough to substantially suppress plasma emission when the gap is small, but the combination of etchant and carrier gas entering the plasma emission region can contribute to the etching profile and etching rate. In some applications, the desired etching profile may transition rapidly from nominally no etching to a fully etched film and can be optimized by the ratio of etchant to carrier gas. The purge gas 256 may be released over the entire upper gap 259 in the upper portion of the semiconductor substrate 210 (e.g., on the front side). In some configurations, the purge gas 256 may be released over the entire lower gap (not shown) in the lower portion of the semiconductor substrate 210, for example, via the lower electrode subassembly 204. The semiconductor substrate 210 being processed by the material removal system may be very close to the dielectric surface of the upper electrode subassembly 202 (e.g., dielectric shield 260) and the dielectric surface of the lower electrode subassembly 204 (e.g., dielectric barrier 258). Therefore, the upper gap 259 may be very small. In some cases, the upper gap 259 may be about 3 mils (about 0.003 inches, or about 76.2 microns). In some cases, the upper gap 259 may be about 100 microns or less (e.g., microns to tens of microns). A lower gap 261 may exist between the semiconductor substrate 210 and the lower electrode subassembly 204. In some mounting configurations, the lower gap 261 may be similar in size to the upper gap 259. In some mounting configurations, the lower gap 261 may have a small (e.g., less than about 10 microns) but non-zero distance.

[0065] It is particularly important to select a sufficiently narrow size for the upper gap 259 between the semiconductor substrate 210 and the upper electrode subassembly 202. When the upper hydrostatic gas bearing gas or purge gas 256 flows through the small gap in the upper gap 259, substantial rigidity can be introduced between the semiconductor substrate 210 and the dielectric surface (e.g., dielectric shield 260). The orifice of the tip 250 may be designed to have choked flow between the outer diameter of the orifice and the small gap to the wafer. The viscous force through the small gap can result in a pressure that balances the pressure at the orifice exit. As the gap size increases, the viscous force decreases, thereby reducing the pressure at the orifice exit and increasing the flow. At the same time, the force between the dielectric and the substrate changes with the gap, thereby introducing rigidity. The purge gas 256 may contribute to the process outcome by suppressing plasma from entering the upper gap 259, which can ensure that etching does not diffuse excessively into the inner portion of the wafer (e.g., 102-i) and improve the reaction product density in the area around the wafer edge. Therefore, another consideration is independent control of the gas flow for configuring the purge gas 256 and / or the hydrostatic gas bearing gas, for example, to optimize wafer edge processing, by supplying a desired amount of gas at a flow rate of 0.1 to 100 standard liters / min (slm) nominally flowing into the upper gap 259. The hydrostatic gas bearing surface area, orifice array spacing, orifice diameter, and pressure are selected to generate sufficient force and stiffness within a controlled range of the gap, so that the spin substrate 210 does not come into contact with the hydrostatic gas bearing surface in the presence of out-of-plane wafer motion. Out-of-plane motion can be caused by reasons including imperfections in the motion of the aligner 212, strain of the substrate 210 including thermally induced strain by the plasma jet, and variations in the thickness of the substrate 210.

[0066] In other words, the hydrostatic gas bearing can hold the substrate 210 on a relatively fixed plane and reduce friction against the hardware surface as the substrate rotates. As the substrate 210 rotates, chemical reaction species, such as etching agents generated in the upper electrode subassembly 202, may be applied to the edges or other parts of the substrate 210. For direct plasma generation, an RF voltage may be applied between the upper electrode 203 and the lower electrode 205, and the plasma can be generated in a relatively small, confined region around the wafer edge (e.g., within the process volume 255). In some etching implementation configurations, the chemical properties of the plasma may be selected to have volatile reaction products with the film being etched. For example, oxygen radicals may be specific to carbon (C) or carbon-based films, while fluorine (F) radicals may be selected for molybdenum (Mo) or tungsten (W) materials for removal. Appropriate reactants can be selected to target the metal or material being etched. For deposition, the chemistry of the plasma may be selected to have deposition products for plasma-enhanced chemical vapor deposition (PECVD) or plasma-enhanced atomic layer deposition (PEALD). Examples of precursors for silicon dioxide deposition include silane and tetraethoxysilane (TEOS). The deposition gas for silicon nitride may include, for example, silane, nitrogen, and ammonia. An exemplary precursor for tungsten deposition includes tungsten hexafluoride (WF6). These examples are illustrative and do not preclude other chemistry properties selected for specific film compositions.

[0067] In some exemplary operations, the distance or gap between the upper electrode subassembly 202 and the lower electrode subassembly 204 may be set or adjusted (for example, via z-axis movement of the electrode assembly and / or substrate 210 via a chuck) so that even a curved substrate can be accepted without touching the surfaces of the upper and lower electrode assemblies.

[0068] In some implementations, the plasma jet or plasma jet emitter of the nozzle may be rasterized on the surface of the substrate 210. Multiple nozzles (e.g., 2 to 10 nozzles or an array or group of plasma jets) may perform the rasterization. In some variations, the multiple nozzles may be fixed relative to each other, and in some cases, the multiple plasma jet emitters may be arranged within a given nozzle.

[0069] In some implementations, the material removal system 200 may include an exhaust section (not shown) for rapidly removing plasma radicals and residues released from the substrate 210 and / or its edges during or after the EBR operation performed by the system 200. Rapid removal of residues and radicals ensures that the residues do not contaminate the substrate surface and that the radicals do not damage any formed devices present on the substrate surface (e.g., the front side).

[0070] In some implementations, the upper and lower electrodes may be offset vertically and / or horizontally from each other so as not to lie on the same vertical axis. In such cases, the electric field lines may be forced to pass through the desired edge region of the semiconductor substrate 210 (e.g., etching).

[0071] Referring here to Figure 2H, a cross-sectional view of the plasma source 208 having a confinement shelf 252 is shown. In some embodiments, as suggested above, the confinement shelf 252 may be part of the upper electrode subassembly 202 (e.g., integrated) or it may be an additional physical feature that can otherwise be incorporated into the system hardware. In some configurations, the confinement shelf 252 may be associated with the plasma source 208 (e.g., adjacent or nearby). In some cases, the confinement shelf 252 may be extended to define an exclusion region on the semiconductor substrate 210 where the plasma can be substantially suppressed below the confinement shelf 252.

[0072] In some implementations, an additional confinement shelf 253 may be present, as shown in Figure 2I. Similar to the confinement shelf 252, the additional confinement shelf 253 may be configured to further restrict the volume in which the plasma can emit light. For example, the confinement shelf 253 may confine and / or at least partially prevent the diffusion of etchants, materials, gases, plasma, etc., from the process volume 255. Allowing plasma in a localized region (e.g., the process volume 255) with an edge of the semiconductor substrate 210, while suppressing plasma in a volume or region 262 that may be undesirable, may improve the efficiency of the plasma generation components (e.g., the plasma source 208, the upper electrode subassembly 202, and / or the lower electrode subassembly 202) and may prevent processing in undesirable areas. The small gap 259, which enables the hydrostatic gas bearing, also provides rigidity and pressure to balance the pressure at, for example, the orifice outlet of the plasma source 208, suppresses plasma generation in the upper gap 259 where processing in the inner portion of the semiconductor substrate 210 is undesirable, and can improve the effectiveness of confinement by controlling the etching profile and etching width.

[0073] Shelf features such as the containment shelf 252 and / or additional containment shelf 253 can prevent other atmospheric gases (e.g., nitrogen) from entering the process volume 255 and further isolate the plasma processing the wafer edge.

[0074] Therefore, by utilizing the various physical configurations described above, reactive species (e.g., etching agents) can be substantially confined using hydrostatic gas bearings in a narrow gap between the wafer and hardware (e.g., upper electrode subassembly) to process the edges of a spinning wafer. Precise positioning and processing of the wafer is possible by modulating RF power to actuate the upper and / or lower electrode assemblies (e.g., in the XYZ directions) and / or by acting the wafer (e.g., in the XY direction). While the wafer is spinning, rapid modulation of RF power (which can be faster than the wafer rotation, as described above) and / or changes in the emission or flow rate of the generated plasma allow for processing (e.g., etching) at desired locations to remove unwanted material from the wafer edges. Processing of non-edge areas, such as inner portions, may be further possible based on wafer acting (e.g., in the XY directions to insert deeper into the narrow gap). In some cases, deposition may be carried out on the front side of the wafer, for example, to reverse over-etching or achieve curvature compensation, or on the back side of the wafer, for achieving curvature compensation.

[0075] As described above, the RF power can be modulated to alter the emission of plasma radicals as the substrate 210 spins, thereby creating a desired etching pattern. Such modulation may be performed based on signals generated by a controller, logic, differential drive, etc., coupled to the plasma source 208, the upper electrode, and / or the lower electrode.

[0076] Furthermore, as will be mentioned elsewhere in this specification, the controller or logic may further control one or any combination of the following parameters: the rotational speed of the substrate, the tip position relative to the substrate (e.g., in the x, y, and / or z axes), and etching rate parameters (such as plasma power, RF frequency, gas flow rate, gas composition, and / or gas pressure).

[0077] In some operations, parameters for control within the etching profile may include the radial position where material removal occurs. This may result in a specific radius (or diameter) of material processed on the substrate 210. The radius or diameter may be selected or specified for each incoming wafer. In some configurations, the material radius may be defined to be within a range of approximately 148–148.5 mm (or a difference of 0.5 mm). In some configurations, the material radius may be defined to be within a range of approximately 147–148 mm (or a difference of 1.0 mm). In some cases, the material radius may be defined to have no range and be substantially a vertical cut. This range of material radius may be narrowed by a precise margin (e.g., within 0.1 mm) so that the film thickness transition is sharp and creates a vertical cut that can help prevent the flow of radicals toward the inner part or center of the wafer.

[0078] Several parameters can also affect the deposition method. Such deposition parameters may include plasma power (on / off, or high / low between high and low RF power, rather than on to off), RF frequency, gas flow rate, gas composition, gas pressure, distance between the nozzle and the substrate, and substrate temperature. Any of these deposition parameters may affect the local thickness and / or internal stress of the back layer. These parameters may be controlled while the substrate is rotating or where the nozzle is positioned relative to the substrate (in XYZ space, radially and azimuthally). In configurations where multiple nozzles are used or included in a nozzle housing, each of the multiple nozzles may be controlled separately.

[0079] method Figure 3 is a flowchart showing a method 300 for processing a semiconductor substrate according to several embodiments. The substrate has a front side, which may have electronic device features fabricated thereon. One or more blocks of method 300 may be implemented by or caused by an apparatus or system controlled by a computing device. Such a system may include, as described above, one or more electrodes, an RF power supply, and / or various hardware components such as actuators (e.g., stages, aligners). Structures for implementing the functions shown in one or more of the blocks shown in Figure 3 may include hardware and / or software components of such an apparatus or system, or computing devices such as a controller or computer-readable device that includes a storage medium for storing computer-readable instructions and / or computer-executable instructions configured to cause a processor device to perform an operation when executed by a processor device. Exemplary components of the apparatus or system are described below with respect to Figure 5.

[0080] It should also be noted that the operations of Method 300 may be performed in any suitable order, not necessarily in the order shown in Figure 3. Furthermore, Method 300 may include additional or fewer operations than those shown in Figure 3 for processing the semiconductor substrate.

[0081] In block 310, method 300 may include the step of receiving an edge portion of a semiconductor substrate into a region between the first electrode and the second electrode. In some embodiments, the region may include one or more shelf features, each configured to prevent plasma from diffusing out of the region. One or more of the confinement shelf sections 252 and 253 shown in Figures 2H and 2I may be examples of one or more shelf features. In some embodiments, the substrate may be positioned within the region between the first electrode and the second electrode using an aligner configured to hold the substrate (e.g., via a vacuum chuck or an electrostatic chuck) and move the substrate toward the region (e.g., via XYZ movement). The region may be a process volume in which a portion of the substrate (e.g., an edge) can be processed using EBR (e.g., etching). The first and second electrodes may be part of their respective assemblies, and each may be configured to actuate (e.g., in the XYZ directions). For example, the upper and / or lower assemblies may increase the gap between them (moving in the opposing Z direction) to accept the substrate, and decrease the gap so that a small gap is created between the substrate and the surface of the upper subassembly, and another small gap is created between the substrate and the surface of the lower subassembly. In some cases, the small gap may be less than about 100 microns, for example, less than 3 mils. In some cases, the other small gap between the substrate and the surface of the lower subassembly may be even smaller, for example, less than about 10 microns.

[0082] In some implementations, an inert hydrostatic bearing gas (e.g., argon, helium, nitrogen, oxygen, air) may be introduced into this small gap (e.g., through an opening in the upper subassembly) to provide precise gap control, assistance in removing etched material, and / or low-friction bearing for spinning the substrate.

[0083] In block 320, method 300 may include the step of receiving a process gas and an inert gas through one or more inlets. In some embodiments, the process gas may include an etching agent gas received through a first inlet of one or more inlets, and the inert gas may include a carrier gas received through a second inlet of one or more inlets. Examples of process gases may be oxygen-based, fluorine-based, hydrogen-based, or chlorine-based chemicals. Examples of carrier gases may include argon, neon, or helium. In some embodiments, the process gas, the inert gas, or a mixture thereof may have a total pressure of about 200 Torr, or possibly higher.

[0084] In block 330, method 300 may include the step of using first and second electrodes and a process gas to generate a point plasma confined within the region between the first and second electrodes by one or more shelf features, wherein the point plasma has a pressure of at least 200 Torre. In some embodiments, the plasma pressure may be atmospheric pressure. In some embodiments, the plasma pressure may be a percentage of atmospheric pressure, for example, at least 200 Torre or at least 300 Torre, or between about 300 Torre and about 760 Torre.

[0085] In some embodiments, the plasma may be generated from a capacitively coupled plasma (CCP) source using direct plasma generation, as described with respect to Figure 2E. For example, RF power may be applied to a process gas, which may be a reactant species (e.g., an etchant gas such as oxygen), using first and second electrodes to create plasma radicals that act as an etchant in a region. The radicals are generated directly on the substrate edge. Therefore, there is no transport of radicals involved, which can reduce radical loss (e.g., via recombination), thereby improving the etching rate and etching profile during etching (block 330).

[0086] In block 340, method 300 may include the step of etching the edge portion of a semiconductor substrate using an etchant generated on the edge portion by a point plasma while the semiconductor substrate is rotating between the first and second electrodes relative to the first and second electrodes. In some embodiments, the exemplary etching rate may be about or at least about 1 mm / min, which is advantageously higher than conventional EBR. In some embodiments, the exemplary etching rate may be less than 1 mm / min. Such etching rates may correspond to the instantaneous etching rate in the plasma zone or the time-averaged effective etching rate around the entire circumference of the wafer. The etchant may be selected based on the material to be etched. For example, a carbon-based film may be etched from the substrate edge using an oxygen-based etchant. In some embodiments, the substrate may be rotated by an aligner or chuck that holds the substrate. The rotation speed may vary, for example, between 60 and 120 revolutions / min. The exemplary rotation speed may be 100 revolutions / min.

[0087] In some configurations, a separate inert purge gas (e.g., hydrogen, argon, helium, nitrogen, oxygen, or air) may be supplied to prevent the etched material from diffusing toward the center of the substrate. In some configurations, at least one containment tray may also be provided with a solid blockage to prevent the etched material from moving away from the edge and reaching other parts of the substrate. The containment trays 252 and 253 shown in Figures 2H and 2I may be examples of at least one containment tray.

[0088] In an alternative embodiment, the apparatus configured to process a semiconductor substrate may include first and second electrodes, and a controller configured to be coupled to a power supply, the controller applying power from the power supply to the first and second electrodes to generate plasma in a region using the first and second electrodes based at least on a process gas received through a first inlet, the process gas being delivered into the region using a carrier gas from a second inlet, the plasma being at least partially confined within the region by one or more confinement racks having a pressure of at least 200 Torr, and the generated plasma being used to etch at least a portion of the semiconductor substrate while the semiconductor substrate is rotating, and the etching rate may be about 1 millimeter (mm) / min or less than 1 mm / min.

[0089] Figure 4 is a flowchart showing a method 400 for processing a semiconductor substrate according to several embodiments. The substrate has a front side, which may have electronic device features fabricated thereon. One or more blocks of method 400 may be implemented by or caused by an apparatus or system controlled by a computing device. Such a system may include, as described above, one or more electrodes, an RF power supply, and / or various hardware components such as actuators (e.g., stages, aligners). Structures for implementing the functions shown in one or more of the blocks shown in Figure 4 may include hardware and / or software components of such an apparatus or system, or computing devices such as a controller or computer-readable device that includes a storage medium for storing computer-readable instructions and / or computer-executable instructions configured to cause a processor device to perform an operation when executed by a processor device. Exemplary components of an apparatus or system are described below with respect to Figure 5.

[0090] It should also be noted that the operations of Method 400 may be carried out in any suitable order, not necessarily in the order shown in Figure 4. Furthermore, Method 400 may include additional or fewer operations than those shown in Figure 4 for processing the semiconductor substrate.

[0091] In block 410, method 400 may include the step of receiving an edge portion of a semiconductor substrate in the region between the first electrode and the second electrode. In some embodiments, the region may include one or more containment racks (e.g., 252 and / or 253). This operation may be implemented similarly to block 310 and will not be repeated for brevity. In some implementations, as described above, an inert hydrostatic bearing gas (e.g., argon, helium, nitrogen, oxygen, air) may be introduced into the small gap.

[0092] In block 420, method 400 may include the step of generating an etching agent having a pressure of at least 200 Torr using a reaction gas and a first electrode. In some embodiments, an inert gas may also be introduced together with a process gas (e.g., reaction gas), and the process gas and inert gas may have a total pressure of at least 200 Torr. In some embodiments, the etching agent may be plasma radicals generated from an inductively coupled plasma (ICP) source using indirect plasma generation, as described with respect to Figure 2D. For example, RF power may be applied to a process gas which may be a reactant species (e.g., an etching agent gas such as oxygen) using the first electrode. An example of the first electrode may be the upper electrode of the upper electrode subassembly 202. Other electrodes, such as a second electrode, may not be involved in the generation of the etching agent in indirect plasma generation. RF power may not be applied to electrodes other than the first electrode. In some embodiments, the plasma pressure may be approximately atmospheric pressure (about 760 Torr), or a percentage of atmospheric pressure, for example, at least 200 Torr, or at least 300 Torr.

[0093] In block 430, method 400 may include the step of transporting an etchant toward an edge portion of a semiconductor substrate positioned in close proximity to a first electrode using a carrier gas. Optionally, the carrier gas may be an inert carrier gas (e.g., argon, neon, helium) that can be used to transport plasma radicals of the etchant from a plasma source via a nozzle or tip. The edge of the semiconductor substrate may be positioned directly beneath such a nozzle or tip so that the edge portion is exposed to the transported plasma radicals.

[0094] In block 440, method 400 may include the step of etching a portion of a semiconductor substrate using an etchant while the semiconductor substrate is rotating between a first electrode and a second electrode. In some embodiments, the etchant may be contained within a region by one or more containment trays. In some embodiments, the exemplary etching rate may be about or at least about 1 mm / min, which is advantageously higher than conventional EBRs. In some embodiments, the exemplary etching rate may be less than 1 mm / min. The etchant may be selected based on the material to be etched. For example, a carbon-based film may be etched from the substrate edge using an oxygen-based etchant. In some embodiments, the substrate may be rotated by an aligner or chuck that holds the substrate. The rotation speed may vary, for example, between 60 and 120 revolutions per minute (RPM). An exemplary rotation speed may be 100 revolutions per minute. In some mounting configurations, the rotation speed may be as low as about 10 RPM or up to 300 RPM.

[0095] In some configurations, a separate inert purge gas (e.g., hydrogen, argon, helium, nitrogen, oxygen, or air) may be supplied to prevent the etched material from diffusing toward the center of the substrate. In some configurations, at least one containment tray may also be provided with a solid blockage to prevent the etched material from moving away from the edge and reaching other parts of the substrate. The containment trays 252 and 253 shown in Figures 2H and 2I may be examples of at least one containment tray.

[0096] Device-Computer and Controller Embodiments Figure 5 shows a simplified block diagram of an APPJ-based material removal system or apparatus 500 described herein, which may include at least one subassembly 510, at least one actuator 520 (e.g., a chuck, an aligner), and at least one controller device 530 coupled to the subassembly 510 and / or the actuator 520. In some embodiments, the subassembly 510 may include one or more subassemblies, an example of which includes an upper subassembly and a lower subassembly (e.g., an upper electrode and a lower electrode) having one or more electrodes 512 each associated therewith. Thus, at least one controller device 530 may be configured to be coupled to one or more electrodes 512. At least one controller device 530 may also be configured to be coupled to an external RF power supply 521. The controller 530 may use an internal RF power supply 519 and / or an external RF power supply 521 to power at least the components of the subassembly 510 and / or the actuator 520. In some embodiments, the subassembly 510 may further include one or more gas inlets (or inlet lines) 514. An example of a gas inlet 514 may include a first gas inlet for supplying process gas (and / or curtain gas) and / or a second gas inlet for supplying purge gas. The inlets 514 may be configured to deliver gas and / or plasma from a source to the outlet of the nozzle 516. The axis of the nozzle 516 may be at any angle with respect to a plane parallel to the substrate, and the angle is adjustable between orthogonal and non-orthogonal (angled). In some embodiments, while the substrate 502 is positioned in close proximity to a portion of the subassembly 510 (for example, between the upper and lower electrode assemblies, which have a small gap above the substrate 502 for the flow of purge gas or hydrostatic bearing gas), the actuator 520 may include a chuck (e.g., a vacuum chuck, an electrostatic clamp) and / or an aligner configured to hold, move (e.g., along XYZR-θ), and / or rotate the substrate 502.In some embodiments, the actuator 520 may include a stage (e.g., XYZ) configured to actuate at least a portion of the subassembly 510. For example, the aligner may move the substrate 502 in the XYZ directions into the space between an upper or lower assembly that is vertically movable to hold and receive the substrate 502, according to the mounting configuration described herein.

[0097] In some embodiments, the subassembly 510 may include at least one nozzle 516, which is at least partially housed by the subassembly 510 or at least partially housed by a nozzle housing that can be at least partially housed within the subassembly 510. The nozzle 516 may be configured to guide a plasma jet into a process volume in which a portion of the substrate 502 is positioned, thereby etching and removing material on the edges of the substrate 502, for example. The actuator 520 may be configured to adjust the position of the substrate 502 relative to the nozzle 516 during etching, and the controller 530 may be configured to control an internal RF power supply 519 and / or an external RF power supply 521 to power, for example, a plasma source 518 to generate plasma radicals that etch the substrate edges. The plasma source 518 may be a direct plasma source (for example, capable of applying RF power to upper and lower electrodes) or an indirect plasma source (for example, capable of applying RF power to the upper electrode).

[0098] The apparatus 500 may be configured to implement the methods 300 and 400 described above using one or more of the components 510 to 530 described above. In some embodiments, the operation of the apparatus 500 may include the step of generating and / or transferring plasma radicals from the plasma source 518 at approximately atmospheric pressure or a percentage thereof (e.g., at least about 200 to 300 Torre), and may improve the etching of a portion or edge of the substrate 502 with a purge gas and / or a static gas bearing gas. The apparatus 500 advantageously enables an etching rate of, for example, about or at least about 1 mm / min.

[0099] In various configurations, the controller 530 may be further configured to adjust one or more process conditions during the operation of the apparatus 500. Process conditions may include the rotational speed of the substrate 502 using the actuator 520, the position and / or angle associated with the nozzle 516, the RF power of the RF power supply 519, the plasma power associated with the plasma jet of the nozzle 516, the RF frequency associated with the plasma jet of the nozzle 516, the residence time of the plasma jet at a position on the substrate, the gas flow rate, the gas composition, the gas pressure, or any combination thereof. In some cases, the controller 530 may be configured to adjust the plasma power during a single rotation of the substrate 502. In some cases, the controller 530 may be configured to repeatedly adjust (e.g., high / low or on / off) the plasma power over a number of rotations of the substrate 502.

[0100] In some implementations, the actuator 520 may be configured to rotate the substrate 502 during EBR / etching of the substrate edge. The actuator 520 may also be configured to translate the substrate 502 (e.g., along the x and / or y axes) along a plane parallel to the substrate or along a plane perpendicular to the plane parallel to the substrate (e.g., the z-axis), or to move the substrate radially relative to the substrate. Depending on the application, the rotation speed of the substrate may be 60 to 120 revolutions per minute. In one example, the rotation speed may be about 100 revolutions per minute. The actuator 520 may also be configured to result in rasterized deposition of material. The actuator 520 may also be configured to maintain a small gap between the substrate and the surface of the subassembly 510 during etching, and the gap may be about 0 to 100 microns.

[0101] This disclosure may be described in the general context of computer code or machine-usable instructions, including computer-executable instructions such as program modules, which are executed by computers or other machines, such as personal data assistants or other handheld devices. Generally, a program module, which includes routines, programs, objects, components, data structures, etc., refers to code that performs a particular task or implements a particular abstract data type. This disclosure may be implemented in a variety of system configurations, including handheld devices, consumer electronics, general-purpose computers, and specialized computing devices. This disclosure may also be implemented in a distributed computing environment where tasks are performed by remote processing devices linked through a communication network.

[0102] In some implementations, the “controller” (e.g., 190) is part of a system including various types of sensors as described herein. Such a system includes a fabrication tool having a camera sensor. Such a system may include a semiconductor processing apparatus including one or more process tools, one or more chambers, one or more platforms for processing, and / or specific processing components (such as a wafer pedestal, a gas flow system). These systems may be integrated with electronics for controlling pre-processing, in-processing, and post-processing operations of a semiconductor wafer or substrate. The controller may be implemented in analytical logic as described above, or coupled thereto. The controller may be implemented as logic, such as electronics having one or more integrated circuits, memory devices, and / or software that receive commands, issue commands, control operations, and / or enable sensing operations.

[0103] Electronic devices that can control various components or sub-parts of one or more systems may be referred to as “controllers.” Depending on the processing requirements and / or the type of system, a controller may be programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, transfer of wafers to and from tools and other transfer tools, and / or load locks connected to or interfaced with a particular system.

[0104] Generally speaking, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive and issue instructions, control operations, enable cleaning operations, enable endpoint measurement, etc. Integrated circuits may include chips in the form of firmware that store program instructions, chips defined as digital signal processors (DSPs), application-specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers (e.g., software) that execute program instructions. Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operating parameters for performing a particular process on a semiconductor wafer or system. In some embodiments, operating parameters may be part of a recipe defined by a process engineer to achieve one or more process steps during processing of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0105] The controller may be configured to control or cause control of various components or sub-components of one or more systems. Depending on the processing requirements and / or the type of system, the controller may be programmed to control any of the following: process which may be used by the fabrication tool during fabrication operations, including adjusting or maintaining the delivery of process gas; temperature settings (e.g., heating and / or cooling), including substrate temperature and chamber wall temperature; pressure settings, including vacuum settings; plasma settings; RF matching circuit settings; and substrate position and movement settings, including the entry and exit of the substrate to and from the fabrication tool and / or load lock. Process gas parameters include process gas composition, flow rate, temperature, and / or pressure. Particularly in relation to the disclosed embodiments, controller parameters may also relate to the power, pulse rate, and / or RF frequency of the plasma generator.

[0106] Process parameters under the controller's control may be provided in the form of a recipe or entered using a user interface. Signals for monitoring the process may be provided by the system controller's analog and / or digital input connections. Signals for controlling the process are output to the depositor's analog and digital output connections.

[0107] In one example, instructions for igniting or maintaining a plasma are provided in the form of process recipes. The relevant process recipes may be arranged sequentially, so that at least some instructions for the process can be executed simultaneously. In some implementations, instructions for setting one or more plasma parameters may be included in a recipe preceding the plasma ignition process. For example, a first recipe may include instructions for a first time delay, instructions for setting the flow rates of an inert gas (e.g., helium) and / or a reactive gas, and instructions for setting the plasma generator to a first power setpoint. A second subsequent recipe may include instructions for a second time delay and instructions for enabling the plasma generator to supply power under a defined set of parameters. A third recipe may include instructions for a third time delay and instructions for deactivating the plasma generator. It will be understood that these recipes may be further subdivided and / or repeated in any preferred manner within the scope of this disclosure. In some deposition processes, the duration of the plasma strike may correspond to a few seconds, such as about 3 to 15 seconds, or it may include longer durations, such as up to about 30 seconds. In certain implementations described herein, much shorter plasma strikes may be applied during the processing cycle. Such plasma strike durations may be less than about 50 milliseconds, and in certain examples, about 25 milliseconds are utilized. As described, the plasma may be pulsed.

[0108] In some embodiments, the controller is configured to control and / or manage the operation of the RF signal generator. In certain implementations, the controller is configured to determine upper and / or lower thresholds for the RF signal power sent to the fabrication tool, the actual (such as real-time) level of the RF signal power sent to the integrated circuit fabrication chamber, the RF signal output activation / deactivation time, the RF signal modulation duration (e.g., high / low or on / off state), the duty cycle, the operating frequency, and so on.

[0109] As a further example, the controller may be configured to control the timing of various operations, gas mixing, pressure within the fabrication tool, temperature within the fabrication tool, temperature of the substrate or pedestal, position of the pedestal, chuck and / or susceptor, and the number of cycles performed on one or more substrates.

[0110] The controller may include one or more programs or routines for controlling designed subsystems related to the fabrication tool. Examples of such programs or routines include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program. The substrate positioning program may include program code for process tool components used to load the substrate onto the pedestal and control the spacing between the substrate and other parts of the fabrication tool. The positioning program may also include instructions for moving the substrate in and out of the reaction chamber to deposit a film on the substrate and to clean the chamber.

[0111] The process gas control program may include code for controlling the gas composition and flow rate, as well as code for introducing gas into one or more process stations before deposition to stabilize the pressure within the process stations. In some implementations, the process gas control program includes instructions for introducing gas during film formation on substrates within the reaction chamber. This may include introducing a different number of cycles of gas to one or more substrates in a batch of substrates. The pressure control program may include code for controlling the pressure within the process stations by, for example, adjusting throttle valves in the exhaust system of the process stations, gas flow to the process stations, etc. The pressure control program may include instructions for maintaining the same pressure while depositing a different number of cycles on one or more substrates during batch processing.

[0112] The heater control program may include code for controlling the current to the heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (such as helium) to the substrate.

[0113] In some implementations, there may be a user interface associated with the controller. The user interface may include a display screen, a graphical software display and / or processing conditions for the device, as well as user input devices such as a pointing device, keyboard, touch screen, and microphone.

[0114] In some implementations, the controller may be part of, or coupled to, a computer integrated with, coupled to, networked to, or in some way networked to, the system. For example, the controller may be all or part of a “cloud” or fab-host computer system, enabling remote access to wafer processing. The computer enables remote access to the system to monitor the current progress of processing operations, examine the history of past processing operations, examine trends or performance metrics from multiple processing operations, modify parameters of the current processing, set process steps to follow the current processing, or initiate new processing. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network that may include a local network or the internet. The remote computer may include a user interface that allows input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data specifying the parameters of each process step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Therefore, as described above, the controllers may be distributed, for example, by comprising one or more individual controllers that are networked together and operate toward a common purpose, such as the processes and control described herein. An example of a distributed controller for such purposes may be one or more integrated circuits on a chamber that communicate with one or more remotely located integrated circuits (such as platform-level or part of a remote computer) that are combined to control the processes on the chamber.

[0115] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, clean chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems related to or usable in the processing and / or manufacturing of semiconductor wafers.

[0116] The system software can be organized in many different ways, which may have various architectures. For example, various chamber component subroutines or control objects may be written to control the operation of the chamber components necessary for the execution of the deposition process (and possibly other processes) according to the disclosed embodiments.

[0117] As described above, depending on one or more process steps performed by the tool, the controller may communicate with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used for material transfer to carry wafer containers to and from tool locations and / or load ports in the semiconductor manufacturing plant.

[0118] Various modifications to the implementations described herein will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Accordingly, the claims are not intended to be limited to the implementations shown herein, but should be given the broadest scope consistent with this disclosure, the principles disclosed herein, and the novel features.

[0119] Certain features described herein in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately or in any appropriate partial combination in multiple implementations. Furthermore, features may be described above as acting in a particular combination, and a patent may be claimed as such initially, although one or more features from the claimed combination may, in some cases, be removed from the combination, and the claimed combination may cover a partial combination or a variation of a partial combination.

[0120] Similarly, while the operations are shown in a specific order in the diagrams, this should not be understood as requiring that such operations be performed in that specific order, or in a sequential order, or that all of the operations shown be performed, in order to achieve the desired result. Furthermore, the diagrams may schematically illustrate another exemplary process in the form of a flow chart. However, other operations not illustrated can be incorporated into the schematicly illustrated exemplary process. For example, one or more additional operations can be performed before, after, simultaneously with, or in between any of the illustrated operations. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the above-described implementations should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged in multiple software products. Furthermore, other implementations are within the scope of the following claims. In some cases, the operations described in the claims can be performed in a different order, and the desired result can still be achieved. [Explanation of Symbols]

[0121] 100 Material Removal System 101 Source Subassembly 102 Semiconductor substrates 102-e Edge 102-i Inner part 104 Upper subassembly 106 Lower subassembly 108 Plasma Source 110 Aligner Hardware 111 directions 112 stages 114 Center axis 137 The third channel 200 Material Removal System 202 Upper electrode subassembly 203 Upper electrode 204 Lower electrode subassembly 205 Lower electrode 206 stages 208 Plasma Source 210 Semiconductor substrates 212 Alaina 213 Chuck 214 pins 215 Alignment Sensor 221 Recombination 231 First Entrance 232 Second Entrance 233 First electrode 234 Second electrode 235 First Channel 236 Second Channel 238 Dielectric Materials 239 Nozzles 242 First opening 243 Second opening 250 Tip 252 Confinement shelf section 253 Additional containment shelf 254 Process gases 255 process volume 256 Purge gas 257 Opening 258 Dielectric Barrier 259 Upper gap 260 Dielectric Shield 261 Lower gap 262 areas 300 ways 400 ways 500 Material removal system or device 502 circuit board 510 Subassembly 512 Electrode 514 Gas Inlet 516 Nozzles 518 Plasma source 519 Internal RF power supply 520 Actuators 521 External RF power supply 530 Controller device

Claims

1. A method for processing a semiconductor substrate, wherein the method is A step of receiving at least an edge portion of the semiconductor substrate in a region between a first electrode and a second electrode, wherein the region comprises one or more shelf features, each configured to prevent the plasma from diffusing from the region; A step of receiving process gas and inert gas from one or more inlets, A step of generating a point plasma confined in the region between the first and second electrodes by one or more shelf features using the first and second electrodes and the process gas, wherein the point plasma has a pressure of at least 200 Torr, The steps include etching the edge portion of the semiconductor substrate using an etching agent generated on the edge portion by the point plasma while the semiconductor substrate is rotating between the first and second electrodes and relative to the first and second electrodes, and Methods that include...

2. The method according to claim 1, wherein the process gas includes an etching agent gas received through a first inlet, and the inert gas includes a carrier gas received through a second inlet.

3. The method according to claim 1, wherein the pressure of the plasma is between approximately 300 Torre and approximately 760 Torre.

4. The method according to claim 1, wherein the step of generating plasma in the region between the first and second electrodes includes the step of applying radio frequency (RF) power to both the first electrode and the second electrode in order to directly generate the etching agent on the edge portion of the semiconductor substrate.

5. The method according to claim 1, wherein the rotation speed of the semiconductor substrate is at least 10 times / minute.

6. The method according to claim 1, wherein the rotation speed of the semiconductor substrate is a maximum of 300 revolutions per minute.

7. The method according to claim 1, wherein the process gas includes an etching agent gas, and the point plasma confined within the region is generated based on the etching agent gas.

8. The method according to claim 7, wherein the etching agent gas includes an oxygen-based, fluorine-based, hydrogen-based, or chlorine-based chemical substance.

9. The step of receiving at least the edge portion of the semiconductor substrate is The step of positioning a portion of the semiconductor substrate in proximity to the first surface of a first hardware component related to the first electrode and in proximity to the second surface of a second hardware component related to the second electrode, The gap between the first surface and the semiconductor substrate includes a distance of 100 microns or less. The method according to claim 1.

10. The method according to claim 9, further comprising the step of releasing a purge gas through the gap between the first surface and the semiconductor substrate, wherein the purge gas includes an inert gas, a process gas, or a combination thereof.

11. The method according to claim 9, further comprising the step of releasing a hydrostatic bearing gas through the gap between the first surface and the semiconductor substrate, wherein the hydrostatic bearing gas includes argon, helium, nitrogen, oxygen, or a combination thereof.

12. The method according to claim 1, further comprising the step of selecting a radial position in which the edge portion of the semiconductor substrate is etched, wherein the etching removes material deposited at the radial position.

13. An apparatus configured to process a semiconductor substrate, wherein the apparatus is The first electrode and A second electrode positioned opposite the first electrode to form a region between the first electrode and the second electrode that is sized to accept at least a portion of the semiconductor substrate, wherein the first and second electrodes are configured to be coupled to a power supply, One or more containment shelves located adjacent to the aforementioned region and configured to contain the gas and plasma, The first gas inlet and The second gas inlet, A controller configured to be coupled to the first and second electrodes and the power supply, wherein the controller When coupled to the first and second electrodes and the power supply, power is applied from the power supply to the first and second electrodes to generate plasma in the region using the first and second electrodes based at least on a process gas received through the first gas inlet, the process gas is delivered to the region using a carrier gas from the second gas inlet, the plasma is at least partially confined within the region by one or more confinement racks, has a pressure of at least 200 Torr, and the generated plasma is used to etch at least the portion of the semiconductor substrate while the semiconductor substrate is rotating. The controller is further configured as follows: A device equipped with the following features.

14. The apparatus according to claim 13, wherein the pressure of the plasma is between approximately 300 Torre and approximately 760 Torre.

15. The apparatus according to claim 13, wherein the process gas includes an oxygen-based, fluorine-based, hydrogen-based, or chlorine-based chemical substance.

16. An upper subassembly and a lower subassembly, wherein the upper subassembly comprises the first electrode and the first surface, and the lower subassembly comprises the second electrode and the second surface, An opening for supplying an inert gas to the gap between the semiconductor substrate and the first surface Furthermore, The first surface is configured to provide a hydrostatic gas bearing on the semiconductor substrate using the inert gas, The apparatus is configured to receive at least the portion of the semiconductor substrate between the upper subassembly and the lower subassembly. The apparatus according to claim 13.

17. The apparatus according to claim 16, further comprising at least one containment shelf configured to prevent at least a portion of the generated plasma from flowing into the gap between the semiconductor substrate and the first surface.

18. The apparatus according to claim 16, further comprising a dielectric barrier associated with the upper subassembly and a dielectric barrier associated with the lower subassembly.

19. A method for processing a semiconductor substrate, wherein the method is A step of receiving the edge portion of the semiconductor substrate in the region between the first electrode and the second electrode, wherein the region comprises one or more containment shelves, A step of generating an etching agent having a pressure of at least 200 Torre using the reaction gas and the first electrode, A step of using a carrier gas to transfer the etching agent toward the edge portion of the semiconductor substrate positioned in close proximity to the first electrode, The steps include etching the edge portion of the semiconductor substrate using the etching agent while the semiconductor substrate is rotating between the first and second electrodes, wherein the etching agent is contained within the region by one or more containment shelves. Methods that include...

20. The method according to claim 19, wherein the reaction gas includes an oxygen-based, fluorine-based, hydrogen-based, or chlorine-based chemical substance.

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