Method and apparatus for SAR-type analog-to-digital conversion

Abstract

A successive approximation register (SAR) type analog-to-digital converter (ADC) can be used to generate N bits of first digital data and N bits of second digital data for analog data. If the second digital data and the first digital data contain a first most significant bit (MSB) sequence with the same value, the SAR ADC can be used in partial mode to generate N bits of third digital data for the analog data. In partial mode, the SAR ADC is configured to skip determining the second MSB sequence of the third digital data and determine only the remaining bits of the third digital data. If the second digital data and the first digital data do not contain a first MSB sequence with the same value, the SAR ADC operates in full mode to determine all bits of the N bits of the third digital data.

Description

[Technical Field]

[0001]

[0001] Cross-reference of related applications This patent application claims priority to, specifically, a continuation of, U.S. Patent Application No. 18 / 669,304, filed on May 20, 2024, entitled “Method and Apparatus for SAR Analog-to-Digital Conversion,” which is incorporated herein by reference as if it were a copy in its entirety.

[0002]

[0002] The disclosure generally relates to the field of analog-to-digital conversion, and in particular embodiments to methods and apparatus for successive approximation register (SAR) type analog-to-digital conversion. [Background technology]

[0003]

[0003] Analog-to-digital converters (ADCs) are commonly used in digital electronic equipment systems to convert analog signals into digital signals. Digital signals can be further processed by various digital processors, such as digital audio processors, digital video processors, and wireless communication processors.

[0004]

[0004] In some applications, the ADC may be implemented as a standalone semiconductor device, and in some other applications, the ADC may be integrated with other circuits on a single integrated circuit. Various analog-digital architectures can be used, but successive approximation register (SAR) ADCs are widely used in a variety of applications such as battery-powered devices, pen digitizers, industrial control, and multiplexed data acquisition. SAR ADCs output digital signals by performing a successive approximation algorithm (sometimes called a "binary search algorithm"). The SAR architecture offers high performance with a moderate sample rate, moderate resolution, and low power consumption. [Overview of the project]

[0005]

[0005] Technical advantages are generally achieved by embodiments of the present disclosure describing methods and apparatus for successive approximation register type analog-to-digital conversion.

[0006]

[0006] According to one aspect of the present disclosure, a method is provided which uses a successive approximation register (SAR) type analog-to-digital converter (ADC) to generate N bits of first digital data and N bits of second digital data for an analog voltage, wherein N is an integer greater than 1, and when it is determined that the second digital data and the first digital data include a first most significant bit (MSB) sequence having the same value, the SAR type ADC is used in partial mode to generate N bits of third digital data for the analog data, wherein the SAR type ADC is configured to skip determining the value of the second MSB sequence for the third digital data.

[0007]

[0007] According to another aspect of the present disclosure, a successive approximation register (SAR) type analog-to-digital converter (ADC) is used to generate first digital data and second digital data for analog data, wherein the first digital data and the second digital data each have N bits, and it is determined whether the second digital data includes a first bit sequence having the same value as a first bit sequence of the first digital data, wherein the first bit sequence begins with the first most significant bit (MSB), and the second digital data includes a first bit sequence having the same value as a first bit sequence of the first digital data. A method is provided which includes determining whether to generate N bits of third digital data for analog data in partial mode using a SAR ADC, based on whether a condition is met; and, if the condition is met, generating third digital data in partial mode, wherein the value of the second bit sequence of the third digital data is set to the value of each bit sequence of the second digital data, wherein the second bit sequence starts from the first MSB and contains less than N bits; and determining the value of the remaining bits of the third digital data using a SAR ADC.

[0008]

[0008] For a more complete understanding of the present disclosure and its advantages, refer hereto to the following description in conjunction with the attached drawings. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic block diagram of an exemplary successive approximation register (SAR) type analog-to-digital converter (ADC) using conventional technology. [Figure 2] Figure 1 is a waveform diagram showing the operation of a SAR-type ADC. [Figure 3] Figure 1 is a schematic block diagram of an exemplary capacitive DAC that may be used in the SAR-type ADC. [Figure 4]This is a flowchart illustrating an exemplary method for SAR-type analog-to-digital (A / D) conversion using a SAR-type ADC. [Figure 5] This is a flowchart illustrating an exemplary method for SAR-type A / D conversion according to embodiments of the present disclosure. [Figure 6] This is a flowchart of another exemplary method for SAR-type A / D conversion according to embodiments of the present disclosure. [Figure 7] This is a flowchart of yet another exemplary method for SAR-type A / D conversion according to embodiments of the present disclosure. [Figure 8] This is a block diagram of an exemplary SAR-type ADC circuit according to an embodiment of the present disclosure. [Figure 9] This is a block diagram of another exemplary SAR-type ADC circuit according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0010]

[0018] Corresponding numbers and symbols in different figures generally refer to corresponding parts unless otherwise specified. The drawings are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale.

[0011]

[0019] The preparation and use of embodiments of this disclosure are described in detail below. However, it should be understood that the concepts disclosed herein can be embodied in a wide variety of specific circumstances, and the specific embodiments described herein are merely illustrative and not intended to limit the scope of the claims. Furthermore, it should be understood that various modifications, substitutions, and alternatives can be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0012]

[0020] Furthermore, one or more features from one or more of the embodiments described below can be combined to create alternative embodiments not expressly described, and features suitable for such combinations will be understood within the scope of this disclosure. Accordingly, the appended claims are intended to encompass any such modifications or embodiments.

[0013]

[0021] Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used in a variety of applications requiring moderate conversion speed and resolution, such as monitoring environments, data acquisition, or applications involving frequencies lower than the conversion frequency. SAR ADCs require less power for green power applications.

[0014]

[0022] Figure 1 is a schematic block diagram of a conventional SAR-type ADC100. The SAR-type ADC100 samples an analog signal and converts it into a digital signal, and is configured so that each sampled value of the analog signal is converted into an N-bit digital value. Specifically, the SAR-type ADC100 takes an analog voltage (or value, or data) V of the input analog signal. IN Sample the data and convert it into an N-bit digital signal / data / value D OUT It is configured to convert to [a specific format]. The SAR-type ADC100 is sometimes called an N-bit SAR-type ADC, having an N-bit resolution. N is an integer greater than 1. For example, N could be 4, 8, 12, etc.

[0015]

[0023] In the illustrated example, the SAR-type ADC 100 includes a sample-and-hold (S / H) circuit 102, a comparator 104, a digital-to-analog converter (DAC) 106, a SAR block / circuit 108, and a clock block / circuit 110. The operation of the SAR-type ADC 100 generally includes a sampling phase and a conversion phase. In the sampling phase, the SAR-type ADC 100 receives an analog voltage V INSample it and obtain and hold the sampled analog value. In the conversion phase, the SAR type ADC100 converts the sampled analog value into an N-bit digital value.

[0016]

[0024] Specifically, the S / H circuit 102 samples the analog voltage V IN and obtains the sampled analog value V SH and is configured to store the sampled value V SH for the conversion phase. The terms "sampled analog value" and "sampled value" are used interchangeably in this specification. The S / H circuit 102 is coupled to the comparator 104 and outputs the sampled value V SH to the comparator 104.

[0017]

[0025] The comparator 104 is an analog comparator and is configured to compare the output of the S / H circuit 102, that is, the sampled value V SH with the analog threshold value V REF generated by the DAC106 based on the reference voltage V DAC . The output of the comparator 104 can be 1 or 0 depending on the comparison of the comparator 104. The output of the comparator 104 is passed to the SAR block 108 as the value of the current bit being converted and is registered and processed by the SAR block 108. The SAR block 108 controls the value of the threshold V DAC generated by the DAC106 and outputs the converted digital value of the sampled analog value of the input analog signal V IN . The output of the SAR block 108 is the N-bit digital signal D OUT of the input analog voltage V IN . The clock block 110 provides a clock signal for the operation of the S / H circuit 102 and the SAR block 108. The threshold V DAC used to determine the (currently being converted) bit is determined based on the reference voltage V REF and the previously determined bits.

[0018]

[0026] Sampling value V SH The N bits of the converted digital value are determined one by one by a binary search process, from the most significant bit (MSB) to the least significant bit (LSB), for example, from bit N to bit 1 (which may also be called bit (N-1) to bit 0, the Nth bit to the 1st bit, or the (N-1)th bit to the 0th bit, depending on various naming conventions). A SAR ADC generally requires one clock cycle to sample the input analog voltage and obtain one sampled value, and one clock cycle to determine each bit of its digital output corresponding to the sampled value. Therefore, an N-bit SAR ADC generally requires (N+1) clock cycles to digitize the sampled analog value into an N-bit digital value. Thus, the conversion time for an N-bit SAR ADC is (N+1) clock cycles per sampled value. Therefore, the conversion rate is f / (N+1), where f is the clock signal frequency. A clock cycle may also be called a conversion cycle in which one bit of the N-bit digital value is determined.

[0019]

[0027] Figure 200 shows an exemplary conversion operation of the SAR-type ADC100 with N=4. The horizontal axis represents time, and the vertical axis represents voltage. Waveform 210 shows the threshold V determined for each bit. DAC This is shown. Line 220 (dashed line) represents the sampled analog value V SH (V IN This shows the sampled analog value V using four clock cycles. SH The binary search algorithm determines the 4 bits of the converted digital value. SH It begins by determining the MSB (or the first MSB of the 4-bit system), i.e., bit 4. To determine the first MSB, the SAR-type ADC100 uses the full-scale value (reference signal V REF A threshold V equal to half of ) DAC , that is, V DAC =(V REFGenerate ( / 2) and sample value V SH threshold V DAC This is compared with the result of this comparison. The MSB (bit 4) is determined according to the result of this comparison. For example, V SH <V DAC In this case, the MSB is 0, and V SH ≥V DAC In this case, the MSB is 1. In this example, V SH <V DAC , that is, V SH <(V REF ( / 2), and therefore bit 4 = 0.

[0020]

[0028] To determine the next effective bit (second MSB), i.e., bit 3, the SAR-type ADC100 compares the sampling value to 0 and (V) based on the previous comparison. REF Since it has been found to be between / 2), based on the previous comparison result for bit 4, another threshold V DAC =(V REF The SAR-type ADC100 then generates the sampled value V SH This threshold V DAC =(V REF Compare with ( / 4) V SH >V DAC , that is, V SH > (V REF Since ( / 4), bit 3 = 1.

[0021]

[0029] For the next valid bit, i.e., bit 2, the SAR-type ADC100 generates another threshold based on the previous comparison for bit 3. In this case, the previous comparison determined that the sampling value was (V REF / 4) and (V REF Since it has been found to be between ( / 2), the threshold is V DAC =(3 / 8V REF ) is set to V SH <V DAC , that is, V SH <(3 / 8V REF ) Therefore, bit 2 = 0. This procedure continues until all 4 bits of the digital output are determined. If bit 1, V DAC=(5 / 16V REF ) and bit 1 = 1. Therefore, the output digital value is 0101. Waveform 210 shows the different thresholds used to determine the four bits.

[0022]

[0030] The S / H circuit 102 and DAC 106 of the SAR-type ADC 100 can be implemented using an array of binary-weighted capacitors, sometimes called a capacitive DAC. For an N-bit SAR-type ADC, the capacitive DAC can include an array of N capacitors, each with binary-weighted capacitance values ​​plus one "dummy LSB" capacitor. Figure 3 shows an exemplary circuit 300 for such an implementation of the 4-bit SAR-type ADC described in Figure 2. As shown, the circuit 300 includes a 4-bit capacitive DAC 310 connected to the comparator 104. The capacitive DAC 310 includes four capacitors 312, 314, 316, and 318, each with binary-weighted capacitance values ​​of 8C, 4C, 2C, and C respectively, and a dummy LSB capacitor 320 with capacitance C. These capacitors are connected in parallel such that the total capacitance of the five capacitors 312-320 is equal to 16C. Each capacitor has a first terminal connected to the first terminal (e.g., the negative terminal) of the comparator 104, and the analog input voltage V is connected via switches, e.g., single-pole triple-throw switches S1 to S5. IN , reference voltage V REF Or each has a second terminal which can be connected to ground. The first terminals of capacitors 312 to 320 are sometimes collectively referred to as the common terminal T1 of the capacitors (which is also the first terminal of comparator 104). The second terminal (positive terminal) T2 of comparator 104 is connected to ground. That is, V T2 = 0. Capacitors 312, 314, 316, and 318 are sometimes referred to as corresponding to bits 4 through 1 of the output digital value, respectively. A switch S0 is connected between terminals T1 and T2. Switch S0 is used to control the switching between the sampling phase and the conversion phase.

[0023]

[0031] During the sampling phase, switch S0 is closed, the common terminal T1 of the capacitor is connected to ground, and the second terminals of capacitors 312-318 are connected to the analog input voltage (V IN It is connected to ). Therefore, the analog input voltage is sampled on capacitors 312-318 in the capacitor array, for example, charge V SH This is stored in the capacitor array.

[0024]

[0032] During the conversion phase, S0 is open, meaning the common terminal T1 is disconnected from ground, and the second terminals of capacitors 312-318 are V IN It is cut off from there. The lower plate of capacitors 312~318 is V REF Connecting either of these to ground may cause charge redistribution between the capacitors. This charge redistribution changes the voltage appearing at the common terminal T1, i.e., the comparator input at the negative terminal of comparator 104.

[0025]

[0033] During the conversion phase, capacitors 312-318 are initially connected to ground in order to execute the binary search algorithm. In this case, -V SH A voltage equal to V appears at the common terminal T1, that is, V T1 =-V SH Therefore, in the first clock cycle for determining the first MSB (i.e., bit 4 in this example), the bottom plate of capacitor 312 (8C), also called the first MSB capacitor, is disconnected from ground, V REF It is connected to the common terminal T1. As a result, the voltage at the common terminal T1 is V T1 =-V SH +V REF / 2. That is, V DAC =V REF It is / 2.

[0026]

[0034] Comparator 104 is V T1 V T2 (i.e., compared to 0v), this is the sampled value V SH threshold V REFCorresponding to comparing with / 2 (see FIG. 2 as an example). The result of this comparison determines the first MSB value. This result also determines whether the first MSB capacitor 312 should be connected to V REF (when bit 4 = 1) or ground (when bit 4 = 0) for the remainder of the conversion phase to determine the remaining bits. V T1 <0 (i.e., V SH > V REF / 2), the comparator 104 outputs a logic 1, i.e., bit 4 = 1. V T1 > 0 (i.e., V SH <V REF / 2), the comparator 104 outputs a logic 0, i.e., bit 4 = 0. When the comparator 104 outputs a logic 1, the bottom plate of the first MSB capacitor 312 remains connected to V REF during the determination of the remaining significant bits. When the comparator 104 outputs a logic 0, the bottom plate of the first MSB capacitor 312 is reconnected to ground during the determination of the remaining significant bits. Considering the example shown with respect to FIG. 2, bit 4 = 0, and thus the second terminal of the capacitor 312 is connected to ground for the remainder of the conversion phase from bit 3 to bit 1.

[0027]

[0035] In the second clock cycle for determining the second MSB, i.e., bit 3, the corresponding capacitor, i.e., capacitor 314, is connected to V REF , which is equivalent to setting V DAC to V REF / 4 in the second clock cycle. This increases the voltage V T1 at the common terminal by V REF / 4, i.e., V T1 = -V SH + 1 / 4 × V REF . The comparator 104 determines the value of bit 3 by comparing V T1 with 0 (or V T2 ). Based on the comparison result, for the remainder of the conversion phase, capacitor 314 is at V REFIt is also determined whether it is connected to the ground. This procedure continues until all bits of the digital value are determined. Considering the example shown with respect to FIG. 2, in the first clock cycle, bit 4 = 0 is first determined, and thus capacitor 312 is connected to the ground for the remainder of the conversion phase. Next, in the second clock cycle, bit 3 = 1 is determined, and capacitor 314 is connected to V REF during the remainder of the conversion phase. In the third clock cycle, bit 2 = 0 is determined, and capacitor 316 is connected to the ground for the remainder of the conversion phase. In the fourth clock cycle, bit 1 = 1 is determined.

[0028]

[0036] Generally, the above-described process for digitizing a sampled analog value may be executed multiple times to obtain a plurality of N-bit digital values of the input analog voltage, and then the plurality of N-bit digital values are processed to obtain the final N-bit digital value of the analog voltage. For example, the average of the plurality of digital values can be used as the final digital value converted for the input analog voltage.

[0029]

[0037] FIG. 4 is a flowchart of an exemplary method 400 for successive approximation register (SAR) type analog-to-digital (A / D) conversion using a SAR type ADC, such as SAR type ADC 100. In this example, the SAR type ADC may be preconfigured to obtain M digital values of the input analog voltage by performing M A / D conversions, where M is a positive integer greater than 1. Each of the M A / D conversions may be referred to as an ADC cycle in the present disclosure. As shown, method 400 can start at block 402, where the SAR type A / D conversion can be started or set to perform an A / D conversion on the input analog voltage. The SAR type ADC can sample the input analog voltage and obtain and hold a sampled value V SH (block 404). The SAR type ADC then SHN-bit A / D conversion can be performed on it to obtain a digital value Dm (N:1) (block 406), where m is an integer and m = 1, 2, ···, M. (N:1) indicates that the digital value Dm has N bits, bit N is the MSB, and bit 1 is the LSB. Next, the SAR ADC stores the obtained digital value Dm (N:1) (block 408) and determines whether M digital values have been generated or M conversions have been completed (block 410). For example, if m < M, that is, if the SAR ADC has not generated M digital values for the input analog value, the SAR ADC proceeds to block 404, performs the next N-bit A / D conversion, resamples the input analog voltage, and performs A / D conversion to generate another digital value. If m = M, the SAR ADC can process the obtained M digital values D1, D2, ···, DM to obtain an N-bit digital output D (N:1) (block 412). D (N:1) is the converted digital value of the analog value output by the SAR ADC.

[0030]

[0038] As mentioned above, an N-bit SAR ADC requires one clock cycle for sampling and N clock cycles to determine the N bits of the digital value in one ADC cycle, i.e., (1+N) clock cycles in one ADC cycle. To generate M digital values ​​from an analog value, an N-bit SAR ADC requires M(1+N) clock cycles. The conversion rate R of an N-bit SAR ADC for converting an analog value to a digital value can be approximately expressed as R = f / (M+M×N), where f is the frequency of the clock signal. Therefore, the conversion rate of an N-bit SAR ADC is low. To improve the conversion rate, to reduce the conversion time (improve the conversion rate), some existing techniques use higher frequencies or combine two types of ADCs, for example, a combination of a flash ADC and a SAR ADC, or a combination of a subrange ADC and a SAR ADC to perform A / D conversion. One drawback is that they cause higher current consumption and require complex algorithms.

[0031]

[0039] Embodiments of this disclosure provide mechanisms / technologies for SAR-type A / D conversion. These mechanisms improve the conversion rate and reduce the current consumption of the SAR-type ADC while maintaining the required resolution. These mechanisms can be applied when multiple SAR-type A / D conversions are performed to acquire digital values / data of analog values / data / voltages. In some embodiments, the mechanism can modify the SAR-type ADC operation flow in later ADC cycles based on measurements of ADC output data acquired in earlier ADC cycles, and control the conversion cycles in the conversion phase of later ADC cycles. Specifically, the mechanism can control and modify the number of comparisons (i.e., the number of clock cycles) required in the conversion phase of later ADC cycles to acquire the converted digital value. Thus, the number of clock cycles in the conversion phase can be reduced, resulting in a shorter conversion time and an improved conversion rate. With these mechanisms, the conversion rate of the SAR-type ADC can be increased by approximately 20-30% compared to conventional SAR-type ADC methods, for example. These mechanisms can provide higher conversion rates (or conversion frequencies) and increased ADC bandwidth. The mechanism may be implemented based on an existing SAR-type ADC architecture, such as the circuit in Figure 1, with the addition of some simple and low-cost circuits / operations, such as a data comparison circuit and an addition operation.

[0032]

[0040] As used herein for illustrative purposes, the N bits of a digital value are represented as bit N, bit (N-1), bit (N-2), ..., bit 2, bit 1 in the order of MSB to LSB. They may also be represented as bit (N-1), bit (N-2), ..., bit 1, bit 0, or in any other applicable way. As used herein for illustrative purposes, bit N may be called the first MSB, bit (N-1) may be called the second MSB, and so on. Bit 1 may be called the first LSB, bit 2 may be called the second LSB, and so on.

[0033]

[0041] In some embodiments, an N-bit SAR ADC can operate in two conversion modes, namely, full mode and partial mode. In full mode, the N-bit SAR ADC operates in the same manner as a conventional SAR ADC to determine each of the N bits of the digital value one by one from the MSB to the LSB, and uses N clock cycles to determine N bits. In partial mode, the N-bit SAR ADC only needs to determine a part of the N bits (for example, K bits from bit K to bit 1), where K < N, and the remaining bits, that is, bits N to bit K+1, are set with values based on previous conversions in previous ADC cycles. The part is a bit sequence including consecutive bits from bit K to bit 1, that is, if the part includes K bits, the part includes bits K, bit K-1, bit K-2, ···, bit 1. The remaining bits are also a series of bits including the bit sequence from bit N to bit K+1. In this partial mode, only K clock cycles are used. The partial mode has fewer clock cycles in the conversion phase than the full mode. K may be referred to as the mode resolution of the partial mode, and K can be preconfigured and made configurable. The N-bit SAR ADC can switch between the two modes based on a determination of whether specific preconfigured conditions are met, as described below.

[0034]

[0042] In some embodiments, the SAR A / D conversion may be performed in full mode to obtain one or more digital values for the input analog value, and based on that, the values of one or more significant bits in the upper positions may be determined and fixed. The SAR A / D conversion in later ADC cycles may be performed in partial mode to only determine the values of the remaining significant bits in the lower positions, thereby reducing the number of conversion cycles required in later ADC cycles.

[0035]

[0043] Figure 5 is a flowchart of an exemplary method 500 for N-bit SAR A / D conversion according to an embodiment of the present disclosure. Method 500 can be performed by using a SAR ADC as described in the embodiments of the present disclosure. In Method 500, M (effective) N-bit digital values ​​D1, D2, ..., DM can be generated for an analog value / voltage by performing M (effective) SAR A / D conversions (also called M conversions) in M ​​ADC cycles. In the generation of each of the M digital values ​​(i.e., in each of the M SAR A / D conversions), the input analog voltage is sampled to obtain a sampled analog value, and the sampled analog value is converted to an N-bit digital value. For each of the M SAR A / D conversions, full mode or partial mode can be selected and used to determine the corresponding output digital value. For convenience of explanation, sample / hold blocks / steps are omitted in the following description and related drawings. Sampling / hold may be performed before the A / D conversion is performed, and a sampled analog value may be obtained each time. For example, sampling / hold may be performed before or after the mode for conversion is selected. As used herein, the terms “digital value” and “digital data” are used interchangeably. M is an integer greater than 1, for example, M could be 8, 10, 15, etc. A valid SAR A / D conversion refers to a SAR A / D conversion that yields an N-bit value that falls within a valid data range. For example, an N-bit digital value containing N “1”s or “0”s is not valid. Method 500 can be performed when M valid SAR A / D conversions are required (M valid digital values ​​are obtained), or when M SAR A / D conversions are required (M or fewer valid digital values ​​are obtained).

[0036]

[0044] Method 500 begins, in block 502, for example, when SAR type A / D conversion is initiated. A conversion mode (full or partial) used for SAR type A / D conversion of an input analog voltage can be selected (block 504). In one embodiment, the full mode may always be selected and executed for the first conversion or the first several conversions performed by the SAR type ADC (or for generating the first digital value or the first several digital values), that is, an N-bit SAR type ADC conversion is performed. In the N conversion cycles (or clock cycles) for the first conversion, all N bits of the digital value are determined one by one. By selecting the full mode for the first conversion (or the first several conversions), a more accurate digital value can be generated as an initial estimate. In another embodiment, the partial mode may be selected and executed for the first conversion or the first several conversions, and only K consecutive LSBs starting from bit 1 (i.e., bit K, bit K - 1, ···, bit 1) are determined. K may be preconfigured. The (N - K) MSBs may be predetermined or may be known in advance. In another example, a low-resolution A / D conversion may be performed for the first conversion or the first several conversions, for example, an S-bit SAR type A / D conversion is performed, where S < N. This may be the case when low resolution is acceptable and a shorter conversion time is more important.

[0037]

[0045] Next, based on the selected full mode, an N-bit SAR A / D conversion can be performed using a SAR ADC (block 506), which generates N-bit digital data D1(N:1) (i.e., Dm(N:1), where m=1) of the sampled analog value of the input analog voltage by determining the N bits one by one as described above for the first conversion. Where used herein, Dm(N:1) may also be called Dm. (N:1) indicates that the digital value D1 has N bits, bit N is the first MSB and bit 1 is the first LSB. S represents the number of bits converted by the SAR ADC, which is also the number of conversion cycles (clock cycles) used to determine the S bits. In this case, S=N. The N-bit digital data D1(N:1) is stored in a register for later processing (block 508).

[0038]

[0046] In some embodiments, a validity check can be performed to determine whether the currently generated digital data is valid (block 510), for example, to check whether the digital data is out of range. For example, the currently generated digital data D1(N:1) can be checked to determine whether it has an overflow (i.e., all 1s) or an underflow (i.e., all 0s). If it is determined that D1(N:1) is invalid, for example, has an overflow or an underflow, D1(N:1) can be invalidated (block 512), and method 500 returns to block 504, where an N-bit SAR type A / D conversion is performed in full mode to regenerate D1(N:1). This may be called "regeneration after invalidation". When the digital data is invalidated, a signal (e.g., a control signal or mode signal) may be generated indicating whether full mode or partial mode may be used for regeneration after invalidation. In some embodiments, a rule can be configured to specify which mode is used for regeneration after invalidation. As an example, the rule may specify that the same mode may be used for regeneration after invalidation. As another example, a rule may specify that if partial mode has been used previously, full mode may be used for regeneration after invalidation. Various rules and combinations can be constructed. Invalidating digital data may include deleting the digital data in a register.

[0039]

[0047] When it is determined that the currently generated digital data is valid, method 500 can determine whether M conversions have been completed or whether M digital values have been generated (block 514). The M conversions herein can refer to M valid conversions for which M valid digital values are generated for the input analog voltage. If there are no invalid digital values generated, the number of conversions performed is equal to the number of digital values generated. Otherwise, if there are invalid digital values generated, the number of conversions performed is greater than the number of digital values generated in order to generate the required number of digital values. In one example, a counter with an initial value of 0 can be used to count the number of valid conversions performed or the number of valid digital values generated. The counter may be incremented by 1 each time a valid digital value Dm(N:1) is generated. When it is incremented such that m equals M, method 500 can end (block 532).

[0040]

[0048] If m < M, that is, if M valid digital values have not been obtained, method 500 can determine whether the digital value previously generated for the input analog voltage, that is, Dm-1(N:1), is available (block 516). If the currently generated digital value is D1(m = 1), that is, if there is no available previously generated digital value, method 500 proceeds to block 504 and performs the next N-bit SAR type A / D conversion (the second conversion) in full mode to generate D2(N:1) and can then save it to a register. The second digital data D2 may also be generated in partial mode using a preset resolution less than N.

[0041]

[0049] If previously generated digital values ​​are available, method 500 can compare the currently generated digital value Dm(N:1) with the previously generated digital value Dm-1(N:1) (block 518). Based on the comparison result, method 500 determines whether Dm has one or more consecutive valid bits, starting from the first MSB, whose corresponding values ​​are the same as those of Dm-1 (block 520). That is, method 500 determines whether there is a bit sequence of Dm starting from the first MSB that has the same values ​​as the bit sequence of Dm-1.

[0042]

[0050] In some embodiments, the bit values ​​of Dm and Dm-1 can be compared starting from bit N. For example, the values ​​corresponding to the first MSB (i.e., bit N) of Dm and Dm-1 can be compared, and if the values ​​are the same, the values ​​corresponding to the second MSB (i.e., bit N-1) of Dm and Dm-1 can be compared. If the values ​​corresponding to the second MSB (i.e., bit N-1) of Dm and Dm-1 are the same, then the values ​​corresponding to the third MSB (i.e., bit N-2) of Dm and Dm-1 can be compared. The comparison continues and can be stopped when it is found that the corresponding values ​​of the bit positions (e.g., bit (NL)) of Dm and Dm-1 are different. That is, the values ​​corresponding to bits (N-L+1) from bit N to bit (N-L+1) of Dm and Dm-1 are the same. In other words, the values ​​of the first L MSBs of Dm and the values ​​of the first L MSBs of Dm-1 are the same, where L is an integer and 1 ≤ L ≤ N. The comparison finds a number L. In the following, the case where "the value of bit q of Dm is the same as the value of bit q of Dm-1" may also be referred to as "bit q of Dm and bit q of Dm-1 are the same" or "Dm and Dm-1 have the same bit q".

[0043]

[0051] Table 1 below shows an example of a digital value Dm (m=1, 2, ...M) generated for an input analog voltage, where M=5 and N=12. Table 1 is used below to illustrate Method 500 of an embodiment as an example. Table 1 also shows the value of L for the generated digital value Dm. As an example, comparing D1 and D2 in Table 1, the first five MSBs (L=5) of D1 and D2, i.e., bits 12 through 8, are the same 10110. [Table 1]

[0044]

[0052] If bit N of Dm and bit N of Dm-1 are not the same, method 500 proceeds to block 504, selects full mode, and performs an N-bit SAR type A / D conversion to generate the next digital value, e.g., D3(N:1). If no identical bits are found in Dm and Dm-1, full mode may be selected in the next ADC cycle to obtain an accurate conversion for subsequent comparisons.

[0045]

[0053] If Dm and Dm-1 (e.g., D1 and D2) have the same first L MSBs (i.e., bits N to (N-L+1)), then method 500 proceeds to determine whether L is greater than a threshold W (block 522). In some embodiments, the bandwidth of the SAR-type ADC may be set to about four times the bandwidth of the input analog signal. Thus, the maximum signal drift (error) is about 1 / 4 of the full scale, and W may be set to N / 4. W may be configured based on other considerations and applications.

[0046]

[0054] If L < W, method 500 returns to block 504 and generates the next digital value in full mode. In this case, one consideration is that since the same MSB is less than the threshold number W, full mode is reused to generate a more accurate conversion. If L ≥ W, method 500 can recommend partial mode for the next conversion (in the next ADC cycle) (block 524). The mode resolution K of the partial mode can be set (block 526), where K < N. The mode resolution K, that is, the number of bits to be determined by the SAR type A / D conversion (that is, the K least significant bits starting from bit 1), can be preconfigured and configurable. In some embodiments, K may be set based on a predefined rule. For example, K may depend on any combination of two of N, W, and L detected in the current ADC cycle. As an example, K = N - L + 1. As another example, K = N - (L - W) + 2. As yet another example, K may be a preconfigured constant. As yet another example, if bit Q is the first bit found to have a value of 0 from bit (N - L + 1) to bit N, K may be set to Q, that is, K = Q.

[0047]

[0055] Using the example shown in Table 1, D1 and D2 have the same first 5 MSBs (from bit 12 to bit 8), that is, 10110, L = 5, and W = N / 4 = 3. Therefore, since L > W, method 500 can recommend using partial mode to perform the next conversion (the third conversion) to generate digital value D3. In one example, K may be set to K = N - L + 1 = 8. Therefore, in the third conversion, only the K least significant bits of D3 (that is, from bit 8 to bit 1) can perform partial mode determined using the SAR type ADC. Bits 12 to bit 9 of D3 may be set to the same values as the bits of D2.

[0048]

[0056] Method 500 can determine whether partial mode is permitted for the next conversion (block 528). This step may be optional. This can be determined based on configuration or conditions. The configuration may be set based on needs or applications (block 530). The configuration may be pre-configured and configurable. In one embodiment, the configuration may permit partial mode for the next conversion after partial mode has been recommended. In another embodiment, the configuration may permit partial mode for the next conversion after partial mode has been recommended a predetermined number of times. In yet another embodiment, the configuration may permit partial mode for the next conversion after partial mode has been recommended and a predetermined number of valid digital values ​​have been generated. In yet another embodiment, the configuration may permit partial mode for the next conversion after partial mode has been recommended and a predetermined number of full mode conversions have been performed. Other applicable conditions / rules may be used to set the configuration for specifying whether partial mode is permitted for the next conversion. In some embodiments, one or more rules may be combined to set the configuration, as described above, for example. Those skilled in the art will recognize various embodiments, alternatives, and modifications for setting the configuration.

[0049]

[0057] If it is determined that partial mode is not permitted for the next conversion, method 500 returns to block 504, where full mode is selected to generate the next digital value D3.

[0050]

[0058] When it is determined that partial mode is permitted for the next conversion, method 500 switches to partial mode (block 504) and performs SAR A / D conversion in partial mode (block 532). Using Table 1 above as an example, in partial mode, K=8, and the SAR ADC determines only the last 8 bits of D3 (bits 8 through 1), and bits 12 through 9 of D3 are assigned the same values ​​1011 as the respective values ​​of bits 12 through 9 of D2. That is, an N-bit SAR ADC performs A / D conversion for only K LSBs, and (NK) MSBs are set to the same values ​​as the values ​​of D2, and this conversion may be called a K-bit partial SAR A / D conversion or a K-bit partial conversion. In an exemplary embodiment (referring again to Figure 2), for 1011, the corresponding capacitors for bits 12, 10, and 9 are connected to the reference voltage / bus, and the corresponding capacitor for bit 11 is connected to ground. Next, the SAR ADC performs an 8-bit SAR A / D conversion to determine the remaining 8 bits (bits 8 through 1) one by one, starting with bit 8. Thus, in the third conversion, the SAR ADC requires only 8 clock cycles to determine the 8 bits. The resulting N-bit digital value produced in partial mode is Dm(N:1) = Dm-1(N:K+1) + Dm(K:1). That is, in the case of Dm(N:1), bits N through (K+1) have the same values ​​as those bits in Dm-1(N:1), and bits K through 1 have the values ​​determined by the SAR ADC during the current conversion. In the example in Table 1, D3(12:1) = D2(12:9) + D3(8:1). D3 can then be stored in a register (block 508). Next, method 500 proceeds to block 510, where it checks whether the generated digital value D3 is valid, and method 500 proceeds in the same manner as described above.

[0051]

[0059] As shown in the example in Table 1, the first six MSBs of D3 (bits 12 through 7) are the same as those of D2 (i.e., L=6), so partial mode is recommended for the fourth transformation. If partial mode is permitted, D4 can be generated in partial mode by performing a K-bit partial transformation, so D4 = D3(N:K+1) + D4(K:1). In this case, K=N-L+1=7, and D4(12:1)=D3(12:8) + D4(7:1). That is, only 7 clock cycles are used to obtain D4 during the fourth transformation, instead of 12 clock cycles.

[0052]

[0060] Similarly, as shown in Table 1, the first eight MSBs of D4 are the same as those of D3 (i.e., L=8), and partial mode is recommended for the fifth conversion. If partial mode is permitted, D5 can be generated in partial mode by performing a K-bit partial conversion, so D5(12:1)=D4(N:K+1)+D5(K:1). If K=N-L+1=5, then D4=D3(12:6)+D4(5:1). That is, only five clock cycles are needed / used to obtain D5 during the fifth conversion. If only five valid digital values ​​(D1~D5) are required for the input analog voltage, then method 500 ends here. The register can output five digital values ​​D1~D5 that can be processed to generate a digital output corresponding to the sampled analog value.

[0053]

[0061] In the above embodiment, method 500 uses five ADC cycles to generate five digital values ​​D1 to D5, and the total number of clock cycles used is 12 + 12 + 8 + 7 + 5 = 44, while using the prior art the total number of clock cycles required is 12 * 5 = 60. By utilizing the previously generated digital values ​​for the analog voltage, the embodiment obtains an estimated range for the analog value and performs a SAR-type A / D conversion within this range in the next conversion. Thus, the embodiment reduces the number of bits determined in some ADC cycles, and therefore reduces the required conversion time and increases the conversion rate. The embodiment would be more beneficial when there is a large number of conversions (ADC cycles) performed and / or when the SAR-type ADC resolution (N) is large.

[0054]

[0062] In some embodiments, the value of W can be determined by testing different values ​​of W using a set of analog voltage / sampling values. As an example, the method 500 of the embodiment can be used to convert a set of analog values ​​to digital values ​​using different values ​​of W. The value of W can be selected based on the resulting conversion time corresponding to different values ​​of W, and optionally, other factors such as a conversion time limit. For example, a value of W corresponding to the minimum conversion time used may be selected. Other rules can also be applied to select the value of W, such as a rule that takes into account the trade-off between conversion time and conversion accuracy.

[0055]

[0063] In some embodiments, method 500 may, in block 518, compare Dm to the average Davg of several previously generated digital values, rather than simply Dm-1. For example, Davg = average{Dm-1, Dm-2, ..., D(mJ)}, where J is an integer, where 1 ≤ J ≤ m-1. Davg may be initialized as void. When Dm is D1 (m=1), Davg is unavailable, and method 500 returns to block 504 to generate D2 in full mode.

[0056]

[0064] In some embodiments, when partial mode is selected (for example, in block 504), a calibration function block / circuit may be provided to avoid generating overflow digital values ​​(performing an overflow check). One clock cycle may be required to perform calibration using the calibration function block, which may result in a decrease in the conversion rate for, for example, one clock cycle. As an example, the calibration function block may include a comparator configured to compare the generated digital value with an overflow reference voltage. If the generated digital value is greater than the overflow reference voltage, the SAR ADC can switch from partial mode to full mode to avoid data loss. If the generated digital value is less than or equal to the overflow reference voltage, the SAR ADC can continue to operate in partial mode.

[0057]

[0065] The overflow reference voltage Dr(N:1) for the current conversion in partial mode may be set based on a digital value Dm(N:1) previously generated by the SAR type ADC. In one example, if bit P is the second bit of Dm from bit L to bit N, which turns out to have a value of 0, then Dr(N:1) can be set to Dm(N:1) but bit P is equal to 1. In another example, Dr(N:1) may be configured such that the value of bit P is 1 from bit N to bit N of Dr, and the value of bit 1 is 0 from bit (P-1) of Dr.

[0058]

[0066] In some embodiments, steps 510 to 528 can be performed by the use of a controller, which may be implemented by hardware, software, or a combination thereof. For example, the controller may be a microcontroller unit (MCU) configured to run software / firmware. As an example, when Dm is generated during the current conversion, Dm can be sent to the MCU, which checks the validity of Dm and determines whether partial mode is recommended and permitted. The MCU can generate an output, e.g., an instruction / command signal or control signal / bit, which instructs the SAR ADC to operate in full mode or partial mode for the next conversion, or to regenerate a digital value for the input analog voltage. The SAR ADC can then select the instructed mode and operate according to the selected mode to generate a digital value.

[0059]

[0067] In some embodiments, partial mode can be disabled or enabled based on various applications or A / D conversion requirements. Enabling partial mode can increase the bandwidth of the SAR ADC. Disabling partial mode can reduce high-frequency noise. In one example, partial mode can be disabled if longer conversion times are not a concern. In this case, steps 516 to 532 may not be performed, and method 400 may be used. In another example, if the application requires a limited conversion time, partial mode can be enabled to meet the requirements. The SAR ADC can switch operation between full mode and full + partial mode depending on the input analog signal. In some embodiments, when the SAR ADC is operating, for example, when only low-resolution conversion is required, the number of conversion bits may be fixed, and only a few measurements of the DC voltage may be required to facilitate processing.

[0060]

[0068] In some embodiments, the data validity check function (block 510) of method 500 can be enabled or disabled, for example, by the use of control bits / signals. As an example, a control bit indicating whether the data validity check function is enabled can be set between the sampling phase and the conversion phase.

[0061]

[0069] Figure 6 is a flowchart of another exemplary method 600 for N-bit SAR-type A / D conversion according to embodiments of the present disclosure. Method 600 can be performed by using a SAR-type ADC as described in embodiments of the present disclosure. Method 600 may include the step (block 602) of using a SAR-type ADC to generate N bits of first digital data and N bits of second digital data for analog data. Method 600 may further include the step (partial mode) of using a SAR-type ADC to generate N bits of third digital data for analog data, once it is determined that the second digital data and the first digital data contain a first most significant bit (MSB) sequence having the same value. In partial mode, the SAR-type ADC is configured to skip determining the second MSB sequence for the third digital data (block 604).

[0062]

[0070] Figure 7 is a flowchart of another exemplary method 700 for N-bit SAR A / D conversion according to embodiments of the present disclosure. Method 700 can be performed by using a SAR ADC as described in embodiments of the present disclosure. Method 700 may include the step of using a SAR ADC to generate first digital data and second digital data for analog data, each having N bits (block 702). Method 700 may further include the step of determining whether the second digital data includes a first bit sequence having the same values ​​as a first bit sequence of the first digital data (block 704). If the second digital data includes a first bit sequence having the same values ​​as a first bit sequence of the first digital data, Method 700 may further include the step of determining whether to generate N-bit third digital data for the analog data using a SAR ADC in partial mode, based on whether the condition is met (block 706). Method 700 may further include a step (block 708) of generating a third digital data in partial mode, provided that the conditions are met. For example, the step of generating a third digital data in partial mode may include setting a second bit sequence of the third digital data with the respective values ​​of the second bit sequence of the second digital data, and determining the values ​​of the remaining bits of the third digital data using a SAR-type ADC. The first and second bit sequences each begin with the first MSB. The second bit sequence contains less than N bits.

[0063]

[0071] It should be noted that various steps of the methods of the embodiments of this disclosure may be modified in different embodiments (e.g., swapped, deleted, rearranged, enhanced, configured, etc.) without altering the exemplary embodiments presented herein. In different embodiments, some of the steps may be skipped or combined, performed in parallel, or performed in an order different from that shown in the figures. As an example, steps 524 and 528 of method 500 may be combined or skipped. As another example, step 530 of method 500 may be removed, and the configuration may be pre-set for the SAR-type ADC before its operation. As yet another example, the order of steps 508 and 510 of method 500 may be swapped.

[0064]

[0072] Figure 8 is a block diagram of an exemplary circuit 800 of a SAR-type ADC according to an embodiment of the present disclosure. The SAR-type ADC has an input analog value / data / voltage V IN Multiple N-bit digital values / data D m It is configured to generate and implement the method of the above-described embodiment. The input analog voltage is sampled and held to produce an N-bit digital value D m It is converted to this. For the sake of explanation, sampling and hold operations will be omitted below. The SAR-type ADC800 includes a comparator 802, a SAR block / module 804, a DAC 806, a binary-to-thermometer code converter (BTCC) 808, and an ADC controller (ADC_C) 810.

[0065]

[0073] Comparator 802 is V REF The first input terminal (negative terminal) is connected to the constant voltage VCM set to / 2, and the voltage V output by the DAC806 is connected to the first input terminal (negative terminal). DAC It has a second input terminal (positive terminal) connected to the SAR block 804. The output terminal of comparator 802 is connected to the SAR block 804. Comparator 802 converts VCM to V DAC The comparison result V can be logically either 1 or 0. C Output: For example, VCM>V DAC In the case of V C= 1, otherwise VCM ≤ V DAC , V C = 0. Next, V C This is passed to SAR block 804. Comparator 802 operates similarly to comparator 104 described with respect to Figure 1.

[0066]

[0074] SAR block 804 is connected to comparator 802, BTCC 808, and ADC_C block 810. SAR block 804 is similar to SAR block 108 described with respect to Figure 1. SAR block 804 is connected to comparison result V C The SAR block 804 is configured to determine the current bit of the digital value Dm based on the logic and register / store the determined bit. For example, if the comparison result is logic high, the current bit is determined to be 1, and if the comparison result is logic low, the current bit is determined to be 0. The SAR block 804 is configured to output the digital value Dm generated in the current ADC cycle for the input analog voltage to the ADC_C810. The SAR block 804 can be configured to operate in partial mode or full mode.

[0067]

[0075] SAR block 804 also contains the analog voltage V generated by DAC806. DAC It is configured to control the value of V. In exemplary operation, after the SAR block 804 has determined the current bit of the digital value Dm, the SAR block 804 may output an intermediate N-bit digital value DI to the BTCC808, where DI contains the values ​​of the bits of the digital value Dm that have been determined so far in the current ADC cycle. The other undetermined bits have a value of 0. The N-bit digital value DI is V IN This can be called the currently determined digital value. DI determines the value of the next bit of the digital value Dm, using the V of the next clock cycle. DAC This is provided to the DAC806 to determine.

[0068]

[0076] The BTCC808 is configured to receive an N-bit digital value DI and perform a binary-to-thermometer code conversion to obtain a thermometer code DT, which is a P-bit code, where P is generally an integer greater than N. The BTCC808 increments the number of bits of the currently determined digital value, V DAC The accuracy of determining the bit value can be improved. In some embodiments, when the SAR block 804 is operating in partial mode, the DI can contain only the bit values ​​of those bits determined by the SAR block 804, and one or more MSBs can be assigned bit values ​​determined in a previous ADC cycle. In this case, the BTCC 808 can obtain the bit values ​​for one or more MSBs from the ADC_C block 810. Using Table 1 as an example, the SAR block 804 is operating in partial mode to determine K=8 bits (bits 8 through 1) of D3, and the bit currently determined is bit 8=0, and therefore DI=[0000 0000 0000]. The BTCC can obtain D2 ([1011 0011 1011]) from the ADC_C 810 and set the DI to [1011 0000 0000], where bits 12 through 9 of the DI have the values ​​of those bits in D2. Next, the BTCC808 can convert DI to P-bit thermometer code DT.

[0069]

[0077] The DAC806 receives the P bit code DT output to the BTCC808 and receives DT and V IN Based on the voltage V DAC It is configured to determine the bit of the digital value Dm. Table 2 below shows the V over i clock cycles for determining the bit of the digital value Dm. DAC The following are illustrative values ​​where i is an integer within the range [1, N]. In this example, to determine bit 1 from bit N, each clock cycle from clock cycle 1 to clock cycle i is used to determine one bit out of N bits. N , B N-1 , B N-2 , , , B N-(i-1)This represents the determined bit values ​​of bits N, N-1, N-2, ..., N-(i-1). [Table 2]

[0070]

[0078] The ADC_C block 810 is configured to receive and store the digital value Dm (m=1, 2, ..., M) converted by the SAR block 804, determine whether to use full mode or partial mode in the next ADC cycle, and control the SAR block 804 to operate in the corresponding mode. The ADC_C block 810 may be configured to output the final digital value converted by the SAR-type ADC for the input analog voltage.

[0071]

[0079] The ADC_C block 810 can determine whether partial mode can be used in the next ADC cycle by comparing the currently generated Dm with a previously generated Dm-1, as described above with respect to Figure 5. If the bit sequences starting from the first MSB in Dm and Dm-1 have the same value, the ADC_C block 810 can decide to use partial mode to generate the digital value Dm+1 in the next ADC cycle, for example, when the conditions / configuration described above are met. In some embodiments, the mode can be determined by comparing the currently generated Dm with an average Davg of several previously generated digital values. For example, Davg may be the average of previously generated digital values ​​D1, D2, ..., Dm-1. As another example, Davg may be the average of a predetermined number J of the most recently generated digital values ​​Dm-1, Dm-2, ..., Dm-J, where 1 ≤ J ≤ m-1. If J=1, the comparison is made between Dm and Dm-1.

[0072]

[0080] Various methods can be used to control a SAR-type ADC to operate in a determined mode. In one embodiment, the ADC_C block 810 can signal the SAR block to begin determining the bits of the digital value from the first MSB (bit N) in full mode, or from the Kth MSB (bit K) in partial mode.

[0073]

[0081] In another embodiment, control can be performed using clock signals. In each ADC cycle and conversion phase, N clock cycles (N clock signals) are used to determine N bits of the digital output value Dm. In one embodiment, the N clock cycles (clock signals) can be numbered from 1 to N. That is, bit N is generated in clock cycle 1 according to clock signal 1 (first clock signal), bit N-1 is generated in clock cycle 2 according to clock signal 2 (second clock signal), ..., bit 1 is generated in clock cycle N according to clock signal N (nth clock signal). Table 2 above shows an example of numbered clock cycles. In exemplary operation, when SAR block 804 receives clock signal 1 as the initial clock signal to initiate A / D conversion in an ADC cycle, SAR block 804 operates in full mode and begins conversion from the determination of bit N. Then, when SAR block 804 receives clock signal K as the initial clock signal to initiate A / D conversion in an ADC cycle, SAR block 804 operates in partial mode and begins conversion from the determination of bit K. Figure 9 shows an example of using a clock signal to control the operation of a SAR-type ADC in the determined mode. Those skilled in the art will recognize that various embodiments, alternatives, and modifications can be made to implement the control.

[0074]

[0082] Figure 9 is a block diagram of another exemplary circuit 900 of a SAR-type ADC according to an embodiment of the present disclosure. Specifically, Figure 9 shows an exemplary circuit for implementing the SAR block 804 and the ADC_C block 810. For illustrative purposes, the SAR block 804, comparator 802, DAC 806, BTCC 808, and ADC_C block 810 are renumbered in Figure 9.

[0075]

[0083] Circuit 900 includes a SAR block 910, a BTCC 920, a DAC 930, a comparator 940, and an ADC controller 950, which operate similarly to the SAR block 804, BTCC 808, DAC 806, comparator 802, and ADC_C block 810, respectively.

[0076]

[0084] The SAR block 910 includes a data latch 912, a SAR logic block 914, and a register 916. The input analog voltage V IN During the current ADC cycle for converting the sampled value to an N-bit digital value Dm (1 ≤ m ≤ M), the data latch 912 receives a comparison result Vc (logic high or logic low) from the comparator 940 according to the ADC_CLK (clock signal) during the conversion phase in each clock cycle, and passes the comparison result Vc to the SAR logic block 914. Based on the comparison result Vc, the SAR logic block 914 determines the value (0 or 1) of the current bit of the digital value Dm, passes the value of the current bit to the register 916, and the register 916 stores the value corresponding to the current bit. DAC To determine this, register 916 uses the N-bit digital value DI(V IN The currently determined digital value is sent to the BTCC920, which converts the binary code DI into a P-bit thermometer code DT. The thermometer code DT is passed to the DAC930, which then determines the value of the next clock cycle. DAC It generates V. Comparator 940 then processes the newly generated V. DACThe SAR block 910 compares the VCM with the Dm and outputs the comparison result for the next clock cycle. The SAR block 910 then determines the value of the next bit based on the comparison result. This procedure continues until bit 1 of Dm is determined, i.e., until Dm is determined, which is then sent from register 916 to the ADC controller 950 by the SAR block 910.

[0077]

[0085] The ADC controller includes registers 952, 954, 958, and 960, a subtractor 956, and a clock signal generator 962. The digital value Dm generated in the current ADC cycle is sent to register 952 and stored. Register 952 receives and stores all digital values ​​D1~DM generated by the SAR block 910 for the input analog voltage and outputs these digital values. Register 952 also sends Dm to register 954.

[0078]

[0086] Register 954 is configured to calculate and store the average Davg of all (e.g., D1 to Dm-1) or some (e.g., D(mJ) to D(m-1)) digital values ​​generated in the previous ADC cycle. Davg is initialized to void and can be updated whenever the currently generated digital value Dm is received. For example, Davg can be updated by the currently generated digital value Dm, such as Davg = (Davg + Dm) / 2. In one embodiment, if only the first digital value for the input analog voltage is generated, Dm = D1 (m=1), then Davg can be updated as Davg = D1. In this case, the ADC controller 950 can skip the operation using registers 956 and 958 and control the SAR block 910 to perform full mode in the next ADC cycle (i.e., to generate the next digital value D2). For example, the ADC controller 950 can send Davg=void to register 960, and based on Davg, register 960 can control the clock signal generator 962 to generate an initial clock signal indicating that full mode should be used in the next ADC cycle.

[0079]

[0087] Based on Dm and Davg, the ADC controller 950 determines whether to select full mode or partial mode for the next ADC cycle and controls the SAR block 910, BTCC 920, and DAC 930 to operate according to the selected mode in the next ADC cycle.

[0080]

[0088] In some embodiments, next, subtraction can be performed on Dm and Davg in the subtractor 956 (before being updated by the currently generated digital value) to obtain the difference Ddiff (N bits) between Dm and Davg. This is equivalent to comparing Dm and Davg to determine whether there is an MSB sequence (starting from bit N) having the same value for Dm and Davg, and determining the number of bits included in the MSB sequence. In the following description, for convenience of explanation, an MSB sequence (starting from bit N) including L MSBs is referred to as the "same L MSBs".

[0081]

[0089] The subtraction may be performed as Ddiff = Dm - Davg or Ddiff = Davg - Dm, and thus Ddiff may be a negative value. The absolute value of Ddiff may be obtained and used for subsequent processing. In the following, when referring to Ddiff, unless otherwise specified, it refers to the absolute value of Ddiff. The obtained Ddiff may be a value that can be represented as a Q-bit binary number, where Q is an integer and 0 ≤ Q ≤ N. For example, Ddiff is 20 and can be represented using Q = 5 bits. This indicates that the five LSBs starting from bit 1 of Dm and Davg have different values, and as a result, Dm and Davg starting from bit N have the same N - 5 (i.e., L = N - 5) MSBs. When Q = N, this indicates that the consecutive MSBs starting from bit N in Dm and Davg are not the same. Next, Ddiff is passed to and stored in the register 958. In one embodiment, the register 958 can store only the maximum Ddiff (Ddiff-max) of the most recent R ADC cycles, where R is an integer and R < N. As an example, R can be set to N / 4 or N / 6. Ddiff-max can be represented as Ddiff-max = max{Ddiffm, Ddiff(m - 1), ···, Ddiff(m - R + 1)}.

[0082]

[0090] The maximum Ddiff, i.e., Ddiff-max (or the number of bits Q of Ddiff-max) is sent to register 960. Based on this, the ADC controller 950 determines whether to select the full mode or the partial mode and executes the initial setting of the selected mode. In some embodiments, if Q < N - 1, the partial mode may be selected, and if Q ≥ N - 1, the full mode may be selected. In some embodiments, the mode may be selected based on the model resolution K (determined based on Q) as described below. Other rules may also be applicable to determine which mode to select based on Ddiff-max (or Q).

[0083]

[0091] In the generation of the digital value Dm + 1, if the partial mode is selected in the next ADC cycle, the initial setting for the partial mode may be executed. In some embodiments, the initial configuration may include configuring the mode resolution K of the partial mode and configuring the DI for the BTCC920. Specifically, the mode resolution K is determined based on Q. Further, the ADC controller 950 determines the LSB of the digital value Dm + 1 that needs to be determined by the SAR block 910, and as a result, determines the MSB of the digital value Dm + 1 that does not need to be determined by the SAR block 910. The values of these MSBs are obtained based on Davg (before update) received from register 954.

[0084]

[0092] As an example, the control block 950 determines that Dm and Davg have the same L most significant bits (MSBs) based on Ddiff-max(Q), where L = N - Q. The mode resolution K can be set / defined as K = N - L + 1 = Q + 1. Other methods of setting / defining K (e.g., those described above) may also be applicable. Next, the (N - K) MSBs of Dm+1 can be set with the values of bits N to bit (K + 1) of Davg(N:1), and the K least significant bits (LSBs) of Dm+1 will be determined by the SAR block 910. That is, Dm+1(N:1) = Davg(N:K + 1) + Dm+1(K:1), where Dm+1(K:1) is determined by the SAR block 910. In order for the SAR block 910 to start the A / D conversion in the next ADC cycle from the determination of bit K, the DI in the BTCC 920 can be initialized with the values of Davg(N:K + 1) for bits N to bit K + 1, and the bit K of DI is initialized with the value 1. This initialization is represented by D LSB and D MSB in FIG. 9. D MSB (N:K + 1) = Davg(N:K + 1). D LSB has K bits, the bit K is initialized with 1, and the bits K - 1 to bit 1 are initialized with 0. That is, D LSB (K:1) = {1, 0, ···, 0}, with K - 1 "0"s. Then, D LSB and D MSB are supplied to the BTCC 920 as initial data for generating V DAC used by the SAR block 910 to determine bit K of Dm+1.

[0085]

[0093] In some embodiments, K may be determined in the register 960 based on Q. When 1 ≤ K < N, the ADC controller selects the partial mode in the next ADC cycle. D LSB and D MSBIt can be initialized as described above. If K ≥ N, this indicates that Dm and Davg do not have MSB sequences with the same bit values, and the ADC controller selects full mode for the next ADC cycle. In this case, D MSB It can be set as void, and also D MSB It can be set to have N bits, where bit N is initialized to the value 1.

[0086]

[0094] In addition to the initial configuration to be performed, the ADC controller 950 also generates a control signal that tells the SAR block 910 which mode to select for the next ADC cycle. In some embodiments, as shown in Figure 9, the register 960 is used as a control signal to control the clock generator 962 to generate the initial clock signal ADC_CLK to start the next ADC cycle when generating Dm+1, LSB and / or D MSB Bit information, such as K, can be sent to the clock generator 962. Based on the initial clock signal, the SAR block 910 understands whether it is operating in full mode or partial mode, and if partial mode is used, it understands which bit (K) is the initial bit to be determined.

[0087]

[0095] In the example where a clock signal is used to control the operation of the selected mode as described above, register 960 can send a number K to clock generator 962, on which the clock generator 962 generates a clock signal of a number (N-K+1) as the initial clock signal for the next ADC cycle, which indicates that the A / D conversion for Dm+1 for the next ADC cycle will begin with the determination of bit K in partial mode. SAR block 910 determines bit K for Dm+1, and then continues to determine bits K-1, K-2, ..., 1.

[0088]

[0096] When K≧N, i.e., (N-K+1)≦1, the clock generator 962 generates clock signal 1 as the initial clock signal for the next ADC cycle, indicating that the A / D conversion in the next ADC cycle for Dm+1 will begin with the determination of bit N. In other words, the SAR type ADC operates in full mode in the next ADC cycle.

[0089]

[0097] The clock generator 962 can generate a clock signal based on the bit information received from register 960 and the pre-scaled clock signal PCLK from the MCU or chip logic control unit. The clock generator 962 can also send a control signal SH to the DAC 930 instructing it to sample the input analog voltage before the initial clock signal for A / D conversion is sent. DAC This is generated based on the thermometer code DT and the sampled values ​​of the input analog voltage.

[0090]

[0098] It should be noted that the circuits in Figures 8 and 9 are merely examples provided for implementing the methods of embodiments of the present disclosure. One or more components in these circuits may be modified, removed, or enhanced, and new components may be added. For example, the subtractor 956 may be removed and a comparator may be used instead, in which case additional components may be added to determine L and K. As another example, the register 958 may be removed. Other circuits having different structures and components may also be applicable for implementing the methods of embodiments of the present disclosure.

[0091]

[0099] While the description has been detailed, it should be understood that various modifications, substitutions, and alternatives can be made without departing from the intent and scope of this disclosure as defined by the attached claims. Furthermore, the scope of this disclosure is not intended to be limited to the specific embodiments described herein, and those skilled in the art will readily understand from this disclosure that existing or subsequently developed processes, machines, manufactures, compositions, means, methods, or steps may perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Accordingly, the attached claims are intended to include such processes, machines, manufactures, compositions of substances, means, methods, or steps within their scope.

Claims

1. The method involves using a successive approximation register (SAR) type analog-to-digital converter (ADC) to generate N bits of first digital data and N bits of second digital data for analog data, wherein N is an integer greater than 1. When it is determined that the second digital data and the first digital data include a first most significant bit (MSB) sequence having the same value, the SAR ADC is used in partial mode to generate N bits of third digital data for the analog data, wherein the SAR ADC is configured to skip determining the value of the second MSB sequence of the third digital data. A method that includes this.

2. In the aforementioned partial mode, the third digital data of N bits is generated. The value of the second MSB sequence of the third digital data is set to the respective values ​​of the second MSB sequence of the second digital data, The SAR-type ADC is used to determine the value of the remaining bits of the third digital data. The method according to claim 1, including the method described in claim 1.

3. The method according to claim 1 or 2, wherein the second MSB sequence includes fewer bits than the first MSB sequence.

4. If the second digital data and the first digital data include the first MSB sequence having the same value, then, based on whether the condition is met, it is determined whether to generate N bits of the third digital data for the analog data in the partial mode. The method according to any one of claims 1 to 3, further comprising:

5. The method according to claim 4, wherein the condition is satisfied when the number L of the first MSB sequence is greater than the threshold number W, and L and W are integers from 1 to N.

6. The method according to claim 5, wherein the threshold number W is based on N.

7. The method according to any one of claims 4 to 6, wherein the condition is satisfied when a predetermined number of digital data is generated for the analog data.

8. If it is determined that the first digital data, the second digital data, or the third digital data is invalid, the first digital data, the second digital data, or the third digital data is regenerated in full mode using the SAR-type ADC, wherein the full mode includes determining all bits of the N-bit digital data regenerated using the SAR-type ADC. The method according to any one of claims 1 to 7, further comprising:

9. The method according to any one of claims 1 to 8, wherein the first digital data or the second digital data is generated using the SAR type ADC in partial mode or full mode, and the full mode includes determining all bits of the digital data using the SAR type ADC.

10. N, determining the number of the second MSB sequences based on the number of the first MSB sequences, or a combination thereof. The method according to any one of claims 1 to 9, further comprising:

11. If it is determined that the second digital data and the first digital data do not contain the first MSB sequence having the same value, then in full mode, the SAR ADC is used to generate the third digital data of N bits for the analog data, wherein the full mode includes determining all bits of the third digital data using the SAR ADC. The method according to any one of claims 1 to 10, further comprising:

12. The method according to any one of claims 1 to 11, wherein the first digital data is the average of a plurality of digital data converted for the analog data.

13. To generate a clock signal indicating the aforementioned partial mode. The method according to any one of claims 1 to 12, further comprising:

14. The method involves generating first digital data and second digital data for analog data using a successive approximation register (SAR) type analog-to-digital converter (ADC), wherein each of the first digital data and the second digital data has N bits. Determining whether the second digital data includes the first bit sequence having the same value as the first bit sequence of the first digital data, wherein the first bit sequence begins with the first most significant bit (MSB), If the second digital data includes the first bit sequence having the same values ​​as the first bit sequence of the first digital data, then, based on whether the conditions are met, it is determined whether to generate N bits of third digital data for the analog data using the SAR type ADC in partial mode, If the above conditions are met, the third digital data is generated in the partial mode, Setting the value of the second bit sequence of the third digital data to the respective values ​​of the second bit sequence of the second digital data, wherein the second bit sequence starts from the first MSB and includes less than N bits, and The value of the remaining bits of the third digital data is determined using the aforementioned SAR-type ADC. including and A method that includes this.

15. The method according to claim 14, wherein the second bit sequence includes fewer bits than the first bit sequence.

16. The method according to claim 14 or 15, wherein the condition is met when the number L of the first bit sequence is greater than the threshold number, and L and the threshold number are integers from 1 to N.

17. The method according to any one of claims 14 to 16, wherein the condition is satisfied when a predetermined number of digital data is generated for the analog data.

18. To determine whether the third digital data is valid digital data, If the third digital data is invalid, the system switches from partial mode to full mode and regenerates the N bits of the third digital data in full mode, wherein the full mode includes determining all bits of the third digital data using the SAR type ADC. The method according to any one of claims 14 to 17, further comprising:

19. The method according to any one of claims 14 to 18, wherein the first digital data or the second digital data is generated using the SAR type ADC in partial mode or full mode, and the full mode includes determining all bits of the digital data using the SAR type ADC.

20. If the second digital data does not include the first bit sequence having the same value as the first bit sequence of the first digital data, the full mode involves using the SAR ADC to generate N bits of the third digital data for the analog data, wherein the full mode includes using the SAR ADC to determine all bits of the third digital data. The method according to any one of claims 14 to 19, further comprising:

21. The method according to claims 16 to 20, wherein the threshold number is based on N.

22. The method according to any one of claims 14 to 21, wherein the first digital data is the average of a plurality of digital data converted for the analog data.

23. N, the number of the first bit sequences, or a combination thereof, determines the number of the second bit sequences. The method according to any one of claims 14 to 22, further comprising:

24. To generate a clock signal indicating the aforementioned partial mode. The method according to any one of claims 14 to 23, further comprising:

Images