Moving average cash hit rate

Abstract

The disclosed device includes a first register for storing a cumulative delta value and a second register for storing an average cache hit rate. The device also includes a control circuit that calculates the cache hit rate and updates the cumulative delta value based on the cache hit rate and the average cache hit rate. Furthermore, the control circuit can update the average cache hit rate based on the updated cumulative delta value and update the cache allocation policy based on the updated average cache hit rate. Various other methods, systems, and computer-readable media are also disclosed.

Description

Background Art

[0001] Managing a cache includes managing a cache allocation policy (e.g., reserving a portion of the cache) to improve performance. Cache thrashing (e.g., consecutive cache misses that require reads from memory) degrades performance and is a factor in determining the cache allocation policy. Detecting cache thrashing includes tracking a running average cache hit rate, which further includes tracking a history of the cache hit rate. However, tracking this history of the cache hit rate may require sufficient processor storage, which can be expensive.

[0002] The accompanying drawings, which are a part of this specification, illustrate several exemplary embodiments. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.

Brief Description of the Drawings

[0003] [Figure 1] It is a block diagram of an exemplary system for a running average cache hit rate. [Figure 2] It is a diagram of a running average cache hit rate without a cache hit rate history. [Figure 3] It is a flowchart of an exemplary method for a running average cache hit rate. [Figure 4] It is a flowchart of another exemplary method for a running average cache hit rate.

Modes for Carrying Out the Invention

[0004] Throughout the drawings, the same reference numerals and designations indicate elements that are similar but not necessarily identical. The exemplary embodiments described herein are open to various modifications and alternative forms, but specific embodiments are shown in the drawings as examples and are described in detail herein. However, the exemplary embodiments described herein are not intended to limit to any particular form disclosed. Rather, this disclosure covers all modifications, equivalents and alternative forms that fall within the appended claims.

[0005] This disclosure generally covers moving average cache hit rates that can be implemented without the need to track the history of cache hit rates. As described in more detail below, embodiments of this disclosure track the cumulative delta value and average cache hit rate from the current cache hit and update the average cache hit rate based on the delta. The cache allocation policy may be updated from the updated average cache hit rate.

[0006] In one embodiment, a device for maintaining a moving average cache hit rate includes a first register configured to store a cumulative delta value, a second register configured to store an average cache hit rate, and a control circuit. The control circuit may be configured to (i) calculate the cache hit rate, (ii) update the cumulative delta value based on the cache hit rate and the average cache hit rate, (iii) update the average cache hit rate based on the updated cumulative delta value, and (iv) update the cache allocation policy based on the updated average cache hit rate.

[0007] In some examples, the control circuit is configured to update the cumulative delta value by determining the difference between the cache hit rate and the average cache hit rate and adding that difference to the cumulative delta value.

[0008] In some examples, the control circuit is configured to update the average cache hit rate based on the determination that the updated cumulative delta value exceeds the delta range. In some examples, the control circuit is configured to determine that the updated cumulative delta value exceeds the delta range by determining that the updated cumulative delta value exceeds an upper delta threshold. In some examples, the control circuit is configured to update the average cache hit rate by incrementing the average cache hit rate in response to the updated cumulative delta value exceeding an upper delta threshold. In some examples, the control circuit is configured to increment the average cache hit rate using an increment coefficient. In some examples, the increment coefficient is based on the magnitude of the updated cumulative delta value that exceeds the upper delta threshold.

[0009] In some examples, the control circuit is configured to determine if the updated cumulative delta value exceeds the delta range by determining if the updated cumulative delta value falls below a lower delta threshold. In some examples, the control circuit is configured to update the average cache hit rate by decrementing the average cache hit rate in response to the updated cumulative delta value falling below a lower delta threshold. In some examples, the control circuit is configured to decrement the average cache hit rate using a decrement coefficient. In some examples, the decrement coefficient is based on the magnitude of the updated cumulative delta value that falls below the lower delta threshold.

[0010] In some examples, the control circuit is further configured to reset the cumulative delta value in response to an update in the average cache hit rate. In some examples, the control circuit is configured to reset the cumulative delta value using the updated average cache hit rate.

[0011] In one embodiment, a system for maintaining a moving average cache hit rate includes physical memory, at least one physical processor having a cache, a first register configured to store a cumulative delta value, a second register configured to store the average cache hit rate of the cache, and a control circuit. The control circuit may be configured to (i) calculate the cache hit rate of the cache, (ii) update the cumulative delta value in the first register based on the cache hit rate and the average cache hit rate, (iii) determine if the updated cumulative delta value exceeds the delta range, (iv) update the average cache hit rate in the second register in response to the determination that the updated cumulative delta value exceeds the delta range, and (v) update the cache allocation policy of the cache based on the updated average cache hit rate.

[0012] In some examples, the control circuit is configured to update the cumulative delta value by determining the difference between the cache hit rate and the average cache hit rate and adding that difference to the cumulative delta value.

[0013] In some examples, the control circuit is configured to determine if the updated cumulative delta value exceeds the delta range by determining that the updated cumulative delta value exceeds the upper delta threshold. In some examples, the control circuit is configured to update the average cache hit rate by incrementing the average cache hit rate using an increment coefficient based on the magnitude of the updated cumulative delta value that exceeded the upper delta threshold, in response to the updated cumulative delta value exceeding the upper delta threshold.

[0014] In some examples, the control circuit is configured to determine if the updated cumulative delta value exceeds the delta range by determining that the updated cumulative delta value falls below a lower delta threshold. In some examples, the control circuit is configured to update the average cache hit rate by decrementing the average cache hit rate using a decrement coefficient based on the magnitude of the updated cumulative delta value falling below the lower delta threshold, in response to the updated cumulative delta value falling below a lower delta threshold.

[0015] In some examples, the control circuit is further configured to reset the cumulative delta value using the updated average cache hit rate.

[0016] In one embodiment, a method for maintaining a moving average cache hit rate includes: (i) calculating the cache hit rate of a cache; (ii) determining the difference between the cache hit rate of a cache and the average cache hit rate; (iii) updating the cumulative delta value by adding the difference to the cumulative delta value; (iv) determining that the updated cumulative delta value exceeds the delta range; (v) updating the average cache hit rate in response to the determination that the updated cumulative delta value exceeds the delta range; (vi) resetting the cumulative delta value in response to the update of the average cache hit rate; and (vii) updating the cache allocation policy of a cache based on the updated average cache hit rate.

[0017] In some examples, determining that the updated cumulative delta value exceeds the delta range includes determining that the updated cumulative delta value exceeds the upper delta threshold. In some examples, updating the average cache hit rate includes updating the average cache hit rate by incrementing the average cache hit rate using an increment coefficient based on the magnitude of the updated cumulative delta value that exceeds the upper delta threshold, in response to the updated cumulative delta value exceeding the upper delta threshold.

[0018] In some examples, determining that the updated cumulative delta value exceeds the delta range includes determining that the updated cumulative delta value falls below the lower delta threshold. In some examples, updating the average cache hit rate includes updating the average cache hit rate by decrementing the average cache hit rate using a decrement coefficient based on the magnitude of the updated cumulative delta value that falls below the lower delta threshold, in response to the updated cumulative delta value falling below the lower delta threshold.

[0019] In some examples, resetting the cumulative delta value involves resetting the cumulative delta value using the updated average cache hit rate.

[0020] Any feature of the embodiments described herein can be used in combination with one another in accordance with the general principles described herein. These and other embodiments, features and advantages will be better understood by reading the following detailed description in conjunction with the accompanying drawings and claims.

[0021] The management of the moving average cash hit rate will be described in detail below with reference to Figures 1 to 4. A detailed description of an exemplary system is provided in relation to Figure 1. A detailed description of the moving average and delta is provided in relation to Figure 2. A detailed description of the corresponding method is provided in relation to Figures 3 and 4.

[0022] Figure 1 is a block diagram of an exemplary system 100 for moving average cache hit rate. System 100 corresponds to computing devices such as desktop computers, laptop computers, servers, tablet devices, mobile devices, smartphones, wearable devices, augmented reality devices, virtual reality devices, network devices, and / or electronic devices. As shown in Figure 1, system 100 includes one or more memory devices, such as memory 120. Memory 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. Examples of memory 120 include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical disk drive, cache, one or more variations or combinations thereof, and / or any other suitable storage memory.

[0023] As shown in Figure 1, the exemplary system 100 includes one or more physical processors, such as a processor 110. The processor 110 generally represents any type or form of hardware implementation processing unit capable of interpreting and / or executing computer-readable instructions. In some examples, the processor 110 accesses and / or modifies data and / or instructions stored in memory 120. Examples of processor 110 include, but are not limited to, chiplets (for example, smaller, and in some cases more specialized processing units that can work together as a single chip), microprocessors, microcontrollers, Central Processing Units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs) implementing soft-core processors, application-specific integrated circuits (ASICs), system-on-chip (SoCs), digital signal processors (DSPs), neural network engines (NNEs), accelerators, graphics processing units (GPUs), one or more of these, one or more variations or combinations of these, and / or any other suitable physical processors.

[0024] As further shown in Figure 1, the processor 110 includes a control circuit 112, a cache 114, registers 116 and 118. The control circuit 112 corresponds to one or more controllers including circuits and / or instructions for maintaining the average cache hit rate of the cache 114, and in some examples may further correspond to or be coupled with a cache controller for the cache 114 (e.g., for applying a cache allocation policy). The cache 114 corresponds to the processor 110's local storage for processing data without incurring latency for accessing data from memory 120, and in some examples may correspond to multiple caches (e.g., a cache hierarchy). Each of the registers 116 and 118 corresponds to a memory element for storing values ​​within the processor 110, and in some examples may store cumulative delta values ​​and / or average cache hit rates, as described herein.

[0025] In some cases, the cache allocation policy for cache 114 can determine whether or not to allocate to cache 114. If cache 114 contains data required by processor 110 to avoid accessing memory 120, it may be desirable to set the cache allocation policy to allocate rather than evicting cached data (e.g., allocating or reserving a portion of cache 114). If cache 114 does not contain data required by processor 110, such as processor 110 accessing memory 120, it may be desirable to set the cache allocation policy to not allocate in order to allow the data to be cached. The cache hit rate (e.g., the rate or percentage of cache hits, or finding requested data in the cache) can indicate whether cache 114 tends to contain the required data. More specifically, the moving average cache hit rate can indicate the historical performance of cache 114 for determining the desired cache allocation policy.

[0026] The moving average cache hit rate can be calculated by remembering the cache hit rate and averaging the cache hit rate. However, remembering a sufficient number of cache hit rates can be prohibitive, for example, by requiring a large memory structure. The systems and methods described herein provide a moving average cache hit rate that avoids remembering historical cache hit rates.

[0027] FIG. 2 shows a diagram 200 for graphically representing a moving average cache hit rate 230 (which may be stored in register 118) calculated using a cumulative delta value 240 (which may be stored in register 116). The control circuit 112 can calculate a new cache hit rate 232 (e.g., using a counter for counting cache hits over a predetermined number of cycles). The delta 242 corresponds to the difference between the new cache hit rate 232 and the moving average cache hit rate 230. FIG. 2 shows the delta 242 as positive (e.g., the new cache hit rate 232 is greater than the moving average cache hit rate 230), but in other embodiments, the delta 242 can be zero or negative.

[0028] The cumulative delta value 240 is updated with the difference between the new cache hit rate 232 and the moving average cache hit rate 230 (e.g., the delta 242) and can be stored (e.g., in register 116) as the updated cumulative delta value 244.

[0029] The control circuit 112 can determine whether the updated cumulative delta value 244 exceeds the delta range. For example, in Figure 2, the updated cumulative delta value 244 exceeds the upper delta threshold 246. In some examples, the upper delta threshold 246 can correspond to the moving average cache hit rate 230, while in other examples, the upper delta threshold 246 can correspond to other values ​​such as a predetermined value, a value relative to the moving average cache hit rate 230 (e.g., an offset from the moving average cache hit rate 230 and / or a percentage of the moving average cache hit rate 230), or a configurable parameter. Accordingly, the control circuit 112 can update the moving average cache hit rate 230. For example, the moving average cache hit rate 230 can be updated by adding an increment coefficient 236 to the updated average cache hit rate 234, which may be stored in the register 118. The increment coefficient 236 may be a predetermined value (e.g., 1) in some examples, but in others it may be based on the magnitude of the updated cumulative delta value 244 that exceeds the upper delta threshold 246 (e.g., scaled by the coefficient), and all of these may also be configurable parameters.

[0030] Figure 2 shows the updated cumulative delta value 244, which exceeds the upper delta threshold 246; however, in other examples, the updated cumulative delta value 244 may fall below the lower delta threshold. Similar to the upper delta threshold 246, the lower delta threshold may be a predetermined value (e.g., 0), a value relative to the moving average cache hit rate 230, and / or a configurable parameter. The control circuit 112 can update the moving average cache hit rate 230 by decrementing it using a decrement coefficient, which is a predetermined value (e.g., -1), similar to the increment coefficient 236; however, in other examples, it may be based on the magnitude of the updated cumulative delta value 244 falling below the lower delta threshold, all of which may be configurable parameters.

[0031] In some examples, after updating the moving average cache hit rate 230, the control circuit 112 can reset the updated cumulative delta value 244, for example, by setting the cumulative delta value 240 to a new value stored in register 116. For example, the cumulative delta value 240 can be reset to a predetermined value (e.g., 0), a value for the updated moving average cache hit rate 234, or a value for the updated cumulative delta value 244, all of which can be configurable parameters.

[0032] Furthermore, in response to the update of the moving average cache hit rate, the control circuit 112 can appropriately update the cache allocation policy of the cache 114 based on the updated average cache hit rate 234.

[0033] Figure 3 is a flowchart of an exemplary computer execution method 300 for tracking the moving average cache hit rate. The steps shown in Figure 3 can be executed by any suitable circuit and / or computing system, including the system shown in Figure 1. In one example, each of the steps shown in Figure 3 represents an algorithm whose structure includes and / or is represented by multiple sub-steps, examples of which are provided in more detail below.

[0034] As shown in Figure 3, in step 302, one or more of the systems described herein calculate the cache hit rate. For example, the control circuit 112 can calculate a new cache hit rate.

[0035] In step 304, one or more of the systems described herein update the cumulative delta value based on the cache hit rate and the average cache hit rate. For example, the control circuit 112 may update the cumulative delta value stored in register 116 based on the new cache hit rate and the average cache hit rate stored in register 118.

[0036] The systems described herein can perform step 304 in various ways. For example, the control circuit 112 can update the cumulative delta value by determining the difference between the cache hit rate and the average cache hit rate and adding that difference to the cumulative delta value, which can be stored in register 116.

[0037] In step 306, one or more of the systems described herein update the average cache hit rate based on the updated cumulative delta value. For example, the control circuit 112 may update the average cache hit rate stored in register 118 based on the updated cumulative delta value stored in register 116.

[0038] The systems described herein can perform step 306 in various ways. In one example, the control circuit 112 can update the average cache hit rate based on determining that the updated cumulative delta value exceeds a delta range. For example, the control circuit 112 can update the average cache hit rate by determining that the updated cumulative delta value exceeds an upper delta threshold and, accordingly, incrementing the average cache hit rate in proportion to the updated cumulative delta value exceeding the upper delta threshold. In some examples, the control circuit 112 can increment the average cache hit rate using an increment coefficient based on the magnitude of the updated cumulative delta value that exceeds the upper delta threshold.

[0039] In another example, the control circuit 112 can determine that the updated cumulative delta value exceeds the delta range by determining that the updated cumulative delta value falls below the lower delta threshold. The control circuit 112 can update the average cache hit rate by decrementing the average cache hit rate in response to the updated cumulative delta value falling below the lower delta threshold. In some examples, the control circuit 112 can decrement the average cache hit rate using a decrement coefficient based on the magnitude of the updated cumulative delta value that falls below the lower delta threshold.

[0040] In some examples, the control circuit 112 can reset the cumulative delta value in response to an update in the average cache hit rate. In some examples, the control circuit 112 can reset the cumulative delta value using the updated average cache hit rate.

[0041] In step 308, one or more of the systems described herein update the cache allocation policy based on the updated average cache hit rate. For example, the control circuit 112 may update the cache allocation policy of the cache 114 based on the updated average cache hit rate.

[0042] Figure 4 is a flowchart of an exemplary computer execution method 400 for tracking the moving average cache hit rate. The steps shown in Figure 4 can be executed by any suitable circuit and / or computing system, including the system shown in Figure 1. In one example, each of the steps shown in Figure 4 represents an algorithm whose structure includes and / or is represented by multiple sub-steps, examples of which are provided in more detail below.

[0043] As shown in Figure 4, in step 402, one or more of the systems described herein calculate the cache hit rate of the cache. For example, the control circuit 112 can calculate the new cache hit rate of the cache 114.

[0044] In step 404, one or more of the systems described herein determine the difference between the cache hit rate of the cache and the average cache hit rate. For example, the control circuit 112 can determine the difference between the new cache hit rate and the average cache hit rate of the cache 114 stored in register 118.

[0045] In step 406, one or more of the systems described herein update the cumulative delta value by adding the difference to the cumulative delta value. For example, the control circuit 112 can update the cumulative delta value stored in register 116 by adding the difference to the cumulative delta value.

[0046] In step 408, one or more of the systems described herein determine that the updated cumulative delta value exceeds the delta range. For example, the control circuit 112 may determine that the updated cumulative delta value stored in register 116 exceeds the delta range (for example, it exceeds the upper delta threshold or falls below the lower delta threshold).

[0047] The systems described herein can perform step 408 in various ways. For example, determining that the updated cumulative delta value exceeds the delta range includes determining that the updated cumulative delta value exceeds the upper delta threshold (see, for example, Figure 2). In another example, determining that the updated cumulative delta value exceeds the delta range includes determining that the updated cumulative delta value falls below the lower delta threshold.

[0048] In step 410, one or more of the systems described herein update the average cache hit rate in response to determining that the updated cumulative delta value exceeds the delta range. For example, the control circuit 112 may update the average cache hit rate stored in register 116 in response to determining that the updated cumulative delta value stored in register 118 exceeds the delta range.

[0049] The systems described herein can perform step 410 in various ways. In one example, updating the average cache hit rate includes updating the average cache hit rate by incrementing the average cache hit rate using an increment coefficient in accordance with whether the updated cumulative delta value exceeds an upper delta threshold (see, for example, Figure 2). In some examples, the increment coefficient may be based on the magnitude of the updated cumulative delta value that exceeds the upper delta threshold.

[0050] In other examples, updating the average cache hit rate involves updating the average cache hit rate by decrementing the average cache hit rate using a decrement coefficient, depending on whether the updated cumulative delta value falls below a lower delta threshold. In some examples, the decrement coefficient can be based on the magnitude of the updated cumulative delta value that falls below the lower delta threshold.

[0051] In step 412, one or more of the systems described herein reset the cumulative delta value in response to an update of the average cache hit rate. For example, the control circuit 112 may reset the cumulative delta value stored in register 116 in response to an update of the average cache hit rate stored in register 118.

[0052] The systems described herein can perform step 412 in various ways. In one example, resetting the cumulative delta value includes resetting the cumulative delta value using the updated average cache hit rate. In other examples, other values ​​may be used to reset the cumulative delta value.

[0053] In step 414, one or more of the systems described herein update the cache allocation policy of the cache based on the updated average cache hit rate. For example, the control circuit 112 may update the cache allocation policy of the cache 114 based on the updated average cache hit rate stored in register 118.

[0054] The systems described herein can perform step 414 in various ways. For example, the control circuit 112 can compare the updated average cache hit rate with various cache hit rate thresholds corresponding to different cache allocation policies.

[0055] As stated above, the systems and methods provided herein concern techniques for maintaining an average rate in a register without retaining a rate history. This technique includes having a current average and maintaining a run count of delta from the average. For each new rate, delta is adjusted either by addition or subtraction based on the difference between the latest rate and the average. In other words, Delta = Delta + (New_Rate - Average). If the magnitude of delta exceeds the average, the average is adjusted. If delta is positive and exceeds the average, the average can be subtracted from delta and the average can be incremented (for example, by incrementing by delta / average, and delta can be delta%average to deal with cases where the average is small and delta is growing rapidly). If delta is negative, the average is subtracted by 1 and delta is adjusted. In this way, if new rates consistently exceed the average, the average increases, but if new rates consistently fall below the average, the average decreases. Larger and more consistent deviations from the mean can lead to faster adjustments to the mean, while hovering close to the mean can either keep the mean the same or require several iterations to update the mean.

[0056] More specifically, in the case of set sampling, continuous cache thrashing (misses) must be detected, and the cache allocation policy must be automatically switched to not allocating. Moving averages can be tracked by retaining a large amount of hit rate history. Moving averages tend to stabilize when hit rates are consistent and move towards zero when hit rates decline. Moving averages can also cover cache warm-up cycles where allocation is desirable despite the duration of misses. Moving averages can cover warm-up cycles if they slowly decline to zero. Thrashing can accommodate zero hits over long durations, where the average tends to move towards zero and, in that case, remains at zero.

[0057] The moving average cache hit rate technique described herein has the advantage of requiring less area on the chip, lower power consumption, and considering longer histories compared to tracking the history of cache hit rates. Similar performance using a FIFO queue for cache hit rates requires a very deep and wide structure and a considerable number of logic gates to sum the entries. In contrast, the systems and methods described herein may be implemented using two counters (e.g., stored in two registers), which may provide more flexibility and configuration parameters for adjusting settings on a workload-by-workload basis. For example, configuration parameters may allow modulating the average sample / response size, selecting between delta size scaling or monotonic scaling, and adjusting the allocation threshold and / or unallocated threshold.

[0058] The average sample / response size corresponds to the average number of responses based on the number of sets observed in the sample set. On the front end, a tag lookup response hit counter can accumulate a fixed number of responses, the corresponding subsets of which can be used to calculate new cache hit rates.

[0059] The delta scaling threshold corresponds to the scaling factor (e.g., + register / - register) when the delta difference exceeds the threshold, resulting in a response curve that can respond more quickly when the hit rate rapidly decreases or spikes. Monotonic scaling (+1 / -1) can be the default, but this scaling can generally be slow to respond to changes in slope. However, monotonic scaling can be tracked well given a large number of samples. For example, for the mean of 64 responses, if the mean is reset to the full hit rate (64), it would take the accumulation of approximately 64 responses for all misses (0) to gradually decrease to the mean of 0 (e.g., 64*64=4096 miss responses).

[0060] The systems and methods provided herein are advantageous because they do not require a data structure to actively track historical cache hit rate values ​​and further enable tracking of longer histories. For example, using a FIFO to track a similar number of cache hit values ​​as possible with the systems and methods described above may require a deep and wide structure (e.g., for storing each value) and a logic gate for summing the entries. Instead, the systems and methods described herein can be implemented using two counters (e.g., cumulative delta value and average cache hit rate) with greater flexibility in configurable parameters (e.g., modulating the mean sample size, delta size scaling or monotonic scaling, assigned or unassigned threshold, etc.). Advantageously, the systems and methods provided herein can be implemented in a smaller area (e.g., requiring fewer components that consume space within the architecture) and further offer reduced power consumption.

[0061] As described above, the circuits and systems described and / or illustrated herein broadly represent any type or form of computing device or system capable of executing computer-readable instructions. In their most basic configurations, each of these computing devices includes at least one memory device and at least one physical processor.

[0062] In some instances, the term “memory device” generally refers to any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. In one example, a memory device stores, loads, and / or maintains one or more modules and / or circuits described herein. Examples of memory devices include, but are not limited to, random-access memory (RAM), read-only memory (ROM), flash memory, hard disk drives (HDDs), solid-state drives (SSDs), optical disk drives, caches, one or more variations or combinations thereof, or any other suitable storage memory.

[0063] In some cases, the term “physical processor” generally refers to any type or form of hardware implementation processing unit capable of interpreting and / or executing computer-readable instructions. In one example, a physical processor accesses and / or modifies one or more modules stored in the memory devices described above. Examples of physical processors include, but are not limited to, microprocessors, microcontrollers, central processing units (CPUs), field-programmable gate arrays (FPGAs) implementing soft-core processors, application-specific integrated circuits (ASICs), systems-on-a-chip (SoCs), digital signal processors (DSPs), neural network engines (NNEs), accelerators, graphics processing units (GPUs), one or more of these, one or more variations or combinations of these, or any other suitable physical processor.

[0064] In some embodiments, the term “computer-readable medium” generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable mediums include, but are not limited to, transmission media such as carrier waves, as well as magnetic storage media (e.g., hard disk drives, tape drives, floppy disks), optical storage media (e.g., compact disks (CDs), digital video disks (DVDs), Blu-ray discs), electronic storage media (e.g., solid-state drives and flash media), and non-transient media such as other distribution systems.

[0065] The process parameters and steps described and / or illustrated herein are given only as examples and may be changed as desired. For example, the steps illustrated and / or described herein are illustrated or discussed in a particular order, but these steps do not necessarily have to be performed in the illustrated or discussed order. Various exemplary methods described and / or shown herein may omit one or more of the steps described or shown herein, or may include additional steps in addition to those disclosed.

[0066] The above description is provided to enable those skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to limit to any specific form disclosed. Many modifications and variations are possible without departing from the spirit and scope of this disclosure. The embodiments disclosed herein should be considered in all respects to be exemplary and not restrictive. In determining the scope of this disclosure, the appended claims and their equivalents should be referenced.

[0067] Unless otherwise stated, the terms “connected” and “joined” (and their derivatives) as used herein and in the claims should be interpreted to allow both direct and indirect connections (i.e., through other elements or components). In addition, the terms “a” or “an” as used herein and in the claims should be interpreted to mean “at least one of.” Finally, for ease of use, the terms “including” and “having” (and their derivatives) as used herein and in the claims are interchangeable with the term “comprising” and have the same meaning.

Claims

1. It is a device, A first register configured to store the cumulative delta value, A second register configured to store the average cache hit rate, Equipped with a control circuit, The aforementioned control circuit is Calculating the cash hit rate, The cumulative delta value is updated based on the aforementioned cash hit rate and the aforementioned average cash hit rate. Based on the updated cumulative delta value, update the average cash hit rate, The cache allocation policy is updated based on the updated average cache hit rate, It is configured to do, device.

2. The aforementioned control circuit is To determine the difference between the aforementioned cash hit rate and the aforementioned average cash hit rate, The difference is added to the cumulative delta value, The system is configured to update the cumulative delta value accordingly. The device according to claim 1.

3. The control circuit is configured to update the average cache hit rate based on the determination that the updated cumulative delta value exceeds the delta range. The device according to claim 1.

4. The control circuit is configured to determine that the updated cumulative delta value exceeds the delta range when it determines that the updated cumulative delta value exceeds the upper delta threshold. The device according to claim 3.

5. The control circuit is configured to update the average cache hit rate by incrementing the average cache hit rate in accordance with whether the updated cumulative delta value exceeds the upper delta threshold. The device according to claim 4.

6. The control circuit is configured to increment the average cache hit rate using an increment coefficient. The device according to claim 5.

7. The increment coefficient is based on the magnitude of the updated cumulative delta value that exceeds the upper delta threshold. The device according to claim 6.

8. The control circuit is configured to determine that the updated cumulative delta value exceeds the delta range when it determines that the updated cumulative delta value falls below the lower delta threshold. The device according to claim 3.

9. The control circuit is configured to update the average cache hit rate by decrementing the average cache hit rate in accordance with the updated cumulative delta value falling below the lower delta threshold. The device according to claim 8.

10. The control circuit is configured to decrement the average cache hit rate using a decrement coefficient. The device according to claim 9.

11. The decrement coefficient is based on the magnitude of the updated cumulative delta value that falls below the lower delta threshold. The device according to claim 10.

12. The control circuit is configured to reset the cumulative delta value in accordance with the update of the average cache hit rate. The device according to claim 1.

13. The control circuit is configured to reset the cumulative delta value using the updated average cache hit rate. The device according to claim 12.

14. It is a system, Physical memory and At least one physical processor with a cache, A first register configured to store the cumulative delta value, A second register configured to store the average cache hit rate of the aforementioned cache, Equipped with a control circuit, The aforementioned control circuit is Calculate the cache hit rate of the aforementioned cache, In the first register, the cumulative delta value is updated based on the cache hit rate and the average cache hit rate. It is determined that the updated cumulative delta value exceeds the delta range, In response to determining that the updated cumulative delta value exceeds the delta range, the average cache hit rate in the second register is updated. Based on the updated average cache hit rate, update the cache allocation policy for the cache, It is configured to do, system.

15. The control circuit controls the cumulative delta value To determine the difference between the aforementioned cash hit rate and the aforementioned average cash hit rate, The difference is added to the cumulative delta value, The system is configured to update the cumulative delta value accordingly. The device according to claim 14.

16. The control circuit is configured to determine that the updated cumulative delta value exceeds the delta range when it determines that the updated cumulative delta value exceeds the upper delta threshold, The control circuit is configured to update the average cache hit rate by incrementing the average cache hit rate using an increment coefficient based on the magnitude of the updated cumulative delta value that exceeds the upper delta threshold, in response to the updated cumulative delta value exceeding the upper delta threshold. The system according to claim 14.

17. The control circuit is configured to determine that the updated cumulative delta value exceeds the delta range when it determines that the updated cumulative delta value falls below the lower delta threshold. The control circuit is configured to update the average cache hit rate by decrementing the average cache hit rate using a decrement coefficient based on the magnitude of the updated cumulative delta value that falls below the lower delta threshold, in response to the updated cumulative delta value falling below the lower delta threshold. The system according to claim 14.

18. The control circuit is configured to reset the cumulative delta value using the updated average cache hit rate. The system according to claim 14.

19. It is a method, Calculating the cache hit rate of the cache, The difference between the cache hit rate of the aforementioned cache and the average cache hit rate is determined. The cumulative delta value is updated by adding the aforementioned difference to the cumulative delta value, It is determined that the updated cumulative delta value exceeds the delta range, In response to determining that the updated cumulative delta value exceeds the delta range, the average cache hit rate is updated. In accordance with updating the average cash hit rate, the cumulative delta value is reset, This includes updating the cache allocation policy for the cache based on the updated average cache hit rate, method.

20. Determining that the updated cumulative delta value exceeds the delta range includes determining that the updated cumulative delta value exceeds the upper delta threshold, Updating the average cache hit rate includes updating the average cache hit rate by incrementing the average cache hit rate using an increment coefficient based on the magnitude of the updated cumulative delta value that exceeds the upper delta threshold, in accordance with the updated cumulative delta value exceeding the upper delta threshold. Determining that the updated cumulative delta value exceeds the delta range includes determining that the updated cumulative delta value falls below the lower delta threshold, thereby determining that the updated cumulative delta value exceeds the delta range. Updating the average cache hit rate includes updating the average cache hit rate by decrementing the average cache hit rate using a decrement coefficient based on the magnitude of the updated cumulative delta value that falls below the lower delta threshold, in accordance with the updated cumulative delta value falling below the lower delta threshold. Resetting the cumulative delta value includes resetting the cumulative delta value using the updated average cache hit rate. The method according to claim 19.

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