A check data calculation unit supporting both RAID5 and RAID6

Abstract

This application provides a parity data calculation unit that simultaneously supports RAID5 and RAID6. The calculation unit includes an XOR calculator, an XOR cache, and an address interleaving unit. The XOR cache comprises M memory banks with a bit width of J. The address interleaving unit generates M memory bank addresses based on the XOR cache addresses and provides them to the M memory banks. The M memory banks then provide M*J data corresponding to a row of M data blocks. The M*J data originates from one XOR cache unit in RAID5 mode or two XOR cache units in RAID6 mode. The XOR calculator performs an XOR operation on the M*J data and user data to generate intermediate parity data P or a combination of intermediate parity data P and intermediate parity data Q. The XOR calculator determines the final parity data based on K cycles of XOR operations. This application enables a calculation unit that supports RAID5 and RAID6 parity data calculation, saving on hardware circuit modification costs.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a parity data calculation unit that simultaneously supports RAID5 and RAID6. Background Technology

[0002] Figure 1A A block diagram of the storage device is shown. Storage device 102 is coupled to a host computer to provide storage capabilities. The host computer and storage device 102 can be coupled in various ways, including but not limited to using storage protocols such as SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device in the above ways, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 includes interface 103, control unit 104, one or more NVM chips 105, and DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] Interface 103 is compatible with exchanging data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110. It is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control unit 104 can be implemented in various ways, including software, hardware, firmware, or a combination thereof. For example, the control unit 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control unit 104 may also include a processor or controller, in which software executes to manipulate the hardware of the control unit 104 to process I / O (Input / Output) commands. The control unit 104 can also be coupled to the DRAM 110 and can access the data in the DRAM 110. FTL tables and / or cached I / O command data can be stored in the DRAM.

[0006] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] Figure 1B A detailed block diagram of the control components of the storage device is shown.

[0008] The host accesses the storage device using I / O commands that conform to the storage protocol. The control unit generates one or more media interface commands based on the I / O commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, erase commands) that conform to the NVM chip's interface protocol based on the media interface commands. The control unit also tracks the completion of all media interface commands generated from a single I / O command and indicates the processing results of the I / O commands to the host.

[0009] See Figure 1BThe control components include, for example, a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage media management unit. The host interface receives I / O commands from the host and generates storage commands, which are then provided to the storage command processing unit. A storage command may access a storage space of the same size, such as 4KB. The data unit recorded in the NVM chip corresponding to the data accessed by a storage command is called a data frame. A physical page records one or more data frames. For example, if the size of a physical page is 17664 bytes and the size of a data frame is 4KB, then one physical page can store four data frames.

[0010] The storage media management unit (SMMU) maintains a logical address to physical address translation for each storage command. For example, the SMMU includes an FTL table. For a read command, the SMMU outputs the physical address corresponding to the logical address accessed by the storage command; for a write command, the SMMU allocates an available physical address and records the mapping between the accessed logical address and the allocated physical address. The SMMU also maintains functions required for managing the NVM chip, such as garbage collection and wear leveling.

[0011] The storage command processing unit, based on the physical address provided by the storage media management unit, operates the media interface controller to issue storage media access commands to the NVM chip. For clarity, commands sent from the host to the storage device are called I / O commands, commands sent from the host command processing unit to the storage command processing unit are called storage commands, commands sent from the storage command processing unit to the media interface controller are called media interface commands, and commands sent from the media interface controller to the NVM chip are called storage media access commands. Storage media access commands conform to the NVM chip's interface protocol.

[0012] SSDs (Solid State Drives) consist of multiple NVM chips. Each NVM chip includes one or more LUNs (Logical Units), and each logical unit includes multiple physical blocks. As storage capacity increases, so does the number of NVM chips / LUNs / blocks, which also increases the likelihood of storage media failure. To ensure the reliability of the stored data delivered to users, enterprise-grade SSDs use technologies similar to RAID (Redundant Arrays of Independent Disks) to construct data protection units across NVM chips / logical units. This ensures that even if a single NVM chip / logical unit fails, data is not lost. This also addresses the occasional data errors that may occur during SSD operation.

[0013] Large blocks serve as the unit for allocating and reclaiming storage media resources in an SSD. When allocating storage media resources to carry write data, free large blocks are selected. Within the selected large block, data is written sequentially. When reclaiming storage media resources, the entire large block is reclaimed, and after the valid data has been reclaimed, all physical blocks within the large block are erased. Therefore, within an SSD, all physical blocks within a large block typically have the same number of write / erase cycles.

[0014] Page stripes are data protection units within an SSD, constructed using RAID technology. Page stripes are built into large blocks, which consist of multiple page stripes. A large block comprises physical blocks from multiple logical units; these logical units that provide physical blocks to the large block are called a logical unit group. Each logical unit in a logical unit group can provide one physical block for the large block. For example, in... Figure 2A The diagram shows a large block constructed across N+1 logical units. Each large block comprises N+1 physical blocks, each originating from one of the N+1 logical units. The large block stores user data and checksum data. Checksum data is calculated from the user data stored within it. For example, checksum data is stored in the last physical block of the large block. Alternatively, other physical blocks within the large block can be used to store checksum data. Other construction methods can also be employed to construct the large block, such as... Figure 2B The diagram illustrates how to construct large blocks within a multi-plane logic unit.

[0015] See Figure 3A as well as Figure 3B A large block comprises multiple page strips, and each page strip comprises multiple physical pages, which originate from different physical blocks within the same large block. For example, a page strip might have P pages storing user data and Q pages storing validation data. Figure 3A and Figure 3B In this context, Q = 1). The data written to page i is denoted as D(i). The checksum D(Q) is generated from the user data of page P according to the specified error correction algorithm. For example, if the checksum is determined based on the XOR operation, then D(Q) = D(0)XOR D(1)XOR...XOR D(P-1). Therefore, in writing data to the page stripe, D(Q) can only be calculated if D(0) to D(P-1) are known. The typical size of D(i) is, for example, 2KB, 4KB, 16KB, etc.

[0016] In TLC (Triple-Level Cell) flash memory, a one-shot programming mode is typically used, requiring the programming of three physical pages on the same word line in a single ONFI command. This means a single programming command operates on three physical pages. Accordingly, to improve write performance, page stripes are constructed in groups of three physical pages, resulting in a typical D(Q) size of 48KB. In multi-plane TLC flash memory, a multi-plane programming mode can be used to improve write performance. This allows a single programming command to operate on, for example, 12 physical pages (each logical cell includes four planes). Accordingly, the D(Q) size is typically 192KB.

[0017] To use RAID technology, parity data D(Q) needs to be calculated for the data written to the page stripe. Calculating the parity data involves numerous XOR operations. To accelerate this process, a dedicated hardware unit (called the XOR calculation unit) is typically used to perform the calculation of D(Q) = D(0)XOR D(1)XOR...XORD(P-1). The XOR calculation unit also includes an XOR cache to cache the data D(i) and intermediate results of each XOR calculation, such as the result of D(0)XORD(1), the result of D(0)XORD(1)XOR D(2), until the final D(Q) is obtained, which is then written to the page stripe. Therefore, the XOR cache needs to be large enough to hold the entire D(i), and once a page stripe is allocated, the entire XOR cache is needed to support the data writing operations until the page stripe is full.

[0018] To improve SSD performance, data can be written to multiple large page stripes simultaneously. Accordingly, each page stripe written concurrently needs its own dedicated XOR cache. As mentioned earlier, the D(Q) size can reach 192KB (including some out-of-band data), thus requiring a single XOR cache of approximately 200KB. However, on-chip cache resources are very expensive, therefore the number of XOR caches in an XOR computation unit is typically small (e.g., 1-4).

[0019] In typical existing technologies, the XOR calculation unit is located within the media interface controller. The XOR calculation unit is operated to adapt page stripes with different data protection capabilities. The data protection level of a page stripe is determined by the relationship between the parity data and the user data; that is, the values ​​of P and Q represent the data protection capability of the page stripe. Furthermore, the XOR calculation is completed while the media interface controller provides data (e.g., D(0)) to the NVM chip (e.g., physical page P0-0) via programming commands. For example, suppose XOR cache 0 is allocated for page stripe 0 (initialized to all 0s). During the process of moving D(0) to page stripe 0 P0-0, 0XOR D(0) is calculated, and the result is D(0) and stored in XOR cache 0. Next, D(1) is moved to page stripe 0 P0-1, and D(0)XOR D(1) is calculated. D(0) is inside XOR cache 0, and D(1) is obtained during the data movement. Then, XOR cache 0 records the result of D(0)XORD(1). Next, D(2) is moved to page stripe 0 P0-2. The result of D(0)XORD(1) recorded in XOR cache 0 is XORed with the moved D(2), and the result is still stored in XOR cache 0. Following this logic, after moving D(P-1) to P0-(P-1) of page stripe 0, D(Q) is obtained in XOR cache 0, and then D(Q) is moved to P0-P of page stripe 0. At this point, page stripe 0 is full, and XOR cache 0 is released.

[0020] To improve the I / O command processing performance of storage devices, Chinese patent application number "2024113764394" provides a data replication technology for NVMe write channels. For example... Figure 4 As shown, the control unit includes a host command processing unit, a media interface controller, a DMA (Direct Memory Access) unit, and an SRAM (Static Random-Access Memory). The DMA unit includes a data copying unit.

[0021] The host command processing unit is coupled to the DMA unit. The host command processing unit receives I / O commands (such as NVMe write commands or NVMe read commands) sent by the host and operates the DMA unit to move data between the host and the storage device. Optionally, in response to receiving an NVMe write command, the host command processing unit generates a DMA command and provides it to the DMA unit. The DMA unit, based on the received DMA command, moves the data indicated by the NVMe write command from the host memory to the storage device.

[0022] Specifically, the DMA unit is coupled to the host command processing unit. In response to receiving a DMA command, it moves the data indicated by the DMA command from the host memory and provides the data to the data copying unit.

[0023] The data copying unit is coupled to both SRAM and DRAM. The data copying unit copies data from the host, which is moved by the DMA unit, to both SRAM and DRAM. The data copied to SRAM and DRAM is identical to the data from the host. For example, the data copying unit receives data D from the DMA unit and copies data D to both SRAM and DRAM. If the data copied to SRAM is denoted as data D1 and the data copied to DRAM as data D2, then data D1 is identical to data D, and data D2 is also identical to data D.

[0024] The media interface controller is coupled to both SRAM and DRAM. Upon receiving a media interface command, the media interface controller moves the data indicated by the command from the SRAM to the NVM chip and deletes the data from the SRAM, freeing up the storage space occupied by the data. Upon detecting that the data indicated by the media interface command has been successfully written to the NVM chip (e.g., the media interface controller receives a data write success indication from the NVM chip), the media interface controller deletes the data indicated by the command from the DRAM, freeing up the DRAM storage space. Upon detecting that the data write to the NVM chip has failed (e.g., the media interface controller receives a data write failure indication from the NVM chip), the media interface controller moves the data indicated by the command from the DRAM to the NVM chip.

[0025] During host write command processing, SRAM is written to once and read from once, requiring twice the bandwidth of the host-to-control unit bandwidth. DRAM is written to once, and read operations occur only with a low probability (the probability of SRAM failing to move data to the NVM chip), thus requiring roughly the same bandwidth as the host-to-control unit bandwidth. Therefore, conventional SRAM / DRAM can meet this bandwidth requirement. Moving data to DRAM does not consume SRAM output bandwidth or its output port, allowing SRAM to have only a single output port, with its full output performance utilized by the media interface controller. Summary of the Invention

[0026] RAID technology organizes data and generates parity data on page stripes. RAID5 is a commonly used RAID technology in storage devices. In RAID5, each page stripe includes, for example, N copies of user data (denoted as D(i)) and 1 copy of parity data (denoted as P), and P = D(0) XOR D(1)... XOR D(N-1). RAID5 can correct one corrupted copy of data in the page stripe.

[0027] RAID 6 is another commonly used RAID technology with stronger error correction capabilities than RAID 5, capable of correcting two simultaneously corrupted data sets in a page stripe. In RAID 6, each page stripe includes, for example, N-1 user data sets (denoted as D(i)) and two parity data sets (denoted as P and O, respectively). P is calculated in the same way as in RAID 5: P = D(0) XOR D(1) ... XOR D(N-2). Q is calculated as Q = (D(0) * K0) XOR (D(1) * K1) ... XOR (D(N-2) * K(N-2)), where "*" represents Galois multiplication, and Ki is a predetermined constant coefficient.

[0028] Storage devices need to support both RAID 5 and RAID 6 simultaneously, requiring an XOR calculation unit capable of calculating both the parity data P for RAID 5 and the parity data P and Q for RAID 6. Obviously, the media interface controller could provide both XOR calculation units for RAID 5 and RAID 6. However, this would increase the size of the media interface controller's hardware circuitry and lead to increased power consumption and cost. Therefore, this application aims to implement an XOR calculation unit that simultaneously supports parity data calculation for RAID 5 and RAID 6 while sharing most of the hardware circuitry.

[0029] On the other hand, solid-state drives (SSDs) with no (or few) built-in independent DRAM chips offer advantages in terms of cost and power consumption. After calculating the parity data, it needs to be written to the NVM chip immediately. If the NVM chip (or LUN) being written to is processing other commands, it may not be able to immediately receive the parity data to be written. Since the XOR cache is a highly scarce resource, keeping the parity data in the XOR cache while waiting for other commands on the NVM chip to complete will severely impact the performance of the storage device. Therefore, it is desirable to further schedule the process of writing the parity data to the NVM chip after the parity data used for page striping is generated to improve the performance of the storage device.

[0030] When moving parity data from the XOR cache to the NVM chip, a bus connection (e.g., AIX bus) is required. Moving data from the XOR cache to the NVM chip requires specifying a particular size of storage space within the address space occupied by the XOR cache on the bus to describe the data to be moved. However, for RAID 5 and RAID 6 operating modes, the XOR cache cells are located in different and partially overlapping data blocks within the XOR cache. This means that read requests from the bus to the XOR cache cells require specifying different addresses depending on the RAID 5 / RAID 6 mode, making it difficult to read data from the XOR cache cells via the bus.

[0031] The embodiments of this application aim to solve one or more of the above-mentioned technical problems.

[0032] In a first aspect, embodiments of this application provide an XOR calculation unit, including an XOR calculator, an XOR cache, and an address interleaving unit, wherein the XOR cache includes M memory banks with a bit width of J;

[0033] The address interleaving unit generates M memory addresses based on the XOR cache address and provides them to the M memory banks. The M memory banks of the XOR cache provide M*J data corresponding to a row of M data blocks. The M*J data comes from one XOR cache unit in RAID5 mode or from two XOR cache units in RAID6 mode. The size of the data block is equal to the bit width of the memory bank.

[0034] The XOR calculator performs an XOR operation based on the M*J data and user data of the same bit width to generate intermediate state check data and write it back to the XOR cache. The intermediate state check data includes intermediate check data P that matches the RAID5 mode, or the intermediate check data includes intermediate check data P and intermediate check data Q that match the RAID6 mode.

[0035] The XOR calculator determines the verification data P or a set of verification data including verification data P and verification data Q based on the XOR operation of K calculation cycles.

[0036] Where M is an even number greater than 0, a row of M data blocks corresponds to M*J bits of data, each calculation cycle corresponds to an XOR cache address, and the size of a single XOR cache unit is G; in RAID5 mode, the value of K is G / (M*J), and in RAID6 mode, the value of K is 2G / (M*J).

[0037] Optionally, the XOR cache provides M data blocks in different rows at different computation cycles;

[0038] In RAID5 mode, the M data blocks originate from a single XOR cache unit;

[0039] In RAID6 mode, M / 2 data blocks come from the first XOR cache unit, and the remaining M / 2 data blocks come from the second XOR cache unit;

[0040] In the same calculation cycle, the M storage banks provide M*J data corresponding to a row of M data blocks based on the same storage bank address.

[0041] Optionally, the data port of the XOR cache has an M*J bit width. In each computation cycle, the M memory banks simultaneously operate in response to the received memory bank address, providing M*J data to the data port of the XOR cache; or

[0042] The data port of the XOR cache is J bits wide. In each calculation cycle, the M memory banks sequentially provide data blocks to the data port of the XOR cache in a time-division manner in response to the received memory bank address.

[0043] Optionally, in RAID5 mode, the G / J data blocks corresponding to a single XOR cache unit are arranged sequentially in M ​​storage units according to their sequence numbers;

[0044] In RAID6 mode, the G / J data blocks corresponding to each of the two XOR cache units are arranged sequentially in the M / 2 storage blocks they occupy.

[0045] Optionally, in RAID5 mode, the G / J data blocks corresponding to a single XOR cache unit occupy consecutive G / (M*J) rows of data blocks in M ​​storage units according to their sequence numbers;

[0046] In RAID6 mode, the G / J data blocks corresponding to each of the two XOR cache units occupy 2G / (M*J) rows of data blocks in the M / 2 storage units they occupy.

[0047] Optionally, the two XOR cache units in RAID6 mode are cache units used to store the parity data P and parity data Q corresponding to RAID6 mode.

[0048] Optionally, in RAID5 mode, each XOR cache unit occupies M storage units, and multiple XOR cache units occupy multiple consecutive G / (M*J) rows of data blocks in the M storage units. The last row of data blocks occupied by the preceding XOR cache unit and the first row of data blocks occupied by the following XOR cache unit are adjacent in each storage unit.

[0049] In RAID6 mode, each XOR cache unit occupies M / 2 storage units. A pair of XOR cache units used to store a set of parity data each occupy consecutive 2G / (M*J) rows of data blocks located in the same row. Multiple XOR cache units storing parity data P occupy multiple consecutive 2G / (M*J) rows of data blocks in M / 2 storage units. Multiple XOR cache units storing parity data Q occupy multiple consecutive 2G / (M*J) rows of data blocks in the remaining M / 2 storage units. The last row of data blocks occupied by the preceding XOR cache unit of adjacent parity data P and the first row of data blocks occupied by the following XOR cache unit are adjacent in each storage unit. Similarly, the last row of data blocks occupied by the preceding XOR cache unit of adjacent parity data Q and the first row of data blocks occupied by the following XOR cache unit are adjacent in each storage unit.

[0050] Optionally, the XOR calculator includes a first XOR unit, a second XOR unit, a first register, and a second register, all with a bit width of M*J / 2.

[0051] The first XOR unit is connected to the first register, which stores data provided by a row of M / 2 data blocks. The first XOR unit performs an XOR operation based on the M*J / 2 bit wide user data and the M*J / 2 bit wide data provided by the first register.

[0052] The second XOR unit is connected to the second register, which stores data provided from a row of remaining M / 2 data blocks. The second XOR unit performs an XOR operation based on the target data with a width of M*J / 2 bits and the data with a width of M*J / 2 bits provided by the second register. The target data is the product of the user data with a width of M*J / 2 bits and a preset constant.

[0053] Optionally, in RDIA5 mode, the preset constant is Galois field constant 1, the target data is user data with a width of M*J / 2 bits, and the M*J / 2 bit width XOR operation results output by the first XOR unit and the second XOR unit are written into the first register and the second register respectively.

[0054] The XOR calculator writes intermediate check data P back to the XOR cache based on the XOR cache address. The intermediate check data P is M*J bit-width data resulting from the combination of the XOR operation results stored in the first register and the second register.

[0055] Optionally, in RDIA6 mode, the preset constant is the Galois domain constant Ki, the target data is the result of multiplying user data and Ki, the first XOR unit outputs intermediate check data P with a width of M*J / 2 and writes it into the first register, and the second XOR unit outputs intermediate check data Q with a width of M*J / 2 and writes it into the second register.

[0056] The XOR calculator writes a set of intermediate check data back to the XOR cache based on the XOR cache address. The set of intermediate check data is an M*J bit-width data composed of the intermediate check data P stored in the first register and the intermediate check data Q stored in the second register.

[0057] Optionally, the XOR calculator includes a selector, a multiplier, and a Ki register, the Ki register being used to store multiple Ki values;

[0058] The first XOR unit is a first XOR calculation circuit, and the second XOR unit is a second XOR calculation circuit;

[0059] In RDIA5 mode, the second XOR calculation circuit receives user data with a width of M*J / 2 bits; in RDIA6 mode, the second XOR calculation circuit receives the result of multiplying the user data with a width of M*J / 2 bits by the Galois domain constant Ki.

[0060] Optionally, the Ki register is connected to the first input of the multiplier, the second input of the multiplier receives user data with a width of M*J / 2 bits, the output of the multiplier is connected to the first input of the selector, the second input of the selector receives user data with a width of M*J / 2 bits, and the output of the selector is connected to the second XOR calculation circuit.

[0061] In RDIA5 mode, the selector outputs user data with a width of M*J / 2 bits. The second calculation circuit performs an XOR operation on the user data with a width of M*J / 2 bits and the data with a width of M*J / 2 bits provided by the second register, and outputs intermediate check data P with a width of M*J / 2 bits.

[0062] In RDIA6 mode, the selector outputs the multiplication result of M*J / 2 bit wide user data and Ki value. The second calculation circuit performs an XOR operation based on the M*J / 2 bit wide multiplication result and the M*J / 2 bit wide data provided by the second register, and outputs M*J / 2 bit wide intermediate check data Q.

[0063] Optionally, the XOR calculator further includes a constant register for outputting the Galois field constant 1;

[0064] The outputs of the constant register and the Ki register are connected to the input of the selector. The output of the selector is connected to the first input of the multiplier. The second input of the multiplier receives user data with a width of M*J / 2 bits. The output of the multiplier is connected to the second XOR calculation circuit.

[0065] In RDIA5 mode, the selector outputs a Galois field constant of 1, and the multiplier outputs user data with a width of M*J / 2 bits.

[0066] In RDIA6 mode, the selector outputs the Galois field constant Ki value, and the multiplier outputs the result of multiplying the M*J / 2 bit-width user data with the Galois field constant Ki value.

[0067] Optionally, the XOR calculator further includes a third register and a fourth register;

[0068] The third register and the first register are connected to the first XOR calculation circuit. The third register and the first register have the same bit width. The third register and the first register are used for data transfer and providing data for XOR operation at the same time, respectively.

[0069] The fourth register and the second register are connected to the second XOR calculation circuit. The fourth register and the second register have the same bit width. The fourth register and the second register are used for data transfer and providing data for XOR operation at the same time, respectively.

[0070] Optionally, one of the first register and the third register stores half of the data read from the XOR cache at one time, and one of the second register and the fourth register stores the other half of the data read from the XOR cache at one time;

[0071] When the first register receives data provided by the XOR cache, the third register provides the first XOR calculation circuit with data to participate in the XOR operation;

[0072] When the second register receives data provided by the XOR cache, the fourth register provides the second XOR calculation circuit with data to participate in the XOR operation;

[0073] In RDIA5 mode, the first XOR calculation circuit outputs intermediate verification data P with a width of M*J / 2 bits through XOR operation, and the second XOR calculation circuit outputs intermediate verification data P with a width of M*J / 2 bits through XOR operation. The first XOR calculation circuit and the second XOR calculation circuit perform XOR operation based on different user data.

[0074] In RDIA6 mode, the first XOR calculation circuit outputs intermediate parity data P with a width of M*J / 2 bits through XOR operation, and the second XOR calculation circuit outputs intermediate parity data Q with a width of M*J / 2 bits through XOR operation. The first XOR calculation circuit and the second XOR calculation circuit perform XOR operation based on the same user data.

[0075] Optionally, in the first time period, the first register receives half of the data read from the XOR cache at one time, and the second register receives the other half of the data read from the XOR cache at one time;

[0076] In the second time period, the first register provides M*J / 2 bit wide data to the first XOR calculation circuit, the second register provides M*J / 2 bit wide data to the second XOR calculation circuit; the third register receives half of the data read from the XOR buffer again, and the fourth register receives the other half of the data read from the XOR buffer again;

[0077] In the third time period, the XOR operation result cached in the first register and the second register is written back to the XOR cache, the third register provides the first XOR calculation circuit with M*J / 2 bit wide data, and the fourth register provides the second XOR calculation circuit with M*J / 2 bit wide data.

[0078] In the fourth time period, the XOR operation result cached in the third register and the fourth register is written back to the XOR cache;

[0079] The first time period, the second time period, and the third time period are combined to form one calculation cycle, and the second time period, the third time period, and the fourth time period are combined to form another calculation cycle.

[0080] Optionally, the XOR calculator includes a fifth register and a sixth register with a bit width of M*J, and both the fifth register and the sixth register are connected to the first XOR unit;

[0081] The fifth register and the sixth register are used simultaneously for data transfer and to provide the first XOR unit with data to participate in the XOR operation.

[0082] Optionally, during the first time period, the fifth register receives data read from the XOR cache in one go;

[0083] In the first half of the second time period, the fifth register provides the first half of the data read from the first XOR unit; in the second half of the second time period, the fifth register provides the second half of the data read from the first XOR unit; during the second time period, the sixth register receives data read from the XOR cache again.

[0084] In the third time period, the XOR operation result stored in the fifth register is written back to the XOR cache. In the first half of the third time period, the sixth register provides the first half of the data read from the first XOR unit. In the second half of the third time period, the sixth register provides the second half of the data read from the first XOR unit.

[0085] In the fourth time period, the XOR operation result stored in the sixth register is written back to the XOR cache;

[0086] The first time period, the second time period, and the third time period are combined to form one calculation cycle, and the second time period, the third time period, and the fourth time period are combined to form another calculation cycle.

[0087] Secondly, embodiments of this application provide a control component, including a media interface controller, wherein the media interface controller includes the XOR calculation unit described in the first aspect.

[0088] According to the embodiments of this application, by providing an XOR calculation unit that simultaneously supports the calculation of parity data for RAID5 and RAID6, the calculation of parity data under different RAID scenarios can be achieved by improving the XOR calculation unit, based on the sharing of most of the hardware circuits. This allows for reasonable control of the hardware circuit scale of the media interface controller and reduces the cost and power consumption of the hardware circuits.

[0089] In a further embodiment, after generating the page stripe verification data, the storage command processing unit is promptly notified, which then generates a media interface command instructing the transfer of the verification data. This allows for the timely release of the XOR cache unit that caches the verification data. By making reasonable use of the XOR cache unit, the process of writing the verification data to the NVM chip can be further scheduled, thereby improving the performance of the storage device.

[0090] In a further embodiment, by introducing a bus address interleaving unit, the bus address interleaving unit determines the corresponding data block in the XOR cache unit based on the bus address, and provides matching data for bus requests to access the XOR cache, which can avoid the problem of providing data from different data blocks based on the same bus request because the XOR cache has cache units with different RAID modes. Attached Figure Description

[0091] Figure 1AA block diagram representing a storage device;

[0092] Figure 1B A detailed block diagram of the control components of the storage device is shown;

[0093] Figure 2A Diagram 1 showing a large block;

[0094] Figure 2B Diagram 2 showing a large block;

[0095] Figure 3A A schematic diagram illustrating page stripes;

[0096] Figure 3B Schematic diagram 2 showing page stripes;

[0097] Figure 4 This diagram illustrates the process of writing data to SRAM and DRAM using a data copy unit.

[0098] Figure 5 This illustration shows the working principle diagram of an XOR computing unit provided in an embodiment of this application in RAID5 mode;

[0099] Figure 6 This application illustrates a schematic diagram of the data storage method within the XOR cache under RAID5 mode, as provided in an embodiment of this application.

[0100] Figure 7 This application provides a schematic diagram illustrating how an XOR calculator accesses the XOR cache in RAID5 mode, as illustrated in an embodiment of this application.

[0101] Figure 8 Showing Figure 7 A diagram illustrating the periodic access of the XOR cache by the XOR calculator.

[0102] Figure 9 This application illustrates a schematic diagram of the data storage method within the XOR cache under RAID6 mode, as provided in an embodiment of this application.

[0103] Figure 10 This illustration shows the working principle diagram of the XOR computing unit provided in the embodiment of this application in RAID6 mode;

[0104] Figure 11 This application provides a schematic diagram illustrating how an XOR calculator accesses the XOR cache in RAID6 mode, as illustrated in an embodiment of this application.

[0105] Figure 12 Showing Figure 11 A diagram illustrating the periodic access of the XOR cache by the XOR calculator.

[0106] Figure 13A hardware structure diagram of an XOR computing unit provided in one embodiment of this application is shown;

[0107] Figure 14 Showing Figure 13 The provided diagram illustrates how the XOR calculator accesses the XOR cache.

[0108] Figure 15 A hardware structure diagram of an XOR computing unit provided in another embodiment of this application is shown;

[0109] Figure 16A Showing Figure 15 A diagram illustrating the periodic access to the XOR cache in RAID6 mode;

[0110] Figure 16B Showing Figure 15 A diagram illustrating the periodic access to the XOR cache in RAID5 mode;

[0111] Figure 17 The hardware structure diagram of the control component provided in the embodiments of this application is shown;

[0112] Figure 18 This illustration shows the working principle diagram of an XOR computing unit provided in RAID5 mode according to another embodiment of this application;

[0113] Figure 19 for Figure 18 A diagram illustrating the XOR calculator accessing the XOR cache;

[0114] Figure 20A Showing Figure 19 A diagram illustrating the periodic access of the XOR cache by the XOR calculator;

[0115] Figure 20B Showing Figure 19 Schematic diagram 2 showing the XOR calculator periodically accessing the XOR cache;

[0116] Figure 21 This illustration shows a schematic diagram of accessing the XOR cache based on address interleaving units provided in an embodiment of this application. Detailed Implementation

[0117] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0118] Figure 5This diagram illustrates the working principle of an XOR computing unit provided in an embodiment of this application in RAID5 mode.

[0119] The XOR calculation unit includes an XOR calculator and an XOR cache. The XOR cache includes one or more XOR cache units, and the XOR calculator includes registers (such as register Reg). The bit width of register Reg is, for example, 256*8 bits. The XOR calculator receives user data D(i) as input data. The XOR calculator is coupled to the XOR cache, reading data from or writing data to the XOR cache. The XOR cache is, for example, SRAM. The data port between the XOR calculator and the XOR cache has, for example, a bit width of 256*8 bits.

[0120] If the size of the XOR cache unit in the XOR cache is, for example, 2KB, and the size of a piece of user data D(i) is also, for example, 2KB, then the XOR calculator needs to complete the XOR calculation between the user data D(i) and the data in the XOR cache unit in 8 calculation cycles.

[0121] In one calculation cycle, the XOR calculator retrieves 256b*8 data from the XOR cache unit, such as data B( Figure 5 (1) represents the data obtained. The XOR calculation is performed between the 256b*8 data in the user data D(i) and the obtained data B. Figure 5 The result is written back to the XOR cache unit and overwrites the aforementioned 256b*8 data in the XOR cache unit. Figure 5 (represented by (3)).

[0122] In the next calculation cycle, the XOR calculator retrieves the next 256b*8 data from the XOR cache and performs an XOR calculation with the 256b*8 user data. This process continues, performing an XOR operation in each calculation cycle, and completing the XOR calculation between the 2KB user data D(i) and the 2KB data in the XOR cache in 8 calculation cycles ((2*1024*8) / (256*8)).

[0123] Figure 6 This illustration shows a schematic diagram of the data storage method within the XOR cache in RAID5 mode provided in an embodiment of this application.

[0124] The XOR cache is implemented using SRAM and includes, for example, eight memory banks (denoted as Bank0 to Bank7). Each memory bank operates independently and is not affected by the others. The port width of each memory bank is, for example, 256 bits, and the eight memory banks collectively provide the 256*8 bit width of the XOR cache. In this application, the data stored in the XOR cache is referred to as intermediate parity data.

[0125] The 256*8b data width corresponding to the XOR cache data port is divided into 8 parts (each 256b) and connected to each memory bank respectively. The address used to access the XOR cache is called the XOR cache address. When accessing the XOR cache through the XOR cache address, the XOR cache address is provided to each of the 8 memory banks to determine the memory bank address to be accessed.

[0126] The XOR cache unit size is, for example, 2KB. 2KB of data comprises 64 data blocks of 256 bytes each. Figure 6 In this context, Ai represents a 256-bit data block, i represents the sequence number of the data block within the 2KB of data, and the size of the data block is equal to the port width of the memory bank (256 bits).

[0127] 2KB of data corresponds to 64 data blocks, see Figure 6 The data blocks are arranged sequentially in eight storage banks (according to their bank numbers). Each row of eight data blocks is stored in Bank0 through Bank7, and all eight data blocks in a row share the same storage bank address across different banks. For example, data blocks A0 through A7 are in one row, located in different storage banks, but with the same storage bank address. The next row of eight data blocks is stored in the same manner across the eight storage banks. Following this pattern, 2KB data blocks are arranged into eight rows, each corresponding to 256 bytes of data, and the eight data blocks in the same row share the same storage bank address. In this embodiment, the storage bank address of a data block indicates its specific location within the storage bank; it can also be understood as indicating its row number. Given that the storage bank to which a data block belongs is known, the data block can be located based on its specific location (e.g., row number). For a row of eight data blocks, although they correspond to different bank numbers, they share the same row number and therefore the same storage bank address.

[0128] Each time the XOR cache is accessed, 256*8b of data is received from its data port or written to the XOR cache. This data corresponds to a row of 8 data blocks in the XOR cache unit, and each data block has a corresponding memory bank address. Thus, when an external device (e.g., an XOR calculator) accesses the 256*8b of data provided by the XOR cache using a single address (the XOR cache address), this single address (the XOR cache address) is translated into the addresses of the individual memory banks to access the 256b of data provided by each memory bank.

[0129] Figure 7 This illustration shows a schematic diagram of an XOR calculator accessing the XOR cache in RAID5 mode, as provided in an embodiment of this application.

[0130] When the XOR calculator reads data from the XOR cache, an XOR cache address is provided to the XOR cache in each calculation cycle. The address interleaving unit processes this XOR cache address, converting it into a memory address provided to each memory bank. For example, the XOR cache address consists of 16 bits (A15 to A0), and the address interleaving unit determines the memory address corresponding to each memory bank based on {A15 to A8} and provides it to the corresponding memory bank. For example, the address interleaving unit generates 8 memory bank addresses based on the XOR cache address and provides them to 8 memory banks, where the 8 memory bank addresses are the same and correspond to a row of 8 data blocks.

[0131] In one alternative implementation, the eight storage banks of the XOR cache can operate simultaneously. Each storage bank, in response to a received storage bank address, outputs 256 bits of data to the XOR cache's data port. The XOR cache collects the data output from the eight storage banks, obtaining 256*8 bits of data, which is then provided to the XOR calculator to provide the XOR calculator with data from the XOR cache based on read operations accessing the XOR cache.

[0132] In another alternative implementation, the data ports of the memory banks and the XOR cache share a 256-bit data path, requiring the eight memory banks to time-share the data path. It's important to understand that each memory bank is 256 bits wide, while the XOR cache's data port is 256*8 bits externally and 256 bits internally. Therefore, the internal bit width of the XOR cache's data port is consistent with the bit width of each memory bank.

[0133] Specifically, at time c0, the address interleaving unit generates a memory address for bank0 based on the XOR cache address, provides the memory address to bank0, and receives its output 256 bits of data. At time c1, the address interleaving unit generates a memory address for bank1 based on the XOR cache address, provides the memory address to bank1, and receives its output 256 bits of data. In this manner, 256*8 bits of data are obtained from eight memory banks and provided to the XOR calculator.

[0134] Figure 8 Showing Figure 7 A diagram illustrating how the XOR calculator periodically accesses the XOR cache.

[0135] During time interval t1, the XOR calculator provides XOR cache address 1, reads 256*8b data from the XOR cache, and records it in register Reg. For this purpose, the address interleaving unit generates 8 memory bank addresses based on XOR cache address 1 and provides them to 8 memory banks to obtain the 256*8b data corresponding to the first row of 8 data blocks.

[0136] During time period t2, within the XOR calculator, the XOR operation is performed between the 256*8b intermediate parity data provided by the XOR cache and the 256*8b user data, and the Reg register is updated based on the operation result.

[0137] During time period t3, the XOR calculator writes 256*8b of data from the Reg register back to the XOR cache based on XOR cache address 1, in order to overwrite the previous 256*8b of intermediate parity data.

[0138] t1-t3 together represent one calculation cycle. Within this calculation cycle, the XOR calculator obtains 256*8b data corresponding to a row of 8 data blocks in the XOR cache unit based on XOR cache address 1, performs an XOR operation between the 256*8b data provided by the XOR cache and the 256*8b user data, and updates the data in the XOR cache based on the operation result.

[0139] t4-t6 represent the next computation cycle. During this cycle, XOR cache address 2 is used to access the 256*8b data corresponding to the second row of 8 data blocks, perform an XOR operation, and update the data in the XOR cache based on the operation result. This process continues for 8 computation cycles, completing the XOR calculation between the user data D(i) and the data in the XOR cache unit.

[0140] Figure 9 This illustration shows a schematic diagram of the data storage method within the XOR cache in RAID6 mode provided in an embodiment of this application.

[0141] The size of an XOR cache unit is, for example, 2KB. In RAID6 mode, a page stripe includes two parity data sets (parity data P and parity data Q), each 2KB in size, and therefore each occupies one XOR cache unit. XOR cache unit 0 is used to store parity data P, and XOR cache unit 1 is used to store parity data Q.

[0142] A pair of parity data (P and Q) needs to be written to the same page stripe and calculated from the same user data (e.g., D(0) to D(N-2)). Each parity data occupies 4 banks in the XOR cache. Thus, each parity data block of 64 data occupies 16 consecutive rows in the XOR cache.

[0143] A pair of parity data corresponds to 16 rows of data blocks, and each row of data blocks corresponds to an XOR cache address. That is, a row of 8 data blocks in the XOR cache corresponds to the same XOR cache address. The 4 data blocks belonging to bank0-bank3 belong to parity data P, while the 4 data blocks belonging to bank4-bank7 belong to parity data Q. Here, P and Q are a pair of parity data. Figure 9In the XOR buffer unit 0 and XOR buffer unit 1, P and Q are a pair of parity data. For each parity data, within its occupied XOR buffer unit, 64 data blocks are arranged sequentially according to the data block number.

[0144] It should be noted that, Figure 9 In the example, the data blocks corresponding to the first four memory banks belong to parity data P, and the data blocks corresponding to the last four memory banks belong to parity data Q. This is just a relatively simple way of partitioning the data; other partitioning methods are also possible. For example, the data blocks corresponding to memory banks 1, 3, 5, and 7 belong to parity data P, and the data blocks corresponding to memory banks 0, 2, 4, and 6 belong to parity data Q.

[0145] The XOR calculator accesses XOR cache cells 0 and 1 in the XOR cache over 16 calculation cycles. In the first cycle, based on XOR cache address 1, the calculator reads the first row of 8 data blocks (256*8b), originating from data blocks A0-A3 in XOR cache cell 0 and XOR cache cell 1. In the second cycle, based on XOR cache address 2, the calculator reads the second row of 8 data blocks (256*8b), originating from data blocks A4-A7 in XOR cache cell 0 and XOR cache cell 1. This process continues, accessing XOR cache cells 0 and 1 based on 16 XOR cache addresses. For the XOR cache, each output of 256*8b data includes four data blocks from each of a parity pair (P and Q).

[0146] Figure 10 This paper illustrates the working principle of the XOR computing unit provided in the embodiment of this application in RAID6 mode.

[0147] The XOR calculator includes an XOR unit P and an XOR unit Q, used to calculate the parity data P and Q, respectively. In RAID6 mode, the parity data P = (data in the XOR cache) XOR D(i), and the parity data Q = (data in the XOR cache) XOR (D(i) * k(i)), where K(i) is a predetermined constant that is pre-stored in the XOR calculator.

[0148] In RAID 5 mode, the Reg register of the XOR cache has a bit width of 256*8 bits. In RAID 6 mode, the Reg register is divided into two parts, denoted as register Reg_P and register Reg_Q, each with a bit width of 256*4 bits. Register Reg_P stores a row of 4 data blocks corresponding to the intermediate parity data P from the XOR cache, and register Reg_Q stores a row of 4 data blocks corresponding to the intermediate parity data Q from the XOR cache.

[0149] The XOR unit P receives 256*4b data from register Reg_P, performs an XOR operation on the acquired 256*4b data and the 256*4b data of D(i), and writes the result to register Reg_P to update it. The XOR unit Q receives 256*4b data from register Reg_Q, performs an XOR operation on the acquired 256*4b data, the 256*4b data of D(i), and the Galois field multiplication result of k(i), and writes the result to register Reg_Q to update it. Then, the updated data from registers Reg_P and Reg_Q are combined and written back to the corresponding location in the XOR buffer as 256*8b data to update the data in the XOR buffer.

[0150] Therefore, it can be seen that in RAID6 mode, the way and process by which the XOR calculator reads data from the XOR cache and writes data to it is exactly the same as in RAID5 mode, so the relevant read and write control circuits do not need to be modified.

[0151] Figure 10 The process by which the combined registers Reg_P and Reg_Q provide 256*8b of data and store the XOR operation result of 256*8b is essentially the same as the operation of the Reg register in RAID5 mode. Therefore, the XOR units P and Q can be used in RAID5 scenarios. When used in RAID5 scenarios, only the input data provided to the XOR unit Q needs to be modified, replacing D(i)*k(i) with D(i), while the connection relationship between registers Reg_P and Reg_Q and the XOR units P and Q remains unchanged. Thus, Figure 10 The provided XOR calculation unit is applicable to the calculation of parity data in both RAID5 and RAID6 scenarios.

[0152] Figure 11 This illustration shows a schematic diagram of an XOR calculator accessing the XOR cache in RAID6 mode, as provided in an embodiment of this application.

[0153] In each computation cycle, the XOR calculator reads 256*8b of data from the XOR cache based on the XOR cache address. This 256*8b data includes four data blocks associated with intermediate parity data P from XOR cache unit 0, and four data blocks associated with intermediate parity data Q from XOR cache unit 1. During this process, the address interleaving unit determines the corresponding memory bank addresses for each of the eight memory banks based on the XOR cache address and provides them to the eight memory banks. Four memory banks (bank0-bank3) provide the four data blocks associated with intermediate parity data P, and the other four memory banks (bank4-bank7) provide the four data blocks associated with intermediate parity data Q. Since the XOR calculator reads 256*8b of data from the XOR cache each time, including the four data blocks associated with intermediate parity data P and the four data blocks associated with intermediate parity data Q, and the address interleaving unit provides the corresponding memory bank addresses for each of the eight memory banks, the address interleaving unit does not need to be modified.

[0154] Within the XOR calculator, an XOR operation is performed on the four data blocks from XOR cache unit 0 and the 256*4b user data D(i). An XOR operation is also performed on the result of the four data blocks from XOR cache unit 1 and the 256*4b user data D(i)*k(i). The result of the two XOR operations, totaling 256*8b of data, is written back to the XOR cache.

[0155] In this calculation cycle, the XOR cache address is different for each cycle. In the first cycle, the XOR calculator reads the first row of 8 data blocks from XOR cache units 0 and 1 based on XOR cache address 1. In the next cycle, the XOR cache address is changed, and the calculator reads the second row of 8 data blocks from XOR cache units 0 and 1 based on XOR cache address 2. This process continues until a pair of checksums is calculated over 16 cycles.

[0156] Figure 12 Showing Figure 11 A diagram illustrating how the XOR calculator periodically accesses the XOR cache.

[0157] During time period t1, the XOR calculator provides XOR cache address 1 and reads 256*8b of data from the XOR cache. Half of the read data comes from XOR cache unit 0 and belongs to intermediate parity data P, while the other half comes from XOR cache unit 1 and belongs to intermediate parity data Q. The 256*4b of data belonging to intermediate parity data P is recorded in register Reg_P, and the 256*4b of data belonging to intermediate parity data Q is recorded in register Reg_Q. Registers Reg_P and Reg_Q are equivalent to the first half and the second half of the corresponding Reg register in RAID5 mode.

[0158] During time period t1, the address interleaving unit generates 8 memory bank addresses based on XOR cache address 1 and provides them to 8 memory banks. Four memory banks (bank0-bank3) provide 4 data blocks associated with intermediate parity data P in the first row of data blocks, and another 4 memory banks (bank4-bank7) provide 4 data blocks associated with intermediate parity data Q in the first row of data blocks, thereby providing 256*8b of data, which are then used to fill registers Reg_P and Reg_Q respectively.

[0159] At time t2, within the XOR calculator, an XOR operation is performed based on the data stored in register Reg_P and user data D(i), and an XOR operation is performed based on the data stored in register Reg_Q and the result of multiplying user data D(i) with k(i). Registers Reg_P and Reg_Q are then updated based on the operation results.

[0160] During time period t3, the XOR calculator writes 256*8b of data provided by registers Reg_P and Reg_Q back to the XOR cache based on XOR cache address 1.

[0161] t1-t3 together represent one calculation cycle. Within this calculation cycle, the XOR calculator obtains a row of 4 data blocks from XOR cache unit 0 and a row of 4 data blocks from XOR cache unit 1 based on XOR cache address 1. It performs an XOR operation on the obtained data and the user data, and updates the data in XOR cache unit 0 and XOR cache unit 1 based on the operation result.

[0162] For each subsequent calculation cycle, data is read from the XOR cache unit based on the above logic, and the calculation result is written back to the XOR cache unit after performing the XOR operation. After 16 calculation cycles, the calculation of the check data P and the check data Q is completed.

[0163] Figure 13 A hardware structure diagram of an XOR computing unit provided in one embodiment of this application is shown.

[0164] exist Figure 13 The XOR calculator includes two XOR calculation circuits (XOR calculation circuit 1 and XOR calculation circuit 2), a multiplier, a selector, registers Reg_1 and Reg_2 (each register has a bit width of 256*4), and register Ki (used to store multiple Ki values). XOR calculation circuit 1 and XOR calculation circuit 2 are equivalent to the two XOR units in the previous embodiment.

[0165] XOR calculation circuits 1 and 2 are used to perform XOR operations on two 256*4b data points, namely user data and intermediate parity data from the XOR buffer. XOR calculation circuit 1 is connected to register Reg_1 and directly receives user data. It performs an XOR operation between the 256*4b user data and the 256*4b data in register Reg_1. Register Reg_1 stores the 256*4b intermediate parity data from the XOR buffer. XOR calculation circuit 2 is connected to register Reg_2 and a selector. Register Reg_2 stores the 256*4b intermediate parity data from the XOR buffer. The selector is connected to a multiplier and can also directly receive 256*4b user data. The multiplier is connected to register Ki and directly receives 256*4b user data. It performs a Galois multiplication of the 256*4b user data D(i) and k(i). The input data width to the multiplier is 256*4b. The selector can choose to directly output user data or output the result of the multiplication of user data D(i) and k(i) to XOR calculation circuit 2 based on the XOR calculator's operating mode. If the XOR calculator is in RAID5 operating mode, the selector outputs user data to XOR calculation circuit 2. XOR calculation circuit 2 performs an XOR operation based on the 256*4b user data and the data provided by register Reg_2. XOR calculation circuit 1 performs an XOR operation based on the 256*4b user data and the data provided by register Reg_1. The XOR operation updates the data in registers Reg_2 and Reg_1, and combines the data in registers Reg_2 and Reg_1 into 256*8b data, which is then written back to the XOR cache. If the XOR calculator is in RAID6 mode, the selector provides the result of the multiplication of user data and k(i) to XOR calculation circuit 2. XOR calculation circuit 2 performs an XOR operation based on the multiplication result and the data provided by register Reg_2. XOR calculation circuit 1 performs an XOR operation based on the 256*4b user data and the data provided by register Reg_1. The XOR operation updates the data in registers Reg_2 and Reg_1, combines the data in registers Reg_2 and Reg_1 into 256*8b data, and writes it back to the XOR cache.

[0166] In this application, the size of user data D(i) is, for example, 2KB. In each calculation cycle of RAID5 working mode, 256*4b of user data D(i) is provided to XOR calculation circuit 1 and XOR calculation circuit 2. XOR calculation circuit 1 performs an XOR operation based on the 256*4b user data and the data in register Reg_1. XOR calculation circuit 2 performs an XOR operation based on the 256*4b user data and the data in register Reg_2. The data in register Reg_1 and register Reg_2 are combined into 256*8b data and written back to the corresponding position of XOR cache.

[0167] In each calculation cycle of RAID6 operating mode, 256*4b of user data D(i) is provided to XOR calculation circuit 1, multiplier, and selector. The selector outputs the calculation result of the multiplier and provides it to XOR calculation circuit 2. Within one calculation cycle, the 256*4b user data used to calculate parity data P and parity data Q are the same. The XOR cache provides 256*8b of data to the XOR calculator. The first half (256*4b) of the data is written to register Reg_1 for calculating parity data P, and the second half (256*4b) of the data is written to register Reg_2 for calculating parity data Q. After the calculation is completed based on XOR calculation circuit 1 and XOR calculation circuit 2, registers Reg_1 and Reg_2 are combined into 256*8b of data and written back to the corresponding position in the XOR cache. Half of the 256*8b data belongs to parity data P, and the other half belongs to parity data Q.

[0168] exist Figure 13 The hardware structure shown can select whether to perform XOR operation in RAID5 mode or RAID6 mode based on the specific working mode of the XOR calculator. This allows for the calculation of parity data in both RAID5 and RAID6 scenarios without the need for two XOR calculation units. This achieves an improvement based on the XOR calculation unit, using a single XOR calculation unit to support the calculation of parity data in both RAID5 and RAID6 modes simultaneously.

[0169] Figure 14 Showing Figure 13 The provided diagram illustrates how the XOR calculator accesses the XOR cache.

[0170] Regardless of whether the XOR calculator operates in RAID5 or RAID6 mode, the XOR cache does not need to be changed for different RAID modes. That is, the XOR cache is applicable to both RAID5 and RAID6 modes. However, the data content stored in the XOR cache (in other words, the arrangement of XOR cache cells in the XOR cache) will change with the RAID mode.

[0171] In RAID 5 mode, one XOR cache unit (used to store parity data P) occupies 8 rows of data blocks across 8 banks, with each row containing 8 data blocks. In RAID 6 mode, two XOR cache units (used to store parity data P and parity data Q) each occupy 16 rows of data blocks across 4 banks, with each row containing 4 data blocks. Regardless of the RAID mode, each time data is read from the XOR cache, one row of 8 data blocks (a total of 256*8 bytes) from 8 banks is read. Specifically, in RAID 5 mode, one row of 8 data blocks is read from one XOR cache unit; in RAID 6 mode, one row of 8 data blocks is read from two XOR cache units. Four data blocks are used to calculate parity data P, and the other four data blocks are used to calculate parity data Q.

[0172] Figure 14 The structure and operation of the XOR cache shown are applicable to both operating modes. Therefore, by simply changing the arrangement of the XOR cache cells in the XOR cache, it is possible to simultaneously support parity data calculation in RAID5 and RAID6 modes.

[0173] Figure 15 A hardware structure diagram of an XOR computing unit provided in another embodiment of this application is shown.

[0174] exist Figure 15 The XOR calculator includes two XOR calculation circuits (XOR calculation circuit 1 and XOR calculation circuit 2), a multiplier, a selector, a register Ki, and four Reg registers (Reg_1_A, Reg_1_B, Reg_2_A, and Reg_2_B), each of which has a bit width of 256*4 bits.

[0175] In RAID5 mode, registers Reg_1_A and Reg_1_B are used to store the first half of the data (256*4b) read in one operation. In RAID6 mode, registers Reg_1_A and Reg_1_B are used to store intermediate parity data P. In RAID5 mode, registers Reg_2_A and Reg_2_B are used to store the second half of the data (256*4b) read in one operation. In RAID6 mode, registers Reg_2_A and Reg_2_B are used to store intermediate parity data Q.

[0176] exist Figure 15In the illustrated structure, XOR calculation circuit 1 is connected to registers Reg_1A and Reg_1_B, directly receiving 256*4b of user data. Simultaneously, registers Reg_1_A and Reg_1_B are used for data transfer and data calculation, respectively. Register Reg_1_A is used to transfer data from the XOR buffer, while register Reg_1_B provides 256*4b of data for the XOR operation. For example, when reading data from the XOR buffer, register Reg_1_A receives the data, and at the same time, register Reg_1_B provides 256*4b of data for the XOR operation. Thus, data transfer and data calculation can be performed simultaneously. Correspondingly, if register Reg_1_B is used to receive data, then register Reg_1_A provides 256*4b of data for the XOR operation.

[0177] XOR calculation circuit 2 connects registers Reg_2_A and Reg_2_B. Registers Reg_2_A and Reg_2_B are used for data transfer and data calculation, respectively. That is, one register Reg_2_A is used to move data from the XOR buffer, and the other is used to provide 256*4b of data for the XOR operation. At the same time, registers Reg_1A and Reg_2_A have the same purpose, either both for data transfer or both for data calculation, and registers Reg_1_B and Reg_2_B have the same purpose, either both for data calculation or both for data transfer. Unlike XOR calculation circuit 1, XOR calculation circuit 2 does not directly receive user data. Instead, it is connected to a multiplier. The multiplier receives 256*4b of user data and is connected to a selector. The input of the selector is connected to register Ki and a constant 1, allowing selection of whether to provide K(i) or the constant 1 to the multiplier. In RAID 5 mode, the selector provides a constant 1 to the multiplier, causing the multiplier to output 256*4b of user data to XOR calculation circuit 2. XOR calculation circuit 2 performs an XOR operation based on the 256*4b of user data and the data moved from the XOR cache. In RAID 6 mode, the selector provides K(i) to the multiplier, causing the multiplier to output the corresponding data of D(i)*k(i). XOR calculation circuit 2 performs an XOR operation based on the corresponding data of D(i)*k(i) and the data moved from the XOR cache.

[0178] XOR calculation circuit 1 and XOR calculation circuit 2 are used to perform the XOR operation on two 256*4b data. XOR calculation circuit 1 performs the XOR operation on the 256*4b user data and the 256*4b intermediate check data. XOR calculation circuit 2 performs the XOR operation on the result of Ki and D(i) and the 256*4b intermediate check data.

[0179] Figure 16A Showing Figure 15 A diagram illustrating the periodic access to the XOR cache in RAID6 mode.

[0180] In each calculation cycle, 256*4b of user data is simultaneously provided to the multiplier and XOR calculation circuit 1. The 256*4b of user data provided to the multiplier is used to calculate the check data Q, and the user data provided to XOR calculation circuit 1 is used to calculate the check data P. Based on the result of multiplying the 256*4b of user data with K(i), the multiplier provides data to XOR calculation circuit 2. Thus, within one calculation cycle, the user data provided to XOR calculation circuit 2 for calculating the check data Q is the same as the user data provided to XOR calculation circuit 1 for calculating the check data P.

[0181] During time period t1, the XOR buffer provides 256*8b of data to the XOR calculator. The first half (256*4b) of data is written to register Reg_1_A for calculating the check data P, and the second half (256*4b) is written to register Reg_2_A for calculating the check data Q.

[0182] During time interval t2, XOR calculation circuit 1 performs an XOR operation on the data stored in register Reg_1_A and the 256*4b user data to calculate the checksum P; XOR calculation circuit 2 performs an XOR operation on the data stored in register Reg_2_A and the result of multiplying the 256*4b user data with K(i) to calculate the checksum Q. Simultaneously, during time interval t2, the XOR buffer provides the XOR calculator with the next 256*8b data; the first half (256*4b) of the data is written to register Reg_1_B, and the second half is written to register Reg_2_B.

[0183] During time period t3, the data calculated in registers Reg_1_A and Reg_2_A is combined into 256*8b data and written back to the XOR buffer; at the same time, XOR calculation circuit 1 and XOR calculation circuit 2 use the data in registers Reg_1_B and Reg_2_B to calculate the parity data P and parity data Q.

[0184] During time slot t4, the data calculated in registers Reg_1_B and Reg_2_B is combined into 256*8b data and written back to the XOR cache.

[0185] In the above calculation process, since registers Reg_1_A and Reg_1_B are used to move data from the XOR buffer and provide 256*4b of data for the XOR operation, respectively, and registers Reg_2_A and Reg_2_B are also used to move data from the XOR buffer and provide 256*4b of data for the XOR operation, one calculation cycle includes t1, t2, and t3; another calculation cycle includes t2, t3, and t4. These two calculation cycles partially overlap in time, thereby improving the computational bandwidth of the XOR calculation unit. Based on 16 calculation cycles, the calculation of parity data P and parity data Q can be completed.

[0186] Figure 16B Showing Figure 15 A diagram illustrating the periodic access to the XOR cache in RAID5 mode.

[0187] In each calculation cycle, the 256*8b user data is divided into two 256*4b data sets, which are provided to the multiplier and XOR calculation circuit 1 respectively. The multiplier provides the 256*4b user data set to the XOR calculation circuit 2. Thus, within one calculation cycle, the user data used by XOR calculation circuit 2 and XOR calculation circuit 1 to calculate the check data P are different. The two sets of user data are combined to form the 256*8b user data set.

[0188] During time period t1, the XOR buffer provides 256*8b of data to the XOR calculator. The first half (256*4b) of data is written to register Reg_1_A for calculating the check data P, and the second half (256*4b) is written to register Reg_2_A for calculating the check data P.

[0189] During time interval t2, XOR calculation circuit 1 performs an XOR operation on the data stored in register Reg_1A and the 256*4b user data to obtain B1, and XOR calculation circuit 2 performs an XOR operation on the data stored in register Reg_2_A and the 256*4b user data to obtain B2. Simultaneously, during time interval t2, the XOR buffer provides the XOR calculator with the next 256*8b data; the first half (256*4b) of the data is written to register Reg_1_B, and the second half is written to register Reg_2_B.

[0190] During time period t3, the data calculated in registers Reg_1_A and Reg_2_A are combined into 256*8b data and written back to the XOR buffer; at the same time, XOR calculation circuit 1 and XOR calculation circuit 2 use the data in registers Reg_1_B and Reg_2_B, as well as two 256*4b data, to calculate the check data.

[0191] During time slot t4, the data calculated in registers Reg_1_B and Reg_2_B is combined into 256*8b data and written back to the XOR cache.

[0192] Similarly, since two adjacent calculation cycles partially overlap in time, the computational bandwidth of the XOR calculation unit can be improved. Unlike RAID6 mode, in RAID5 mode, XOR calculation circuit 1 and XOR calculation circuit 2 can work together to complete the calculation of parity data P based on 8 calculation cycles.

[0193] DRAMLess solid-state drives (SSDs), as a type of SSD that does not have (or has only a few) built-in independent DRAM chips, offer advantages in terms of cost and power consumption. This is because they eliminate the need for DRAM chips. Figure 4 The structure shown is no longer applicable, so an improved method for processing verification data needs to be designed.

[0194] After the parity data is calculated, during the process of writing the parity data to the NVM chip, the NVM chip (or LUN) being written to may be processing other commands and cannot immediately receive the parity data to be written. Since the XOR cache is a highly scarce resource, keeping the parity data in the XOR cache while waiting for other commands on the NVM chip to complete will severely impact the performance of the storage device. Therefore, it is desirable to further schedule the process of writing the parity data to the NVM chip after the parity data for page striping is generated, in order to improve the performance of the storage device.

[0195] Based on this, this application provides a processing method in which the storage command processing unit generates a new command for the verification data to write the verification data into the NVM chip. It is worth noting that the process of generating page strip verification data is time-consuming. Under the existing architecture, verification data will only appear in the XOR cache after all user data in the page strip has been written to the NVM chip. Therefore, the storage command processing unit needs to be notified promptly when the page strip verification data appears to facilitate efficient subsequent processing.

[0196] Figure 17 A hardware structure diagram of the control component provided in an embodiment of this application is shown.

[0197] and Figure 4 Compared to the structure shown, Figure 17 The data copying unit has been eliminated. When processing write commands, data from the host is moved to SRAM by the DMA unit. To enable the same chip to support different application scenarios (e.g., storage devices with DRAM and storage devices without DRAM), "eliminating the data copying unit" means that the data copying unit exists in the control unit but is configured to be inactive.

[0198] exist Figure 17 In this configuration, the media interface controller adds multiple counters (denoted as CNTs), each corresponding to an XOR buffer unit. When allocating an XOR buffer unit for a page strip, the media interface controller is informed of the number of user data for that page strip (e.g., N, i.e., the parity data for that page strip is generated based on N copies of user data). The media interface controller sets N to the count value of the counter corresponding to the allocated XOR buffer unit.

[0199] Each time the XOR calculation unit receives a piece of user data, it updates the intermediate parity data in the corresponding XOR cache unit based on the XOR operation and decrements the counter corresponding to that XOR cache unit by 1. When the counter decrements to 0, it means that the final parity data that can be written to the page stripe has appeared in the XOR cache unit. At this time, the media interface controller sends a notification message to the storage command processing unit, and the notification message carries the index of the XOR cache unit.

[0200] Upon receiving a notification message, the storage command processing unit, in response to the message, further processes the parity data indicated by the index of the XOR cache unit carried in the notification message. For example, it generates a media interface command that instructs the media interface controller to write the parity data in the XOR cache unit to a specified physical address of the NVM chip, thereby writing the parity data into a page stripe. Alternatively, the media interface command instructs the media interface controller to move the parity data in the XOR cache unit to SRAM and release the XOR cache unit, allowing it to be allocated to other page stripes for efficient use. At an appropriate time, it generates another media interface command to write the parity data already moved to SRAM into the NVM chip, thus writing the parity data into a page stripe.

[0201] As an optional implementation, the media interface controller provides a "Terminate" function. Based on this function, a CNT counter in the XOR calculation unit is forcibly cleared to 0. After the counter is cleared, the media interface controller sends a notification message to the storage command processing unit. In response to the received notification message, the storage command processing unit writes the intermediate parity data stored in the corresponding XOR cache unit into SRAM, thereby releasing the current XOR cache unit in a timely manner. Subsequently, at an appropriate time, an XOR cache unit is reallocated to this page strip, and XOR calculations are continued based on the intermediate parity data written to SRAM and the received user data to obtain complete parity data to be written to the page strip.

[0202] The "Terminate" function of the media interface controller is executed based on media interface commands issued by the storage command processing unit to the media interface controller. The media interface controller executes the termination function in the following scenarios: 1. The host issues some write commands, writing the data carried by these write commands into a page stripe, but the page stripe is not yet full, i.e., not all N copies of user data used to generate checksum data have been received. Subsequently, no new write commands are received from the host for a long time, causing the checksum data for that page stripe to be delayed in generation. At this time, based on the instruction from the storage command processing unit, the media interface controller uses the "Terminate" function to clear the counter to zero and move the intermediate checksum data out of the current XOR cache unit, so that the current XOR cache unit can be used for other page stripes, avoiding the XOR cache unit being occupied by the current page stripe for a long time. 2. When the device is powered off (e.g., host shutdown, control component shutdown), based on the instruction from the storage command processing unit, the media interface controller uses the "Terminate" function to forcibly clear the counter to 0, so as to store the intermediate checksum data in a timely manner.

[0203] In another optional implementation, the media interface controller also provides a "virtual write" function. The storage command processing unit provides a piece of data (denoted as D(x)) to the media interface controller. The media interface controller uses D(x) as user data to update the intermediate parity data in the XOR cache unit. Accordingly, the counter is decremented, but since D(x) is not actual user data, it is not written to the NVM chip. Therefore, in scenarios where no new write commands are received from the host for a long time, the "virtual write" function can be used to calculate complete parity data based on the data D(x) provided by the storage command processing unit, allowing the XOR cache unit to be released in a timely manner and avoiding long-term occupation of the XOR cache unit. D(x) can be, for example, all zeros or a specified value.

[0204] for Figure 17 The counter provided in the embodiment can also be used Figure 5 , Figure 10 , Figure 13 , Figure 15 In the corresponding embodiments described above, a counter is provided for the XOR cache unit. In RAID5 mode, each cache unit corresponds to one counter, and in RAID6 mode, one counter corresponds to two cache units. That is, two cache units corresponding to parity data P and parity data Q of the same page strip share one counter. The counter is set with a value based on the number of user data provided by the page stripe corresponding to the XOR cache unit. When the counter is normally cleared to 0, it is determined that the XOR cache unit stores complete parity data.

[0205] Figure 18This illustration shows the working principle of the XOR computing unit provided in another embodiment of this application in RAID5 mode.

[0206] and Figure 5 and Figure 10 The XOR calculation units provided are different, in Figure 18 In the XOR function, the XOR calculator includes two registers (denoted as Reg_A and Reg_B), each with a bit width of 256*8 bits. The XOR calculator also includes an XOR unit, which has a bit width of either 256*8 bits or 256*4 bits. Each cache unit corresponds to a counter CNT, used to record the number of user data items corresponding to the allocated page stripe.

[0207] Figure 19 for Figure 18 The diagram illustrates how the XOR calculator accesses the XOR cache.

[0208] The storage method of verification data in the XOR cache is the same as Figure 7 The parity data storage method is the same for RAID5. Each XOR cache unit occupies 8 banks, providing 8 data blocks per row. Each data block is 32 bytes in size. For further details, please refer to [link to relevant documentation]. Figure 7 The relevant descriptions will not be elaborated here. Each counter in the XOR calculation unit corresponds one-to-one with an XOR cache unit. The XOR calculator reads a row of data blocks from the XOR cache each time, calculates the parity data P, and writes the result back to the XOR cache. After eight such calculation cycles, the counter CNT corresponding to the accessed XOR cache unit gradually decreases. If CNT decreases to 0, a notification message is sent to the storage command processing unit.

[0209] Figure 20A Showing Figure 19 A diagram illustrating the periodic access of the XOR cache by the XOR calculator.

[0210] exist Figure 20AIn this process, the XOR unit has a bit width of 256*8 bits. During time interval t1, the XOR calculator reads 256*8 bits of data (e.g., data B0) from the XOR buffer and writes it to register Reg_A. During time interval t2, the XOR unit performs an XOR operation on data B0 in register Reg_A and the 256*8 bits of user data, and writes the result back to register Reg_A to update the data in register Reg_A. Simultaneously, the next row of 256*8 bits of data (e.g., data B1) is read from the XOR buffer and written to register Reg_B. During time interval t3, the data in register Reg_A is written back to the XOR buffer, and the XOR unit performs an XOR operation on data B1 in register Reg_B and the 256*8 bits of user data, writing the result back to register Reg_B to update the data in register Reg_B. During time interval t4, the data in register Reg_B is written back to the XOR buffer.

[0211] Figure 20B Showing Figure 19 The diagram below illustrates how the XOR calculator periodically accesses the XOR cache.

[0212] exist Figure 20B In this context, the bit width of the XOR unit is 256*4 bits. During the t1 time interval, the XOR calculator reads 256*8 bits of data (such as data B0) from the XOR buffer and writes it to register Reg_A.

[0213] In this embodiment, the 256*4b bit width of the XOR unit is smaller than the 256*8b bit width of the register. The time required for an XOR operation is typically less than the time required to read data from the XOR cache; therefore, t2 can be subdivided into two segments, denoted as t21 and t22. During t21, the 256*4b XOR unit performs an XOR operation on the first half of the data (B0_1) in register Reg_A and 256*4b of user data, and writes the result back to the first half of register Reg_A. During t22, the 256*4b XOR unit performs an XOR operation on the second half of the data (B0_2) in register Reg_A and another 256*4b of user data, and writes the result back to the second half of register Reg_A. Thus, during t2, the XOR unit performs two XOR operations, calculating 256*4b of data each time. Therefore, when the bit width of the XOR unit decreases, the required hardware resources are significantly reduced compared to the 256*8b bit width XOR unit in the previous example. During the t2 time period, the XOR calculator also reads the next row of 256*8b data (such as data B1) from the XOR cache and writes it to the register Reg_B.

[0214] During time slot t3, the data in register Reg_A is written back to the XOR buffer. Time slot t3 also includes two other time slots, t31 and t32. In time slot t31, the XOR unit corresponding to the 256*4b bit width performs an XOR operation on the first half of the data (B1_1) in register Reg_B and 256*4b of user data, and the result is written back to the first half of register Reg_B. In time slot t32, the XOR unit corresponding to the 256*4b bit width performs an XOR operation on the second half of the data (B1_2) in register Reg_B and the remaining 256*4b of user data, and the result is written back to the second half of register Reg_B. Thus, during time slot t3, the XOR unit performs two XOR operations, each calculating 256*4b of data.

[0215] During time slot t4, the data in register Reg_B is written back to the XOR cache.

[0216] Figure 20B This paper describes the XOR operation when the XOR unit has a width of 256*4 bits. To further reduce the hardware resources required for XOR operations, the bit width of the XOR unit can be further reduced. For example, when the XOR unit has a width of 256 bits, it needs to perform 8 XOR operations in time periods t2 and t3.

[0217] In some implementations, after the XOR cache unit stores the parity data for page striping, the parity data in the XOR cache unit needs to be moved to the NVM chip. The parity data in the XOR cache unit can be moved to SRAM first and then moved to the NVM chip at an appropriate time, or it can be moved directly from the XOR cache unit to the NVM chip.

[0218] The XOR cache is connected to the XOR calculator via a 256*8b port, but there is no direct connection between the XOR cache and the NVM chip; a bus connection (e.g., AIX bus) is required. As a bus device, the XOR cache occupies a certain address space on the bus. When moving data from the XOR cache to the NVM chip, a 2KB memory space needs to be specified within the address space occupied by the XOR cache on the bus to describe the data to be moved.

[0219] However, for both RAID5 and RAID6 operating modes, the 2KB XOR cache unit contains different and partially overlapping data blocks in the XOR cache (see, for example, see...). Figure 6 and Figure 9 This means that for data read requests from the bus to the XOR cache unit (reading 2KB of address space), different addresses need to be specified depending on the RAID5 / RAID6 mode, which makes it difficult to read data from the XOR cache unit via the bus.

[0220] Based on this, this application embodiment provides two address interleaving units for the XOR cache, which are respectively denoted as address interleaving unit 1 for the XOR calculator and address interleaving unit 2 for the bus. The bus address is converted into the memory address for accessing the XOR cache through address interleaving unit 2 for the bus.

[0221] Figure 21 This illustration shows a schematic diagram of accessing the XOR cache based on address interleaving units provided in an embodiment of this application.

[0222] exist Figure 21 In the XOR calculator, address interleaving unit 1 is... Figure 7 In the address interleaving unit, the XOR calculator provides the XOR cache address, and address interleaving unit 1 determines the memory bank address based on the XOR cache address, reading a row of data from the XOR cache. For example, the XOR cache address includes 16 bits (A15~A0), and address interleaving unit 1 generates a memory bank address based on {A15~A8} to provide to each memory bank in order to obtain the data block provided by each memory bank.

[0223] In RAID5 mode, address interleaving unit 2 (also known as bus address interleaving unit) maps a contiguous 2KB storage space on the bus address space to eight consecutive rows of data blocks in eight banks of the XOR cache. The way address interleaving unit 2 generates the addresses of each storage bank based on the XOR cache addresses is largely the same as the operation of address interleaving unit 1 described above.

[0224] In RAID 6 mode, Address Interleaving Unit 2 (also called Bus Address Interleaving Unit) maps a contiguous 2KB of storage space on the bus address space to 16 consecutive rows of data blocks across four banks of the XOR cache. For example, the XOR cache address consists of 16 bits (A15–A0), where the lower 11 bits (A10–A0) address the 2KB storage space, and the higher bits (A15–A11) identify an XOR cache cell. Address A11 determines whether the XOR cache cell to be accessed stores P-parity data or Q-parity data. For P-parity data, Address Interleaving Unit 2 selects Banks 0–Bank 3; for Q-parity data, it selects Banks 4–Bank 7. Addresses (A6, A5) determine one of the four banks to be accessed. Addresses (A10–A7) determine one of the data blocks within the selected bank (selecting the accessed data block from 16 data blocks). A data block size is 256 bytes, corresponding to addresses A4–A0; addresses A4–A0 do not need to be provided to the banks. It is understood that the above address allocation method is just an example, and there are many other address allocation methods.

[0225] In one alternative implementation, the data port width of the bus is, for example, 256 bits. For an access request to the 2KB storage space of the XOR cache unit, the address interleaving unit 2 for the bus generates 64 addresses and provides them sequentially to the XOR cache, reading 32 bytes of data (one data block) from the XOR cache each time using one address. See, for example, [link to relevant documentation]. Figure 21 The first address reads data block A0, and the second address reads data block A1. After reading data block A3, the next data block is the data block in bank0 that follows data block A0.

[0226] Optionally, a bus request to read the XOR cache can also describe 64 consecutive data blocks starting from data block A0, and the address interleaving unit 2 for the bus generates 64 addresses that are sequentially provided to the XOR cache.

[0227] As an alternative, a bus request to read the XOR cache can also describe a data block using addresses {A15-A0}. The address interleaving unit 2 for the bus uses A11 to determine whether to select Bank 0-3 or Bank 4-7, uses addresses (A6, A5) to determine one of the four banks to be accessed, and uses addresses (A10-A7) to determine the data block within the selected bank (the selection range is one of 16 data blocks belonging to the same XOR cache unit within that bank). Alternatively, addresses (A15-A12) can also be used to determine the data block within the selected bank (the selection range is one of multiple data blocks belonging to multiple XOR cache units within that bank).

[0228] It's important to understand that in RAID 6 mode, when accessing the XOR cache via the bus, the address interleaving unit 2 for the bus translates the bus address into the selected bank and the address for that bank, as described above. In RAID 5 mode, addresses (A7-A5) determine one of the eight banks to be accessed, and addresses (A10-A8) determine the data block within the selected bank (the selection range is one of eight data blocks within that bank belonging to the same XOR cache unit). Optionally, addresses (A15-A11) are also used to determine one of the data blocks within the selected bank (the selection range is one of multiple data blocks within that bank belonging to multiple XOR cache units).

[0229] By using address interleaving unit 2 to translate the bus address into the memory address for accessing the XOR cache in different ways in RAID5 and RAID6 modes, the 2KB XOR cache cells contained in the XOR cache appear to other bus devices as easily identifiable (e.g., contiguous) arranged in the bus address space. Thus, the bus address of each XOR cache cell can be directly determined by its index, and address interleaving unit 2 can locate the individual data blocks of the XOR cache cell based on the bus address. This easily identifiable arrangement is the same as how the XOR calculator accesses the XOR cache, thereby simplifying the addressing of XOR cache cells when different devices access the XOR cache in different RAID modes using a unified method.

[0230] Among them, for Figure 21 The address interleaving unit 2 provided in the embodiment can also be used for Figure 5 , Figure 10 , Figure 13 , Figure 15 In the corresponding embodiments, the bus address is converted into a memory address based on the address interleaving unit 2 for the bus, so as to access the corresponding data block based on the memory address.

[0231] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An XOR calculation unit, characterized in that, It includes an XOR calculator, an XOR cache, and an address interleaving unit, wherein the XOR cache includes M memory banks with a bit width of J; The address interleaving unit generates M memory addresses based on the XOR cache address and provides them to the M memory banks. The M memory banks of the XOR cache provide M*J data corresponding to a row of M data blocks. The M*J data comes from one XOR cache unit in RAID5 mode or from two XOR cache units in RAID6 mode. The size of the data block is equal to the bit width of the memory bank. The XOR calculator performs an XOR operation based on the M*J data and user data of the same bit width to generate intermediate state check data and write it back to the XOR cache. The intermediate state check data includes intermediate check data P that matches the RAID5 mode, or the intermediate check data includes intermediate check data P and intermediate check data Q that match the RAID6 mode. The XOR calculator determines the verification data P or a set of verification data including verification data P and verification data Q based on the XOR operation of K calculation cycles. Where M is an even number greater than 0, each calculation cycle corresponds to an XOR cache address, and the size of a single XOR cache unit is G; in RAID5 mode, the value of K is G / (M*J), and in RAID6 mode, the value of K is 2G / (M*J).

2. The XOR calculation unit according to claim 1, characterized in that, In different computation cycles, the XOR cache provides M data blocks in different rows; In RAID5 mode, the M data blocks originate from a single XOR cache unit; In RAID6 mode, M / 2 data blocks come from the first XOR cache unit, and the remaining M / 2 data blocks come from the second XOR cache unit; In the same calculation cycle, the M storage banks provide M*J data corresponding to a row of M data blocks based on the same storage bank address.

3. The XOR calculation unit according to claim 2, characterized in that, In RAID5 mode, the G / J data blocks corresponding to a single XOR cache unit are arranged sequentially in M ​​storage units according to their sequence numbers; In RAID6 mode, the G / J data blocks corresponding to each of the two XOR cache units are arranged sequentially in the M / 2 storage blocks they occupy.

4. The XOR calculation unit according to claim 3, characterized in that, In RAID5 mode, the G / J data blocks corresponding to a single XOR cache unit occupy consecutive G / (M*J) rows of data blocks in M ​​storage units according to their sequence numbers; In RAID6 mode, the G / J data blocks corresponding to each of the two XOR cache units occupy 2G / (M*J) rows of data blocks in the M / 2 storage units they occupy.

5. The XOR calculation unit according to any one of claims 1 to 4, characterized in that, The XOR calculator includes a first XOR unit, a second XOR unit, a first register, and a second register, all with a bit width of M*J / 2. The first XOR unit is connected to the first register, which stores data provided by a row of M / 2 data blocks. The first XOR unit performs an XOR operation based on the M*J / 2 bit wide user data and the M*J / 2 bit wide data provided by the first register. The second XOR unit is connected to the second register, which stores data provided from a row of remaining M / 2 data blocks. The second XOR unit performs an XOR operation based on the target data with a width of M*J / 2 bits and the data with a width of M*J / 2 bits provided by the second register. The target data is the product of the user data with a width of M*J / 2 bits and a preset constant.

6. The XOR calculation unit according to claim 5, characterized in that, The XOR calculator includes a selector, a multiplier, and a Ki register, the Ki register being used to store multiple Ki values; The first XOR unit is a first XOR calculation circuit, and the second XOR unit is a second XOR calculation circuit; In RDIA5 mode, the second XOR calculation circuit receives user data with a width of M*J / 2 bits; in RDIA6 mode, the second XOR calculation circuit receives the result of multiplying the user data with a width of M*J / 2 bits by the Galois domain constant Ki.

7. The XOR calculation unit according to claim 6, characterized in that, The XOR calculator also includes a third register and a fourth register; The third register and the first register are connected to the first XOR calculation circuit. The third register and the first register have the same bit width. The third register and the first register are used for data transfer and providing data for XOR operation at the same time, respectively. The fourth register and the second register are connected to the second XOR calculation circuit. The fourth register and the second register have the same bit width. The fourth register and the second register are used for data transfer and providing data for XOR operation at the same time, respectively.

8. The XOR calculation unit according to claim 7, characterized in that, One of the first register and the third register stores half of the data read from the XOR cache at one time, and one of the second register and the fourth register stores the other half of the data read from the XOR cache at one time; When the first register receives data provided by the XOR cache, the third register provides the first XOR calculation circuit with data to participate in the XOR operation; When the second register receives data provided by the XOR cache, the fourth register provides the second XOR calculation circuit with data to participate in the XOR operation; In RDIA5 mode, the first XOR calculation circuit outputs intermediate verification data P with a width of M*J / 2 bits through XOR operation, and the second XOR calculation circuit outputs intermediate verification data P with a width of M*J / 2 bits through XOR operation. The first XOR calculation circuit and the second XOR calculation circuit perform XOR operation based on different user data. In RDIA6 mode, the first XOR calculation circuit outputs intermediate parity data P with a width of M*J / 2 bits through XOR operation, and the second XOR calculation circuit outputs intermediate parity data Q with a width of M*J / 2 bits through XOR operation. The first XOR calculation circuit and the second XOR calculation circuit perform XOR operation based on the same user data.

9. The XOR calculation unit according to any one of claims 5 to 8, characterized in that, The XOR calculator includes a fifth register and a sixth register with a bit width of M*J, and both the fifth register and the sixth register are connected to the first XOR unit; The fifth register and the sixth register are used simultaneously for data transfer and to provide the first XOR unit with data to participate in the XOR operation.

10. A control component, characterized in that, It includes a media interface controller, which includes an XOR calculation unit as described in any one of claims 1 to 9.

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