High-bandwidth 3D die stack

Abstract

The examples described herein illustrate a technique for generating a three-dimensional (3D) die stack. The technique includes stacking a first die on top of a second die. The first die is offset from the second die in at least one of the x and y directions, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die. The technique further includes stacking a third die on top of the second die. The third die is offset from the second die in at least one of the x and y directions, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die.

Description

Technical Field

[0001] Examples of the present disclosure generally relate to integrated circuit (IC) devices, and more particularly, to high bandwidth 3D die stacks.

Background Art

[0002] Increasingly, high-performance computing applications are implementing integrated circuit (IC) packaging technologies that enable multiple dies to communicate within a single package. In one such technology (commonly referred to as "2.5D" IC packaging), multiple dies are coupled to an interposer that includes several metal layers for routing signals between the dies. These technologies are widely adopted by the industry but have many drawbacks.

Summary of the Invention

[0003] Techniques for generating three-dimensional (3D) die stacks. The techniques include stacking a first die on top of a second die. The first die is offset from the second die in at least one of the x and y directions, and a first routing sub-region of the first die is aligned with a second routing sub-region of the second die. The techniques further include stacking a third die on top of the second die. The third die is offset from the second die in at least one of the x and y directions, and a third routing sub-region of the third die is aligned with a fourth routing sub-region of the second die.

[0004] An example described herein is a 3D die stack. The 3D die stack includes a first die stacked on top of a second die. The first die is offset from the second die in at least one of the x and y directions, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die. The 3D die stack further includes a third die stacked on top of the second die. The third die is offset from the second die in at least one of the x and y directions, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die.

[0005] An example described herein is a computing system. The computing system includes memory and a 3D die stack coupled to the memory. The 3D die stack includes a first die stacked on top of a second die. The first die is offset from the second die in at least one of the x and y directions, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die. The 3D die stack further includes a third die stacked on top of the second die. The third die is offset from the second die in at least one of the x and y directions, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die. [Brief explanation of the drawing]

[0006] More detailed explanations of the features listed above, which are briefly summarized above, can be provided by referring to exemplary implementations, some of which are illustrated in the attached drawings. However, it should be noted that the attached drawings illustrate only typical exemplary implementations and should therefore not be considered limiting in scope. [Figure 1] This is a block diagram of an SoC, including a data processing engine array and programmable logic, as an example. [Figure 2]This is a block diagram of a data processing engine within a data processing engine array, as an example. [Figure 3A] This is a schematic cross-sectional view of a three-dimensional (3D) die stack including two PL die types, as an example. [Figure 3B] Figure 3A shows an exploded top view of the 3D die stack. [Figure 4] A schematic cross-sectional view of a 3D die stack containing a single programmable logic (PL) die type is shown as an example. [Figure 5] This shows the multiple logical sub-regions contained within each PL die. [Figure 6A] Schematic cross-sectional views of different 3D die stacks, including a first type of PL die and / or a second type of PL die, are shown with several examples. [Figure 6B] Schematic cross-sectional views of different 3D die stacks, including a first type of PL die and / or a second type of PL die, are shown with several examples. [Figure 6C] Schematic cross-sectional views of different 3D die stacks, including a first type of PL die and / or a second type of PL die, are shown with several examples. [Figure 6D] This section shows schematic cross-sectional views of different 3D die stacks, including various types of dies, using several examples. [Figure 6E] This section shows schematic cross-sectional views of different 3D die stacks, including various types of dies, using several examples. [Figure 6F] This section shows schematic cross-sectional views of different 3D die stacks, including various types of dies, using several examples. [Figure 6G] This section shows schematic cross-sectional views of different 3D die stacks, including various types of dies, using several examples. [Figure 6H] This section shows schematic cross-sectional views of different 3D die stacks, including various types of dies, using several examples. [Figure 6I] This section shows schematic cross-sectional views of different 3D die stacks, including various types of dies, using several examples. [Figure 6J]This section shows schematic cross-sectional views of different 3D die stacks, including various types of dies, using several examples. [Figure 6K] This section shows schematic cross-sectional views of different 3D die stacks, including various types of dies, using several examples. [Figure 6L] This section shows schematic cross-sectional views of different 3D die stacks, including various types of dies, using several examples. [Figure 6M] This section shows schematic cross-sectional views of different 3D die stacks, including various types of dies, using several examples. [Figure 6N] This section shows schematic cross-sectional views of different 3D die stacks, including various types of dies, using several examples. [Figure 6O] This section shows schematic cross-sectional views of different 3D die stacks, including various types of dies, using several examples. [Figure 7] This example demonstrates a technique for generating different types of heterogeneous dies by offsetting a single set of mask patterns. [Figure 8] The present invention demonstrates a technique for generating different types of dissimilar dies by offsetting a single set of mask patterns and cutting the resulting die along the x or y direction, following several examples. [Figure 9] The present invention demonstrates a technique for generating different types of dissimilar dies by offsetting a single set of mask patterns and cutting the resulting die along the x or y direction, following several examples. [Figure 10A] This example demonstrates a technique for generating large-scale 3D die stacks by offsetting a single set of mask patterns. [Figure 10B] This example demonstrates a technique for generating large-scale 3D die stacks by offsetting a single set of mask patterns. [Figure 10C] This example demonstrates a technique for generating large-scale 3D die stacks by offsetting a single set of mask patterns. [Figure 11]A flowchart of a method for generating a 3D die stack according to one example. [Figure 12] A flowchart of a method for generating a 3D die stack by stepping a set of mask patterns in an offset manner according to one example.

[0007] For ease of understanding, where possible, the same reference numbers are used to denote the same elements common to the drawings. It is contemplated that elements of one embodiment may be beneficially incorporated into other embodiments.

Best Mode for Carrying Out the Invention

[0008] Various features are described below with reference to the drawings. Note that the drawings may or may not be drawn to scale, and elements of similar structure or function are represented by like reference numerals throughout the drawings. Note that the drawings are intended only to facilitate the description of the features. They are not intended as an exhaustive description or as a limitation on the scope of the claims. Additionally, the illustrated examples need not have all of the aspects or advantages shown. Aspects or advantages described in connection with a particular embodiment are not necessarily limited to that embodiment and may be implemented in any other embodiment even if not so illustrated or explicitly described as such.

[0009] The examples in this specification describe techniques for generating high-bandwidth three-dimensional (3D) die stacks. In various embodiments, the high-bandwidth 3D die stack techniques disclosed herein can be implemented to connect dies in an offset manner such that an adjacent die (or any other die within the die stack) can communicate through one or more dies disposed in a layer located above and / or below the adjacent die. Each die can include 15+ metal layers, and the dies are connected to each other at a much finer pitch (e.g., a pitch of less than 10 microns) than conventional interposer techniques, so the lateral communication bandwidth between the dies is significantly increased. Further, the resulting 3D die stack is directly coupled to a PCB, eliminating the need for an interposer, and thus reducing the packaging size, cost, and complexity. In contrast, conventional techniques require an interposer to build products larger than a monolithic size. Conventional techniques that do not require an interposer typically utilize wires that cross unprocessed regions of the wafer (e.g., scribe) in wafer scale integration, which results in a reduction in bandwidth to enable stitching. <​​​​​​In one embodiment, DPE110 is identical; that is, each DPE110 (also called a tile or block) may have the same hardware components or circuits. Furthermore, the embodiments herein are not limited to DPE110. Alternatively, device 100 may include an array of any kind of processing elements; for example, DPE110 may be a digital signal processing engine, a cryptographic engine, a forward error correction (FEC) engine, or other specialized hardware for performing one or more special tasks.

[0012] In Figure 1, array 105 includes DPEs 110 of the same type (e.g., homogeneous array). However, in another embodiment, array 105 may include different types of engines. For example, array 105 may include a digital signal processing engine, a cryptographic engine, a graphics processing engine, and so on. Regardless of whether array 105 is homogeneous or heterogeneous, the DPEs 110 may include direct connections between DPEs 110, which allows the DPEs 110 to transfer data directly, as will be described in more detail below.

[0013] In one embodiment, DPE110 is formed from (i.e., hardened) software-configurable hardened logic. One advantage of doing so is that DPE110 can occupy less space within SoC100 compared to using programmable logic to configure hardware elements within DPE110. That is, using hardened logic circuits to configure hardware elements within DPE110, such as program memory, instruction fetch / decode units, fixed-point vector units, floating-point vector units, arithmetic logic unit (ALU), and multiplication accumulator (MAC), can significantly reduce the footprint of array 105 within SoC100. DPE110 may be hardened, but this does not mean that DPE110 is not programmable. That is, DPE110 can be configured when SoC100 is powered on or restarted to perform different functions or tasks.

[0014] The DPE array 105 also includes an SoC interface block 115 (also called a shim) that serves as a communication interface between the DPE 110 and other hardware components within the SoC 100. In this example, the SoC 100 includes a network-on-chip (NoC) 120 that is communicatively coupled to the SoC interface block 115. Although not shown, the NoC 120 may extend throughout the SoC 100 to enable various components within the SoC 100 to communicate with each other. For example, in one physical implementation, the DPE array 105 may be located in the upper right portion of the integrated circuit forming the SoC 100. However, using the NoC 120, the array 105 can communicate with, for example, the PL 125, the processor subsystem (PS) 130, the input / output (I / O) 135, or the memory controller (MC) 140, and may be located in different positions throughout the SoC 100.

[0015] In addition to providing an interface between the DPE 110 and the NoC 120, the SoC interface block 115 may also provide a direct connection to the communication fabric within the PL 125. In this example, some kernels in the dataflow graph may be assigned to the DPE 110 for execution, and other kernels may be assigned to the PL 125, so that the PL 125 and DPE 110 constitute a heterogeneous processing system. Figure 1 shows a heterogeneous processing system in an SoC, but in other examples, a heterogeneous processing system may include multiple devices or chips. For example, a heterogeneous processing system may include two FPGAs or other dedicated accelerator chips that are either the same type or different types. Furthermore, a heterogeneous processing system may include two communicably coupled SoCs.

[0016] In one embodiment, the SoC interface block 115 includes separate hardware components for communicatively coupling the DPE 110 to the NoC 120 and to a PL 125 located near array 105 within the SoC 100. In one embodiment, the SoC interface block 115 can stream data directly to a fabric for the PL 125. For example, the PL 125 may include an FPGA fabric from which the SoC interface block 115 can stream and receive data without using the NoC 120. That is, the circuit switching and packet switching described herein can be used to communicatively couple the DPE 110 to the SoC interface block 115 and to other hardware blocks within the SoC 100. In another example, the SoC interface block 115 may be implemented on a different die from the DPE 110. In yet another example, the DPE array 105 and at least one subsystem may be implemented on the same die, while other subsystems and / or other DPE arrays are implemented on other dies. Furthermore, the streaming interconnection and routing described herein with respect to the DPE 110 within the DPE array 105 can also be applied to data routed via the SoC interface block 115.

[0017] Figure 1 shows PL 125 as a single continuous block, but SoC 100 may include multiple blocks of PL 125 (also called logic sub-regions) that are adjacent to each other and / or located at different locations within SoC 100. Each logic sub-region (also called fabric sub-region) may include a set of constituent logic blocks (CLBs) that can include lookup tables (LUTs). In some embodiments, each logic sub-region is driven by a separate clock signal. In such embodiments, the logic sub-region may be called a “clock region”. PL 125 may include hardware elements that constitute a field-programmable gate array (FPGA). However, in other embodiments, SoC 100 may not include any PL 125, and for example, SoC 100 may be an application-specific integrated circuit (ASIC).

[0018] Figure 2 is a block diagram of a DPE 110 within the DPE array 105 shown in Figure 1, as an example. The DPE 110 includes an interconnect 205, a core 210, and a memory module 230. The interconnect 205 allows data to be transferred from the core 210 and the memory module 230 to different cores within the array 105. That is, the interconnects 205 in each of the DPEs 110 may be connected to each other so that data can be transferred north and south (e.g., up and down) and east and west (e.g., right and left) within the array of DPEs 110.

[0019] Referring back to Figure 1, in one embodiment, the DPE 110 in the upper row of array 105 relies on the interconnect 205 of the DPE 110 in the lower row to communicate with the SoC interface block 115. For example, to send data to the SoC interface block 115, the core 210 in the DPE 110 in the upper row sends data to its interconnect 205, which is then communicatively coupled to the interconnect 205 in the DPE 110 in the lower row. The interconnect 205 in the lower row connects to the SoC interface block 115. The process may also be reversed, where data intended for the DPE 110 in the upper row is first sent from the SoC interface block 115 to the interconnect 205 in the lower row, and then sent to the interconnect 205 in the upper row which is the target DPE 110. In this way, the DPE 110 in the upper row may send data to the SoC interface block 115 and rely on the interconnect 205 of the DPE 110 in the lower row to receive data from there.

[0020] In one embodiment, the interconnect 205 includes a configurable switching network that allows the user to determine how data is routed through the interconnect 205. In one embodiment, unlike a packet routing network, the interconnect 205 may constitute a streaming point-to-point connection. That is, streaming connections and streaming interconnects (not shown in Figure 2) within the interconnect 205 can constitute routes from the core 210 and memory module 230 to adjacent DPE 110 or SoC interface block 115. Once configured, the core 210 and memory module 230 can transmit and receive streaming data along those routes. In one embodiment, the interconnect 205 is configured using the Advanced Extensible Interface (AXI) 4 streaming protocol.

[0021] In addition to forming a streaming network, interconnect 205 may include a separate network for programming or configuring hardware elements within the DPE 110. Although not shown, interconnect 205 may include a memory-mapped interconnect with different connection and switch elements used to set values ​​in configuration registers within the DPE 110 that modify or set the functionality of the streaming network, core 210, and memory module 230.

[0022] In one embodiment, the streaming interconnect (or network) within interconnect 205 supports two different operating modes, referred to herein as circuit switching and packet switching. In one embodiment, both of these modes are part of or compatible with the same streaming protocol, e.g., the AXI streaming protocol. Circuit switching relies on a reserved point-to-point communication path between a source DPE 110 and one or more destination DPEs 110. In one embodiment, the point-to-point communication path used when performing circuit switching in interconnect 205 is not shared with other streams (whether those streams are circuit-switched or packet-switched). However, when transmitting streaming data between two or more DPEs 110 using packet switching, the same physical wire can be shared with other logical streams.

[0023] Core 210 may include hardware elements for processing digital signals. For example, Core 210 may be used to process signals related to wireless communication, radar, vector operations, machine learning applications, etc. Thus, Core 210 may include program memory, instruction fetch / decode units, fixed-point vector units, floating-point vector units, arithmetic logic units (ALUs), multiplication accumulators (MACs), etc. However, as stated above, this disclosure is not limited to DPE 110. The hardware elements within Core 210 may vary depending on the engine type; that is, the cores in a digital signal processing engine, a cryptographic engine, or an FEC may differ.

[0024] The memory module 230 includes a DMA engine 215, a memory bank 220, and a hardware synchronization circuit (HSC) 225 or other type of hardware synchronization block. In one embodiment, the DMA engine 215 enables data to be received by and transmitted to the interconnect 205. That is, the DMA engine 215 may be used to perform DMA reads and writes to the memory bank 220 using data received via the interconnect 205 from an SoC interface block or other DPE 110 in the array.

[0025] The memory bank 220 can contain any number of physical memory elements (e.g., SRAM). For example, the memory module 230 may contain different memory banks 220, such as 4, 8, 16, or 32. In this embodiment, the core 210 has a direct connection 235 to the memory bank 220. In other words, the core 210 can write data to or read data from the memory bank 220 without using the interconnect 205. That is, the direct connection 235 can be isolated from the interconnect 205. In one embodiment, one or more wires in the direct connection 235 connect the core 210 to a memory interface in the memory module 230, which is then connected to the memory bank 220.

[0026] In one embodiment, the memory module 230 also has a direct connection 240 to a core in an adjacent DPE 110. In other words, adjacent DPEs in the array can use the direct adjacency connection 240 to read data from or write data to the memory bank 220 without relying on their interconnection or the interconnection 205 shown in Figure 2. The HSC 225 may be used to manage or protect access to the memory bank 220. In one embodiment, before a core 210 or a core in an adjacent DPE can read data from or write data to the memory bank 220, the core (or DMA engine 215) requests the HSC 225 to acquire a lock when it wants to read from or write to the memory bank 220 (for example, when the core / DMA engine wants to "own" a buffer which is an allocated portion of the memory bank 220). If the core or DMA engine does not acquire a lock, the HSC 225 stalls (e.g., stops) the core or DMA engine from accessing the memory bank 220. When the core or DMA engine finishes buffering, they release the lock to the HSC 225. In one embodiment, the HSC 225 synchronizes the DMA engine 215 and the core 210 within the same DPE 110 (e.g., a memory bank 220 within one DPE 110 is shared between the DMA engine 215 and the core 210). Once writing is complete, the core (or DMA engine 215) can release the lock, allowing a core in an adjacent DPE to read the data.

[0027] High-bandwidth 3D die stack Increasingly, high-performance computing applications are implementing integrated circuit (IC) packaging techniques that allow multiple dies to communicate within a single package. In one such technique (commonly referred to as "2.5D" IC packaging), multiple dies are coupled to an interposer that includes several metal layers for routing signals between the dies. While these techniques are widely adopted by industry, they have many drawbacks.

[0028] For example, the microbumps implemented to mount dies to an interposer typically have a pitch of 50-150 microns, limiting the number of connections that can be formed between each die and the interposer for a given surface area. Furthermore, interposers generally contain only three metal layers compared to 15+ metal layers in a typical monolithic die. As a result, the communication bandwidth from each die to the interposer, and therefore the communication bandwidth between dies mounted to the interposer, is significantly reduced compared to the bandwidth available within each monolithic die, leading to a data routing bottleneck.

[0029] In various embodiments, the high-bandwidth 3D die stacking technology disclosed herein can be implemented to connect dies in an offset manner so that adjacent dies (or any other dies in the die stack) can communicate with each other via one or more dies located in layers above and / or below adjacent dies. Each die may contain 15+ layers of metal, and the dies are connected to each other at a much finer pitch (e.g., less than 10 microns) than conventional interposer technology, thus significantly increasing the lateral communication bandwidth between dies. In some embodiments, wafer-on-wafer stacking allows dies contained in each wafer to be connected vertically at an even finer pitch (e.g., less than 5 microns, such as less than 1 micron) to the technology for stacking dion dies or dion wafers, which can allow for pitches up to 10 microns. Furthermore, the resulting 3D die stack can be directly coupled to a PCB, eliminating the need for an interposer and thus reducing packaging size, cost, and complexity. Such technology is described in further detail below in conjunction with Figures 3A-3B, 4, 5, 6A-6L, and 7-12.

[0030] Figure 3A shows a schematic cross-sectional view of a three-dimensional (3D) die stack 300 including two PL die types, as an example. Figure 3B shows an exploded top view of the 3D die stack 300 of Figure 3A. The 3D die stack 300 includes a first type of PL die 310, a second type of PL die 312, a compute die 320, and an I / O die 330. The 3D die stack 300 may be electrically coupled to a PCB (not shown). In some embodiments, the compute die 320 includes any other associated circuitry included in the DPE array 105 and / or SoC 100 having one or more DPEs 110. The I / O die 330 may include any other associated circuitry included in the I / O 135 and / or SoC 100.

[0031] In various embodiments, each layer of the die may include a single wafer that forms a vertical connection via wafer-on-wafer bonding, or one or more layers of the die may consist of a single wafer, while one or more different layers may include separate, different dies that are bonded to the wafer via dion-wafer bonding rather than being part of a single wafer. For example, the layers of the compute die 320 may be formed on a single compute wafer 321, the layers of the I / O die 330 may be formed on a single I / O wafer 331, and the layers of the PL dies 310, 312 (e.g., the upper layer of PL die 312, the middle layer of PL die 310, and the lower layer of PL die 312) may be formed on a single PL wafer 311 (e.g., including a total of three PL wafers 311-1, 311-2, 311-3 in a 3D die stack 300). Figure 3B shows a rectangular wafer shape, but in various embodiments, the shape of each wafer may be any shape (e.g., circular). Furthermore, each wafer may include blank spaces (not shown) where no dies are manufactured.

[0032] Generally, the first type of PL die 310 and the second type of PL die 312 may contain similar types of circuitry, as described below with respect to the PL die 410 in Figures 4 and 5, but may be manufactured via different sets of mask patterns having different circuits, dimensions, and / or sizes. As will be further described below in relation to Figures 4 and 5, the logic sub-regions of each PL die 310, 312 may be vertically aligned with the logic sub-regions of other PL dies 310, 312 and / or the corresponding regions of the compute die 320 (314, 316). Figure 3A shows three layers of PL dies 310, 312, but any number of layers, each having any number of PL dies 310, 312, may be implemented within the 3D die stack 300.

[0033] As shown in the figure, the second type of PL die 312 has smaller dimensions than the first type of PL die 310. In some embodiments, this configuration allows the PL dies 310, 312 to be stacked on top of each other in an offset manner, enabling high-bandwidth communication through the PL dies 310, 312, while still aligning the edges of the dies 310, 312 along the perimeter of the 3D die stack 300. Such a configuration provides a more practical IC package design and avoids cutting the active silicon region of a given die. Such a configuration can also improve the yield of the 3D die stack 300 by providing additional redundancy to the layer containing the second type of PL die 312. For example, by connecting two or more PL dies 312 between each pair of PL dies 312 contained in a given layer, connectivity between two PL dies 312 can be maintained even if one of the PL dies 310 fails.

[0034] Figure 4 shows a schematic cross-sectional view of a 3D die stack 400 containing a single programmable logic (PL) die type, as an example. As shown, the 3D die stack 400 includes a PL die 410, a compute die 320, and an I / O die 330. Figure 4 shows three layers of the PL die 410, but any number of layers of the PL die 410 can be implemented within the 3D die stack 400.

[0035] In various embodiments, each layer of the die comprises a single wafer, and thus the 3D die stack 400 is formed via multiple wafer-on-wafer bonding processes (e.g., at a pitch of less than 5 microns, such as less than 1 micron). For example, the layers of the compute die 320 may be formed on a single compute wafer 321, the layers of the I / O die 330 may be formed on a single I / O wafer 331, and each layer of the PL die 410 may be formed on a single PL wafer 411 (e.g., including a total of three PL wafers 411-1, 411-2, 411-3 within the 3D die stack 400). In some embodiments, fewer layers than all of the die layers are formed from a single wafer. For example, one or more layers of the 3D die stack 400 may be formed from a single wafer, and one or more different layers may include separate, different dies that are bonded to the wafer via dion-wafer bonding, rather than being part of a single wafer. Figure 4 shows the interlayer gaps along the edges of the 3D die stack 400, but in various embodiments, the edges of each layer (e.g., the edges of each wafer) can be aligned so that the edges of the 3D die stack 400 are coplanar. For example, each wafer may include blank spaces (not shown) where dies are not manufactured, allowing the layer edges to be aligned.

[0036] As shown in Figure 5, each PL die 410 (and PL dies 310, 312, 610, 612, etc.) may include a plurality of logic sub-regions 412 (also referred to herein as “fabric sub-regions” or “clock regions”). In various embodiments, each PL die 410 (and PL dies 310, 312, 610, 612, etc.) may include programmable or configurable hardware elements (e.g., circuits). In one embodiment, a PL within a PL die (e.g., PL 125) includes a programmable logic fabric. The fabric may be part of a field-programmable gate array (FPGA). In one embodiment, the PL may be contiguous or discontinuous and may be located in a CLB (e.g., a programmable logic block) which may include programmable interconnects and lookup tables (LUTs).

[0037] The 3D die stack 400 includes multiple layers of PL dies 410, where a PL die 410 contained in a particular layer is offset in at least one of the x and y directions from a PL die 410 contained in a layer above or below that particular layer. In some embodiments, a first PL die 410-1 contained in a first layer is stacked on top of and offset from a second PL die 410-2 contained in a second layer located below the first layer, such that a vertical alignment 414 exists between a first logical sub-region 412 contained in the first PL die 410-1 and at least a portion of the second logical sub-region 412 contained in the second PL die 410-2. In addition, in some embodiments, the third PL die 410-3 included in the first layer is stacked on top of the second PL die 410-2 and offset from the second PL die 410-2 such that a vertical alignment 416 exists between the third logical sub-region 412-3 included in the third PL die 410-3 and at least a portion of the fourth logical sub-region 412-4 included in the second PL die 410-2. Although only two vertical alignment regions 414, 416 are shown in Figure 4 for clarity and ease of explanation, in various embodiments any number of vertical alignment regions may be implemented in any of the 3D die stacks described herein. For example, in some embodiments, each PL die 410 includes at least one logical sub-region 412 that is vertically aligned with the logical sub-regions 412 (or regions 422) in all PL dies 410 (or compute dies 320) coupled to the top or bottom of the PL die 410.

[0038] As shown in Figure 4, the PL die 410 contained in a particular layer is offset in the x-direction by half the die size from the PL die 410 contained in the layer above or below that particular layer. In some embodiments, some or all of the PL die 410 contained in a particular layer is also offset in the y-direction (e.g., by half the die size, by a quarter of the die size, etc.) from the PL die 410 contained in the layer above or below that particular layer. In other embodiments, the edges of some or all of the PL die 410 contained in a particular layer are aligned in the y-direction with the edges of the PL die 410 contained in the layer above or below that particular layer.

[0039] As described above, this configuration provides high-bandwidth connectivity between multiple PL dies 410, including adjacent PL dies 410 (e.g., a first PL die 410-1 and a third PL die 410-3). For example, a first routing sub-region (e.g., a first logical sub-region 412-1) may be pitch-matched to a second routing sub-region (e.g., a second logical sub-region 412-2), and high-density through-silicon vias (TSVs) included in the first logical sub-region 412-1 may be electrically connected to the second logical sub-region 412-2. Similarly, a third routing sub-region (e.g., a third logical sub-region 412-3) may be pitch-matched to a fourth routing sub-region (e.g., a fourth logical sub-region 412-4), and high-density through-silicon vias (TSVs) included in the third logical sub-region 412-3 may be electrically connected to the fourth logical sub-region 412-4. Therefore, a communication path is formed through the second PL die 410-2 to enable high-bandwidth lateral connectivity between the first PL die 410-1 and the third PL die 410-3.

[0040] In some embodiments, the region of programmable logic (e.g., FPGA circuitry) contained within each PL die 410 includes a regular, repeating circuit pattern that is substantially uniform across the region of the PL die 410. This regularity makes it possible to form high-density vertical connections (e.g., in the z-direction) between the PL dies 410. For example, the first PL die 410-1 and the third PL die 410-3 may include such regular, repeating circuits hybrid oxide-bonded to the corresponding circuitry on the second PL die 410-2. This hybrid oxide bonding (or similar technique for electrically connecting the PL dies) can be implemented with a pitch of less than 10 microns, e.g., less than 5 microns, e.g., less than 1 micron. Therefore, each PL die 410 may be smaller than the reticle size and may be manufactured with a single set of mask patterns, while the resulting 3D die stack 400 is significantly larger than the reticle size (e.g., 2x2 dies, 3x3 dies, 4x4 dies, 10x10 dies, wafer scale, or more), while still allowing inter-die connectivity with substantially the same or similar bandwidth as the communication bandwidth within the monolithic die.

[0041] In some embodiments, the 3D die stack 400 further includes one or more compute dies 320 positioned above (or below or between) one or more PL die 410 layers, and / or one or more I / O dies 330 positioned below (or above or between) one or more PL die 410 layers. For example, as shown in Figure 4, compute die 320-1 may be stacked on and offset from the first PL die 410-1 and the third PL die 410-3. Optionally, one or more layers of PL die 410 may be positioned between compute die 320-1 (or compute die 320) and the layers on which the first PL die 410-1 and the third PL die 410-3 are positioned, or compute die 320-1 (or compute die 320) may be directly stacked and directly bonded on the first PL die 410-1 and the third PL die 410-3.

[0042] To provide high-bandwidth connectivity between the compute die 320-1 and the PL die 410, a first region 422 of the compute die 320-1 (e.g., including programmable logic, routing circuits, FPGA circuits, NoC 120, etc.) may be aligned with a first routing sub-region (e.g., a first logic sub-region 412-1) and a second routing sub-region (e.g., a second logic sub-region 412-2). Similarly, a routing region 424 of the compute die 320-1 (e.g., including programmable logic, routing circuits, FPGA circuits, NoC 120, etc.) may be aligned with a third routing sub-region (e.g., a third logic sub-region 412-3) and a fourth routing sub-region (e.g., a fourth logic sub-region 412-4). Thus, one or more cores included in the compute die 320 (e.g., DPE 110) are provided with high-bandwidth connectivity to the PL die 410, the I / O die 330, and / or other compute dies 320.

[0043] As shown in Figure 4, the PL die 410 may be offset from one or more I / O dies 330 and stacked on top of them. This configuration provides high-bandwidth connectivity between any PL die 410 and any I / O die 330 (for example, via one or more PL dies 410). This configuration can further provide high-bandwidth connectivity between different I / O dies 330 (for example, via one or more PL dies 410).

[0044] In some embodiments, the communication redundancy provided by the configuration shown in Figure 4 allows the level of device functionality to be maintained even if one or more defective dies are included in the 3D die stack 400 (or any other 3D die stack configuration described herein). For example, if a portion of the second PL die 410-2 is defective, and that defect prevents the first PL die 410-1 stacked on top of the second PL die 410-2 from routing communication through the first PL die 410-1, the second PL die 410-2 can instead route communication between one or more different PL dies 410 in the layers above or below the second PL die 410. Thus, a 3D die stack with one or more defective dies can be remedied and instead placed in a lower market segment, improving the overall device yield.

[0045] Figures 6A to 6C show schematic cross-sectional views of different 3D die stacks 600, 602, and 604, including a first type PL die 610 and / or a second type PL die 612, by some example. As shown in Figures 6A and 6B, the second type PL die 612 may have a dimension in the x-direction that is half the corresponding dimension of the first type PL die 610. Thus, both the first type PL die 610 and the second type PL die 612 can be arranged in the same stack (e.g., in a 1:2 ratio) while still maintaining an overall length in the x-direction that is substantially the same as the overall length of an integer number of PL dies 610. As described above, each 3D die stack 600, 602, and 604 may include any number of vertically aligned regions (e.g., vertically aligned regions 614, 616) to enable high-bandwidth connectivity between the PL dies 610, 612, the compute die 320, and / or the I / O die 330.

[0046] In various embodiments, each layer of the die shown in Figures 6A to 6C may include a single wafer forming a vertical connection via wafer-on-wafer bonding, or one or more layers of the die may consist of a single wafer, while one or more different layers may include separate, different dies that are bonded to the wafer via dion-wafer bonding rather than being part of a single wafer. In addition, Figure 6C shows the gaps between layers along the edges of the 3D die stack 604, but in various embodiments, the edges of each layer (e.g., the edges of each wafer) may be aligned so that the edges of the 3D die stack 604 are coplanar. For example, each wafer may include blank spaces (not shown) where no dies are manufactured, allowing the edges of the layers to be aligned.

[0047] Figures 6D to 6O show schematic cross-sectional views of different 3D die stacks containing various types of dies, as shown in several examples. As shown in Figures 6D and 6E, a first layer 311-1 of CPU dies or GPU dies may be stacked on top of a second layer 311-2 of PL dies. Each 3D die stack 606, 608 may include any number of vertically aligned regions (e.g., vertically aligned regions 614, 616) where routing subregions containing CPU dies (or GPU dies) and PL dies are aligned, enabling high-bandwidth connectivity between the CPU dies (or GPU dies) and PL dies.

[0048] As shown in Figure 6F, the first layer 311-1 of the CPU die may be stacked on top of the second layer 311-2 of the GPU die. The 3D die stack 610 may include any number of vertically aligned regions in which routing subregions containing the CPU dies and GPU dies are aligned. For example, vertically aligned regions 614, 616 are included in the GPU die and enable high-bandwidth connectivity between the CPU die and the GPU die on which the CPU die is stacked via routing circuits 630 located within the vertically aligned regions 614, 616. Although not shown, each die included in a given 3D die stack (e.g., die stack 610) may include similar routing circuits 630 in vertically aligned regions (e.g., 614, 616) between dies located on different layers 311 of the 3D die stack.

[0049] Figures 6G to 6L show schematic cross-sectional views of different 3D die stacks, including different types of dies (e.g., CPU dies, GPU dies, SoC dies, PL dies, ASIC dies, I / O dies, compute dies, routing dies) stacked on top of layers 311-3 of memory dies, in several examples. In various embodiments, one or more dies included in a particular layer 311 of the 3D die stack may share one or more memory dies included in the layers of memory dies. Such a shared memory configuration enables faster and more efficient communication between dies included in the 3D die stack and allows the memory size allocated to one or more dies to be dynamically scaled in a more flexible manner. The memory dies may include any type of memory (e.g., DRAM, SRAM, or UltraRAM, also known as "URAM").

[0050] Figures 6M to 6O show schematic cross-sectional views of different 3D die stacks, including different types of dies (e.g., CPU dies, GPU dies, SoC dies, PL dies, ASIC dies, I / O dies, compute dies, routing) stacked above and / or below the routing layer 311, in several examples. In various embodiments, the routing layer 311 may include a wafer on which static metal connections, static connections with metals and transistors, and / or programmable interconnects are fabricated. In some embodiments, the routing may be a continuous structure formed on the wafer, or the routing may be formed as separate dies on the wafer, separated by an unprocessed area of ​​the wafer. Furthermore, in some embodiments, the routing may be formed within a portion of any other type of die, and / or the routing die (or a plurality of routing dies) may be included on a given wafer together with any other type of die. Figures 6M to 6O show specific combinations of dies, but in various embodiments, any combination of dies (e.g., CPU dies, GPU dies, SoC dies, PL dies, ASIC dies, I / O dies, compute dies) may be stacked on and / or below a given routing layer 311.

[0051] While a particular type of die is shown as being located in a specific layer 311 of a given 3D die stack, in various embodiments, any type of die may be included in any layer 311 of the 3D die stack. For example, a memory die is included in layer 311-3 of 3D die stacks 612, 614, 616, 618, 620, 622, and 628, but in other embodiments, a memory die may be included in layer 311-1 or 311-2, or any other layer of the 3D die stack. As shown in the figures, each type of die may include routing circuits 630 that enable high-bandwidth connectivity between the die and dies located above and / or below it. For example, as shown in Figures 6J, 6L, 6N, and 6O, the routing circuits 630 may provide high-bandwidth connectivity to dies and other routing both above and below the CPU die and the SoC die, respectively. The routing circuits 630 may be implemented in any other type of die described herein.

[0052] To clarify the explanation, the exemplary 3D die stacks shown in Figures 6D to 6I include only two layers of dies, and the exemplary 3D die stacks shown in Figures 6J to 6O include only three layers of dies. However, in various embodiments, a 3D die stack may include any number of layers having any type and / or combination of dies, including, but not limited to, PL dies, CPU dies, GPU dies, SoC dies, ASIC dies, memory dies, I / O dies, compute dies, routing dies, etc., and having any dimensions. For example, all layers included in a given 3D die stack shown in Figures 6D to 6O may include dies having the same dimensions, or one or more layers in a given 3D die stack shown in Figures 6D to 6O may include dies having different dimensions from the dies in the other layers of the 3D die stack. Each layer of the die shown in Figures 6D to 6O may include a single wafer that forms a vertical connection via wafer-on-wafer bonding, or one or more layers of the die may consist of a single wafer, while one or more different layers may include separate, distinct dies that are bonded to the wafer via dion wafer bonding, rather than being part of a single wafer.

[0053] Figure 7 illustrates, as an example, a technique for generating different types of heterogeneous dies by offsetting a single set of mask patterns. As shown, the first wafer 700 includes a set of first dies 710, each die 710 comprising sub-components including a set of sub-dies 720-1 to 720-4. Further shown, the second wafer 701 includes a set of second dies 711, each die 711 including the same set of sub-dies 720-1 to 720-4 in different configurations. In various embodiments, each sub-die 720, defined by a set of mask patterns, is an independent IC such as an SoC 100, a PL die 310, a compute die 320, or an I / O die 330. The first wafer 700 and the second wafer 701 are shown as having a rectangular shape for simplicity of illustration, but any wafer shape or size (e.g., circular) can be implemented. For example, the rectangular region of the die shown in Figures 7-9 and 10A may be part of a larger circular wafer not shown in Figures 7-9 and 10A.

[0054] In various embodiments, a first die set 710 is produced by stepping a set of mask patterns across a first wafer 700, starting from a first starting position, and a second die set 711 is produced by stepping the same set of mask patterns across a second wafer 701, starting from a second starting position offset from the first starting position in at least one of the x and y directions. In Figure 7, the positions where the set of mask patterns is stepped across each wafer 700, 701 are indicated by thicker vertical and horizontal lines. In some embodiments, a first die set 710 is produced by stepping a first mask set across a first wafer 700, and a second die set 711 is produced by stepping a second mask set across a second wafer 701, and the first and second mask sets contain substantially the same set of mask patterns. That is, in various embodiments, separate mask sets having the same set of mask patterns can be implemented.

[0055] As shown in Figure 7, the set of mask patterns can be stepped across the second wafer 701, starting from a second starting position offset 730 by approximately 2 / 3 of the total length of dies 710, 711 in the x-direction from a first starting position, and offset 732 by approximately 2 / 3 of the total length of dies 710, 711 in the y-direction from the first starting position. Thus, each of the dies 710 and 711 contains the same set of subdies 720, which are positioned differently from each other. As a result, when the wafer 701 containing the die 710 is stacked on top of the wafer 700 containing the die 711, and the bonded wafer stacks 700, 701 are cut, the resulting 3D die stack 739 includes one or more vertically aligned regions 714 where the subdies 720 positioned at different corners of the dies 711, 710 overlap, enabling high-bandwidth communication between the subdies 720 (e.g., by the hybrid oxide bonded logic subregions 312 and / or regions 322 contained within the subdies 720). In Figure 7, the lower subdies 720 included in the 3D die stack 739 are indicated by underlining the subdie numbers (e.g., 1, 2, 3, 4), and the boundaries between the lower subdies 720 are indicated by dotted lines.

[0056] Figures 8 and 9 illustrate techniques for generating different types of heterogeneous dies by offsetting a single set of mask patterns and cutting the resulting bonded wafer stack and / or die along the x or y direction, according to several examples. As shown in Figure 8, a third set of dies 712 is generated by stepping a set of mask patterns across wafer 702, starting from a starting position offset 734 in the x direction (e.g., by about two-thirds of the total length of dies 710, 712). The first wafer 700 and the second wafer 702 are then stacked on top of each other and bonded (e.g., via a hybrid oxide bond).

[0057] Next, the bonded wafer stack (including the first wafer 700 and the second wafer 702) is cut. For example, each die 710 can be cut along the outer boundary shown by the thick black line in Figure 8, and at the same time, wafer 702 can be cut to produce each die 712. In addition, each resulting die stack 710, 712 can be further cut along the inner horizontal boundary 750 of the set of mask patterns located between the subdies 720 contained in die 712, while each die 712 can be simultaneously cut along the inner horizontal boundary 752 of the set of mask patterns located between the subdies 720 contained in die 710 to produce two 3D die stacks 740, 742.

[0058] The 3D die stacks 740, 742 include vertically aligned regions 714 in which sub-dies 720 located on different sides of the die are arranged, enabling high-bandwidth communication between the sub-dies 720 (e.g., by hybrid oxide junction logic sub-regions 312 and / or region 322 contained within the sub-dies 720). In Figure 8, the lower sub-dies 720 contained within the 3D die stacks 740, 742 are indicated by underlining the sub-die numbers (e.g., 1, 2, 3, 4), and the boundaries between the lower sub-dies 720 are indicated by dotted lines.

[0059] As shown in Figure 9, the fourth die set 713 is produced by stepping a set of mask patterns across wafer 703, starting from a starting position 736 that is offset in the y-direction (for example, by about two-thirds of the total length of dies 710, 713). The first wafer 700 and the second wafer 703 are then stacked on top of each other and bonded.

[0060] Next, the bonded wafer stack (including the first wafer 700 and the second wafer 703) is cut. For example, each die 710 can be cut along the outer boundary shown by the thick black line in Figure 9, and at the same time, wafer 703 can be cut to produce each die 713. In addition, each resulting die stack 710, 713 can be further cut along the inner vertical boundary 754 of the set of mask patterns located between the subdies 720, while each die 713 can be simultaneously cut along the inner vertical boundary 756 of the set of mask patterns located between the subdies 720 contained in die 713 to produce two 3D die stacks 744, 746.

[0061] The 3D die stacks 744 and 746 include vertically aligned regions 714 in which sub-dies 720 located on different sides of the die overlap, enabling high-bandwidth communication between the sub-dies 720 (e.g., by hybrid oxide junction logic sub-regions 312 and / or region 322 contained within the sub-dies 720). In Figure 9, the lower sub-dies 720 included in the 3D die stacks 744 and 746 are indicated by underlining the sub-die number (e.g., 1, 2, 3, 4), and the boundaries between the lower sub-dies 720 are indicated by dotted lines.

[0062] Each of Figures 7 to 9 shows a 3D die stack containing only two different dies, but in various embodiments, each 3D die stack may contain any number of layers of different dies. For example, with respect to Figure 7, the 3D die stack 739 may contain multiple (e.g., 3, 4, 5, 8, 10, etc.) alternating layers of dies 710 and 711. In another example, the 3D die stack 739 may contain multiple layers containing the same die (e.g., 710), with different dies (e.g., 711) stacked on top of the multiple layers. Similar configurations can be implemented with respect to the 3D die stacks shown in Figures 8 and 9. Furthermore, while Figures 7 to 9 show wafers and dies cut along specific boundaries, in various embodiments, the cutting may be performed along any boundary located between subdies (e.g., an inner boundary defined by a set of mask patterns and / or an outer boundary defined by the perimeter of a set of mask patterns, shown in thick lines in Figures 7 to 9).

[0063] Figures 10A to 10C illustrate, by example, a technique for generating a large 3D die stack 1020 by offsetting a single set of mask patterns. As shown, the first wafer 1000 contains a first set of dies 1010, each die 1010 containing a set of four subdies 1005. As further shown, the second wafer 1002 contains a second set of dies 1010, each die 1010 containing the same set of subdies 1005. In various embodiments, each subdie 1005, defined by a set of mask patterns, is an independent IC such as an SoC 100, a PL die 310, a compute die 320, or an I / O die 330. The first wafer 1000 and the second wafer 1002 are shown having a rectangular shape for simplicity of illustration, but any wafer shape or size (e.g., circular) can be implemented. Furthermore, each die 1010 may contain any number of subdies 1005.

[0064] In various embodiments, a set of mask patterns is stepped across a first wafer 1000, starting from a first starting position, and stepped across a second wafer 1002, starting from a second starting position offset from the first starting position in at least one of the x and y directions (for example, offset by half the length of the sub-die 1005 contained in the die 1010). Furthermore, the set of mask patterns may be stepped across the second wafer 1002 such that gaps 1007 exist between sets 1012 of the die 1010 (for example, between each 2x2 set 1012 of the die 1010 containing a 4x4 sub-die 1005).

[0065] As shown in Figure 10B, the set of dies 1010 1012 is offset from the top of the dies 1010 contained in the first wafer 1000 and stacked on top of it. In some embodiments, the set of dies 1010 1012 is first cut from the second wafer 1002 and then stacked on top of the dies 1010 contained in the first wafer 1000 in the offset manner shown in Figure 10B. In other embodiments, the set of dies 1010 1012 is stacked on top of the dies 1010 contained in the first wafer 1000 by stacking the second wafer 1002 on top of the first wafer (or stacking the first wafer 1000 on top of the second wafer 1002).

[0066] The first wafer 1000 may be cut along a boundary 1030 either before or after stacking a set of dies 1010 1012 on top of the dies 1010 contained in the first wafer 1000 to produce the 3D die stack 1020 shown in Figure 10C. As shown in Figure 10C, the 3D die stack 1020 includes a lower layer having a set of 5×5 subdies 1005 1013 and an upper layer having a set of 4×4 subdies 1005 1012. The 3D die stack 1020 includes vertically aligned regions 1014 where the offset subdies 1010 overlap, enabling high-bandwidth communication between subdies 1005 and between adjacent dies 1005 (e.g., by hybrid oxide junction logic subregions 312 and / or regions 322 contained in the subdies 1005).

[0067] Figure 10C shows that each 3D die stack 1020 contains only two layers of dies 1010, but in various embodiments, each 3D die stack 1020 may contain any number of layers of dies 1010. For example, a 3D die stack 1020 may contain multiple (e.g., 3, 4, 5, 8, 10, etc.) alternating layers of sets 1013 of dies 1005 (e.g., 5x5 subdies 1010) from a first wafer 1000 and sets 1012 of dies 1005 (e.g., 4x4 subdies 1010) from a second wafer 1002. In another example, a 3D die stack 1020 may contain multiple layers (e.g., 3, 4, 5, etc.) of sets 1013 of dies 1010 aligned with each other, and sets 1012 of dies 1010 (e.g., 711) are stacked on top of the multiple layers. In such an embodiment, the offset between the set 1012 of die 1010 and the upper set 1013 of die 1010 enables high-bandwidth communication between the rows of subdies 1005 included in the set 1012 of die 1010 (e.g., via the vertical alignment region 1014).

[0068] Figure 11 is a flowchart of Method 1100 for generating a 3D die stack, as an example. For ease of explanation, Method 1100 will be described in conjunction with the 3D die stacks shown in Figures 1 to 6.

[0069] In block 1102, a first wafer (e.g., 311-2, 411-2) containing a first die (e.g., 310, 410, etc.) is stacked on a second wafer (e.g., 311-3, 411-3) containing a second die (e.g., 312, 410, etc.), and the first die is offset from the second die in at least one of the x and y directions. In some embodiments, the first wafer contains a plurality of first dies (e.g., 310, 410, etc.), and the second wafer contains a plurality of second dies (e.g., 312, 410, etc.).

[0070] In block 1104, a third wafer (e.g., 311-1, 411-1) containing a third die (e.g., 312, 410, etc.) is stacked on a first wafer, and the third die is offset from the first die in at least one of the x and y directions. In some embodiments, the third wafer contains a plurality of third dies (e.g., 312, 410, etc.).

[0071] In block 1106, a fourth wafer (e.g., 321) containing one or more dies (e.g., 320) is stacked on a third wafer, and each of the one or more dies is offset from the third die in at least one of the x and y directions. In some embodiments, the fourth wafer contains a plurality of compute dies (e.g., 320). Method 1100 can then be optionally repeated for several additional wafers containing, for example, PL dies, CPU dies, GPU dies, SoC dies, ASIC dies, compute dies, and / or I / O dies (e.g., 330).

[0072] Figure 12 is a flowchart of Method 1200 for generating a 3D die stack by stepping a set of mask patterns in an offset manner, as an example. For ease of explanation, Method 1200 will be described in conjunction with the 3D die stacks shown in Figures 7-9 and 10A-10C.

[0073] In block 1202, a set of mask patterns is stepped across a first wafer (e.g., 700) at a first set of locations. In block 1204, the set of mask patterns is stepped across a second wafer (e.g., 701, 702, 703) at a second set of locations offset from the first set of locations (e.g., by two-thirds of the die length, by half the die length, etc.).

[0074] In block 1206, the first wafer is stacked on top of the second wafer and bonded to the second wafer (e.g., via a hybrid oxide junction). In block 1208, the bonded wafer stack (including the first and second wafers) is cut along a first boundary (e.g., an outer boundary) corresponding to the outer periphery of a set of mask patterns (e.g., shown in bold in Figures 7-9) to generate a first die (e.g., 710), and simultaneously, the second wafer is cut along a second boundary defined within the set of mask patterns to generate second dies (e.g., 711, 712, 713), thereby generating a 3D die stack (e.g., 739, 740, 742, 744, 746). In some embodiments, the second boundary is an inner boundary defined within the set of mask patterns (e.g., 750, 752, 754, 756).

[0075] The embodiments presented in this disclosure are referenced above. However, the scope of this disclosure is not limited to the specific embodiments described. Rather, any combination of the features and elements described is intended to implement and practice the intended embodiments, whether or not they relate to different embodiments. Furthermore, while the embodiments disclosed herein may achieve advantages over other possible solutions or prior art, whether or not a particular advantage is achieved by a given embodiment does not limit the scope of this disclosure. Accordingly, the aforementioned aspects, features, embodiments, and advantages are merely illustrative and shall not be considered elements or limitations of the appended claims unless expressly enumerated in the claims.

[0076] As will be understood by those skilled in the art, the embodiments disclosed herein may be embodied as systems, methods, or computer program products. Accordingly, embodiments may take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments that combine software and hardware embodiments, all of which may be collectively referred to herein as “circuits,” “modules,” or “systems.” Furthermore, embodiments may take the form of computer program products embodied in one or more computer-readable media in which computer-readable program code is embodied.

[0077] Any combination of one or more computer-readable media may be used. A computer-readable media may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any preferred combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include electrical connections with one or more wires, portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any preferred combination thereof. In the context of this specification, a computer-readable storage medium is any tangible medium that can contain or store programs for use by, or in connection with, an instruction execution system, apparatus, or device.

[0078] A computer-readable signal medium may include, for example, a propagating data signal in which computer-readable program code is embodied, either in the baseband or as part of a carrier wave. Such a propagating signal may take any of a variety of configurations, including but not limited to electromagnetic, optical, or any preferred combination thereof. A computer-readable signal medium may be any computer-readable medium, rather than a computer-readable storage medium, that can communicate, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device.

[0079] Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, fiber optic cable, RF, or any preferred combination thereof.

[0080] Computer program code for performing the operations of the embodiments of this disclosure may be written in any combination of one or more programming languages, including, for example, object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the C programming language or similar programming languages. The program code may run entirely on the user's computer, partially as a standalone software package on the user's computer, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it may be connected to an external computer (for example, via the Internet using an Internet service provider).

[0081] Aspects of the present disclosure are described below with reference to the flowcharts and / or block diagrams of the methods, apparatus (systems), and computer program products according to the embodiments presented herein. It will be understood that each block in the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a general-purpose computer, a dedicated computer, or a processor of another programmable data processing device such that instructions executed via the processor of the computer or other programmable data processing device result in a machine that creates means for implementing the functions / actions specified in the blocks of the flowcharts and / or block diagrams.

[0082] These computer program instructions may also be stored in computer-readable storage media, and the instructions may also instruct computers, programmable data processing devices, and / or other devices to function in a particular manner, such as to generate products containing instructions that implement functions / actions specified in blocks of flowcharts and / or block diagrams.

[0083] Computer program instructions can also be loaded into a computer, other programmable data processing device, or other device to perform a series of operations on the computer, other programmable device, or other device, thereby generating a computer implementation process. Thus, instructions executed on a computer or other programmable device provide a process for implementing the functions / actions specified in the blocks of a flowchart and / or block diagram.

[0084] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described in a block may occur in a different order than shown in the figure. For example, two consecutively shown blocks may actually be executed substantially simultaneously, or blocks may be executed in reverse order depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs a specified function or action or a combination of dedicated hardware and computer instructions. [Examples]

[0085] The technology disclosed above may be represented in the following non-limiting embodiments.

[0086] Example 1. A method for generating a three-dimensional (3D) die stack, comprising: stacking a first die on top of a second die, wherein the first die is offset from the second die in at least one of the x and y directions, and the first routing sub-region of the first die is aligned with the second routing sub-region of the second die; and stacking a third die on top of the second die, wherein the third die is offset from the second die in at least one of the x and y directions, and the third routing sub-region of the third die is aligned with the fourth routing sub-region of the second die.

[0087] Example 2. The method according to Example 1, wherein the first routing sub-region of the first die communicates with the third routing sub-region of the third die via the second and fourth routing sub-regions.

[0088] Example 3. The method according to Example 2, wherein the first die does not communicate directly with the third die.

[0089] Example 4. The method according to Example 1, wherein the first die, the second die, and the third die include programmable logic (PL), and the first routing sub-region, the second routing sub-region, the third routing sub-region, and the fourth routing sub-region include a fabric sub-region.

[0090] Example 5. The method according to Example 1, further comprising stacking a fourth die on a first die and a third die, wherein a fifth routing sub-region of the fourth die is aligned with at least a portion of the second routing sub-region of the second die, a sixth routing sub-region of the fourth die is aligned with at least a portion of the fourth routing sub-region of the second die, the fifth routing sub-region of the fourth die communicates with the second routing sub-region via the first routing sub-region of the first die, and the sixth routing sub-region of the fourth die communicates with the fourth routing sub-region via the third routing sub-region of the third die.

[0091] Example 6. The method according to Example 1, further comprising stacking a second die on an input / output (I / O) die, wherein the second die is offset from the I / O die in at least one of the x and y directions, and a fifth routing sub-region of the I / O die is aligned with a second routing sub-region of the second die.

[0092] Example 7. The method according to Example 1, wherein the first die, second die, and third die include at least one of the following: a central processing unit (CPU) die, a graphics processing unit (GPU) die, a programmable logic (PL) die, a system-on-a-chip (SoC) die, an application-specific integrated circuit (ASIC) die, and a memory die.

[0093] Example 8. The method according to Example 7, wherein one or more die layers are arranged between the first die and the second die.

[0094] Example 9. The method according to Example 1, wherein stacking a first die on a second die includes hybrid oxide bonding a first wafer having the first die to a second wafer having the second die, and stacking a third die on a second die includes hybrid oxide bonding a third wafer having the third die to a second wafer.

[0095] Example 10. The method according to Example 1, wherein the dies are contained in a first wafer containing a first plurality of dies, the second dies are contained in a second wafer containing a second plurality of dies, each die contained in the first plurality of dies is offset from each die contained in the second plurality of dies in at least one of the x and y directions, and at least one routing sub-region of each die contained in the first plurality of dies is aligned with at least one routing sub-region of the dies contained in the second plurality of dies.

[0096] Example 11. The method according to Example 1, wherein the pitch of the electrical connections between (i) the bottom of the first die and the top of the second die, and (ii) the bottom of the third die and the top of the second die is less than 5 microns.

[0097] Example 12. The method according to Example 1, wherein the first routing sub-region includes a first field-programmable gate array (FPGA) fabric, the second routing sub-region includes a second FPGA fabric, the third routing sub-region includes a third FPGA fabric, and the fourth routing sub-region includes a fourth FPGA fabric.

[0098] Example 13. A three-dimensional (3D) die stack, A three-dimensional (3D) die stack comprising: a first die stacked on top of a second die, the first die being offset from the second die in at least one of the x and y directions, and a first routing sub-region of the first die aligning with a second routing sub-region of the second die; and a third die stacked on top of the second die, the third die being offset from the second die in at least one of the x and y directions, and a third routing sub-region of the third die aligning with a fourth routing sub-region of the second die.

[0099] Example 14. The 3D die stack according to Example 13, wherein the first routing sub-region of the first die communicates with the third routing sub-region of the third die via the second and fourth routing sub-regions.

[0100] Example 15. The 3D die stack described in Example 14, wherein the first die does not communicate directly with the third die.

[0101] Example 16. The 3D die stack according to Example 13, wherein the first die, the second die, and the third die include programmable logic (PL), and the first routing sub-region, the second routing sub-region, the third routing sub-region, and the fourth routing sub-region include a fabric sub-region.

[0102] Example 17. The 3D die stack according to Example 13, wherein the first die, second die, and third die include at least one of the following: a central processing unit (CPU) die, a graphics processing unit (GPU) die, a programmable logic (PL) die, a system-on-a-chip (SoC) die, an application-specific integrated circuit (ASIC) die, and a memory die.

[0103] Example 18. The 3D die stack according to Embodiment 17, wherein one or more die layers are arranged between a first die and a second die.

[0104] Example 19. A 3D die stack according to Example 13, wherein the first die is contained in a first wafer containing a plurality of first dies, the second die is contained in a second wafer containing a plurality of second dies, each die contained in the first plurality of dies is offset from each die contained in the second plurality of dies in at least one of the x and y directions, and at least one routing sub-region of each die contained in the first plurality of dies is aligned with at least one routing sub-region of a die contained in the second plurality of dies.

[0105] Example 20. A computing system comprising a memory and a three-dimensional (3D) die stack coupled to the memory, wherein the three-dimensional (3D) die stack comprises a first die stacked on a second die, the first die being offset from the second die in at least one of the x and y directions, and the first routing sub-region of the first die being aligned with the second routing sub-region of the second die, and a third die stacked on the second die, the third die being offset from the second die in at least one of the x and y directions, and the third routing sub-region of the third die being aligned with the fourth routing sub-region of the second die.

[0106] The above applies to specific examples, but other and further examples may be devised without departing from the basic scope, and the scope will be determined by the following "Claims".

Claims

1. A method for generating a three-dimensional (3D) die stack, The invention involves stacking a first die on a second die, wherein the first die is offset from the second die in at least one of the x and y directions, and the first routing sub-region of the first die is aligned with the second routing sub-region of the second die. A method comprising stacking a third die on top of the second die, wherein the third die is offset from the second die in at least one of the x and y directions, and a third routing sub-region of the third die is aligned with a fourth routing sub-region of the second die.

2. The method according to claim 1, wherein the first routing sub-region of the first die communicates with the third routing sub-region of the third die via the second routing sub-region and the fourth routing sub-region.

3. The method according to claim 1 or 2, wherein the first die does not communicate directly with the third die.

4. The method according to any one of claims 1 to 3, wherein the first die, the second die, and the third die are equipped with programmable logic (PL), and the first routing sub-region, the second routing sub-region, the third routing sub-region, and the fourth routing sub-region are equipped with a fabric sub-region.

5. The method according to any one of claims 1 to 4, further comprising stacking a fourth die on the first die and the third die, wherein a fifth routing sub-region of the fourth die is aligned with at least a portion of the second routing sub-region of the second die, a sixth routing sub-region of the fourth die is aligned with at least a portion of the fourth routing sub-region of the second die, the fifth routing sub-region of the fourth die communicates with the second routing sub-region of the first die via the first routing sub-region of the first die, and the sixth routing sub-region of the fourth die communicates with the fourth routing sub-region of the third die via the third routing sub-region of the third die.

6. The method according to any one of claims 1 to 5, wherein the first die, the second die, and the third die include at least one of a central processing unit (CPU) die, a graphics processing unit (GPU) die, a programmable logic (PL) die, a system-on-a-chip (SoC) die, an application-specific integrated circuit (ASIC) die, and a memory die.

7. The method according to any one of claims 1 to 6, wherein stacking the first die on the second die includes hybrid oxide bonding a first wafer having the first die to a second wafer having the second die, and stacking the third die on the second die includes hybrid oxide bonding a third wafer having the third die to the second wafer.

8. The method according to any one of claims 1 to 7, wherein the first die is included in a first wafer including a first plurality of dies, the second die is included in a second wafer including a second plurality of dies, each die included in the first plurality of dies is offset from each die included in the second plurality of dies in at least one of the x-direction and the y-direction, and at least one routing sub-region of each die included in the first plurality of dies is aligned with at least one routing sub-region of a die included in the second plurality of dies.

9. The method according to any one of claims 1 to 8, wherein the pitch of the electrical connections between the bottom of the first die and the top of the second die, and between the bottom of the third die and the top of the second die is less than 5 microns.

10. The method according to any one of claims 1 to 9, wherein the first routing sub-region comprises a first field-programmable gate array (FPGA) fabric, the second routing sub-region comprises a second FPGA fabric, the third routing sub-region comprises a third FPGA fabric, and the fourth routing sub-region comprises a fourth FPGA fabric.

11. It is a three-dimensional (3D) die stack, A first die stacked on a second die, wherein the first die is offset from the second die in at least one of the x and y directions, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die, and A three-dimensional (3D) die stack comprising: a third die stacked on top of the second die, the third die being offset from the second die in at least one of the x and y directions, and a third routing sub-region of the third die aligning with a fourth routing sub-region of the second die.

12. The 3D die stack according to claim 11, wherein the first routing sub-region of the first die communicates with the third routing sub-region of the third die via the second routing sub-region and the fourth routing sub-region.

13. The 3D die stack according to claim 11 or 12, wherein the first die does not communicate directly with the third die.

14. The 3D die stack according to any one of claims 11 to 13, wherein the first die, the second die, and the third die include at least one of a central processing unit (CPU) die, a graphics processing unit (GPU) die, a programmable logic (PL) die, a system-on-a-chip (SoC) die, an application-specific integrated circuit (ASIC) die, and a memory die.

15. The 3D die stack according to any one of claims 11 to 14, wherein the first die is included in a first wafer including a first plurality of dies, the second die is included in a second wafer including a second plurality of dies, each die included in the first plurality of dies is offset from each die included in the second plurality of dies in at least one of the x-direction and the y-direction, and at least one routing sub-region of each die included in the first plurality of dies is aligned with at least one routing sub-region of a die included in the second plurality of dies.

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