Semiconductor packages

Abstract

We provide a sufficiently miniaturized semiconductor package suitable for smart glasses. [Solution] The semiconductor package of the present invention includes a substrate 120, a molded layer 130, a plurality of semiconductor chips, and a plurality of solder balls 190. The plurality of semiconductor chips are arranged on the upper surface of the substrate, the molded layer is formed on the substrate and covers the plurality of semiconductor chips, the edge of the molded layer is flush with the edge of the substrate, and the plurality of solder balls are formed on the lower surface of the substrate. The semiconductor package of the present invention has a length of 6.5 mm to 7.0 mm, a width of 5.5 mm to 7.0 mm, and a thickness of 0.35 mm to 0.8 mm. When the semiconductor package of the present invention is used in smart glasses, its small size allows for more space to be secured for adding other components inside the glasses, and its thinness allows for an increase in the battery capacity of the glasses.

Description

Technical Field

[0001] The present invention relates to a semiconductor package, and particularly to a semiconductor package for a small-sized embedded multimedia card.

Background Art

[0002] An embedded multimedia card (eMMC) is a standard specification for built-in memory formulated by the JEDEC Association for smartphones. The eMMC format package is composed of an MMC interface, flash memory, and a controller. This solution can significantly reduce the circuit board area occupied by components and has become the mainstream built-in memory in smartphones.

[0003] However, the minimum size of the current eMMC format package is limited to about 7.2×7.2 mm. When used in smart glass, there is a problem that the available space inside the glass is reduced.

Summary of the Invention

Problems to be Solved by the Invention

[0004] In view of the above problems, an object of the present invention is to provide a sufficiently miniaturized semiconductor package suitable for smart glass.

Means for Solving the Problems

[0005] To achieve the above object, the semiconductor package of the present invention includes a substrate, a molding layer, a plurality of semiconductor chips, and a plurality of solder balls. The plurality of semiconductor chips are disposed on the upper surface of the substrate. The molding layer is formed on the substrate and covers the plurality of semiconductor chips. The edge of the molding layer is aligned flush with the edge of the substrate. The plurality of solder balls are formed on the lower surface of the substrate. The length of the semiconductor package is 6.5 mm to 7.0 mm, and the width is 5.5 mm to 7.0 mm.

[0006] In the above embodiment, the thickness of the semiconductor package is preferably 0.35 mm to 0.8 mm.

[0007] In the above embodiment, it is preferable that the plurality of semiconductor chips include flash memory and a controller.

[0008] In the above embodiment, it is preferable that the flash memory is electrically connected to the substrate via a plurality of bonding wires.

[0009] In the above embodiment, it is preferable that the controller is positioned above the flash memory and electrically connected to the substrate. [Effects of the Invention]

[0010] When the semiconductor package of this invention is used in smart glasses, its miniaturization allows for space to be allocated for other components, and its reduced thickness allows for an increase in battery capacity. [Brief explanation of the drawing]

[0011] [Figure 1] This is a schematic cross-sectional view of the semiconductor package of the present invention. [Figure 2] This is a plan view of the semiconductor package of the present invention. [Figure 3] This is a bottom view of the semiconductor package of the present invention. [Modes for carrying out the invention]

[0012] Embodiments of the present invention will be described in detail below with reference to the attached drawings. In the drawings, identical components are denoted by the same reference numerals. Several different embodiments are shown below to illustrate the embodiments of this specification. In the following description, specific examples of components and their arrangements are provided for brevity and are not intended to limit the content of this specification. Furthermore, this specification uses relative positional expressions such as "up" and "down" based on the illustrated direction, but these should be interpreted appropriately depending on the installation direction of the device.

[0013] The following describes how the present invention can be implemented. The following disclosure provides many different embodiments or examples for implementing different features of this specification. For the sake of brevity of this disclosure, specific examples of members and configurations are described below. Naturally, these members and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming the first member above or on top of the second member may include embodiments in which the first member and the second member are formed in direct contact, and may also include embodiments in which an additional member is formed between the first member and the second member so that the first member and the second member are not in direct contact. Furthermore, in various examples of this disclosure, reference numbers and / or letters may be repeated. This repetition is for simplification and clarity and does not in itself indicate relationships between the various embodiments and / or configurations being discussed.

[0014] Furthermore, for the purpose of brevity and clarity, the same reference numerals may be used repeatedly for identical or similar components, but this does not indicate a relationship between each embodiment or component. In addition, spatially relative terms such as "down," "bottom," "up," and "top" may be used to describe the relative positional relationship between one component and another as shown in the drawings, but these spatially relative terms are not limited to the directions shown in the drawings, but should be interpreted to include different directions during use or operation of the device. For example, the device may be oriented in other ways (90-degree rotation or other orientations), and the spatially relative descriptions used herein should be interpreted accordingly.

[0015] Referring to FIGS. 1 to 3, the semiconductor package of the present invention includes a package body 110 and a plurality of solder balls 190. Here, the package body 110 refers to a structure including a substrate 120 and a molding layer 130 that constitute the semiconductor package.

[0016] Specifically, a plurality of electronic components are provided inside the package body 110, including at least a plurality of semiconductor chips and a plurality of passive components 143.

[0017] The plurality of semiconductor chips are disposed on the upper surface of the substrate 120 and sealed within the molding layer 130.

[0018] In the present invention, the plurality of semiconductor chips can include a flash memory 141 and a controller 142.

[0019] The flash memory 141 is electrically connected to the substrate 120 via a plurality of bonding wires 148. The controller 142 is disposed above the flash memory 141 and is electrically connected to the substrate 120.

[0020] The plurality of passive components 143 are disposed on the substrate 120 and sealed within the molding layer 130.

[0021] The molding layer 130 is formed of a resin material for sealing and is formed on the upper surface of the substrate 120. The substrate 120 has a rectangular structure, and the molding layer 130 has a cuboid structure, and its edges are aligned flush with the edges of the substrate 120.

[0022] The package body 110 is composed of at least a flash memory 141, a controller 142, a plurality of passive components 143, a substrate 120, and a molding layer 130.

[0023] The shape of the package body 110 is determined by the combination of the substrate 120 and the molding layer 130.

[0024] The package body 110 has a rectangular parallelepiped structure and has an upper surface 150, a lower surface 160, and four side surfaces 170. In FIG. 1, only two of the side surfaces 170 are shown.

[0025] The upper surface 150 of the package body 110 is located on the upper surface of the molding layer 130, and the lower surface 160 of the package body 110 is located on the lower surface of the substrate 120.

[0026] The plurality of solder balls 190 are formed on the lower surface 160 of the package body 110 according to a predetermined arrangement method. That is, the plurality of solder balls 190 are arranged on the lower surface of the substrate 120.

[0027] The plurality of solder balls 190 are electrically connected to the plurality of semiconductor chips via the substrate 120. Thereby, the plurality of semiconductor chips can be electrically connected to an external circuit via the plurality of solder balls 190.

[0028] The upper surface 150 of the package body 110 is rectangular, has two long sides 151 and two short sides 152, and is connected to the four side surfaces 170 of the package body 110. The two long sides 151 have the same length and are parallel to each other, and the two short sides 152 also have the same length and are parallel to each other, and are orthogonal to the long sides 151.

[0029] The lower surface 160 of the package body 110 is disposed opposite to the upper surface 150, and its shape and dimensions are the same as those of the upper surface 150.

[0030] The lower surface 160 of the package body 110 is also rectangular, has two long sides 161 and two short sides 162, and is connected to the four side surfaces 170 of the package body 110. The two long sides 161 have the same length and are parallel to each other, and the two short sides 162 also have the same length and are parallel to each other, and are orthogonal to the long sides 161.

[0031] The semiconductor package of this invention has a length of 6.5 mm to 7.0 mm, that is, the lengths of the long sides 151 and 161 are 6.5 mm to 7.0 mm.

[0032] The semiconductor package of this invention has a width of 5.5 mm to 7.0 mm, that is, the lengths of the short sides 152 and 162 are 5.5 mm to 7.0 mm.

[0033] The semiconductor package of this invention has a thickness of 0.35 mm to 0.8 mm.

[0034] Specifically, referring to Figure 1, when the semiconductor package of the present invention is placed on a plane 195 and the plurality of solder balls 190 are in direct contact with the plane 195, the distance D from the upper surface 150 of the package body 110 to the plane 195 becomes the thickness of the semiconductor package of the present invention.

[0035] When the semiconductor package of this invention is used in smart glasses, its miniaturization allows for space to be secured for other components, and its reduced thickness allows for an increase in battery capacity.

[0036] Although the present invention has been described above based on the embodiments described herein, it is not limited thereto. Any person with ordinary skill in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Accordingly, the scope of protection of the present invention shall be defined by the claims for utility model registration described below. [Explanation of symbols]

[0037] 110: Package body 120: Circuit board 130: Molding layer 141: Flash memory 142: Controller 143: Passive components 148: Bonding wire 150:Top surface 151: Long side 152: Short side 160: Bottom surface 161: Long side 162: Short side 170: Side view 190: Solder ball 195: Plane D: Distance

Claims

1. A semiconductor package comprising a substrate, a molded layer, multiple semiconductor chips, and multiple solder balls, The plurality of semiconductor chips are arranged on the upper surface of the substrate. The molded layer is formed on the substrate and covers the plurality of semiconductor chips. The edge of the molded layer is aligned flush with the edge of the substrate. The plurality of solder balls are formed on the lower surface of the substrate, A semiconductor package characterized in that the length of the semiconductor package is 6.5 mm to 7.0 mm and the width is 5.5 mm to 7.0 mm.

2. The semiconductor package according to claim 1, characterized in that the thickness of the semiconductor package is 0.35 mm to 0.8 mm.

3. The semiconductor package according to claim 1, characterized in that the plurality of semiconductor chips include flash memory and a controller.

4. The semiconductor package according to claim 3, characterized in that the flash memory is electrically connected to the substrate via a plurality of bonding wires.

5. The semiconductor package according to claim 4, characterized in that the controller is positioned above the flash memory and electrically connected to the substrate.

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