Display device

Abstract

To improve performance of a display device.SOLUTION: A peripheral wiring area PFWA of a display device DSP1 includes an insulation layer 31 on a substrate 10, a wiring layer WL1 on the insulation layer 31, an insulation layer 32 that is on the insulation layer 31 and covers the wiring layer WL1, and a wiring layer WL2 on the insulation layer 32. The wiring layer WL1 is arranged with a plurality of video signal wiring lines VSW. The wiring layer WL2 is formed with a plurality of touch detection wiring lines TDW and conductor patters CCP supplied with a fixed potential that are disposed in a matrix shape in an X direction and a Y direction. The conductor patterns CCP are arranged at positions where they overlap portions of the plurality of video signal wiring lines VSW, and are capacitively coupled with the portions of the plurality of video signal wiring lines VSW.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to display device technology. [Background technology]

[0002] Patent Document 1 (JP 2018-132606 A) describes a structure in which a mesh-shaped shielding section is arranged above a sensor power supply line as a measure against noise caused by high-frequency pulses for touch sensing. Patent Document 2 (JP 2019-39985 A) describes a structure in which a shielding layer made of the same material as the transparent electrodes is arranged above a plurality of connection lines connected to a signal selection circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-132606 A [Patent Document 2] JP 2019-39985 A Summary of the Invention [Problem to be solved by the invention]

[0004] Display devices may be used as portable terminal devices equipped with wireless communication functions between external devices. In the case of display devices equipped with wireless communication functions, if electromagnetic waves generated by switching operations for inputting signals for the display function interfere with the band of wireless communication, they will become noise for wireless communication. For this reason, technology is needed to suppress the generation of electromagnetic waves that are a source of noise.

[0005] An object of the present invention is to provide a technique for improving the performance of a display device. [Means for solving the problem]

[0006] A display device according to one embodiment of the present invention has a first substrate having a first side extending in a first direction and a second side opposite to the first side in a second direction perpendicular to the first direction, a display area between the first side and the second side in the second direction, a plurality of touch detection electrodes arranged in a matrix in the first direction and the second direction in the display area, a switch circuit area between the first side and the display area in the second direction and in which a signal selection circuit is arranged, a peripheral wiring area between the first side and the switch circuit area in the second direction and in which a plurality of peripheral wirings are arranged, the peripheral wirings including a plurality of video signal wirings connected to the signal selection circuit and a plurality of touch detection wirings connected to the plurality of touch detection electrodes, and a terminal area between the first side and the peripheral wiring area in the second direction and in which a plurality of terminals electrically connected to the plurality of peripheral wirings are arranged. The peripheral wiring region includes a first insulating layer on the first substrate, a first wiring layer on the first insulating layer, a second insulating layer on the first insulating layer and covering the first wiring layer, and a second wiring layer on the second insulating layer. The first wiring layer has the video signal wirings arranged thereon. The second wiring layer has the touch detection wirings and a conductor pattern to which a first potential is supplied. The conductor pattern is arranged at a position overlapping with a portion of the video signal wirings and is capacitively coupled to the portion of the video signal wirings. In the display region, the touch detection electrodes are formed on the second insulating layer. [Brief description of the drawings]

[0007] [Figure 1] 1 is a plan view of a display surface side showing an example of a display device according to an embodiment; [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] 2 is a circuit diagram showing an example of a circuit configuration around a pixel included in the display device shown in FIG. [Figure 4] 3 is an enlarged cross-sectional view of a display area of ​​the display device shown in FIG. 2. [Diagram 5]2 is a plan view showing an example of the layout of a common electrode (touch detection electrode) included in the display device shown in FIG. [Figure 6] 2 is an explanatory diagram illustrating an example of the operation of a signal selection circuit arranged in a switch circuit region shown in FIG. 1. [Figure 7] 2 is an enlarged cross-sectional view showing an example of a noise countermeasure in the peripheral wiring region shown in FIG. [Figure 8] FIG. 2 is an enlarged plan view of part B shown in FIG. [Figure 9] 9 is an enlarged plan view showing a modification of a portion of the wiring region shown in FIG. 8. FIG. [Figure 10] 9 is an enlarged plan view showing a modification of another part of the wiring region shown in FIG. 8. FIG. [Figure 11] FIG. 11 is an enlarged plan view showing a study example for FIG. 10. [Figure 12] FIG. 8 is an enlarged cross-sectional view showing a modification of FIG. 7. [Figure 13] FIG. 8 is an enlarged cross-sectional view showing another modified example of FIG. 7. [Figure 14] FIG. 8 is an enlarged cross-sectional view showing another modified example of FIG. 7. [Figure 15] 11 is an enlarged plan view showing a modified example of a plurality of video signal lines shown in FIG. [Figure 16] 11 is an enlarged plan view showing another modified example of the plurality of video signal lines shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiment of the present invention will be described with reference to the drawings. Note that the disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, in order to make the explanation clearer, the drawings may show the width, thickness, shape, etc. of each part in a schematic manner compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same or related symbols, and detailed explanations may be omitted as appropriate.

[0009] In the following embodiment, a liquid crystal display device having a liquid crystal layer as an electro-optical layer will be described as an example of a display device. However, the technology described below can be applied to various modified examples in addition to liquid crystal display devices. For example, the electro-optical layer may be a layer including elements whose optical characteristics change when electrical energy is applied, such as a liquid crystal layer, an organic light-emitting element layer, an inorganic light-emitting element layer including a micro LED, a MEMS (Micro Electro Mechanical Systems) shutter, or an electrophoretic element layer.

[0010] Liquid crystal display devices are broadly classified into the following two types according to the direction of application of an electric field for changing the alignment of liquid crystal molecules in the liquid crystal layer. The first type is a so-called vertical electric field mode in which an electric field is applied in the thickness direction (or out-of-plane direction) of the display device. The vertical electric field mode includes, for example, a twisted nematic (TN) mode and a vertical alignment (VA) mode. The second type is a so-called horizontal electric field mode in which an electric field is applied in the plane direction (or in-plane direction) of the display device. The horizontal electric field mode includes, for example, an in-plane switching (IPS) mode and a fringe field switching (FFS) mode, which is one of the IPS modes. The technology described below can be applied to both the vertical electric field mode and the horizontal electric field mode, but the embodiment described below will be described by taking a display device in the horizontal electric field mode as an example.

[0011] <Display device configuration> First, the configuration of the display device will be described. FIG. 1 is a plan view of the display surface side showing an example of the display device of the present embodiment. In FIG. 1, the boundary between the display area DA and the peripheral area PFA, the switch circuit area ASWA, the peripheral wiring area PFWA, and the terminal area TMA are each shown by a two-dot chain line. In FIG. 1, the area where the seal material SLM is arranged is hatched. In FIG. 1, four video signal wirings VSW arranged at the end of the video signal wiring group are representatively shown among many video signal wirings VSW. FIG. 2 is a cross-sectional view taken along the line AA in FIG. 1. As shown in FIG. 4 described later, in addition to the liquid crystal layer LQ, there are a plurality of conductive layers and insulating layers between the substrate 10 and the substrate 20, but these are omitted in FIG. 2. FIG. 3 is a circuit diagram showing an example of a circuit configuration around a pixel in the display area of ​​the display device shown in FIG. 1. FIG. 4 is an enlarged cross-sectional view of the display area of ​​the display device shown in FIG. 2. In Figure 4, in order to show an example of the positional relationship between the scanning signal lines GL and the video signal lines SL in the thickness direction of the substrate 10 (the Z direction shown in Figure 4), the scanning signal lines GL arranged in a cross section different from that in Figure 4 are shown by dotted lines.

[0012] 1, the display device DSP1 of the present embodiment includes a substrate 10, a display area DA, a switch circuit area ASWA, a peripheral wiring area PFWA, and a terminal area TMA. The substrate 10 includes a side 10s1 extending in the X direction (first direction) and a side 10s2 on the opposite side of the side 10s1 in the Y direction (second direction) perpendicular to the X direction. The substrate 10 also includes a side 10s3 extending in the Y direction and a side 10s4 on the opposite side of the side 10s3 in the X direction.

[0013] The display area DA is between the side 10s1 and the side 10s2 in the Y direction. In the display area DA, an image is formed according to an input signal supplied from the outside. The display area DA is an effective area in which the display device DSP1 displays an image in a plan view of the display surface. The display device DSP1 also has a peripheral area (non-display area) PFA around the display area DA in a plan view. In the example shown in FIG. 1, the peripheral area PFA is disposed between the side 10s2 and the display area DA, between the side 10s3 and the display area DA, and between the side 10s4 and the display area DA. However, as a modified example, the peripheral area PFA may not be provided between the side 10s2 and the display area DA, between the side 10s3 and the display area DA, and between the side 10s4 and the display area DA, and the display area DA may extend to the peripheral edge of the substrate 10.

[0014] The switch circuit area ASWA is between the side 10s1 and the display area DA in the Y direction. A signal selection circuit ASW (see FIG. 6 described later) consisting of a plurality of switching elements is arranged in the switch circuit area ASWA. The signal selection circuit ASW will be described in detail later.

[0015] The peripheral wiring area PFWA is located between the side 10s1 and the switch circuit area ASWA in the Y direction. In the switch circuit area PFWA, a plurality of peripheral wirings including a plurality of video signal wirings connected to the signal selection circuit and a plurality of touch detection wirings connected to the plurality of touch detection electrodes are arranged. The video signal wirings and the touch detection outer wirings will be described in detail later.

[0016] The terminal area TMA is located between the side 10s1 and the peripheral wiring area PFWA in the Y direction. In the terminal area TMA, a plurality of terminals TM1 (see FIG. 2) electrically connected to a plurality of peripheral wirings are arranged. The plurality of terminals TM1 arranged in the terminal area TMA are electrically connected to a control circuit that controls a video signal (video signal) VS (see FIG. 3) and a drive signal. In the example shown in FIG. 2, a semiconductor device SCP is mounted on the terminal TM1, and a control circuit that controls the video signal and the drive signal is formed in the semiconductor device SCP. As an example, the semiconductor device SCP is an external drive circuit such as a driver IC chip. In addition, as a modified example, the semiconductor device SCP may be formed on a flexible wiring board (not shown), the terminal TM1 may be connected to a terminal of the flexible wiring board, and the terminal TM1 may be connected to a control circuit (the scan drive circuit GD, the video signal drive circuit SD, and the common potential supply circuit CD shown in FIG. 3) that controls the video signal and the drive signal via the flexible wiring board.

[0017] As shown in FIG. 2, the display device DSP1 has a substrate 10 and a substrate 20 bonded together so as to face each other via a liquid crystal layer LQ. The substrate 10 and the substrate 20 face each other in the thickness direction (Z direction) of the display device DSP1. The substrate 10 has a front surface 10f facing the liquid crystal layer LQ (and the substrate 20). The substrate 10 has a rear surface 10b on the opposite side of the front surface 10f. The substrate 20 has a rear surface 20b facing the front surface 10f (and the liquid crystal layer LQ) of the substrate 10. The substrate 20 has a front surface 20f on the opposite side of the rear surface 20b. The substrate 10 is an array substrate on which a plurality of transistors (transistor elements) Tr1 (see FIG. 3) as switching elements (active elements) are arranged in an array. The substrate 20 is a substrate provided on the display surface side. The substrate 20 can be called an opposing substrate in the sense that it is a substrate arranged opposite the array substrate.

[0018] The liquid crystal layer LQ is located between the front surface 10f of the substrate 10 and the back surface 20b of the substrate 20. The liquid crystal layer LQ is an electro-optical layer that controls the transmission state of visible light. It has a function of modulating the light passing therethrough by controlling the state of the electric field formed around the liquid crystal layer LQ via the switching element. The display area DA on the substrate 10 and the substrate 20 overlaps with the liquid crystal layer LQ as shown in FIG. 2.

[0019] The substrates 10 and 20 are bonded together via a sealant (adhesive) SLM. As shown in FIG. 1, the sealant SLM is disposed in the peripheral area PFA so as to surround the periphery of the display area DA. As shown in FIG. 2, a liquid crystal layer LQ is disposed inside the sealant SLM. The sealant SLM serves as a seal for sealing liquid crystal between the substrates 10 and 20. The sealant SLM also serves as an adhesive for bonding the substrates 10 and 20 together.

[0020] The display device DSP1 also has optical elements OD1 and OD2. The optical element OD1 is disposed on the rear surface 10b side of the substrate 10. The optical element OD2 is disposed on the front surface 20f side of the substrate 20, in other words, on the display surface side. The optical elements OD1 and OD2 each include at least a polarizing plate, and may include a retardation plate as necessary. Although not shown, the display device DSP1 includes a light source unit. The light source unit is disposed, for example, on the rear surface side of the optical element OD1 (the opposite side of the substrate 10) or in the peripheral area PFA on the substrate 10.

[0021] Each of the substrates 10 and 20 is a transparent plate material having visible light transmissivity (a property that allows visible light to pass through). An example of a substrate that is a transparent plate material is a glass substrate. In addition, resin materials (visible light transmissive resin materials) containing polymers such as polyimide, polyamide, polycarbonate, or polyester can also be used as the constituent material of the substrates 10 and 20. In addition, in the case of a substrate made of a resin material such as polyimide, the substrate has flexibility. When the substrate 10 has flexibility, a part of the substrate 10 (for example, the peripheral area PFA) can be curved or folded. When the substrate 10 and the substrate 20 have flexibility, the area of ​​the peripheral area PFA in plan view can be reduced. In this case, the occupancy rate of the effective display area in plan view can be increased.

[0022] As shown in Fig. 3, a plurality of pixels PX are arranged in the display area DA. In the example shown in Fig. 3, each of the plurality of pixels PX has a plurality of sub-pixels PXs. The plurality of sub-pixels PXs include, for example, red, blue, and green sub-pixels PXs, and a color image can be displayed by controlling the color tones of the plurality of sub-pixels PXs. The number of types of sub-pixels PXs constituting one pixel PX can be variously modified in addition to the three types illustrated in Fig. 3.

[0023] Each of the subpixels PXs includes a transistor Tr1, which is a switching element that controls the on / off of an electric field applied to the liquid crystal layer LQ. The transistor Tr1 controls the operation of the subpixel PXs. As will be described later, the transistor Tr1 is a thin film transistor (TFT) formed on the substrate 10.

[0024] Also, as shown in Fig. 3, the display device DSP1 has a plurality of scanning signal lines GL extending in the X direction in the display area DA, and a plurality of video signal lines SL extending in the Y direction intersecting the X direction (perpendicular in Fig. 3) in the display area DA. The scanning signal lines GL are gate lines connected to the gate of the transistor Tr1. The video signal lines SL are source lines connected to the source of the transistor Tr1. Each of the plurality of scanning signal lines GL extends in the X direction and is arranged, for example, at equal intervals in the Y direction. Each of the plurality of video signal lines SL extends in the Y direction and is arranged, for example, at equal intervals in the X direction.

[0025] Each of the multiple scanning signal lines GL is connected to a scanning drive circuit (gate drive circuit) GD. A scanning signal Gsi output from the scanning drive circuit GD is input to the gate of the transistor Tr1 via the scanning signal line GL. Each of the multiple video signal lines SL is connected to a video signal drive circuit SD. A video signal VS output from the video signal drive circuit SD is input to the source of the transistor Tr1 via the video signal line SL. The scanning drive circuit GD and the video signal drive circuit SD are provided in, for example, a semiconductor device SCP shown in FIG. 2. Alternatively, as a modified example, the video signal drive circuit SD may be formed on a substrate 10 shown in FIG. 1.

[0026] Each of the video signal lines SL is connected to a pixel electrode PE via a transistor Tr1. More specifically, the video signal line SL is connected to the source of the transistor Tr1, and the pixel electrode PE is connected to the drain of the transistor Tr1. When the transistor Tr1 is on, a video signal VS is supplied to the pixel electrode PE from the video signal line SL. The pixel electrode PE is also connected to the electrode CE via a dielectric layer (capacitor element CS shown in FIG. 3). During a display period in which an image is displayed in the display area DA, a fixed potential is supplied to each of the electrodes CE as a common electrode from a common potential supply circuit CD. The fixed potential supplied to the electrode CE is a potential common to the sub-pixels PXs (hereinafter, may be referred to as a common potential). During the display period, an electric field is formed in each sub-pixel PXs according to the potential difference between the common potential supplied to the electrode CE and the potential supplied to the pixel electrode PE, and the liquid crystal molecules contained in the liquid crystal layer LQ are driven by this electric field.

[0027] The scan drive circuit GD, the video signal drive circuit SD, and the common potential supply circuit CD shown in FIG. 3 are each led out by wiring to the terminal area TMA shown in FIG. 1 and electrically connected to the semiconductor device SCP.

[0028] 4, between the substrate 10 and the liquid crystal layer LQ, there are a plurality of conductive layers CL1-CL5, a plurality of insulating films 11-16, and an alignment film AL1. The plurality of conductive layers CL1-CL5, the plurality of insulating films 11-16, and the alignment film AL1 are formed on the front surface 10f of the substrate 10. In addition, between the substrate 20 and the liquid crystal layer LQ, there are a light-shielding film BM, color filters CFR, CFG, and CFB, an insulating film OC1, and an alignment film AL2. The light-shielding film BM, the color filters CFR, CFG, and CFB, the insulating film OC1, and the alignment film AL2 are formed on the rear surface 20b of the substrate 20.

[0029] Each of the conductive layers CL1, CL2, and CL3 shown in FIG. 4 has a conductor pattern (metal wiring) made of a light-shielding metal. The conductive layer CL1 includes a metal film made of metal such as molybdenum (Mo) or tungsten (W) or an alloy thereof. The conductive patterns of the conductive layers CL2 and CL3 include a multilayered metal film, such as a laminated film in which an aluminum (Al) film is sandwiched between a titanium (Ti) film or a titanium nitride (TiN) film. The conductive layers CL4 and CL5 mainly include a conductive oxide material (transparent conductive material) such as ITO (indium tin oxide) or IZO (indium zinc oxide). In this specification, a conductive film formed of a material that has both visible light transparency and conductivity, such as ITO or IZO, is called a transparent conductive film.

[0030] Insulating films are interposed between the conductive layers CL1 to CL5. Insulating films 11 and 12 are interposed between the conductive layer CL1 and the substrate 10. Insulating film 13 is interposed between the conductive layer CL1 and the conductive layer CL2. Insulating film 14 is interposed between the conductive layer CL3 and the conductive layer CL4. Insulating film 15 is interposed between the conductive layer CL4 and the conductive layer CL5. An alignment film AL1 is interposed between the conductive layer CL5 and the liquid crystal layer LQ. Each of the insulating films 11, 12, 13, and 16 is an inorganic insulating film. Examples of the inorganic insulating film include a silicon nitride (SiN) film, a silicon oxide (SiO) film, an aluminum oxide (AlOx) film, or a laminated film of these. Insulating films 14 and 15 are organic insulating films. An insulating film made of an organic material can be formed thicker than an insulating film made of an inorganic material to flatten the upper surface (front surface). The insulating films 14 and 15 are used as planarizing films that planarize the unevenness of the conductor pattern formed on the underlayer. Therefore, the thickness of the insulating film 14 and the thickness of the insulating film 15 are greater than the thickness of each of the inorganic insulating films 11, 12, and 13. An example of an organic insulating film is an acrylic photosensitive resin.

[0031] Each of the plurality of scanning signal lines GL is formed on a conductive layer CL1 on a substrate 10. Insulating films 11 and 12 are laminated on the substrate 10, and the scanning signal lines GL are formed on the insulating film 12. Each of the plurality of video signal lines SL is formed on a conductive layer CL2 on the substrate 10. Insulating films 11, 12, and 13 are laminated on the substrate 10, and the video signal lines SL are formed on the insulating film 13.

[0032] Between the insulating film 11 and the insulating film 12, a semiconductor layer of a transistor (transistor element) Tr1 shown in FIG. 3 is formed. The semiconductor layer is not shown in FIG. 4 because it is in a different cross section from that in FIG. 4. The source region of the semiconductor layer is electrically connected to a video signal line SL formed in the conductive layer CL2. The drain region of the semiconductor layer is electrically connected to a pixel electrode PE of the conductive layer CL5. In a plan view, a scanning signal line GL extends between the source region and the drain region of the semiconductor layer. The scanning signal line GL overlaps with a channel region of the semiconductor layer and functions as a gate electrode of the transistor Tr1. The insulating film 12 interposed between the channel region and the scanning signal line GL functions as a gate insulating film. As in the above example, a TFT having a structure in which a gate electrode is arranged above the channel region of the transistor Tr1 is called a top gate type. However, there are various modified types of TFT types, and for example, a bottom gate type in which a gate electrode is arranged below the channel region may be used. Alternatively, there is also a type in which gate electrodes are arranged both above and below the channel region.

[0033] The conductive layer CL3 has a wiring MW3 disposed thereon. The wiring MW3 is a metal wiring made of metal, like the scanning signal lines GL and the video signal lines SL. The wiring MW3 is disposed at a position overlapping the video signal lines SL in the thickness direction (Z direction). The wiring MW3 is electrically connected to an electrode CE formed on the conductive layer CL4. In this case, the wiring MW3 can be used as a wiring for supplying a potential to the electrode CE. As will be described later, the electrode CE is used as a detection electrode for detecting an input position (touch position) by utilizing a change in capacitance in the display device DSP1 as a touch panel. The wiring MW3 electrically connects the electrode CE for detecting the input position to a detection circuit. In this case, the wiring MW3 is used as a signal transmission path for transmitting a drive signal or a detection signal used for detecting a touch position.

[0034] The conductive layer CL4 includes a transparent conductive film TCF1 that is transparent to visible light, and is located between the substrate 10 and the substrate 20. An electrode CE is formed on the conductive layer CL4. The plurality of transparent conductive films TCF1 formed on the conductive layer CL4 include the electrode CE. The electrode CE is formed on an insulating film 15, which is a planarizing film, in the display area DA. The insulating film 15 corresponds to an insulating layer 32 shown in FIG. 7, which will be described later. Although one electrode CE is shown in FIG. 3, a plurality of electrodes CE are arranged at a distance from each other in the display area DA shown in FIG. 1. Also, as described above, a common potential is supplied to the electrode CE for a plurality of sub-pixels PXs. Therefore, as shown in FIG. 3, the electrode CE may be arranged across a plurality of sub-pixels PXs. In the case of the present embodiment, the electrode CE is used as a detection electrode for input position detection, as will be described later. Therefore, a plurality of electrodes CE are arranged at a distance from each other in the display area DA shown in FIG. 1. Details of the layout of the electrode CE in a planar view will be described later.

[0035] The conductive layer CL5 includes a transparent conductive film TCF2 that is transparent to visible light, and is located between the conductive layer CL4 and the substrate 20. A plurality of pixel electrodes PE are formed on the conductive layer CL5. The plurality of transparent conductive films TCF2 formed on the conductive layer CL5 include a plurality of pixel electrodes PE. An insulating film 16, which is an inorganic insulating film, is interposed between the conductive layer CL5 on which the pixel electrodes PE are formed and the conductive layer CL4 on which the electrode CE is formed. This insulating film 16 functions as a dielectric layer to form the capacitive element CS shown in FIG. 3.

[0036] The pixel electrodes PE are covered with an alignment film AL1. The alignment film AL1 is an organic insulating film having a function of aligning the initial alignment of the liquid crystal molecules contained in the liquid crystal layer LQ, and is made of, for example, a polyimide resin. The alignment film AL1 is in contact with the liquid crystal layer LQ.

[0037] As shown in FIG. 3, on the back surface (main surface, surface) 20b of the substrate 20, a light-shielding film BM, color filters CFR, CFG, and CFB, an insulating film OC1, and an alignment film AL2 are formed.

[0038] The color filters CFR, CFG, and CFB are formed on the rear surface 20b side facing the substrate 10. In the example shown in FIG. 4, the color filters CFR, CFG, and CFB of three colors, red (R), green (G), and blue (B), are periodically arranged. In a color display device, for example, a color image is displayed by using a set of pixels of three colors, red (R), green (G), and blue (B). The multiple color filters CFR, CFG, and CFB of the substrate 20 are arranged at positions facing each other and the respective pixels PX (see FIG. 1) having pixel electrodes PE formed on the substrate 10. The types of color filters are not limited to the three colors of red (R), green (G), and blue (B).

[0039] In addition, a light-shielding film BM is disposed at each boundary between the color filters CFR, CFG, and CFB of each color. The light-shielding film BM is called a black matrix and is made of, for example, black resin or low-reflectivity metal. The light-shielding film BM in the display area DA is formed, for example, in a lattice shape in a plan view. In other words, the light-shielding film BM extends in the X direction and the Y direction. More specifically, the light-shielding film BM has a plurality of portions extending in the Y direction and a plurality of portions extending in the X direction intersecting the Y direction. By dividing each pixel PX with a black matrix, light leakage and color mixing can be suppressed.

[0040] In the display area DA, the light-shielding film BM overlaps with the scanning signal lines GL, the video signal lines SL, and the wiring MW3, which are metal wirings. The metal wirings having light-shielding properties are arranged at positions overlapping the light-shielding film BM, so that the metal wirings are difficult to see on the display screen. Meanwhile, at least a portion of the electrode CE and the pixel electrode PE are arranged at positions not overlapping with the light-shielding film BM. The electrode CE and the pixel electrode PE are formed of a conductive material that is transparent to visible light. Therefore, although the electrode CE and the pixel electrode PE are arranged at positions not overlapping with the light-shielding film BM, visible light is not blocked by the electrode CE or the pixel electrode PE in each sub-pixel PXs.

[0041] The light-shielding film BM is also formed in the peripheral area PFA (see FIG. 1) of the substrate 20. The peripheral area PFA overlaps with the light-shielding film BM. The display area DA is defined as an area inside the peripheral area PFA. The peripheral area PFA is also a region overlapping with the light-shielding film BM that blocks light emitted from a backlight unit (light source, not shown). The light-shielding film BM is also formed in the display area DA, but a plurality of openings are formed in the light-shielding film BM in the display area DA. In general, among the openings formed in the light-shielding film BM and exposing the color filters, the edge of the opening formed closest to the periphery is defined as the boundary between the display area DA and the peripheral area PFA.

[0042] The insulating film OC1 shown in Fig. 4 covers the color filters CFR, CFG, and CFB. The insulating film OC1 functions as a protective film that prevents impurities from diffusing from the color filters to the liquid crystal layer. The insulating film OC1 is an organic insulating film made of, for example, an acrylic photosensitive resin.

[0043] The insulating film OC1 is covered with an alignment film AL2. The alignment film AL2 is an organic insulating film having a function of aligning the initial alignment of the liquid crystal molecules contained in the liquid crystal layer LQ, and is made of, for example, a polyimide resin. The alignment film AL2 is in contact with the liquid crystal layer LQ.

[0044] <Touch panel function> Next, a touch panel function of the display device DSP1 of the present embodiment will be described. Fig. 5 is a plan view showing an example of the layout of a common electrode (touch detection electrode) included in the display device shown in Fig. 1. Fig. 5 shows, as a representative example, four touch detection wirings TDW arranged at ends of a group of touch detection wirings among a large number of touch detection wirings TDW.

[0045] The display device DSP1 is a sensor-equipped display device having a touch panel function for detecting an input position by utilizing a change in capacitance in a sensor region overlapping with the display area DA. The display area DA shown in FIG. 1 includes a sensor region as a detection device having a touch panel function for detecting a change in capacitance. As shown in FIG. 5, the display device DSP1 has a plurality of electrodes CE separated from each other. The plurality of electrodes CE are arranged in a matrix in the X direction and the Y direction in the display area DA. Each electrode CE is shown in a schematic rectangular or square shape in a plan view. As described above, the electrode CE is formed by the conductor layer CL4, and is made of a conductive material having visible light transparency, such as ITO. As shown in FIG. 5, the plurality of electrodes CE are arranged in a matrix in the X direction and the Y direction in the display area DA. Each of the plurality of electrodes CE functions as a touch electrode for detecting that a dielectric such as a finger has come into contact with or approached a part of the display area DA. That is, the display device DSP1 of the present embodiment has a plurality of electrodes (touch detection electrodes) CE arranged in the display area DA.

[0046] A connection circuit MP is provided on the short side of the peripheral area PFA. A touch detection circuit (detection control circuit) DP for controlling a touch panel function is provided on the short side of the peripheral area PFA. The touch detection circuit DP is formed, for example, in a semiconductor device SCP (see FIG. 2) mounted on the terminal area TMA shown in FIG. 1. The connection circuit MP and the detection circuit DP are electrically connected via a plurality of touch detection wirings TDW. The arrangement of the connection circuit MP and the detection circuit DP is not limited to the example shown in FIG. 5, and the connection circuit MP and the detection circuit DP may be provided, for example, on a substrate 10 of the display device DSP1. The connection circuit MP may be a built-in circuit formed on the substrate 10, or may be a circuit formed in a driver IC (for example, the semiconductor device SCP shown in FIG. 2) mounted on the substrate 10. Alternatively, when a flexible wiring board (not shown) is connected to the terminal area TMA (see FIG. 1), the connection circuit MP and the detection circuit DP may be provided on a control substrate or flexible wiring board outside the module.

[0047] The electrode CE is electrically connected to the detection circuit DP through the wiring MW3, the connection circuit MP, and the touch detection wiring TDW. The wiring MW3 and the touch detection wiring TDW supply a drive signal to be supplied to the electrode CE, and send a signal according to the change in capacitance to the analog front end. For example, a drive circuit built in the detection circuit DP is connected to the electrodes CE through the touch detection wiring TDW arranged in the peripheral area PFA, the connection circuit MP, and the wiring MW3. In this embodiment, the wirings MW3 and the touch detection wirings TDW are distinguished as follows. That is, the wirings MW3 are wirings for touch detection formed in the display area DA. On the other hand, the touch detection wirings TDW are wirings for touch detection formed in the peripheral area PFA. The wirings MW3 and the touch detection wirings TDW are electrically connected to each other through the connection circuit MP. Each of the wirings MW3 extends along the Y direction, and the wirings MW3 are arranged side by side in the X direction.

[0048] The detection circuit DP includes a circuit that supplies a drive signal for detecting a change in capacitance during a detection period in which the touch panel function of the display device DSP1 is operating, and a circuit that receives a detection signal output from the electrode CE. The connection circuit MP is provided between the electrode CE and the detection circuit DP. The connection circuit MP is a circuit that switches between connection and disconnection between the electrode CE that is the target of detection drive and the detection circuit DP based on a control signal supplied from the detection circuit DP. The connection circuit MP has an analog front end.

[0049] In the insulating film 15 shown in Fig. 4, an opening (contact hole) (not shown) is formed at a position where the electrode CE and the wiring MW3 overlap, and the electrode CE and the wiring MW3 are electrically connected through the opening. In the example shown in Fig. 5, one wiring MW3 and one electrode CE are electrically connected. However, one electrode CE may be electrically connected to multiple wirings MW3. In this case, a bundle of multiple wirings MW3 connected to one electrode CE constitutes a transmission path for a drive signal and a detection signal for touch detection.

[0050] In the case of the display device DSP1, a display period in which the liquid crystal layer LQ (see FIG. 2) is driven to display an image and a detection period in which the electrode CE is driven to detect an input position are alternately and repeatedly performed. In the display period, the electrode CE operates as a common electrode. Therefore, in the display period, a common potential for forming an electric field for driving the liquid crystal layer LQ is supplied to each of the electrodes CE arranged across the pixels. In other words, during the display period, a fixed potential (for example, a first potential) is supplied to each of the touch detection wirings TDW, the wirings MW3, and the electrodes CE. Also, the electrode CE operates as a drive electrode for detecting an input position in the sensor area in the detection period. Therefore, in the detection period, a drive signal for detecting an input position is input to the electrode CE from the detection circuit DP. Also, the electrode CE operates as a detection electrode for detecting an input position in the sensor area in the detection period. Therefore, in the detection period, the electrode CE outputs a detection signal corresponding to the input drive signal.

[0051] The detection signal from the electrode CE changes due to the effect of the capacitance around the electrode CE. When an input tool such as a finger approaches one of the multiple electrodes CE, the capacitance around that electrode CE changes due to the effect of the input tool. In this case, the detection signal output from the electrode CE close to the input tool has a waveform different from the detection signals output from the other electrodes CE. The detection circuit DP receives the detection signals supplied from each of the multiple electrodes CE and identifies the input position based on these detection signals.

[0052] In the case of the electrode CE of this embodiment, it functions as both a driving electrode to which a driving signal is supplied and a detection electrode to which a detection signal is output. However, as a modified example, the driving electrode and the detection electrode may be provided separately. For example, when the electrode CE is used as a driving electrode, a detection electrode may be provided separately from the electrode CE.

[0053] <Signal selection circuit> Next, the signal selection circuit arranged in the switch circuit area ASWA shown in FIG. 1 will be described. FIG. 6 is an explanatory diagram that shows a schematic diagram of the operation of the signal selection circuit arranged in the switch circuit area shown in FIG. 1. In this embodiment, the multiple video signal lines SL and the multiple video signal wirings VSW are distinguished as follows. That is, the multiple video signal lines SL are wirings for transmitting video signals formed in the display area DA. On the other hand, the multiple video signal wirings VSW are wirings for transmitting video signals formed in the peripheral area PFA. The multiple video signal lines SL and the multiple video signal wirings VSW are electrically connected via the signal selection circuit ASW shown in FIG. 6.

[0054] As shown in Fig. 6, a plurality of signal selection circuits ASW are arranged in the switch circuit area ASWA. The signal selection circuit ASW includes a plurality of switching elements (three in the example shown in Fig. 6). Each of the plurality of switching elements provided in the signal selection circuit ASW is connected to a video signal line SL. In the example shown in Fig. 6, three video signal lines SL are connected to the signal selection circuit ASW consisting of three sets of switching elements. Meanwhile, one video signal wiring VSW is connected to one signal selection circuit ASW.

[0055] The signal selection circuit ASW selects each of the three switching elements in turn and turns them on based on the signal selection signal ASWS input from the video signal drive circuit SD. When one of the three switching elements is in the on state, the other two switching elements are in the off state. The video signal VS (see FIG. 3) transmitted through the video signal wiring VSW is transmitted to one of the three video signal lines SL via the switching element that is in the on state. Since the three switching elements are turned on in turn, the video signal VS is supplied to each of the three video signal lines SL in turn.

[0056] In this way, by interposing the signal selection circuit ASW between the video signal lines SL in the display area DA and the video signal lines VSW in the peripheral wiring area PFWA, the number of video signal lines VSW arranged in the peripheral wiring area PFWA can be reduced. As shown in FIG. 6, the number of the video signal lines VSW is less than the number of the video signal lines SL. In the example shown in FIG. 6, the number of the video signal lines VSW is 1 / 3 the number of the video signal lines SL. By reducing the number of lines arranged in the peripheral wiring area PFWA, the area of ​​the peripheral area PFA shown in FIG. 1 can be reduced.

[0057] <Noise countermeasures> As described above, the signal selection circuit ASW has the advantage of being able to reduce the area of ​​the peripheral area PFA. However, according to the study by the present inventor, it has been found that the electromagnetic waves generated by the switching operation of the signal selection circuit ASW may become noise. The display device DSP1 may be used as a portable terminal device having a wireless communication function with an external device. For example, in the example shown in FIG. 2, the display device includes a display module DM including a substrate 10 and a substrate 20, as well as a communication module TMM having a wireless communication function. If the electromagnetic waves generated by the switching operation of the signal selection circuit ASW interfere with the band of wireless communication performed by the communication module TMM, it becomes noise for wireless communication. Therefore, the present inventor has studied a technology for suppressing the generation of electromagnetic waves caused by the switching operation of the signal selection circuit ASW or the diffusion of the generated electromagnetic waves.

[0058] Electromagnetic waves accompanying the switching operation of the signal selection circuit ASW shown in Fig. 6 are particularly likely to be generated from the video signal wiring VSW arranged in the peripheral wiring area PFWA. Therefore, the inventors of the present application have studied a method of implementing noise countermeasures around the multiple video signal wirings VSW. As a result of the study, it has been found that the generation of electromagnetic waves accompanying the switching operation of the signal selection circuit ASW or the diffusion of the generated electromagnetic waves can be suppressed by arranging a conductor pattern that is capacitively coupled to the multiple video signal wirings VSW around the multiple video signal wirings VSW. The concept of noise countermeasures in this embodiment will be described with reference to Fig. 7.

[0059] Fig. 7 is an enlarged cross-sectional view showing an example of a noise countermeasure in the peripheral wiring region shown in Fig. 1. In Fig. 7, a state in which a conductor pattern formed on the wiring layer WL1 and a conductor pattern formed on the wiring layer WL2 are capacitively coupled is shown using a circuit symbol for a capacitor.

[0060] 7, the peripheral wiring area PFWA includes an insulating layer 31 on the substrate 10, a wiring layer WL1 on the insulating layer 31, an insulating layer 32 on the insulating layer 31 and covering the wiring layer WL1, and a wiring layer WL2 on the insulating layer 32. The insulating layer 31 is, for example, an inorganic insulating film made of a laminated film of the insulating film 11, the insulating film 12, and the insulating film 13 shown in FIG. 4. The insulating layer 32 is, for example, an organic insulating film (planarizing film) corresponding to the insulating film 14 shown in FIG. 4. The insulating layer 33 is, for example, an organic insulating film corresponding to the insulating film 15 shown in FIG. 4. The wiring layer WL1 corresponds to the conductive layer CL2 shown in FIG. 4, and the wiring layer WL2 corresponds to the conductive layer CL3 shown in FIG. 4.

[0061] As shown in Fig. 7, a plurality of video signal lines VSW are arranged in the wiring layer WL1. A plurality of touch detection lines TDW and a conductor pattern CCP are formed in the wiring layer WL2. In a display period in which the signal selection circuit ASW shown in Fig. 6 operates, a fixed potential (for example, the same potential as the common potential supplied to the touch detection lines TDW) is supplied to the conductor pattern CCP. In addition, the conductor pattern CCP is arranged at a position overlapping with a portion of the plurality of video signal lines VSW, and is capacitively coupled to a portion of the plurality of video signal lines VSW.

[0062] As shown in FIG. 7, another part (hereinafter, referred to as the other part) of the multiple video signal wirings VSW overlaps with the touch detection wiring TDW. As described above, the touch detection wiring TDW is used as a transmission path for supplying a common potential to each of the multiple electrodes CE shown in FIG. 5 during the display period. Therefore, during the display period in which the signal selection circuit ASW shown in FIG. 6 operates, a common potential is supplied to the touch detection wiring TDW. Therefore, when a noise current flows through a video signal wiring VSW that is capacitively coupled with the touch detection wiring TDW among the multiple video signal wirings VSW, the noise component can be reduced by the decoupling function of the capacitor coupled to the video signal wiring VSW through which the noise current flows.

[0063] However, the number of the touch detection wirings TDW is smaller than the number of the video signal wirings VSW. In other words, the number of the video signal wirings VSW is greater than the number of the touch detection wirings TDW. Therefore, not all the video signal wirings VSW overlap with the touch detection wirings TDW. Therefore, in this embodiment, by arranging a conductor pattern CCP at a position overlapping with the video signal wirings VSW that are arranged at a position not overlapping with the touch detection wirings TDW among the multiple video signal wirings VSW, it is possible to reduce the noise components flowing in each of the multiple video signal wirings VSW. The conductor pattern CCP shown in FIG. 7 is capacitively coupled with a part of the multiple video signal wirings VSW, and is supplied with a fixed potential during the display period in which the signal selection circuit ASW shown in FIG. 6 operates. As a result, when a noise current flows in the video signal wiring VSW that is capacitively coupled with the conductor pattern CCP, the noise components can be reduced by the decoupling function of the capacitor coupled to the video signal wiring VSW through which the noise current flows.

[0064] There are various modes for the shape of the conductor pattern CCP as a noise countermeasure. Below, several regions where the conductor pattern CCP should be arranged are illustrated, and a preferred mode of the conductor pattern CCP in each region is described. Fig. 8 is an enlarged plan view of part B shown in Fig. 1. Although Fig. 8 is a plan view, the touch detection wiring TDW and the video signal wiring VSW are hatched to make it easier to see the range in which the touch detection wiring TDW and the video signal wiring VSW are arranged and the extending direction of the touch detection wiring TDW and the video signal wiring VSW.

[0065] As shown in FIG. 8, the peripheral wiring area PFWA can be divided into a plurality of areas according to the presence or absence of the touch detection wiring TDW and the video signal wiring VSW, or the extending direction. The peripheral wiring area PFWA includes a wiring area R1 in which a plurality of video signal wirings VSW extend in a direction inclined with respect to each of the X direction and the Y direction. The peripheral wiring area PFWA is between the terminal area TMA and the wiring area R1 in the Y direction, and includes a wiring area R2 in which a plurality of video signal wirings VSW extend in the Y direction. The peripheral wiring area PFWA includes a wiring area R3 in which a plurality of video signal wirings VSW are not arranged between the side 10s1 and the wiring area R1 in the Y direction. Note that the wiring area R7 described later is also between the side 10s1 and the wiring area R1 in the Y direction, similar to the wiring area R3, and does not include a plurality of video signal wirings VSW. However, in this embodiment, the wiring area R3 and the wiring area R7 will be described separately. The peripheral wiring area PFWA also includes a wiring area R9 in which a plurality of touch detection wirings TDW are not arranged in the wiring area R1. In the wiring region R9, noise is easily diffused from the multiple video signal wirings VSW. Therefore, it is preferable that a conductor pattern CCP is arranged in the wiring region R9 at a position overlapping the multiple video signal wirings VSW as a countermeasure against noise generated from the video signal wirings VSW. Next to the wiring region R9, there is a wiring region R3 in which the multiple video signal wirings VSW and the multiple touch detection wirings TDW are not arranged. The conductor pattern CCP1 is arranged so as to straddle the boundary between the wiring region R3 and the wiring region R1 (specifically, the wiring region R9). In other words, the conductor pattern CCP includes a conductor pattern CCP1 arranged so as to straddle the boundary between the wiring region R3 and the wiring region R1. This makes it possible to reduce the generation of noise from the multiple video signal wirings VSW arranged in the wiring region R9.

[0066] The above-described structure can also be expressed as follows. That is, the peripheral wiring area PFWA includes a wiring area R9 in which the plurality of touch detection wirings TDW are not arranged in the wiring area R1. The plurality of conductor patterns CCP includes a conductor pattern CCP1 arranged in the wiring area R9. In this expression, in addition to the case where the conductor pattern CCP1 is arranged across the wiring area R3 and the wiring area R9, the case where the conductor pattern CCP1 is arranged in the wiring area R9 and is not arranged in the wiring area R3 is also included.

[0067] The peripheral wiring area PFWA includes the wiring area R4 in the wiring area R2 where the touch detection wirings TDW are arranged adjacent to each other in the wiring layer WL2. The peripheral wiring area PFWA includes the wiring area R5 and the wiring area R6 in the wiring area R2 where the touch detection wirings TDW are not arranged and which are between the wiring area R1 and the terminal area TMA in the Y direction. In the X direction, the wiring area R4 is between the wiring area R5 and the wiring area R6. In other words, in the X direction, the wiring area R5 and the wiring area R6 are on opposite sides of the wiring area R4. The wiring area R5 and the wiring area R6 are areas in which the video signal wirings VSW are arranged and the touch detection wirings TDW are not arranged. For this reason, it is preferable that the conductor pattern CCP2 is arranged in the wiring area R5 and the wiring area R6 at a position overlapping the video signal wirings VSW as a countermeasure against noise generated from the video signal wirings VSW. In the example shown in FIG. 8, the conductor pattern CCP includes conductor patterns CCP2 arranged in each of the wiring areas R5 and R6.

[0068] The peripheral wiring area PFWA includes a wiring area R7 that is adjacent to the wiring area R6 in the X direction, between the side 10s1 and the wiring area R1 in the Y direction, and in which the video signal wirings VSW are not arranged. The video signal wirings VSW and the touch detection wirings TDW are not arranged in the wiring area R7. The peripheral wiring area PFWA includes a wiring area R10 in the wiring area R1 in which the touch detection wirings TDW are not arranged. In the wiring area R10, noise is likely to be diffused from the video signal wirings VSW, as in the wiring area R9. Therefore, it is preferable that the wiring area R10 includes a conductor pattern CCP as a countermeasure against noise generated from the video signal wirings VSW at a position overlapping the video signal wirings VSW. Next to the wiring area R10 is the wiring area R7 in which the video signal wirings VSW and the touch detection wirings TDW are not arranged. The conductor pattern CCP3 is arranged so as to straddle the boundary between the wiring area R7 and the wiring area R1 (specifically, the wiring area R10). In other words, the conductor pattern CCP includes the conductor pattern CCP3 arranged so as to straddle the boundary between the wiring region R7 and the wiring region R1, thereby making it possible to reduce noise generation from the multiple video signal lines VSW arranged in the wiring region R10.

[0069] The structure regarding the wiring region R10 described above can also be expressed as follows. That is, the peripheral wiring region PFWA includes the wiring region R8 in the wiring region R1 where the multiple touch detection wirings TDW extend in the Y direction. The peripheral wiring region PFWA includes the wiring region R9 and the wiring region R10 in the wiring region R1 where the multiple touch detection wirings TDW are not arranged. In a plan view, the wiring region R8 is arranged between the wiring region R9 and the wiring region R10. The multiple conductor patterns CCP include the conductor pattern CCP3 arranged in the wiring region R10. In this expression, in addition to the case where the conductor pattern CCP3 is arranged across the wiring region R7 and the wiring region R10, the case where the conductor pattern CCP3 is arranged in the wiring region R10 and is not arranged in the wiring region R7 is also included.

[0070] Moreover, the peripheral wiring area PFWA includes the wiring area R4 in the wiring area R2 where the touch detection wirings TDW are arranged adjacent to each other in the wiring layer WL2. The peripheral wiring area PFWA includes the wiring area R8 in the wiring area R1 where the touch detection wirings TDW extend in the Y direction. In the wiring area R4 and the wiring area R8, each of the touch detection wirings TDW extends in the Y direction, so that the distance between the adjacent touch detection wirings TDW is large. For this reason, it is preferable that the conductor pattern CCP is arranged in this portion from the viewpoint of suppressing the generation of noise from the portion of the video signal wirings VSW arranged in the gap between the adjacent touch detection wirings TDW. In the example shown in FIG. 8, the conductor pattern CCP4 is arranged so as to straddle the boundary between the wiring area R4 and the wiring area R8. In other words, the conductor pattern CCP includes the plurality of conductor patterns CCP4 arranged so as to straddle the boundary between the wiring area R4 and the wiring area R8. This makes it possible to reduce the generation of noise from the plurality of video signal wirings VSW arranged in the wiring area R4 and the wiring area R8.

[0071] Moreover, the peripheral wiring area PFWA includes a wiring area R11 in which the plurality of touch detection wirings TDW extend in a direction inclined with respect to each of the X direction and the Y direction in the wiring area R1. In the area in which the extension direction of the touch detection wirings TDW is inclined with respect to each of the X direction and the Y direction, the separation distance between the adjacent touch detection wirings TDW is smaller than in the area in which each of the plurality of touch detection wirings TDW extends in the Y direction (for example, the wiring area R4 and the wiring area R8). Therefore, the conductor pattern CCP is not arranged between the adjacent touch detection wirings TDW. In the wiring area R10, even if the conductor pattern CCP is not arranged, most of the plurality of video signal wirings VSW overlap with the touch detection wirings TDW, so that the risk of noise generation is relatively low.

[0072] In the example shown in Fig. 8, an embodiment in which a conductor pattern CCP is arranged in each of wiring areas R4, R5, R6, R8, R9, and R10 is described. However, as a modified example, a conductor pattern CCP may be arranged in one or several of wiring areas R4, R5, R6, R8, R9, and R10 shown in Fig. 8. In this case, it is possible to reduce noise generation from a plurality of video signal wirings VSW in the wiring area in which the conductor pattern CCP is arranged.

[0073] <Routing areas R9 and R10> Next, details of each wiring region described with reference to Fig. 8 will be described, including modified examples. Fig. 9 is an enlarged plan view showing a modified example of a part (around the boundary between wiring region R9 and wiring region R3) of the wiring region shown in Fig. 8. Although Fig. 9 is a plan view, in order to easily identify the touch detection wiring TDW and the video signal wiring VSW, the touch detection wiring TDW, the video signal wiring VSW, and the conductor pattern CCP are each hatched.

[0074] The example shown in Fig. 9 differs from the conductor pattern CCP1 shown in Fig. 8 in that the conductor pattern CCP1 is formed as a plurality of elongated wiring patterns. The conductor pattern CCP includes a plurality of conductor patterns CCP1 extending in the Y direction so as to straddle the boundary between the wiring region R3 and the wiring region R1. However, as shown in Fig. 8, the conductor pattern CCP1 may be a large-area conductor pattern CCP that uniformly spreads over the wiring region R3 and the wiring region R9. Alternatively, although not shown, the conductor pattern CCP1 may be a mesh-shaped conductor pattern CCP.

[0075] Each of the plurality of conductor patterns CCP1 extends in the Y direction from the wiring region R3. Each of the plurality of conductor patterns CCP1 extends to the vicinity of the boundary between the wiring region R9 and the wiring region R11, but is not formed in the wiring region R11. The plurality of touch detection wirings TDW are arranged in the wiring region R11. In other words, each of the plurality of conductor patterns CCP1 extends to the vicinity of the touch detection wiring TDW.

[0076] Also, as shown in FIG. 9, in the wiring region R3, the wiring layer WL1 is provided with wiring VCW arranged along the boundary between the wiring region R3 and the wiring region R1. The wiring (first potential wiring) VCW is a wiring for electromagnetically shielding the peripheral area PFA around the display area DA shown in FIG. 1. The wiring VCW is arranged in the peripheral area PFA so as to surround the periphery of the display area DA. A fixed potential is supplied to the wiring VCW during both the display period and the touch detection period. Each of the multiple conductor patterns CCP1 is electrically connected to each other via the wiring VCW. In this case, a fixed potential is supplied to each of the multiple conductor patterns CCP1 via the wiring VCW. Therefore, each of the multiple conductor patterns CCP1 is capacitively coupled to the multiple video signal wirings VSW in the wiring region R9, thereby suppressing the generation of noise from the multiple video signal wirings VSW.

[0077] There are various modified methods for supplying a fixed potential to the conductor pattern CCP1 shown in Fig. 8 and Fig. 9. However, by utilizing a wiring that is arranged for another purpose and to which a fixed potential is supplied, such as the wiring VCW shown in Fig. 9, a fixed potential can be easily supplied to the conductor pattern CCP1.

[0078] 9 is an enlarged plan view of the periphery of the boundary between the wiring region R9 and the wiring region R3 shown in FIG. 8, but it can also be applied to the periphery of the boundary between the wiring region R10 and the wiring region R7 shown in FIG. 8. In this case, the description in this section can be applied by replacing the wiring region R9 with the wiring region R10, the wiring region R3 with the wiring region R7, and the conductor pattern CCP1 with the conductor pattern CCP3. If the wiring VCW is arranged in the wiring region R7, the conductor pattern CCP3 and the wiring VCW can be easily electrically connected. If the wiring VCW is not arranged in the wiring region R7, it is preferable that a conductor pattern such as a wiring or an electrode to which some fixed potential is supplied at least during the display period is formed in the wiring region R7, and the conductor pattern CCP3 is connected to this conductor pattern.

[0079] <Routing areas R4 and R8> Next, a detailed description will be given of the structure around the wiring region R4 and the wiring region R8 shown in Fig. 8. Fig. 10 is an enlarged plan view showing a modified example of another part (around the boundary between the wiring region R4 and the wiring region R8) of the wiring region shown in Fig. 8. Fig. 11 is an enlarged plan view showing an example of consideration of Fig. 10. Although Fig. 10 and Fig. 11 are each plan views, in order to easily identify the touch detection wiring TDW and the video signal wiring VSW, the touch detection wiring TDW and the video signal wiring VSW are each hatched.

[0080] As shown in FIG. 11 as a display device DSPc as an example of consideration, when noise countermeasures are not applied to the wiring area R4 and the wiring area R8, the area of ​​the part of the multiple video signal wirings VSW that does not overlap with the touch detection wiring TDW is large. Therefore, from the viewpoint of suppressing noise generation from the part of the multiple video signal wirings VSW that is arranged in the gap between the adjacent touch detection wirings TDW, it is preferable to arrange the conductor pattern CCP (see FIG. 8 or FIG. 10) in this part. In the case of the display device DSP1 shown in FIG. 10, the conductor pattern CCP4 is arranged between the adjacent touch detection wirings TDW. The conductor pattern CCP4 is arranged so as to straddle the boundary between the wiring area R4 and the wiring area R8. This makes it possible to reduce noise generation from the multiple video signal wirings VSW arranged in the wiring area R4 and the wiring area R8.

[0081] In the example shown in FIG. 10, each of the plurality of conductor patterns CCP4 is formed in the wiring layer WL2. Each of the plurality of conductor patterns CCP4 is connected to one of the plurality of touch detection wirings TDW in the wiring layer WL2. In other words, one touch detection wiring TDW is branched into a plurality of conductive patterns CCP4. As described above, a fixed potential (for example, a first potential) is supplied to each of the plurality of touch detection wirings TDW during the display period. When the conductor pattern CCP4 and the touch detection wiring TDW are electrically connected, the fixed potential is also supplied to the conductor pattern CCP4 during the display period. Therefore, the conductor pattern CCP4 can be used as a pattern for noise countermeasures without being connected to another fixed potential supply source.

[0082] There is no particular limitation on the location where the conductor pattern CCP4 is connected to the touch detection wiring TDW. However, from the viewpoint of obtaining a noise suppression effect by the conductor pattern CCP4, it is preferable that the conductor pattern CCP4 extends to the vicinity of the terminal area TMA shown in FIG.

[0083] In the example shown in FIG. 10, in the wiring area R8, one or more of the plurality of conductor patterns CCP4 (two conductor patterns CCP4 in FIG. 10) are arranged between two adjacent touch detection wirings TDW among the plurality of touch detection wirings TDW. However, the number of conductive patterns CCP4 and the line thickness can be appropriately changed, and for example, one thick conductive pattern CCP4 or two or more thin conductive patterns CCP4 can be applied. In this case, the following effects can be obtained. When the conductor pattern CCP4 and the touch detection wiring TDW are electrically connected as in the example shown in FIG. 10, it is necessary to consider the influence of the conductor pattern CCP4 on erroneous detection during the touch detection period. When the area of ​​the touch detection wiring TDW in the peripheral wiring area PFWA is large compared to the area of ​​the electrode CE as the touch detection electrode described with reference to FIG. 5, erroneous detection is likely to occur. Therefore, from the viewpoint of reducing erroneous detection, it is preferable to reduce the area of ​​the touch detection wiring TDW in the peripheral wiring area PFWA.

[0084] 10, when the conductor pattern CCP4 is connected to the touch detection wiring TDW, the conductor pattern CCP4 can be regarded as a part of the touch detection wiring TDW in terms of the circuit. Therefore, from the viewpoint of reducing the area of ​​the conductor pattern CCP4 and overlapping a plurality of video signal wirings VSW over a wide range, it is preferable that the conductor pattern CCP4 arranged between the adjacent touch detection wirings TDW is divided into a plurality of parts.

[0085] Of course, as a modification of the example shown in FIG. 10, there is a method in which the conductor pattern CCP4 is not connected to the touch detection wiring TDW, and a fixed potential is supplied to the conductor pattern CCP4 from a path other than the touch detection wiring TDW. In this case, even if a single conductor pattern CCP4 having a width wider than the wiring width of the touch detection wiring TDW is arranged between adjacent touch detection wirings TDW as shown in FIG. 8, the occurrence of erroneous detection can be suppressed. In addition, in order to suppress the occurrence of erroneous detection, it is certainly preferable to reduce the area of ​​the touch detection wiring TDW in the peripheral wiring area PFWA, but depending on the setting conditions of the touch detection circuit, there are cases in which erroneous detection does not occur even if the conductor pattern CCP4 shown in FIG. 8 is connected to the touch detection wiring TDW. In this case, the conductor pattern CCP4 shown in FIG. 8 may be connected to the touch detection wiring TDW.

[0086] <Method of adding capacitance other than wiring layer WL2> Next, in addition to the noise countermeasures using the conductor pattern CCP described with reference to Figures 7 to 10, a method of arranging a conductor pattern in a layer other than the wiring layer WL2 shown in Figure 7 and capacitively coupling with a plurality of video signal lines VSW will be described. Figure 12 is an enlarged cross-sectional view showing a modification of Figure 7. Figure 13 is an enlarged cross-sectional view showing another modification of Figure 7. Figure 14 is an enlarged cross-sectional view showing another modification of Figure 7.

[0087] The display device DSP2 shown in FIG. 12 differs from the display device DSP1 shown in FIG. 7 in the following points. That is, the peripheral wiring area PFWA of the display device DSP2 further includes a semiconductor film SCF formed between the substrate 10 and the wiring layer WL1. The semiconductor film SCF is disposed at a position overlapping with a part of the multiple video signal wirings VSW, and is capacitively coupled to a part of the multiple video signal wirings VSW. The semiconductor film SCF is made of the same material as the semiconductor layer (not shown) used as the channel layer of the transistor Tr1 shown in FIG. 3. The semiconductor film SCF is, for example, a film made of polysilicon, and is disposed in a portion corresponding to the portion between the insulating film 11 and the insulating film 12. In addition, a fixed potential is supplied to the semiconductor film SCF. The type of potential supplied to the semiconductor film SCF does not matter, but, for example, the semiconductor film SCF is electrically connected to the wiring VCW shown in FIG. 9. In the peripheral wiring area PFWA shown in FIG. 9, a semiconductor film SCF to which a fixed potential is supplied is disposed at a position overlapping with a plurality of video signal wirings VSW, so that each of the plurality of video signal wirings VSW is capacitively coupled to the semiconductor film SCF, as shown in FIG. 12 with a circuit symbol of a capacitor. This makes it possible to reduce noise generated from the plurality of video signal wirings VSW in the peripheral wiring area PFWA. Note that, in the example shown in FIG. 12, an example in which the semiconductor film SCF is formed in the entire peripheral wiring area PFWA is shown, but there are various modified examples of the shape of the semiconductor film SCF. For example, in the peripheral wiring area PFWA, the semiconductor film SCF may be divided into a plurality of parts. In addition, the semiconductor film SCF is electrically separated from the semiconductor layer in the display area DA (see FIG. 1). For example, the semiconductor film SCF is formed only in the peripheral area PFA shown in FIG. 1, and is not formed in the display area DA.

[0088] 13 is different from the display device DSP1 shown in FIG. 7 in the following respects. That is, the peripheral wiring area PFWA of the display device DSP3 further includes a conductor film CDF formed between the substrate 10 and the wiring layer WL1. The conductor film CDF is disposed at a position overlapping with a part of the multiple video signal wirings VSW, and is capacitively coupled with a part of the multiple video signal wirings VSW. The conductor film CDF is, for example, a metal film used as a light shielding film for shielding the peripheral area PFA (see FIG. 1). A fixed potential is also supplied to the conductor film CDF. Although the type of potential supplied to the conductor film CDF does not matter, for example, the conductor film CDF is electrically connected to the wiring VCW shown in FIG. 9. In the peripheral wiring area PFWA shown in FIG. 9, the conductor film CDF to which a fixed potential is supplied is disposed at a position overlapping with the multiple video signal wirings VSW, and as shown in FIG. 13 with a circuit symbol of a capacitor, each of the multiple video signal wirings VSW is capacitively coupled with the conductor film CDF. This makes it possible to reduce noise generated from the multiple video signal wirings VSW in the peripheral wiring area PFWA. Note that, although the example shown in FIG. 13 shows an example in which the conductor film CDF is formed over the entire peripheral wiring area PFWA, there are various modifications to the shape of the conductor film CDF. For example, in the peripheral wiring area PFWA, the conductor film CDF may be divided into multiple parts. Also, for example, the conductor film CDF is formed only in the peripheral area PFA shown in FIG. 1, and is not formed in the display area DA.

[0089] The display device DSP6 shown in FIG. 14 is different from the display device DSP1 shown in FIG. 7 in the following respects. That is, the insulating layer 32h shown in FIG. 14 has a different thickness from the insulating layer 32 shown in FIG. 7. The insulating layer 32h is formed thinner than the insulating layer 32. The insulating layer 32h is an insulating film of an organic resin corresponding to the insulating film 14 shown in FIG. 4, but is formed thinner than the insulating film 14 in the display area DA and the insulating layer 32h in the peripheral area PFWA. By forming the insulating layer 32h thin, when a noise current flows in the video signal wiring VSW that is capacitively coupled with the touch detection wiring TDW among the multiple video signal wirings VSW, the decoupling function of the capacitor coupled to the video signal wiring VSW through which the noise current flows can be made larger than that of FIG. 7, and the noise component can be reduced. The extent to which the insulating layer 32h is made thinner than the insulating film 14 shown in FIG. 4 can be appropriately changed. However, in order to maintain the flatness of the peripheral area PFWA, the thickness of the insulating layer 32h is preferably about half the thickness of the insulating film 14 shown in FIG. 4.

[0090] As in the display device DSP2 shown in FIG. 12, the display device DSP3 shown in FIG. 13, or the display device DSP6 shown in FIG. 14, the value of the capacitance coupled to the video signal wiring VSW can be increased by utilizing the conductor pattern CCP formed in the wiring layer WL2 and the conductor pattern formed in another layer to capacitively couple to a plurality of video signal wirings VSW. As a result, the noise suppression effect can be improved. Note that the examples shown in FIG. 12 and FIG. 13 representatively show the embodiment in the region corresponding to the wiring region R4 and the wiring region R8 shown in FIG. 8. However, the modified examples shown in FIG. 12 and FIG. 13 can also be applied to the wiring region R9, the wiring region R10, and the wiring region R11 shown in FIG. 8.

[0091] Except for the above-mentioned differences, the display device DSP2 shown in Fig. 12 and the display device DSP3 shown in Fig. 13 are similar to the display device DSP1 described with reference to Fig. 1 to Fig. 10. Therefore, a duplicated description will be omitted.

[0092] Next, another method for increasing the capacitance value, which is shown typically using the circuit symbol of the capacitor shown in Fig. 7, will be described. Fig. 15 is an enlarged plan view showing a modified example of the plurality of video signal wirings shown in Fig. 10. Fig. 16 is an enlarged plan view showing another modified example of the plurality of video signal wirings shown in Fig. 10. Each of Fig. 15 and Fig. 16 is an enlarged plan view of a portion corresponding to wiring region R4 shown in Fig. 10.

[0093] The display device DSP4 shown in Fig. 15 and the display device DSP5 shown in Fig. 16 differ from the display device DSP1 shown in Fig. 10 in the following points. That is, in the display device DSP4, the wiring width W1 of each of the multiple video signal wirings VSW in the wiring region R4 is wider than the wiring width W2 of each of the multiple video signal wirings VSW in the wiring region R8. Also, in the display device DSP5, each of the multiple video signal wirings VSW meanders in the wiring region R4. The width (meander width) W3 of the meandering portion of the video signal wiring VSW is wider than the wiring width W2 of each of the multiple video signal wirings VSW in the wiring region R8.

[0094] The capacitance value of the capacitor shown in Fig. 7 increases in proportion to the opposing area between the video signal wiring VSW and the conductor pattern CCP. In the case of the display device DSP4 shown in Fig. 15 and the display device DSP5 shown in Fig. 16, the opposing area between the video signal wiring VSW and the conductor pattern CCP (see Fig. 7) is increased by increasing the area of ​​the video signal wiring VSW in the wiring region R4. By increasing the value of the coupling capacitance formed between the video signal wiring VSW and the conductor pattern CCP, the noise suppression effect can be improved.

[0095] 15 and 16 show an example of a method for increasing the opposing area between the video signal wiring VSW and the conductor pattern CCP (see FIG. 7), but there are various modified methods for increasing the opposing area other than those shown in FIGS. 15 and 16. For example, the shape of the video signal wiring VSW may be a mesh pattern. Alternatively, the shape of the video signal wiring VSW may be the same as the shape of the conductor pattern CCP4 shown in FIG.

[0096] Except for the above-mentioned differences, the display device DSP4 shown in Fig. 15 and the display device DSP5 shown in Fig. 16 are similar to the display device DSP1 described with reference to Fig. 1 to Fig. 10. Therefore, a duplicated description will be omitted.

[0097] Within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds, deletes, or modifies the design of the above-mentioned embodiments, or adds, omits, or modifies the conditions of steps, are also included in the scope of the present invention as long as they include the gist of the present invention. [Industrial Applicability]

[0098] The present invention can be used in a display device. [Explanation of symbols]

[0099] 10,20 Board 10f,20f Front (surface, main surface) 10s1, 10s2, 10s3, 10s4 sides 20b Back (surface, main surface) 11-16 Insulating film 31, 32, 32h, 33 Insulation layer AL1, AL2 alignment film ASW signal selection circuit ASWA Switch Circuit Area ASWS signal selection signal BM light shielding film CCP, CCP1, CCP2, CCP3, CCP4 Conductor pattern CD Common potential supply circuit CDF conductor film CE electrode (touch detection electrode) CFB, CFG, CFR color filters CL1,CL2,CL3,CL4,CL5 Conductive layer CS capacitive element DA display area DM Display Module DP detection circuit DSP1,DSP2,DSP3,DSP4,DSP5,DSP6,DSPc Display device GD Scanning drive circuit (gate drive circuit) GL scanning signal line Gsi Scan signal LQ Liquid crystal layer MP connection circuit MW3,VCW wiring OD1,OD2 optical elements PE pixel electrode PFA surrounding area PFWA peripheral wiring area PFWA Switch Circuit Area PX Pixels PXs Subpixel R1-R11 wiring area SCF Semiconductor film SCP Semiconductor Equipment SD video signal drive circuit SL Video signal line SLM sealing material (adhesive) TCF1,TCF2 Transparent conductive film TDW Touch detection wiring TM1 terminal TMA terminal area TMM Communication Module Tr1 Transistor (transistor element) VS Video signal (video signal) VSW Video signal wiring W1, W2 Wiring width W3 width WL1,WL2 wiring layers

Claims

1. a first substrate having a first side extending in a first direction and a second side opposite to the first side in a second direction perpendicular to the first direction; a display area between the first side and the second side in the second direction; a plurality of touch detection electrodes arranged in a matrix in the first direction and the second direction in the display area; a switch circuit region located between the first side and the display region in the second direction, the switch circuit region including a signal selection circuit; a peripheral wiring area in which a plurality of peripheral wirings are arranged, the peripheral wiring area being between the first side and the switch circuit area in the second direction, the peripheral wirings including a plurality of video signal wirings connected to the signal selection circuit and a plurality of touch detection wirings connected to the plurality of touch detection electrodes; a terminal region located between the first side and the peripheral wiring region in the second direction, the terminal region including a plurality of terminals electrically connected to the plurality of peripheral wirings; having The peripheral wiring area includes: a first insulating layer on the first substrate; a first wiring layer on the first insulating layer; a second insulating layer on the first insulating layer and covering the first wiring layer; a second wiring layer on the second insulating layer; Including, the first wiring layer includes the plurality of video signal lines; The second wiring layer is formed with the touch detection lines and a conductor pattern to which a first potential is supplied, the conductor pattern is disposed at a position overlapping with a portion of the plurality of video signal wirings and is capacitively coupled to the portion of the plurality of video signal wirings; The display device, wherein the plurality of touch detection electrodes are formed on the second insulating layer in the display area.

2. In claim 1, the number of the plurality of video signal wirings is greater than the number of the plurality of touch detection wirings; a plurality of the conductor patterns to which the first potential is supplied are formed in the second wiring layer; The peripheral wiring area includes: a first wiring region in which the plurality of video signal wirings extend in a direction inclined with respect to each of the first direction and the second direction; a second wiring region located between the terminal region and the first wiring region in the second direction, and in which the plurality of video signal lines extend in the second direction; a third wiring area located between the first side and the first wiring area in the second direction, and in which the plurality of video signal lines are not arranged; Including, the plurality of conductor patterns include a first conductor pattern arranged so as to straddle a boundary line between the third wiring region and the first wiring region.

3. In claim 2, The display device, wherein the plurality of conductor patterns include a plurality of the first conductor patterns extending in the second direction so as to straddle a boundary line between the third wiring region and the first wiring region.

4. In claim 3, In the third wiring region, a first potential wiring is arranged in the first wiring layer along a boundary line between the third wiring region and the first wiring region, the first conductor patterns are electrically connected to one another via the first potential wiring.

5. In claim 2, The peripheral wiring area includes: a fourth wiring region in which the plurality of touch detection wirings are arranged adjacent to each other in the second wiring layer in the second wiring region; a fifth wiring region and a sixth wiring region in the second wiring region, in which the touch detection lines are not arranged and which are between the first wiring region and the terminal region in the second direction; Including, In the first direction, the fourth wiring region is between the fifth wiring region and the sixth wiring region, The display device, wherein the plurality of conductor patterns include second conductor patterns arranged in each of the fifth wiring region and the sixth wiring region.

6. In claim 5, the peripheral wiring region includes a seventh wiring region that is adjacent to the sixth wiring region in the first direction and is between the first side and the first wiring region in the second direction, and in which the plurality of video signal lines are not arranged; the plurality of conductor patterns include a third conductor pattern extending in the second direction so as to straddle a boundary line between the seventh wiring region and the first wiring region.

7. In claim 2, The peripheral wiring area includes: a fourth wiring region in which the plurality of touch detection wirings are arranged adjacent to each other in the second wiring layer in the second wiring region; an eighth wiring region in the first wiring region, in which the plurality of touch detection lines extend in the second direction; Including, the plurality of conductor patterns include a plurality of fourth conductor patterns arranged so as to straddle a boundary line between the fourth wiring region and the eighth wiring region.

8. In claim 7, each of the plurality of fourth conductor patterns is electrically connected to one of the plurality of touch detection wirings.

9. In claim 8, in the eighth wiring region, two or more fourth conductor patterns among the plurality of fourth conductor patterns are arranged between two adjacent touch detection wirings among the plurality of touch detection wirings.

10. In claim 1, the number of the plurality of video signal wirings is greater than the number of the plurality of touch detection wirings; a plurality of the conductor patterns to which the first potential is supplied are formed in the second wiring layer; The peripheral wiring area includes: a first wiring region in which the plurality of video signal wirings extend in a direction inclined with respect to each of the first direction and the second direction; a second wiring region located between the terminal region and the first wiring region in the second direction, and in which the plurality of video signal lines extend in the second direction; a ninth wiring region in which the plurality of touch detection lines are not arranged, among the first wiring region; Including, The display device, wherein the plurality of conductor patterns include a fifth conductor pattern arranged in the ninth wiring region.

11. In claim 10, the number of the plurality of video signal wirings is greater than the number of the plurality of touch detection wirings; a plurality of the conductor patterns to which the first potential is supplied are formed in the second wiring layer; The peripheral wiring area includes: an eighth wiring region in the first wiring region, in which the plurality of touch detection lines extend in the second direction; a tenth wiring area in which the touch detection lines are not arranged, the tenth wiring area being included in the first wiring area; Further comprising: the eighth wiring region is between the ninth wiring region and the tenth wiring region; The display device, wherein the plurality of conductor patterns include a sixth conductor pattern arranged in the tenth wiring region.

12. In any one of claims 1 to 11, the peripheral wiring region further includes a semiconductor film formed between the first substrate and the first wiring layer, the semiconductor film is disposed at a position overlapping with a portion of the plurality of video signal wirings, and is capacitively coupled to the portion of the plurality of video signal wirings.

13. In any one of claims 1 to 11, the peripheral wiring region further includes a conductor film formed between the first substrate and the first wiring layer, the conductive film is disposed at a position overlapping with a portion of the plurality of video signal wirings and is capacitively coupled to the portion of the plurality of video signal wirings.

Images