Control and monitoring signal transmission system

Abstract

This control / monitor signal transmission system comprises a plurality of slave stations for performing receipt and delivery of data by a transmission synchronization scheme via a common transmission line with a master station that performs receipt and delivery of data with a control unit. When, in a period between clock voltage regions of a voltage clock signal having a prescribed cycle and duty ratio, the impedance of a circuit composed of a plurality of internal circuits of the slave stations and the transmission line, in a first state of being at a first voltage level that is set to the goal after a voltage level is changed, becomes higher than in a start state before the voltage level is changed, a change to the first voltage level occurs by way of a second voltage level at which the impedance assumes a second state that is lower than the first state.

Description

[Technical field]

[0001] The present invention relates to a control and monitoring signal transmission system that reduces the number of signal lines between a parent station on the controlling side and multiple child stations on the controlled side, connects them with a common transmission line, and transmits data using a transmission synchronization method such as synchronizing with a transmission clock.

[0002] In a system that centrally controls a large number of devices installed in a facility, a method of reducing the number of wires, that is, so-called wiring reduction, is widely implemented.In addition, as a general method of reducing the number of wires, instead of a parallel connection in which each of a plurality of devices installed on the controlled side is directly connected to a control unit installed on the control side, a method is widely adopted in which a master station and a plurality of slave stations each having a function of converting parallel signals and serial signals are connected to the control unit and the plurality of devices, respectively, and data is exchanged between the master station and the plurality of slave stations by serial signals via a common transmission line.

[0003] In addition, a transmission synchronous system, such as a system for transmitting and receiving data by serial signals via a common transmission line, is known, in which data is synchronized by a transmission clock. Various methods have been proposed for transmitting and receiving data between a parent station and multiple child stations by transmission synchronization.

[0004] For example, Japanese Patent Application Laid-Open No. 2002-16621 proposes a control and monitoring signal transmission system in which a parent station outputs a control signal in the first half of one clock cycle, and a child station outputs a signal with a higher frequency than the clock (hereinafter referred to as a "frequency signal") as a monitoring signal in the second half, in a serial pulse voltage signal in which the second half of one clock cycle is the power supply voltage and the first half is a region of a potential different from the power supply voltage.

[0005] Furthermore, Japanese Patent Application Laid-Open No. 2002-152864 proposes a control and monitoring signal transmission system in which, in a serial pulse voltage signal in which the latter half of one clock cycle is the power supply voltage and the first half is a region at a voltage level different from the power supply voltage, the first half of one clock cycle is time-divided and a control signal from a parent station and a monitoring signal from a child station are output to the divided region. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2002-16621 A [Patent Document 2] JP 2002-152864 A Summary of the Invention [Problem to be solved by the invention]

[0007] The clock voltage domain of a serial pulse voltage signal (hereinafter referred to as a "voltage clock signal") for synchronizing a parent station and multiple child stations must maintain a constant voltage level for a certain period of time to function as a clock. In other words, the voltage clock signal must have a duty ratio equal to or greater than a certain value.

[0008] Therefore, as in the above-mentioned conventional technology, a method has been proposed in which a frequency signal is used as a method for using the clock voltage domain (the latter half of one cycle of the clock, which is the power supply voltage in the above-mentioned conventional technology) for data transmission and reception while maintaining the duty ratio of the voltage clock signal at a predetermined value or higher. However, when the frequency signal reaches a high frequency of about 1 MHz, the amplitude of the current change is reduced due to the inductance of the transmission line, or the amplitude becomes unstable due to a transient phenomenon, and detection may not be possible. In other words, the clock voltage domain in the voltage clock signal may not be usable as a domain for data transmission and reception.

[0009] On the other hand, potential changes in the voltage clock signal during the period between clock voltage domains have little effect on synchronization. Therefore, as in the above-mentioned conventional technology, it has been proposed to use the period between clock voltage domains (the domain with a voltage level different from the power supply voltage in the above-mentioned conventional technology) for data transmission between the master station and the slave station. In this case, the voltage clock signal used has a predetermined period in order to execute data transmission between the master station and the slave station during the period between the clock voltage domains.

[0010] However, when the period between the clock voltage domains is used for data transmission between the parent station and the child station, a so-called transient phenomenon occurs in which the voltage level change is dulled due to the impedance of the circuit, etc., when the voltage level changes, and the accuracy of the data transmission decreases due to the influence of this transient phenomenon.

[0011] For example, when changing the voltage level by combining a P-channel MOS FET and a capacitor, the voltage level change is blunted when the voltage clock signal changes from the voltage level of a high-potential clock voltage region to a different voltage level (hereinafter referred to as the "falling edge"). Therefore, if the falling edge of the clock voltage region is used as the base point for synchronization, a deviation in the synchronization timing may occur, causing a voltage level different from the voltage level that should be detected, resulting in an incorrect data value being extracted using the voltage level.

[0012] Furthermore, due to the characteristics of the circuit configuration, the rounding of the voltage level change when changing from a voltage level different from the voltage level of the high-potential clock voltage domain to the voltage level of the clock voltage domain (hereinafter referred to as "rising edge") is small, so that the transition period is shorter than the transition period when falling. Therefore, when extracting a data value using the time width from the synchronization base point (falling edge) to the rising edge, the extracted data value may be incorrect.

[0013] Moreover, since the rounding of the voltage level change is determined by the circuit configuration and is unrelated to the period of the voltage clock signal, the faster the period, the greater the effect on the accuracy of data transmission and reception.

[0014] Therefore, an object of the present invention is to provide a control / monitoring signal transmission system that can improve the accuracy of data exchange by utilizing the period between clock voltage domains of a voltage clock signal having a predetermined period and duty ratio. [Means for solving the problem]

[0015] The control and monitoring signal transmission system according to the present invention includes a master station which transmits and receives data to and from a control unit, and a plurality of slave stations which transmit and receive data to and from the master station by a transmission synchronization method via a common transmission line. In a period between clock voltage domains of a voltage clock signal having a predetermined cycle and duty ratio, when an impedance of a circuit formed of a plurality of internal circuits of the slave stations and the transmission line in a first state where a first voltage level set as a target after changing the voltage level becomes higher than an initial state before changing the voltage level, the impedance is changed to the first voltage level via a second voltage level where the impedance is in a second state where the impedance is lower than the first state. Effect of the Invention

[0016] According to the present invention, when the impedance of a circuit consisting of a plurality of internal circuits and transmission lines of a slave station in a first state where the voltage level is set to a first voltage level set as a target after changing the voltage level becomes higher than the initial state before changing the voltage level, the voltage level is changed to the first voltage level via a second voltage level where the impedance is in a second state lower than the first state, thereby shortening the transition period. That is, it is possible to suppress the deviation in the timing of synchronization caused by the transition period to a small value. Therefore, it is possible to improve the accuracy of data transmission and reception using the period between the clock voltage domains of the voltage clock signal. [Brief description of the drawings]

[0017] [Figure 1] 3 is a time chart of a transmission signal in the embodiment of the control and monitoring signal transmission system according to the present invention. [Diagram 2] FIG. 2 is a system configuration diagram of the embodiment. [Diagram 3] FIG. 2 is a functional block diagram of a master station. [Figure 4] FIG. 2 is a schematic diagram showing a transmission procedure of a transmission signal. [Diagram 5] FIG. 2 is a functional block diagram of an input slave station. [Figure 6] FIG. 4 is a functional block diagram of an output slave station. [Figure 7] 5 is a time chart of a transmission signal in another embodiment of the control and monitoring signal transmission system according to the present invention. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] An embodiment of a control and monitoring signal transmission system according to the present invention will be described. This control and monitoring signal transmission system is for centralized control of a large number of devices installed in a facility such as a factory by a control unit. As shown in Fig. 2, it is composed of a parent station 2 connected to a control unit 1 and common data signal lines DP and DN (hereinafter referred to as transmission lines), and multiple input child stations 4, output child stations 5, and input / output child stations 6 that are installed in the facility to be controlled and connected to the transmission lines. Note that, for convenience of illustration, Fig. 2 shows one of each child station, but there is no limit to the type or number of child stations that can be connected to the transmission lines.

[0019] The input unit 7 to which the input slave station 4 is connected, the output unit 8 to which the output slave station 5 is connected, and the input / output unit 9 to which the input / output slave station 6 is connected are devices arranged within the facility to be controlled.

[0020] Examples of the input unit 7 include, but are not limited to, a reed switch, a microswitch, a push button switch, a photoelectric switch, and various other sensors.

[0021] Examples of the output unit 8 include, but are not limited to, an actuator, a (stepping) motor, a solenoid, a solenoid valve, a relay, a thyristor, and a lamp.

[0022] The input / output unit 9 is a device having the functions of both the input unit 7 and the output unit 8. For example, a device such as a temperature controller, a timer, or a counter has both a function of transmitting information to the parent station 2 and a function of performing an output operation based on data transmitted from the parent station 2.

[0023] The input unit 7 may be an input unit-integrated slave station 70 integrated with the input slave station 4. The output unit 8 may be an output unit-integrated slave station 80 integrated with the output slave station 5.

[0024] The control unit 1 includes a management and judgment means 11 having a calculation function, and an input / output unit 12. The management and judgment means 11 receives data from the master station 2 via the input / output unit 12, and performs necessary calculation processing based on a program stored inside.

[0025] <Master station configuration> 3, the master station 2 includes an output data section 21, a management data section 22, a timing generating section 23, a master station output section 24, a master station input section 25, and an input data section 26. The master station 2 outputs a voltage clock signal having a predetermined period and duty ratio with control data included therein, and extracts monitoring data output from the input slave station 4, the output slave station 5, and the input / output slave station 6 during a period between clock voltage regions of the voltage clock signal, and outputs the data to the input / output unit 12 of the control section 1.

[0026] The output data unit 21 passes the data received from the control unit 1 to the parent station output unit 24 as serial data.

[0027] Based on the data received from the control unit 1, the management data unit 22 passes data required for issuing instructions to the slave stations in a management control data area, which will be described later, to the master station output unit 24 as serial data.

[0028] The timing generating unit 23 comprises an oscillator circuit (OSC) 31 and timing generating means 32 . Based on the oscillator circuit (OSC) 31 , the timing generating means 32 generates a timing clock for this system and passes it to the parent station output unit 24 and parent station input unit 25 .

[0029] The parent station output unit 24 comprises a control data generating means 33 and a line driver 34. The control data generating means 33 outputs a voltage clock signal including control data to the transmission line via the line driver 34 based on the data received from the output data unit 21 and the timing clock received from the timing generating unit 23.

[0030] 1, the voltage clock signal is configured by a series of clock voltage domains in which a voltage level Ep higher than a threshold Est is maintained for a predetermined time period, at a fixed period. In this embodiment, the voltage level Ep is set to +24V.

[0031] The clock voltage domain is not limited as long as it functions as a synchronous clock, and can be appropriately determined according to the usage environment and usage state. For example, it may be a domain in which a negative voltage lower than the ground level is maintained for a predetermined period of time.

[0032] In the period between the clock voltage domains, the data value is represented by a voltage level lower than the voltage level Ep of the clock voltage domain. However, the voltage level representing the data value may be appropriately determined according to the usage environment and usage state, and may be a voltage level higher than the voltage level Ep of the clock voltage domain. The same applies even if the voltage level Ep of the clock voltage domain is a negative voltage lower than the ground level.

[0033] In this embodiment, the impedance of the circuit formed by the internal circuits and transmission lines of all the slave stations 4, 5, and 6 (hereinafter referred to as "transmission circuit impedance") is larger than that of the clock voltage domain in a state (first state) where the voltage level indicates a data value. A transient phenomenon occurs when the voltage level Ep of the clock voltage domain changes to the voltage level indicating the data value.

[0034] The period between the clock voltage domains is divided into four regions. In the following description, the four regions in the period between the clock voltage domains are referred to as I-domain, V-domain, F-domain, and P-domain in the order of proximity to the transition period t in which the voltage level drops from the voltage level Ep of the clock voltage domain.

[0035] In this embodiment, in the I, V, and F regions, a potential lower than the threshold Ect is a voltage level indicating a logical data value of "1," and a potential higher than the threshold Ect is a voltage level indicating a logical data value of "0." In this embodiment, the threshold Ect is set between 10V and the ground level (approximately 6V), but there is no limit to its magnitude and it may be set according to the usage situation and the usage environment. There is no limit to the correspondence between the voltage level indicating the data value and the logical data value, and it may be appropriately determined according to the usage environment and the usage state.

[0036] In this embodiment, the P region is used only for the output from the parent station 2, and a voltage level lower than the threshold Est indicates a logical data value of "1", and a voltage level higher than the threshold Est indicates a logical data value of "0". By increasing the time width of the high voltage level region, that is, by making the duty ratio larger than the set value, the influence of noise is reduced and the stability of the clock function is improved. As with the I region, V region, and F region, there is no restriction on the correspondence between the voltage level indicating the data value and the logical data value, and it can be appropriately determined according to the usage environment and usage state.

[0037] When changing from the voltage level Ep of the clock voltage domain to the voltage level indicating the data value, the voltage drops to the low voltage level GND, which is a state (second state) in which the transmission circuit impedance is lower than the state (first state) in which the voltage level indicates the data value. Then, it changes to the voltage level indicating the data value via the low voltage level GND. Note that the state in which the transmission circuit impedance is lower than the state in which the voltage level indicates the data value can be created, for example, by setting the low voltage level GND to a level that can wipe out the charge and back electromotive force accumulated in the circuit.

[0038] In addition, if, due to the circuit configuration, etc., the transmission circuit impedance at the voltage level indicating the data value is smaller than that of the clock voltage domain, when changing from the voltage level indicating the data value to the voltage level Ep of the clock voltage domain, the voltage will change to the voltage level Ep of the clock voltage domain via a voltage level at which the transmission circuit impedance is lower than that of the clock voltage domain.

[0039] As shown in Figure 4, the transmission procedure is such that one frame cycle is made up of a series of areas between a start signal ST in the voltage clock signal and the next start signal ST, including the management data area, the control and monitoring data area, and the CRC area. The control and monitoring data area is used to transmit and receive regular data between the parent station 2, the input slave station 4, the output slave station 5, and the input / output slave station 6.

[0040] In addition, non-routine data that is not assigned to the control and monitoring data area is sent and received using the management data area. Furthermore, the CRC area is used to determine whether there is a transmission error.

[0041] In the start signal ST, the voltage level Ep of the clock voltage area in the management data area, the control and monitoring data area, and the CRC area is maintained longer than the time width of the clock voltage area. Note that there is no limit to the time width of the start signal ST, and it can be determined appropriately taking into account the conditions of use, etc.

[0042] The master station input unit 25 is made up of a line receiver 35 and a supervisory data extraction means 36. The line receiver 35 receives a voltage clock signal from the transmission line, shapes the waveform, and passes it to the supervisory data extraction means 36.

[0043] The monitoring data extraction means 36 obtains the timing for extracting the data value by utilizing the timing clock delivered from the timing generating unit 23, and extracts the data based on the digital value of the voltage level of the voltage clock signal delivered from the line receiver 35. Then, it delivers it to the input data unit 26 as steady data DIO in the control / monitoring data area and management data DEX in the management data area.

[0044] The input data section 26 converts the serial input data received from the monitoring data extraction means 36 into parallel data, and outputs it to the input / output unit 12 of the control section 1 as monitoring data and management monitoring data.

[0045] <Input slave station configuration> As shown in FIG. 5, the input slave station 4 comprises a slave station input unit 40 which executes main arithmetic processing, and a slave station line receiver 48 and a slave station line driver 49 which are arranged between the slave station input unit 40 and the transmission line. The input slave station 4 receives a voltage clock signal from the transmission line via the slave station line receiver 48, and outputs a supervisory signal to the transmission line via the slave station line driver 49.

[0046] The slave station input unit 40 has a transmission / reception means 41 , a management control data extraction means 42 , an address extraction means 43 , an address setting means 44 , a management monitoring data transmission means 45 , an input means 46 and a monitoring data transmission means 47 .

[0047] In addition, the input slave station 4 in this embodiment has an MCU, which is a microcomputer control unit, as an internal circuit, and this MCU functions as the slave station input section 40.

[0048] The slave station line receiver 48 receives the voltage clock signal from the transmission line, shapes the waveform, and passes it to the transmission / reception means 41 .

[0049] The transmission / reception means 41 discriminates between the voltage level thresholds Est and Ect, and passes the digital value of the voltage level of the voltage clock signal passed from the slave station line receiver 48 to the management control data extraction means 42, the address extraction means 43, and the management monitoring data transmission means 45.

[0050] The management control data extraction means 42 identifies the start signal ST based on the digital value of the voltage level of the voltage clock signal. Then, starting from the timing when the start signal ST ends (in this embodiment, the falling edge), it extracts management data based on the digital value of the voltage level of the inter-pulse area corresponding to the management data area. The extracted management data is passed to a processing means (not shown) that executes processing based on the data.

[0051] The address extraction means 43 identifies the start signal ST based on the digital value of the voltage level of the voltage clock signal, and counts the clock voltage area starting from the timing when the start signal ST ends (in this embodiment, the falling edge). Then, it obtains the timing at which this count value matches the local station address data set by the address setting means 44. This timing is the timing at which the data area assigned to the local station in the voltage clock signal (hereinafter referred to as the "local station area") starts (hereinafter referred to as the "local station area start timing").

[0052] The address extraction means 43 also obtains the timing of the I-region, V-region, and F-region based on the elapsed time from the falling edge of the clock voltage region.

[0053] Then, the address extraction means 43, which has obtained the local station area start timing, activates the monitoring data transmission means 47 for the periods of the I area, V area, and F area assigned to the local station. Note that if the local station area is composed of a plurality of periods between clock voltage areas, the monitoring data transmission means 47 is activated for the period of the power supply voltage area each time the I area, V area, and F area assigned to the local station appears until the local station area ends.

[0054] The management monitoring data transmission means 45 identifies the start signal ST based on the digital value of the voltage level of the voltage clock signal, and outputs a signal in the region set for outputting the monitoring signal among the I region, V region, and F region in the period between the clock voltage regions corresponding to the management data region, starting from the timing when the start signal ST ends.

[0055] The supervisory signal output from the management and supervisory data transmitting means 45 is transmitted only when data to be transmitted to the master station 2 has been handed over from a processing means (not shown).

[0056] The input means 46 passes data based on the input from the input unit 7 to the monitoring data transmission means 47 .

[0057] When the monitoring data transmitting means 47 is validated by the address extracting means 43, it outputs the data passed from the input means 46 to the transmission line via the slave station line driver 49 as a monitoring signal.

[0058] <Output slave station configuration> As shown in Fig. 6, the output slave station 5 comprises a slave station output section 50 which executes main arithmetic processing, and a slave station line receiver 48 and a slave station line driver 49 which are arranged between the slave station output section 50 and the transmission line, and receives a voltage clock signal from the transmission line via the slave station line receiver 48, and outputs a supervisory signal to the transmission line via the slave station line driver 49. In Fig. 6, parts which are substantially the same as those in the input slave station 4 are given the same reference numerals, and their explanation will be simplified or omitted.

[0059] The slave station output unit 50 has a transmission / reception means 41 , a management control data extraction means 42 , an address extraction means 43 , an address setting means 44 , a management / monitoring data transmission means 45 , a control data extraction means 51 and an output means 52 .

[0060] Like the input slave station 4 , the output slave station 5 of this embodiment also has an MCU, which is a microcomputer control unit, as an internal circuit, and this MCU functions as a slave station output section 50 .

[0061] The transmission and receiving means 41 of the output slave station 5 adds the digital value of the voltage level of the voltage clock signal handed over from the slave station line receiver 48 to the management control data extraction means 42, address extraction means 43 and management monitoring data transmission means 45, and further passes it on to the control data extraction means 51.

[0062] The address extraction means 43 of the output slave station 5 obtains the start timing of its own station area by counting the high potential area starting from the timing when the start signal ST ends, and obtains the timing of the P area in its own station area based on the elapsed time starting from the falling edge of the clock voltage area. Note that if the I area, V area, or F area is assigned for output from the master station 2 to its own station, the timing of the I area, V area, or F area is also obtained.

[0063] Then, the address extraction means 43, which has obtained the local station area start timing, activates the monitoring data transmission means 47 for the period of the P area assigned to the local station, and, if an I area, V area, or F area is assigned, for the period of that area. Also, if the local station area is composed of a plurality of periods between clock voltage areas, the monitoring data transmission means 47 is activated for the period of the power supply voltage area each time the I area, V area, F area, or P area assigned to the local station appears until the local station area ends.

[0064] When the control data extraction means 51 is validated by the address extraction means 43 , it extracts control data based on the digital value of the voltage level of the voltage clock signal delivered from the transmission / reception means 41 and delivers it to the output means 52 .

[0065] The output means 52 outputs information based on the control data passed from the control data extraction means 51 to the output unit 8, and operates or stops the output unit 8.

[0066] <Configuration of I / O slave station> The input / output slave station 6 has the functions of both the input slave station 4 and the output slave station 5, and has a slave station input / output section having the configuration of both the slave station input section 40 and the slave station output section 50. However, since its configuration is essentially the same as the slave station input section 40 and the slave station output section 50, illustration and description thereof will be omitted.

[0067] In this embodiment, data values ​​in the I, V, F, and P regions are extracted based on voltage levels detected at predetermined timings in the regions. That is, data is exchanged by making the voltage level of the voltage clock signal correspond to the data value, but data may also be exchanged by making the duty ratio of the voltage clock signal correspond to the data value.

[0068] Fig. 7 is a time chart of a transmission signal in an embodiment in which data is exchanged by making the duty ratio of a voltage clock signal correspond to a data value. In the description of the embodiment shown in Fig. 7, the same reference numerals are used for parts that are substantially the same as those in the embodiment shown in Figs. 1 to 6, and the description thereof will be omitted or simplified.

[0069] In the embodiment shown in Fig. 7, the time width of the clock voltage domain, i.e. the duty ratio of the voltage clock signal, corresponds to the data value. The time width of the clock voltage domain can be obtained by measuring the elapsed time from the falling edge to the rising edge of the clock voltage domain.

[0070] 7, the falling edge of the clock voltage domain, which is the base point of the synchronization timing, is set to a fixed cycle, so when the time width of the clock voltage domain is large, the elapsed time from the falling edge to the rising edge of the clock voltage domain is small, and when the time width of the clock voltage domain is small, the elapsed time from the falling edge to the rising edge of the clock voltage domain is large. Therefore, the length of the time width of the clock voltage domain can be determined based on the length of the elapsed time.

[0071] In Fig. 7, an elapsed time TL longer than a certain threshold indicates a data value "1" corresponding to a small time width, and an elapsed time TS shorter than a certain threshold indicates a data value "0" corresponding to a large time width. There is no restriction on the correspondence between the time width of the clock voltage domain and the data value, and it may be set appropriately according to the usage situation. However, the time width of the clock voltage domain must be a certain width or more necessary to function as a clock, that is, the duty ratio must be larger than the set value of the voltage clock signal. [Explanation of symbols]

[0072] 1. Control section 2 Master station 4 Input slave station 5 Output slave station 6 Input / Output slave station 7 Input section 8 Output section 9 Input / output section 11 Management Judgment Means 12 Input / Output Unit 21 Output data section 22 Management Data Section 23 Timing Generator 24 Master station output section 25 Master station input section 26 Input Data Section 31 Oscillator circuit (OSC) 32 Timing generation means 33 Control data generating means 34 Line Driver 35 Surveillance signal detection means 36 Surveillance Data Extraction Methods 40 Slave station input section 41 Transmission and reception means 42 Management control data extraction means 43 Address Extraction Method 44 Address setting method 45 Management and monitoring data transmission means 46 Input Methods 47 Monitoring data transmission means 48 Slave line receiver 49 Slave station line driver 50 Slave unit output section 51 Control data extraction means 52 Output Means 70 Input unit integrated slave station 80 Output section integrated slave unit

Claims

1. A master station that transmits and receives data to and from a control unit, and a plurality of slave stations that transmit and receive data to and from the master station by a transmission synchronous method via a common transmission line, During a period between clock voltage domains of a voltage clock signal having a predetermined period and a predetermined duty ratio, a control and monitoring signal transmission system, characterized in that, when an impedance of a circuit formed of internal circuits of the plurality of slave stations and the transmission line in a first state in which a first voltage level set as a target after the voltage level is changed becomes higher than the impedance in a starting state before the voltage level is changed, the voltage level is changed to the first voltage level via a second voltage level in which the impedance is in a second state in which it is lower than the first state.

2. 2. The control and supervisory signal transmission system according to claim 1, wherein the period between said clock voltage domains is time-divided into three or more domains.

3. 3. The control and monitoring signal transmission system according to claim 2, wherein in a period between said clock voltage domains, a timing at which the voltage level of said clock voltage domain changes is advanced, and a region in which the duty ratio is greater than said predetermined duty ratio is provided.

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