Apparatus and method for synchronous serial data transmission - Patents.com

Abstract

The present invention relates to a device 30 for synchronous serial data transmission over a differential data channel 62 and a differential clock channel 60. The device comprises an interface controller 40 having a clock generator 44 and a data controller 42, a clock transmission module 50, and a data reception module 54, in which: a transmitter clock signal CLK_S comprising a periodic pulse train TP having a periodic duration T during a data transmission period can be generated by said clock generator 44; the transmitter clock signal CLK_S is supplied to the clock transmitter module 50, which converts the transmitter clock signal CLK_S into a differential clock signal C+, C− for output via the clock channel 60; the differential data signals D+, D− arriving via the differential data channel 62 are supplied to the data receiving module 54, which converts the differential data signals D+, D− into a data signal DT and supplies it to the data controller 42, The transmitter clock signal CLK_S is supplied to the data controller 42 for synchronization with the input of the data signal DT. The clock generator 44 is suitably configured to set the length of the first clock period TH1 of the first clock period T1 of the clock pulse train TP to be longer than the first clock period TH of the subsequent clock period and shorter than the period required to reach the maximum differential voltage UDmax during a data transmission period in a dynamic operating state in which the maximum differential voltage generated by the differential clock signals C+, C- is smaller than the maximum differential voltage UDmax of the clock transmission module 50. Furthermore, the present invention relates to a method for synchronously transmitting serial data (FIG. 1).

Description

[Technical field]

[0001] The invention relates to an apparatus and a method for synchronous serial data transmission according to claims 1 or 6. Furthermore, the invention relates to a subsequent electronic unit according to claim 11. The invention is highly advantageous in automation technology applications, since here data transmission over long cables is often necessary. [Background technology]

[0002] In automation technology, measuring instruments that process digital values ​​are frequently used. For example, in the field of numerical controls used to control machine tools, the automation technology applies in particular to encoders for measuring linear or rotary movements. Encoders that generate digital (absolute) measurement values ​​are called absolute encoders.

[0003] For transmitting absolute position values ​​and other data, the use of serial data transmission is becoming mainstream, since it requires only a small number of data transmission cables and nevertheless has a high data transmission rate. In many cases, the data transmission is carried out over long cable lengths, so that the interface signals are transmitted differentially, for example according to the RS485 standard. For this purpose, on the transmitter side, single-ended digital signals are converted into differential signals and output by a special driver module. On the receiver side, the transmitted signals are reconverted in the receiver module for further processing. The transmission is carried out via cable pairs, in which several cables are twisted together.

[0004] Particularly useful are so-called synchronous serial interfaces, which have a data cable pair and a clock cable pair that are driven unidirectionally or bidirectionally. Data packets are transmitted over the data cable pair in a synchronous manner with respect to the clock signal on the clock cable pair. The automation technology recognizes a large number of such digital standard interfaces. A popular product for a synchronous serial interface is, for example, the Applicant's EnDat interface. Other interfaces are known under the type designation SSI.

[0005] The SSI interface is described in EP 0 171 579 A1. It is a synchronous serial data interface having one unidirectionally driven data cable pair and a unidirectionally driven clock cable pair, in which position values ​​are read out from the encoder synchronously with respect to a clock signal transmitted over the clock cable pair.

[0006] In contrast, EP 0 660 209 A1 describes the principle of the EnDat interface of the present application. This EnDat interface is likewise a synchronous serial interface. However, in addition to the unidirectionally driven clock cable pair, it has a bidirectionally driven data cable pair. This allows data transmission in both directions - from the subsequent electronic unit (e.g. a numerical control device) to the encoder and from the encoder to the subsequent electronic unit. Here too, the data transmission is carried out synchronously with respect to the clock signal.

[0007] In addition to the ohmic resistance, the cable pair used for the transmission also has capacitive and electromagnetic inductive properties that depend on the cable pair. In this connection, the transmission technology takes into account the capacitance per unit length and the inductance per unit length. During data transmission, several transient phenomena arising from these properties distort the transmitted signal. The maximum cable length that allows reliable transmission and achieves a certain data rate is therefore determined by the performance of the differential receiver at the receiver side, which requires as a prerequisite the recovery of the originally transmitted digital signal from the received signal. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] European Patent Application Publication No. 0171579 [Patent Document 2] European Patent Application Publication No. 0660209 Summary of the Invention [Problem to be solved by the invention]

[0009] SUMMARY OF THE DISCLOSURE The object of the invention is to provide a device for increasing the maximum cable length in the case of a synchronous serial interface.

[0010] It is a further object of the invention to provide a method for increasing the maximum cable length in the case of a synchronous serial interface. [Means for solving the problem]

[0011] This problem is solved by a device according to claim 1.

[0012] An apparatus for synchronous serial data transmission via differential data channels and differential clock channels is proposed, comprising an interface controller with a clock generator and a data controller, a clock transmission module and a data reception module, in which: a transmitter clock signal comprising a periodic pulse train having a periodic duration during a data transmission period is generateable by said clock generator; the transmitter clock signal is provided to the clock transmit module, which converts the transmitter clock signal into a differential clock signal for output via the clock channel; a differential data signal arriving via said differential data channel is provided to said data receiving module, which converts said differential data signal into a data signal and provides it to said data controller, The transmitter clock signal is provided to the data controller for synchronizing with the input of the data signal.

[0013] According to the present invention, during a data transmission period in a dynamic operating state in which the maximum differential voltage generated by the differential clock signal is smaller than the maximum differential voltage of the clock transmission module, the clock generator is appropriately configured to set the length of the first clock period of the first clock period of the clock pulse train to be longer than the first clock period of the subsequent clock period and shorter than the period required to reach the maximum differential voltage.

[0014] This problem is solved by the method according to claim 6.

[0015] A method is proposed for synchronous serial data transmission via differential data channels and differential clock channels by means of an apparatus comprising an interface controller with a clock generator and a data controller, a clock transmission module and a data reception module, in which: a transmitter clock signal comprising a periodic pulse train having a periodic duration during a data transmission period is generated by said clock generator; - the transmitter clock signal is provided to the clock transmit module, which converts the transmitter clock signal into a differential clock signal for output via the clock channel; a differential data signal arriving via said differential data channel is provided to said data receiving module, which converts said differential data signal into a data signal and provides it to said data controller; The transmitter clock signal is provided to the data controller for synchronizing with the input of the data signal.

[0016] According to the present invention, during a data transmission period in a dynamic operating state (DYN), the clock generator (44) is appropriately configured to set the length of the first clock period (TH1) of the first clock period (TH) of the clock pulse train, in which the maximum differential voltage generated by the differential clock signal (C+, C-) is smaller than the maximum differential voltage (UDmax) of the clock transmitting module (50), to be longer than the first clock period of the subsequent clock period and shorter than the period required to reach the maximum differential voltage. [Brief description of the drawings]

[0017] [Figure 1] FIG. 2 is a block diagram of the device of the present invention in a subsequent electronic unit. [Diagram 2] 2 shows a schematic signal diagram of the transmission of a transmitter clock signal in the case of a long cable length L according to the prior art; [Diagram 3] 2 shows a schematic signal diagram according to the invention for the transmission of a transmitter clock signal CLK_S in the case of a long cable length L; [Figure 4a] FIG. 1 is a block diagram of a first embodiment of a clock generator according to the present invention. [Figure 4b] FIG. 4 is a block diagram of another embodiment of a clock generator of the present invention. [Figure 4c] FIG. 4 is a block diagram of another embodiment of a clock generator of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] 1 shows a block diagram of a subsequent electronic unit 10 which is connected for data transmission purposes to an encoder 100 by means of an interface connection having a clock channel 60 and a data channel 62. To control said data transmission, a master interface 30 is provided on the subsequent electronic unit 10 side, which constitutes the device of the invention and communicates with a slave interface 120 of the encoder 100. The master interface 30 is configured as a synchronous serial interface. In this case, the data transmission is carried out differentially, for example according to the RS485 standard. The clock channel 60 and the data channel 62 each therefore comprise one cable pair.

[0019] The subsequent electronic unit 10 is an automation technology device, for example a numerical control device of a machine tool, a control device of an industrial robot, a position indicator or other system control device. The subsequent electronic unit 10 has a program-controlled central control device 20 configured as a computer. The subsequent electronic device 10 thus has at least one microprocessor or microcontroller and a number of memory devices and may have various further interfaces, for example for connecting peripheral devices (keyboard, mouse, monitor, etc.). A power device may be associated with the control device 20, for example for controlling an electric motor. In addition to the illustrated master interface 30, naturally further master interfaces according to the invention may be provided for connecting further encoders.

[0020] The encoder 100 may be configured as a rotary encoder, an angle measuring device, a length measuring device or any other position encoder generating absolute position values. The encoder 100 comprises a position detection device 110 which is suitable for generating a number of position-dependent signals by scanning a measuring graduation by means of a scanning device, calculating a number of absolute position values ​​therefrom and transmitting them to the subsequent electronic unit 10 via the slave interface 120 upon request of the master interface 30. Furthermore, a storage device may be provided in the encoder 100 in which further data can be stored. Similarly, the further data may also be transmitted from the subsequent electronic unit 10 via the slave interface 120 and transmitted to the subsequent electronic unit 10.

[0021] The master interface 30 comprises an interface controller 40 with a clock generator 44 and a data controller 42, a clock transmission module 50, an (optional) data transmission module 52 and a data reception module 54. The interface controller 40 of the master interface 30 is connected to the control device 20 via an internal interface 25. The internal interface 25 allows communication between the control device 20 and the interface controller 40. Thus, commands and possibly data that have to be sent from the control device 20 to the encoder 100 can be transmitted to the interface controller 40. Data arriving at the master interface 30 from the encoder 100 can be forwarded from the interface controller 40 via the internal interface 25 to the control device 20 for further processing. Thus, the communication of the master interface 30 via the clock channel 60 and the data channel 62 is controlled by the control device 20 via the internal interface 25.

[0022] The clock generator 44 generates a transmitter clock signal CLK_S, which is transmitted to the encoder 100 on the one hand and is supplied to the data controller 42 on the other hand. The transmitter clock signal CLK_S has a constant level between two data transmission periods. The clock generator 44 outputs a train of clock pulses via the transmitter clock signal CLK_S during one data transmission period.

[0023] The data controller 42 is suitably configured, on the one hand, to transmit commands and possibly data to the encoder 100, and on the other hand, to receive data from the encoder 100. A bidirectional data signal DT is output or input serially and synchronously with respect to the transmitter clock signal CLK_S.

[0024] To transmit the transmitter clock signal CLK_S through the clock channel 60, the transmitter clock signal CLK_S is fed to a clock transmission module 50. The clock transmission module 50 converts the single-ended signal into a differential clock signal consisting of a non-inverted clock signal C+ and an inverted clock signal C-. Such a module is also called a differential driver.

[0025] To output a (likewise single-ended) data signal DT, the data signal DT is fed to a data transmission module 52, which generates from the data transmission module 52 a differential data signal consisting of a non-inverted data signal D+ and an inverted data signal D-. To receive data, the differential data signal D+, D- is fed to a data reception module 54 (differential receiver), which generates again from the data reception module 54 a single-ended digital data signal DT. To avoid signal collisions, a data direction signal TR is provided. By means of the data direction signal TR, the data controller 42 activates the respective module (data reception module 54 or data transmission module 52) or switches it to high impedance. When and which module has to be activated is defined by the interface protocol.

[0026] On the encoder 100 side, the differential clock signals C+, C- are fed to a clock receiving module 150, which reconverts the differential clock signals C+, C- into a single-ended signal, which is fed as a receiver clock signal CLK_R to an interface controller 130 for synchronizing the data inputs or outputs, which corresponds to the interface controller 40 of the subsequent electronic unit. On the one hand, the differential data signals D+, D- are fed to a data receiving module 154, which reconverts the differential data signals D+, D- into a single-ended signal DT. On the other hand, a data transmitting module 152 is provided, which converts the data signals DT to be output for transmission to the subsequent electronic unit 10 in the opposite data direction into differential data signals D+, D-. Here again, the data direction is set by a data direction signal TR, which is switched according to the interface protocol.

[0027] A data request command of the subsequent electronic unit 10 that arrives at the slave interface 120 is in turn provided to the position detection device 110 via the internal interface 115. The position detection device 110 prepares the requested data and forwards it to the slave interface 120. The arriving data is likewise forwarded via the internal interface 115 to the position detection device 110, where it is processed or stored.

[0028] The depicted encoder 100 is therefore suitable for carrying out the bidirectional data transmission described in EP-A-0 660 209.

[0029] Alternatively, the encoder 100 may be constructed according to EP 0 171 579. In this case, the data receiving module 154 (and the corresponding data transmitting module 52 of the subsequent electronic unit) may be omitted. As a result, data transmission is performed in one direction.

[0030] In both cases, the clock channel 60 is unidirectional, i.e. the clock signal CLK_S is transmitted from the master interface 30 to the slave interface 120. According to the basic principles of synchronous serial data transmission, the serial transmission data bits are synchronized on the data channel 62 by the transmit clock signal CLK_S transmitted via the clock channel 60. In this case, during one data transmission period, one data bit is transmitted or read per clock period of the clock pulse train output via the transmitter clock signal CLK_S. It can therefore be seen that only the frequency of said clock pulse train is the limiting factor for the achievable cable length L between the subsequent electronic unit 10 and the encoder 100, since the maximum frequency that can occur in the data signal DT corresponds only to half the clock frequency of the transmitter clock signal CLK_S. In other words, as long as the transmission path of the transmitter clock signal CLK_S (differential driver, cable pair, differential receiver) and the transmission path of the data signal DT (differential driver, cable pair, differential receiver) have approximately the same characteristics, reliable data transmission can be performed if the clock pulse train of the transmitter clock signal CLK_S can be restored at the receiver side (at the encoder 100 side) (as the receiver clock signal CLK_R).

[0031] 2 shows a schematic signal diagram of the prior art for transmitting a transmitter clock signal CLK_S from a subsequent electronic unit 10 to an encoder 100 in the case of a long cable length L. However, the time delay of the receiver clock signal CLK_R recovered at the encoder 100 resulting from the cable length L is not shown. Only the effect of differential transmission and recovery on the encoder 100 side is shown.

[0032] The train of clock pulses of the transmitter clock signal CLK_S, generated during data transmission in a conventional clock generator, has a constant frequency determined by the period T. The clock period is symmetrical, i.e. the high amplitude period TH and the low amplitude period TL of each period are of equal length and each amplitude period corresponds to T / 2.

[0033] In the period when no data is transmitted, the transmitter clock signal CLK_S has a constant logic level, in the illustrated example a low level. As a result, the differential clock signals C+, C- exhibit a maximum differential voltage UDmax. The receiver clock signal CLK_R, which is reconstructed in the encoder 100 from said clock signals C+, C-, likewise has a constant low logic level. The clock channel 60 is therefore in a static operating state STAT. In the case of a long cable length L, relative to the time at which a clock pulse train is transmitted, i.e. relative to the time at which data is transmitted, said clock pulse train no longer reaches the maximum differential voltage UDmax during the duration of said signal period. That is to say, multiple transients of the cable pair of the clock channel 60 are superimposed. Only when the clock signal CLK_R again transitions to a static level after a data transmission period is said cable pair again charged to the maximum differential voltage UDmax. From the time at which the first clock pulse for transmitting data is output until the static operating state STAT is reached again after said data transmission, the clock channel 60 is in a dynamic operating state DYN.

[0034] Since the clock receiver module 150 recovers the receiver clock signal CLK_R from the non-inverted clock signal C+ and the inverted clock signal C-, it can be seen that the pulse duration of the recovered first pulse (first high amplitude period TH1) is shortened by the higher differential voltage that must be applied with the first pulse (in the illustrated example, first high amplitude period TH1) of the clock train of the data transmission in order to cause a level change in the receiver clock signal CLK_R. The first low amplitude period TL1 of the recovered signal is slightly longer because the differential voltage at the end of the first pulse is smaller due to the shortened pulse duration. The other pulses are approximately aligned with the clock pulse train of the transmitter clock signal CLK_S.

[0035] If the initial high amplitude period TH1 of the receiver clock signal CLK_R becomes shorter, the clock signal can no longer be evaluated accurately, as a result of which errors occur during data transmission.

[0036] FIG. 3 shows a schematic signal diagram according to the invention for the transmission of the transmitter clock signal CLK_S from the subsequent electronic unit 10 to the encoder 100 in the case of a long cable length L. A data transmission cycle is carried out in a dynamic operating state DYN, i.e. the maximum differential voltage UDmax of the differential clock signals C+, C- is not reached. According to the invention, for generating the transmitter clock signal CLK_S, the clock generator 44 is configured to increase the length of the first clock period of the first clock period T1 of the clock pulse train TP of the data transmission cycle. As a result, a corresponding clock period (high amplitude period TH1) of the first clock period T1 of the restored clock pulse train can be evaluated again on the encoder 100 side. However, the length of said first clock period (first high amplitude period TH1) must not be increased so much that the differential clock signals C+, C- reach the maximum differential voltage UDmax.

[0037] This solution is premised on the realization that if the frequency of the clock pulse train TP of the transmitter clock signal CLK_S remains unchanged and the cable length L increases, errors will arise only from the first clock period of the clock pulse train, while all other clock periods can be accurately restored at the receiver side (i.e., at the encoder 100 side).

[0038] Furthermore, the data signal DT is transmitted and received synchronously both on the subsequent electronic unit 10 side and on the encoder 100 side with respect to the assigned clock edge of the transmitter clock signal CLK_S or the receiver clock signal CLK_R. Therefore, no adaptation of the data controller 42 is necessary. Therefore, only the data signal DT is shown in Fig. 3. In the illustrated case, it is scanned with the falling edge of the receiver clock signal CLK_R.

[0039] 4a is a block diagram of a first embodiment of a clock generator 44 of the present invention. The clock generator 44 has a clock output device 46 and at least one register 48.

[0040] The clock output device 46 is configured to output a transmitter clock signal CLK_S. For this purpose, the length of the first clock period (first high amplitude period TH1) of the clock pulse train TP is stored in a register 48. Information about the normal clock pulses of the clock pulse train TP, such as the length of the high amplitude period TH1 and the length of the low amplitude period TL or the period duration T in case of a symmetrical clock signal, can be stored in at least one further register 49. A running clock signal CLK used as a time reference for generating the clock pulse train TP and a start signal for starting the output of the clock pulse train TP are supplied to the clock output device 46.

[0041] To generate the clock pulse train TP, for example a counter may be provided in the clock output device 46. The counter counts per time grid of the running clock signal CLK and outputs the required logic level per period of the values ​​stored in the registers 48, 49.

[0042] Preferably, the value of the register 48 can be written by the control device 20 of the subsequent electronic unit 10. In this way it is possible to adapt to different cable lengths L, cable specifications, frequencies of the transmitter clock signal CLK_S etc.

[0043] The length of the first clock period can be determined by calculation, measurement and step-by-step approximation (successive approximation method).

[0044] 4b is a block diagram of another embodiment of the clock generator 44 of the invention. Here, the cable length L is recorded in a register 48 and the clock output device 46 determines the required length of the first clock period by calculation or by selecting from a table (preferably, the value of said period is already determined and stored at the manufacturer's side). If the clock frequency of the transmitter clock signal CLK_S is variable, said variable frequency can be taken into account as well, e.g. by storing the duration of the high amplitude period TH and / or the length of the low amplitude period TL, or the period duration T, in another register 49 and supplying it to the clock output device 46.

[0045] Fig. 4c is a block diagram of yet another embodiment of a clock generator 44 according to the invention. Here, only a constant K is stored in a register 48. The clock output device 46 sets the length of the first clock period TH1 of the transmitter clock signal CLK_S on the basis of this constant K. The length of this first clock period TH1 may be a multiplier that determines the extension of the first clock period TH1 from the normal clock period TH, i.e. TH1=K*TH. The constant K is selected such that for at least one frequency of the clock pulse train TP of the transmitter clock signal CLK_S, an error-free transmission is possible up to a predefined maximum cable length, which is longer than the cable length achievable with a master interface 30 that is not improved according to the invention. A value for the first clock period that has been demonstrated to achieve a longer cable length L compared to the prior art is twice the duration of the normal clock period TH of the transmitter clock signal CLK_S. If the first clock period is the high amplitude period TH1 shown in Fig. 3, then TH1=2*TH. The present application relates to the invention described in the claims, but may also include the following configurations as other aspects. 1. An apparatus (30) for synchronous serial data transmission over a differential data channel (62) and a differential clock channel (60), comprising an interface controller (40) having a clock generator (44) and a data controller (42), a clock transmission module (50) and a data reception module (54), a transmitter clock signal (CLK_S) comprising a periodic pulse train (TP) having a periodic duration (T) during a data transmission period can be generated by said clock generator (44); - the transmitter clock signal (CLK_S) is provided to the clock transmission module (50) which converts the transmitter clock signal (CLK_S) into a differential clock signal (C+, C-) for output via the clock channel (60); - a differential data signal (D+, D-) arriving via the differential data channel (62) is supplied to the data receiving module (54) which converts the differential data signal (D+, D-) into a data signal (DT) and supplies it to the data controller (42), In the device (30), the transmitter clock signal (CLK_S) is provided to the data controller (42) for synchronization with the input of the data signal (DT), The device (30), in which the clock generator (44) is appropriately configured to set the length of a first clock period (TH1) of a first clock period (T1) of the clock pulse train (TP) to be longer than the first clock period (TH) of a subsequent clock period and shorter than the period required to reach the maximum differential voltage (UDmax) during a data transmission period in a dynamic operating state in which the maximum differential voltage generated by the differential clock signals (C+, C-) is smaller than the maximum differential voltage (UDmax) of the clock transmission module (50). 2. The clock generator (44) - one register (48) in which the length of said first clock period (TH1) can be stored; at least one further register (49) in which information regarding the correct clock pulses of said clock pulse train (TP) can be stored; - one clock output device (46) for outputting said clock pulse train (TP) from said information stored in said registers (48, 49) as a result of a start command (START). 3. The clock generator (44) - one register (48) in which the cable length (L) can be stored; at least one further register (49) in which information regarding the correct clock pulses of said clock pulse train (TP) can be stored; - one clock output device (46) for calculating the length of the first clock period (TH1) based on the cable length (L) and on information about the correct clock pulses of the clock pulse train (TP) and for outputting the clock pulse train (TP) as a result of a start command (START). 4. The clock generator (44) one register (48) in which a constant (K) can be stored; at least one further register (49) in which information regarding the correct clock pulses of said clock pulse train (TP) can be stored; - one clock output device (46) for calculating the length of the first clock period (TH1) based on information about the normal clock pulses of the clock pulse train (TP) and on the constant (K) as a multiplier, and for outputting the clock pulse train (TP) as a result of a start command (START). 5. The device (30) according to any one of 1 to 4 above, wherein the data signal (DT) is configured bidirectionally, a data transmission module (52) is provided for converting the data signal (DT) to be output into a differential data signal (D+, D-), and the data controller (42) generates a data direction signal (TR) for setting the data direction of the differential data channel (62) in accordance with an interface protocol. 6. A method for synchronously transmitting serial data over a differential data channel (62) and a differential clock channel (60) by an apparatus (30) including an interface controller (40) having a clock generator (44) and a data controller (42), a clock transmission module (50) and a data reception module (54), comprising: a transmitter clock signal (CLK_S) comprising a periodic pulse train (TP) having a periodic duration (T) during a data transmission period is generated by said clock generator (44); - the transmitter clock signal (CLK_S) is provided to the clock transmission module (50) which converts the transmitter clock signal (CLK_S) into a differential clock signal (C+, C-) for output via the clock channel (60); - a differential data signal (D+, D-) arriving via the differential data channel (62) is supplied to the data receiving module (54) which converts the differential data signal (D+, D-) into a data signal (DT) and supplies it to the data controller (42); The method, wherein the transmitter clock signal (CLK_S) is provided to the data controller (42) for synchronization with the input of the data signal (DT), The method, in which the clock generator (44) is appropriately configured to set the length of a first clock period (TH1) of a first clock period (T1) of the clock pulse train (TP) to be longer than the first clock period (TH) of a subsequent clock period and shorter than the period required to reach the maximum differential voltage (UDmax) during a data transmission period in a dynamic operating state in which the maximum differential voltage generated by the differential clock signals (C+, C-) is smaller than the maximum differential voltage (UDmax) of the clock transmitting module (50). 7. The clock generator (44) - one register (48) in which the length of said first clock period (TH1) is stored; at least one further register (49) in which information regarding the correct clock pulses of said clock pulse train (TP) is stored; - one clock output device (46) for outputting said clock pulse train (TP) from said information stored in said registers (48, 49) as a result of a start command (START). 8. The clock generator (44) - one register (48) in which the cable length (L) is stored; at least one further register (49) in which information regarding the correct clock pulses of said clock pulse train (TP) is stored; - one clock output device (46) for calculating the length of the first clock period (TH1) based on the cable length (L) and information about the normal clock pulses of the clock pulse train (TP) and for outputting the clock pulse train (TP) as a result of a start command (START). 9. The clock generator (44) one register (48) in which a constant (K) is stored; at least one further register (49) in which information regarding the correct clock pulses of said clock pulse train (TP) is stored; - one clock output device (46) for calculating the length of the first clock period (TH1) based on information about normal clock pulses of the clock pulse train (TP) and the constant (K) as a multiplier, and for outputting the clock pulse train (TP) as a result of a start command (START). 10. A method according to any one of claims 6 to 9, wherein the data signal (DT) is configured bidirectionally, a data transmission module (52) is provided for converting the data signal (DT) to be output into a differential data signal (D+, D-), and a data direction signal (TR) is generated by the data controller (42) to set the data direction of the differential data channel (62) in accordance with an interface protocol. 11. A subsequent electronic unit comprising an apparatus (30) according to any one of 1 to 5 above, further comprising a control device (20) connected to an interface controller (40) of the apparatus (30) via an internal interface (25). [Explanation of symbols]

[0046] 10 Trailing Electronic Unit 20 Control device 25 Internal Interfaces 30 Master Interface 40 Interface Controller 42 Data Controller 44 Clock Generator 46 Clock Output Device 48 Registers 49 Another Register 50 Clock transmission module 52 Data transmission module 54 Data Reception Module 60 Clock Channels 62 Data Channels 100 Encoder 110 Position detection device 115 Internal Interface 120 Slave Interface 130 Interface Controller 150 Clock Receiver Module 152 Data transmission module 154 Data Reception Module L Cable length CLK_S Transmitter clock signal CLK_R Receiver clock signal DT Data Signal TR Data direction signal C+, C- Differential clock signal T cycle period TH High amplitude period TL low amplitude period UDmax Maximum differential voltage STAT Static operating status DYN Dynamic Operating State TP Clock Pulse Train T1 Clock Period CLK Operating clock signal K constant START start command

Claims

1. An apparatus (30) for synchronous serial data transmission over a differential data channel (62) and a differential clock channel (60), comprising an interface controller (40) having a clock generator (44) and a data controller (42), a clock transmission module (50) and a data reception module (54), a transmitter clock signal (CLK_S) comprising a train of clock pulses (TP) having a period duration (T) during a data transmission period can be generated by said clock generator (44); - the transmitter clock signal (CLK_S) is fed to the clock transmission module (50) which converts the transmitter clock signal (CLK_S) into a differential clock signal (C+, C-) for output via the clock channel (60); - a differential data signal (D+, D-) arriving via said differential data channel (62) is fed to said data receiving module (54) which converts said differential data signal (D+, D-) into a data signal (DT) and feeds it to said data controller (42), In said device (30), said transmitter clock signal (CLK_S) is supplied to said data controller (42) for synchronizing with the input of said data signal (DT), The clock generator (44) is appropriately configured to set the length of a first clock period (TH1) of a first clock period (T1) of the clock pulse train (TP) to be longer than the first clock period (TH) of a subsequent clock period and shorter than the period required to reach the maximum differential voltage (UDmax) during a data transmission period in a dynamic operating state in which the maximum differential voltage generated by the differential clock signals (C+, C-) is smaller than the maximum differential voltage (UDmax) of the clock transmission module (50).

2. The clock generator (44) one register (48) in which the length of said first clock period (TH1) can be stored; at least one further register (49) in which information regarding the correct clock pulses of said clock pulse train (TP) can be stored; A clock output device (46) for outputting said clock pulse train (TP) from said information stored in said registers (48, 49) as a result of a start command (START).

3. The clock generator (44) - one register (48) in which the cable length (L) can be stored; at least one further register (49) in which information regarding the correct clock pulses of said clock pulse train (TP) can be stored; - one clock output device (46) for calculating the length of the first clock period (TH1) based on the cable length (L) and on information about the normal clock pulses of the clock pulse train (TP) and for outputting the clock pulse train (TP) as a result of a start command (START).

4. The clock generator (44) one register (48) in which a constant (K) can be stored; at least one further register (49) in which information regarding the correct clock pulses of said clock pulse train (TP) can be stored; - one clock output device (46) for calculating the length of the first clock period (TH1) based on information about the normal clock pulses of the clock pulse train (TP) and on the constant (K) as a multiplier, and for outputting the clock pulse train (TP) as a result of a start command (START).

5. The device (30) according to any one of claims 1 to 4, wherein the data signal (DT) is configured bidirectionally, and a data transmission module (52) is provided for converting the data signal (DT) to be output into a differential data signal (D+, D-), and the data controller (42) generates a data direction signal (TR) for setting the data direction of the differential data channel (62) in accordance with an interface protocol.

6. A method for synchronously transmitting serial data over a differential data channel (62) and a differential clock channel (60) by an apparatus (30) comprising an interface controller (40) having a clock generator (44) and a data controller (42), a clock transmission module (50) and a data reception module (54), comprising: a transmitter clock signal (CLK_S) comprising a train of clock pulses (TP) having a period duration (T) during a data transmission period is generated by said clock generator (44); - the transmitter clock signal (CLK_S) is fed to the clock transmission module (50) which converts the transmitter clock signal (CLK_S) into a differential clock signal (C+, C-) for output via the clock channel (60); - a differential data signal (D+, D-) arriving via said differential data channel (62) is fed to said data receiving module (54) which converts said differential data signal (D+, D-) into a data signal (DT) and feeds it to said data controller (42); said method, in which the transmitter clock signal (CLK_S) is provided to the data controller (42) for synchronization with the input of the data signal (DT), The clock generator (44) is appropriately configured to set the length of a first clock period (TH1) of a first clock period (T1) of the clock pulse train (TP) to be longer than the first clock period (TH) of a subsequent clock period and shorter than the period required to reach the maximum differential voltage (UDmax) during a data transmission period in a dynamic operating state in which the maximum differential voltage generated by the differential clock signals (C+, C-) is smaller than the maximum differential voltage (UDmax) of the clock transmission module (50).

7. The clock generator (44) one register (48) in which the length of said first clock period (TH1) is stored; at least one further register (49) in which information regarding the correct clock pulses of said clock pulse train (TP) is stored; a clock output device (46) for outputting said clock pulse train (TP) from said information stored in said registers (48, 49) as a result of a start command (START).

8. The clock generator (44) - one register (48) in which the cable length (L) is stored; at least one further register (49) in which information regarding the correct clock pulses of said clock pulse train (TP) is stored; - one clock output device (46) for calculating the length of the first clock period (TH1) based on the cable length (L) and on information about the normal clock pulses of the clock pulse train (TP) and for outputting the clock pulse train (TP) as a result of a start command (START).

9. The clock generator (44) one register (48) in which a constant (K) is stored; at least one further register (49) in which information regarding the correct clock pulses of said clock pulse train (TP) is stored; - one clock output device (46) for calculating the length of the first clock period (TH1) based on information about the normal clock pulses of the clock pulse train (TP) and on the constant (K) as a multiplier, and for outputting the clock pulse train (TP) as a result of a start command (START).

10. The method according to any one of claims 6 to 9, wherein the data signal (DT) is configured bidirectionally, a data transmission module (52) is provided for converting the data signal (DT) to be outputted into a differential data signal (D+, D-), and a data direction signal (TR) is generated by the data controller (42) for setting the data direction of the differential data channel (62) according to an interface protocol.

11. A subsequent electronic unit following an encoder (100), comprising an apparatus (30) according to any one of claims 1 to 5, further comprising a control device (20) connected to an interface controller (40) of the apparatus (30) via an internal interface (25).

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