Control circuit, display device, and main processor driving method

Abstract

To provide a control circuit, display device, and method of driving a main processor, which may reduce power consumption of a transmission / reception circuit connected to an interface.SOLUTION: Embodiments of the present disclosure relate to a control circuit, display device, and method of driving a main processor and, specifically, those which allow for powering off at least one of a source transmission / reception circuit and a sink transmission / reception circuit electrically connected to an auxiliary channel AUX during at least a partial period of a vertical blank period.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] [1] The embodiments of the present specification relate to a control circuit, a display device, and a method for driving a main processor. [Background technology]

[0002] [2] As the information society develops, the demand for display devices in various forms for displaying images is increasing, and in recent years, various display devices such as liquid crystal display devices (LCDs), plasma display panels (PDPs), and organic light emitting display devices (OLEDs) have been used.

[0003] [3] The display device may include a display driver circuit that generates and outputs a voltage for displaying an image, and a timing controller that controls the operation timing of the display driver circuit.

[0004] [4] The timing controller can be connected to the main processor through a preset interface. The main processor and the timing controller can transmit and receive commands, data, etc. according to the preset interface standard. Summary of the Invention [Problem to be solved by the invention]

[0005] [5] The embodiments of the present specification can provide a control circuit, a display device, and a method for driving a main processor that can reduce the power consumed by a transmission / reception circuit connected to an interface. [Means for solving the problem]

[0006] [6] An embodiment of the present specification may provide a timing controller including a main processor including a source transceiver circuit, and a sink transceiver circuit connected to the main processor via an interface, the timing controller generating and outputting image data and control signals, the interface including a main link and an auxiliary channel, the main processor providing control circuitry for powering off at least one of the source transceiver circuit and the sink transceiver circuit electrically connected to the auxiliary channel during at least a portion of a vertical blanking period between different refresh frame periods.

[0007] [7] An embodiment of the present specification may provide a display device comprising: a main processor including a source transceiver circuit; a timing controller including a sink transceiver circuit connected to the main processor via an interface, the timing controller generating and outputting image data and control signals; a data drive circuit whose drive timing is controlled by the timing controller and which generates and outputs a data voltage based on the image data and the control signal; a gate drive circuit controlled by the timing controller and which outputs a gate voltage based on the control signal; and a display panel in which a plurality of data lines to which the data voltage is applied, a plurality of gate lines to which the gate voltage is applied, and a plurality of sub-pixels electrically connected to the plurality of data lines and the plurality of gate lines are arranged, the interface including a main link and an auxiliary channel, and the main processor turning off power to at least one of the source transceiver circuit and the sink transceiver circuit electrically connected to the auxiliary channel during at least a portion of a vertical blanking period between different refresh frame periods.

[0008] [8] An embodiment of the present specification may provide a method for driving a main processor, the method including: a step in which a main processor transmits pixel packets for generating image data to a timing controller via a main link of an interface; after the timing controller receives the pixel packets, the main processor including a source transceiver circuit turns off a power supply to the source transceiver circuit electrically connected to an auxiliary channel of the interface; a step in which the main processor turns on a power supply to the source transceiver circuit electrically connected to the auxiliary channel; and a step in which the main processor transmits a link training signal via the main link. Effect of the Invention

[0009] [9] According to an embodiment of the present disclosure, it is possible to provide a control circuit, a display device, and a method for driving a main processor that can reduce the power consumed by a transmission / reception circuit connected to an interface. [Brief description of the drawings]

[0010] [Figure 1] 2 is a block diagram of a control circuit and a display driver circuit controlled by the control circuit according to an embodiment herein; [Diagram 2] FIG. 2 is a configuration block diagram of a main processor according to an embodiment of the present specification. [Diagram 3] 2 is a system configuration diagram of a display device including the control circuit of FIG. 1. [Figure 4] FIG. 2 illustrates an example of a display device according to embodiments herein implementing various refresh frame rates. [Diagram 5] FIG. 2 illustrates an interface between a main processor and a timing controller according to an embodiment of the present specification. [Figure 6] FIG. 2 is a block diagram of a phase-locked loop; [Figure 7]FIG. 2 illustrates the display timing of a display device according to an embodiment of the present specification and the corresponding status of the main link and auxiliary channels. [Figure 8] 1A-1C are exemplary diagrams illustrating embodiments and methods of operation of a counter. [Figure 9] 1A-1C are exemplary diagrams illustrating embodiments and methods of operation of a counter. [Figure 10] 1A-1C are exemplary diagrams illustrating embodiments and methods of operation of a counter. [Figure 11] FIG. 13 illustrates that both the main link and the auxiliary channel are in a link-off state during at least a portion of a vertical blanking period. [Figure 12] 2 is a flowchart of a method for driving a main processor according to an embodiment of the present specification. [Figure 13] 2 is a flowchart of a method for driving a main processor according to an embodiment of the present specification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[11] Some embodiments of the present disclosure will be described in detail below with reference to exemplary drawings. When adding reference symbols to components in each drawing, the same components may be assigned the same symbols as much as possible, even if they are displayed in other drawings. In describing the present disclosure, if it is determined that a specific description of a related publicly known configuration or function may obscure the gist of the present disclosure, the detailed description will be omitted. When the terms "include," "have," "perform," and the like mentioned in the present specification are used, other parts may be added unless "only" is used. When a component is expressed as a singular number, it may include a case where a plurality is included, unless otherwise explicitly stated.

[0012]

[12] In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of the present disclosure. These terms are used only to distinguish the components from other components, and do not limit the nature, order, sequence, number, etc. of the components.

[0013]

[13] When two or more components are described as being "coupled," "coupled," or "connected" in a description of the positional relationship of components, it should be understood that the two or more components may be directly "coupled," "coupled," or "connected," but that the two or more components may also be further "intervened" and "coupled," "coupled," or "connected" to other components. Here, the other components may be included in one or more of the two or more components that are "coupled," "coupled," or "connected" to each other.

[0014]

[14] In describing the temporal relationship of components, methods of operation, or methods of production, for example, when a chronological or sequential relationship is described using "after," "following," "next to," or "before," this may not necessarily be contiguous, unless "immediately" or "directly" is used.

[0015]

[15] On the other hand, when a numerical value or corresponding information (e.g., level, etc.) relating to a component is mentioned, the numerical value or corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external impacts, noise, etc.) even if there is no explicit statement to the contrary.

[0016]

[16] Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0017]

[17] Figure 1 is a block diagram of a control circuit 100 and a display driver circuit 130 controlled by the control circuit 100 according to an embodiment of the present disclosure.

[0018]

[18] Referring to FIG. 1, a control circuit 100 according to an embodiment of the present specification includes a main processor 110 and a timing controller 120 configured to generate and output data voltages for image display.

[0019]

[19] The main processor 110 and the timing controller 120 can transmit and receive commands, signals, etc. that are converted according to a preset interface standard.

[0020]

[20] The timing controller 120 controls the display driver circuit 130 so that the display driver circuit 130 outputs signals (eg, data voltages, gate voltages, etc.) for displaying images to the display panel in accordance with the timing.

[0021]

[21] FIG. 2 is a block diagram of main processor 110 according to an embodiment of the present disclosure.

[0022]

[22] Referring to FIG. 2, the main processor 110 according to an embodiment of the present specification may include a system memory 210, a CPU (Central Processing Unit) 220, an interrupt controller 230, a transceiver circuit 240, a memory controller 250, an image generation unit 260, and a display controller 270, etc.

[0023]

[23] The system memory 210 can store instructions, parameters, etc. necessary for the operation of the aforementioned display driver circuit 130. For example, the CPU 220 can operate using the instructions, parameters, etc. stored in the system memory 210.

[0024]

[24] CPU 220 may generally control the operation of main processor 110. For example, CPU 220 may control the operation of each component, such as system memory 210, interrupt controller 230, transceiver circuit 240, memory controller 250, image generator 260, and display controller 270. CPU 220 may also request image generator 260 to generate or process an image.

[0025]

[25] The interrupt controller 230 can control interrupts that occur during the operation of the main processor 110. That is, the interrupt controller 230 can receive interrupts from each component, adjust the execution order of each interrupt, and transmit the interrupt to the CPU 220 so as to perform an operation corresponding to the interrupt.

[0026]

[26] The transmission / reception circuit 240 can transmit and receive commands, signals, interrupts, and data converted according to various interface standards to and from the timing controller 120. The transmission / reception circuit 240 can provide image data stored in an external memory (not shown) to the display driver circuit 130 (particularly a data driver circuit) via the timing controller 120. In this specification, the transmission / reception circuit 240 may mean only a transmission circuit including a configuration for transmitting data, etc., may mean only a reception circuit including a configuration for receiving data, etc., or may mean a transmission / reception circuit including a configuration for transmitting and receiving data, etc.

[0027]

[27] The memory controller 250 can control the external memory when transmitting data to or receiving data from the external memory connected to the main processor 110. That is, the memory controller 250 can access the external memory to read, write, or delete image data in response to a request from the CPU 220, the image generator 260, or the display controller 270.

[0028]

[28] The image generator 260 may generate or process program instructions related to graphic processing under the control of the CPU 220. Such an image generator 260 may be realized as a graphic engine, a graphic processing unit (GPU), a graphic accelerator, 2D, or the like.

[0029]

[29] The display controller 270 can control the operation of the main processor 110 with respect to the timing controller 120 described above, or can control the operation of the timing controller 120 with respect to the main processor 110. For example, the display controller 270 can control the memory controller 250 so that data stored in an external memory is output via the transmission / reception circuit 240. The display controller 270 can also control the image generation unit 260 so that image data generated by the image generation unit 260 is output via the transmission / reception circuit 240.

[0030]

[30] The system bus 280 can connect each component of the main processor 110 and serve as a path for data transmission and reception between each component. The system bus 280 can include a small bus for data communication between the components.

[0031]

[31] Main processor 110 according to embodiments herein may be a host system, a System on Chip (SoC) device, or the like.

[0032]

[32] FIG. 3 is a system configuration diagram of a display device 300 including the control circuit 100 of FIG.

[0033]

[33] Referring to FIG. 3, a display device 300 according to an embodiment of the present specification includes a main processor 110, a timing controller 120 capable of communicating with the main processor 110, a display driver circuit 130 whose operation timing is controlled by the timing controller 120, and a display panel 310 on which a plurality of data lines DL and a plurality of gate lines GL to which a voltage output from the display driver circuit 130 is applied are arranged.

[0034]

[34] The display driving circuit 130 is a circuit for configuring the display panel 310, and may include a data driving circuit 320 and a gate driving circuit 330.

[0035]

[35] The display panel 310 may include a display area AA where an image is displayed, and a non-display area NA where no image is displayed. The non-display area NA may be an outer peripheral area of ​​the display area AA, and may also be called a bezel area. The entire or part of the non-display area NA may be an area that is visible from the front surface of the display device 300, or may be an area that is curved and cannot be seen from the front surface of the display device 300.

[0036]

[36] The display panel 310 may include a substrate and a plurality of sub-pixels SP disposed on the substrate. In addition, the display panel 310 may further include various kinds of signal lines for driving the plurality of sub-pixels SP.

[0037]

[37] The display device 300 according to the embodiment of the present specification may be a liquid crystal display device or the like, or may be a self-emitting display device in which the display panel 310 emits light by itself. When the display device 300 according to the embodiment of the present specification is a self-emitting display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0038]

[38] For example, the display device 300 according to the embodiment of the present specification may be an organic light emitting display device in which the light emitting element is an organic light emitting diode (OLED). As another example, the display device 300 according to the embodiment of the present specification may be a quantum dot display device in which the light emitting element is a quantum dot of a semiconductor crystal that emits light by itself.

[0039]

[39] For example, various types of signal lines may include a plurality of data lines DL that transmit data signals (also called data voltages or image signals) and a plurality of gate lines GL that transmit gate signals (also called gate voltages or scan signals).

[0040]

[40] The data driving circuit 320 is configured to drive a plurality of data lines DL and can output data voltages to the plurality of data lines DL. The gate driving circuit 330 is configured to drive a plurality of gate lines GL and can output gate signals to the plurality of gate lines GL.

[0041]

[41] The timing controller 120 may be a device configured to control the data driving circuit 320 and the gate driving circuit 330. The timing controller 120 may control the driving timing for a plurality of data lines DL and the driving timing for a plurality of gate lines GL.

[0042]

[42] The timing controller 120 can provide a data drive control signal DCS to the data drive circuit 320 to control the data drive circuit 320. The timing controller 120 can provide a gate drive control signal GCS to the gate drive circuit 330 to control the gate drive circuit 330.

[0043]

[43] The timing controller 120 can receive input image data from the main processor 110, and provide image data DATA to the data driving circuit 320 based on the input image data.

[0044]

[44] The timing controller 120 may generate and output one or more synchronization signals to drive the data driving circuit 320 and the gate driving circuit 330 with precise timing.

[0045]

[45] For example, the timing controller 120 may generate a vertical synchronization signal (also called a Vsync signal) that indicates the start of each frame, and a horizontal synchronization signal (also called an Hsync signal) that indicates the start of a horizontal line.

[0046]

[46] The data driving circuit 320 can supply data voltages to a plurality of data lines DL according to the driving timing control of the timing controller 120.

[0047]

[47] The data driving circuit 320 receives digital image data DATA from the timing controller 120, converts the received image data DATA into analog data voltages, and outputs the analog data voltages to a plurality of data lines DL.

[0048]

[48] ​​The gate driving circuit 330 can supply gate signals to the multiple gate lines GL in response to the timing control of the timing controller 120. The gate driving circuit 330 is supplied with a first gate voltage corresponding to a turn-on level voltage and a second gate voltage corresponding to a turn-off level voltage together with various gate driving control signals GCS, generates gate signals, and supplies the generated gate signals to the multiple gate lines GL.

[0049]

[49] For example, the data driving circuit 320 may be connected to the display panel 310 using a tape atomized bonding (TAB) method, or may be connected to a bonding pad of the display panel 310 using a chip on glass (COG) or chip on panel (COP) method, or may be embodied as a chip on film (COF) method and connected to the display panel 310.

[0050]

[50] The gate driving circuit 330 may be connected to the display panel 310 by a tape automated bonding (TAB) method, may be connected to a bonding pad of the display panel 310 by a chip on glass (COG) or chip on panel (COP) method, or may be connected to the display panel according to a chip on film (COF) method. Alternatively, the gate driving circuit 330 may be formed in the non-display area NA of the display panel 310 as a gate in panel (GIP) type.

[0051]

[51] Meanwhile, at least one of the data driving circuit 320 and the gate driving circuit 330 may be disposed in the display area AA of the display panel 310. For example, at least one of the data driving circuit 320 and the gate driving circuit 330 may be disposed so as not to overlap the sub-pixel SP, or may be disposed so as to overlap partially or completely with the sub-pixel SP.

[0052]

[52] The data driving circuit 320 may be connected to one side (e.g., the top or bottom) of the display panel 310. Depending on the driving scheme, design scheme, etc., the data driving circuit 320 may be connected to both sides (e.g., the top and bottom) of the display panel 310, or may be connected to two or more of the four sides of the display panel 310.

[0053]

[53] The gate drive circuit 330 may be connected to one side (e.g., the left or right side) of the display panel 310. Depending on the driving scheme, panel design scheme, etc., the gate drive circuit 330 may be connected to both sides (e.g., the left and right sides) of the display panel 310, or to two or more of the four sides of the display panel 310.

[0054]

[54] The timing controller 120 may be implemented as a component separate from the data driving circuit 320, or may be integrated with the data driving circuit 320 and implemented as an integrated circuit.

[0055]

[55] The timing controller 120 may be a timing controller used in a typical display technology, or may be a control device including a timing controller and capable of performing other control functions, or may be a circuit within the control device. The timing controller 120 may be realized by various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0056]

[56] The timing controller 120 may be electrically connected to the data driving circuit 320 and the gate driving circuit 330 via a printed circuit board (PCB), a flexible printed circuit board (FPCB), or the like.

[0057]

[57] The timing controller 120 can transmit and receive signals to and from the data driving circuit 320 according to one or more predetermined interfaces. Here, the interfaces can include, for example, a Low Voltage Differential Signaling (LVDS) interface, an EPI interface, a Serial Peripheral Interface (SPI), etc.

[0058]

[58] The display device 300 according to the embodiments of this specification may include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or pen and to detect the touch position, in order to provide not only an image display function but also a touch sensing function.

[0059]

[59] The touch sensing circuit may include a touch drive circuit 360 that drives and senses the touch sensor and generates and outputs touch sensing data, and a touch controller 370 that can use the touch sensing data to sense the occurrence of a touch and detect the touch position.

[0060]

[60] The touch sensor may include multiple touch electrodes. The touch sensor may further include multiple touch lines for electrically connecting the multiple touch electrodes to the touch driving circuit 360.

[0061]

[61] The touch sensor may be present in the form of a touch panel outside the display panel 310, or may be present inside the display panel 310. When the touch sensor is present outside the display panel 310 in the form of a panel, the touch sensor is called an external type. When the touch sensor is an external type, the touch panel and the display panel 310 can be fabricated separately and combined during the assembly process. The external type touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0062]

[62] If the touch sensor is present inside the display panel 310, the touch sensor may be formed on a substrate during the manufacturing process of the display panel 310 along with signal lines, electrodes, etc. associated with display driving.

[0063]

[63] The touch drive circuit 160 may provide a touch drive signal to at least one of the plurality of touch electrodes, and sense the at least one of the plurality of touch electrodes to generate touch sensing data.

[0064]

[64] The touch sensing circuit can perform touch sensing using a self-capacitance sensing method or a mutual-capacitance sensing method.

[0065]

[65] The touch sensing circuit includes a touch driver circuit 360 and a touch controller 370, which may be implemented as separate devices or as a single device. The touch driver circuit 360 and the data driver circuit 320 may be implemented as separate devices or as a single device.

[0066]

[66] The display device 300 may further include a power supply circuit that supplies various power sources to the display driving circuit 130 and / or the touch sensing circuit.

[0067]

[67] The display device 300 according to the embodiments of this specification may be a mobile terminal such as a smartphone or a tablet, or may be a monitor or television (TV) of various sizes, including but not limited to, any type and size of display device capable of displaying information or images.

[0068]

[68] Figure 4 is a diagram illustrating an example of how a display device according to embodiments herein can achieve various refresh frame rates.

[0069]

[69] Referring to Figure 4, the display device according to the embodiment of the present specification can realize various refresh frame rates by changing the ratio of refresh frames to skip frames based on the vertical synchronization signal. For example, the refresh frames and skip frames can be started based on the rising edge or falling edge of the vertical synchronization signal.

[0070]

[70] A refresh frame may refer to a frame period during which the data driving circuit 320 outputs data voltages of various levels depending on the brightness of the sub-pixels. During the refresh frame period, data voltages of various levels may be applied to each sub-pixel depending on the brightness of an image displayed by the sub-pixel.

[0071]

[71] During a refresh frame period, a capacitor included in a subpixel is charged by a data voltage applied to the subpixel, so that the subpixel can emit light for one frame period.

[0072]

[72] A skip frame is distinguished from a refresh frame in which different levels of data voltage are applied to different sub-pixels. During a skip frame, multiple sub-pixels may have preset levels of data voltage applied to them.

[0073]

[73] This allows the display of static images, such as still images, at a low refresh frame rate when they are displayed on the display area for a long period of time, which has the advantage of reducing the power consumption of the data drive circuit.

[0074]

[74] Referring to Figure 4, if all frames are refresh frames based on a vertical synchronization signal having a frequency of 120 Hz, the refresh frame rate is 120 Hz. That is, if the refresh frame rate is the same as the frequency of the vertical synchronization signal, there may be no skip frames. When displaying video content, a high refresh frame rate may be desirable.

[0075]

[75] According to this, the time interval between refresh frames may be approximately 8.3 ms (1 / 120th of a second).

[0076]

[76] On the other hand, after one refresh frame is completed, one or more skip frames may be started.

[0077]

[77] Referring to Figure 4, after one refresh frame ends, four refresh frames are started consecutively based on a vertical synchronization signal having a frequency of 120 Hz. Thus, the refresh frame rate is 24 Hz. The time interval between refresh frames is about 41.7 ms (1 / 24 seconds).

[0078]

[78] The refresh frame rate may be controlled by the aforementioned main processor 110. For example, referring to FIG. 1, depending on the refresh frame rate set by the main processor 110, the main processor 110 may transmit pixel packets for generating image data to the timing controller 120 on a frame-by-frame or intermittently, thereby realizing various refresh frame rates.

[0079]

[79] Figure 5 illustrates an interface 510 between a main processor 110 and a timing controller 120 according to an embodiment of the present disclosure.

[0080]

[80] Referring to FIG. 5, the interface 510 may be a Display Port including a main link (also referred to as MAIN or MAIN LINK), an auxiliary channel (AUX), and a Hot Plug Detector (HPD) signal line (hereinafter referred to as "HPD").

[0081]

[81] The main link MAIN of the DisplayPort is a channel for transmitting image data from the main processor 110 to the timing controller 120. The main link MAIN is a high-bandwidth, low-latency channel, and is a unidirectional (Simplex) channel for transmitting data from the main processor 110 to the timing controller 120.

[0082]

[82] The DisplayPort auxiliary channel, AUX, is a half-duplex, bidirectional channel used for link management and device control.

[0083]

[83] HPD is used to inform the connection status between the main processor 110 and the timing controller 120.

[0084]

[84] Data to be transmitted may be converted to 8B / 10B code, Manchester code, etc., and transmitted from the source transceiver circuit 520 and the sink transceiver circuit 530 to the interface 510.

[0085]

[85] The source transceiver circuit 520 and the sink transceiver circuit 530 may include one or more transmitters for transmitting data and one or more receivers for receiving data. The source transceiver circuit 520 and the sink transceiver circuit 530 constitute a physical layer.

[0086]

[86] Referring to FIG. 5, the main processor 110 and the timing controller 120 include timing generators 540, 550, respectively.

[0087]

[87] The timing generator 540 included in the main processor 110 may be a device that generates timing signals for synchronization of signals received from the timing controller 120. Also, the timing generator 550 included in the timing controller 120 may be a device that generates timing signals for synchronization of signals received from the main processor 110.

[0088]

[88] Such timing generators 540, 550 may perform the function of a clock generator that generates a clock signal.

[0089]

[89] The timing generators 540, 550 allow the main processor 110 and the timing controller 120 to be synchronized with each other.

[0090]

[90] FIG. 6 is a block diagram of a Phase Locked Loop (PLL) 600.

[0091]

[91] The timing generators 540, 550 of FIG. 5 above may include a phase-locked loop 600.

[0092]

[92] The phase-locked loop 600 may include a phase frequency detector 601, a charge pump 602, a low pass filter 603, a voltage controlled oscillator (VCO) 604, and a divider circuit 605, among others.

[0093]

[93] Referring to Figure 6, a phase frequency detector 601 receives a reference frequency (Freq Ref) input to an input stage 606 of a phase locked loop 600 and a feedback signal input from a frequency divider circuit 605. The phase frequency detector 601 generates and outputs a pulse based on the phase difference between the two input signals. The pulse output from the phase frequency detector 601 is input to a charge pump 602.

[0094]

[94] The output stage of the charge pump 602 is connected via a low pass filter 603 to an input stage of a voltage controlled oscillator 604. The output stage 607 of the voltage controlled oscillator 604 is connected to an input stage of a frequency divider circuit 605.

[0095]

[95] The phase frequency detector 601 may be configured to compare the output of a reference frequency (Freq Ref) and a divider circuit 605 and generate a pulse proportional to the phase difference between the compared signals.

[0096]

[96] The phase frequency detector 601 can be implemented, in one example, by summing the outputs of two analog multipliers, or by a combination of exclusive-or logic gates, flip-flops, or digital logic gates, etc.

[0097]

[97] Charge pump 602 can be configured to charge and discharge a capacitor depending on the output of phase frequency detector 601. Phase frequency detector 601 can provide two output signals called "up" and "down". The two output signals can be signals that charge and discharge the capacitor, respectively. Thus, the voltage across the capacitor is proportional to the phase difference between the pulse input to input stage 606 of phase locked loop 600 and the pulse input from divider circuit 605.

[0098]

[98] Charge pump 602 may, by way of example, source current to a capacitor via a p-channel MOSFET and discharge current from the capacitor via an n-channel MOSFET.

[0099]

[99] Meanwhile, the phase-locked loop 600 may further include a low pass filter 603 configured to remove high-frequency harmonic components output from the output stage of the phase frequency detector 601. The low pass filter 603 may be realized as a passive filter configured by connecting a resistor and a capacitor in series. Alternatively, the low pass filter 603 may be realized as an active filter. In this case, the low pass filter 603 may include an amplifier such as an operational amplifier (also called an op amp), and a feedback path including a resistor, a capacitor, etc.

[0100]

[0100] The cutoff frequency of the low pass filter 603 may be preset to determine the "capture range" for the phase locked loop 600 to operate.

[0101]

[0101] On the other hand, the voltage controlled oscillator 604 can be configured to output a frequency that depends on the output of the charge pump 602 filtered by the low pass filter 603.

[0102]

[0102] The voltage controlled oscillator 604 can be implemented as a harmonic oscillator, a relaxation oscillator, etc. The variable current as the capacitor of the charge pump 602 is charged and discharged can vary the frequency of the voltage controlled oscillator 604. In this way, the output of the voltage controlled oscillator 604 becomes dependent on the output of the charge pump 602.

[0103] 6, the frequency divider circuit 605 may be configured to divide the signal output from the output stage 607 of the voltage controlled oscillator 604 into a preset value. In this way, the frequency divided into the preset value can be input to the phase frequency detector 601. As a result, a frequency different from the signal input to the input stage 606 can be output to the output stage 607.

[0104]

[0104] A signal of a preset frequency is input to the input stage 606. For example, a crystal oscillator, an RC oscillator, an LC oscillator, or the like can be used as a configuration for outputting a signal of a preset frequency.

[0105]

[0105] Such a preset frequency must be within the range of frequencies for operation of phase-locked loop 600. The range for operation of phase-locked loop 600 is sometimes referred to as the "capture range."

[0106]

[0106] When the preset frequency is higher than the frequency of the signal output from the frequency divider circuit 605, the phase frequency detector 601 can send a signal to the charge pump 602 to charge a capacitor included in the charge pump 602. When the preset frequency is lower than the frequency of the signal output from the frequency divider circuit 605, the phase frequency detector 601 can send a signal to the charge pump 602 to remove the charge from the capacitor included in the charge pump 602.

[0107]

[0107] Alternatively, if the preset frequency is higher than the frequency of the signal output from the frequency divider circuit 605, the phase frequency detector 601 can send a signal to the charge pump 602 to remove charge from the capacitor included in the charge pump 602. If the preset frequency is lower than the frequency of the signal output from the frequency divider circuit 605, the phase frequency detector 601 can send a signal to the charge pump 602 to charge the capacitor included in the charge pump 602.

[0108]

[0108] The signal output from the charge pump 602 is filtered by a low-pass filter 603, and the filtered signal is input to a voltage-controlled oscillator 604. The voltage-controlled oscillator 604 can generate and output a signal having a frequency corresponding to the filtered signal.

[0109]

[0109] When the frequency and phase of the signal input to the input stage 606 of the phase-locked loop 600 are equal to the frequency and phase of the signal output from the output stage 607 of the phase-locked loop 600, the phase-locked loop 600 is said to be "locked."

[0110]

[0110] If the frequency or phase of the signal input to input stage 606 of phase-locked loop 600 is different from the frequency or phase of the signal output from output stage 607 of phase-locked loop 600 (i.e., when phase-locked loop 600 is not locked), the frequency or phase of the signal output from output stage 607 can be compensated through the feedback process described above.

[0111]

[0111] FIG. 7 is a diagram illustrating the display timing of a display device according to an embodiment of the present specification and the corresponding states of the main link (MAIN; MAIN LINK) and auxiliary channel (AUX).

[0112]

[0112] Referring to FIG. 7, the display timing of the display device according to the embodiment of the present specification may include an active period ACTIVE and a vertical blank period VBLANK.

[0113]

[0113] An active period ACTIVE in FIG. 7 corresponds to a period during which the main processor transmits pixel packets PXL PACKET for displaying an image to the timing controller via the main link MAIN LINK.

[0114]

[0114] In addition to image data for displaying actual images, the pixel packet PXL PACKET may further include information such as the number of pixels (or sub-pixels) arranged on a horizontal line, the total number of lines in one image frame, the width of the horizontal synchronization signal, and the width of the vertical synchronization signal.

[0115]

[0115] That is, the active period ACTIVE in FIG. 7 may correspond to the period (the period from t0 to t1 and the period after t7) during which the data voltage for image display is applied to a plurality of data lines during the aforementioned refresh frame period.

[0116]

[0116] Meanwhile, referring to FIG. 7, the display timing may further include a dummy video period DUMMY VIDEO before and after the active period ACTIVE (periods t1 to t2 and t6 to t7 in FIG. 7).

[0117]

[0117] The dummy video period DUMMY VIDEO is not a period during which image data for displaying an image is input to the display area. For example, if a dummy gate line that is not electrically connected to the subpixel is further disposed in the non-display area of ​​the display panel, a gate signal may be output to the dummy gate line during the dummy video period DUMMY VIDEO.

[0118]

[0118] According to this, by detecting the output timing of the gate signal input to the dummy gate line, it is possible to indirectly confirm whether the gate signal is input at the appropriate timing to the gate line arranged in the display area of ​​the display panel.

[0119]

[0119] During the dummy video period DUMMY VIDEO, the main link MAIN LINK can transmit either Vertical Front Dummy data (VFD) or Vertical Back Dummy data (VBD).

[0120]

[0120] In some cases, a gate signal can be input to the dummy gate line during a part of the vertical blank period VBLANK. In this case, the dummy video period DUMMY VIDEO may be omitted.

[0121]

[0121] According to this, the period during which the main link MAIN LINK transmits a vertical front dummy data (VFD) or vertical back dummy data (VBD) signal can overlap with the vertical blank period VBLANK.

[0122]

[0122] Meanwhile, referring to Fig. 7, a vertical blanking period VBLANK exists in a period that does not overlap with the active period ACTIVE. The vertical blanking period VBLANK can include a vertical blanking period of a refresh frame and a skip frame period. Thus, the length of the vertical blanking period VBLANK can exceed the length of one frame period (for example, about 8.3 ms based on 120 Hz).

[0123]

[0123] When the period (t1 to t2) during which the main link MAIN LINK transmits the vertical front dummy data VFD ends, the main link MAIN LINK enters a period (t2 to t3) during which it transmits a vertical front porch (VFP) signal. When the period (t5 to t6) during which the main link MAIN LINK transmits the vertical back porch (VBP) signal ends, the main link MAIN LINK enters a period (t6 to t7) during which it transmits the vertical back dummy data VBD.

[0124]

[0124] During the period when the main link MAIN LINK transmits the vertical front porch VFP signal (period t2 to t3) or the period when it transmits the vertical back porch VBP signal (period t5 to t6), the main processor can transmit data other than the pixel packet PXL PACKET to the timing controller via the main link MAIN LINK.

[0125]

[0125] For example, the main processor can send timing data for performing touch sensing functions to the timing controller via the main link MAIN LINK. The timing controller can receive the input of the timing data for performing touch sensing functions, generate a touch synchronization signal (e.g., Tsync signal, etc.), and output it to the touch controller described above.

[0126]

[0126] Alternatively, the main processor can transmit data for adjusting the brightness of the screen to the timing controller via the main link MAIN LINK, whereby the timing controller can adjust the brightness of the sub-pixels according to a set value based on the received data even without receiving new image data.

[0127]

[0127] Referring to FIG. 7, during the period (corresponding to the period from t3 to t5) between the time when the transmission of the vertical front porch VFP signal via the main link MAIN LINK ends (corresponding to t3) and the time when the transmission of the vertical back porch VBP signal starts (corresponding to t5), the power supply of the transceiver circuit (e.g., the source transceiver circuit and / or the sink transceiver circuit) connected to the main link MAIN LINK may be turned off.

[0128]

[0128] Referring to Figures 5 and 7 together, power consumption can be reduced by turning off the power to the transmission / reception circuits 520 and 530 connected to the main link MAIN LINK during at least a portion of the relevant period (the period from t3 to t5).

[0129]

[0129] From the viewpoint of the main link MAIN LINK, a state in which the power supply of the source transceiver circuit 520 and / or the sink transceiver circuit 530 connected to the main link MAIN LINK is turned off can be defined as a "LINK OFF" state. The "LINK OFF" state may also be called a "sleep" state.

[0130]

[0130] Conversely, from the perspective of the main link MAIN LINK, a state in which the power of the source transceiver circuit 520 and the sink transceiver circuit 530 connected to the main link MAIN LINK is turned on can be defined as a "link on" state.

[0131]

[0131] The link off state of the main link MAIN LINK can be terminated by the main processor sending an active sync signal 710 to the timing controller via the auxiliary channel AUX.

[0132]

[0132] Therefore, while the main link MAIN LINK is in a link-off state, the power supplies of the source transceiver circuit 520 and the sink transceiver circuit 530 connected to the auxiliary channel AUX may be in an on state. Accordingly, while the main link MAIN LINK is in a "link-off" state, the auxiliary channel AUX may be in a "link-on" state.

[0133]

[0133] Referring to FIG. 7, an active sync signal 710 is transmitted from the main processor to the timing controller via the auxiliary channel AUX at time t4, and the link-off state of the main link MAIN LINK ends.

[0134]

[0134] When the link-off state of the main link MAIN LINK ends, transmission of the link training signal LINK TRAINING starts via the main link MAIN LINK.

[0135]

[0135] The link training signal LINK TRAINING may include a clock recovery parameter. The timing controller receives the clock recovery parameter and can recover the clock in which an error occurs through the above-mentioned phase-locked loop 600 (see FIG. 6).

[0136]

[0136] The link training signal LINK TRAINING may include one or more symbol lock patterns. The symbol lock pattern may be transmitted over the main link after the transmission of the clock recovery parameters is completed. The timing controller may receive the symbol lock pattern and be synchronized with the main processor.

[0137]

[0137] As a result, the main processor and the timing controller are synchronized at the time when the main processor finishes transmitting the link training signal LINK TRAINING (at time t5).

[0138] After the main processor finishes transmitting the link training signal LINK TRAINING, the main link MAIN LINK can transmit the vertical back porch VBP signal and the vertical back dummy data VBD.

[0139]

[0139] On the other hand, referring to Fig. 7, during the period when the main link MAIN LINK is in the "link off" state, the auxiliary channel AUX is in the "link on" state. Since the main processor needs to transmit an active sync signal 710 through the auxiliary channel AUX to end the link off state of the main link MAIN LINK, it is difficult to keep the auxiliary channel AUX in the link off state.

[0140]

[0140] The embodiment of the present specification can switch both the main link MAIN LINK and the auxiliary channel AUX to a link-off state based on the number of pulses of the clock signal CLK.

[0141]

[0141] Referring to Fig. 7, both the main link MAIN LINK and the auxiliary channel AUX can be kept in the link-off state based on the number of pulses of the clock signal CLK corresponding to the period (period from t3 to t4) during which the main link MAIN LINK is in the link-off state. The clock signal CLK may be a signal output from the above-mentioned timing generators 540 and 550 (see Fig. 5).

[0142]

[0142] The main processor and / or the timing controller according to the embodiments of this specification may further include a counter COUNTER for calculating the number of pulses of the clock signal CLK.

[0143]

[0143] The counter COUNTER receives the clock signal CLK and detects the rising edge or falling edge of the pulse of the clock signal CLK to calculate the number of pulses. The number of pulses of the clock signal CLK calculated by the counter COUNTER during a certain period corresponds to the length of the period.

[0144]

[0144] According to this, the length of the link-off period of the main link MAIN LINK can be replaced with the number of pulses calculated by the counter COUNTER.

[0145]

[0145] The counter COUNTER included in the main processor can output the calculated number of pulses to the main processor. The counter COUTNER included in the timing controller can output the calculated number of pulses to the timing controller.

[0146]

[0146] Below, with reference to Figures 5 and 7, a method will be described in which the main processor 110 adjusts the period during which the power supply to the transmission / reception circuits 520, 530 connected to the main link MAIN LINK and the transmission / reception circuits 520, 530 connected to the auxiliary channel AUX is turned off.

[0147]

[0147] The main processor 110 according to an embodiment of the present invention may include a memory (not shown), in which a value for the length of the vertical blanking period VBLANK according to the refresh frame rate may be pre-stored.

[0148]

[0148] The memory in which the value of the length of the vertical blanking period VBLANK is stored may be a memory included in the main processor 110, or may be an external memory connected to the main processor 110. When the memory is included in the main processor 110, the display controller 270 may include the memory.

[0149]

[0149] The main processor 110 turns off the power supply of the source transmitting / receiving circuit 520 connected to the main link MAIN LINK at time t3 based on the refresh frame rate information of the image data transmitted via the main link MAIN LINK.

[0150]

[0150] This allows the power supply to the source transmitting / receiving circuit 520 connected to the main link MAIN LINK to be turned off.

[0151] On the other hand, the main processor 110 can turn off the power supply of the source transmitting / receiving circuit 520 connected to the auxiliary channel AUX at time t3.

[0152]

[0152] The source transceiver circuit 520 and the sink transceiver circuit 530 connected to the auxiliary channel AUX can be designed to be connected to the same power supply. By connecting the power supplies of the source transceiver circuit 520 and the sink transceiver circuit 530 connected to the auxiliary channel AUX to a single power supply, the source transceiver circuit 520 and the sink transceiver circuit 530 can be turned off at the same time. This can further increase the effect of reducing power consumption.

[0153]

[0153] Thus, at time t3, both the main link MAIN LINK and the auxiliary channel AUX may be switched to the "link off" state.

[0154]

[0154] The counter COUNTER counts the number of pulses from time t3 based on the clock signal CLK, and outputs the count result value.

[0155]

[0155] The main processor 110 compares the output value of the counter COUNTER with the length of the vertical blanking period VBLANK stored in advance. When the input output value of the counter COUNTER becomes equal to the length of the vertical blanking period VBLANK set in advance, the main processor 110 turns on the power supply of the source transmitting / receiving circuit 520 connected to the main link MAIN LINK, and turns on the power supply of the source transmitting / receiving circuit 520 and the sink transmitting / receiving circuit 530 connected to the auxiliary channel AUX. That is, according to the value output by the counter COUNTER at the time point t4, the main processor 110 can switch the main link MAIN LINK and the auxiliary channel AUX from a "link off" state to a "link on" state.

[0156]

[0156] When both the main link MAIN LINK and the auxiliary channel AUX are switched from the "link off" state to the "link on" state, the main processor 110 transmits a link training signal LINK TRAINING to the timing controller 120 via the main link MAIN LINK. The timing controller 120 receives the link training signal LINK TRAINING and can execute a process of being synchronized with the main processor 110.

[0157]

[0157] The main processor 110 can initialize the output value of the counter COUNTER after time t4.

[0158]

[0158] Meanwhile, the main processor 110 according to an embodiment of the present invention may include a memory (not shown), and the value of the length of the vertical blanking period VBLANK according to the refresh frame rate may not be stored in advance in the memory. In this case, the value stored in the memory may be updated based on the value output from the counter COUNTER.

[0159]

[0159] For example, in the first vertical blank period VBLANK in which the refresh frame rate is not maintained and the main link MAIN LINK is in the "link off" state, and in the period in which the main link MAIN LINK is in the "link off" state, the auxiliary channel AUX can maintain the "link on" state.

[0160]

[0160] The counter COUNTER counts the number of pulses of the clock signal CLK from time t3. The counter COUNTER counts the number of pulses of the clock signal CLK during the period from time t3 to time t4 when the main processor 110 transmits the active sync signal 710 to the auxiliary channel AUX (i.e., the period from t3 to t4).

[0161]

[0161] The counter COUNTER outputs the number of pulses of the clock signal CLK that has been counted during the period from t3 to t4, and the main processor 110 can store the output value of the counter COUNTER in a memory.

[0162]

[0162] During the vertical blanking period VBLANK during which the refresh frame rate is maintained, both the main link MAIN LINK and the auxiliary channel AUX can be in a "link off" state.

[0163]

[0163] From time t3, the main processor 110 can receive the value output from the counter COUNTER. The main processor 110 can compare the value stored in the memory with the value output from the counter COUNTER. When the two compared values ​​become equal, the main processor 110 can switch the states of both the main link MAIN LINK and the auxiliary channel AUX from the "link off" state to the "link on" state.

[0164]

[0164] According to this, the main link MAIN LINK and the auxiliary channel AUX can both be in a "link off" state during at least a part of the vertical blank period VBLANK. This has the effect of reducing power consumption.

[0165]

[0165] Referring to FIG. 7, during the period before time t3 and the period after time t4, the counter COUNTER may or may not count the number of pulses of the clock signal CLK (DON'T CARE).

[0166] 8-10 are diagrams illustrating exemplary embodiments and methods of operation of a counter 800. FIG.

[0167]

[0167] Referring to Fig. 8, a counter 800 can be configured to receive a clock signal CLK PULSE and count the number of pulses of the input signal. The counter 800 in Fig. 8 is merely one example for implementing the counter COUNTER in Fig. 7, and is not limited thereto.

[0168] 8, a counter 800 may include two or more flip-flops 810, 820, 830, and 840. For example, the counter 800 may include a first flip-flop 810, a second flip-flop 820, a third flip-flop 830, and a fourth flip-flop 840.

[0169]

[0169] A clock signal CLK PULSE is input to an input stage of a first flip-flop 810. An output stage of the first flip-flop 810 is connected to an input stage of a second flip-flop 820. An output stage of the second flip-flop 820 is connected to an input stage of a third flip-flop 830. An output stage of the third flip-flop 830 is connected to an input stage of a fourth flip-flop 840.

[0170]

[0170] The output value Q0 of the first flip-flop 810 is input to the input stage of the second flip-flop 820. The output value Q1 of the second flip-flop 820 is input to the input stage of the third flip-flop 830. The output value Q2 of the third flip-flop 830 is input to the input stage of the fourth flip-flop 840. The output value of the fourth flip-flop 840 is Q3.

[0171]

[0171] Each of the first to fourth flip-flops 810 to 840 detects a rising edge or a falling edge of a pulse. When a rising edge or a falling edge of a pulse is detected, the phase of the output value changes. Each of the first to fourth flip-flops 810 to 840 can be realized by a normal JK flip-flop.

[0172]

[0172] FIG. 9 is a diagram showing the principle by which the counter 800 in FIG. 8 counts the number of pulses of the clock signal CLK PULSE.

[0173]

[0173] Referring to Figures 8 and 9, the first to fourth flip-flops 810 to 840 can detect the falling edge of the input pulse. For example, when the logical value of the clock signal CLK PULSE input to the first flip-flop 810 changes from 1 to 0, the logical value of the output value Q0 of the first flip-flop 810 changes. According to this, the Q0 value changes from 0 to 1, or from 1 to 0.

[0174]

[0174] According to this, the frequency of the signal output from each of the first to fourth flip-flops 810 to 840 is half the frequency of the signal input thereto.

[0175]

[0175] Therefore, the number of pulses of the clock signal CLK PULSE can be expressed in binary using the output value Q0 of the first flip-flop 810, the output value Q1 of the second flip-flop 820, the output value Q2 of the third flip-flop 830, and the output value Q4 of the fourth flip-flop 840.

[0176]

[0176] According to this, the counter 800 including N flip-flops can count the number of pulses of the clock signal CLK PULSE up to 2^N.

[0177]

[0177] Referring to Figure 9, when the values ​​of Q0, Q1, Q2, and Q3 are 0, 0, 0, and 0, respectively, the number of pulses is counted to 0. When the values ​​of Q0, Q1, Q2, and Q3 are 1, 0, 0, and 0, respectively, the number of pulses is counted to 1. When the values ​​of Q0, Q1, Q2, and Q3 are 1, 1, 1, and 1, respectively, the number of pulses is counted to 15.

[0178]

[178] Thus, the first to fourth flip-flops 810 to 840 can be used to configure counter 800 that can count 16 pulse numbers.

[0179] FIG. 10 is a truth table for counter 800 of FIG.

[0180]

[0180] Referring to FIG. 10, Q0 corresponds to the first digit of the binary number, Q1 corresponds to the second digit of the binary number, Q2 corresponds to the third digit of the binary number, and Q3 corresponds to the fourth digit of the binary number.

[0181]

[0181] When the number of counted pulses increases by 1, the Q0 value increases by 1. When the Q0 value increases by 1 after the values ​​of Q0, Q1, Q2, and Q3 all become 1, Q0, Q1, Q2, and Q3 all return to 0.

[0182]

[0182] In this way, the number of pulses of the clock signal in a certain period can be detected up to a maximum of 16 using the logical values ​​of Q0, Q1, Q2, and Q3.

[0183]

[0183] Figures 8 to 10 are merely examples for implementing the counter COUNTER in Figure 7, and are not limited thereto. Taking into consideration the length of the LINK OFF period of the main link and auxiliary channel, the frequency of the reference clock signal CLK, and the like, the maximum number of pulses that the counter COUNTER can count (for example, the maximum number of pulses that can be detected in the case of the counter 800 shown in Figure 8 is 16) can be designed to be different.

[0184]

[0184] FIG. 11 is a diagram showing that both the main link MAIN LINK and the auxiliary channel AUX are in a link-off state during at least a part of the vertical blank period VBLANK.

[0185]

[0185] Referring to Figure 11, the main link MAIN LINK may be in a link-off state during a period from t3 to t4. The auxiliary channel AUX may be in a link-off state during a period from t3 to t4. In some cases, the auxiliary channel AUX may be in a link-off state during at least a portion of the period from t3 to t4, and in a link-on state during the remaining portion of the period.

[0186]

[0186] Referring to Fig. 11, when a link training signal LINK TRAINING is transmitted to the main link MAIN LINK, a constant voltage of a preset level may be applied to the auxiliary channel AUX. That is, the active sync signal 710 (see Fig. 7) may not be applied to the auxiliary channel AUX, and a constant voltage of a preset level may be applied to the auxiliary channel AUX. Even if the active sync signal 710 is not transmitted through the auxiliary channel AUX, the link training signal LINK TRAINING may be transmitted through the main link MAIN LINK.

[0187]

[0187] The length of the period during which the main link MAIN LINK and the auxiliary channel AUX are in the link-off state (the length of the period from t3 to t4) may be replaced with the number of pulses of the CLK signal.

[0188]

[0203] The above-mentioned counter COUNTER (see FIG. 7) can count the number of pulses of the clock signal CLK from time t3.

[0189]

[0189] The main processor adjusts the length of the period during which the main link MAIN LINK and the auxiliary channel AUX are in a link-off state based on the refresh frame rate. The main processor can adjust the length of the period using the number of pulses calculated by the counter COUNTER.

[0190]

[0213] The clock signal CLK by which the counter COUNTER counts the number of pulses may be, for example, a signal having the same frequency as the horizontal synchronization signal (also called Hsync signal) generated and output by the timing controller.

[0191]

[0191] This allows the main processor according to an embodiment of the present specification to control the transmission / reception circuit 240 (see Figure 2) so that both the main link MAIN LINK and the auxiliary channel AUX have a period in which they are in a link-off state.

[0192]

[0192] Figure 12 is a flow chart of a method (1200) for driving a main processor according to an embodiment of the present disclosure.

[0193] 12, the start of the flowchart is defined (1210). The start of the flowchart may correspond to a step in which the main processor transmits pixel packets for generating image data to the timing controller via the main link.

[0194]

[0194] When the display timing enters the vertical blanking period VBLANK, the main processor can transmit signals for generating touch signals, etc., over the main link (1220). During the vertical blanking period VBLANK, the signals transmitted over the main link can be signals other than image data.

[0195]

[0195] The main processor may power off the transceiver circuits (e.g., source transceiver circuits, etc.) during the vertical blanking period VBLANK so that the main link MAIN LINK and the auxiliary channel AUX switch to a link-off state (1230).

[0196]

[0196] After the main link MAIN LINK and the auxiliary channel AUX are switched to the link-off state, the main processor counts the number of pulses based on the clock signal (1240). A counter included in the main processor may count the number of pulses of the clock signal.

[0197]

[0197] When the number of pulses of the clock signal calculated by the counter becomes equal to the number of pulses of the clock signal corresponding to the length of the preset link-off period, the main processor turns on the power supply of the transmission / reception circuits connected to the main link MAIN LINK and the auxiliary channel AUX (1250). As a result, the main link MAIN LINK and the auxiliary channel AUX are switched to the link-on state.

[0198]

[0198] The main processor transmits a link training signal LINK TRAINING to the timing controller via the main link MAIN LINK (1260). The timing controller synchronizes with the main processor based on the received link training signal.

[0199]

[0199] During the active period VACTIVE, the main processor transmits pixel packets for video display to the timing controller via the main link MAIN LINK (1270).

[0200]

[0200] After this, the end of the flow chart is defined (1280).

[0201]

[0201] According to this, in the method of driving the main processor according to an embodiment of the present specification, a training signal is transmitted via the main link MAIN LINK even if an active sync signal indicating the start of an active period is not transmitted via the auxiliary channel.

[0202]

[0202] As a result, while the main link MAIN LINK is in a link-off state, the auxiliary channel AUX can be in a link-off state. That is, by turning off the power supply of the transmission / reception circuit connected to the auxiliary channel AUX, it is possible to reduce power consumption.

[0203]

[0203] Figure 13 is a flow chart of a method (1300) for operating a main processor according to an embodiment of the present disclosure.

[0204]

[0204] Referring to Figure 13, the start of the flowchart is defined (1310). The start of the flowchart may correspond to a step in which the main processor transmits pixel packets for generating image data to the timing controller via the main link.

[0205]

[0205] When the display timing enters the vertical blank period VBLANK, the main processor can transmit timing signals for generating touch signals, etc., via the main link MAIN LINK (1315).

[0206]

[0206] During the vertical blank period VBLANK of the display timing, the main processor can turn off the power supply of the transmitting / receiving circuit (e.g., the source transmitting / receiving circuit, etc.) connected to the main link MAIN LINK (1320). This allows the main link MAIN LINK to be in a link-off state.

[0207]

[0207] After turning off the power supply of the transmitting / receiving circuit connected to the main link MAIN LINK, the main processor counts the number of pulses of the clock signal CLK (1325). The counter included in the main processor can count the number of pulses of the clock signal.

[0208]

[0208] The main processor transmits an active sync signal ACTIVE SYNC, which indicates the start of an active period, to the timing controller via the auxiliary channel AUX (1330). The main processor stores in memory the number of pulses of the clock signal counted by the counter until the main processor outputs the active sync signal ACTIVE SYNC to the auxiliary channel AUX.

[0209]

[0209] During the active period VACTIVE, the main processor transmits pixel packets for generating image data to the timing controller via the main link MAIN LINK (1335).

[0210]

[0210] After the active period VACTIVE ends, the display timing enters the vertical blank period VBLANK (1340). The main processor can transmit timing signals for generating touch signals, etc., via the main link MAIN LINK.

[0211]

[0211] The main processor turns off the power supply of the transmission / reception circuit electrically connected to the main link MAIN LINK, and turns off the power supply of the transmission / reception circuit electrically connected to the auxiliary channel AUX (1345). As a result, the states of the main link and the auxiliary channel enter the link-off state.

[0212]

[0212] The main processor counts the number of pulses of the clock signal CLK (1350). A counter included in the main processor may count the number of pulses of the clock signal CLK.

[0213]

[0213] When the number of pulses counted by the counter becomes equal to the number of pulses of the clock signal stored in the memory, the main processor turns on the power supply of the transmitting / receiving circuit connected to the main link MAIN LINK and the power supply of the transmitting / receiving circuit connected to the auxiliary channel AUX (1355). As a result, the states of the main link MAIN LINK and the auxiliary channel AUX are switched to the link-on state. The main processor can transmit a link training signal to the timing controller via the main link. As a result, the main processor and the timing controller are synchronized.

[0214]

[0214] The display timing enters an active period, and the main processor transmits a pixel packet via the main link MAIN LINK (1360).

[0215]

[0215] The end of the flow chart is defined (1365).

[0216]

[0216] With this, even if the length of the vertical blanking period for each refresh frame rate is not pre-stored in memory, it is possible to detect the length of the vertical blanking period and turn off the power supply of the transmitting / receiving circuit connected to the auxiliary channel.

[0217]

[0217] This makes it possible to reduce the power consumption of the main processor and the timing controller.

[0218]

[0218] The embodiments of the present specification described above can be briefly explained as follows.

[0219]

[0219] An embodiment of the present specification includes a main processor 110 including a source transceiver circuit 520, and a sink transceiver circuit 530, the sink transceiver circuit 530 including a timing controller 120 connected to the main processor 110 via an interface 510 and generating and outputting image data DATA and control signals DCS, GCS, the interface 510 including main links MAIN, MAIN LINK and an auxiliary channel AUX, the main processor 110 may provide a control circuit 100 that turns off the power of at least one of the source transceiver circuit 520 and the sink transceiver circuit 530 electrically connected to the auxiliary channel AUX during at least a portion of a vertical blank period VBLANK between different refresh frame periods.

[0220]

[0220] In an embodiment of this specification, the main processor 110 may provide a control circuit 100 including a timing generator 540 that generates and outputs a clock signal CLK, and a counter 800 configured to detect pulse edges of the clock signal CLK.

[0221]

[0221] In an embodiment of this specification, the main processor 110 may provide a control circuit 100 that powers on a source transceiver circuit 520 electrically connected to the auxiliary channel AUX when a preset number of pulse edges of the clock signal CLK are detected.

[0222]

[0222] In the embodiment of the present specification, the counter 800 can provide a control circuit 100 that detects either a falling edge or a rising edge of the clock signal CLK.

[0223]

[0223] In an embodiment of this specification, the timing controller 120 generates and outputs a horizontal synchronization signal that indicates the start of a horizontal line in one frame, and the clock signal CLK output by the timing generator 540 can provide a control circuit 100 with the same frequency as the horizontal synchronization signal.

[0224]

[0224] An embodiment of the present specification can provide a control circuit 100 that detects the length of a period during which a source transceiver circuit 520 electrically connected to a main link MAIN LINK is powered off, and the main processor 110 controls the length of a period during which the source transceiver circuit 520 electrically connected to an auxiliary channel AUX is powered off based on the length of the detected period.

[0225]

[0225] The embodiments of this specification can provide a control circuit 100 in which the length of the period during which the source transceiver circuit 520 electrically connected to the auxiliary channel AUX is powered off can be varied depending on the length of the vertical blanking period VBLANK.

[0226]

[0226] In an embodiment of the present specification, the main processor 110 can provide a control circuit 100 that controls the length of the period during which the source transceiver circuit 520 electrically connected to the auxiliary channel AUX is powered off differently depending on the length of the vertical blanking period VBLANK.

[0227]

[0227] In the embodiment of the present specification, the source transceiver circuit 520 and the sink transceiver circuit 530, which are electrically connected to the auxiliary channel AUX, can provide a control circuit 100 connected to one power supply.

[0228]

[0228] In the embodiment of the present specification, the main processor 110 can provide a control circuit 100 that controls the on / off timing of the one power supply.

[0229]

[0229] In an embodiment herein, the counter 800 may be provided with a control circuit 100 that includes a flip-flop (eg, a first flip-flop 810) that receives an input of the clock signal CLK.

[0230]

[0230] An embodiment of the present specification can provide a control circuit 100 in which a constant voltage of a preset level is applied to the auxiliary channel AUX at the time (e.g., at time t4) when the main processor 110 transmits a link training signal LINK TRAINING for synchronization between the main processor 110 and the timing controller 120 via the main link MAIN LINK.

[0231]

[0231] The embodiment of the present specification includes a main processor 110 including a source transceiver circuit 520, and a sink transceiver circuit 530. The sink transceiver circuit 530 includes a timing controller 120 connected to the main processor 110 via an interface 510, generating and outputting image data DATA and control signals DCS and GCS, a data driving circuit 320 whose driving timing is controlled by the timing controller 120 and generating and outputting a data voltage based on the image data DATA and the control signal DCS, a gate driving circuit 330 controlled by the timing controller 120 and outputting a gate voltage based on the control signal GCS, and a display panel 310 in which a plurality of data lines DL to which the data voltage is applied, a plurality of gate lines GL to which the gate voltage is applied, and a plurality of sub-pixels SP electrically connected to the plurality of data lines DL and the plurality of gate lines GL are arranged. The interface 510 is connected to a main link MAIN A display device 300 can be provided that includes a LINK and an auxiliary channel AUX, and the main processor 110 turns off the power of at least one of the source transceiver circuit 520 and the sink transceiver circuit 530 electrically connected to the auxiliary channel AUX during at least a portion of a vertical blanking period VBLANK between different refresh frame periods.

[0232]

[0232] In an embodiment of the present specification, the timing controller 120 generates and outputs a vertical synchronization signal defining a plurality of frame periods, the main processor 110 transmits a pixel packet PXL PACKET to the timing controller 120 via the main link MAIN LINK during a refresh frame period among the plurality of frame periods, and the main processor 110 turns off the power of at least one of the source transceiver circuit 520 and the sink transceiver circuit 530 electrically connected to the auxiliary channel AUX during a skip frame period different from the refresh frame period among the plurality of frame periods.

[0233]

[0233] The embodiment of the present specification can provide a method (1200, 1300) for driving a main processor, the method including the steps of: a main processor 110 transmitting a pixel packet PXL PACKET for generating image data DATA to a timing controller 120 via a main link MAIN LINK of an interface 510 (1210, 1310); after the timing controller 120 receives the pixel packet PXL PACKET, the main processor 110 including a source transceiver circuit 520 turns off a power supply of the source transceiver circuit 520 electrically connected to an auxiliary channel AUX of the interface 510 (1230, 1345); the main processor 110 turns on a power supply of the source transceiver circuit 520 electrically connected to the auxiliary channel AUX (1250, 1355); and the main processor 110 transmitting a link training signal LINK TRAINING via the main link MAIN LINK (1260, 1355).

[0234]

[0234] An embodiment of the present specification can provide a method (1200, 1300) for driving a main processor, further including steps (1240, 1325, 1350) of a counter 800 included in the main processor 110 counting the number of pulses of a clock signal CLK generated and output from the main processor 110.

[0235]

[0235] In an embodiment of the present specification, a method (1200, 1300) for driving a main processor can be provided in which the step (1240, 1350) of the counter 800 counting the number of pulses of the clock signal CLK is performed with the power to the source transceiver circuit 520 electrically connected to the auxiliary channel AUX turned off.

[0236]

[0236] In an embodiment of the present specification, a method (1300) for driving a main processor can be provided in which step 1325 in which the counter 800 counts the number of pulses of the clock signal CLK is performed with the source transceiver circuit 520 electrically connected to the auxiliary channel AUX being powered on.

[0237]

[0237] The above description is merely an illustrative explanation of the technical idea of ​​the present disclosure, and a person having ordinary knowledge in the technical field to which the present disclosure belongs may make various modifications and variations without departing from the essential characteristics of the present disclosure. In addition, the embodiments shown in the present disclosure are for the purpose of explanation, not for the purpose of limiting the technical idea of ​​the present disclosure, and therefore the scope of the technical idea of ​​the present disclosure is not limited by these embodiments. The scope of protection of the present disclosure should be interpreted according to the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the rights of the present disclosure.

Claims

1. A display panel including a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels; a data driving circuit for controlling the plurality of data lines; A gate driver circuit for controlling the gate lines; and a control circuit for controlling the data driving circuit and the gate driving circuit; The control circuit includes: A main processor including source transmitting and receiving circuitry; and a timing controller connected to the main processor via an interface, including a sink transmission / reception circuit, and generating and outputting video data and control signals; the interface includes a main link and an auxiliary channel; The main processor controls at least one of the main link and the auxiliary channel to be in an off state during at least a portion of a vertical blank period between different refresh frame periods; A display device in which the main processor controls the auxiliary channel to be in an off state by turning off the power supply of at least one of the source transceiver circuit and the sink transceiver circuit electrically connected to the auxiliary channel.

2. the main link is a unidirectional channel for transmitting data from the main processor to the timing controller; 2. The display device of claim 1, wherein the auxiliary channel is a half-duplex bi-directional channel for link management and control.

3. The display device according to claim 1 , wherein the main processor controls the main link to be in an off state by turning off the power supply of at least one of the source transceiver circuit and the sink transceiver circuit electrically connected to the main link.

4. The display device according to claim 1 , wherein the main link is in an OFF state and the auxiliary channel is in an ON state during at least a portion of the vertical blanking period.

5. The display device according to claim 4 , wherein the main processor transmits an active sync signal via the auxiliary channel to control the main link to be switched from an off state to an on state.

6. The display device of claim 5 , wherein during the vertical blanking period, the main link switches from an OFF state to an ON state.

7. A display panel including a plurality of data lines, a plurality of gate lines, and a plurality of subpixels; a data driving circuit for controlling the plurality of data lines; A gate driver circuit for controlling the gate lines; and a control circuit for controlling the data driving circuit and the gate driving circuit; The control circuit includes: A main processor including source transmitting and receiving circuitry; and a timing controller connected to the main processor via an interface, including a sink transmission / reception circuit, and generating and outputting video data and control signals; the interface includes a main link and an auxiliary channel; The main processor controls at least one of the main link and the auxiliary channel to be in an off state during at least a portion of a vertical blank period between different refresh frame periods; A display device, wherein during at least a portion of the vertical blanking period, the main link is in an off state and the auxiliary channel is in an off state.

8. a counter configured to count the number of pulses of the clock signal; 8. The display device according to claim 7, wherein the main processor controls the main link and the auxiliary channel to be switched from an off state to an on state in response to the number of pulses of the clock signal counted by the counter.

9. The display device of claim 8 , wherein during the vertical blanking period, the main link and the auxiliary channels switch from an OFF state to an ON state.

10. 9. The display device of claim 8, wherein the clock signal has the same frequency as a horizontal synchronization signal.

11. The display device according to claim 1 , wherein the length of the vertical blanking period exceeds the length of one frame period defined by a vertical synchronization signal.

12. the vertical blanking period includes a skip frame period during which a preset data voltage is applied to a plurality of sub-pixels; The display device according to claim 1 , wherein at least one of the main link and the auxiliary channel is controlled to be in an off state during the skip frame period.

13. A display panel comprising a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels; a data driving circuit for controlling the plurality of data lines; A gate driver circuit for controlling the gate lines; and a control circuit for controlling the data driving circuit and the gate driving circuit; The control circuit includes: A main processor including source transmitting and receiving circuitry; and a timing controller connected to the main processor via an interface, including a sink transmission / reception circuit, and generating and outputting video data and control signals; the interface includes a main link and an auxiliary channel; The main processor controls at least one of the main link and the auxiliary channel to be in an off state during at least a portion of a vertical blank period between different refresh frame periods; the display panel further includes a dummy gate line disposed in a non-display area, A display device, wherein a gate signal is output to the dummy gate line during a part of the vertical blanking period.

14. A display panel comprising a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels; a data driving circuit for controlling the plurality of data lines; A gate driver circuit for controlling the gate lines; and a control circuit for controlling the data driving circuit and the gate driving circuit; The control circuit includes: A main processor including source transmitting and receiving circuitry; and a timing controller connected to the main processor via an interface, including a sink transmission / reception circuit, and generating and outputting video data and control signals; the interface includes a main link and an auxiliary channel; The main processor controls at least one of the main link and the auxiliary channel to be in an off state during at least a portion of a vertical blank period between different refresh frame periods; After the vertical blanking period, a dummy image period is performed before the active period, During the dummy image period, the main link transmits vertical front dummy data or vertical back dummy data.

15. A display panel comprising a plurality of data lines, a plurality of gate lines, and a plurality of subpixels; a data driving circuit for controlling the plurality of data lines; A gate driver circuit for controlling the gate lines; and a control circuit for controlling the data driving circuit and the gate driving circuit; The control circuit includes: A main processor including source transmitting and receiving circuitry; and a timing controller connected to the main processor via an interface, including a sink transmission / reception circuit, and generating and outputting video data and control signals; the interface includes a main link and an auxiliary channel; The main processor controls at least one of the main link and the auxiliary channel to be in an off state during at least a portion of a vertical blank period between different refresh frame periods; After the vertical blanking period, a dummy image period is performed before the active period, During the dummy video period, a gate signal is output to a dummy gate line arranged in a non-display area of ​​the display panel.

16. A main processor including source transmitting and receiving circuitry; and a timing controller connected to the main processor via an interface, including a sink transmission / reception circuit, and generating and outputting video data and control signals; the interface includes a main link and an auxiliary channel; The main processor controls at least one of the main link and the auxiliary channel to be in an off state during at least a portion of a vertical blank period between different refresh frame periods; The control circuitry, during at least a portion of the vertical blanking period, the main link is in an off state and the auxiliary channel is in an off state.

17. 17. The control circuit of claim 16, wherein during at least a portion of the vertical blanking period, the main link is in an off state and the auxiliary channel is in an on state.

18. The control circuit of claim 16 , wherein the length of the vertical blanking period exceeds the length of one frame period defined by a vertical synchronization signal.

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