Receiver, system and method of operating the receiver

Abstract

To optimize power efficiency of each of multiple types of power in a receiver that converts a radio signal received through an antenna into the multiple types of power.SOLUTION: A receiver includes: a first matching circuit configured to receive, through a branch point, antenna input power that is input from an antenna in accordance with a radio signal received by the antenna and input a portion of the received antenna input power to a first circuit as first input power, an impedance of the first matching circuit decreasing as the antenna input power increases; and a second matching circuit configured to receive, through the branch point, the antenna input power, and input another portion of the received antenna input power to a second circuit as second input power, an impedance of the second matching circuit increasing as the antenna input power increases.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a receiver, a system and a method of operating a receiver. [Background technology]

[0002] There is known a wireless communication device including an RFID (Radio Frequency IDentification) system and a cellular system with high transmission power. When the frequency bands of the RFID system and the cellular system are the same, the radio section of the RFID system that receives a transmission signal from the cellular system is driven by the transmission signal, increasing unwanted radiation. Therefore, a resonant circuit that changes the resonant frequency to outside the frequency band when a transmission signal from the cellular system is received is provided in the power supply circuit of the radio section (see, for example, Patent Document 1). Also, there is known a wireless power receiver having rectifiers or matching devices arranged alternately (see, for example, Patent Documents 2 and 3). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-39235 A [Patent Document 2] Special Publication No. 2019-530395 [Patent Document 3] JP 2019-47205 A Summary of the Invention [Problem to be solved by the invention]

[0004] In RFID tags and the like, a radio signal received via an antenna may be converted into multiple powers to operate multiple types of internal circuits. However, no method has been proposed for optimizing the power efficiency of each of the multiple powers relative to the antenna input power. For example, when there is a difference in power efficiency between the multiple powers, the communication distance at which the side with the lower power efficiency can receive power to operate the corresponding internal circuit becomes shorter.

[0005] In one aspect, the present invention aims to optimize the power efficiency of each of a plurality of power sources in a receiver that converts a radio signal received via an antenna into a plurality of power sources. [Means for solving the problem]

[0006] According to one aspect, a receiver has a first matching circuit that receives antenna input power via a branch point, which is input from an antenna in response to a radio signal received by the antenna, and inputs a portion of the received antenna input power to a first circuit as a first input power, and has an impedance that decreases as the antenna input power increases, and a second matching circuit that receives the antenna input power via the branch point, inputs another portion of the received antenna input power to a second circuit as a second input power, and has an impedance that increases as the antenna input power increases. Effect of the Invention

[0007] According to one aspect, the present invention can optimize the power efficiency of each of a plurality of power sources in a receiver that converts a radio signal received via an antenna into a plurality of power sources. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a block diagram illustrating an example of a system including a receiver in one embodiment. [Diagram 2] 2 is a diagram showing an example of impedance characteristics and power characteristics of the receiver of FIG. 1. [Diagram 3]FIG. 2 is a block diagram illustrating an example of a system including a receiver in another embodiment. [Figure 4] 4 is a diagram showing an example of power characteristics and a Smith chart of RP2 and RP3 in FIG. 3. [Diagram 5] 4 is a diagram showing an example of power characteristics and power efficiency of P2L and P3L in FIG. 3, and a Smith chart of Z2L and Z3L. FIG. [Figure 6] FIG. 4 is a diagram showing an example of a Smith chart of Z2, Z3, Z23, and Z1 in FIG. [Figure 7] FIG. 13 is a block diagram illustrating an example of a system including another receiver. [Figure 8] 8 is a diagram showing an example of power characteristics and power efficiency of P2L and P3L in FIG. 7, and a Smith chart of Z2L and Z3L. FIG. [Figure 9] FIG. 8 is a diagram showing an example of a Smith chart of Z2, Z3, Z23, and Z1 in FIG. [Figure 10] FIG. 2 is a block diagram illustrating another example of a system including another receiver. [Figure 11] 11 is a diagram showing an example of power characteristics and a Smith chart of RP2 and RP3 in FIG. 10. FIG. [Figure 12] 11 is a diagram showing an example of the power characteristics and power efficiency of P2L and P3L in FIG. 10 and a Smith chart of Z2L and Z3L. FIG. [Figure 13] FIG. 11 is a diagram showing an example of a Smith chart of Z2, Z3, Z23, and Z1 in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings.

[0010] FIG. 1 shows an example of a system including a receiver in one embodiment. The system 100 shown in FIG. 1 has an antenna 1, a receiver 2, and a circuit section 3. The circuit section 3 has a first circuit 3a and a second circuit 3b, and is mounted on, for example, an LSI (Large-Scale Integration). The antenna 1 and the receiver 2 are connected via conductors, and the receiver 2 is connected via conductors to the first circuit 3a and the second circuit 3b, respectively. For example, the receiver 2 and the circuit section 3 are mounted on a wiring board housed in a housing of the system 100. The antenna 1 may be built into the wiring board or may be mounted on the wiring board. By building the antenna 1 into the wiring board, the system 100 can be made smaller.

[0011] Although not particularly limited, for example, the system 100 is a radio frequency identification (RFID) tag. The circuit unit 3 including the first circuit 3a and the second circuit 3b is mounted on an LSI chip for RFID.

[0012] The antenna 1 receives a high-frequency radio signal RF transmitted from a reader / writer for RFID tags or the like, and outputs an antenna input power PIN corresponding to the received radio signal RF to the receiver 2. The receiver 2 has a first matching circuit 2a and a second matching circuit 2b connected in parallel to the antenna 1 via a branch point BN.

[0013] The first matching circuit 2a includes a delay element and has a function of performing impedance matching. The first matching circuit 2a inputs a part of the antenna input power PIN input via a branch point BN as a first input power PIN1 (a high-frequency first input signal IN1) to the first circuit 3a. The first circuit 3a operates by receiving the first input power PIN1. The first matching circuit 2a includes a π-type circuit, a T-type circuit, or a distributed constant circuit, and is designed so that the impedance decreases as the antenna input power PIN increases.

[0014] The second matching circuit 2b includes a delay element and has a function of performing impedance matching. The second matching circuit 2b inputs another part of the antenna input power PIN input via the branch point BN as a second input power PIN2 (a high-frequency second input signal IN2) to the second circuit 3b. The second circuit 3b operates by receiving the second input power PIN2. The second matching circuit 2b includes a π-type circuit, a T-type circuit, or a distributed constant circuit, and is designed so that the impedance increases as the antenna input power PIN increases.

[0015] The delay amount of the delay element of the first matching circuit 2a and the delay amount of the delay element of the second matching circuit 2b are different from each other. As a result, the phases of the first input signal IN1 and the second input signal IN2 are shifted from each other. For example, the delay amount of the delay element of the first matching circuit 2a is set to 0°, and the delay amount of the delay element of the second matching circuit 2b is set to +90° or +45°. That is, the phase of the second input signal IN2 is delayed, for example, by 90° or 45° compared to the phase of the first input signal IN1. Here, the delay amount is indicated by the phase of the radio signal RF received by the antenna 1. For example, the delay amount of the delay elements of the first matching circuit 2a and the second matching circuit 2b is smaller than one period of the radio signal RF.

[0016] The delay amount of the delay element of the first matching circuit 2a may be set to 0°, and the delay amount of the delay element of the second matching circuit 2b may be set to -90° or -45°. The delay amount of the delay element of the first matching circuit 2a may be set to -45°, and the delay amount of the delay element of the second matching circuit 2b may be set to +45°. Furthermore, the delay amount of the delay element of the first matching circuit 2a may be set to +45°, and the delay amount of the delay element of the second matching circuit 2b may be set to -45°.

[0017] The delay amount of the delay elements in the first matching circuit 2a and the second matching circuit 2b is set to a value that obtains a predetermined communication characteristic, taking into consideration the impedance of the antenna 1 and the frequency characteristics of the impedance on the first circuit 3a side and the second circuit 3b side, etc. In this case, the delay amount of the delay elements in the first matching circuit 2a and the second matching circuit 2b may be set in consideration of simplification of the first matching circuit 2a and the second matching circuit 2b.

[0018] FIG. 2 shows an example of the impedance characteristics and power characteristics of the receiver 2 in FIG. 1. That is, FIG. 2 shows an example of the operation method of the receiver 2. As shown in the impedance characteristics on the left side of FIG. 2, the impedance of the first matching circuit 2a as seen from the LSI side from the branch point BN is approximately inversely proportional to the antenna input power PIN. The impedance of the second matching circuit 2b as seen from the LSI side from the branch point BN is approximately proportional to the antenna input power PIN. That is, the impedance of the first matching circuit 2a decreases as the antenna input power PIN increases, and the impedance of the second matching circuit 2b increases as the antenna input power PIN increases.

[0019] When the antenna input power PIN is small, since the impedance of the first matching circuit 2a is high and the impedance of the second matching circuit 2b is low, most of the antenna input power PIN is supplied as the second input power PIN2 to the second circuit 3b (PIN1 < PIN2). Also, when the antenna input power PIN is large, since the impedance of the first matching circuit 2a is low and the impedance of the second matching circuit 2b is high, most of the antenna input power PIN is supplied as the first input power PIN1 to the first circuit 3a (PIN1 > PIN2) Thereby, as shown on the right side of FIG. 2, when the antenna input power PIN exceeds the power value PINmin2, the second input power PIN2 exceeds the minimum power PIN2min at which the second circuit 3b can operate, and the second circuit 3b can start operating. At this time, since the impedance of the first matching circuit 2a is high and the first input power PIN1 is lower than the second input power PIN2, the first circuit 3a has not reached the minimum power PIN1min at which it can operate. Therefore, the first circuit 3a does not operate. Thus, most of the antenna input power PIN can be used for the operation of the second circuit 3b, and the power efficiency can be improved.

[0020] On the other hand, when the antenna input power PIN exceeds the power value PINmin1, the first input power PIN1 exceeds the minimum power PIN1min at which the first circuit 3a can operate, and the first circuit 3a can start operating. At this time, the impedance of the second matching circuit 2b is high, and the increase in the second input power PIN2 reaches a plateau. This makes it possible to prevent excess second input power PIN2 from being supplied to the second circuit 3b. Therefore, it is possible to supply the minimum necessary second input power PIN2 to the second circuit 3b and use the remaining power for the operation of the first circuit 3a, thereby improving power efficiency.

[0021] As described above, in this embodiment, the first input power PIN1 and the second input power PIN2 according to the antenna input power PIN can be made to approach ideal power distribution characteristics. By making the delay amounts (phases) of the delay elements of the first matching circuit 2a and the second matching circuit 2b different from each other, the impedance change characteristics of the first matching circuit 2a and the second matching circuit 2b with respect to the antenna input power PIN can be set to be opposite to each other.

[0022] That is, the impedance of the first matching circuit 2a can be decreased as the antenna input power PIN increases, and the impedance of the second matching circuit 2b can be increased as the antenna input power PIN increases. Therefore, as described in Fig. 2, the first input power PIN1 supplied to the first circuit 3a and the second input power PIN2 supplied to the second circuit 3b can be appropriately set according to the antenna input power PIN. As a result, in the receiver 2 that converts the radio signal RF received via the antenna 1 into a plurality of powers, the first input power PIN1 and the second input power PIN2 can be appropriately distributed according to the magnitude of the antenna input power PIN, and the power efficiency can be optimized for each.

[0023] Fig. 3 shows an example of a system including a receiver according to another embodiment. Detailed description of elements similar to those in Fig. 1 will be omitted. The system 102 shown in Fig. 3 includes an antenna 10, a receiver 20, an LSI 30, and electronic paper 40. The electronic paper 40 is an example of an electronic device.

[0024] The receiver 20 has a balun (balanced-unbalanced converter) 21 and matching circuits 22, 23, and 24. The LSI 30 has a first circuit 31 and a second circuit 32. Although not particularly limited, the system 102 is, for example, an RFID battery-less electronic paper tag. The LSI 30 is an LSI chip for RFID.

[0025] The receiver 20 receives the radio signal RF from the antenna 10 as an unbalanced signal. The balun 21 is disposed between the antenna 10 and a matching circuit 22, and converts the unbalanced signal received from the antenna 10 into a balanced signal and outputs the balanced signal to the matching circuit 22.

[0026] The matching circuit 22 is disposed between the balun 21 and the branch points BN+ and BN-, and performs impedance matching between the balun 21 and the branch point BN. For example, the matching circuit 22 has elements 22a, 22b, 22c, and 22d as a π-type circuit. At least one of the elements 22a, 22b, 22c, and 22d includes a delay element.

[0027] The matching circuit 23 is disposed between the branch points BN+, BN- and the first circuit 31 of the LSI 30, and performs impedance matching between the branch points BN+, BN- and the first circuit 31. For example, the matching circuit 23 has elements 23a, 23b, 23c, and 23d as a π-type circuit. At least one of the elements 23a, 23b, 23c, and 23d includes a delay element. The matching circuit 23 outputs a part of the antenna input power received via the matching circuit 22 to the first circuit 31 as the first input power. Note that the X mark shown on the element 24d indicates that the element 24d is not implemented in this embodiment. In Figs. 7 and 10 described later, the elements marked with an X also indicate that they are not implemented.

[0028] The matching circuit 24 is disposed between the branch points BN+, BN- and the second circuit 32 of the LSI 30, and performs impedance matching between the branch points BN+, BN- and the second circuit 32. For example, the matching circuit 24 has elements 24a, 24b, 24c, and 24d as a π-type circuit. At least one of the elements 24a, 24b, 24c, and 24d includes a delay element. The matching circuit 24 outputs another portion of the antenna input power received via the matching circuit 22 to the second circuit 32 as a second input power. The matching circuits 22, 23, and 24 are The symbols P (PB, P1, P23, P2, P3, P2L, P3L) shown in Fig. 3 indicate power. The symbols Z (ZB, Z1, Z23, Z2, Z3, Z2L, Z3L) shown in Fig. 3 indicate impedance when viewed toward the arrow, which will be described in Fig. 4 to Fig. 6. The powers P2L, P3L and the impedances Z1, Z23, Z2, Z3, Z2L, Z3L will be described in Fig. 5 and Fig. 6.

[0029] Note that the elements in the matching circuits 22, 23, 24 shown in Fig. 3 are merely examples, and elements may be added or removed. The matching circuits 22, 23, 24 may include a T-type circuit including a delay element or a distributed constant circuit including a delay element instead of a π-type circuit. The matching circuit 22 is an example of a third matching circuit. The matching circuit 23 is an example of a first matching circuit. The matching circuit 24 is an example of a second matching circuit.

[0030] The first circuit 31 has a power supply voltage generation circuit PS1 that generates a first power supply voltage for operating the electronic paper 40 according to a first input power (P2L) received from the matching circuit 23. The first circuit 31 is represented as an equivalent circuit including an input capacitance CP2 and an input resistance RP2. The second circuit 32 has a power supply voltage generation circuit PS2, a communication circuit RF-COM, a logic circuit LG, and FRAM (registered trademark). The second circuit 32 is represented as an equivalent circuit including an input capacitance CP3 and an input resistance RP3.

[0031] FRAM is an example of an electrically rewritable non-volatile memory. The power supply voltage generating circuit PS2 generates a second power supply voltage for operating the communication circuit RF-COM, the logic circuit LG, and the FRAM in response to the second input power (P3L) received from the matching circuit 24. When the second power supply voltages used by the communication circuit RF-COM, the logic circuit LG, and the FRAM are different from each other, the power supply voltage generating circuit PS2 may have a function of generating a plurality of types of second power supply voltages.

[0032] The communication circuit RF-COM performs reception processing of the wireless signal RF received via the antenna 10, and performs transmission processing of the wireless signal RF transmitted from the antenna 10. The communication circuit RF-COM is an example of an extraction unit that extracts display information to be displayed on the electronic paper 40, which is information contained in the wireless signal RF received by the antenna 10.

[0033] The logic circuit LG writes display information received from the communication circuit RF-COM to the FRAM. The logic circuit LG generates a control signal for operating the electronic paper 40, reads display information to be displayed on the electronic paper 40 from the FRAM, and outputs the control signal and the display information to the electronic paper 40. The logic circuit LG also outputs transmission information to be transmitted from the antenna 10 to the communication circuit RF-COM. The logic circuit LG is an example of a control circuit.

[0034] The electronic paper 40 operates by receiving a first power supply voltage from the power supply voltage generating circuit PS1, and performs an operation of rewriting the display on the electronic paper 40 in response to a control signal received from the logic circuit LG.

[0035] The minimum value of the second power supply voltage at which the communication circuit RF-COM, the logic circuit LG, and the FRAM can operate is lower than the minimum value of the first power supply voltage at which the electronic paper 40 can operate. Therefore, even when the distance between the RFID tag and the reader / writer is far and the antenna input power is low, and the first power supply voltage required for the rewriting operation of the electronic paper 40 cannot be generated, the second circuit 32 can be operated to read the EPC (Electronic Product Code) of the RFID tag from the reader / writer, and the item to which the RFID tag is attached can be identified from a distance.

[0036] Note that the system 102 may have another electronic device instead of the electronic paper 40. In this case as well, the LSI 30 outputs from the first circuit 31 a first power supply voltage for operating the electronic device, and outputs from the second circuit 32 a control signal for controlling the operation of the electronic device.

[0037] 4 to 6 show an example of electrical characteristics of the receiver 20 and the LSI 30 in Fig. 3. In the following, for example, the frequency of the wireless signal RF is 920 MHz, the minimum power at which a rewrite operation for rewriting the display on the electronic paper 40 is possible is +20 dBm, and the minimum power at which the second circuit 32 (the communication circuit RF-COM, the logic circuit LG, and the FRAM) is possible to operate is -20 dBm.

[0038] For example, the input capacitance CP2 of the first circuit 31 of the LSI 30 is set to 3 pF, and the input capacitance CP3 of the second circuit 32 of the LSI 30 is set to 1 pF. The input resistance RP2 of the first circuit 31 and the input resistance RP3 of the second circuit 32 are power dependent, and therefore their respective power characteristics are shown in FIG.

[0039] The circuit constants of the matching circuit 22 are 7.5 nH for the element 22a, 1.4 nH for the elements 22b and 22c, and 3.3 pF for the element 22d. This achieves matching between 50 Ω on the antenna 10 and balun 21 side and 100 Ω on the branch points BN+ and BN- side, and a delay of 13.4°.

[0040] The circuit constants of the matching circuit 23 are 10 nH for the element 23a, 0 Ω for the elements 23b and 23c, and an element 23d is not mounted. This achieves matching between 100 Ω on the branch points BN+ and BN- side and 100 Ω / / 3 pF (CP2) on the first circuit 31 side, and a delay of 0°.

[0041] The circuit constants of the matching circuit 24 are 100 nH for the element 24a, 0.6 pF for the elements 24b and 24c, and 23 nH for the element 24d. This achieves matching between 100 Ω on the branch points BN+ and BN- side and 3.5 kΩ / / 1 pF (CP3) on the second circuit 32 side, and a delay of -90°.

[0042] Figure 4 shows an example of the power characteristics and Smith chart of the input resistors RP2 and RP3 in Figure 3. Since the input resistors RP2 and RP3 have different applications, their power dependencies are different from each other and their Smith charts are different from each other.

[0043] Fig. 5 is a diagram showing an example of the power characteristics and power efficiency of P2L and P3L in Fig. 3, and the Smith charts of Z2L and Z3L. That is, Fig. 5 shows an example of the operation method of the receiver 20. As shown in the Smith chart of Z2L, the impedance Z2L has a characteristic that slopes downward to the right due to the input capacitance CP2. As shown in the Smith chart of Z3L, the impedance Z3L, which has a different application from the impedance Z2L, also has different characteristics from the impedance Z2L.

[0044] In the power characteristics of power P2L, which is the operating power of electronic paper 40, rewriting operation of electronic paper 40 is possible when power PM ≧+20 dBm, where P2L ≧+20 dBm, and electronic paper 40 can operate at approximately the theoretical limit. Here, power PM is the maximum available power of antenna 10 (the maximum power that can be supplied when matching is optimal).

[0045] In the power characteristics of the power P3L which is the operating power of the second circuit 32, the logic circuit LG etc. of the second circuit 32 can operate at approximately the theoretical limit value with power P3L≧−20 dBm and power PM≧−20 dBm.

[0046] As a result, as shown by the power efficiencies of P2L and P3L, the power efficiency of the power P2L can be set to 0% at the power P3L of about -20 dBm at which the logic circuit LG of the second circuit 32 and the like start to operate. Therefore, almost all of the antenna input power can be used to operate the logic circuit LG of the second circuit 32 and the like.

[0047] Furthermore, the power efficiency of the power P3L near the power P2L=+20 dBm at which the electronic paper 40 starts to operate can be reduced to 5% or less. Therefore, most of the antenna input power can be used to operate the electronic paper 40, and it is possible to prevent unnecessary supply of power P3L to the logic circuit LG of the second circuit 32, etc. As a result, it is possible to optimize the power efficiency for each of a plurality of power states (+20 dBm for the rewrite operation of the electronic paper 40 and -20 dBm for the second circuit 32).

[0048] 3, the number of elements in the matching circuit can be reduced, and the circuit scale of the receiver 20 can be reduced. As a result, the reduction in the number of parts can improve the reliability of the system 102, and reduce the cost of the system 102.

[0049] For example, element 22d of matching circuit 22, element 23a of matching circuit 23, and element 24a of matching circuit 24 may be left unmounted. This is because the parallel combined admittance of element 22d (3.3 pF, +19.08 mS), element 23a (100 nH, -j1.73 mS), and element 24a (10 nH, -j17.30 mS) is +j0.05 mS (almost 0), and the characteristics are almost unchanged.

[0050] Fig. 6 shows an example of the Smith chart of Z2, Z3, Z23, and Z1 in Fig. 3. As shown in the Smith chart of Z2, the impedance Z2 is adjusted to 100Ω at +20 dBm, and to a higher impedance as the power decreases. Here, the reason for adjusting to 100Ω instead of 50Ω is to simplify the circuit of the matching circuit 23.

[0051] As shown in the Smith chart of Z3, the impedance Z3 is adjusted to 100Ω at −20 dBm by impedance matching, and to a higher impedance as the power increases by a delay of −90°.

[0052] As shown in the Smith chart of Z23, the impedance Z23 is adjusted to match 100Ω at +20 dBm and −20 dBm. As shown in the Smith chart of Z1, the impedance Z1 is adjusted to match 50Ω, which is the impedance on the antenna 10 side, at +20 dBm and −20 dBm.

[0053] As described above, this embodiment can also provide the same effects as the above-mentioned embodiment. For example, the powers P2L and P3L according to the antenna input power can be made to approach ideal power distribution characteristics. By making the delay amounts (phases) of the delay elements of the matching circuits 23 and 24 different from each other, the characteristics of the changes in the impedances Z2L and Z3L relative to the antenna input power can be set to be opposite to each other. That is, the impedance Z2L can be lowered as the antenna input power increases, and the impedance Z3L can be raised as the antenna input power increases.

[0054] 5, the power P2L supplied to the first circuit 31 and the power P3L supplied to the second circuit 32 can be appropriately set according to the antenna input power. As a result, in the receiver 20 that converts the radio signal RF received via the antenna 10 into a plurality of powers, the powers P2L and P3L can be appropriately distributed according to the magnitude of the antenna input power, and the power efficiency can be optimized.

[0055] It is possible to reduce the maximum available power PM for obtaining the minimum power (+20 dBm) of the power P2L for operating the matching circuit 23, compared to the conventional case. For this reason, for example, when the system 102 (RFID tag) is attached to a product shelf or product in a store, the distance between the system 102 and a reader / writer that can identify the product by reading the EPC can be made longer than before (for example, 3 to 10 times).

[0056] As a result, it is possible to increase the number of systems 102 that can transmit information to the reader / writer. Note that the system 102 may include other electronic devices instead of the electronic paper 40.

[0057] Fig. 7 shows an example of a system including another receiver. The same elements as those in Fig. 3 are given the same reference numerals, and detailed description thereof will be omitted. The system 104 shown in Fig. 7 includes an antenna 10, a receiver 20A, an LSI 30, and an electronic paper 40. The receiver 20A has a similar configuration to the receiver 20 in Fig. 3, except that it has a matching circuit 24A instead of the matching circuit 24 of the receiver 20 in Fig. 3. In the matching circuit 24A, the elements 24a and 24d are not mounted, and the elements 24b and 24c are set to 16 pF.

[0058] Fig. 8 and Fig. 9 show an example of electrical characteristics of the receiver 20A in Fig. 7. As in the above-described embodiment, the frequency of the wireless signal RF is 920 MHz, the minimum power at which the electronic paper 40 can be rewritten is +20 dBm, and the minimum power at which the second circuit 32 (the communication circuit RF-COM, the logic circuit LG, and the FRAM) can operate is -20 dBm.

[0059] As in Fig. 3, the input capacitance CP2 of the first circuit 31 in Fig. 7 is 3 pF, and the input capacitance CP3 of the second circuit 32 in Fig. 7 is 1 pF. The input resistances RP2 and RP3 have power dependence similar to the input resistances RP2 and RP3 in Fig. 3. Therefore, the power characteristics and Smith chart of the input resistances RP2 and RP3 are the same as those in Fig. 4.

[0060] The circuit constants of the matching circuit 22 are the same as those in the above-mentioned embodiment, with the element 22a being 7.5 nH, the elements 22b and 22c being 1.4 nH, and the element 22d being 3.3 pF. This achieves matching between the 50 Ω on the antenna 10 and balun 21 side and the 97-j17 Ω on the branch points BN+ and BN- side, and a delay of 13.4°.

[0061] As in the above-described embodiment, the circuit constants of the matching circuit 23 are 10 nH for the element 23a, 0 Ω for the elements 23b and 23c, and the element 23d is not mounted. This achieves matching between 100 Ω on the branch points BN+ and BN- sides and 100 Ω / / 3 pF (CP2) on the first circuit 31 side, and a delay of 0°. The circuit constants of the matching circuit 24 are 1 pF for the elements 24b and 24c, and the elements 24a and 24d are not mounted. This reduces the amount of coupling to the second circuit 32 side.

[0062] Fig. 8 shows an example of the power characteristics and power efficiency of P2L and P3L in Fig. 7, and the Smith charts of Z2L and Z3L. The Smith charts of Z2L and Z3L are the same as Fig. 6. Since the power characteristics of power P2L are almost the same as Fig. 5, the rewriting operation of electronic paper 40 becomes possible when power PM ≧+20 dBm, which is the power P2L ≧+20 dBm, and the electronic paper 40 can operate at the theoretical limit value.

[0063] On the other hand, the logic circuit LG of the second circuit 32 can operate when PM≧0 dBm, where P3L≧−20 dBm. Therefore, the maximum available power PM is degraded by nearly 20 dB from the theoretical limit. Therefore, in the system 104 of FIG. 7, a larger antenna input power is required to operate the logic circuit LG of the second circuit 32, compared to the system 102 of FIG. 3. As a result, the distance between the system 104 and a reader / writer that can identify products by reading the EPC is shorter (for example, one-third to one-tenth) than in the above-mentioned embodiment.

[0064] Figure 9 shows an example of Smith charts of Z2, Z3, Z23, and Z1 in Figure 7. The Smith chart of Z2 is the same as Figure 6. As shown in the Smith chart of Z3, the impedance Z3 is adjusted to a high impedance regardless of the power in order to reduce the amount of coupling.

[0065] As shown in the Smith chart of Z23, the impedance Z23 is adjusted to be approximately 100Ω at +20 dBm. As shown in the Smith chart of Z1, the impedance Z1 is adjusted to match 50Ω, which is the impedance on the antenna 10 side, at +20 dBm.

[0066] Fig. 10 shows another example of a system including another receiver. The same elements as those in Fig. 3 are given the same reference numerals, and detailed description thereof will be omitted. The system 106 shown in Fig. 10 includes an antenna 10, a receiver 20B, an LSI 30B, and an electronic paper 40. The receiver 20B has the same configuration as the receiver 20 in Fig. 3, except that it includes matching circuits 22B and 24B instead of the matching circuits 22 and 24 in Fig. 3.

[0067] LSI30B has the same configuration as LSI30 in Fig. 3, except that it has a second circuit 32B instead of the second circuit 32 in Fig. 3. The second circuit 32B has the same configuration as the second circuit 32 in Fig. 3, except that the input capacitance CP3 is different from the input capacitance CP3 in Fig. 3.

[0068] Figures 11 to 13 show an example of the electrical characteristics of the receiver 20B of Figure 10. In the following, for example, the frequency of the wireless signal RF is 920 MHz, the minimum power at which a rewrite operation for rewriting the display on the electronic paper 40 is possible is +20 dBm, and the minimum power at which the second circuit 32 (the communication circuit RF-COM, the logic circuit LG, and the FRAM) is possible to operate is -20 dBm.

[0069] For example, the input capacitance CP2 of the first circuit 31 of the LSI 30B is set to 3 pF, and the input capacitance CP3 of the second circuit 32B of the LSI 30B is set to 3 pF. The power supply voltage generation circuits PS1 and PS2 have the same characteristics. The input resistance RP2 of the first circuit 31 and the input resistance RP3 of the second circuit 32 are power dependent and are the same as each other. The power characteristics of the input resistances RP2 and RP3 are shown in FIG.

[0070] The circuit constants of the matching circuit 22B are 0Ω for the elements 24b and 24c, and elements 22a and 22d are not mounted. This achieves matching between 50Ω on the antenna 10 and balun 21 side and 50Ω on the branch points BN+ and BN- side, and a delay of 0°.

[0071] 3, the circuit constants of the matching circuit 23 are 10 nH for the element 23a, 0 Ω for the elements 23b and 23c, and an element 23d is not mounted. This achieves matching between 100 Ω on the branch points BN+ and BN- side and 100 Ω / / 3 pF (CP2) on the first circuit 31 side, and a delay of 0°.

[0072] Matching circuit 23 and matching circuit 25B have the same characteristics except for the delay, and except for canceling the admittance of input capacitance CP2 and input capacitance CP3, they only convert 100Ω to 100Ω and do not substantially have a matching function.

[0073] Fig. 11 shows an example of the power characteristics and Smith chart of the input resistors RP2 and RP3 of Fig. 10. The power characteristics of the input resistors RP2 and RP3 are the same, and the Smith charts of the input resistors RP2 and RP3 are the same.

[0074] FIG. 12 shows an example of the power characteristics and power efficiency of P2L and P3L in FIG. 10, and the Smith charts of Z2L and Z3L. In the power characteristics of the power P2L, which is the operating power of the electronic paper 40, the rewriting operation of the electronic paper 40 is possible at power PM≧+30 dBm, where power P2L≧+20 dBm. In the power characteristics of the power P3L, which is the operating power of the second circuit 32B, the logic circuit LG of the second circuit 32B is possible at power PM≧-15 dBm, where power P3L≧-20 dBm. As shown in the power efficiencies of P2L and P3L, the optimal power efficiency is limited to a specific power condition (in this example, around 0 dBm). Note that, as shown in the Smith charts of Z2L and Z3L, the characteristics of the impedances Z2L and Z3L are the same.

[0075] Fig. 13 shows an example of the Smith chart of Z2, Z3, Z23, and Z1 in Fig. 10. As shown in the Smith chart of Z2, the impedance Z2 is adjusted to 100Ω when the power P2L is -3 dBm (P2L and P3L combined is 0 dBm), and is adjusted so that the impedance becomes higher as the power becomes smaller.

[0076] As shown in the Smith chart of Z3, the impedance Z3 is adjusted to 100Ω when the power P3L is -3dBm (P2L and P3L combined is 0dBm), and is adjusted so that the impedance becomes higher as the power increases. The Smith charts of Z23 and Z1 are the same, and are adjusted to 50Ω (two parallel 100Ω) when the power is +0dBm.

[0077] Regarding the embodiment shown in the above-mentioned Figs. 1 to 6, the following supplementary notes are further disclosed. (Appendix 1) a first matching circuit that receives, via a branch point, antenna input power input from an antenna in response to a radio signal received by the antenna, inputs a portion of the received antenna input power to a first circuit as a first input power, and reduces impedance as the antenna input power increases; a second matching circuit that receives the antenna input power via the branch point, inputs another part of the received antenna input power to a second circuit as a second input power, and increases its impedance as the antenna input power increases; A receiver having: (Appendix 2) When the antenna input power is smaller than a predetermined value, the first input power is smaller than the second input power; When the antenna input power is greater than the predetermined value, the first input power is greater than the second input power. 2. A receiver as defined in claim 1. (Appendix 3) A phase of a first input signal that the first matching circuit inputs to the first circuit as the first input power and a phase of a second input signal that the second matching circuit inputs to the second circuit as the second input power are different from each other. 2. A receiver as claimed in claim 1 or 2. (Appendix 4) At least one of the first matching circuit and the second matching circuit has a delay element that delays the phase of the second input signal relative to the phase of the first input signal. 4. A receiver as described in claim 3. (Appendix 5) The phase delay caused by the delay element is less than one period of the radio signal received by the antenna. 5. A receiver as described in claim 4. (Appendix 6) a third matching circuit arranged between the antenna and the branch point and performing impedance matching between the antenna and the branch point; 6. A receiver according to any one of claims 1 to 5. (Appendix 7) A system including a receiver including a first matching circuit and a second matching circuit, each of which receives an antenna input power input from an antenna through a branch point in response to a radio signal received by the antenna, a first circuit, and a second circuit, the first matching circuit inputs a part of the received antenna input power to the first circuit as a first input power, and an impedance decreases as the antenna input power increases; the second matching circuit inputs another part of the received antenna input power to the second circuit as a second input power, and an impedance increases as the antenna input power increases; the first circuit is powered by the first input power; The second circuit is operated by the second input power. system. (Appendix 8) further comprising an electronic device connected to the first circuit and the second circuit; the first circuit includes a first power supply voltage generating circuit configured to generate a first power supply voltage for operating the electronic device based on the first input power; The second circuit is a second power supply voltage generating circuit that generates a second power supply voltage based on the second input power; a control circuit that is powered by the second power supply voltage and that generates a control signal for operating the electronic device; 8. The system of claim 7. (Appendix 9) the electronic device is electronic paper, The second circuit is an electrically rewritable non-volatile memory that stores display information to be displayed on the electronic paper; An extractor that extracts the display information included in the wireless signal received by the antenna, The control circuit further includes a function of writing the display information extracted by the extraction unit to the non-volatile memory, and a function of reading the display information from the non-volatile memory and outputting it to the electronic paper. 9. The system of claim 8. (Appendix 10) a substrate on which the first matching circuit, the second matching circuit, the first circuit, and the second circuit are mounted, The antenna is built into the substrate. 11. The system according to any one of claims 7 to 10. (Appendix 11) 1. A method for operating a receiver including a first matching circuit and a second matching circuit, each of which receives an antenna input power input from an antenna in response to a radio signal received by the antenna through a branch point, comprising: the first matching circuit inputs a part of the received antenna input power to a first circuit as a first input power, and reduces impedance as the antenna input power increases; The second matching circuit inputs another part of the received antenna input power to a second circuit as a second input power, and increases impedance as the antenna input power increases. How the receiver works.

[0078] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims cover the features and advantages of the embodiments as described above without departing from the spirit and scope of the claims. In addition, any improvements and modifications can be easily made by a person having ordinary skill in the art. Therefore, it is not intended to limit the scope of the inventive embodiments to the above, and appropriate improvements and equivalents within the scope of the embodiments disclosed can be used. [Explanation of symbols]

[0079] 1 Antenna 2 Receiver 2a 1st matching circuit 2b Second matching circuit 3 Circuit section 3a 1st circuit 3b 2nd circuit 10 Antennas 20, 20A, 20B Receiver 21 Balan 22, 22B matching circuit 22a, 22b, 22c, 22d Elements 23 Matching circuit 23a, 23b, 23c, 23d Elements 24, 24A, 24B matching circuit 24a, 24b, 24c, 24d Elements LSI 30, 30B 31 1st circuit 32, 32B 2nd circuit 40 Electronic Paper 100, 102, 104, 106 systems BN, BN+, BN- Branch points CP2, CP3 input capacitance LG Logic Circuit IN1 First input signal IN2 Second input signal PIN antenna input power PIN1 1st input power PIN2 Second input power RF radio signal RF-CON communication circuit RP2, RP3 Input resistors

Claims

1. a first matching circuit that receives, via a branch point, antenna input power input from an antenna in response to a radio signal received by the antenna, inputs a portion of the received antenna input power to a first circuit as a first input power, and reduces impedance as the antenna input power increases; a second matching circuit that receives the antenna input power via the branch point, inputs another part of the received antenna input power to a second circuit as a second input power, and increases its impedance as the antenna input power increases; A receiver having:

2. when the antenna input power is less than a predetermined value, the first input power is less than the second input power; When the antenna input power is greater than the predetermined value, the first input power is greater than the second input power.

2. The receiver of claim 1.

3. A phase of a first input signal that the first matching circuit inputs to the first circuit as the first input power and a phase of a second input signal that the second matching circuit inputs to the second circuit as the second input power are different from each other.

3. A receiver as claimed in claim 1 or 2.

4. At least one of the first matching circuit and the second matching circuit has a delay element that delays the phase of the second input signal relative to the phase of the first input signal.

4. The receiver of claim 3.

5. A system including a receiver including a first matching circuit and a second matching circuit, each of which receives an antenna input power input from an antenna through a branch point in response to a radio signal received by the antenna, a first circuit, and a second circuit, the first matching circuit inputs a part of the received antenna input power to the first circuit as a first input power, and an impedance decreases as the antenna input power increases; the second matching circuit inputs another part of the received antenna input power to the second circuit as a second input power, and an impedance increases as the antenna input power increases; the first circuit is powered by the first input power; The second circuit is operated by the second input power. system.

6. further comprising an electronic device connected to the first circuit and the second circuit; the first circuit includes a first power supply voltage generating circuit that generates a first power supply voltage for operating the electronic device based on the first input power; The second circuit is a second power supply voltage generating circuit that generates a second power supply voltage based on the second input power; a control circuit that operates on the second power supply voltage and generates a control signal for operating the electronic device; The system of claim 5.

7. the electronic device is electronic paper, The second circuit is an electrically rewritable non-volatile memory that stores display information to be displayed on the electronic paper; An extractor that extracts the display information included in the wireless signal received by the antenna, The control circuit further includes a function of writing the display information extracted by the extraction unit to the non-volatile memory, and a function of reading the display information from the non-volatile memory and outputting it to the electronic paper. The system of claim 6.

8. 1. A method for operating a receiver including a first matching circuit and a second matching circuit, each of which receives an antenna input power input from an antenna in response to a radio signal received by the antenna through a branch point, comprising: the first matching circuit inputs a part of the received antenna input power to a first circuit as a first input power, and decreases impedance as the antenna input power increases; The second matching circuit inputs another part of the received antenna input power to a second circuit as a second input power, and increases impedance as the antenna input power increases. How the receiver works.

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