Synthesis circuit

Abstract

To reduce the size of a backscatter type communication system.SOLUTION: A synthesis circuit includes a transmission circuit configured to be connected to an antenna, and a control circuit configured to control the impedance of the transmission circuit, and the transmission circuit includes multiple impedance circuits with different impedances, and multiple first switch elements, one of which is connected to each of multiple impedance circuits. The control circuit includes multiple comparators respectively connected to the first switch elements, and a voltage divider circuit composed of a plurality of resistance elements configured to divide an input reference voltage and output voltage divider power to each of the multiple comparators.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a synthesis circuit. [Background technology]

[0002] A backscattering method is known as a data communication method for wireless communication devices. For example, Patent Document 1 discloses a technique for realizing a single sideband by suppressing either an upper sideband (USB) signal or a lower sideband (LSB) signal using a splitter / combiner. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2005-323223 A Summary of the Invention [Problem to be solved by the invention]

[0004] In an RFID (Radio Frequency Identification) system that performs backscatter data communication, there is a demand for miniaturization of wireless communication devices. However, Patent Document 1 uses a splitter / combiner to realize a single sideband, which is a disadvantage in terms of miniaturization.

[0005] An object of the present disclosure is to provide a combining circuit that can reduce the size of a backscattering wireless communication device. [Means for solving the problem]

[0006] A combining circuit according to one embodiment of the present disclosure includes a transmission circuit configured to be connected to an antenna and a control circuit configured to control the impedance of the transmission circuit, wherein the transmission circuit includes a plurality of impedance circuits each having a different impedance, and a plurality of first switch elements, one of which is connected to each of the plurality of impedance circuits, and the control circuit includes a plurality of comparators connected to each of the first switch elements, and a voltage divider circuit including a plurality of resistance elements configured to divide an input reference voltage and output divided power to each of the plurality of comparators. Effect of the Invention

[0007] According to the present disclosure, it is possible to reduce the size of a single sideband backscattering wireless communication device. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing an example of a configuration of a wireless communication device according to an embodiment. [Diagram 2] FIG. 2 is a diagram for explaining a method for controlling the rotation of impedance on a complex plane according to the embodiment. [Figure 3A] FIG. 3A is a diagram for explaining a change in a backscatter signal. [Figure 3B] FIG. 3B is a diagram for explaining a change in the backscatter signal. [Figure 3C] FIG. 3C is a diagram for explaining a change in the backscatter signal. [Figure 4] FIG. 4 is a diagram for explaining a method for controlling the impedance of the transmission circuit according to the embodiment. [Diagram 5] FIG. 5 is a diagram for explaining the position on the complex plane of the impedance of the transmission circuit according to the embodiment. [Figure 6A] FIG. 6A is a diagram showing an example of an input signal. [Figure 6B] FIG. 6B is a diagram showing an example of an input signal. [Figure 7] FIG. 7 is a diagram showing an example of a spectral waveform of a backscatter signal. [Figure 8] FIG. 8 is a diagram showing an example of a spectral waveform of a backscatter signal. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the present disclosure is not limited to these embodiments, and when there are multiple embodiments, the present disclosure also includes a configuration in which each embodiment is combined. In the following embodiments, the same parts are denoted by the same reference numerals, and duplicated descriptions are omitted.

[0010] [Embodiment] The configuration of a wireless communication device according to an embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the configuration of a wireless communication device according to an embodiment.

[0011] 1, the wireless communication device 1 includes an antenna 10, a BPF (Band Pass Filter) 11, an RFBS (Radio Frequency Backscatter) device 20, a control device 30, and a sensor 40. The wireless communication device 1 is a communication device configured to perform wireless communication using a backscatter method such as RFID.

[0012] The antenna 10 is configured to receive a signal transmitted to the wireless communication device 1. The antenna 10 is configured to transmit radio waves toward the outside of the wireless communication device 1. The BPF 11 is a filter configured to pass a signal in a desired frequency band.

[0013] The RFBS device 20 includes a high frequency switch 21, an amplifier 22, a demodulator 23, an oscillator 24, an LPF (Low Pass Filter) 25, an LPF 26, a control circuit 27, and a transmission circuit 28. The RFBS device 20 is a wireless communication device that supports backscattering data communication. In backscattering data communication, communication is performed by utilizing the reflection of transmitted radio waves.

[0014] The high frequency switch 21 is configured to switch the connection between the antenna 10 and a transmission circuit system or a reception circuit system. The high frequency switch 21 is configured to be able to connect the transmission circuit system to the antenna 10. The wireless communication device 1 is configured to transmit when the antenna 10 is connected to the transmission circuit system. The high frequency switch 21 is configured to be able to connect the reception circuit system to the antenna 10. The transmission circuit system includes an oscillator 24, an LPF 25, an LPF 26, a control circuit 27, and a transmission circuit 28. The reception circuit system includes an amplifier 22 and a demodulator 23.

[0015] The amplifier 22 is configured to amplify and output a signal received from the antenna 10. The amplifier 22 is configured to output the amplified signal to the demodulation unit 23. The demodulation unit 23 is configured to perform demodulation processing on the input signal. The demodulation unit 23 is configured to demodulate the signal received from the amplifier 22. For example, the demodulation unit 23 is configured to perform demodulation processing on the signal received from the amplifier 22 (a modulated signal such as ASK (Amplitude Shift Keying)).

[0016] The control device 30 is realized, for example, by a processor or the like executing a program stored therein using a RAM (Random Access Memory) or the like as a working area. The control device 30 may be a controller. The control device 30 may be realized, for example, by an integrated circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). The control device 30 may be realized by a combination of software and hardware.

[0017] The control device 30 is configured to output serial data S1 based on output data from the sensor 40 to the control circuit 27 via the LPF 25. The control device 30 is configured to output serial data S2 based on output data from the sensor 40 to the control circuit 27 via the LPF 26. The serial data S1 and the serial data S2 are out of phase with each other by approximately 90°.

[0018] The control device 30 is configured to output a control signal S3 for suppressing either the USB signal or the LSB signal relative to the carrier signal to the control circuit 27. The control device 30 is configured to output a control signal S4 for controlling a channel used for communication to the oscillator 24.

[0019] The sensor 40 is configured to detect various physical quantities. There is no particular limit to the physical quantities detected by the sensor 40. The sensor 40 may include, for example, one or both of a temperature sensor configured to detect the temperature around the wireless communication device 1 and an acceleration sensor configured to detect acceleration occurring in the wireless communication device 1. The sensor 40 may include other sensors.

[0020] The oscillator 24 is configured to generate an oscillation signal of a predetermined frequency. The oscillator 24 is configured to generate an oscillation signal S5 in accordance with a control signal S4. The oscillator 24 is configured to generate an oscillation signal S6 that is 90° out of phase with the oscillation signal S5.

[0021] The control circuit 27 is configured to control the transmission circuit 28. The control circuit 27 is configured to control the impedance value of the transmission circuit 28 based on the serial data S1, the serial data S2, and the control signal S3. The control circuit 27 is configured to change the impedance of the transmission circuit 28. Due to the change in impedance, the reflection coefficient of the output terminal on the antenna 10 side rotates in the complex plane. The control circuit 27 changes the impedance of the transmission circuit 28 to control the reflection coefficient of the output terminal to rotate in the complex plane. For example, the control circuit 27 is configured to control the impedance of the transmission circuit 28 so as to reduce the USB signal or LSB signal relative to the carrier signal in the reflected signal (hereinafter also referred to as the backscatter signal) and realize a single sideband.

[0022] A method in which the control circuit 27 controls the reflection coefficient of the output terminal of the transmission circuit 28 on the antenna 10 side to rotate on the complex plane of the polar chart will be described using the polar chart (polar coordinates) in Fig. 2. Fig. 2 is a diagram for explaining a method in which the control circuit 27 changes the impedance of the transmission circuit 28 and controls the reflection coefficient of the output terminal to rotate.

[0023] Figure 2 shows the change in reflection coefficient Γ due to the change in impedance on a polar chart. Impedance is calculated by the following formula (1). In formula (1), Z is impedance, R is resistance, j is an imaginary number, ω is angular frequency, L is inductance, and C is capacitance. Z = R + j(ωL-1 / ωC) (1)

[0024] The reflection coefficient Γ can be expressed by the following equation: Γ=(Z-Z0) / (Z+Z0) (2) Here, Z0 is the impedance of the antenna 10 or the BPF 11.

[0025] The control circuit 27 selects and controls the impedance Z to control the reflection coefficient Γ to rotate around a reference point. The reference point includes the origin, but is not limited to the origin, and includes any point. The closer the reference point is to the origin, the more likely it is that the transmission circuit will obtain a signal that is closer to the ideal. The more the transmission circuit is controlled to rotate in a circle around the reference point, the more likely it is that the signal will be closer to the ideal. In terms of a Smith chart, the lower semicircular area indicates capacitive properties, and the upper half indicates inductive properties. Changes on the real axis represent changes in resistance value.

[0026] The control circuit 27 can selectively control a plurality of impedances included in the transmission circuit 28. For example, the control circuit 27 is configured to control the impedance of the transmission circuit 28 in increments of 45°, i.e., 0°, 45°, 90°, 135°, 180°, −135°, −90°, and −45°. The control circuit 27 is configured to control the voltage reflection coefficient Γ by controlling the impedance. The control circuit 27 is configured to be able to control the impedance to rotate discretely by sequentially changing the impedance of the transmission circuit 28. The control circuit 27 rotates the reflection coefficient Γ discretely in response to the discrete rotation of the impedance.

[0027] The control circuit 27 is configured to be able to change the impedance in a counterclockwise direction by changing the impedance of the transmission circuit 28. The control circuit 27 is configured to be able to change the reflection coefficient Γ in a counterclockwise direction by rotating the impedance in a counterclockwise direction. When the control of the reflection coefficient is in a counterclockwise direction, the reflected signal for the RF (Radio Frequency) is only a USB (Upper Side Band) signal. When the control is performed so that the reflection coefficient is in a clockwise direction, only a LSB (Lower Side Band) signal is obtained. At that time, the frequency of the reflected signal is a frequency detuned by the rotation speed frequency from the RF signal frequency. Using FIG. 3A, FIG. 3B, and FIG. 3C, some examples of changes in the backscatter signal caused by changing the impedance and controlling the reflection coefficient will be described.

[0028] FIG. 3A is a diagram showing a frequency spectrum for explaining the state of a backscatter signal when the control circuit 27 controls only the resistance component of the impedance and changes the reflection coefficient Γ on the real axis of the polar chart (FIG. 2). The horizontal axis shows frequency, and the vertical axis shows the intensity of the RF signal and the reflected signal. FIG. 3A shows a carrier signal 51, a USB signal 52, and an LSB signal 53. When the resistance component is controlled, the reflection coefficient Γ is controlled to either 0° or 180° on the real axis. When the reflection coefficient Γ is controlled by changing the impedance only with the resistance component, as shown in FIG. 3A, for example, when switching from 0° to 180°, a right-handed signal component and a left-handed signal component are inherent. Due to the existence of signal components of two rotation directions, the USB signal 52 and the LSB signal 53 appear simultaneously, and it is not possible to selectively suppress only one of the signals. As a result, an SSB signal cannot be obtained by controlling only the resistance component.

[0029] FIG. 3B is a diagram showing a frequency spectrum for explaining the change in the backscatter signal when the control circuit 27 changes the inductance / capacitance of the impedance to control the locus of the reflection coefficient Γ to draw a circle. The horizontal axis indicates the frequency, and the vertical axis indicates the intensity of the RF signal and the reflected signal. Based on the formulas (1) and (2), the control circuit 27 can control the impedance to rotate counterclockwise by controlling the value of the inductance. At this time, the impedance rotates counterclockwise, for example, from 0° to 45°, 90°, and 135°. The control circuit 27 can further control the impedance to rotate counterclockwise by controlling the value of the capacitance. At this time, the impedance rotates counterclockwise, for example, from 180° to -135°, -90°, and -45°. As shown in FIG. 3B, the control circuit 27 can reflect the transmitted RF signal so as to suppress the LSB signal 53 by controlling the impedance to rotate counterclockwise. In other words, the control circuit 27 can obtain a backscattered signal converted into SSB in the USB signal 52 by controlling the impedance to rotate counterclockwise.

[0030] FIG. 3C is a diagram for explaining the change of the backscatter signal when the control circuit 27 changes the capacitance / inductance of the impedance and controls the locus of the reflection coefficient Γ to draw a circle. Based on the formulas (1) and (2), the control circuit 27 can control the impedance to rotate clockwise by controlling the capacitance value. At this time, the impedance rotates clockwise, for example, from 0° to −45°, −90°, and −135°. The control circuit 27 can further control the impedance to rotate clockwise by controlling the inductance value. At this time, the impedance rotates clockwise, for example, from 180° to 135°, 90°, and 45°. As shown in FIG. 3C, the control circuit 27 can reflect the transmitted RF signal so as to suppress the USB signal 52 by controlling the impedance to rotate clockwise. In other words, the control circuit 27 can obtain the backscatter signal that has been SSB-converted into the LSB signal 53 by controlling the clockwise rotation of the impedance.

[0031] The transmission circuit 28 is disposed at the front end of the wireless communication device 1. The transmission circuit 28 is a circuit configured to perform backscatter communication in which a transmitted radio wave is reflected as a backscatter signal. The transmission circuit 28 is configured to be connected to the antenna 10. The transmission circuit 28 includes a plurality of impedance circuits each having a different impedance. Each of the plurality of impedance circuits includes a switch element. The switch element is configured to switch the connection of the impedance circuit. The control circuit 27 is configured to switch the connection of the plurality of impedance circuits by controlling the plurality of switch elements. The control circuit 27 is configured to control the impedance of the transmission circuit 28 by controlling the plurality of switch elements.

[0032] [Impedance control method] A method for controlling the impedance of a transmission circuit according to an embodiment will be described with reference to Fig. 4. Fig. 4 is a diagram for explaining a method for controlling the impedance of a transmission circuit according to an embodiment. The control circuit 27 receives an input signal corresponding to transmission data to be transmitted to an external device. The control circuit 27 outputs a control signal for controlling the impedance of the transmission circuit 28 in response to the control signal.

[0033] Fig. 4 shows the configuration of a drive control circuit 29 corresponding to the output section of the control circuit 27 in Fig. 1, and a transmission circuit 28. The drive control circuit 29 is a drive control circuit for the transmission circuit 28 that switches impedance and controls the reflection coefficient Γ to rotate on a complex plane. The control circuit 27 (drive control circuit 29) and the transmission circuit 28 may also be referred to as a synthesis circuit.

[0034] As shown in FIG. 4, the drive control circuit 29 includes a reference power supply V, a resistive element R1, a resistive element R2, a resistive element R3, a resistive element R4, a resistive element R5, a resistive element R6, a resistive element R7, a resistive element R8, a resistive element R9, a resistive element R10, a resistive element R11, a resistive element R12, a resistive element R13, a resistive element R14, a resistive element R15, a resistive element R16, a resistive element R17, and a resistive element R18. The drive control circuit 29 also includes a comparator CM1, a comparator CM2, a comparator CM3, a comparator CM4, a comparator CM5, a comparator CM6, a comparator CM7, a comparator CM8, a comparator CM9, a comparator CM10, a comparator CM11, a comparator CM12, a comparator CM13, a comparator CM14, a comparator CM15, and a comparator CM16.

[0035] The transmission circuit 28 includes an inductor circuit 110 and a capacitor circuit 120. The inductor circuit 110 and the capacitor circuit 120 are a type of impedance circuit.

[0036] The resistor elements R1 to R9 are connected in series. The resistor element R1 is connected to a reference potential. The resistor element R9 is connected to a reference power supply V. The resistor elements R1 to R9 and the comparators CM1 to CM8 form a voltage divider circuit that outputs a control signal to the inductor circuit 110.

[0037] The node N1 is a node to which the input signal S11 is input. The node N2 is a node between the resistor element R1 and the resistor element R2. The node N3 is a node between the resistor element R2 and the resistor element R3. The node N4 is a node between the resistor element R3 and the resistor element R4. The node N5 is a node between the resistor element R4 and the resistor element R5. The node N6 is a node between the resistor element R5 and the resistor element R6. The node N7 is a node between the resistor element R6 and the resistor element R7. The node N8 is a node between the resistor element R7 and the resistor element R8. The node N9 is a node between the resistor element R8 and the resistor element R9. The nodes N10 to N16 are each a node electrically connected to the node N1. A reference signal according to the voltage value of the input signal S11 can be output from the node N1. From nodes N2 to N9, divided voltages according to the voltage value of the reference power supply V and the resistance values ​​of resistor elements R1 to R9 can be output as output signals.

[0038] A node N1 is electrically connected to one input terminal of the comparator CM1. A node N2 is electrically connected to the other input terminal of the comparator CM1. An output terminal of the comparator CM1 is electrically connected to the switch element SWL1 of the inductor circuit 110. The comparator CM1 is configured to compare an input signal S11 input from the node N1 with a first divided voltage as a control signal input from the node N2, and output a switch control signal according to the comparison result. For example, the comparator CM1 is configured to output a switch control signal that closes the switch element SWL1 if the first divided voltage is greater than the input signal S11. The comparator CM1 is configured to output a switch control signal that opens the switch element SWL1 if the first divided voltage is smaller than the input signal S11.

[0039] A node N10 is electrically connected to one input terminal of the comparator CM2. A node N3 is electrically connected to the other input terminal of the comparator CM2. An output terminal of the comparator CM2 is electrically connected to the switch element SWL2 of the inductor circuit 110. The comparator CM2 is configured to compare the input signal S11 input from the node N10 with the second divided voltage as a control signal input from the node N3, and output a switch control signal according to the comparison result. For example, the comparator CM2 is configured to output a switch control signal that closes the switch element SWL2 if the second divided voltage is greater than the input signal S11. The comparator CM2 is configured to output a switch control signal that opens the switch element SWL2 if the second divided voltage is smaller than the input signal S11.

[0040] A node N11 is electrically connected to one input terminal of the comparator CM3. A node N4 is electrically connected to the other input terminal of the comparator CM3. An output terminal of the comparator CM3 is electrically connected to the switch element SWL3 of the inductor circuit 110. The comparator CM3 is configured to compare the input signal S11 input from the node N11 with the third divided voltage as a control signal input from the node N4, and output a switch control signal according to the comparison result. For example, the comparator CM3 is configured to output a switch control signal that closes the switch element SWL3 if the third divided voltage is greater than the input signal S11. The comparator CM3 is configured to output a switch control signal that opens the switch element SWL3 if the third divided voltage is smaller than the input signal S11.

[0041] A node N12 is electrically connected to one input terminal of the comparator CM4. A node N5 is electrically connected to the other input terminal of the comparator CM4. An output terminal of the comparator CM4 is electrically connected to the switch element SWL4 of the inductor circuit 110. The comparator CM4 is configured to compare the input signal S11 input from the node N12 with the fourth divided voltage as a control signal input from the node N5, and output a switch control signal according to the comparison result. For example, the comparator CM4 is configured to output a switch control signal that closes the switch element SWL4 if the fourth divided voltage is greater than the input signal S11. The comparator CM4 is configured to output a switch control signal that opens the switch element SWL4 if the fourth divided voltage is smaller than the input signal S11.

[0042] A node N13 is electrically connected to one input terminal of the comparator CM5. A node N6 is electrically connected to the other input terminal of the comparator CM5. An output terminal of the comparator CM5 is electrically connected to the switch element SWL5 of the inductor circuit 110. The comparator CM5 is configured to compare the input signal S11 input from the node N13 with the fifth divided voltage as a control signal input from the node N6, and output a switch control signal according to the comparison result. For example, the comparator CM5 is configured to output a switch control signal that closes the switch element SWL5 if the fifth divided voltage is greater than the input signal S11. The comparator CM5 is configured to output a switch control signal that opens the switch element SWL5 if the fifth divided voltage is smaller than the input signal S11.

[0043] A node N14 is electrically connected to one input terminal of the comparator CM6. A node N7 is electrically connected to the other input terminal of the comparator CM6. An output terminal of the comparator CM6 is electrically connected to the switch element SWL6 of the inductor circuit 110. The comparator CM6 is configured to compare the input signal S11 input from the node N14 with the sixth divided voltage as a control signal input from the node N7, and output a switch control signal according to the comparison result. For example, the comparator CM6 is configured to output a switch control signal that closes the switch element SWL6 if the sixth divided voltage is greater than the input signal S11. The comparator CM6 is configured to output a switch control signal that opens the switch element SWL6 if the sixth divided voltage is smaller than the input signal S11.

[0044] A node N15 is electrically connected to one input terminal of the comparator CM7. A node N8 is electrically connected to the other input terminal of the comparator CM7. An output terminal of the comparator CM7 is electrically connected to the switch element SWL7 of the inductor circuit 110. The comparator CM7 is configured to compare the input signal S11 input from the node N15 with the seventh divided voltage as a control signal input from the node N8, and output a switch control signal according to the comparison result. For example, the comparator CM7 is configured to output a switch control signal that closes the switch element SWL7 if the seventh divided voltage is greater than the input signal S11. The comparator CM7 is configured to output a switch control signal that opens the switch element SWL7 if the seventh divided voltage is smaller than the input signal S11.

[0045] A node N16 is electrically connected to one input terminal of the comparator CM8. A node N9 is electrically connected to the other input terminal of the comparator CM8. An output terminal of the comparator CM8 is electrically connected to the switch element SWL8 of the inductor circuit 110. The comparator CM8 is configured to compare the input signal S11 input from the node N16 with the eighth divided voltage as a control signal input from the node N9, and output a switch control signal according to the comparison result. For example, the comparator CM8 is configured to output a switch control signal that closes the switch element SWL7 if the eighth divided voltage is greater than the input signal S11. The comparator CM8 is configured to output a switch control signal that opens the switch element SWL8 if the eighth divided voltage is smaller than the input signal S11.

[0046] The resistor elements R10 to R18 are connected in series. The resistor elements R1 to R9 and the resistor elements R10 to R18 are connected in parallel. The resistor element R10 is connected to a reference potential. The resistor element R18 is connected to a reference power supply V via a node N17. The resistor elements R10 to R18 and the comparators CM9 to CM16 form a voltage divider circuit that outputs a control signal to the capacitor circuit 120.

[0047] The node N18 is a node between the resistor element R10 and the resistor element R11. The node N19 is a node between the resistor element R11 and the resistor element R12. The node N20 is a node between the resistor element R12 and the resistor element R13. The node N21 is a node between the resistor element R13 and the resistor element R14. The node N22 is a node between the resistor element R14 and the resistor element R15. The node N23 is a node between the resistor element R15 and the resistor element R16. The node N24 is a node between the resistor element R16 and the resistor element R17. The node N25 is a node between the resistor element R17 and the resistor element R18. Nodes N26 to N32 are each electrically connected to node N1. A divided voltage according to the voltage value of the reference power supply V and the resistance values ​​of resistor elements R10 to R18 can be output as an output voltage from nodes N26 to N32.

[0048] A node N1 is electrically connected to one input terminal of the comparator CM9. A node N18 is electrically connected to the other input terminal of the comparator CM9. An output terminal of the comparator CM9 is electrically connected to the switch element SWC1 of the capacitor circuit 120. The comparator CM9 is configured to compare the input signal S11 input from the node N1 with the ninth divided voltage as a control signal input from the node N18, and output a switch control signal according to the comparison result. For example, the comparator CM9 is configured to output a switch control signal that closes the switch element SWC1 if the ninth divided voltage is greater than the input signal S11. The comparator CM9 is configured to output a switch control signal that opens the switch element SWC1 if the ninth divided voltage is smaller than the input signal S11.

[0049] A node N26 is electrically connected to one input terminal of the comparator CM10. A node N19 is electrically connected to the other input terminal of the comparator CM10. An output terminal of the comparator CM10 is electrically connected to the switch element SWC2 of the capacitor circuit 120. The comparator CM10 is configured to compare the input signal S11 input from the node N26 with the tenth divided voltage as a control signal input from the node N19, and output a switch control signal according to the comparison result. For example, the comparator CM10 is configured to output a switch control signal that closes the switch element SWC2 if the tenth divided voltage is greater than the input signal S11. The comparator CM10 is configured to output a switch control signal that opens the switch element SWC2 if the tenth divided voltage is smaller than the input signal S11.

[0050] A node N27 is electrically connected to one input terminal of the comparator CM11. A node N20 is electrically connected to the other input terminal of the comparator CM11. An output terminal of the comparator CM11 is electrically connected to the switch element SWC3 of the capacitor circuit 120. The comparator CM11 is configured to compare the input signal S11 input from the node N27 with the eleventh divided voltage as a control signal input from the node N20, and output a switch control signal according to the comparison result. For example, the comparator CM11 is configured to output a switch control signal that closes the switch element SWC3 if the eleventh divided voltage is greater than the input signal S11. The comparator CM11 is configured to output a switch control signal that opens the switch element SWC3 if the eleventh divided voltage is smaller than the input signal S11.

[0051] A node N28 is electrically connected to one input terminal of the comparator CM12. A node N21 is electrically connected to the other input terminal of the comparator CM12. An output terminal of the comparator CM12 is electrically connected to the switch element SWC4 of the capacitor circuit 120. The comparator CM12 is configured to compare the input signal S11 input from the node N28 with the twelfth divided voltage as a control signal input from the node N21, and output a switch control signal according to the comparison result. For example, the comparator CM12 is configured to output a switch control signal that closes the switch element SWC4 if the twelfth divided voltage is greater than the input signal S11. The comparator CM12 is configured to output a switch control signal that opens the switch element SWC4 if the twelfth divided voltage is smaller than the input signal S11.

[0052] A node N29 is electrically connected to one input terminal of the comparator CM13. A node N22 is electrically connected to the other input terminal of the comparator CM13. An output terminal of the comparator CM13 is electrically connected to the switch element SWC5 of the capacitor circuit 120. The comparator CM13 is configured to compare the input signal S11 input from the node N29 with the thirteenth divided voltage as a control signal input from the node N22, and output a switch control signal according to the comparison result. For example, the comparator CM13 is configured to output a switch control signal that closes the switch element SWC5 if the thirteenth divided voltage is greater than the input signal S11. The comparator CM13 is configured to output a switch control signal that opens the switch element SWC5 if the thirteenth divided voltage is smaller than the input signal S11.

[0053] A node N30 is electrically connected to one input terminal of the comparator CM14. A node N23 is electrically connected to the other input terminal of the comparator CM14. An output terminal of the comparator CM14 is electrically connected to the switch element SWC6 of the capacitor circuit 120. The comparator CM14 is configured to compare the input signal S11 input from the node N30 with the 14th divided voltage as a control signal input from the node N23, and output a switch control signal according to the comparison result. For example, the comparator CM14 is configured to output a switch control signal that closes the switch element SWC6 if the 14th divided voltage is greater than the input signal S11. The comparator CM14 is configured to output a switch control signal that opens the switch element SWC6 if the 14th divided voltage is smaller than the input signal S11.

[0054] A node N31 is electrically connected to one input terminal of the comparator CM15. A node N24 is electrically connected to the other input terminal of the comparator CM15. An output terminal of the comparator CM15 is electrically connected to the switch element SWC7 of the capacitor circuit 120. The comparator CM15 is configured to compare the input signal S11 input from the node N31 with the 15th divided voltage as a control signal input from the node N24, and output a switch control signal according to the comparison result. For example, the comparator CM15 is configured to output a switch control signal that closes the switch element SWC7 if the 15th divided voltage is greater than the input signal S11. The comparator CM15 is configured to output a switch control signal that opens the switch element SWC7 if the 15th divided voltage is smaller than the input signal S11.

[0055] A node N32 is electrically connected to one input terminal of the comparator CM16. A node N25 is electrically connected to the other input terminal of the comparator CM16. An output terminal of the comparator CM16 is electrically connected to the switch element SWC8 of the capacitor circuit 120. The comparator CM16 is configured to compare the input signal S11 input from the node N32 with the 16th divided voltage as a control signal input from the node N25, and output a switch control signal according to the comparison result. For example, the comparator CM16 is configured to output a switch control signal that closes the switch element SWC8 if the 16th divided voltage is greater than the input signal S11. The comparator CM16 is configured to output a switch control signal that opens the switch element SWC8 if the 16th divided voltage is smaller than the input signal S11.

[0056] The following describes the configuration of the inductor circuit 110. The inductor circuit 110 includes a switch element SWL1, a switch element SWL2, a switch element SWL3, a switch element SWL4, a switch element SWL5, a switch element SWL6, a switch element SWL7, a switch element SWL8, an inductor L1, an inductor L2, an inductor L3, an inductor L4, an inductor L5, an inductor L6, an inductor L7, and a high-resistance element RL.

[0057] An input terminal of the switch element SWL1 is electrically connected to an output terminal of the comparator CM1. One end of the output terminal of the switch element SWL1 is electrically connected to a reference potential via one end of the inductor L1 and a high resistance element RL. The other end of the output terminal of the switch element SWL1 is connected to the reference potential. The other end of the inductor L1 is electrically connected to the selection circuit 130 via inductors L2 to L7. The switch element SWL1 is configured to electrically connect the inductor L1 to the selection circuit 130 when in a closed state. The switch element SWL1 is configured to electrically separate the inductor L1 from the selection circuit 130 when in an open state. When the switch element SWL1 is in a closed state, the impedance of the inductor circuit 110 becomes the sum of the inductances of the inductors L1 to L7.

[0058] An input terminal of the switch element SWL2 is electrically connected to an output terminal of the comparator CM2. One end of the output terminal of the switch element SWL2 is electrically connected to the other end of the inductor L1 and one end of the inductor L2. The other end of the output terminal of the switch element SWL2 is connected to a reference potential. The other end of the inductor L2 is electrically connected to the selection circuit 130 via inductors L3 to L7. The switch element SWL2 is configured to electrically connect the inductor L2 and the selection circuit 130 when in a closed state. The switch element SWL2 is configured to electrically separate the inductor L2 and the selection circuit 130 when in an open state. That is, when the switch element SWL2 is in a closed state, the inductance of the inductor L2 is subtracted from the impedance of the inductor circuit 110.

[0059] An input terminal of the switch element SWL3 is electrically connected to an output terminal of the comparator CM3. One end of the output terminal of the switch element SWL3 is electrically connected to the other end of the inductor L2 and one end of the inductor L3. The other end of the output terminal of the switch element SWL3 is connected to a reference potential. The other end of the inductor L3 is electrically connected to the selection circuit 130 via inductors L4 to L7. The switch element SWL3 is configured to electrically connect the inductor L3 and the selection circuit 130 when in a closed state. The switch element SWL3 is configured to electrically separate the inductor L3 and the selection circuit 130 when in an open state. That is, when the switch element SWL3 is in a closed state, the inductance of the inductor L3 is subtracted from the impedance of the inductor circuit 110.

[0060] An input terminal of the switch element SWL4 is electrically connected to an output terminal of the comparator CM4. One end of the output terminal of the switch element SWL4 is connected to the other end of the inductor L3 and one end of the inductor L4. The other end of the output terminal of the switch element SWL4 is connected to the reference potential. The other end of the inductor L4 is electrically connected to the selection circuit 130 via inductors L5 to L7. The switch element SWL4 is configured to electrically connect the inductor L4 and the selection circuit 130 when in a closed state. The switch element SWL4 is configured to electrically separate the inductor L4 and the selection circuit 130 when in an open state. That is, when the switch element SWL4 is in a closed state, the inductance of the inductor L4 is subtracted from the impedance of the inductor circuit 110.

[0061] The input terminal of the switch element SWL5 is electrically connected to the output terminal of the comparator CM5. One end of the output terminal of the switch element SWL5 is electrically connected to the other end of the inductor L4 and one end of the inductor L5. The other end of the output terminal of the switch element SWL5 is connected to the reference potential. The other end of the inductor L5 is electrically connected to the selection circuit 130 via the inductors L6 and L7. The switch element SWL5 is configured to electrically connect the inductor L5 and the selection circuit 130 when in a closed state. The switch element SWL5 is configured to electrically separate the inductor L5 and the selection circuit 130 when in an open state. That is, when the switch element SWL5 is in a closed state, the inductance of the inductor L5 is subtracted from the impedance of the inductor circuit 110.

[0062] An input terminal of the switch element SWL6 is electrically connected to an output terminal of the comparator CM6. One end of the output terminal of the switch element SWL6 is electrically connected to the other end of the inductor L5 and one end of the inductor L6. The other end of the output terminal of the switch element SWL6 is connected to a reference potential. The other end of the inductor L6 is electrically connected to the selection circuit 130 via an inductor L7. The switch element SWL6 is configured to electrically connect the inductor L6 and the selection circuit 130 when in a closed state. The switch element SWL6 is configured to electrically separate the inductor L6 and the selection circuit 130 when in an open state. That is, when the switch element SW6 is in a closed state, the inductance of the inductor L6 is subtracted from the impedance of the inductor circuit 110.

[0063] An input terminal of the switch element SWL7 is electrically connected to an output terminal of the comparator CM7. One end of the output terminal of the switch element SWL7 is connected to the other end of the inductor L6 and one end of the inductor L7. The other end of the output terminal of the switch element SWL7 is connected to a reference potential. The other end of the inductor L7 is electrically connected to the selection circuit 130. The switch element SWL7 is configured to electrically connect the inductor L7 and the selection circuit 130 when in a closed state. The switch element SWL7 is configured to electrically separate the inductor L7 and the selection circuit 130 when in an open state. That is, when the switch element SWL7 is in a closed state, the inductance of the inductor L7 is subtracted from the impedance of the inductor circuit 110.

[0064] An input terminal of the switch element SWL8 is electrically connected to an output terminal of the comparator CM8. One end of the output terminal of the switch element SWL8 is electrically connected to the other end of the inductor L7 and the selection circuit 130. The other end of the output terminal of the switch element SWL8 is connected to a reference potential. The switch element SWL8 is configured to be electrically connected to the selection circuit 130 when in a closed state. The switch element SWL2 is configured to be electrically separated from the selection circuit 130 when in an open state.

[0065] In the inductor circuit 110, the inductors L1 to L7 are configured to be connected in series. That is, when each switch element is in a closed state, the sum of the inductors connected in series changes. As the input signal S11 changes from 0V to a high voltage, the switch elements SWL1 to SWL8 are closed in this order. Since the inductor circuit 110 includes a high resistance element RL that is a ground resistor with a relatively large resistance value (for example, 10 kilohms), the inductors subsequent to the switch element that is in a closed state can be ignored. That is, when the switch element SWL8 is in a closed state, the inductances of the inductors L1 to L7 can be ignored. The inductor circuit 110 outputs an impedance state according to the open / close state of each switch element to the selection circuit 130 via the connection S12.

[0066] The configuration of the capacitor circuit 120 will be described. The capacitor circuit 120 includes a switch element SWC1, a switch element SWC2, a switch element SWC3, a switch element SWC4, a switch element SWC5, a switch element SWC6, a switch element SWC7, a switch element SWC8, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, and a high resistance element RC. In the capacitor circuit 120, nodes N33 to N40 and the selection circuit 130 are electrically connected to each other.

[0067] An input terminal of the switch element SWC1 is electrically connected to an output terminal of the comparator CM9. One end of the output terminal of the switch element SWC1 is electrically connected to a node N33. The node N33 is electrically connected to a reference potential via a high resistance element RC and to the selection circuit 130 via nodes N34 to N40. The other end of the output terminal of the switch element SWC1 is connected to the reference potential via a capacitor C1. The switch element SWC1 is configured to electrically connect the capacitor C1 and the selection circuit 130 when in a closed state. The switch element SWC1 is configured to electrically separate the capacitor C1 and the selection circuit 130 when in an open state. That is, when the switch element SWC1 is in a closed state, the capacitance of the capacitor C1 is added to the impedance of the capacitor circuit 120.

[0068] An input terminal of the switch element SWC2 is electrically connected to an output terminal of the comparator CM10. One end of the output terminal of the switch element SWC2 is electrically connected to a node N34. The node N34 is electrically connected to the selection circuit 130 via nodes N35 to N40. The other end of the output terminal of the switch element SWC2 is connected to a reference potential via a capacitor C2. The switch element SWC2 is configured to electrically connect the capacitor C2 and the selection circuit 130 when in a closed state. The switch element SWC2 is configured to electrically separate the capacitor C2 and the selection circuit 130 when in an open state. That is, when the switch element SWC2 is in a closed state, the capacitance of the capacitor C2 is added to the impedance of the capacitor circuit 120.

[0069] An input terminal of the switch element SWC3 is electrically connected to an output terminal of the comparator CM11. One end of the output terminal of the switch element SWC3 is electrically connected to a node N35. The node N35 is electrically connected to the selection circuit 130 via nodes N36 to N40. The other end of the output terminal of the switch element SWC3 is connected to a reference potential via a capacitor C3. The switch element SWC3 is configured to electrically connect the capacitor C3 and the selection circuit 130 when in a closed state. The switch element SWC3 is configured to electrically separate the capacitor C3 and the selection circuit 130 when in an open state. That is, when the switch element SWC3 is in a closed state, the capacitance of the capacitor C3 is added to the impedance of the capacitor circuit 120.

[0070] An input terminal of the switch element SWC4 is electrically connected to an output terminal of the comparator CM12. One end of the output terminal of the switch element SWC4 is electrically connected to a node N36. The node N36 is electrically connected to the selection circuit 130 via nodes N37 to N40. The other end of the output terminal of the switch element SWC4 is connected to a reference potential via a capacitor C4. The switch element SWC4 is configured to electrically connect the capacitor C4 and the selection circuit 130 when in a closed state. The switch element SWC4 is configured to electrically separate the capacitor C4 and the selection circuit 130 when in an open state. That is, when the switch element SWC4 is in a closed state, the capacitance of the capacitor C4 is added to the impedance of the capacitor circuit 120.

[0071] An input terminal of the switch element SWC5 is electrically connected to an output terminal of the comparator CM13. One end of the output terminal of the switch element SWC5 is electrically connected to a node N37. The node N37 is electrically connected to the selection circuit 130 via nodes N38 to N40. The other end of the output terminal of the switch element SWC5 is connected to a reference potential via a capacitor C5. The switch element SWC5 is configured to electrically connect the capacitor C5 and the selection circuit 130 when in a closed state. The switch element SWC5 is configured to electrically separate the capacitor C5 and the selection circuit 130 when in an open state. That is, when the switch element SWC5 is in a closed state, the capacitance of the capacitor C5 is added to the impedance of the capacitor circuit 120.

[0072] An input terminal of the switch element SWC6 is electrically connected to an output terminal of the comparator CM14. One end of the output terminal of the switch element SWC6 is electrically connected to a node N38. The node N38 is electrically connected to the selection circuit 130 via nodes N39 and N40. The other end of the output terminal of the switch element SWC6 is connected to a reference potential via a capacitor C6. The switch element SWC6 is configured to electrically connect the capacitor C6 and the selection circuit 130 when in a closed state. The switch element SWC6 is configured to electrically separate the capacitor C6 and the selection circuit 130 when in an open state. That is, when the switch element SWC6 is in a closed state, the capacitance of the capacitor C6 is added to the impedance of the capacitor circuit 120.

[0073] An input terminal of the switch element SWC7 is electrically connected to an output terminal of the comparator CM15. One end of the output terminal of the switch element SWC7 is electrically connected to a node N39. The node N39 is electrically connected to the selection circuit 130 via a node N40. The other end of the output terminal of the switch element SWC7 is connected to a reference potential via a capacitor C7. The switch element SWC7 is configured to electrically connect the capacitor C7 and the selection circuit 130 when in a closed state. The switch element SWC7 is configured to electrically separate the capacitor C7 and the selection circuit 130 when in an open state. That is, when the switch element SWC7 is in a closed state, the capacitance of the capacitor C7 is added to the impedance of the capacitor circuit 120.

[0074] An input terminal of the switch element SWC8 is electrically connected to an output terminal of the comparator CM16. One end of the output terminal of the switch element SWC8 is electrically connected to a node N40. The node N40 is electrically connected to the selection circuit 130. The other end of the output terminal of the switch element SWC2 is connected to a reference potential. The switch element SWC8 is configured to be electrically connected to the selection circuit 130 when in a closed state. The switch element SWC2 is configured to be electrically separated from the selection circuit 130 when in an open state.

[0075] In the capacitor circuit 120, the switch elements SWC1 to SWC7 are electrically connected to the capacitors C1 to C7, respectively. Therefore, when each switch element is in a closed state, the sum of the capacitances changes. As the input signal S11 changes from 0V to a high voltage, the switch elements SWC1 to SWC8 are closed in this order. Since the capacitor circuit 120 includes a high resistance element RC that is a ground resistor with a relatively large resistance value (for example, 10 kilohms), each capacitance can be ignored when all the switch elements are in a closed state. In other words, when the switch element SWC8 is in a closed state, the capacitances of the capacitors C1 to C7 can be ignored. The capacitor circuit 120 outputs an impedance state according to the open / closed state of each switch element to the selection circuit 130 via the connection S13.

[0076] In the transmission circuit 28, the switching elements SWL1 to SWL8 of the inductor circuit 110 or the switching elements SWC1 to SWC8 of the capacitor circuit 120 can be controlled to open or close in accordance with the output results of the comparators connected to each of them.

[0077] The operation of the transmission circuit according to the embodiment will be described with reference to Fig. 5. Fig. 5 is a diagram for explaining the operation of the transmission circuit according to the embodiment.

[0078] Fig. 5 shows the position in polar coordinates (polar chart) of the reflection coefficient Γ due to the impedance of the transmission circuit 28 according to the embodiment. Points P1 to P16 on the polar coordinates are shown in Fig. 5. The drive control circuit 29 is configured to position the impedance of the transmission circuit 28 at any of the phases of points P1 to P16 by controlling the switch elements SWL1 to SWL8 and the switch elements SWC1 to SWC8.

[0079] In FIG. 5, the phase of point P1 is 0°. The phase of point P2 is 22.5°. The phase of point P3 is 45°. The phase of point P4 is 67.5°. The phase of point P5 is 90°. The phase of point P6 is 112.5°. The phase of point P7 is 135°. The phase of point P8 is 157.5°. The phase of point P9 is 180°. The phase of point P10 is 202.5°. The phase of point P11 is 225°. The phase of point P12 is 247.5°. The phase of point P13 is 270°. The phase of point P14 is 292.5°. The phase of point P15 is 315°. The phase of point P16 is 337.5°.

[0080] Point P1 indicates the impedance when all of switch elements SWL1 to SWL8 and switch elements SWC1 to SWC8 are in the open state. In this case, the impedance of transmission circuit 28 is, in principle, infinite. Point P9 indicates the impedance when all of switch elements SWL1 to SWL8 and switch elements SWC1 to SWC8 are in the closed state. In this case, the impedance of transmission circuit 28 is, in principle, zero.

[0081] The operation of the inductor circuit 110 will be described. When the voltage of the input signal S11 rises, that is, when the voltage value of the input signal S11 changes from 0V (reference potential: GND) to a high voltage value, the switch elements SWL1 to SWL8 are switched from the open state to the closed state in this order. In this case, the impedance of the inductor circuit 110 changes counterclockwise in the upper semicircular area. For example, when the switch element SWL1 is closed, the impedance of the inductor circuit 110 changes to the phase of point P2. The impedance of the inductor circuit 110 at this time is the sum of the inductances of inductors L1 to L7. For example, when the switch element SWL2 is closed, the impedance of the inductor circuit 110 changes to the phase of point P3. The impedance of the inductor circuit 110 at this time is the sum of the inductances of inductors L1 to L7 minus the inductance of inductor L2. For example, when switch elements SWL1 to SWL7 are closed, the impedance of inductor circuit 110 changes to the phase of point P8. The impedance of inductor circuit 110 at this time is the sum of inductors L1 to L7 minus the sum of inductors L2 to L7, and is therefore the inductance value of inductor L1.

[0082] On the other hand, when the voltage of the input signal S11 falls, that is, when the voltage of the input signal S11 changes from a high voltage value to 0V (reference potential: GND), the impedance of the inductor circuit 110 changes clockwise in the upper semicircular region. That is, the inductor circuit 110 performs an operation opposite to that when the voltage value changes from 0V (reference potential: GND) to a high voltage value.

[0083] The operation of the capacitor circuit 120 will be described. When the voltage of the input signal S11 rises, that is, when the voltage value of the input signal S11 changes from 0V to a high voltage value, the switch elements SWC1 to SWC8 are switched from the open state to the closed state in this order. In this case, the impedance of the capacitor circuit 120 changes clockwise in the area of ​​the lower semicircle. For example, when the switch element SWC1 is closed, the impedance of the capacitor circuit 120 changes to the phase of the point P16. The impedance of the capacitor circuit 120 at this time is the capacitance value of the capacitor C1. For example, when the switch element SWC2 is closed, the impedance of the capacitor circuit 120 changes to the phase of the point P15. The impedance of the capacitor circuit 120 at this time is the sum of the capacitances of the capacitors C1 and C2. For example, when the switch elements SWC1 to SWC7 are closed, the impedance of the capacitor circuit 120 changes to the phase of the point P10. At this time, the impedance of the capacitor circuit 120 is the sum of the capacitances of the capacitors C1 to C7.

[0084] On the other hand, the impedance of the capacitor circuit 120 changes counterclockwise in the lower semicircular region when the voltage of the input signal S11 falls, that is, when the voltage of the input signal S11 changes from a high voltage value to 0 V. That is, the impedance of the capacitor circuit 120 performs an operation opposite to that when the voltage value changes from 0 V to a high voltage value.

[0085] 4 again, the operation of the selection circuit 130 will be described. At the rising edge of the input signal S11, the selection circuit 130 selects the connection S12 with the inductor circuit 110 and controls the impedance counterclockwise, thereby suppressing the LSB signal and obtaining the SSB signal of the USB. At the falling edge of the input signal S11, the selection circuit 130 selects the connection S13 with the capacitor circuit 120 and controls the impedance counterclockwise, thereby suppressing the LSB signal and obtaining the SSB signal of the USB.

[0086] Furthermore, when the input signal S11 falls, the selection circuit 130 selects the connection S12 from the inductor circuit 110 and controls the impedance clockwise, thereby suppressing the USB signal and obtaining an SSB signal of the LSB. When the input signal S11 rises, the selection circuit 130 selects the connection S13 from the capacitor circuit and controls the impedance clockwise, thereby suppressing the USB signal and obtaining an SSB signal of the LSB.

[0087] The selection circuit 130 receives a selection signal S14 from a control device such as an external computer. The selection signal S14 is a signal for selecting whether to obtain a USB SSB signal or an LSB SSB signal. The selection circuit 130 selects either the connection S12 or the connection S13 based on the input signal S11 and the selection signal S14.

[0088] [An example of backscattering operation] Next, an example of the backscatter operation will be described.

[0089] 6A and 6B are diagrams showing an example of an input signal S11 according to the embodiment. FIG. 6A shows a trapezoidal wave SL1 as an example of the input signal S11. FIG. 6B shows a triangular wave SL1A as an example of the input signal S11. In this embodiment, the input signal S11 having a waveform as shown in FIG. 6A or FIG. 6B is input, and the impedance is changed and the reflection coefficient is rotated by utilizing the slope of the voltage at the time of the voltage rising or falling. An example of a backscattering operation using the trapezoidal wave SL1 shown in FIG. 6A will be described below.

[0090] An example of a backscattering signal will be described with reference to Fig. 7 and Fig. 8. Fig. 7 and Fig. 8 are diagrams showing an example of a spectrum waveform of a backscattering signal according to an embodiment. In Fig. 7 and Fig. 8, the horizontal axis indicates time (seconds) and the vertical axis indicates signal level (V).

[0091] As shown in FIG. 7, the spectrum waveform W1 includes a carrier signal RF1, an LSB signal LS1, and a USB signal US1. The spectrum waveform W1 shows an example in which the USB signal US1 is obtained by selecting the connection S12 using the slope at the rising edge of the trapezoidal wave SL1 or by selecting the connection S13 using the slope at the falling edge of the trapezoidal wave SL1. The frequency of the carrier signal RF1 is 1.0 GHz. The frequency of the LSB signal LS1 is .99 GHz. The frequency of the USB signal US1 is 1.01 GHz. As shown in FIG. 7, the LSB signal LS1 is suppressed compared to the USB signal US1. That is, in the spectrum waveform W1 shown in FIG. 7, the SSB of the USB signal US1 is realized.

[0092] As shown in FIG. 8, the spectrum waveform W2 includes a carrier signal RF2, an LSB signal LS2, and a USB signal US2. The spectrum waveform W2 shows an example in which the LSB signal LS2 is obtained by selecting the connection S12 using the slope at the falling edge of the trapezoidal wave SL1 or by selecting the connection S13 using the slope at the rising edge of the trapezoidal wave SL1. The frequency of the carrier signal RF1 is 1.0 GHz. The frequency of the LSB signal LS1 is .99 GHz. The frequency of the USB signal US1 is 1.01 GHz. As shown in FIG. 8, the USB signal US2 is suppressed compared to the LSB signal LS2. That is, in the spectrum waveform W2 shown in FIG. 8, the SSB of the LSB signal LS2 is realized.

[0093] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the contents of these embodiments. The above-mentioned components include those that a person skilled in the art can easily imagine, those that are substantially the same, and those that are within the so-called equivalent range. Furthermore, the above-mentioned components can be appropriately combined. Furthermore, various omissions, substitutions, or modifications of the components can be made without departing from the gist of the above-mentioned embodiments. [Explanation of symbols]

[0094] 1. Wireless communication devices 10 Antennas 11 BPF 20 RFBS Devices 21 High Frequency Switch 22 Amplifier 23 Demodulation section 24 Oscillator 25,26 LPF 27 Control circuit 28 Transmission Circuit 30 Control device 40 Sensors 110 Inductor Circuit 120 Capacitor Circuit SWL1 to SWL8, SWC1 to SWC8 Switch elements CM1~CM15 Comparators

Claims

1. A synthesis circuit including a transmission circuit configured to be connected to an antenna and a control circuit configured to control an impedance of the transmission circuit, The transmission circuit includes: A plurality of impedance circuits each having a different impedance; a plurality of first switch elements, any one of which is connected to each of the plurality of impedance circuits; The control circuit includes a plurality of comparators connected to the first switch elements, a voltage dividing circuit including a plurality of resistor elements configured to divide an input reference voltage and output a divided power to each of the plurality of comparators; The voltage divider circuit is configured to be controllable by changing the impedance of the transmission circuit so that a reflection coefficient with the antenna rotates around a reference point on a complex plane. Synthetic circuit.

2. A composite circuit including a transmission circuit configured to be connected to an antenna and a control circuit configured to control an impedance of the transmission circuit, The transmission circuit includes: A plurality of impedance circuits each having a different impedance; a plurality of first switch elements, any one of which is connected to each of the plurality of impedance circuits; The control circuit includes a plurality of comparators connected to the first switch elements, a voltage dividing circuit including a plurality of resistor elements configured to divide an input reference voltage and output a divided power to each of the plurality of comparators; Each of the plurality of comparators is configured to control the open / closed states of the plurality of first switch elements based on a comparison result between a divided voltage input from the voltage divider circuit and a predetermined input signal input from an external source. Synthetic circuit.

3. A composite circuit including a transmission circuit configured to be connected to an antenna and a control circuit configured to control an impedance of the transmission circuit, The transmission circuit includes: A plurality of impedance circuits each having a different impedance; a plurality of first switch elements, any one of which is connected to each of the plurality of impedance circuits; The control circuit includes a plurality of comparators connected to the first switch elements, a voltage dividing circuit including a plurality of resistor elements configured to divide an input reference voltage and output a divided power to each of the plurality of comparators; The plurality of impedance circuits include a plurality of inductor circuits configured to adjust an inductance among a reactance component of an impedance. Synthetic circuit.

4. A composite circuit including a transmission circuit configured to be connected to an antenna and a control circuit configured to control an impedance of the transmission circuit, The transmission circuit includes: A plurality of impedance circuits each having a different impedance; a plurality of first switch elements, any one of which is connected to each of the plurality of impedance circuits; The control circuit includes a plurality of comparators connected to the first switch elements, a voltage dividing circuit including a plurality of resistor elements configured to divide an input reference voltage and output a divided power to each of the plurality of comparators; The plurality of impedance circuits include a plurality of capacitor circuits configured to adjust capacitance among reactance components of impedance. Synthetic circuit.

5. 5. The synthesis circuit according to claim 2, a combining circuit, the voltage dividing circuit being configured to be controllable by changing the impedance of the transmission circuit so that a reflection coefficient with the antenna rotates around a reference point on a complex plane.

6. 6. The synthesis circuit according to claim 1, The reference point is an origin,

7. 6. The synthesis circuit according to claim 1, A combining circuit, wherein the voltage divider circuit is configured to be controllable so that the reflection coefficient rotates around a reference point in a complex plane.

8. 8. The synthesis circuit according to claim 1, The voltage divider circuit is configured to output divided voltages having different voltage values ​​to each of the plurality of comparators.

9. 9. A synthesis circuit according to claim 1, comprising: The voltage divider circuit outputs a divided voltage to each of the plurality of comparators so as to bring at least one first switch element out of the plurality of first switch elements into a closed state.

10. 4. The synthesis circuit according to claim 3, The multiple inductor circuits each have a different impedance.

11. 11. The synthesis circuit according to claim 3, A composite circuit, wherein at least one of the plurality of inductor circuits includes a plurality of inductor elements.

12. 12. The synthesis circuit according to claim 3, 10 or 11, A composite circuit, wherein at least one of the plurality of inductor circuits includes a resistive element.

13. 12. The synthesis circuit according to claim 3, 10 or 11, A composite circuit, wherein at least one of the plurality of inductor circuits includes a capacitor element.

14. 5. The synthesis circuit according to claim 4, A composite circuit, in which the plurality of capacitor circuits each have a different impedance.

15. 15. The synthesis circuit according to claim 4, A composite circuit, wherein at least one of the plurality of capacitor circuits includes a plurality of capacitor elements.

16. 16. The synthesis circuit according to claim 4, 14 or 15, A composite circuit, wherein at least one of the plurality of capacitor circuits includes a resistive element.

17. 16. The synthesis circuit according to claim 4, 14 or 15, A composite circuit, wherein at least one of the plurality of capacitor circuits includes an inductor element.

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