System and method for measuring small frequency differences - Patents.com

Abstract

The present disclosure is directed to a system and method for quickly and accurately measuring small frequency differences between two signals. In a particular example, the offset between two clock signals on a satellite can be precisely determined in time allowing for rapid clock synchronization useful in position, navigation, and tracking (PNT) and satellite communications applications. The system and method may also be implemented in a constellation of cooperating satellites or other space-borne and high altitude assets, where multiple such assets are precisely time synchronized and more accurate ensemble average calculations are enabled using a two-way time transfer (TWTT) protocol. A particular application disclosed is the measurement and correction of very small frequency differences between atomic and tunable clock signals.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of priority to U.S. Provisional Application No. 63 / 142,932, filed January 28, 2021, which is incorporated by reference in its entirety.

[0002] (Technical field) The technology described herein relates to systems and methods for measuring the frequency difference between two signals, such as two clock signals on a satellite. In particular, the disclosed systems and methods can be used to determine very small frequency differences between atomic and tunable clock signals, properly synchronize the clocks locally, and enable more accurate ensemble clock averaging in a constellation of satellites. [Background technology]

[0003] As satellite processing systems increase in speed and complexity, and as cooperating constellations of satellites continue to grow in size and number, the need for precise clock signals at local and constellation levels becomes increasingly important. Many functions on satellites and constellations of satellites depend on knowledge of precise time. For example, position, navigation, and timing (PNT) applications require precise synchronization of multiple clocks, both locally on each satellite and as contributions to an ensemble average clock for a group of satellites. Another example arises in sensing applications, especially those involving two (or more) satellites, where knowledge of precise time of arrival (ToA) directly impacts performance. Consider a conceptual but realistic scenario in which two satellites, 5,000 km apart in the same plane at an altitude of 1,000 km, are used to detect the location of a target. For this example, the target is located at sea level to simplify the problem. In the two-satellite case, there is a 10 nanosecond (10 nanosecond) gap between the clocks on the two satellites. E-9If there was a relative clock error of 0.01 nanoseconds, a displacement error of approximately 2.3 meters would result. On the other hand, if the two clocks had exactly the same time (i.e., the relative clock error between the two satellites was 0 nanoseconds), but were offset by 1,000 nanoseconds relative to absolute time (such as that defined by a ground-based master clock reference), the resulting displacement error would be approximately 7 mm (7 E-3 The effect of very small relative time errors between satellites would be over 30,000 times greater than the absolute error of the two satellites relative to the master clock, highlighting the importance of precise time synchronization locally and between satellites. Furthermore, it is noted that the use of GNSS as a method for synchronizing satellites in a constellation is vulnerable to spoofing and other means of degrading their accuracy, and therefore, for certain applications (e.g., national security, military, and other implementations), GNSS is not considered to be a reliable time source. The present disclosure, described in detail below, is directed to ensuring precise time synchronization in space-based and high altitude systems, but also has application in terrestrial systems that rely on highly accurate synchronization between multiple components.

[0004] The information contained in this Background section of the specification, including any references cited herein and any description or discussion thereof, is included for technical reference purposes and should not be considered as subject matter upon which the scope of the invention as defined in the claims should be constrained. Summary of the Invention [Means for solving the problem]

[0005] The embodiments of the present disclosure have been developed to address the shortcomings of existing technologies discussed below. For example, existing solutions, such as the use of heterodyne mixers, require significant periods of time to estimate small frequency differences between high frequency clock signals. Long estimation times can make frequency difference estimates out of date for use in high precision position, navigation, and timing (PNT) applications, autonomous operation, cyber / transmission security, and repeatability, and thus result in large inaccuracies in determining position. If the sampling time is reduced in such systems, the high relative error makes heterodyne-based estimates unreliable.

[0006] To remedy this deficiency, embodiments of the present disclosure provide a method for detecting tens of megahertz (10 MHz) over a sampling period of less than 6 seconds. E+6 The time between clocks running in Hz is one millihertz (1 E-3 It is possible to reliably determine frequency differences of less than 100 Hz. This short sampling time makes synchronous operation suitable for use in applications such as high precision position, navigation, and timing.

[0007] Atomic clock sources, such as, but not limited to, chip-scale atomic clocks (CSACs), provide clock signals that are stable over long periods of time, making them preferable for specialized space applications such as PNT, reciprocity, specialized science projects, and autonomous operation. An exemplary CSAC has a minimum Allan deviation that occurs over an interval of about several thousand seconds. A locally tunable clock, such as, but not limited to, a regular crystal oscillator (DO), such as an oven-controlled crystal oscillator (OCXO), is provided as a reference clock for synchronizing satellite processing systems and constellations of cooperating satellites. The minimum Allan deviation of the DO typically occurs over an interval that spans tens of seconds, after which clock drift begins to dominate clock stability. The DO is guided toward the ensemble mean for the constellation using the CSAC as a long-term stable reference.

[0008] The embodiment of the present disclosure uses the DO output (S DO) to obtain the CSAC output (S CSAC ) and performs quadrature demodulation of the DO signal. In some embodiments, a separate oscillator coupled to a phase-locked loop (PLL) synchronizes an analog-to-digital converter (ADC) to the reference signal. Real-to-IQ conversion of the digitized CSAC and DO signals is performed to generate in-phase and quadrature signals. The systems and methods of the present disclosure then perform complex multiplication (using a physical device or a virtual equivalent) between complex-valued inputs, whose frequency is S CSAC Signal and S DO This yields a complex-valued signal that is the difference between the signals.

[0009] Other embodiments of the present disclosure eliminate the separate oscillator and phase-locked loop, eliminate the ADC associated with DO, and use S as the ADC and real / IQ converter clock. DO In some embodiments, a "virtual" mixer is established by clocking the R2IQ converter (responsible for converting the CSAC signal to in-phase and quadrature components) at a multiple of the DO frequency and timing the I / Q switching and inversion. This achieves the result of calculating the frequency offset between the CSAC and DO signals with high accuracy, but also simplifies the implementation from a SWaP-C (size, weight, power, and cost), design, and processing standpoint.

[0010] This Summary of the Invention is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. It is not intended to be used to limit the scope of the claimed subject matter. A more extensive presentation of the features, details, utilities, and advantages of embodiments of the invention is provided in the following written description and illustrated in the accompanying drawings. The present invention provides, for example, the following: (Item 1) 1. A method for synchronizing clocks in a space-based electronic system, the method comprising: providing, by a first clock source, a first clock signal having a first frequency; providing, by a second clock source, a second clock signal having a second frequency that can be varied based on the tuning signal; converting the first clock signal into a digital first clock signal by an analog-to-digital converter (ADC), the ADC being sampled at a sampling frequency; converting the digital first clock signal into in-phase (I) and quadrature (Q) components by a real-to-IQ (R2IQ) switch, the R2IQ switch being clocked at the sampling frequency; demodulating, by the R2 IQ switch, the in-phase (I) component and the quadrature (Q) component of the first clock signal to generate a frequency difference signal; extracting a phase of the frequency difference signal by a phase detection circuit; estimating, with a frequency estimator circuit, a frequency offset between the first frequency and the second frequency based on the phase slope of the frequency difference signal; setting a tuning signal based on the frequency offset by a frequency tuning circuit, and adjusting the second frequency by the tuning signal to generate a corrected second clock signal; A method comprising: (Item 2) 2. The method of claim 1, wherein the tuning signal is based on the frequency offset, and adjusting the second frequency with the tuning signal modifies the second frequency to be substantially equal to the first frequency. (Item 3) 2. The method of claim 1, wherein the sampling frequency is based on the second frequency of the second clock signal. (Item 4) 4. The method according to item 3, wherein the sampling frequency is a multiple N of the Nyquist frequency of the second frequency, and N is a value between 1.1 and 5. (Item 5) 4. The method of claim 3, wherein the sampling frequency is four times the second frequency. (Item 6) providing said frequency offset based contribution to an ensemble averaging circuit; calculating an average time signal of two or more electronic systems based on the contributions using the ensemble averaging circuit; The method of claim 1, further comprising: (Item 7) 7. The method of claim 6, wherein the ensemble averaging circuitry is provided on the space-based electronic system. (Item 8) 7. The method of claim 6, wherein the ensemble averaging circuitry is provided on a second space-based electronic system and the contributions are transmitted to the second space-based electronic system by a transmitting antenna. (Item 9) 7. The method of claim 6, wherein the contribution is a fraction of the frequency offset. (Item 10) 7. The method according to claim 6, wherein the magnitude of the contribution is variable. (Item 11) providing the corrected second clock signal or a contribution based on the frequency offset to the ensemble averaging circuit by a bidirectional time transfer circuit; calculating, by said ensemble averaging circuitry, said average time signal of two or more space-based electronic systems; The method of claim 1, further comprising: (Item 12) 2. The method of claim 1, wherein the R2IQ switch comprises a 1:2 demultiplexer, a timing circuit, and sign inversion logic. (Item 13) 2. The method of claim 1, further comprising converting the samples of the first frequency in an I, Q, -I, -Q pattern using the R2 IQ switch. (Item 14) Using the R2IQ switch, converting a first sample at the first frequency to an in-phase (I) component; converting second samples of the first frequency into a quadrature (Q) component; converting a third sample of the first frequency to an inverted in-phase component (-I); converting the fourth sample of the first frequency into an inverse quadrature (-Q) component; Item 14. The method of item 13, further comprising: (Item 15) Using the R2IQ switch, converting a fifth sample of the first frequency to an in-phase (I) component; converting a sixth sample of the first frequency into a quadrature (Q) component; converting a seventh sample of the first frequency to an inverted in-phase component (-I); converting the eighth sample of the first frequency into an inverse quadrature (−Q) component; 15. The method of claim 14, further comprising: (Item 16) 2. The method of claim 1, wherein the first clock source is an atomic clock source and the second clock source is a tunable clock source. (Item 17) 2. The method of claim 1, wherein the first clock source is a chip-scale atomic clock (CSAC) clock source and the second clock source is one of a regular crystal oscillator (DO) and an oven-controlled crystal oscillator (OCXO). (Item 18) A satellite payload comprising a processor, a memory, and a program stored in the memory, the program being configured, when executed by the processor, to implement the method described in item 1. (Item 19) 1. A space-based system for synchronizing clocks in a constellation of satellites, the system comprising: one or more satellites, each of which: at least one transmitting antenna and at least one receiving antenna; A payload processor; a first clock signal source providing a first clock signal at a first frequency; a second clock signal source providing a second clock signal at a second frequency, the second clock signal being capable of being modified based on a tuning signal; a frequency difference detection (FDD) circuit configured to determine a frequency difference between the first frequency and the second frequency; Equipped with The frequency difference detection circuit includes: a real / IQ (R2IQ) switch configured to operate at a sampling rate based on the second frequency and configured to output a frequency difference signal; a phase detection circuit for extracting the phase of the frequency difference signal; a slope estimation circuit for detecting a slope of the phase of the frequency difference signal; Equipped with the slope of the frequency difference signal phase is the frequency offset between the first frequency and the second frequency; one or more satellites, a frequency tuning circuit configured to adjust the tuning signal based on the frequency difference determined by the FDD circuit, and further configured to adjust the second clock signal with the tuning signal; an ensemble clock calculation circuit provided on board said one or more satellites; Equipped with the ensemble clock calculation circuitry is configured to receive a contribution based on the frequency offset or a time stamp based on the frequency offset from another of the one or more satellites and generate an ensemble clock average for the population of satellites based on the contributions. [Brief description of the drawings]

[0011] [Figure 1]FIG. 1 illustrates an example payload block diagram for a system of the present disclosure.

[0012] [Diagram 2] FIG. 2 illustrates an exemplary system that utilizes the methods of the present disclosure.

[0013] [Diagram 3] FIG. 3 is a functional block diagram of an example of the present disclosure.

[0014] [Figure 4] FIG. 4 is a functional block diagram of another example of the present disclosure.

[0015] [Diagram 5] FIG. 5 illustrates an example circuit block diagram of the system of FIGS.

[0016] [Figure 6] 6A and 6B illustrate output signal plots of signal processing according to the present disclosure.

[0017] [Figure 7] 7A and 7B illustrate the resulting time offset error between the clocks on an exemplary constellation of cooperating satellites for the composite constellation time within the constellation (FIG. 7A) and for each local constellation (FIG. 7B).

[0018] [Figure 8] FIG. 8 depicts representative results comparing the true versus estimated difference frequency using a prior art heterodyne-based approach. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] In some examples, the disclosure is directed to measuring and correcting small frequency differences between two signals. In one example, the disclosure is directed to measuring small frequency differences between similar signals, such as two sinusoidal signals. A preferred use is provided below with respect to synchronizing two or more clocks on and / or between a constellation of satellites (or other satellite-borne assets). Although discussed in the context of satellites and constellations of satellites, the disclosure may have broader applications including the synchronization of any two similar input or output signals, such as control or feedback signals between two electric motors or other systems where precise synchronization of the devices is required.

[0020] The satellite may be equipped with a long-term stable clock source, such as an atomic clock conforming to a space-qualified atomic frequency standard (AFS), to provide a stable reference for the local clock, which may have a lower drift rate and inherent insensitivity to radiation compared to a conventional quartz crystal oscillator (XO). In some examples, the atomic clock is a chip-scale atomic clock (CSAC). Other types of oscillators may be used in place of the CSAC, provided that the Allan deviation of such clocks is substantially lower than the tunable clock source to which they are synchronized. In some examples, a typical Allan deviation for a CSAC is approximately 1 over a 10,000 second interval. E-11 while that of high-quality DO is 5 in 10 seconds. E-13 The Allan deviation of a regular crystal oscillator (DO) is about 3 in 10,000 seconds. E-10The CSAC rapidly increases to 0.5 V. A tunable regular crystal oscillator may be provided to allow the local satellite clock reference to be guided toward the ensemble average for the constellation of cooperating satellites, while the CSAC provides a stable reference to counteract time drifts that occur naturally in crystal oscillators. In some examples, the regular crystal oscillator may be an oven-controlled crystal oscillator (OCXO). In other examples, a tunable clock source such as an LC oscillator (e.g., Clapp or Colpitts oscillator), a voltage-controlled oscillator (VCO), a single distributed oscillator, a group of master oscillators, etc. may be used. As will be explained, the ensemble average calculation (e.g., clocks between satellite constellation assets) may take much longer than detection and correction for local clock offsets (e.g., offsets within satellites or other on-orbit payload components) so that instability in the ensemble average is not introduced.

[0021] Various embodiments of the present disclosure implement a quadrature demodulation algorithm to determine the small frequency difference between the CSAC clock signal and the DO clock signal and use this frequency difference to correct the tunable DO clock signal local to the satellite. The calculated frequency difference may also be used as a contribution to the ensemble clock average in a constellation of satellites. For example, a contribution may be generated by an ensemble clock calculation circuit provided on an individual satellite (e.g., satellite payload 100) based on the determined frequency difference, using a time stamp embedded in a two-way time transfer (TWTT) signal, or by a similar representation of the frequency difference. In some embodiments, a frequency difference of less than 1 millihertz (1 mHz or 0.001 Hz) can be measured and corrected between two signals operating at tens of megahertz (MHz). The disclosed quadrature demodulation operation operates on complex-valued signals and preserves the phase of the signal, which may be, for example, the phase of the two signals S DO and S CSAC, which of the two is at a higher or lower frequency. Thus, in contrast to existing solutions, the frequency difference calculation informs the magnitude and direction in which the tunable clock must be adjusted, without the need for additional processing steps. Quadrature demodulation is capable of estimating the frequency difference in a small time interval (6 seconds or less), arriving at a very accurate estimate (relative error between the true and calculated frequency difference less than 1%). Furthermore, in the example of two similar signals, such as single-tone sine waves, there is no need for any Fast Fourier Transform (FFT) processing, which would be very inefficient in this application. For example, assuming a difference frequency range of ±1 Hz, an FFT on the order of 2,000 samples in length would be required. By eliminating the need for an FFT, the complexity and size, weight, and power (SWaP) considerations are greatly improved.

[0022] Embodiments of the present disclosure will now be discussed with reference to various figures.

[0023] 1 illustrates a simplified satellite 100 payload having, among other things, one or more analog-to-digital converters (ADCs) 102, one or more digital-to-analog converters (DACs) 104, one or more digital signal processing pipelines (DSPs) 110, one or more processors 112, a clock source 114 with long-term stability such as a chip-scale atomic clock (CSAC), a tunable clock source 116 such as a regular crystal oscillator (DO), and a frequency difference detector (FDD) 118 module for determining a frequency difference between the DO 116 and the CSAC 114. The satellite payload 100 may have transmit and receive antennas 106, 108 (or optical transceivers) for communicating between the satellite and the ground and / or between satellites in a constellation of other satellites 100. Signal inputs and outputs (not shown), serializers and deserializers (SerDes) (not shown), and other component interconnects (not shown) electrically couple the components of the payload 100 in a conventional manner. As discussed below, one or more components of the satellite payload 100 may be designed or manufactured to be radiation resistant. In some examples, this may include a set of specific materials and / or specific semiconductor fabrication, processing, and treatment steps that perform better in space and high altitude radiation environments. Individual components may be equipped with radiation detection and mitigation functionality, or radiation effects detection and mitigation algorithms may be implemented in the payload at a systems level to mitigate and recover from any radiation effects on the satellite components.

[0024] The processor 112 includes one or more processing cores and may be formed as an application specific integrated circuit (ASIC), structured ASIC, field programmable gate array (FPGA), general purpose processor, central processing unit (CPU), graphics processing unit (GPU), etc., which may be provided on one or more dies within a semiconductor package or distributed across multiple packages. Various components including the DSP core 110, the processor 112, the ADC 102, the DAC 104, and / or the FDD 118 may have feature sizes between 3 nm and 180 nm, including, for example, 3 nm, 5 nm, 7 nm, 12 nm, 14 nm, 22 nm, 28 nm, 32 nm, 45 nm, 65 nm, 90 nm, or combinations of feature sizes within a semiconductor package. In some embodiments, two or more components of the satellite payload 100 are integrated together on one or more dies within a semiconductor package. For example, the ADC 102, DAC 104, DSP 110, processor 112, clock source 114, tunable clock source 116, and / or FDD 118 may be integrated together on one or more dies in a semiconductor package. The transmit antenna 106 and receive antenna 108 may be provided as a phased array (PA), a direct radiating array (DRA), a parabolic reflector, an optical (e.g., laser) link, etc. A combination of both optical and RF transceivers may also be provided. All or some of these components may be utilized in the implementation of the frequency difference algorithm described herein.

[0025] FIG. 2 illustrates multiple satellites 100 in orbit around the Earth 300 or other celestial body (e.g., an orbiting moon, asteroid, etc.). Inter-satellite communication links 150, which may be the same or different type as the transmitting antennas 106 and receiving antennas 108, facilitate the transfer of information between the satellites 100 in the constellation. Transmitting antennas 106, receiving antennas 108, and ground communication links 160, which may be the same or different type as the inter-satellite communication links 150, facilitate communication between the satellites 100 and ground assets 200 in the constellation. In some examples, the ground assets 200 may be assets such as mobile assets, including, but not limited to, people, automobiles, aircraft, watercraft, balloons, etc. In other examples, the ground assets 200 may be stationary assets such as satellite gateways, antenna arrays, buildings, homes, etc. The ground assets 200 may provide "true time" that the constellation or individual satellites 100 may use for fine calibration of local and ensemble time averages. Although discussed in the context of a constellation of satellites, satellite 100 may be provided as a single orbital asset (i.e., not part of a constellation) without departing from the scope of this disclosure. In such an implementation, inter-satellite communications link 150 may be optionally omitted.

[0026] The satellites 100 need to be time synchronized to share a common understanding of the current time with high accuracy. The communication links 150 are used to share each satellite's local estimate with its nearest neighbors in the constellation of satellites 100. A two-way time transfer (TWTT) protocol, such as, but not limited to, that defined by IEEE 1588 (incorporated herein by reference), allows each satellite payload 100 to estimate the relative time difference between itself and its neighbors to drive the difference towards zero. TWTT may be required in cases where separate nodes do not have direct access to a common time base, such as with satellites in GPS denial or poor environments. Over time, an ensemble clock for the constellation can be maintained using optimal estimation techniques such as Kalman filtering. The present disclosure describes a system that achieves on-satellite synchronization more quickly and accurately, and TWTT is therefore also more accurate and ensemble averaging is achieved more efficiently. In some examples, another process may be used to correct for any offset between the ensemble mean time and absolute time as determined by a terrestrial master oscillator at a ground station (e.g., terrestrial asset 200) using terrestrial communication link 160. The term "terrestrial" in the context of this disclosure may refer to celestial bodies other than Earth, such as, but not limited to, the Moon, Mars, Venus, asteroids, etc.

[0027]

[0033] Referring now to Figure 3, an embodiment of a frequency difference detection method and associated modules will be discussed. It should be noted that although the frequency difference detector FDD 188 (see Figure 1) is illustrated as a single module for performing the frequency difference detection method, the frequency difference detection method may be accomplished by one or more dedicated modules or by modules implemented within other satellite 100 payload components such as the DSP 110, processor 112 (ASIC, structured ASIC, FPGA, CPU, GPU, etc.).

[0028] The functional steps performed by the FDD 118 represent the complete frequency difference detection algorithm discussed below. DO and SCSAC An auxiliary oscillator 320, operating at a frequency that meets the Nyquist criterion for .pi., provides the clock for analog-to-digital conversion by ADC 324 and ADC 326. The auxiliary oscillator 320 output is clocked using a phase-locked loop (PLL) circuit 322 to generate a DO It can be synchronized with S DO may be used as a clock for other circuitry within the satellite 100 payload, as represented by signal line 321 in FIG. 3. The signals output by the real-to-IQ (R2IQ) converters 328 and 330 are complex-valued representations of the outputs of the ADCs 324 and 326. Complex mixer 331 circuitry performs a complex-by-complex multiplication between the signals output by the R2IQ converters 328 and 330. The steps performed to complete the frequency differencing algorithm are performed by a frequency difference estimation module 338, which in some examples may include the R2IQ converters 328 and 330 and the complex mixer 331. In other examples, the R2IQ converters 328 and 330 and the complex mixer 331 may be provided as individual components separate from the frequency difference estimation (FDE) module 338. The output of the complex mixer 331 may be filtered by a low pass filter 332. Data rate reduction may be performed by low pass filter 332, which may take the form of decimation of the signal output by complex mixer 331. The phase of the signal output by low pass filter 332 is extracted by phase unwrapper 334. The phase unwrapper 334 circuit removes any modulo 2π phase jumps that may be introduced. The slope of the signal output by phase unwrapper 334 is extracted and both the sign and magnitude are retained by frequency difference estimation circuit 336. The magnitude of the slope of the unwrapped phase signal is the frequency difference between the CSAC and DO signals, while the sign informs the direction of the offset required to correct this frequency difference. Hence, no additional processing is required to determine the magnitude of the frequency difference, nor which clock is at a higher or lower frequency.

[0029] The FDD118 uses a regular crystal oscillator DO output (S DO ) to obtain the Chip Scale Atomic Clock (CSAC) output (S CSAC ) is configured to perform quadrature demodulation of the CSAC signal S CSAC is provided to the ADC324, while the DO signal S DO is provided to the ADC326. The ADC324 CSAC Digital representation of CSAC(D) and the ADC326 converts it to S DO Digital representation of DO(D) The auxiliary oscillator 320 signal and S DO The signal is provided as an input to a phase-locked loop (PLL) 322, the output of which determines the sampling frequency (f S ) is provided as a PLL 322 when the auxiliary oscillator 320 generates a signal S DO The digital representation of the DO and CSAC signals, S DO(D) and S CSAC(D) are converted to in-phase and quadrature components, respectively, by real-to-IQ converters 328 and 330. The real-to-IQ (R2IQ) converters 328 and 330 may include low-pass filters to remove undesirable sum frequencies resulting from the R2IQ process.

[0030] After conversion to IQ components, the DO and CSAC signals are provided to a complex mixer 331 (i.e., non-real valued), which mixes at S CSAC and S. DO In one example, S DO The signal is selected as the reference signal, S CSAC The signal is selected as an unknown signal. This selection is simply a selection convention and may be changed without departing from the scope of this disclosure. CSAC is selected as the standard, and S DO can be selected as unknown.

[0031] In some examples, decimation of more than 100,000:1 is performed to match the significantly reduced signal bandwidth after the complex multiplication performed by the mixer 331. The decimation ratio can be chosen to minimize the number of samples retained while still respecting the Nyquist criterion with sufficient oversampling margin. In the non-limiting example of a 10 MHz CSAC signal, the bandwidth at this point of the signal processing is a few millihertz compared to the supportable bandwidth of 10 MHz, which allows decimation to be performed by only saving every nth sample and discarding the rest. In other implementations, explicit decimation by conventional methods may be necessary and may be included in the filter characteristics of the LPF and decimation module 332. In some examples, decimation below or above 100,000:1 may be performed, with the decimation level being S CSAC , S DO The frequency of the FDD signal processing chain may be selected based on the frequency of the FDD signal processing chain or the processing bandwidth of the individual components in the FDD signal processing chain.

[0032] S in Complex Mixer 331 CSAC Signal and S DO After mixing with the signal, the mixed signal is presented to a low pass filter 332 to provide noise filtering. In some examples, the low pass filter 332 may be a third order low pass filter 332 with a frequency response cutoff of 0.1 Hz. The resulting noise filtered signal may be phase unwrapped by an unwrapper 334, and the derivative of the unwrapped signal is determined by a derivative in a frequency estimation circuit 336. The derivative of the phase of the resulting signal is the frequency difference between the CSAC and the DO, with appropriate scaling. The frequency estimation circuit 336 also scales the derivative signal by 2π (e.g., divides the signal by 2π), and the result is S CSAC and S. DO The division by 2π converts the signal from units of radians per second to frequency, or cycles per second. In some cases, the slope

number

[0033] Although described as being performed by separate components 332, 334, and 336, all or part of the low pass filtering, decimation, phase unwrapping, derivative calculation, and slope estimation processing may be performed by a frequency difference estimation module 338 (e.g., a general purpose processor, a central processing unit, an ASIC, a structured ASIC, an FPGA, etc.) without departing from the scope of this disclosure.

[0034] As discussed above, the unknown signal S CSAC and S as the reference signal DO By using, the negative slope estimate is f DO >f CSAC whereas a positive slope indicates the opposite condition (f is the frequency of the respective signal). CSAC A signal is selected as the reference, S DO If is selected as unknown, the positive slope estimate is f CSAC >f DO whereas a negative slope indicates the opposite condition: complex demodulation is a function of the sign of the slope, S CSAC and S DO is at higher and lower frequencies, which simplifies processing complexity. DO The clock signal is S CSAC or S CSAC5) to be at a known offset (eg, by a frequency control circuit such as part of the circuit of FIG. 5) relative to the frequency of the first input signal.

[0035] 4 illustrates another embodiment of a frequency difference detector (FDD) 118. In the example of FIG. 4, the FDD 118a uses a regular crystal oscillator DO output (S DO ) to obtain the chip-scale atomic clock CSAC output (S CSAC ) is configured to perform quadrature demodulation of S DO The signal is S CSAC It is configured to be 2.2 to 10 times the frequency of the signal, or 1.1 to 5 times the nominal Nyquist frequency of the CSAC signal. In some examples, the S used as the sampling rate for the R2IQ switch and ADC. DO The signal is generated at a multiple N of 1.1, 1.5, 1.7, 2, 2.5, 3, 3.5, 4, 4.5, or 5 times the Nyquist frequency of the CSAC (i.e., S CSAC The frequency of the signal, f CSAC In some implementations, S CSAC and S DO The roles of S can be reversed, in which case the negative slope CSAC will be shown to be at the higher of the two frequencies. In some implementations, the sampling frequency f S may enable real-to-IQ conversion, such that the baseband demodulation performed in the R2 IQ switch 428 can be performed as a single step.

[0036] An analog-to-digital converter (ADC) 424 outputs a signal S CSAC Digitize the clock signal S DO_Nx But the signal S CSAC The input signal is provided to the ADC 424 at a frequency that is a multiple N of the Nyquist frequency of S. CSAC and S DOSince the signals are expected to have similar or close frequencies to each other, S DO_Nx In some cases, S DO may represent a frequency that is a multiple N of the Nyquist frequency of S. As discussed above, N may be a number in the range of 1.1 to 5 (e.g., N may be selected to be equal to 1.1, 1.5, 1.7, 2, 2.5, 3, 3.5, 4, 4.5, or 5). The R2IQ switch 428 circuit, which performs the real-to-IQ conversion, also DO_Nx It is clocked by the signal S DO_Nx may be used by other circuitry in the satellite 100 payload, as represented by signal line 421. A low pass filter (LPE) and decimation circuit 432 performs a low pass filtering operation to remove unwanted frequency images on the signal output by the R2 IQ switch 428. The LPF and decimation circuit 432 may also reduce the sample rate of the data stream output by the R2 IQ switch 428 in some examples. The phase of the signal output by the LPF circuit 432 is extracted by a phase unwrapper 434. The phase may be unwrapped to remove modulo 2π phase jumps that may have been introduced in the signal output by the R2 IQ switch 428 and / or the LPF and decimation circuit 432. The slope of the signal output by the phase unwrapper 434 (e.g., the derivative of the unwrapped phase) is calculated and both the sign and magnitude are preserved by the derivative in the frequency estimation circuit 436. With appropriate scaling, this output is the frequency difference between the CSAC and the DO. The frequency estimation circuit 436 scales the derivative signal by 2π (e.g., divides the signal by 2π), resulting in S CSAC and S. DO is the difference frequency between

[0037] Sampling frequency f s But, f DO_2x (i.e., N=2 or the sampling frequency is four times the frequency of DO). In some implementations, an explicit complex mixer multiplication operation S CSAC ·SDO can be eliminated. This can eliminate a complex multiplication operation consisting of four real-valued multipliers and two real-valued adders, and hence in this discussion it is referred to as "virtual mixing". The virtual mixer implemented by the "R2IQ" switch 428 can include a 1:2 demultiplexer, sign inversion logic, and a timing circuit (e.g., a 2-bit counter). The result of this operation is S CSAC and S. DO For example, f S Quadrature demodulation with / 4 is

number

number

number

[0038] This demodulation is implemented using appropriately arranged switches and code changes performed by the R2IQ switch 428. For example, CSAC The first sample of S may be converted to its in-phase (I) component, the second sample to its quadrature (Q) component, the third sample to its −I component, and the fourth sample to its −Q component. This switching sequence is then repeated. CSAC Since the frequency of is approximately, or in some cases exactly, one-quarter the sampling rate (i.e., fs / 4), S CSAC is S CSAC and S. DOThe frequency is demodulated to the difference frequency between

[0039] S CSAC The demodulation of is ±f S A narrowband low pass filter 432, which may be similar to the LPF discussed above with respect to FIG. 3, filters out any f introduced by the processing (or pre-existing in the DO or CSAC signal) S In one example, low pass filter 432 can be a simple low order filter, such as a third order LPF with a frequency response cutoff of 0.1 Hz.

[0040] Continuing with reference to FIG. 4, the output of the R2IQ switch 428 is decimated and noise is filtered out by the low pass filter and decimation module 432, similar to the process described above with respect to FIG. 3. In operation, significant decimation (in some examples, greater than 100,000:1) is performed to match the significantly reduced signal bandwidth after the complex multiplication performed by the virtual mixer (e.g., the R2IQ switch 428). In a non-limiting example of a 10 MHz CSAC signal, the bandwidth at this point is a few millihertz compared to the supportable bandwidth of 10 MHz, which allows decimation to be performed by only saving every nth sample and discarding the rest. In other implementations, explicit decimation in a conventional manner may be required and may be included in the filter characteristics of the LPF and decimation module 432. Decimation below or above 100,000:1 may be implemented, with decimation levels of S CSAC , S DO The frequency of the FDD signal may be selected based on the processing bandwidth of the individual components in the FDD signal processing chain. CSAC and S DOAfter the signals are virtually mixed, low pass filter 432 operates to reduce unwanted noise and signal images, as discussed above. The phase of the resulting noise filtered signal is unwrapped by unwrapper 434, and the derivative of the unwrapped signal is determined by frequency estimation circuit 436. The derivative of the phase of the resulting signal is the frequency difference between CSAC and DO, with appropriate scaling. Frequency estimation circuit 436 scales the derivative signal by 2π (e.g., divides the signal by 2π), and the result is S CSAC and S. DO is the difference frequency between

[0041] Similar to the discussion of FIG. 3, although described in the example of FIG. 4 as being performed by separate components 428, 432, 434, and 436, all or part of the low-pass filtering, decimation, phase unwrapping, derivative calculation, and slope estimation processing may be performed by a frequency difference estimation (FDE) module 438 (e.g., a signal processor, a general-purpose processor, a CPU, a graphics processing unit (GPU), an ASIC, a structured ASIC, an FPGA, etc.) without departing from the scope of this disclosure.

[0042] As discussed above, the unknown signal S CSAC and S as the reference signal DO By using, the negative slope estimate is f DO >f CSAC Show that f DO and f CSAC are the respective signals S DO and S CSAC A positive slope indicates the opposite condition. On the other hand, S CSAC A signal is selected as the reference, S DO If is selected as unknown, the negative slope estimate is f CSAC >f DO whereas a positive slope indicates the opposite condition. Therefore, S DO The clock signal is S CSAC or S CSAC5) to be at a known offset (e.g., by a fractional value of the frequency offset or frequency difference) relative to the frequency of S. CSAC and S DO It preserves information that allows the higher and lower frequencies to be determined from the sign of the slope, which reduces processing complexity. Furthermore, size, weight, power, and cost (SWaP-C) are significantly improved by eliminating the explicit complex multiplication operations consisting of four real-valued multipliers and two real-valued adders.

[0043] For example, a typical complex digital demodulator consists of four digital multipliers and two digital adders, which corresponds to roughly 8,000 two-input equivalent gates. If radiation mitigation and / or radiation resistant logic is included, the size may expand to 24,000 equivalent gates. In this disclosure, a complex digital demodulator using a 1:2 switch (e.g., R2IQ switch 428) comprises two sets of registers and a two-bit counter. The two-bit counter is configured to generate a repeating binary sequence [b'00, b'01, b'10, b'11] required to demultiplex the real-valued stream into in-phase and quadrature channels with alternating code conversion as described above. Compared to the typical complex digital modulator described above, this allows for implementation of the R2IQ switch 428 including radiation-hardened, radiation-resistant, and / or radiation-mitigating logic, which corresponds to roughly 1,000 equivalent gates or a 24:1 reduction in circuit size and complexity for the demodulation function alone (i.e., 24:1 when compared to the 24,000 equivalent gates of a typical complex digital demodulator). In addition to this approximately 24:1 reduction in circuit size and complexity, even greater size, weight, power, and cost (SWaP-C) benefits are realized by implementation of the R2IQ switch 428 and algorithms discussed above, due to the elimination of a separate oscillator (e.g., auxiliary oscillator 320 of FIG. 3) and phase-locked loop PLL (e.g., PLL 322 of FIG. 3) as discussed above with respect to FIG. 4. Additionally, in the example of FIG. 4, there is a reduction in the amount of noise introduced by the R2IQ signal processing, due to the elimination of the need for a physical mixer.

[0044] FIG. 5 shows the signal S in FIGS. DO and S CSAC and generates a correction signal S corr 513 and receives the measurement signal S MeasFIG. 5 illustrates example connections between the frequency difference detector component 501 transmitting 514 and the circuitry in the clock sources Chip Scale Atomic Clock (CSAC) 504 and Regular Crystal Oscillator (DO) 505. FIG. 5 illustrates frequency control paths, which may be circuit traces, parallel circuit interconnects, SerDes traces, etc., that allow the frequency of the DO 505 (or other tunable clock sources) to be tuned and controlled in response to a detected frequency difference between two or more clock sources. In some examples, the FDD 501 may include components of a frequency difference estimation module 338 or 438 as discussed above with respect to FIGS. 3 and 4. As illustrated in FIG. 4, the S CSAC is digitized by an analog-to-digital converter (ADC) 502, the output of which is passed to the R2IQ switch 428 (see FIG. 4). DO_4x is used as a sampling clock for the ADC 502 and is also provided to the FDD 501. DO_Nx 510 is, for example, a signal Clk Ref 512. The Clk may be used by other circuitry within the satellite 100 payload as a clock signal represented by 512. Ref 512 is a clock distribution circuit (CDC) 511 for making multiple copies, changing phase and frequency, changing impedance characteristics, and changing output level characteristics. DO_4x 510. In some embodiments, the frequency of the CSAC 504 can be controlled by a digital or analog control S ctrl_stat 506. Digital implementations may implement a Universal Asynchronous Transmitter / Receiver (UART) using electrical standards such as RS-232, RS-422, RS-485, Serial Peripheral Interface (SPI), etc. In particular, in some embodiments where a UART provides the interface, ctrl_stat 506 can be a bidirectional signal that returns status regarding the health and performance of the CSAC 504. DO 505 is a control voltage V tune 508. In some embodiments, the V tune508 is a multi-bit digital signal S generated by the FDD 501 tune 509, where the circuit 503 is an analog signal formed by a digital-to-analog converter (DAC). tune 508 is a pulse width modulated (PWM) signal S tune where circuit 503 is a combined active or passive low pass filter and isolation amplifier circuit (not shown). tune 508 is a digital word whose word length can vary from 8 bits to 16 bits or more. In some embodiments, the signal S corr 513 is the signal S tune 509. In some embodiments, the signal S may be an analog or digital input from a CPU, GPU, ASIC, structured ASIC, FPGA, DSP, or similar processing device that provides the correction values ​​used to derive the signal S Meas 514 may be a representation of the measurement difference signal as determined by FDD 501 that is supplied to a CPU, GPU, ASIC, structured ASIC, FPGA, DSP, or similar processing device to support calculations or as a status indication.

[0045] Figure 6 illustrates an example of the signal processing output described in the embodiment of Figures 3 and 4. A low noise case is shown for clarity, however, even with a noise level of 11 dB (or more), the frequency difference detection algorithm is able to calculate frequency differences below 1 mHz in less than 6 seconds and with a relative error below 1%.

[0046] FIG. 6A shows a case where the frequency difference is −0.001 Hz. DO When is used as the criterion, S DO FIG. 6B shows the case where the frequency difference is +0.001 Hz. The frequency difference of +0.001 Hz means that S DOmeans that the difference frequency is at the lower of the two frequencies. Curves 602 and 612 show the results after low pass filtering and decimation by LPF module 432. Curves 604 and 614 show the least squares estimates of curves 602 and 612. Curves 606 and 616 are scaled versions of the slope estimated in 434 and represent the value of the difference frequency. The magnitude of the slope of curves 606 and 616 indicates the absolute value of the frequency difference. The sign of the slope of 606 and 616 is S CSAC and S DO which are at higher and lower frequencies.

[0047] In FIG. 6A, line 602 represents the unwrapped instantaneous phase output of mixer 331 (or the output of R2IQ switch 428, acting as a virtual mixer, after processing by LPF 432 and phase unwrapper 434, as discussed above with respect to FIG. 4). Line 604 is a linear least squares fit of unwrapped instantaneous phase 602, and when scaled by 2π as discussed above, the result is slope estimation curve 606. The slope of curve 606, labeled "estimated phase," represents the frequency difference between the DO and CSAC signals. In this convention, the sign of the slope tells us which signal dominates the other, as discussed above. In the example of FIG. 6A, DO has been chosen as the reference signal for the real mixer (FIG. 3) or virtual mixer (FIG. 4), as discussed above with respect to FIGS. 3 and 4, so a positive slope on slope estimation curve 606 indicates that the DO is the reference signal for the real mixer (FIG. 3) or virtual mixer (FIG. 4). DO The frequency of is frequency S CSAC Therefore, S DO The clock signal is ramped by an amount corresponding to the estimated slope calculated by the slope estimation curve 606. DO By increasing the frequency of S CSAC or S CSAC 5) so that it is at a known offset from .gamma., it can be tuned accordingly (eg, by a frequency control circuit such as the circuit of FIG. 5).

[0048] Similarly, FIG. 6B illustrates an instantaneous phase trace 612, which represents the instantaneous phase output of mixer 331 (or the output of R2IQ switch 428, which acts as a virtual mixer, as discussed above with respect to FIG. 4). Line 614 is a linear least squares fit of the unwrapped instantaneous phase 612. When scaled by 2π, as discussed above, the slope coefficient m of 616 is the frequency difference between the DO and CSAC signals. In this convention, the sign of the slope indicates which signal dominates the other, as discussed above. In the example shown in FIGS. 6A and 6B, DO has been selected as the reference signal for the real mixer (FIG. 3) or virtual mixer (FIG. 4), as discussed above with respect to FIGS. 3 and 4, so the negative slope on curve 616, labeled “Estimated Phase,” indicates the phase difference between the DO and CSAC signals. DO The frequency of is frequency S CSAC S DO The clock signal is incremented by an amount corresponding to the estimated slope calculated by the slope estimation curve 616. DO By decreasing the frequency of S CSAC or S CSAC 5) so that it is at a known offset from .gamma., it can be tuned accordingly (eg, by a frequency control circuit such as the circuit of FIG. 5).

[0049] As shown in the captions of Figures 6A and 6B, the relative error in the estimated slope is less than one tenth of a percent. DO and S. CSACThis slope estimation, which is the detected frequency difference between the two high frequency clock signals, is performed over a sampling interval of 3 seconds in this example. The low relative error between the actual frequency difference and the calculated frequency difference, coupled with the very short sampling frequency, provides a great improvement in measuring the small frequency difference between the two high frequency clock signals. This allows for more accurate clock synchronization between the Chip Scale Atomic Clock (CSAC) 114, 504 and the Regular Crystal Oscillator (DO) 116, 505. When provided on a satellite in a cooperative constellation of satellites (such as that illustrated in FIG. 2), it allows for a more accurate and updated ensemble clock average for the constellation, thus improving the position, navigation, and timing accuracy provided locally to the constellation constituents (e.g., satellite 100) and end users (e.g., land assets 200). Two-way time transfer (TWTT) with other satellites 100 may be performed, for example, using the inter-satellite communication link 150, to provide Kalman filtering and determine optimal estimates for the ensemble clock average corrections in a conventional manner. The inter-satellite communication link 150 may be an optical link, an RF link, or a combination of optical and RF links in some examples. The ensemble clock calculation circuitry may alternatively or additionally be provided in a human, a satellite gateway, a ground or airborne asset such as an airplane, a drone, a balloon, etc.

[0050] 7A and 7B illustrate the resulting time offset error between clocks in a constellation of 100 satellites in 10 planes of 10 satellites (100) after application of an optimal ensemble average estimation technique, each of which may be Kalman filtering. Lines 702, 704, and 706 show 1x, 2x, and 3x standard deviation (σ) levels in each plot, respectively. In this exemplary situation, a notional but realistic measurement noise value of 5 nanoseconds is assumed, while a correction gain of 0.005 (i.e., 0.5% of the estimated error is applied as a correction for each iteration) is applied. Trace 708 represents the offset relative to a zero time offset. The initial time offset error was set to 30 nanoseconds (ns) and the initial frequency error was set to be 1 mHz (0.001 Hz). Two-way time transfer (TWTT) between each satellite's four nearest neighbors is used to share time offset information between adjacent satellites, and an optimal estimation technique, which may be a Kalman filter, is used in conjunction with a frequency difference detection circuit to determine the required frequency correction that minimizes the least squared error between the reference clock frequencies across the adjacent satellites. Each trace 708 represents the offset error for a single satellite. Since only a small portion of the measured correction (the amount of correction or the size of the contribution being applied, which may be a fraction or percentage of the measured frequency difference) is applied for each iteration (e.g., 0.5% of the satellite's local offset), in this non-limiting example, the clocks across the satellites in the constellation reach equilibrium in about one and a half days (120,000 seconds). The 1 σ (first standard deviation) of the time offset error between any two satellites in the constellation is about 1.6 nanoseconds for this non-limiting simulation run. A lower bound on this error is determined by the measurement uncertainty due to the sampling frequency clock used in the TWTT process.

[0051] FIG. 7B shows the time error between satellites in a local constellation, which are four satellites adjacent to a central satellite. Trace 710 represents the absolute value of the magnitude of the time offset relative to the central satellite node. As illustrated in FIG. 7B, the 1σ (first standard deviation) time difference is approximately 1 nanosecond after 5 days. As discussed above, the TWTT process used herein may conform to known protocols such as those described by IEEE 1588-2019 (IEEE Standard for Precision Clock Synchronization Protocol for Networked Measurement and Control Systems, incorporated herein by reference), and the like.

[0052] In some examples, the derivation of the ensemble average may not be instantaneous, and it may be selectively and variably adjusted to ensure that a stable ensemble average is achieved. For example, but not limited to, if a 1 mHz frequency difference is determined between the CSAC and the DO, the contribution to the ensemble average (performed by a two-way time transfer (TWTT) algorithm, including local and remote Kalman filtering) may be, for example, but not limited to, about 0.1 mHz. The magnitude and frequency of the contribution to the ensemble average may vary depending on several variables, including the size of the population, the difference between the existing ensemble average and the local satellite frequency difference, the size of the frequency difference, etc. For example, a fraction or percentage of the actual measurement time and frequency difference measured locally on the satellite may be contributed to the ensemble average. This may avoid unnecessary instability in the calculation of the ensemble average that may be introduced by very frequent (or large magnitude) contributions. Thus, at the ensemble level, a stable ensemble average may take a longer period (e.g., minutes, hours, or days) to settle compared to how quickly local satellite frequency difference calculations and corrections can be achieved, but once the ensemble average is established, the contribution of the calculated local time and frequency differences (e.g., differences between DO and CSAC frequencies on various satellites) will allow the ensemble average to be much more accurate (e.g., less deviation over time) compared to existing solutions. In other examples, as the ensemble average is calculated, the magnitude of the time corrections (e.g., the time offset contribution to the ensemble average algorithm) may be larger (larger "gain") when the ensemble average is further from equilibrium (e.g., the time average still has a large variance), and the time offset contribution may be smaller (smaller "gain") as the ensemble average is closer to the equilibrium state. An equilibrium state may be a state in which the ensemble mean varies from one mean to the next by an amount less than a predetermined threshold; the mean value of the ensemble mean has a value that varies by less than a threshold from one period to a subsequent period, etc. An equilibrium state may also be defined when the slope or first derivative of the standard deviation values ​​is about zero over a predetermined period.

[0053] Illustrate the advantages of the disclosed approach compared to the prior art heterodyne-based approach for measuring small frequency differences. FIG. 8 depicts representative results comparing true frequency difference (plot 802) versus measured frequency difference (plot 804) using prior art heterodyne. In FIG. 8, noise has been added to resemble real-world applications. However, the heterodyne-based noise-free simulation is only slightly more accurate, resulting in large signal errors when the frequency difference is small, even after significant durations. As illustrated in FIG. 8, the average relative errors are about 67%, 44%, 51%, and 23% over 60, 180, 300, and 480 seconds, respectively. Even in the noise-free case, the average relative errors are about 44%, 15%, 9%, and 4% over 60, 180, 300, and 480 seconds, respectively. This relative error reflects the failure of the heterodyne approach to take advantage of the fact that both signals have the same structure (i.e., in this case, both are sinusoidal). A frequency of 0.001 Hz requires 1,000 seconds for a sine wave to complete one cycle. At 60 seconds, only 6% of the cycle can be used to estimate the frequency. Even at 480 seconds, less than half a cycle is available to make an estimate.

[0054] In comparison, the present disclosure is able to measure a 1 mHz frequency difference in just 6 seconds with a relative error of 2.65% (error STD 7.01E-5Hz) using a real-valued mixer and 1.90% (error STD 5.54E-6Hz) using a virtual mixer. (Radiation considerations)

[0055] Due to the ionizing radiation environment experienced by electronics operating in satellite applications, it may be desirable for all or a portion of the electronics implemented in the embodiments of the present disclosure to be radiation hardened or radiation resistant. For example, all or a subset of the components described herein and depicted (non-exhaustively) in Figures 1-5 may be radiation hardened or radiation hardened. This may include any or some combination of electronics that are radiation hardened by process (related to the underlying semiconductor technology regarding how electronic devices are manufactured), by design (related to the physical layout of circuit elements on a die), or by other means. Radiation hardness may be determined through testing, analysis, or testing and analysis of devices whose design is not intentionally optimized for use in an ionizing radiation environment.

[0056] The harsh environment faced by satellites can increase the difficulty of designing electronic circuitry. One of the major environmental risks in satellite applications is associated with the ionizing radiation environment present in space. It is noted that radiation effects associated with ionizing radiation are also present in terrestrial applications, and such radiation effects are generally referred to as soft errors. The ionizing radiation environment in space includes heavy ions, protons, and neutrons, which can affect the normal operation of semiconductor devices through single event effects (SEE), total ionizing dose (TID), and / or displacement damage dose (DDD). The effects of TID and DDD generally accumulate over the mission duration and affect semiconductor parameters including current leakage. The effects of SEE are generally instantaneous and can affect the operation of semiconductor circuits. These SEE effects include single event latch-up (SEL), single event upset (SEU), single event transient (SET), and single event functional interrupt (SEFI). Mitigation for SEL can be provided through the use of technologies such as silicon-on-insulator (SOI). The effects of an SEU, SET, and / or SEFI may include causing a serial communication line (commonly referred to as a lane) to enter an invalid state (an example would be a loss of lock) such that valid data is no longer transmitted or received for an extended period of time. The incidence of soft errors in terrestrial applications for a typical semiconductor chip design is significantly lower than the incidence of SEU, SET, and / or SEFI for the same semiconductor chip design in space applications.

[0057] Unlike natural radiation environments, various man-made radiation environments are contemplated herein (e.g., prompt dose, system generated EMP effects (SGEMP), x-ray and gamma ray flash, transient dose effects, dose rate reversals, dose rate burnout, dose rate metallization failure, dose rate latch-up, dose rate rail span collapse, etc.). Radiation considerations and hardening are different from returnability considerations and operation through conditions.

[0058] Mitigation of SEU, SET, and / or SEFI in semiconductor chip designs for space applications can be performed using a variety of techniques, including the selection and optimization of materials and processing techniques in semiconductor manufacturing (Radiation Hardening by Process (RHBP)), and then the design and fabrication of specialized structures in the design of the chip that are manufactured through conventional materials and processes in the semiconductor manufacturing process (Radiation Hardening by Design (RHBD)). Additional techniques exist for providing system-level mitigation in systems that include semiconductor chips that are either RHBP, RHBD, or conventional (not specifically optimized for use in ionizing radiation environments), and such SEU, SET, and / or SEFI mitigation techniques are referred to herein as system-level radiation mitigation techniques (SLRMT). Other system-level radiation mitigation techniques may use error detection and correction (EDAC) in close proximity in time or space to radiation-affected components (e.g., system-level mitigation provided on-package or on-die, etc.).

[0059] For example, radiation effects on a clock signal, a clock generator, a clock buffer, a clock prescaler, an ADC, a DAC, a DSP core, an operational amplifier, or any of the various computational circuits may be detected by other circuitry provided in the same package, in a different package, on the same substrate, or in the same payload. Radiation effect mitigation may be provided by one or more other elements in the system, rather than the circuit or module being affected by the radiation event. Conversely, these elements may also be equipped with logic that allows them to recover from the radiation effect. In the example of a clock generator, such as a crystal oscillator, a chip-scale atomic clock, the crystal structure or material may be selected or designed to minimize the effect of the radiation effect. For example, using swept quartz (or other space-friendly material) as the oscillating crystal may reduce or prevent TID and DDD effects over time. Additionally, these elements may be equipped with logic and circuitry to block radiation effects from causing damage. In the example of a DSP, a CPU, and associated memory subsystem, circuitry may be implemented to detect the onset of a radiation event, such as elevated current draw, and disable power before damage can occur.

[0060] Effective design of electronics systems for use in space ionizing radiation environments requires system design teams to effectively and efficiently utilize components that are either RHBP, RHBD, and / or conventional, often including the use of SLRMT. Component selection and optimization of SLRMT are highly dependent on the specific details of the radiation effect to be mitigated and the desired level of system radiation resistance to be obtained. Many SEUs, SETs, and / or SEFIs are generally best mitigated as close as possible in both space and time to where the SEE-inducing event occurred in the component or system level circuitry to provide effective and efficient mitigation of such effects. For example, the duration of SETs induced in ASIC technology nodes with feature sizes <90 nm may be <1 nanosecond and may be as short as tens of picoseconds for feature sizes <32 nm. Mitigation of such short duration SETs within the same semiconductor package can provide a more efficient implementation of SET mitigation versus approaches that span two or more chips in separate locations within the same system. This efficiency comes from the ability to detect and mitigate in close spatial and / or temporal proximity to the source of the SEE-induced error.

[0061] Radiation testing may be accomplished using a beam of charged particles from a particle accelerator, which may include protons and / or heavy ions, and which may be a cyclotron or a linear accelerator. For proton beams, the beam energy may range from 0.1 MeV to 200 MeV or more, typically ranging from about >1 MeV to about either 65 or 200 MeV. For heavy ion beams, the beam energy may range from 0.1 to 100 MeV cm. 2 / mg or more, typically >0.5 to about 60-85 MeV cm 2 The total particle fluence used in such tests can vary considerably, often in the range of 1 cm for proton beams at each beam energy. 2 10 per 6 ~10 12ions or more, and in most cases, in the case of heavy ion beams, it is 1 cm at each LET value. 2 10 per 2 ~10 8 The number of SEUs, SETs, and / or SEFIs as a function of beam fluence in a given area (typically 1 cm2 or less) is often 2 ) is expressed as a cross section related to the number of observed events in the 10 -10 cm 2 It can be smaller, often about 10 -2 ~<10 -10 cm 2 A device is generally considered to be radiation hard if the number of detected SEUs, SETs, and / or SEFIs is sufficiently small that it would not significantly affect the operation of a system or circuit that contains one or more instances of that device. LET>37MeV cm as demonstrated by testing and / or analysis. 2 Heavy ion cross section at / mg < 10 -4 cm 2 are examples of cross sections that may be sufficient to demonstrate that a given device is radiation resistant. The heavy ion or proton cross sections measured or determined by analysis for a device to be considered radiation resistant at one or more beam LET or beam energy values ​​may vary considerably and depend, in part, on the expected orbit for the satellite and the extent to which the circuits and / or systems containing the device are capable of maintaining desired operation when an SEU, SET, and / or SEFI occurs.

[0062] Some or all of the electrical components disclosed in this disclosure may include at least some type of radiation hardening, radiation resistant, radiation mitigation logic, and / or compensation. Thus, ADCs, DACs, R2IQ switches, local oscillators, PLLs, LPF circuits, frequency difference detection circuits, FPGAs, ASICs, structured ASICs, CPUs, mixers, SerDes, operational amplifiers, clock distribution buffers, clock prescalers, and all or some of the circuit inputs / outputs may be monitored for radiation effects that are radiation resistant, radiation hardened, or mitigated by other processing steps. In some examples, partial or complete triple modular redundancy (TMR) may be provided, potentially at the expense of additional die space or power consumption. In other examples, the use of library cells with physical designs optimized to reduce the probability of SEEs may be used. Implementation of the algorithms of this disclosure may best be accomplished using a mixture of operational amplifiers, CPUs, ASICs, structured ASICs, and / or FPGAs coupled with radiation mitigation algorithms in DSP processors, in the logic of individual elements, etc. This may include, in some examples, scrubbing algorithms and processes and out-of-package radiation effects detection and radiation mitigation triggers.

[0063] Although only certain exemplary embodiments and methods have been described in detail above, those skilled in the art will readily appreciate that numerous modifications are possible to the exemplary embodiments and methods without substantially departing from the novel teachings and advantages of the present disclosure.

[0064] All directional references (e.g., proximal, distal, upper, lower, upward, downward, left, right, lateral, longitudinal, front, rear, top, bottom, above, below, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are used for identification purposes only to aid the reader's understanding of the present invention, and do not create limitations on the position, orientation, or use of the present invention in particular. Connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between a collection of elements and relative movement between the elements, unless otherwise indicated. Thus, connection references do not necessarily imply that two elements are directly connected and in fixed relationship to each other. The exemplary drawings are for illustrative purposes only, and the dimensions, positions, order, and relative sizes reflected in the drawings attached hereto may vary.

[0065] The above specification, examples, and data provide a complete description of the structure and use of exemplary embodiments of the invention as defined in the claims. Although various embodiments of the claimed invention have been described above with some detail or with reference to one or more individual embodiments, those skilled in the art may make numerous modifications of the disclosed embodiments without departing from the spirit or scope of the claimed invention. Other embodiments are therefore contemplated. It is intended that all matters contained in the above description and shown in the accompanying drawings shall be interpreted only as illustrations of specific embodiments, not as limitations. Changes in detail or structure may be made without departing from the basic elements of the invention as defined in the following claims.

Claims

1. 1. A method for synchronizing clocks in a space-based electronic system, the method comprising: a first clock source providing a first clock signal having a first frequency; a second clock source providing a second clock signal having a second frequency that can be varied based on the tuning signal; an analog-to-digital converter (ADC) converting the first clock signal into a digital first clock signal, the ADC being sampled at a sampling frequency; a real-to-IQ (R2IQ) switch converting the digital first clock signal into in-phase (I) and quadrature (Q) components, the R2IQ switch being clocked at the sampling frequency; the R2 IQ switch demodulating the in-phase (I) and quadrature (Q) components of the first clock signal to generate a frequency difference signal; a phase detection circuit extracting a phase of the frequency difference signal; a frequency estimator circuit estimating a frequency offset between the first frequency and the second frequency based on the phase slope of the frequency difference signal; a frequency tuning circuit setting a tuning signal based on the frequency offset and adjusting the second frequency with the tuning signal to generate a corrected second clock signal; providing said frequency offset based contribution to an ensemble averaging circuit; calculating an average time signal of two or more electronic systems based on the contributions using the ensemble averaging circuit; A method comprising:

2. 2. The method of claim 1, wherein the tuning signal is based on the frequency offset, and wherein adjusting the second frequency with the tuning signal modifies the second frequency to be substantially equal to the first frequency.

3. The method of claim 1 , wherein the sampling frequency is based on the second frequency of the second clock signal.

4. 4. The method of claim 3, wherein the sampling frequency is a multiple N of the Nyquist frequency of the second frequency, where N is a value between 1.1 and 5.

5. The method of claim 3 , wherein the sampling frequency is four times the second frequency.

6. The method of claim 1 , wherein the ensemble averaging circuitry is provided on the space-based electronic system.

7. The method of claim 1 , wherein the ensemble averaging circuitry is provided on a second space-based electronic system, and the contributions are transmitted to the second space-based electronic system by a transmitting antenna.

8. The method of claim 1 , wherein the contribution is a fraction of the frequency offset.

9. The method of claim 1 , wherein the magnitude of the contribution is variable.

10. a bidirectional time transfer circuit providing the corrected second clock signal or a contribution based on the frequency offset to the ensemble averaging circuit; the ensemble averaging circuit calculating the average time signal of two or more space-based electronic systems; The method of claim 1 further comprising:

11. 2. The method of claim 1, wherein the R2 IQ switch comprises a 1:2 demultiplexer, a timing circuit, and sign inversion logic.

12. 2. The method of claim 1, further comprising converting the samples of the first frequency in an I, Q, -I, -Q pattern with the R2 IQ switch.

13. Using the R2IQ switch, converting a first sample at the first frequency to an in-phase (I) component; converting second samples of the first frequency into a quadrature (Q) component; converting a third sample of the first frequency to an inverted in-phase component (−I); converting a fourth sample of the first frequency into an inverse quadrature (−Q) component; The method of claim 12 further comprising:

14. Using the R2IQ switch, converting a fifth sample of the first frequency to an in-phase (I) component; converting a sixth sample of the first frequency into a quadrature (Q) component; converting a seventh sample of the first frequency to an inverted in-phase component (−I); converting the eighth sample of the first frequency into an inverse quadrature (−Q) component; The method of claim 13 further comprising:

15. 2. The method of claim 1, wherein the first clock source is an atomic clock source and the second clock source is a tunable clock source.

16. 2. The method of claim 1, wherein the first clock source is a chip-scale atomic clock (CSAC) clock source and the second clock source is one of a regular crystal oscillator (DO) and an oven-controlled crystal oscillator (OCXO).

17. A satellite payload comprising a processor, a memory, and a program stored in said memory, said program configured to be executed by said processor and to implement the method of claim 1.

18. A method for synchronizing clocks in a space-based electronic system, the method comprising: a first clock source providing a first clock signal having a first frequency; a second clock source providing a second clock signal having a second frequency that can be varied based on the tuning signal; an analog-to-digital converter (ADC) converting the first clock signal into a digital first clock signal, the ADC being sampled at a sampling frequency; a real-to-IQ (R2IQ) switch converting the digital first clock signal into in-phase (I) and quadrature (Q) components, the R2IQ switch being clocked at the sampling frequency; the R2 IQ switch demodulating the in-phase (I) and quadrature (Q) components of the first clock signal to generate a frequency difference signal; a phase detection circuit extracting a phase of the frequency difference signal; a frequency estimator circuit estimating a frequency offset between the first frequency and the second frequency based on the phase slope of the frequency difference signal; a frequency tuning circuit setting a tuning signal based on the frequency offset, and adjusting the second frequency with the tuning signal to generate a corrected second clock signal; Including, the sampling frequency is based on the second frequency of the second clock signal and is a multiple N of the Nyquist frequency of the second frequency, where N is a value between 1.1 and 5.

19. 1. A space-based system for synchronizing clocks in a constellation of satellites, the system comprising: one or more satellites, each of which: a first clock signal source for providing a first clock signal at a first frequency; a second clock signal source for providing a second clock signal at a second frequency, the second clock signal being capable of being varied based on a tuning signal; an ADC for converting the first clock signal into a digital first clock signal, the ADC configured to sample at a sampling frequency; A frequency difference detection (FDD) circuit configured to determine a frequency difference between the first frequency and the second frequency, the frequency difference detection circuit comprising: An R2IQ switch, comprising: converting the digital first clock signal into in-phase (I) and quadrature (Q) components, the R2 IQ switch being clocked at the sampling frequency; demodulating the in-phase (I) and quadrature (Q) components of the first clock signal to generate a frequency difference signal; An R2IQ switch for performing a phase detection circuit for extracting the phase of the frequency difference signal; a frequency estimator circuit for estimating a frequency offset between the first frequency and the second frequency based on the phase slope of the frequency difference signal; A frequency difference detection circuit comprising: one or more satellites, a frequency tuning circuit for setting a tuning signal based on the frequency offset, wherein a corrected second clock signal is generated by adjusting the second frequency based on the tuning signal; and an ensemble averaging circuit for calculating an average time signal of two or more electronic systems based on contributions, the contributions being provided to the ensemble averaging circuit based on the frequency offset; A system comprising:

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