Display device

Abstract

Provided is a display device which is equipped with a horizontal scanning circuit that has an amplifier for supplying initialization voltage of arbitrary level to multiple data lines via a write switch; a vertical scanning circuit that supplies a drive signal simultaneously for every multiple scanning lines; and pixel circuits that are provided to correspond to the multiple data lines and the multiple scanning lines, and is configured such that the write switch of the horizontal scanning circuit is turned on, the write switch maintains an on-state, and the initialization voltage is written in the pixel circuits connected to the multiple scanning lines that are driven simultaneously by the vertical scanning circuit.　FIG. 4

Description

[Technical field]

[0001] The present technology relates to an active matrix display device. [Background technology]

[0002] Display devices using organic light emitting diodes (hereinafter referred to as OLEDs (Organic Light Emitting Diodes)) and the like as light emitting elements are known. In the display device, pixel circuits including light emitting elements and transistors are provided corresponding to pixels at the intersections of scanning lines (gate lines) and data lines (signal lines). When a data signal of a potential corresponding to the gradation level of a pixel is applied to the gate of the transistor in the pixel circuit, the transistor supplies a current corresponding to the gate-source voltage to the light emitting element, and the light emitting element emits light with a brightness corresponding to the gradation level.

[0003] In active matrix type pixels, the pixel potential is in an undefined state immediately after power is turned on, so the first light emission from that state has the problem of unintended light emission intensity or through current. Similar problems occur not only immediately after power is turned on, but also when switching inputs or modes. Therefore, it is necessary to make the pixel emit light after an initialization operation in which an initialization voltage (for example, a black level voltage) is written to the pixel.

[0004] The conventional startup initialization method involves inputting an initialization voltage from outside, turning on the write switch of the horizontal scanning circuit, holding the externally input initialization voltage in the parasitic capacitance of the data line, and then turning off the write switch. Next, the vertical scanning circuit is driven line by line, and the initialization voltage held in the parasitic capacitance of the pixel signal line is written into the pixels line by line.

[0005] This initialization method writes an initialization voltage into the pixels one line at a time, and since the initialization requires time for the number of vertical pixels, it takes a long time to display the image. In addition, there is a problem of increased rush current, and since the quality of the initialization voltage input from outside differs for each set, there is a risk that initialization will not be performed properly.

[0006] Patent Document 1 also describes a problem that occurs when starting up a liquid crystal display device. After starting up the liquid crystal display device, before the scanning lines are selected sequentially to form an image in a plurality of pixel formation portions (i.e., before the display starts), the common electrode Ec and the auxiliary electrode Es rise to a predetermined potential, and the liquid crystal capacitance and auxiliary capacitance are charged according to the potential difference between the two electrodes, resulting in an unexpected black screen (in the case of normally white) or white screen (in the case of normally black) being displayed. That is, just before the display starts, an ON voltage is applied to all the scanning lines as an active signal to turn on the TFTs, and the accumulated charges in the liquid crystal capacitance and auxiliary capacitance are discharged through the data lines. That is, in the display ON sequence at the start of the active matrix liquid crystal display device, all the scanning lines of the liquid crystal panel are selected to discharge the charges in the liquid crystal capacitance and auxiliary capacitance in each pixel formation portion through the data lines, and then the scanning lines are gradually deselected in a number of steps before the sequential selection (scanning) of the scanning lines for display starts. This reduces the current flowing through the bulk of the scanning line driving circuit, as compared with the conventional method in which all scanning lines are simultaneously in the unselected state. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Republished patent WO2006 / 085555 Summary of the Invention [Problem to be solved by the invention]

[0008] The technique described in Patent Document 1 involves gradually deselecting the scanning lines multiple times in order to discharge the charges stored in the liquid crystal capacitance and auxiliary capacitance, which is different from the technique of writing an initialization voltage to perform initialization. In other words, Patent Document 1 was unable to solve the problem of excessive rush current.

[0009] Therefore, an object of the present technology is to provide a display device that can reduce the time required for initialization while suppressing rush current. [Means for solving the problem]

[0010] This technology is A write switch is connected to each of the multiple data lines, and the write switches are continuously turned on for a period longer than one horizontal scanning period during the initialization period to display black. a horizontal scanning circuit having an amplifier for supplying an initialization voltage of the same level to a plurality of data lines via a write switch; A vertical scanning circuit that simultaneously supplies drive signals to each of a plurality of scanning lines; A pixel circuit provided corresponding to a plurality of data lines and a plurality of scanning lines; Equipped with An initialization voltage is held in the parasitic capacitance of the data line, A pixel circuit connected to a plurality of scanning lines simultaneously driven by a vertical scanning circuit Capacity A display device in which the initialization voltage is written And, At the same time, the number of scanning lines to which the drive signal is supplied is set so as to suppress the increase in rush current within an allowable range and to satisfy the requirement that the initialization period is shorter than one frame. It is a display device.

[0011] According to at least one embodiment, it is possible to shorten the initialization period while suppressing an increase in rush current and current consumption. Note that the present technology is not necessarily limited to the effects described herein, and may be any of the effects described in the present technology or effects different from those effects. Furthermore, the contents of the present technology should not be interpreted as being limited by the effects exemplified in the following description. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram of an example of a display device to which the present technology can be applied. [Diagram 2] FIG. 2 is a connection diagram for explaining a drive circuit of a conventional display device. [Diagram 3] FIG. 3 is a timing chart for explaining a drive circuit of a conventional display device. [Figure 4] FIG. 4 is a connection diagram for explaining a drive circuit according to an embodiment of the present technology. [Diagram 5] FIG. 5 is a timing chart for explaining an example of the operation of the drive circuit. [Figure 6] FIG. 6 is a timing chart for explaining an example of operation of an embodiment of the present technology. [Figure 7] FIG. 7 is a connection diagram for explaining the operation of an embodiment of the present technology. [Figure 8] FIG. 8 is a connection diagram of a first modified example of the present technology. [Figure 9] FIG. 9 is a connection diagram of a second modified example of the present technology. [Figure 10] FIG. 10 is a connection diagram of a third modified example of the present technology. [Figure 11] 11A and 11B are connection diagrams of a fourth modified example of the present technology. [Figure 12] 12A and 12B are block diagrams of an example and another example of the initialization voltage generating unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The embodiments described below are preferred specific examples of the present technology, and various technically preferable limitations are attached. However, the scope of the present technology is not limited to these embodiments unless otherwise specified in the following description to limit the present technology.

[0014] Prior to describing the present technology, an active matrix type drive circuit of a conventional display device will be described with reference to Figures 1, 2, and 3. Figure 1 is a block diagram showing a schematic configuration of a display device, Figure 2 is a connection diagram showing a part of a drive circuit of the conventional display device, and Figure 3 is a timing chart of the drive circuit.

[0015] 1, a display device equipped with an active matrix type drive circuit, such as an organic EL display device, has a vertical scanning circuit (scanning line drive circuit) 11, a horizontal scanning circuit (data line drive circuit) 12, and a pixel section 13 formed on a semiconductor substrate, such as a silicon substrate. A plurality of scanning lines (lines) from the vertical scanning circuit 11 extend horizontally to the pixel section 13, and a plurality of data lines from the horizontal scanning circuit 12 extend vertically.

[0016] As partially shown in FIG. 2, pixel circuits are connected in a matrix to data lines D1, D2, D3 extending vertically and scanning lines G1, G2, ..., Gm extending horizontally. The pixel circuits are provided with pixel circuits corresponding to pixels of the three primary colors of R (red), G (green), and blue (B). These three pixels represent one dot of a color image. For example, a pixel circuit PX1-R is connected to the scanning line G1 and data line D1, a pixel circuit PX1-G is connected to the scanning line G1 and data line D2, and a pixel circuit PX1-B is connected to the scanning line G1 and data line D3. A capacitance C1 is connected to the data lines D1, D2, and D3. The capacitance C1 is formed by the parasitic capacitance of the data lines.

[0017] A pixel circuit, for example, PX1-R, is composed of two pixel switches S1 and S2, a storage capacitor C2, and an OLED. When the pixel switches S1 and S2 are turned on, a voltage corresponding to the voltage stored in the storage capacitor C2 is applied to the OLED. The pixel switches S1 and S2 are composed of transistors, for example, P-type MOSFETs. The other switches in Fig. 2 are also composed of transistors. An initialization voltage of a predetermined level (for example, black level) is supplied from an external terminal t to the data lines D1, D2, and D3 via the write switches SEL1, SEL2, and SEL3, respectively.

[0018] 3 shows, from top to bottom, the vertical sync signal, horizontal sync signal, and pixel power supply. The first frame after the pixel power supply preparation period is set as the initialization period, after which the light emission period begins. At the beginning of the initialization period, an initialization voltage of a predetermined level (e.g., black level BK) is supplied to terminal t.

[0019] Next, the write switches SEL1, SEL2, and SEL3 are sequentially turned on, and the initialization voltage is stored in the capacitor C1 through the write switches SEL1, SEL2, and SEL3, and then the write switches SEL1, SEL2, and SEL3 are turned off. Next, the vertical scanning circuit 11 drives the scanning lines G1, G2, ..., Gm one line at a time, and the pixel switches S1 and S2 of the pixel circuits connected to the driven scanning lines are turned on. By turning on the pixel switches S1 and S2, the initialization voltage held in the capacitor C1 is transferred to the holding capacitor C2 one line at a time. For example, when the scanning line G1 is driven, the initialization voltage is applied to the OLEDs of the pixel circuits PX1-R, PX1-G, and PX1-B.

[0020] In the conventional initialization method described above, an initialization voltage is written to the pixel circuits one line at a time, and therefore initialization requires time equal to the number of vertical pixels, resulting in a long time until the image is displayed.

[0021] An embodiment of the present technology that solves such a problem will be described with reference to Figs. 4 to 7. Fig. 4 partially illustrates a circuit configuration of the embodiment. As in the configuration of Fig. 2, pixel circuits are connected in a matrix to data lines D1, D2, and D3 and scanning lines G1, G2, ..., Gm. For example, a pixel circuit PX1-R is connected to the scanning line G1 and data line D1, a pixel circuit PX1-G is connected to the scanning line G1 and data line D2, and a pixel circuit PX1-B is connected to the scanning line G1 and data line D3. A capacitance C1 is connected to the data lines D1, D2, and D3. The capacitance C1 is formed by a parasitic capacitance of the data line.

[0022] The pixel circuit PX1-R is configured by two pixel switches S1 and S2, a storage capacitor C2, and an OLED, and when the pixel switches S1 and S2 are turned on, a voltage corresponding to the voltage stored in the storage capacitor C2 is applied to the OLED. Note that in the present technology, the pixel circuit may have another configuration.

[0023] An initialization voltage generating unit 21 is provided, and an initialization voltage from the initialization voltage generating unit 21 is supplied to an amplifier 22. Write switches SEL1, SEL2, and SEL3 are connected to the amplifier 22. When the write switches SEL1, SEL2, and SEL3 are on, the initialization voltage is held in the parasitic capacitance (capacitance C1) of the data line via the amplifier 22. Thereafter, the write switches maintain the on state. There is no need to provide an external terminal as in the conventional configuration. Also, an optimal initialization voltage that is not affected by external input specifications can be generated.

[0024] A plurality of scanning lines are driven simultaneously by the vertical scanning circuit 11, and an initialization voltage is simultaneously written directly from the amplifier 22 of the horizontal scanning circuit 12 to the pixel circuits of the plurality of scanning lines, thereby performing initialization. Since the initialization voltage is simultaneously written into the pixel circuits of the plurality of scanning lines, no time is required for the number of vertical pixels.

[0025] The timing chart in Fig. 5 is an example of an operation in which an initialization voltage is written to all pixel circuits at the same time. During the initialization period, the write switches SEL1 to SEL3 are continuously turned on for one horizontal period, and an initialization voltage of a predetermined level is supplied to the data lines D1 to D3. Furthermore, during the same one horizontal period, all the scanning lines G1 to Gm are turned on. As a result, the initialization voltage is written to all pixel circuits.

[0026] However, although this all-pixel writing method can shorten the initialization period to one horizontal period, it has the problem of increasing the instantaneous current (called rush current), which means that the rush current flowing through each data line during initialization may exceed the allowable range.

[0027] In one embodiment, at the time of initialization, the pixel switches of a plurality of pixel circuits connected to a plurality of scanning lines (several scanning lines) are turned on simultaneously, rather than to all scanning lines. The timing chart shown in Fig. 6 shows an example in which an initialization voltage is written simultaneously to pixel circuits connected to, for example, two scanning lines.

[0028] In the timing chart of Fig. 6, during the initialization period (half the length of the vertical scanning period), the write switches SEL1 to SEL3 are successively turned on, and an initialization voltage of a predetermined level is supplied to the data lines D1 to D3. Furthermore, during one horizontal period, the scanning lines G1 and G2 are turned on. As a result, the initialization voltage is written to the pixel circuits PX1-R, PX1-G, PX1-B, PX2-R, PX2-G, and PX2-B connected to the scanning lines G1 and G2. Thereafter, the initialization voltage is written sequentially for every two scanning lines.

[0029] If the initialization voltage is written every other scanning line, for example, every four scanning lines, the initialization period can be reduced to 1 / 4 of the vertical scanning period. In this way, the present technology can shorten the time required for initialization compared to the conventional process of writing the initialization voltage every scanning line. In addition, the number of times the write switches SEL1 to SEL3 are turned on and off during initialization can be reduced compared to the conventional method, thereby reducing current consumption.

[0030] For example, the circuit configuration for one data line D(n) when pixel switches S1 of pixel circuits connected to n scanning lines are turned on simultaneously is as shown in Fig. 7. C1(n) is the capacitance of the data line D(n), C2(1) to C2(n) are the retention capacitances of the n pixel circuits, and S1(n) to S1(n) are the pixel switches of the n pixel circuits.

[0031] In the configuration of FIG. C1(n) <C2(1)+C2(1)+....+C2(n)

[0032] Due to this relationship, when the voltage stored in the capacitance C1 is transferred to the retention capacitances C2(1) to C2(n) of the n pixel circuits as in the conventional technique, there is a risk of insufficient writing of the initialization voltage due to an increase in output load. However, in one embodiment of the present technology, the write switches SEL1 to SEL3 are simultaneously and constantly (continuously) turned on, so that insufficient writing can be prevented. In addition, since the initialization voltage is generated by the initialization voltage generation unit 21, initialization can be performed using a stable initialization voltage.

[0033] In one embodiment of the present technology, the number of scanning lines to which the initialization voltage is simultaneously written is set so as to satisfy the conditions that "the increase in rush current is suppressed to an acceptable range, and the initialization period is shorter than one frame."

[0034] Next, a modified example of the present technology will be described. The present technology can be applied to a configuration in which a write switch is inserted between the horizontal scanning circuit 12 and the data lines. As shown in Fig. 8, the present technology can also be applied to a drive circuit (configuration in which an initialization voltage is written from above and below) in which a horizontal scanning circuit 12a having an amplifier 22a and write switches SEL1 to SEL3 is provided for three consecutive data lines D1 to D3, and a horizontal scanning circuit 12b having an amplifier 22b and write switches SEL1 to SEL3 is provided for the next three consecutive data lines D4 to D6. An initialization voltage is supplied to the horizontal scanning circuits 12a and 12b from an initialization voltage generating unit 21.

[0035] 9, the present technology can also be applied to a drive circuit (configuration in which initialization voltages are written from above and below, but the connections are nested) in which an initialization voltage is supplied from a horizontal scanning circuit 12a to odd-numbered data lines D1, D3, and D5, and an initialization voltage is supplied from a horizontal scanning circuit 12b to even-numbered data lines D2, D4, and D6. An initialization voltage is supplied to the horizontal scanning circuits 12a and 12b from an initialization voltage generator 21. Furthermore, the initialization voltage generator 21 is configured to generate a digital output, and is provided with DACs (digital-to-analog converters) 23a and 23b.

[0036] Furthermore, as shown in FIG. 10, the present technology can also be applied to a drive circuit that supplies an initialization voltage from a horizontal scanning circuit 12a to data lines D1 to D6 (configuration in which the initialization voltage is written collectively from one side).

[0037] Furthermore, the present technology can also be applied to a configuration that uses a ramp waveform to form grayscale data for a pixel, as shown in Fig. 11A and Fig. 11B. As shown in Fig. 11A, a ramp waveform (inclined waveform) from a ramp waveform generating circuit 25 is supplied to a switch group 26. The switch group 26 is configured with a plurality of switches (switching transistors) connected in parallel. A pixel circuit is connected to the output side of the switch via a data line. Therefore, the switch corresponds to the write switch in the above-mentioned embodiment of the present technology.

[0038] During normal writing, the switches in the switching group 26 are turned off at the timing of a ramp voltage corresponding to the gradation. For example, switch PA in the switch group 26 is turned on during the high level period of the waveform PA in Fig. 11B, and then turned off. Also, switch PB is turned on during the high level period of the waveform PB in Fig. 11B, and then turned off. In the case of such a configuration, when performing initialization, an initialization voltage can be written by constantly keeping the switches in the switch group 26 on.

[0039] The initialization voltage generating unit 21 is configured to generate an optimal initialization voltage that is not affected by external input specifications and fluctuations in output load. As an example, the initialization voltage generating unit 21 is configured as shown in Fig. 12A and Fig. 12B.

[0040] FIG. 12A shows a configuration in which a BGR (Band Gap Reference) circuit 27 is connected to a system power supply, an initialization voltage and a grayscale voltage that are not affected by the power supply voltage are generated, and the initialization voltage and the grayscale voltage are output via an amplifier .

[0041] 12B shows another configuration example. A BGR circuit 29 is connected to the system power supply, and a stable reference voltage that is not affected by the system power supply is formed by the BGR circuit 29, and this reference voltage is supplied to a grayscale voltage generating circuit 30. The grayscale voltage generating circuit 30 is connected to another system power supply. Using the stable reference voltage from the BGR circuit 29, the grayscale voltage generating circuit 30 can generate a grayscale voltage (and an initialization voltage) that is not dependent on another system power supply.

[0042] As described above, this technology generates an initialization voltage internally that is not affected by fluctuations in the power supply voltage and fluctuations in the output load, making it possible to switch the drive of the horizontal scanning circuit and adjust the number of simultaneously driven lines of the vertical scanning circuit only during initialization, thereby shortening the time until an image is displayed while suppressing increases in current consumption and rush current.

[0043] Although the embodiments of the present technology have been specifically described above, they are not limited to the above-mentioned embodiments, and various modifications based on the technical ideas of the present technology are possible. In addition, the modification modes can be appropriately combined with one or more arbitrarily selected ones. In addition, the configurations, methods, processes, shapes, materials, and numerical values ​​of the above-mentioned embodiments can be combined with each other as long as they do not deviate from the gist of the present technology.

[0044] In the above-described embodiment, an OLED, which is a light-emitting element, is exemplified as an electro-optical element, but any element that emits light with a luminance according to a current, such as an inorganic light-emitting diode or an LED (Light Emitting Diode), may be used.

[0045] Next, an electronic device to which the display device according to the embodiment is applied will be described. The display device is suitable for applications in which the pixels are small and high-definition. Therefore, the display device can be applied to electronic devices such as head-mounted displays, smart glasses, smartphones, and electronic viewfinders for digital cameras. [Explanation of symbols]

[0047] 11... vertical scanning circuit, 12... horizontal scanning circuit, 13... pixel unit, 21: Initialization voltage generator; 22: Amplifier; D1, D2, D3: Data lines; S1, S2: pixel switches; G1, G2, ..., Gm: scan lines; SEL1, SEL2, SEL3... Write switch

Claims

1. A horizontal scanning circuit having a write switch connected to each of a plurality of data lines, the write switches being continuously turned on for a period longer than one horizontal scanning period during an initialization period, and an amplifier supplying a black level initialization voltage to the plurality of data lines via the write switches; A vertical scanning circuit that simultaneously supplies drive signals to each of a plurality of scanning lines; pixel circuits provided corresponding to the plurality of data lines and the plurality of scanning lines; Equipped with A display device configured to hold the initialization voltage in a parasitic capacitance of the data line, and to write the initialization voltage to capacitances of the pixel circuits connected to a plurality of scanning lines simultaneously driven by the vertical scanning circuit, The number of scanning lines to which the drive signals are simultaneously supplied is set so as to suppress an increase in rush current within an allowable range, and the initialization period is set to be shorter than one frame.

2. 2. The display device according to claim 1, further comprising an initialization voltage generating section for generating the initialization voltage, the initialization voltage generating section being configured so as not to be affected by fluctuations in a power supply voltage.

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