High density multipole thin film piezoelectric element and method for making same

Abstract

A multipole piezoelectric element with improved packing density and a method for fabricating such an improved packing density multipole piezoelectric element are disclosed, which includes: a) a top electrode, a piezoelectric layer, and a bottom electrode fabricated on a substrate, b) vias created by etching the piezoelectric layer, the top electrode, or both, and c) a redistribution layer (RDL) deposited on one or more of the top electrode, the piezoelectric layer, the bottom electrode, or the one or more vias.

Description

[Technical field]

[0001] cross reference This application claims the benefit of U.S. Provisional Application No. 62 / 811,960, entitled “High Density Multi-Poled Thin Film Piezoelectric Devices and Methods of Making the Same,” filed February 28, 2019, which is incorporated by reference in its entirety for all purposes. [Background technology]

[0002] Piezoelectric devices utilize piezoelectric material during their operation. Thin film piezoelectric devices include piezoelectric materials that are thin films as opposed to bulk materials. Thin film piezoelectric devices may include capacitors, memory cells, inkjet printheads, piezoelectric micromachined ultrasonic transducers (pMUTs), and gyros. Summary of the Invention

[0003] A thin film may have a lateral dimension along a vertical direction that is substantially greater (e.g., 10 or 100 times greater) than its thickness or depth. A thin film of a piezoelectric element may be about 10 μm or less in thickness. Exemplary thin film piezoelectric elements may include capacitors, memory cells, inkjet printheads, pMUTs, and gyros. Other applications may be found in many areas around the sensor and actuator fields, such as micromirror actuators, speakerphones, microphones, autofocus drivers, passive infrared detectors, etc.

[0004] A piezoelectric material can become a ferroelectric material when it is below its Curie temperature, Tc. In the case of a ferroelectric material, the unit cell of the piezoelectric material can have an asymmetry in the unit cell such that the charged constituent ions form dipoles (e.g., a center of positive charge is displaced from a center of negative charge). The dipoles can form domains in which the dipoles are all oriented in the same direction. In some embodiments, the piezoelectric material has multiple domains, with the dipole moment of each domain being 180 degrees or 90 degrees to the adjacent domain. The domains separated by the crystal boundaries of the piezoelectric material can assume any relative orientation. In some embodiments, the process of poling aligns the domains within the piezoelectric material and the dipoles of the different piezoelectric materials essentially in one direction.

[0005] In some cases, thin film piezoelectric elements may perform better if they have multiple polar directions (e.g., two directions). For example, using a bipolar membrane reduces the number of electrode connections required by the transducer while increasing the charge for membrane deflection. The generation of more charge increases the performance of the transducer. Actuators and sensors that utilize bending beams / diaphragms are examples of such devices, including pMUTs, inkjet printheads, gyros, speakerphones, microphones, mirror actuators, and autofocus drivers. For example, for pMUTs with bipolar membranes, the driving and / or sensing schemes may be simpler and easier than devices with monopolar membranes. Furthermore, a simpler scheme (e.g., for bias voltage) is required to keep the bipolar membrane polarized than for monopolar membranes. In some embodiments, to keep the piezoelectric membrane polarized during operation, a typically constant bias voltage (Vb) is maintained across the membrane aligned with the polarization direction. By poling the membrane during operation, the dipole moment of the piezoelectric membrane is kept aligned in one direction, facilitating superior operation of the device. A time-dependent actuation voltage, Vd(t), can be used such that Vb+Vd(t) is always aligned with the polarization direction. In some embodiments, this ensures that the piezoelectric membrane remains polarized.

[0006] In some embodiments, the disclosure herein includes independent multipole piezoelectric elements, which may be produced using the same top electrode, piezoelectric layer, and bottom electrode, all fabricated on a substrate. In some embodiments, the methods and apparatus herein advantageously include vertical interconnect accesses (vias) with improved topography over existing vias. In some embodiments, the methods and apparatus herein advantageously include vias that allow for higher packing density of piezoelectric elements than existing vias. In some embodiments, the methods and apparatus herein advantageously include vias with a step profile in the piezoelectric layer. In some embodiments, the methods herein advantageously combine two different etching methods to etch the piezoelectric layer, thereby producing an improved profile of the vias. In some embodiments, the high packing density multipole piezoelectric elements are used in pMUTs for ultrasonic imaging. In some embodiments, pMUTs including the high packing density multipole piezoelectric elements herein may be produced using the same top electrode, piezoelectric layer, and bottom electrode, all fabricated on a substrate. In some embodiments, pMUTs including the high packing density multipole piezoelectric elements herein include vias with improved topography over existing vias.

[0007] In one aspect, disclosed herein is a method of fabricating a multipole piezoelectric element from a first piezoelectric element, the method comprising: a) providing a first piezoelectric element comprising a first bottom electrode, a first piezoelectric layer, a first top electrode, and a first substrate; b) separating the first piezoelectric element into a plurality of piezoelectric elements by etching one or more of the first bottom electrode, the first piezoelectric layer, or the first top electrode, where each of the plurality of piezoelectric elements comprises a bottom electrode, a piezoelectric layer, and a top electrode; c) creating one or more vertical interconnect accesses (vias) by etching the first piezoelectric layer, the first top electrode, or both; and d) depositing a redistribution layer (RDL) over the first piezoelectric element, the one or more vias, or both.

[0008] In some embodiments, step b) includes: i) etching the first top electrode to produce a plurality of top electrodes; ii) after step i), etching the first piezoelectric layer to produce a plurality of piezoelectric layers; and iii) after step ii), etching the first bottom electrode to produce a plurality of bottom electrodes of the plurality of piezoelectric elements. In some embodiments, steps i), ii) or iii) include using one or more of a dry etch, an anisotropic etch, a wet etch, or an isotropic etch.

[0009] In some embodiments, step b) further comprises patterning with a photoresist for etching in one or more of steps i), ii) or iii). In some embodiments, step b) further comprises patterning with a photoresist for etching in step ii). In some embodiments, step iii) is performed without removing the photoresist of step ii).

[0010] In some embodiments, the method further comprises removing the photoresist after step b) and before step c).

[0011] In some embodiments, step d) includes using one or more of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputter deposition, evaporation, spin-on, or plating materials. In some embodiments, step d) includes i) depositing an RDL dielectric layer on the first piezoelectric element, and ii) depositing an RDL conductor layer on the RDL dielectric layer. In some embodiments, step d) further includes etching and patterning the RDL dielectric layer after step i) and before step ii), and / or etching and patterning the RDL conductor layer after step ii). Another embodiment of step d) includes etching and patterning the RDL dielectric layer after step i) and before step ii), and step ii) is accomplished using a lift-off process to deposit and pattern said RDL dielectric layer. A further embodiment of step d) includes a process in which both steps i) and ii) are performed via lift-off.

[0012] Yet another embodiment of step d) is such that after step i), a RDL dielectric layer is deposited and patterned via lift-off, and before step ii), a RDL conductor layer is patterned and etched.

[0013] In some embodiments, step c) includes using an isotropic etch or a wet etch to etch through the first piezoelectric layer. In some embodiments, step c) includes using an anisotropic etch or a dry etch to etch through the first piezoelectric layer. In some embodiments, step c) includes i) depositing a photoresist on the first piezoelectric element, ii) etching the first piezoelectric layer to a predetermined depth, iii) etching through the first piezoelectric layer from the predetermined depth to stop at a top surface of the first bottom electrode along a vertical direction, and iv) removing the photoresist from the first piezoelectric element. In some embodiments, step ii) includes using an isotropic etch or a wet etch and step iii) includes using an anisotropic etch or a dry etch. In some embodiments, step ii) includes using an anisotropic etch or a dry etch and step iii) includes using an isotropic etch or a wet etch. In some embodiments, the first piezoelectric layer includes a stepped profile along the vertical direction configured to mitigate via topography issues. In some embodiments, the predetermined depth is less than a total depth of the piezoelectric layer along a vertical direction. In some embodiments, the methods herein are configured to reduce a characteristic length of one or more vias along a horizontal direction, thereby increasing the packing density of the plurality of piezoelectric elements.

[0014] In some embodiments, step c) includes: i) depositing a photoresist on the first piezoelectric element; ii) etching the first piezoelectric layer using an isotropic etch; and iii) removing the photoresist. In some embodiments, etching one or more of the first bottom electrode, the first piezoelectric layer, or the first top electrode includes etching two of the first bottom electrode, the first piezoelectric layer, and the first top electrode. In some embodiments, each of the plurality of piezoelectric elements is independent. In some embodiments, the multipole piezoelectric element or the first piezoelectric element is at least a portion of a piezoelectric micromachined ultrasonic transducer (pMUT).

[0015] In another aspect, disclosed herein is a method of making a multipole piezoelectric element, the method comprising: a) providing a first piezoelectric element comprising a first bottom electrode, a first piezoelectric layer, a first top electrode, and a first substrate; b) etching the first top electrode; c) depositing an RDL dielectric layer on the first top electrode; d) etching the RDL dielectric layer using an anisotropic etch; e) etching the first piezoelectric layer using an anisotropic etch; and f) depositing an RDL conductor layer on the RDL dielectric layer. In some embodiments, the method further comprises depositing a photoresist after step c) and before step d) and removing the photoresist before step f). In some embodiments, the multipole piezoelectric element or the first piezoelectric element is at least a part of a pMUT.

[0016] In another aspect, disclosed herein is a multipole piezoelectric element comprising: a) a top electrode, a piezoelectric layer, and a bottom electrode fabricated on a substrate; b) one or more vias created by etching the piezoelectric layer, the top electrode, or both; and c) a redistribution layer (RDL) deposited on one or more of the top electrode, the piezoelectric layer, the bottom electrode, or the one or more vias. In some embodiments, the one or more vias comprise a predetermined depth of the piezoelectric layer etched by a first method and a second depth remaining from the predetermined depth of the piezoelectric layer etched by a second method to stop a top surface of the bottom electrode. In some embodiments, the first method is an isotropic etch or a wet etch, and the second method is an anisotropic etch or a dry etch. In some embodiments, the first method is an anisotropic etch or a dry etch, and the second method is an isotropic etch or a wet etch. In some embodiments, the first piezoelectric layer comprises a stepped profile along a vertical direction configured to mitigate via topography issues. In some embodiments, the predetermined depth is less than a total depth of the piezoelectric layer along a vertical direction. In some embodiments, the RDL includes an RDL dielectric layer and an RDL conductor layer overlying the RDL dielectric layer. In some embodiments, one or both of the RDL dielectric layer and the RDL conductor layer are etched. In some embodiments, the RDL dielectric layer is patterned and etched using a lift-off process, and the RDL conductor layer is also deposited and patterned using a lift-off process. In some embodiments, one or more of the top electrode, the piezoelectric layer, or the bottom electrode are produced from etching a first piezoelectric element. In some embodiments, the first piezoelectric element includes a first bottom electrode, a first piezoelectric layer, a first top electrode, and a first substrate. In some embodiments, the first piezoelectric element is unipolar. In some embodiments, the first piezoelectric element is multipolar. In some embodiments, the multipolar piezoelectric element or the first piezoelectric element is at least a portion of a pMUT. [Brief description of the drawings]

[0017] A better understanding of the features and advantages of the present subject matter will be obtained by reference to the following detailed description and the accompanying drawings that set forth illustrative embodiments. [Figure 1A] FIG. 1A shows a layout diagram of an exemplary diaphragm-based pMUT, with the polar orientation of the piezoelectric material indicated by the arrows in the cross-sectional view. [Figure 1B] FIG. 1B illustrates a cross-sectional view of an exemplary diaphragm-based pMUT, with the polar direction of the piezoelectric material indicated by the arrows in the cross-sectional view. [Figure 2A] FIG. 2A shows an exemplary primary drum mode of operation of the pMUT of FIGS. 1A-1B in cross-section (top) and layout diagram (bottom). (Note: the substrate and membrane above the diaphragm are not depicted for illustrative purposes, but the electrodes of port A and port B are covered in the layout diagram. In the layout diagram, deflection is depicted by levels of grey, with black being maximum positive deflection and white being minimum deflection.) [Figure 2B] FIG. 2B is an enlarged view of the diaphragm of FIG. 2A in a cross-sectional view, illustrating the tensile and compressive strains of the substrate. [Figure 3A] FIG. 3A shows a layout diagram of an exemplary monopolar, diaphragm-based pMUT, with the polar orientation of the piezoelectric material indicated by the arrows in the cross-sectional view. [Figure 3B] FIG. 3B illustrates a cross-sectional view of an exemplary monopolar, diaphragm-based pMUT, with the polar direction of the piezoelectric material indicated by the arrows in the cross-sectional view. [Figure 4] FIG. 4 shows an example drive scheme for the monopole pMUT of FIGS. 3A-3B to efficiently drive the drum mode of FIG. 2A. [Figure 5A] FIG. 5A shows a layout diagram of an exemplary bipolar diaphragm-based pMUT, with the pole directions of the piezoelectric material indicated by the arrows in the cross-sectional view. [Figure 5B] FIG. 5B illustrates a cross-sectional view of an exemplary bipolar diaphragm-based pMUT, with the polar orientation of the piezoelectric material indicated by the arrows in the cross-sectional view. [Figure 6]FIG. 6 shows a graph of an example drive scheme for the bipolar pMUT of FIGS. 5A-5B to efficiently drive the drum mode of FIG. 2A. [Figure 7A] FIG. 7A shows a layout diagram of an exemplary bipolar diaphragm-based pMUT, with the pole directions of the piezoelectric material indicated by the arrows in the cross-sectional view. [Figure 7B] FIG. 7B illustrates a cross-sectional view of an exemplary bipolar diaphragm-based pMUT, with the polar orientation of the piezoelectric material indicated by the arrows in the cross-sectional view. [Figure 8] FIG. 8 shows a graph of an example drive scheme for the bipolar pMUT of FIGS. 7A-7B to efficiently drive the drum mode of FIG. 2A. [Figure 9A] FIG. 9A illustrates a cross-sectional view of an exemplary process sequence for fabricating a high density multipole piezoelectric element with a redistribution layer (RDL). [Figure 9B] FIG. 9B illustrates a cross-sectional view of an exemplary process sequence for fabricating a high density multipole piezoelectric element with a redistribution layer (RDL). [Figure 9C] FIG. 9C illustrates a cross-sectional view of an exemplary process sequence for fabricating a high density multipole piezoelectric element with a redistribution layer (RDL). [Figure 9D] FIG. 9D illustrates a cross-sectional view of an exemplary process sequence for fabricating a high density multipole piezoelectric element with a redistribution layer (RDL). [Figure 9E] FIG. 9E illustrates a cross-sectional view of an exemplary process sequence for fabricating a high density multipole piezoelectric element with a redistribution layer (RDL). [Figure 9F] FIG. 9F illustrates a cross-sectional view of an exemplary process sequence for fabricating a high density multipole piezoelectric element with a redistribution layer (RDL). [Figure 9G] FIG. 9G illustrates a cross-sectional view of an exemplary process sequence for fabricating a high density multipole piezoelectric element with a redistribution layer (RDL). [Figure 9H] FIG. 9H illustrates a cross-sectional view of an exemplary process sequence for fabricating a high density multipole piezoelectric element with a redistribution layer (RDL). [Figure 10A]FIG. 10A illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using anisotropic etching. [Figure 10B] FIG. 10B illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using anisotropic etching. [Figure 10C] FIG. 10C illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using anisotropic etching. [Figure 10D] FIG. 10D illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using anisotropic etching. [Figure 10E] FIG. 10E illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using anisotropic etching. [Figure 10F] FIG. 10F illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using anisotropic etching. [Figure 10G] FIG. 10G illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using anisotropic etching. [Figure 11A] FIG. 11A shows a cross-sectional view of an exemplary process sequence for creating high-density vias using isotropic etching. [Figure 11B] FIG. 11B illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using isotropic etching. [Figure 11C] FIG. 11C illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using isotropic etching. [Figure 11D] FIG. 11D illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using isotropic etching. [Figure 11E] FIG. 11E illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using isotropic etching. [Figure 11F] FIG. 11F illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using isotropic etching. [Figure 11G] FIG. 11G illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using isotropic etching. [Figure 12A] FIG. 12A shows a cross-sectional view of an exemplary process sequence for creating high-density vias using an isotropic etch followed by an anisotropic etch. [Figure 12B] FIG. 12B illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using an isotropic etch followed by an anisotropic etch. [Figure 12C] FIG. 12C illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using an isotropic etch followed by an anisotropic etch. [Figure 12D] FIG. 12D illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using an isotropic etch followed by an anisotropic etch. [Figure 12E] FIG. 12E illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using an isotropic etch followed by an anisotropic etch. [Figure 12F] FIG. 12F illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using an isotropic etch followed by an anisotropic etch. [Figure 12G] FIG. 12G illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using an isotropic etch followed by an anisotropic etch. [Figure 12H] FIG. 12H shows a cross-sectional view of an exemplary process sequence for creating high-density vias using an isotropic etch followed by an anisotropic etch. [Figure 13A] FIG. 13A shows a cross-sectional view of an exemplary process sequence for creating high-density vias using anisotropic etching followed by isotropic etching. [Figure 13B] FIG. 13B illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using anisotropic etching followed by isotropic etching. [Figure 13C]FIG. 13C illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using anisotropic etching followed by isotropic etching. [Figure 13D] FIG. 13D illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using anisotropic etching followed by isotropic etching. [Figure 13E] FIG. 13E illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using anisotropic etching followed by isotropic etching. [Figure 13F] FIG. 13F illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using anisotropic etching followed by isotropic etching. [Figure 13G] FIG. 13G illustrates a cross-sectional view of an exemplary process sequence for creating high-density vias using anisotropic etching followed by isotropic etching. [Figure 13H] FIG. 13H shows a cross-sectional view of an exemplary process sequence for creating high-density vias using an anisotropic etch followed by an isotropic etch. [Figure 14A] FIG. 14A shows a cross-sectional view of a comparison of via dimensions for the various via formation methods disclosed herein. [Figure 14B] FIG. 14B shows a cross-sectional view of a comparison of via dimensions for the various via formation methods disclosed herein. [Figure 14C] FIG. 14C shows a cross-sectional view of a comparison of via dimensions for the various via formation methods disclosed herein. [Figure 14D] FIG. 14D shows a cross-sectional view of a comparison of via dimensions for the various via formation methods disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] In one aspect, disclosed herein is a method of fabricating a multipole piezoelectric element from a first piezoelectric element, the method comprising: a) providing a first piezoelectric element comprising a first bottom electrode, a first piezoelectric layer, a first top electrode, and a first substrate; b) separating the first piezoelectric element into a plurality of piezoelectric elements by etching one or more of the first bottom electrode, the first piezoelectric layer, or the first top electrode, where each of the plurality of piezoelectric elements comprises a bottom electrode, a piezoelectric layer, and a top electrode; c) creating one or more vertical interconnect accesses (vias) by etching the first piezoelectric layer, the first top electrode, or both; and d) depositing a redistribution layer (RDL) over the first piezoelectric element, the one or more vias, or both. In some embodiments, step b) includes: i) etching the first top electrode to generate a plurality of top electrodes; ii) after step i), etching the first piezoelectric layer to generate a plurality of piezoelectric layers; and iii) after step ii), etching the first bottom electrode to generate a plurality of bottom electrodes of the plurality of piezoelectric elements. In some embodiments, steps i), ii) or iii) include using one or more of a dry etch, an anisotropic etch, a wet etch, or an isotropic etch. In some embodiments, step b) further includes patterning with a photoresist for etching in one or more of steps i), ii) or iii). In some embodiments, step b) further includes patterning with a photoresist for etching in step ii). In some embodiments, step iii) is performed without removing the photoresist of step ii). In some embodiments, the method further includes removing the photoresist after step b) and before step c). In some embodiments, step d) includes using one or more of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputter deposition, evaporation, spin-on, or plating materials.

[0019] In some embodiments, step d) comprises i) depositing an RDL dielectric layer on the first piezoelectric element and ii) depositing an RDL conductor layer on the RDL dielectric layer. In some embodiments, step d) comprises etching and patterning the RDL dielectric layer after step i) and before step ii), and further comprises etching and patterning the RDL conductor layer after step ii), or both. Another embodiment of step d) comprises etching and patterning the RDL dielectric layer after step i) and before step ii), and step ii) is accomplished using a lift-off process to deposit and pattern said RDL dielectric layer. A further embodiment of step d) comprises a process in which both steps i) and ii) are performed via lift-off. Yet another embodiment of step d) is such that in step i) depositing and patterning the RDL dielectric layer via lift-off and after step ii) patterning and etching the RDL conductor layer are performed.

[0020] In some embodiments, step c) includes using an isotropic etch or a wet etch to etch through the first piezoelectric layer. In some embodiments, step c) includes using an anisotropic etch or a dry etch to etch through the first piezoelectric layer. In some embodiments, step c) includes i) depositing a photoresist on the first piezoelectric element, ii) etching the first piezoelectric layer to a predetermined depth, iii) etching through the first piezoelectric layer from the predetermined depth to stop at a top surface of the first bottom electrode along a vertical direction, and iv) removing the photoresist from the first piezoelectric element. In some embodiments, step ii) includes using an isotropic etch or a wet etch and step iii) includes using an anisotropic etch or a dry etch. In some embodiments, step ii) includes using an anisotropic etch or a dry etch and step iii) includes using an isotropic etch or a wet etch. In some embodiments, the first piezoelectric layer includes a stepped profile along the vertical direction configured to mitigate via topography issues. In some embodiments, the predetermined depth is less than the full depth of the piezoelectric layer along the vertical direction.

[0021] In some embodiments, the methods herein are configured to reduce a feature length of one or more vias along a horizontal direction, thereby increasing the packing density of the plurality of piezoelectric elements. In some embodiments, step c) includes i) depositing a photoresist on the first piezoelectric element, ii) etching the first piezoelectric layer using an isotropic etch, and iii) removing the photoresist. In some embodiments, etching one or more of the first bottom electrode, the first piezoelectric layer, or the first top electrode includes etching two of the first bottom electrode, the first piezoelectric layer, and the first top electrode. In some embodiments, each of the plurality of piezoelectric elements is independent.

[0022] In another aspect, disclosed herein is a method of making a multipole piezoelectric element, the method comprising: a) providing a first piezoelectric element comprising a first bottom electrode, a first piezoelectric layer, a first top electrode, and a first substrate, b) etching the first top electrode, c) depositing an RDL dielectric layer on the first top electrode, d) etching the RDL dielectric layer using an anisotropic etch, e) etching the first piezoelectric layer using an anisotropic etch, and f) depositing an RDL conductor layer on the RDL dielectric layer. In some embodiments, the method further comprises depositing a photoresist after step c) and before step d) and removing the photoresist before step f).

[0023] In another aspect, disclosed herein is a multipole piezoelectric element comprising: a) a top electrode, a piezoelectric layer, and a bottom electrode fabricated on a substrate; b) vias created by etching the piezoelectric layer, the top electrode, or both; and c) a redistribution layer (RDL) deposited on one or more of the top electrode, the piezoelectric layer, the bottom electrode, or the one or more vias. In some embodiments, the one or more vias comprise a predetermined depth of the piezoelectric layer etched by a first method and a second depth that remains from the predetermined depth of the piezoelectric layer etched by a second method to stop a top surface of the bottom electrode. In some embodiments, the first method is an isotropic etch or a wet etch, and the second method is an anisotropic etch or a dry etch. In some embodiments, the first method is an anisotropic etch or a dry etch, and the second method is an isotropic etch or a wet etch. In some embodiments, the first piezoelectric layer comprises a stepped profile along a vertical direction configured to mitigate via topography issues. In some embodiments, the predetermined depth is less than a full depth of the piezoelectric layer along the vertical direction. In some embodiments, the RDL includes an RDL dielectric layer and an RDL conductor layer overlying the RDL dielectric layer. In some embodiments, one or both of the RDL dielectric layer and the RDL conductor layer are etched. In some embodiments, one or more of the top electrode, the piezoelectric layer, or the bottom electrode are produced from etching a first piezoelectric element. In some embodiments, the first piezoelectric element includes a first bottom electrode, a first piezoelectric layer, a first top electrode, and a first substrate. In some embodiments, the first piezoelectric element is unipolar. In some embodiments, the first piezoelectric element is multipolar.

[0024] Specific Terms Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art of the present invention.

[0025] As used herein, the singular forms "a," "an," and "the" include the plural forms as well, unless the context clearly indicates otherwise. Any reference herein to "or" is intended to include "and / or" unless otherwise indicated.

[0026] In some embodiments, an electrode herein is equivalent to a conductor. In some embodiments, a wafer herein comprises one or more piezoelectric elements. In some embodiments, a wafer herein comprises a plurality of independent piezoelectric elements formed from a bottom electrode (200), a piezoelectric material (201), and top electrodes (202), (203), all fabricated on a handle substrate (100).

[0027] In some embodiments, a piezoelectric thin film is used such that the piezoelectric effect is manifested by the d31 coefficient of the film. This means that a strain in the transverse direction (the "1" direction) of the film can cause a charge density in the perpendicular direction (or "3" direction). Thus, a piezoelectric element can be made with a top electrode and a bottom electrode to take advantage of this piezoelectric coefficient. Under tensile strain, a voltage change of dV can evolve across the electrodes, while an equal and opposite compressive strain causes a voltage change of -dV.

[0028] In some embodiments, actuators and / or sensors utilizing bending beams or diaphragms may simultaneously produce both tensile and compressive strains. Piezoelectric materials may be placed at these strain points to actuate or sense the strain of the element. In some embodiments, the configuration of electrodes or poles must be considered so that the electrodes do not produce conflicting positive and negative voltages.

[0029] 1A-1B, in a particular embodiment, the pMUT includes a substrate (100) having a membrane (101) formed, for example, by substrate etching. FIG. 1A shows a layout diagram of the pMUT at BB' in FIG. 1B, and FIG. 1B shows a cross-sectional view at AA' in FIG. 1A. In this embodiment, on top of the substrate (100) is a dielectric (102) layer and a piezoelectric membrane (201) sandwiched between a bottom conductor (200) and a top conductor (202), (203). In this embodiment, the pMUT operates by converting an out-of-plane electric field between the bottom and top conductors ((200), (202) and (203)) into an in-plane strain that moves the membrane (101). Thus, the pMUT converts electric charge into mechanical motion, for example, ultrasonic waves.

[0030] In some embodiments, the pMUT can be operated in its fundamental mode, i.e., drum mode, as shown in FIG. 2A. As noted in FIG. 2B, the top of the membrane (101) along the vertical direction (z-direction) can produce a region of tensile strain at the center and annular regions of compressive strain around the membrane edge. In some embodiments, the membrane (201) is polarized in only one direction along the vertical direction, as shown by the arrows in FIG. 1A-FIG. 1B and FIG. 3A-FIG. 3B. Such a membrane can be a monopolar membrane.

[0031] In some embodiments, to effectively drive the drum mode of FIG. 2A and keep the membrane (201) polarized, a non-limiting exemplary driving scheme can be used as shown in FIG. 4. In this embodiment, V A0 is the voltage from port A to port 0 (e.g., in Figures 1A and 3A), and V B0 is the voltage from port B to port 0, and F is the frequency of the drum mode. V A0 and V B0 may be of the same magnitude and frequency but different phase. In some embodiments, V A0 and V B0can be approximately shifted by half a cycle or 180 degrees in phase. In this embodiment, the positive constants Vb and Vd are a bias voltage and a driving voltage, respectively, where Vd < Vb. The function sin(2 * pi * F * t) is a sine wave with unit amplitude and frequency F. In this case, when V A0 generates a compressive stress in the piezoelectric film on the outer surface, V B0 can generate a tensile stress at the center of the diaphragm and match the stress pattern of the drum mode shown in FIG. 2B. This configuration may require at least three ports and electronics capable of delivering a two-stage driving voltage.

[0032] Similarly, when sensing the voltage across the piezoelectric film during vibration in the drum mode configuration of FIG. 2, the piezoelectric film (201) may cause a positive change in voltage in the tensile region across port B and port 0. At the same time, in the compressive region, the piezoelectric film may cause a negative change in voltage across port A and port 0.

[0033] In some embodiments, various driving and / or sensing schemes can be used with the bipolar film. In some embodiments, the bipolar film is a multipolar film having two polarities such as the pMUT shown in FIG. 5. In this case, an exemplary driving scheme shown in FIG. 6 can be used to effectively drive the drum mode of FIG. 2A and keep the film polarized. In this embodiment, the driving scheme may include two bias voltages, Vb and -Vb, having only one phase of the sine wave driving voltage so that V A0 and V B0 can have the same phase. This configuration may also require at least three ports to connect to the device.

[0034] In some embodiments, if there is a separate bottom electrode with a bipolar membrane (201) as depicted in Figures 7A-7B, the drum mode of Figure 2A can be driven with the voltages shown in Figure 8. In this case, only a single bias voltage Vb and a single drive phase are required, and the minimum number of ports is reduced from three to two.

[0035] In some embodiments, integration with a large number of pMUTs may have technical challenges in interconnecting the device with the outside world (e.g., redistribution layers [RDL] on topography and high density recording, high count density wire bond arrays, or array bonding techniques such as flip chip, ball bump, thermocompression bonding, eutectic bonding, etc.). Such technical challenges may be present in applications including ultrasound imaging, inkjet printheads, memory cells, and capacitors. In some embodiments, reduced interconnect complexity advantageously reduces production challenges, ASIC requirements, and / or increases yield. One way to solve the challenge of interconnecting a device to another device may be to bond the die on which the device is fabricated to the die on which another device is fabricated.

[0036] In some embodiments, the methods herein are configured to fabricate bipolar piezoelectric elements with high packing density. In some embodiments, the methods herein include, but are not limited to, one or more of the following operations, not necessarily in the order presented herein: applying a through-film etch to build multiple bottom electrodes, adding RDLs of additional dielectric and metal layers to allow interconnections between multiple ports, modifying the terminal etch to reduce its footprint for higher packing density.

[0037] In some embodiments, the methods herein start with an existing thin-film piezoelectric element (20) or any other device including a bottom electrode (200), a piezoelectric material (201), and a top electrode (202), (203), all fabricated on a handle substrate (100), as shown in Figures 1A-1B, 3A-3B, 5A-5B, and 9A, 10A, 11A, 12A, and 13A. In some embodiments, the existing thin-film piezoelectric element (20) may already include patterned and / or etched top electrodes (202), (203) as shown in Figures 1A-1B and 3A-3B, a backside cavity as shown in Figure 1B, and open access to the bottom electrode (200) as shown in Figure 7B.

[0038] In some embodiments, pMUT processes can be performed on thin film piezoelectric elements (20) to allow for patterning of top electrodes, adding backside cavities, and / or opening access to bottom electrodes. In some embodiments, the piezoelectric elements herein are thin film piezoelectric elements. In some embodiments, the piezoelectric elements are unipolar or multipolar thin film piezoelectric elements. In some embodiments, the methods disclosed herein generate one or more high packing density multipolar piezoelectric elements from existing piezoelectric elements. As a reference, low packing density terminals (e.g., using only wet etches) may have terminals occupying 50μm×50μm to 100μm×100μm of area, with a density of 2,500 to 10,000μm^2 per terminal. In some embodiments, the high packing density piezoelectric elements shown herein can reduce area requirements to the approximate range of 40μm×40μm to 5μm×5μm, or 1,600 to 25μm^2 per terminal. Further improvements may be realized depending on the film thickness and process equipment specifications. Thus, in some embodiments, high packing density piezoelectric elements can improve packing density by approximately 2x to 400x. In some embodiments, multi-pole piezoelectric elements can include 2, 3, 4, or more alternating polarization directions. In some embodiments, multi-pole piezoelectric elements can include two polarization directions that are approximately parallel to each other.

[0039] 9A-9H, 10A-10G, 11A-11G, 12A-12H, 13A-13H, and 14A-14D, one or more operations can be used on thin-film piezoelectric elements (20) alone or in combination with the pMUT process disclosed herein to achieve high packing density multipole (e.g., bipole) piezoelectric elements. In some embodiments, such operations include, but are not limited to, performing a through-membrane etch to etch the top electrode, piezoelectric layer (201), bottom electrode (200), or a combination thereof, depositing the RDL (redistribution layer) (205), (206), and reducing the via (207) dimensions to the bottom electrode by combining an anisotropic dry etch with an isotropic wet etch. In some embodiments, the through-membrane etch allows for the creation of a large number of independent piezoelectric elements that can function independently with independent top and bottom electrodes. In some embodiments, through-membrane etching allows for poling in two directions, thereby increasing the performance of many piezoelectric elements. In some embodiments, the RDL includes an additional dielectric layer (205) and an additional metal layer (206). Both layers of the RDL can be photosensitive. In some embodiments, the RDL, or components thereof, allow the designer to significantly reduce the complexity of the interconnects in the piezoelectric element, allowing for the creation of higher packing density piezoelectric elements.

[0040] 9A-9H show an exemplary embodiment of applying a through-membrane etch to an existing piezoelectric element (20) and depositing an RDL. In some embodiments, the existing piezoelectric element is a unipolar element that can be separated into one or more independent piezoelectric elements, e.g., multipolar piezoelectric elements. FIG. 9A shows an existing piezoelectric element (20) including a substrate (100) and a dielectric (102). On top of the dielectric (102) is a piezoelectric film (201) sandwiched between a bottom conductor (200) and a top conductor (202). If the top conductor (202) is not patterned and etched into multiple independent top electrodes as shown in FIG. 9A, an additional operation may be included to etch and pattern the top electrode (202). The piezoelectric film (201) is then patterned and etched as shown in FIG. 9B, possibly with a photoresist deposited on the element (20). In some embodiments, this is done by an isotropic etch, such as a wet etch, as shown by the curved profile in FIG. 9B. However, to increase the packing density, this etch can be done by anisotropic techniques such as dry etch. Next, with or without the intact photoresist (210) from the previous step, the bottom conductor (200) is etched by anisotropic etch, for example as in FIG. 9C (cross-sectional view shown after the photoresist (210) has been peeled off the element (20)). A wet etch can be used as well. The photoresist (210) from the piezoelectric film (201) etch can be removed after the piezoelectric film (201) etch, and various photoresist films (not shown) are deposited and patterned to allow the bottom electrode to be etched.

[0041] Photoresist (210) is used to pattern the piezoelectric film (201) and bottom conductor (200) and then removed. Terminals (207), such as vias, are patterned and etched in the piezoelectric film (201), as shown in FIG. 9D. FIGS. 10-13 show an exemplary embodiment for etching the terminals (207). Next, a dielectric film, RDL dielectric (205), is deposited on the device (20) or wafer, as shown in FIG. 9E. One or many techniques can be used for this deposition, including but not limited to CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), sputter deposition, and spin-on materials. Then, contact holes (208) are patterned and etched in the RDL dielectric (205) in FIG. 9F. This can be accomplished by anisotropic or isotropic etching. Later, RDL conductors (206) are deposited in FIG. 9G. For this deposition, one or many techniques can be used, including but not limited to CVD, PECVD, sputter deposition, evaporation, plating and spin-on materials. Finally, the RDL conductor (206) is patterned and etched. This can be accomplished by techniques such as lift-off, deposition and etching (isotropic or anisotropic), and plating. Contact holes (209) are patterned and etched in the RDL conductor (206) of FIG. 9H. The operating sequence shown in FIG. 9A-FIG. 9H may allow the designer to create independent bottom electrodes for multipole piezoelectric elements. The RDL layer, RDL dielectric (205) and RDL conductor (206) allow the designer to tightly connect various top electrodes, for example etched from a single top electrode, in any number of combinations with the bottom electrodes to enable high density recording, and may allow fewer interconnections with the outside of the element if properly designed.

[0042] To further increase the packing density of the piezoelectric elements, one may also try to shrink the via dimensions from the RDL conductor (206) to the bottom conductor (200). Such an exemplary process is shown in Figures 10A-10G. In this embodiment, the RDL dielectric (205) is deposited immediately after the top conductor (202) is patterned and etched, as shown in Figures 10A-10B. Next, photoresist (210) is deposited and patterned in Figure 10C, after which the RDL dielectric (205) is anisotropically etched, as shown in Figure 10D, followed by anisotropic etching of the piezoelectric film (201), and stopping on the bottom conductor (200), as shown in Figures 10D-10E. The photoresist (210) is removed, as shown in Figure 10F, and the RDL conductor (206) is deposited, as shown in Figure 10G. Operations such as those in Figures 10A-10G can result in a small vertical profile, which is good for packing density. However, sometimes it may be desired that the RDL conductors (206) be deposited over significant topography which may result in spaces, broken lines or other problems.

[0043] In some embodiments, to improve the via topography, the via can be created using isotropic etching of the piezoelectric film (201), as detailed in Figures 11A-11G. Referring to Figure 11A, the top electrode (202) is patterned and etched. Then, as in Figure 11B, a photoresist (210) is deposited and patterned. Next, the piezoelectric film (201) can be isotropically etched, as shown in Figure 11C. After the photoresist (210) is removed, as shown in Figure 11D, a gradually sloping profile remains in the piezoelectric film (201), which reduces the sidewall slope of the via and minimizes the impact of the topography on subsequently deposited layers or films (topography is the height difference between the shallowest and tallest element features). Next, the RDL dielectric (205) is deposited, as shown in Figure 11E, and patterned and etched, as in Figure 11F. Finally, the RDL conductors (206) are deposited as shown in Figure 11G. The process techniques shown in Figures 11A-11B can be effective in reducing the sidewall slope of the via, but can result in larger vias than the embodiment of Figures 10A-10G.

[0044] In some embodiments, the methods herein include a hybrid via processing approach that utilizes both isotropic and anisotropic etching of the piezoelectric film (201). Figures 12A-12G show an exemplary embodiment of this hybrid via processing approach. In some embodiments, this hybrid approach advantageously reduces the total via area, thereby increasing packing density. In some embodiments, this hybrid approach advantageously facilitates mitigating topography issues by reducing the sidewall angle of the via. With reference to Figures 12A-12G, in this particular embodiment, the top electrode (202) may be patterned and etched as in Figure 12A, and a photoresist (210) may be deposited and patterned on the wafer as shown in Figure 12B. The piezoelectric film (201) is then subjected to a partial isotropic etching of the film as shown in Figure 12C. In some embodiments, the partial etching extends from the top surface of the film to a predetermined depth of the film that is less than the total thickness of the film (i.e., the thickness of the film from the top surface to the bottom surface along the vertical, or z, direction). The depth of the etch can be adjusted for depth control and feature relief. To complete the etch, an anisotropic etch is performed in FIG. 12D, from a predetermined depth and through the piezoelectric film (201), stopping at the top surface of the bottom conductor (200). After the photoresist (210) is removed in FIG. 12E, the piezoelectric film (201) has a stepped profile as shown in FIG. 12E, which tends to alleviate the problems encountered in the feature. Next, the RDL dielectric (205) can be deposited in FIG. 12F and patterned and etched as in FIG. 12G. Then, the RDL conductor (206) can be deposited as shown in FIG. 12H.

[0045] An alternative approach to the technique used in FIGS. 12A - 12H is to first perform anisotropic etching and then isotropic etching, as detailed in FIGS. 13A - 13H. In this particular embodiment, a photoresist (210) is deposited and patterned on the wafer as shown in FIG. 13B. The piezoelectric film (201) is subjected to partial anisotropic etching of the film as shown in FIG. 13C. The depth of the etching can be adjusted for depth control and relaxation of the microstructure. To complete the etching, the isotropic etching is performed through the piezoelectric film (201) and stops on the lower conductor (200) and is carried out as shown in FIG. 13D. After the photoresist (210) is removed, the RDL dielectric (205) is deposited (FIG. 13F), patterned, and etched (FIG. 13G). Thereafter, the RDL conductor (206) can be deposited (FIG. 13H). In this embodiment, the piezoelectric film (201) has a profile that is more inclined than those in FIGS. 10A - 10G. In the same embodiment, the vias are smaller than those in FIGS. 11G and / or 12H. However, there may still be higher sidewall angles and associated microstructure problems compared to FIGS. 11G and 12H.

[0046] FIGS. 14A - 14D show a comparison of various techniques disclosed herein for forming an RDL conductor (206) to a lower conductor (200) via. In some embodiments, the characteristic length of the via can be determined as La for the anisotropic etching in FIG. 10G, Lb for the isotropic etching in FIG. 11G, Lc for the anisotropic etching after the isotropic etching in FIG. 12H, and Ld for the isotropic etching after the anisotropic etching in FIG. 13H. In this embodiment, La < Ld ~ Lc < Lb. That is, all anisotropic etching produces the smallest vias, and all isotropic etching produces the largest vias. The isotropic and anisotropic hybrid approaches disclosed herein provide smaller vias while reducing concerns regarding microstructure, thereby enabling denser recording of piezoelectric elements.

[0047] In some embodiments, one or more of the operations in Figures 9A-9H, 10A-10G, 11A-11G, 12A-12H, and 13A-13H may be performed in a different order.

[0048] Although certain embodiments and examples are provided in the above description, the subject matter of the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or applications, as well as modifications and equivalents thereof. Thus, the claims appended hereto are not limited to any of the specific embodiments described below. For example, in any method or process disclosed herein, the acts or operations of the method or process may be performed in any suitable order, but are not necessarily limited to any suitable order disclosed. As may be useful in understanding certain embodiments, various operations may be described as multiple separate operations. However, the order of description should not be construed to imply that these operations are order-dependent. In addition, the structures, systems, and / or devices described herein may be embodied as integrated components or separate components.

[0049] For purposes of comparing various embodiments, certain aspects and advantages of the embodiments are described. Not necessarily all such aspects or advantages are achieved by any particular embodiment. Thus, for example, various embodiments may be implemented to achieve or optimize one or a set of advantages as taught herein, without necessarily achieving other aspects or advantages as taught or suggested herein.

[0050] As used herein, A and / or B includes one or more of A or B, and combinations of A and B, etc. It is understood that the terms "first," "second," "third," etc. may be used to describe various elements, components, regions, and / or sections. These terms are merely used to distinguish one element, component, region, or section from another element, component, region, or section. Thus, a first element, component, region, or section described below may be referred to as a second element, component, region, or section without departing from the teachings of the present disclosure.

[0051] The terms used herein are for describing specific embodiments only and are not intended to limit the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including", as used herein, specify the presence of the stated features, regions, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0052] As used herein and in the claims, unless otherwise indicated, the terms "about" and "approximately" refer to a range of + / -0.1%, + / -1%, + / -2%, + / -3%, + / -4%, + / -5%, + / -6%, + / -7%, + / -8%, + / -9%, + / -10%, + / -11%, + / -12%, + / -14%, + / -15%, or + / -20% of a numerical value, and increments thereof, depending on the embodiment. As a non-limiting example, about 100 meters represents a range of 95 to 105 meters (+ / -5% of 100 meters), 90 to 110 meters (+ / -10% of 100 meters), or 85 to 115 meters (+ / -15% of 100 meters), depending on the embodiment.

[0053] While preferred embodiments have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Numerous variations, changes, and substitutions will occur to those skilled in the art without departing from the scope of the present disclosure. It should be understood that various alternatives to the embodiments described herein may be utilized in practice. Various combinations of the embodiments described herein are possible, and such combinations are considered part of the present disclosure. In addition, all features discussed with respect to any one embodiment herein can be readily adapted for use with other embodiments herein. It is intended that the following claims define the scope of the present disclosure, and that methods and structures within the scope of the claims, and equivalents thereof, are covered by the present disclosure.

Claims

1. 1. A method of making a multipole piezoelectric element from a first piezoelectric element, the method comprising: a) providing a first piezoelectric element comprising a dielectric layer, a first bottom electrode, a first piezoelectric layer, a first top electrode and a first substrate; b) separating the first piezoelectric element into a plurality of piezoelectric elements by etching one or more of the first bottom electrode, the first piezoelectric layer, or the first top electrode, where each of the plurality of piezoelectric elements includes a bottom electrode, a piezoelectric layer, and a top electrode; c) creating one or more first vertical interconnect accesses (vias) by etching the first piezoelectric layer, the first top electrode, stopping on the first bottom electrode; d) creating one or more second vertical interconnect accesses (vias) by etching the first piezoelectric layer, the first top electrode, and the first bottom electrode, stopping on the dielectric layer; e) depositing a redistribution layer (RDL) over the first piezoelectric element, the one or more first vias, the one or more second vias, and the entire top surface of the first top electrode; The method, wherein step e) comprises the steps of: (i) depositing an RDL dielectric layer over the first piezoelectric element; and (ii) depositing an RDL conductor layer over the RDL dielectric layer.

2. Step b) comprises: i) etching the first top electrode to create a plurality of top electrodes; ii) after step i), etching the first piezoelectric layer to produce a plurality of piezoelectric layers; iii) after step ii), etching the first bottom electrode to produce a plurality of bottom electrodes of a plurality of piezoelectric elements.

3. 3. The method of claim 2, wherein step b) further comprises using a photoresist to pattern in one or more of steps i), ii) or iii) for etching.

4. The method of claim 3 , wherein step iii) is performed without removing the photoresist of step ii).

5. 4. The method of claim 3, further comprising the step of removing the photoresist after step b) and before step c).

6. 6. The method of claim 5, wherein step e) further comprises: etching and patterning the RDL dielectric layer after step i) and before step ii), and / or etching and patterning the RDL conductor layer after step ii).

7. Step c) comprises: i) depositing a photoresist onto the first piezoelectric element; ii) etching the first piezoelectric layer to a predetermined depth; iii) etching through the first piezoelectric layer from the predetermined depth along a vertical direction to stop at a top surface of the first bottom electrode; and iv) removing the photoresist from the first piezoelectric element.

8. The method of claim 7 , wherein the first piezoelectric layer comprises a step profile along a vertical direction.

9. The method of claim 7 , wherein the predetermined depth is less than a total depth of the piezoelectric layer along a vertical direction.

10. 8. The method of claim 7, wherein performing steps a)-e) shortens a feature length of one or more vias along a horizontal direction, thereby increasing the packing density of the plurality of piezoelectric elements.

11. Step c) comprises: i) depositing a photoresist onto the first piezoelectric element; ii) etching the first piezoelectric layer using an isotropic etch; and iii) removing the photoresist.

12. 1. A method of making a multipole piezoelectric element, the method comprising: a) providing a first piezoelectric element comprising a first bottom electrode, a first piezoelectric layer, a first top electrode and a first substrate; b) etching the first top electrode and the first piezoelectric layer to create a first vertical interconnect access (via) and etching the first top electrode, the first piezoelectric layer and the first bottom electrode to create a second vertical interconnect access (via); c) depositing a RDL dielectric layer over and in contact with the entire top surface of the first upper electrode; d) etching the RDL dielectric layer using an anisotropic etch; e) etching the first piezoelectric layer using an anisotropic etch; f) depositing an RDL conductor layer on said RDL dielectric layer.

13. 13. The method of claim 12, further comprising depositing a photoresist after step c) and before step d), and removing the photoresist before step f).

14. A multi-pole piezoelectric element, the multi-pole piezoelectric element comprising: a) a top electrode, a piezoelectric layer, and a bottom electrode fabricated on a substrate; b) a first vertical interconnect access via etched into said piezoelectric layer and said top electrode; c) a second vertical interconnect access via created by etching the piezoelectric layer, the top electrode, and the bottom electrode; d) a redistribution layer (RDL) deposited on one or more of the top electrode, the piezoelectric layer, the bottom electrode, or one or more of the vias, the redistribution layer comprising: e) a RDL dielectric layer deposited on a first piezoelectric element, the first piezoelectric element including the top electrode, the piezoelectric layer, and the bottom electrode; f) a RDL conductor layer deposited on said RDL dielectric layer.

15. 15. The multipole piezoelectric element of claim 14, wherein the one or more vias include a predetermined depth in the piezoelectric layer and a second depth that continues from the predetermined depth in the piezoelectric layer to terminate at a top surface of the bottom electrode.

16. The multipole piezoelectric element of claim 14 , wherein the piezoelectric layer comprises a step profile along a vertical direction.

17. 16. The multipole piezoelectric element of claim 15, wherein the predetermined depth is less than a total depth of the piezoelectric layer along a vertical direction.

18. The multipole piezoelectric element of claim 14 , wherein the RDL includes an RDL dielectric layer and an RDL conductor layer overlying the RDL dielectric layer.

19. The multipole piezoelectric element of claim 14 , wherein one or more of the top electrode, the piezoelectric layer, or the bottom electrode are produced from a first piezoelectric element.

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