Semiconductor device, display device

Abstract

To provide a semiconductor device and a shift register circuit that generate less noise in a non-selection period and do not turn a transistor all the time.SOLUTION: A shift register circuit includes four transistors. A gate of a transistor 95 is connected to Vout, one of a source and a drain is connected to an input terminal 52, and the other of the source and the drain is connected to a gate of transistor 92. One of the source and the drain of the transistor 92 is connected to VSS, and the other of the source and the drain is connected to an output terminal 55. A gate of a transistor 93 is connected to an input terminal 53, one of the source and the drain is connected to VSS, and the other of the source and the drain is connected to the output terminal 55. A gate of a transistor 94 is connected to an input terminal 54, one of the source and the drain is connected to VSS, and the other of the source and the drain is connected to the output terminal 55.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. In particular, the present invention relates to a shift register configured using transistors. The present invention also relates to a display device including the semiconductor device, and an electronic device including the display device. Regarding child devices.

[0002] The term "semiconductor device" used here refers to any device that can function by utilizing semiconductor characteristics. This refers to. [Background technology]

[0003] In recent years, display devices such as liquid crystal display devices and light-emitting devices have become increasingly popular as large display devices such as liquid crystal televisions. In particular, the development of transistors formed from amorphous semiconductors on insulators has been actively pursued. Using transistors, the pixel circuit and the driver circuit including the shift register circuit (hereinafter referred to as the internal The technology of forming integrated circuits is actively being developed because it contributes greatly to reducing power consumption and costs. The internal circuit formed on the insulator is connected to the controller via an FPC, etc. The external circuit is connected to an external IC or the like and its operation is controlled.

[0004] For example, a semiconductor memory device may be constructed using only N-channel transistors formed from amorphous semiconductor. A shift register circuit in which the shift register is arranged has been proposed (for example, Patent Document 1). In the circuit shown in FIG. 1, the output of the shift register circuit is floating during the non-selection period. There was a problem that noise was generated during the non-selection period.

[0005] To solve this problem, the output of the shift register circuit is floated during the non-selection period. A shift register circuit that does not require a shift register has been devised (for example, Non-Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Special table 10-500243 [Non-patent literature]

[0007] [Non-Patent Document 1] 2.0inch a-Si:H TFT-LCD with Low Noise Integrated Gate Driver SID'05 Digest P942-945 Summary of the Invention [Problem to be solved by the invention]

[0008] In Non-Patent Document 1, a transistor connected in series between the output and the power supply is always turned on during the non-selection period. The power supply voltage is output by turning on the shift register circuit when the Since most of the time between the transistors is non-selected, the transistors are always on during the non-selected period. If the shift register circuit is turned on, the shift register circuit will be turned on for most of its operation period.

[0009] However, transistors made of amorphous semiconductors are turned on for a long time when a voltage is applied. It is known that the characteristics deteriorate according to the voltage applied. The threshold voltage shift is significant and is one of the major causes of malfunctions in shift register circuits. Become one.

[0010] In view of such problems, the present invention provides a method for reducing noise and reducing traces even during a non-selection period. A semiconductor device in which a transistor is not always turned on, a shift register circuit, and such a semiconductor device The present invention aims to provide a display device including a semiconductor device and an electronic device including the display device. The target. [Means for solving the problem]

[0011] The semiconductor device of the present invention includes a first transistor, a second transistor, and a third transistor. The first transistor has a gate connected to a first signal and a fourth transistor. A predetermined potential is input to one of the source and drain, and a predetermined potential is input to the other of the source and drain. The other end is connected to the gate of the second transistor and one of the source and drain of the third transistor. a second signal is input to one of the source and the drain of the second transistor; The other of the source and the drain is connected to the output terminal, and the third transistor has a third A signal is input, a predetermined potential is input to the other of the source and the drain, and the fourth transistor The transistor has a gate to which a third signal is input and a predetermined potential input to either the source or the drain. The other of the source and the drain is connected to the output terminal.

[0012] The shift register of the present invention is a shift register consisting of a plurality of stages. Each stage of the transistor circuit is turned on by receiving a high-level output signal from the previous stage. A first transistor that outputs a potential of about high level, and One of the source and drain is connected to the first signal line, and the other of the source and drain is connected to the second signal line. The other of the two transistors is a second transistor connected to a first transistor in the next stage, and A low-level output signal is input from the second stage, and the second transistor operates in bootstrap mode. During the period when the transistor is not in operation, a low-level potential is output to the gate of the second transistor at regular intervals. A first means for inputting a low-level output signal from a previous stage and a second transistor During the period when the bootstrap operation is not performed, the source and drain of the second transistor and a second means for outputting a low-level potential to the other of the two at regular intervals. is doing.

[0013] In the shift register of the present invention, in the above configuration, the first means and the second means are It is characterized by being controlled by lines.

[0014] In the shift register of the present invention, the first means is a second signal line that is at a high level. When the first signal line is at a low level, the second signal line outputs a low-level potential. The present invention is characterized in that the above-mentioned is realized by a circuit configuration including a third transistor having a function other than that of the first transistor. is.

[0015] In the shift register of the present invention, the second means is a second signal line that is at a high level. When the first signal line is at a low level, the second signal line outputs a low-level potential. When the second signal line is at a low level, the second signal line outputs nothing. The present invention is characterized in that the above-mentioned is realized by a circuit configuration including a fourth transistor having a function other than that of the first transistor. is.

[0016] In the shift register of the present invention, in the above configuration, the first means is The first means is controlled by a first signal line, and the second means is controlled by a second signal line.

[0017] In the shift register of the present invention, in the above configuration, the first means is a means for detecting that the output of the next stage is at a high level. When the output of the next stage is at low level, it outputs a low-level potential. The present invention is characterized in that the above-mentioned is realized by a circuit configuration including a fifth transistor having a function other than that of the first transistor. is.

[0018] In the shift register of the present invention, the second means is a second signal line that is at a high level. When the first signal line is at a low level, the second signal line outputs a low-level potential. When the second signal line is at a low level, the second signal line outputs nothing. The present invention is characterized in that the above-mentioned is realized by a circuit configuration including a sixth transistor having a function other than that of the first transistor. is.

[0019] In the shift register of the present invention, in the above configuration, the first means is controlled by the second signal line. the first means is controlled by a second signal line and a third signal line. is doing.

[0020] In the shift register of the present invention, in the above configuration, the first means is a means for detecting that the output of the next stage is at a high level. When the output of the next stage is at low level, it outputs a low-level potential. The present invention is characterized in that the above-mentioned is realized by a circuit configuration including a seventh transistor having a function other than that of the first transistor. is.

[0021] In the shift register of the present invention, the second means is a second signal line that is at a high level. When the first signal line is at a low level, the second signal line outputs a low-level potential. When the second signal line is at a low level, the second signal line outputs nothing. The present invention is characterized in that the above-mentioned function is realized by a circuit configuration including an eighth transistor having a function other than that of the first transistor. a shift register that outputs a low-level potential when the third signal line is at a high level, A ninth transistor is connected to the third signal line to have the function of not outputting anything when the third signal line is at a low level. A shift register is realized by a circuit configuration including Its distinctive feature is that it is realized by

[0022] The shift register of the present invention is a shift register consisting of a plurality of stages. Each stage of the transistor circuit is turned on by receiving a high-level output signal from the previous stage. A first transistor that outputs a potential of about high level, and One of the source and drain is connected to the first signal line, and the other of the source and drain is connected to the second signal line. The other of the two transistors is a second transistor connected to a first transistor in the next stage, and A low-level output signal is input from the second stage, and the second transistor operates in bootstrap mode. During the period when the transistor is not in operation, a low-level potential is output to the gate of the second transistor at regular intervals. and a first means for inputting a voltage to the second transistor during a period when the second transistor is not performing a bootstrap operation. a third transistor for outputting a low-level potential to the other of the source and drain of the second transistor; The present invention is characterized by comprising a means.

[0023] In the shift register of the present invention, in the above configuration, the first means is controlled by the second signal line. The third means is a first signal, a second signal, a third signal, and a second transistor. It is characterized by being controlled by an inverted signal of the gate potential.

[0024] In the shift register of the present invention, the first means is a second signal line that is at a high level. When the first signal line is at a low level, the second signal line outputs a low-level potential. The present invention is characterized in that the above-mentioned is realized by a circuit configuration including a tenth transistor having a function not included in the above-mentioned. is doing.

[0025] In the shift register of the present invention, the second means is a second signal line that is at a high level. When the first signal line is at a low level, the second signal line outputs a low-level potential. an eleventh transistor having a function that does not have a low level when the third signal line is at a high level; When the second signal line is at a low level, the output is not generated. The inverted signal of the potential of the gate of the twelfth transistor and the second transistor is at high level. When the potential of the gate of the second transistor is inverted, the signal of the first signal line is output. A 13th transistor having a function of not outputting anything when at a low level; The transistor outputs a signal on the first signal line, and when the first signal line is at high level, the transistor goes low. The first signal line is at low level, and the thirteenth transistor is at no output. A circuit configuration including a 14th transistor having a function of not outputting anything when no input is being input. Thus, the present invention is characterized by the fact that it can be realized.

[0026] In the shift register of the present invention, in the above-mentioned configuration, the potential of the gate of the second transistor is When the voltage is high, a low-level potential is output. When the voltage of the gate of the second transistor is low, A fifteenth transistor that has the function of not outputting anything when it is at a - level, and one terminal of The other terminal is connected to the output of the 14th transistor. The present invention is characterized in that it is realized by a circuit configuration including an element having a resistance component.

[0027] In the shift register of the present invention, in the above-mentioned configuration, the element having a resistance component is diode-connected. a 16th transistor being arranged in a shift register.

[0028] The shift register of the present invention is a shift register consisting of a plurality of stages. Each stage of the transistor circuit is turned on by receiving a high-level output signal from the previous stage. A first transistor that outputs a potential of about high level, and One of the source and drain is connected to the first signal line, and the other of the source and drain is connected to the second signal line. The other of the two transistors is a second transistor connected to a first transistor in the next stage, and A low-level output signal is input from the second stage, and the second transistor operates in bootstrap mode. A fourth transistor that outputs a low-level potential to the gate of the second transistor during a period when the second transistor is not being turned on. means for supplying a voltage to the second transistor during a period when the second transistor is not performing a bootstrap operation; and a third means for outputting a low-level potential to the other of the source and drain of the transistor. It is characterized by the fact that

[0029] In the shift register of the present invention, in the above-mentioned configuration, the third means and the fourth means are the first A signal line, a second signal line, a third signal line, and an inverted signal of the potential of the gate of the second transistor It is characterized by being controlled by a signal.

[0030] In the shift register of the present invention, the second means is a second signal line that is at a high level. When the first signal line is at a low level, the second signal line outputs a low-level potential. The potential of the gate of the 17th transistor and the gate of the 2nd transistor are inverted. When the signal is at high level, the signal on the first signal line is output, and the gate of the second transistor An 18th transistor having a function of not outputting anything when the potential inversion signal is at a low level. When the inverted signal of the potential of the gate of the second transistor is at a high level, When the inverted signal of the potential of the gate of the second transistor is at a low level, A 19th transistor having a function of not outputting any signal, and a 18th transistor having a function of outputting no signal. a low-level potential is output when the first signal line is at a high level; When the first signal line is at a low level and the 18th transistor does not output anything, The 20th transistor having a function of not outputting and the 18th transistor are connected to the first signal line When the first signal line is at a high level, a low level potential is output. When the signal line is at low level and the 19th transistor does not output anything, and a 21st transistor having a function of not providing a function of ... It states that:

[0031] In the shift register of the present invention, the gate and source of the second transistor are and the other of the drains, a capacitive element is connected between the drain and the other of the drains.

[0032] In the shift register of the present invention, the gate of the first transistor is connected to the gate of the previous stage. The output signal of is input, and one of the source and drain is connected to a high-level power supply line, The other of the source and drain is connected to the gate of a second transistor. is doing.

[0033] In the shift register of the present invention, the gate of the first transistor is connected to the gate of the previous stage. The output signal of is input, and one of the source and drain is connected to a high-level power supply line, The other of the source and drain is connected to the gate of the second transistor. It states that:

[0034] In the shift register of the present invention, the gate and source of the first transistor are The output signal from the previous stage is input to one of the source and drain, and the other is It is characterized in that it is connected to the gate of the second transistor.

[0035] In the shift register of the present invention, in the above configuration, the Nth stage (N is a natural number) of the input signal is The control signal transmitted from the first signal line to the N+1th stage is The control signal and the control signal transmitted from the first signal line input to the N+2 stage are 120 degrees apart. The phase difference is

[0036] In the shift register of the present invention, in the above configuration, the Nth stage (N is a natural number) of the input signal is The control signal transmitted from the second signal line and the control signal transmitted from the second signal line input to the N+1th stage are The control signal transmitted from the second signal line input to the N+2th stage is 12 It is characterized by having a phase difference of 0 degrees.

[0037] In the shift register of the present invention, in the above configuration, the Nth stage (N is a natural number) of the input signal is The control signal transmitted from the third signal line and the control signal transmitted from the third signal line input to the N+1th stage The control signal transmitted from the third signal line input to the N+2th stage is 12 It is characterized by having a phase difference of 0 degrees.

[0038] In the shift register of the present invention, the first to twenty-first transistors are A transistor is characterized by being made of an amorphous semiconductor.

[0039] The shift register of the present invention has the above-mentioned configuration, and further comprises a first signal line, a second signal line, and At least one line is provided between the third signal line and the first to twenty-first transistors. It is characterized by having a power line.

[0040] In the shift register of the present invention, the channel region of the second transistor is It is characterized by its U-shape.

[0041] In the shift register of the present invention, the output signal of the shift register is a level shifter. It is characterized by outputting the signal via a soft circuit.

[0042] In the shift register of the present invention, in the above configuration, a control signal input to the shift register is input via a level shift circuit.

[0043] In the shift register of the present invention, in the above-mentioned configuration, multiple The switching element is turned on in sequence in a number of steps.

[0044] The display device of the present invention has the above-mentioned structure and is configured using pixels and a shift register. A gate driver, a gate signal line for transmitting an output signal of the gate driver to a pixel, and a video The pixel is driven by an output signal from a gate driver. This is characterized by selecting pixels and writing a video signal to the selected pixels.

[0045] In addition, a pixel is made up of a liquid crystal element whose transmittance changes depending on the applied voltage, and a gate signal line. a 22nd transistor that operates as a switching element that is turned on and off by the A video signal is written to the liquid crystal element through the turned-on 22nd transistor. It is characterized by being embedded in

[0046] The display device of the present invention includes a gate driver configured with a transistor using an amorphous semiconductor. The gate drivers are arranged opposite each other and drive the same gate signal line at the same timing. It is characterized by selection. Effect of the Invention

[0047] According to the present invention, during a non-selection period, a plurality of transistors that output a power supply voltage are sequentially By turning on the transistor, it is possible to eliminate the transistor that is always on. In addition, during the non-selection period, the By outputting a fixed voltage, noise can be reduced. [Brief description of the drawings]

[0048] [Figure 1] FIG. 1 is a diagram showing a first embodiment. [Diagram 2] FIG. 4 is a timing chart according to the first embodiment. [Diagram 3] FIG. 1 is a diagram showing a first embodiment. [Figure 4] FIG. 1 is a diagram showing a first embodiment. [Diagram 5] 1A to 1C are diagrams showing a second embodiment to a fourth embodiment. [Figure 6] FIG. [Figure 7] FIG. [Figure 8] FIG. 13 shows a third embodiment. [Figure 9] FIG. 13 shows a third embodiment. [Figure 10] FIG. 13 shows a third embodiment. [Figure 11] FIG. 13 is a diagram showing a fourth embodiment. [Figure 12] FIG. 13 is a diagram showing a fourth embodiment. [Figure 13] FIG. 13 is a diagram showing a fifth embodiment. [Figure 14] FIG. 13 is a diagram showing a fifth embodiment. [Figure 15] 13A and 13B are diagrams showing a fifth embodiment and a sixth embodiment. [Figure 16] 13A and 13B are diagrams showing a fifth embodiment and a sixth embodiment. [Figure 17] FIG. 13 is a diagram showing a fifth embodiment. [Figure 18] FIG. 13 is a diagram showing a fifth embodiment. [Figure 19] FIG. 13 is a diagram showing a fifth embodiment. [Figure 20] FIG. 13 is a diagram showing a fifth embodiment. [Figure 21] FIG. 13 is a diagram showing a sixth embodiment. [Figure 22] FIG. 13 is a diagram showing a sixth embodiment. [Diagram 23] FIG. 13 is a diagram showing a sixth embodiment. [Figure 24] FIG. [Diagram 25] FIG. 13 shows Example 6. [Figure 26] FIG. 13 shows Example 7. [Figure 27] FIG. 13 shows Example 8. [Figure 28] FIG. [Figure 29] FIG. [Diagram 30] FIG. [Diagram 31] FIG. 11 shows a third embodiment. [Diagram 32] FIG. 11 shows a third embodiment. [Diagram 33] FIG. 11 shows a third embodiment. [Diagram 34] FIG. 11 shows a third embodiment. [Diagram 35] FIG. 11 shows a third embodiment. [Diagram 36] FIG. 11 shows a third embodiment. [Figure 37] FIG. 11 shows a third embodiment. [Figure 38] FIG. 13 is a diagram showing a sixth embodiment. [Figure 39] FIG. 13 is a diagram showing a sixth embodiment. [Diagram 40] FIG. 13 is a diagram showing a sixth embodiment. [Diagram 41] FIG. 11 shows Example 5. [Diagram 42] FIG. 11 shows Example 5. [Diagram 43] FIG. 11 shows Example 5. [Diagram 44] FIG. 13 is a diagram showing a seventh embodiment. [Diagram 45] FIG. 13 is a diagram showing a seventh embodiment. [Figure 46] FIG. 13 is a diagram showing a sixth embodiment. [Figure 47] FIG. 13 is a diagram showing a sixth embodiment. [Figure 48] FIG. 13 shows a third embodiment. [Figure 49] FIG. 13 is a diagram showing a sixth embodiment. [Figure 50] FIG. 13 shows a third embodiment. [Figure 51] FIG. 1 is a diagram showing a first embodiment. [Figure 52] FIG. [Figure 53] FIG. 13 shows a third embodiment. [Figure 54] FIG. 13 is a diagram showing a fourth embodiment. [Figure 55] FIG. 1 is a diagram showing a first embodiment. [Figure 56] FIG. [Figure 57] FIG. 13 shows a third embodiment. [Figure 58] FIG. 13 is a diagram showing a fourth embodiment. [Figure 59] FIG. 1 is a diagram showing a first embodiment. [Figure 60] FIG. [Figure 61] FIG. 13 shows a third embodiment. [Figure 62] A third embodiment and a fourth embodiment will be described. [Figure 63] FIG. 13 is a diagram showing a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] The present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the above, and the embodiments and details thereof may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the above may be modified in various ways. The present invention should not be construed as being limited to the description of the embodiment shown in FIG.

[0050] (First embodiment) In this embodiment, in order to reduce noise in the output voltage during the non-selection period, VSS is set to The configuration and operation of a shift register circuit characterized by reducing noise by outputting This will be described with reference to FIGS.

[0051] As shown in FIG. 1, the circuit 10 includes n circuits SR(1) to SR( n) are connected in series to form a shift register circuit.

[0052] The input terminal 11 inputs a start pulse to the SR(1) of the first stage circuit 10, The circuits 10 in the second and subsequent stages have input terminals for inputting the output from the output terminal 14 of the previous stage. The input terminal 12 receives clock signals CK1 and CK2 in the first stage circuit 10, SR(1). In the circuit 10 of the third stage, SR(2) is a clock signal CK2, and in the circuit 10 of the third stage, The clock signal CK3 is input to the SR(3) in the fourth stage, and the clock signal CK1 is input to the SR(4) in the fourth stage. In other words, it is an input terminal for inputting CK1, CK2, and CK3 in that order.

[0053] The input terminal 13 is CK2 in the first stage circuit 10, which is SR(1), and CK3 in the second stage circuit 10. In the circuit 10 of the third stage, SR(3) is CK1, and in the circuit 11 of the fourth stage, SR(4) is CK2. In SR(4) on path 10, input CK1, CK2, and CK3 in that order, such as CK2. The output terminal 14 is an output terminal of the circuit 10, and is the first-stage circuit 10. In one SR(1), OUT(1) is output, and in the second stage circuit 10, SR(2), OUT(1) is output to the input terminal 11, and OUT( 2) and inputs OUT(2) to the input terminal 11 of the third stage circuit 10, SR(3). The input terminals 11 to 14 are each connected to a wiring.

[0054] Here, SSP, CK1, CK2, and CK3 have two values: High and Low. It is a 1-bit signal. Also, OUT(1), OUT(2), OUT(3), OUT(n -1), and OUT(n) are also 1-bit outputs with two values, High and Low. High is the same potential as the positive power supply VDD, and Low is the same potential as the negative power supply VSS. It is one potential.

[0055] The operation of the shift register circuit of FIG. 1 will be described with reference to the timing chart of this embodiment shown in FIG. This will be explained with reference to the above.

[0056] In FIG. 2, the SSP has a pulse width of 1 of CK1, CK2, and CK3 at any timing. CK1, CK2, and CK3 are 3-phase start pulses with a period of 1 / 3. It is a clock signal. Also, in Figure 1, when CK3 becomes High, SSP also becomes High. gh. NodeP(1) is the potential of nodeP in FIG. 3, which will be described later. OUT(1) is the output of SR(1), which is the first stage circuit 10, and OUT(2) is the output of SR(2), which is the second stage circuit 10, and OUT(3) is the output of SR(2), which is the third stage circuit 10. OUT(n-1) is the output of SR(3) in the n-1th stage of the circuit 10, SR(n −1), and OUT(n) is the output of SR(n), which is the n-th stage circuit 10.

[0057] As shown in the timing chart of FIG. 2, when SSP becomes High during period T1, During period T2, OUT(1) becomes High, and during period T3, OUT(2) becomes High. Thus, the shift register circuit is created by shifting the output of the SSP. It is composed of.

[0058] Next, the configuration of the first stage circuit 10 will be described with reference to FIG.

[0059] The circuit 10 shown in FIG. 3 includes an input terminal 11, an input terminal 12, an input terminal 13, an output terminal 14, The transistor 31, the transistor 32, the capacitance element 33, the circuit 34, and the circuit 35 are included. The input terminals 11 to 13 are connected to wiring. The input terminal 12, the input terminal 13, and the output terminal 14 are the same as those described in FIG. The transistors 31 and 32 are N-channel transistors and are amorphous. The capacitance element 33 is made of a semiconductor, a polycrystalline semiconductor, or a single crystal semiconductor. , a capacitance element having two electrodes. The circuit 34 is connected to node P when CK2 is High. When CK2 is low, the output becomes floating. The circuit 35 outputs a low signal to the output terminal 14 when CK2 is high, and This is a circuit that has the function of making the output floating when 2 is low.

[0060] The connection relationship in FIG. 3 will be described. The gate of the transistor 31 is connected to the input terminal 11. One of the source and drain is connected to VDD, and the other is connected to the capacitance One electrode of the capacitance element 33, the gate of the transistor 32, and the output terminal of the circuit 34, i.e., n Also, one of the source and drain of the transistor 32 is connected to the input The other of the source and drain is connected to the output terminal 12 of the circuit 35 and the capacitance element 3 The input terminal 13 is connected to the other terminal of the input terminal 3 and the output terminal 14. and is connected to the input terminal of the circuit 35.

[0061] Regarding the operation of FIG. 3, with reference to the timing chart of the present embodiment shown in FIG. The following will be explained in three periods: 1, T2, and T3. In the initial state, nodes P and O The potential of UT(1) is VSS.

[0062] During period T1, SSP is High, CK1 is Low, CK2 is Low, and CK3 is H. At this time, the gate potential of the transistor 31 is VDD, and the source and drain potential is The potential of one of the two is VDD, and the potential of the other of the source and drain is VSS. The transistor 31 turns on, and the potential of node P starts to rise from VSS. The potential of P rises to a potential that is smaller than VDD by the threshold voltage of transistor 31. The potential of node P at this time is Vn1. In addition, since CK2 is low, the outputs of the circuits 34 and 35 are floating. Therefore, no charge is supplied to nodeP, so it is floating. At this time, the potential of the gate of the transistor 32 is Vn1, and the potential of one of the source and drain The potential of the other of the source and drain is VSS. The transistor 32 is on. However, the potential of one of the source and drain and the potential of the source and drain are Since the potential of the other electrode is the same as that of the other electrode, and no charge moves, no current flows and the potential does not change. The capacitance element 33 does not operate at the potential VSS of the output terminal 14 and the potential of node P. The potential difference between Vn1 and Vn2 is maintained.

[0063] During period T2, SSP is Low, CK1 is High, CK2 is Low, and CK3 is L. At this time, the gate potential of the transistor 31 is VSS, and the source and drain potential is VSS. The potential of one of them is VDD, and the potential of the other of the source and drain is Vn1. The transistor 31 is turned off. The circuits 34 and 35 are turned off because the CK2 is low. Therefore, the output is floating. At this time, the potential of the gate of the transistor 32 is Vn1 The potential of one of the source and drain is VDD, and the potential of the other of the source and drain is Since the potential of the input terminal 14 becomes VSS, the transistor 32 is turned on, and the potential of the output terminal 14 The potential of the gate, source, and drain of the transistor 32 starts to rise. The capacitance element 33 connected between the other terminals maintains the potential difference maintained during the period T1. Therefore, when the potential of the other of the source and drain increases, the gate voltage also increases at the same time. At this time, the potential of nodeP is Vn2. When the potential of the output terminal 14 rises to the sum of the threshold voltage of the transistor 32 and the threshold voltage of the transistor 32, the potential of the output terminal 14 rises at the same rate as CK1. The CK1 high level is stopped by the bootstrap operation. The potential of the output terminal 14 can be increased up to VDD, which is the potential of the ground potential.

[0064] During period T3, SSP is Low, CK1 is Low, CK2 is Hight, and CK3 is At this time, the potential of node P is CK2 High and the potential of node P is CK1 High. Since VSS is output, it becomes VSS, and the potential of OUT(1) is also VSS output from circuit 35. At this time, the gate potential of the transistor 31 is VSS, and the source potential is VSS. The potential of one of the drains is VDD, and the potential of the other of the source and drain is VSS. The transistor 31 is turned off. The gate potential of the transistor 32 is Vss, and the source The potential of one of the source and drain is VSS, and the potential of the other of the source and drain is VSS. As a result, the transistor 32 is turned off.

[0065] Due to the operations in the periods T1, T2, and T3 described above, SSP is input in the period T1. In other words, when the SSP is turned on, OUT(1) is output during period T2. The shift register circuit is formed by connecting n stages of the circuit 10 which shifts the signal every n stages and outputs the signal. It is composed of.

[0066] In FIG. 3, SR(1) is shown as the first stage circuit 10, but the nth stage circuit 10 A certain SR(n) will be described with reference to FIG. 51. In FIG. 51, the transistor 31 , a transistor 32, a capacitor 33, a circuit 34, a circuit 35, an input terminal 11, and an input terminal 12. , the input terminal 13, and the output terminal 14 are the same as those described in FIG. The input signal input from 11 is connected to the output terminal 14 of the previous stage circuit 10. It is characterized by:

[0067] The gate of the transistor 31 and the other of the source and drain of the transistor 32 may be connected to a power supply line (hereinafter referred to as the "power supply line"); for example, the positive power supply VDD It may be connected to a power supply line such as the negative power supply VSS or other power supply lines, or may be connected to wiring that serves as other signal lines. The source and drain of the transistor 31 may be connected to a line (hereinafter, referred to as a "signal line"). The other of the drains may be connected to a signal line, such as CK1, CK2, CK3, SSP, etc. It may be connected to any signal line, or to other signal lines, or to other power lines.

[0068] The transistors used in the shift register circuit shown in Figure 3 are N-channel transistors. However, it may be configured with only P-channel transistors. Of course, a combination of P-channel transistors and N-channel transistors may be used. Regarding the shift register circuit when all the transistors are P-channel type transistors, This will be described with reference to FIG.

[0069] In the circuit configuration shown in Figure 55, the positive power supply VDD, the negative power supply VSS, the input terminal 11, the input terminal The terminal 12, input terminal 13, and output terminal 14 can be the same as those shown in FIG. The resistor 551 and the transistor 552 are P-channel transistors and are made of amorphous semiconductor. The capacitor 553 is made of a semiconductor material such as a polycrystalline semiconductor or a single crystal semiconductor. A circuit 554 is a capacitance element having two electrodes. When CK2 is Low, the circuit 554 outputs a high level to node P. A circuit that outputs gh and has the function of making the output floating when CK2 is High. The circuit 555 outputs a high signal to the output terminal 14 when CK2 is low. This is a circuit that has the function of making the output floating when is High.

[0070] The connection relationship in Fig. 55 will be described. The gate of the transistor 551 is connected to the input terminal 11. One of the source and drain is connected to the positive power supply VSS. The other is one electrode of a capacitor 553, a gate of a transistor 552, and an output of a circuit 554. The source and drain of transistor 552 are connected to the output terminal, i.e., node P. One of them is connected to the input terminal 12, and the other of the source and drain is connected to the output terminal of the circuit 555. The input terminal 13 is connected to the other electrode of the capacitor 553 and the output terminal 14. It is connected to the input terminal of the circuit 554 and the input terminal of the circuit 555 .

[0071] Note that the gate of the transistor 551 and the source and drain of the transistor 552 The other may be connected to a power supply line, for example, a power supply line such as a positive power supply VDD or a negative power supply VSS, or It may be connected to another power supply line or to another signal line. The other of the source and drain of C1 may be connected to a signal line, for example, CK1, CK2, C It may be connected to signal lines such as K3, SSP, or other signal lines, or to other power lines. Good too.

[0072] An example of the configuration of the circuit 554 shown in FIG. 55 will be described with reference to FIG. 59(a). As shown in the circuit 554 shown in FIG. 59(a), the input terminal 13 and node P are the same as those in FIG. The transistor 591 is a P-channel transistor and is made of an amorphous semiconductor. The semiconductor layer 11 is made of a polycrystalline semiconductor or a single crystal semiconductor.

[0073] The connection relationship in FIG. 59(a) will be described. The gate of transistor 591 is connected to input terminal 1. 3, one of the source and drain is connected to VDD, and The other one is connected to nodeP.

[0074] The operation of FIG. 59(a) will be described. When CK2 input from the input terminal 13 is Low, In this case, the transistor 591 turns on, outputting VDD to nodeP, and CK2 goes High. In the case of h, the transistor 591 is turned off and nothing is output to node P. The circuit 554 outputs High when CK2 is Low, and The circuit has a function of being floating. The configuration is not limited, and any circuit configuration having the same function may be used.

[0075] In addition, one of the source and drain of the transistor 591 may be connected to a signal line. For example, it may be connected to signal lines such as CK1, CK2, CK3, SSP, or other signal lines. Alternatively, the gate of the transistor 591 may be connected to a power supply line. For example, it may be connected to a power supply line such as a positive power supply VDD or a negative power supply VSS, or to another power supply line. Alternatively, it may be connected to another signal line.

[0076] An example of the configuration of the circuit 555 shown in FIG. 55 will be described with reference to FIG. 59(b). As shown in the circuit 555 shown in FIG. 59(b), the input terminal 13 and the output terminal 14 are the same as those in FIG. The transistor 592 is a P-channel transistor and is made of an amorphous semiconductor. The semiconductor layer 11 is made of a polycrystalline semiconductor or a single crystal semiconductor.

[0077] The operation of FIG. 59(b) will be described. When CK2 input from the input terminal 13 is Low, In this case, the transistor 592 is turned on to output VDD to the output terminal 14, and CK2 is Hi. In the case of gh, the transistor 592 is turned off and nothing is output to the output terminal 14. Thus, circuit 555 outputs High when CK2 is Low and The circuit has a function of floating. The circuit configuration is not limited, and any circuit configuration having the same function may be used.

[0078] In addition, one of the source and drain of the transistor 592 may be connected to a signal line. For example, it may be connected to signal lines such as CK1, CK2, CK3, SSP, or other signal lines. Alternatively, the gate of the transistor 592 may be connected to a power supply line. For example, it may be connected to a power supply line such as a positive power supply VDD or a negative power supply VSS, or to another power supply line. Alternatively, it may be connected to another signal line.

[0079] Next, an example of the configuration of the circuit 34 shown in FIG. 3 will be described with reference to FIG.

[0080] In the circuit 34 shown in FIG. 4(a), the input terminal 13 and node P are the same as those in FIG. The transistor 41 is an N-channel transistor, and is made of an amorphous semiconductor, a polycrystalline The semiconductor layer 11 is made of a semiconductor or a single crystal semiconductor.

[0081] The connection relationship in FIG. 4(a) will be described. The gate of the transistor 41 is connected to the input terminal 13. One of the source and drain is connected to VSS, and the other of the source and drain is connected to VSS. The other side is connected to nodeP.

[0082] The operation of FIG. 4(a) will be described. When CK2 input from the input terminal 13 is High, In this case, the transistor 41 turns on, VSS is output to the node P, and CK2 is low. In this case, the transistor 41 is turned off and nothing is output to the node P. The circuit 34 outputs a low signal when CK2 is high, and a floating state when CK2 is low. The circuit configuration is not limited to the circuit configuration described above. It is sufficient that the circuit configuration has the same function.

[0083] One of the source and drain of the transistor 41 may be connected to a signal line. For example, For example, it may be connected to signal lines such as CK1, CK2, CK3, SSP, or other signal lines. The gate of the transistor 41 may be connected to a power supply line. For example, it may be connected to a power supply line such as a positive power supply VDD or a negative power supply VSS, or to another power supply line. Alternatively, it may be connected to another signal line.

[0084] An example of the configuration of the circuit 35 shown in FIG. 3 will be described with reference to FIG.

[0085] In the circuit 35 shown in FIG. 4(b), the input terminal 13 and the output terminal 14 are the same as those in FIG. The transistor 42 is an N-channel transistor, made of an amorphous semiconductor, a multi-crystal The insulating film is made of a crystalline semiconductor or a single crystal semiconductor.

[0086] The operation of FIG. 4(b) will be described. When CK2 input from the input terminal 13 is High, In this case, the transistor 42 is turned on to output VSS to the output terminal 14, and CK2 is low. In this case, the transistor 42 is turned off and nothing is output to the output terminal 14. The circuit 35 outputs a low signal when CK2 is high, and a flow The circuit configuration is the same as the circuit configuration described above. However, any circuit configuration having the same function may be used.

[0087] In addition, one of the source and drain of the transistor 42 may be connected to a signal line. For example, it may be connected to signal lines such as CK1, CK2, CK3, SSP, or other signal lines. Of course, the source and drain of the transistor 42 may be connected to the other power supply line. One of the two is a wiring to which one of the source and drain of the transistor 41 is connected, which serves as VSS. The gate of the transistor 42 may be connected to a power supply line, for example. It may be connected to the power supply lines such as the positive power supply VDD and the negative power supply VSS, or to other power supply lines, or to other signals. It may be connected to the line.

[0088] That is, the structure shown in FIG. 3 and FIG. 4 includes a first transistor (transistor 31) and a second transistor (transistor 32). a first transistor (transistor 32), a third transistor (transistor 41), A fourth transistor (transistor 42) is provided. The first transistor has a source and a drain. One of the source and drain is connected to the first wiring (VDD), and the other of the source and drain is connected to the second wiring (VDD). The gate electrode of the second transistor and the other of the source and drain of the third transistor are connected to the gate electrode of the second transistor. The first transistor is connected to the first wiring (input terminal 11) and the gate electrode is connected to the fifth wiring (input terminal 12). One of the source and drain is connected to the third wiring (input terminal 12), and the source and drain The other of the first and second transistors is connected to the sixth wiring (output terminal 14), and the third transistor has a source One of the source and drain is connected to the second wiring (VSS), and the other of the source and drain is is connected to the gate electrode of the second transistor, and the gate electrode is connected to the fourth wiring (input terminal 13 ), and the fourth transistor has one of its source and drain connected to the second wiring (VS S), and the other of the source and drain is connected to the sixth wiring (output terminal 14). The gate electrode is connected to the fourth wiring (input terminal 13). In the transistor, one of the source and the drain is connected to the fifth wiring (input terminal 11). It is also possible to make it.

[0089] In the above shift register circuit, as CK2 becomes High, P and the output terminal 14 can be supplied with VSS. By inputting VSS every 100ms, noise can be reduced and the device can be kept on. Since there is no transistor, the deterioration of characteristics can be suppressed. Since it can operate with four transistors, the number of elements in the entire shift register circuit is This makes it possible to configure an internal circuit on an insulating substrate with a small area.

[0090] Below, some examples of possible configurations and operations of this embodiment will be described. The configuration and operation examples described are "means for solving the problems" and "best practice for carrying out the invention." This is applicable to the "Good Mode" and "Example".

[0091] As shown in FIG. 1, the clock signals CK1, CK2, and CK3 are generated when the circuit 10 is deselected. However, a switch element or the like is provided to switch the input to the circuit 10 during the non-selection period. This reduces the load on the clock signal line, which reduces power consumption. It can be made smaller.

[0092] Furthermore, in FIG. 1, the shift register circuit described above may be scanned in the opposite direction. For example, the output of the nth stage circuit 10 may be input to the n-1th stage circuit 10. It is possible to scan in the opposite direction by repeating

[0093] As shown in Figure 2, the pulse widths of SSP, CK1, CK2, and CK3 are set to 1 / 3 of the period. The pulse width may be made slightly shorter than 1 / 3 of the period. This prevents instantaneous It can effectively suppress the current that flows, can operate under a wide range of operating conditions, and has low power consumption. In addition, in a circuit configuration that performs a bootstrap operation, This is also advantageous for performing a normal bootstrap operation since the nodes are generated.

[0094] In FIG. 2, the period when SSP is high corresponds to the period when CK3 is high and the period when However, this is not limited to the above. For example, When transmitting a signal from the input to the internal circuit, a buffer circuit and a level shift circuit that changes the signal amplitude are used. This is because the delay time between control signals may change due to factors such as the above.

[0095] In FIG. 3, a capacitive element 33 is connected for bootstrap operation. A bootstrap current is applied between the gate of the transistor 32 and the other of the source and drain. If there is enough capacitance between the gate and source to operate the device, it may not be necessary. Any method for forming the third insulating film 3 may be used. For example, a capacitance element may be formed between the semiconductor layer and the gate wiring layer. Alternatively, a capacitor may be formed between the amorphous semiconductor layer and the wiring. When forming a capacitance element with a gate wiring layer, a bottom gate transistor and a top gate type Regardless of the transistor, it is small because it is formed by sandwiching a thin GI film (gate insulating film). This is advantageous since it allows for a larger capacitance value to be obtained per area.

[0096] In FIG. 3, the SSP is input to the gate of the transistor 31. If you connect the gate of 31 to either the source or drain and input SSP to it, This eliminates the need for a positive power supply VDD, reducing the number of power lines by one. Therefore, the area required for forming the shift register circuit can be reduced. It is therefore possible to provide a display device with higher resolution and narrower frame.

[0097] As described above, when CK2 is High, the circuits 34 and 35 shown in FIG. It is sufficient if the circuit outputs VSS when CK1 is low and becomes floating when CK2 is low. Also, the output of the next stage circuit 10 may be input to the input terminal of the circuit 34. The output of the next stage circuit 10 may be input to the input terminal of the 5, or the input terminal of the circuit 34, The output of the circuit 10 in the next stage may be input to the input terminal of the circuit 35. By using the output, it is possible to synchronize the actual shift register circuit rather than just the control signal. Since it can be synchronized with the output, it is possible to switch the potential to suit the operation of the shift register circuit. This is advantageous because it can be replaced.

[0098] As shown in FIG. 3, a capacitive element may be connected between nodeP and VSS or VDD. By connecting a capacitance element, the potential of nodeP can be stabilized.

[0099] In FIG. 3, the circuit 34 is not necessarily required. That is, the circuit 35 is Since VSS is output at regular intervals, even if there is noise on node P, transistor 3 This is because it is sufficient to keep 2 off. By doing this, the number of elements can be reduced. In this case, a capacitive element may be connected between nodeP and VSS or VDD.

[0100] Second embodiment In this embodiment, in order to reduce noise in the output voltage during the non-selection period, VSS is set to The configuration and operation of a shift register circuit characterized by reducing noise by outputting This will be described with reference to FIG. 2 and FIG. 5 to FIG.

[0101] As shown in FIG. 5, the circuit 50 includes n circuits SR(1) to SR( n) are connected in series to form a shift register circuit.

[0102] The input terminal 51 inputs a start pulse in the first stage circuit 50, SR(1), In the SR(2) circuit 50 after the second stage, the output from the output terminal 55 of the previous stage is input. The input terminal 52 is the input terminal of the first stage circuit 50, SR(1), which receives the clock signal. The second stage circuit 50 has clock signals CK1 and CK2 and CK3 in SR(2). The SR(3) circuit 50 in the third stage receives a clock signal CK3, and the SR(4) circuit 50 in the fourth stage receives a clock signal CK4. (4) is an input terminal that inputs clock signals in sequence, such as CK1. Input terminal 5 3 is CK2 in the first stage circuit 50, SR(1), and CK3 in the second stage circuit 50, SR(2 ) is CK3, the third stage circuit 50. SR(3) is CK1, the fourth stage circuit 50. In SR(4), the clock signal is input in sequence to the input terminal CK2. The child 54 is CK3 in the first stage circuit 50, SR(1), and SR In (2), CK1 is the third circuit 50, and in (3), CK2 is the fourth circuit 50. In one SR(4), CK3 is an input terminal that inputs a clock signal in sequence. The output terminal 55 is the output terminal of the circuit 50, and in the first stage circuit 50, SR(1), (1) is output, and OUT(1) is input to the input terminal 51 of the second stage circuit 50, SR(2). The second stage circuit 50, SR(2), outputs OUT(2), and the third stage The circuit 50 outputs OUT(2) to an input terminal 51 of SR(3).

[0103] Here, SSP, CK1, CK2 and CK3 are 1-bit clocks with two values, High and Low. High is the same potential as the positive power supply VDD, and Low is the negative The potential is the same as VSS, the power supply. Here, SSP, CK1, CK2, and CK3 are H It is a 1-bit signal with two values, Light and Low. 2), OUT(3), OUT(n-1) and OUT(n) also have two values: High and Low. It is a 1-bit output with a value. High is the same potential as the positive power supply VDD, and L ow is at the same potential as VSS, the negative power supply.

[0104] The operation of the shift register circuit in FIG. 5 will be described with reference to the timing chart of this embodiment shown in FIG. This will be explained with reference to the above.

[0105] SSP, CK1, CK2, and CK3 can be the same as those in the first embodiment. Note that nodeP(1) is the potential of nodeP in FIG. 6, which will be described later. 1) is the output of SR(1), which is the first stage circuit 50, and OUT(2) is the output of the second stage circuit 5 0 is the output of SR(2), and OUT(3) is the output of SR(3), which is the third stage circuit 50. OUT(n-1) is the output of SR(n-1), which is the n-1th stage circuit 50. OUT(n) is the output of SR(n), which is the n-th stage circuit 50.

[0106] In the timing chart of FIG. 2, when SSP becomes High during period T1, During period T2, OUT(1) becomes High, and during period T3, OUT(2) becomes High. h. In this way, a shift register circuit is constructed by shifting the output of the SSP. is doing.

[0107] Next, the configuration of the first stage circuit 50 will be described with reference to FIG.

[0108] A circuit 50 shown in FIG. 6 includes an input terminal 51, an input terminal 52, an input terminal 53, an input terminal 54, Output terminal 55, transistor 31, transistor 32, capacitance element 33, circuit 34, circuit 3 5. It is composed of input terminal 51, input terminal 52, input terminal 53, input terminal 54, output terminal 55, The input terminal 55 is the same as that described in FIG. 32 and nodeP are the same as those explained in FIG. When CK2 is low, the output is floating. The circuit 62 has a function of switching the CK2 and CK3 signals when either CK2 or CK3 is High. When CK2 and CK3 are low, the output is full. This is a circuit that has the function of loading.

[0109] The connection relationship in FIG. 6 will be described. The gate of the transistor 31 is connected to the input terminal 51. One of the source and drain is connected to VDD, and the other is connected to the capacitance One electrode of the capacitance element 33, the gate of the transistor 32, and the output terminal of the circuit 61, i.e., n The source and drain of the transistor 32 are connected to the input terminal 52, and the other of the source and drain is connected to the output terminal of the circuit 62, the capacitance element 33, and The input terminal 53 is connected to the input terminal of the circuit 61 and the output terminal 55. The input terminal 54 is connected to an input terminal of the circuit 62 .

[0110] Regarding the operation of FIG. 6, with reference to the timing chart of the present embodiment shown in FIG. The following will be explained in three periods: period T1, period T2, and period T3. The potential of OUT(1) and OUT(2) is VSS.

[0111] During period T1, SSP is High, CK1 is Low, CK2 is Low, and CK3 is H. At this time, the gate potential of the transistor 31 is VDD, and the source and drain potential is The potential of one of the two is VDD, and the potential of the other of the source and drain is VSS. The transistor 31 turns on, and the potential of node P starts to rise from VSS. The potential of P rises to a potential that is smaller than VDD by the threshold voltage of transistor 31. The potential of node P at this time is defined as Vn1. In the circuit 61, since CK2 is low, the output is floating. Since no charge is supplied to node P, the node P is floating. Since CK1 is Low and CK2 is High, the output is Low. The gate potential of the transistor 32 is Vn1, one of the source and drain potentials is VSS, and the source and drain potentials are VSS. Since the potential of the other drain is VSS, the transistor 32 is turned on. However, the potential of one of the source and drain is the same as the potential of the other of the source and drain. Since there is no movement of charge, no current flows and the potential does not change. The potential difference between VSS, which is the potential of the output terminal 55, and Vn1, which is the potential of node P, is It holds.

[0112] During period T2, SSP is Low, CK1 is High, CK2 is Low, and CK3 is L. At this time, the gate potential of the transistor 31 is VSS, and the source and drain potential is VSS. The potential of one of them is VDD, and the potential of the other of the source and drain is Vn1. The transistor 31 is turned off. In the circuit 61, the CK2 is low, so the output is In circuit 62, CK2 is low and CK3 is low, so The output is floating. At this time, the gate potential of the transistor 32 is Vn1, The potential of one of the source and drain is VDD, and the potential of the other of the source and drain, that is, the output terminal Since the potential of the output terminal 55 becomes VSS, the transistor 32 is turned on, and the potential of the output terminal 55 becomes As a result, the gate of transistor 32 and the other of the source and drain The capacitance element 33 connected between the first and second terminals maintains the potential difference maintained during the period T1. When the potential of the other of the source and drain increases, the gate voltage also increases. When the potential of nodeP is Vn2, the potential of nodeP is Vn3. If the voltage rises to the sum of the threshold voltage of CK1 and CK2, the rise in the potential of the output terminal 14 will be the same as VD D. The so-called bootstrap operation stops at the High The potential of the output terminal 55 can be increased to VDD, which is the potential of the power supply 51.

[0113] During period T3, SSP is Low, CK1 is Low, CK2 is High, and CK3 is L. At this time, the potential of nodeP is high because CK2 is high. Since VSS is output from the output terminal, it becomes VSS, and the potential of OUT(1) is also VSS from the circuit 62. At this time, the gate potential of the transistor 31 is VSS, The potential of one of the source and drain is VDD, and the potential of the other of the source and drain is VSS. The transistor 31 is turned off. The gate potential of the transistor 32 is VSS. The potential of one of the source and drain is VSS, and the potential of the other of the source and drain is VS S, and the transistor 32 is turned off.

[0114] Due to the operations in the periods T1, T2, and T3 described above, SSP is input in the period T1. In other words, when the SSP is turned on, OUT(1) is output during period T2. The shift register circuit is formed by connecting n stages of the circuit 50 which shifts the signal every n stages and outputs the signal. It is composed of.

[0115] The first stage circuit 50 shown in FIG. 6 is shown, but the nth stage circuit 50 will be described with reference to FIG. In FIG. 52, a transistor 31, a transistor 32, a capacitor 33, a circuit 61 , circuit 62, input terminal 51, input terminal 52, input terminal 53, input terminal 54, and output terminal 55 is the same as that explained in FIG. 6. The input signal inputted from the input terminal 51 is It is characterized in that it is connected to the output terminal 55 of the previous stage circuit.

[0116] The gate of the transistor 31 and the source and drain of the transistor 32 are The terminals may be connected to power supply lines, such as the positive power supply VDD, the negative power supply VSS, or other power supply lines. It may be connected to the power supply line of the transistor 31 or to another signal line. The other of the source and drain may be connected to a signal line, for example, CK1, CK2, CK3. , SSP, or other signal lines, or may be connected to other power supply lines. stomach.

[0117] The transistors used in the shift register circuit shown in Figure 6 are N-channel transistors. However, it may be configured with only P-channel transistors. Of course, a combination of P-channel transistors and N-channel transistors may be used. The figure shows a shift register circuit in which all transistors are P-channel type. Please refer to 56 for further explanation.

[0118] In the circuit configuration shown in FIG. 56, a positive power supply VDD, a negative power supply SS, an input terminal 51, an input terminal 52, an input terminal 53, an input terminal 54, a transistor 551, a transistor 552, and a capacitor The capacitance element 553 can be the same as that in FIG. 55. In the circuit 561, CK2 is Lo When w, output High to nodeP, and when CK2 is High, the output is floating. The circuit 562 is a circuit having a function of switching between CK2 and CK3. When CK2 and CK3 are HIGH, the output is High. This is a circuit that has the function of making the output floating.

[0119] The connection relationship in FIG. 56 will be described. The gate of the transistor 551 is connected to the input terminal 51. One of the source and drain is connected to the positive power supply VSS. The other is one electrode of a capacitor 553, a gate of a transistor 552, and an output terminal of a circuit 561. The source and drain of transistor 552 are connected to the output terminal, i.e., node P. One of them is connected to the input terminal 52, and the other of the source and drain is connected to the output terminal of the circuit 562. The other electrode of the capacitor 553 and the output terminal 55 are connected to the input terminal 53. The input terminal 54 is connected to an input terminal of the circuit 561 and a first input terminal of the circuit 562. The second input terminal of the first transistor of the second input terminal is connected to the second input terminal of the first transistor of the second input terminal.

[0120] The gate of the transistor 551 and the source and drain of the transistor 552 The other may be connected to a power supply line, for example, a power supply line such as a positive power supply VDD or a negative power supply VSS. It may be connected to another power supply line or to another signal line. The other of the source and drain of C1 may be connected to a signal line, for example, CK1, CK2, C It may be connected to signal lines such as K3, SSP, or other signal lines, or to other power lines. Good too.

[0121] Next, with reference to FIG. 60(a), an example of the configuration of the circuit 561 shown in FIG. do.

[0122] In the circuit 561 shown in FIG. 60(a), the input terminal 53 and node P are the same as those in FIG. The transistor 601 is a P-channel transistor, and is made of an amorphous semiconductor. The semiconductor layer 11 is made of a polycrystalline semiconductor or a single crystal semiconductor.

[0123] The connection relationship in Figure 60(a) will be described. The gate of the transistor 601 is connected to the input terminal 53, one of the source and drain is connected to VDD, and The other one is connected to nodeP.

[0124] The operation of FIG. 60(a) will be described. When CK2 input from the input terminal 53 is Low, In this case, the transistor 601 is turned on, VDD is output to the node P, and CK2 is High. In the case of h, the transistor 601 is turned off and nothing is output to node P. The circuit 561 outputs High when CK2 is Low, and The circuit has a function of being floating. The configuration is not limited, and any circuit configuration having the same function may be used.

[0125] In addition, one of the source and drain of the transistor 601 may be connected to a signal line. For example, it may be connected to signal lines such as CK1, CK2, CK3, SSP, or other signal lines. Alternatively, the gate of the transistor 601 may be connected to another power supply line. For example, it may be connected to a power supply line such as a positive power supply VDD or a negative power supply VSS, or to another power supply line. Alternatively, it may be connected to another signal line.

[0126] An example of the configuration of the circuit 562 shown in FIG. 56 will be described with reference to FIG. 60(b).

[0127] In the circuit 562 shown in FIG. 60(b), the input terminals 53 and 54 and the output terminal 55 are The transistors 602 and 603 are P-channel transistors. The semiconductor layer 11 is made of an amorphous semiconductor, a polycrystalline semiconductor, or a single crystal semiconductor.

[0128] The operation of FIG. 60(b) will be described. When CK2 input from the input terminal 53 is Low, In this case, the transistor 602 is turned on, VDD is output to the output terminal 55, and CK2 is Hi. In the case of gh, the transistor 602 is turned off and nothing is output to the output terminal 55 . When the CK3 input from the input terminal 54 is low, the transistor 603 is turned on and the output When CK3 is high, VDD is output to input terminal 55. When CK3 is high, nothing is output to output terminal 55. Thus, the circuit 562 outputs a high signal when either CK2 or CK3 is low. h, and configures a circuit that has the function of floating when it is high. In addition, the circuit configuration is not limited to the circuit configuration described above, and any circuit configuration having the same function may be used. stomach.

[0129] In addition, one of the source and drain of the transistor 592 may be connected to a signal line. For example, it may be connected to signal lines such as CK1, CK2, CK3, SSP, or other signal lines. Alternatively, the gate of the transistor 592 may be connected to a power supply line. For example, it may be connected to a power supply line such as a positive power supply VDD or a negative power supply VSS, or to another power supply line. Alternatively, it may be connected to another signal line.

[0130] Next, an example of the configuration of the circuit 61 shown in FIG. 6 will be described with reference to FIG.

[0131] As shown in the circuit 61 in FIG. 7(a), the input terminal 53 and node P are the same as those in FIG. The transistor 71 is an N-channel transistor, and is made of an amorphous semiconductor, The semiconductor layer 11 is made of a crystalline semiconductor or a single crystalline semiconductor.

[0132] The connection relationship in FIG. 7(a) will be described. The gate of the transistor 71 is connected to the input terminal 53. One of the source and drain is connected to VSS, and the other of the source and drain is connected to VSS. The other side is connected to nodeP.

[0133] The operation of FIG. 7(a) will be described. When CK2 input from the input terminal 53 is at High level, When CK2 is low, transistor 71 turns on, outputting VSS to nodeP. In this case, the transistor 71 is turned off and nothing is output to the node P. The circuit 61 outputs a low signal when CK2 is high, and a floating state when CK2 is low. The circuit configuration is not limited to the circuit configuration described above. It is sufficient that the circuit configuration has the same function.

[0134] One of the source and drain of the transistor 71 may be connected to a signal line. For example, it may be connected to signal lines such as CK1, CK2, CK3, SSP, or other signal lines. The gate of the transistor 71 may be connected to a power supply line. For example, it may be connected to a power supply line such as a positive power supply VDD or a negative power supply VSS, or to another power supply line. Alternatively, it may be connected to another signal line.

[0135] An example of the configuration of the circuit 62 shown in FIG. 6 will be described with reference to FIG.

[0136] As shown in the circuit 62 in FIG. 7(b), the input terminal 53, the input terminal 54 and the OUT(1 6. The transistors 72 and 73 are N-channel A transistor made of amorphous semiconductor, polycrystalline semiconductor, or single crystal semiconductor. It has been done.

[0137] The connection relationship in FIG. 7(b) will be described. The gate of the transistor 72 is connected to the input terminal 53. One of the source and drain is connected to VSS, and the other of the source and drain is connected to VSS. The gate of the transistor 73 is connected to the input terminal 54. One of the source and drain is connected to VSS, and the other is connected to the output. Of course, the sources of the transistors 72 and 73 are connected to the input terminal 55. One of the source and drain of the transistor 71 is connected to one of the source and drain of the transistor 72. Alternatively, it may be connected to a wiring that serves as VSS.

[0138] The operation of FIG. 7(b) will be described. When CK2 input from the input terminal 53 is at High level, In this case, the transistor 72 turns on, outputting VSS to OUT(1), and CK2 goes low. In this case, the transistor 72 is turned off and nothing is output to OUT(1). When the CK3 input from the input terminal 54 is high, the transistor 73 is turned on and When CK3 is low, transistor 73 is turned off and O Thus, the circuit 62 outputs neither CK2 nor CK3. When either of these is High, OUT(1) outputs Low, and when CK2 and CK3 are Low, The circuit has a function of floating. The circuit configuration is not limited, and any circuit configuration having the same function may be used.

[0139] In addition, one of the source and drain of the transistor 72 and the source of the transistor 73 Either the source or drain may be connected to a signal line, e.g. CK1, CK2, CK3, SSP or other signal lines, or may be connected to other power supply lines. The gate of the transistor 72 may be connected to a power supply line, for example, a positive power supply VDD or a negative power supply V It may be connected to a power supply line such as SS or other power supply line, or may be connected to other signal lines. The gate of the transistor 73 may be connected to a power supply line, for example, a positive power supply VDD, a negative power supply It may be connected to a power supply line such as the power supply VSS, or other power supply lines, or it may be connected to other signal lines. stomach.

[0140] That is, the structure shown in FIG. 6 and FIG. 7 includes a first transistor (transistor 31) and a second transistor (transistor 32). a first transistor (transistor 32), a third transistor (transistor 71), A fourth transistor (transistor 72) and a fifth transistor (transistor 73) The first transistor has a source and a drain, one of which is connected to a first wiring (VDD). the other of the source and drain is connected to the gate electrode of the second transistor and the gate of the third transistor. The gate electrode is connected to the fifth wiring (the input terminal The second transistor has one of its source and drain connected to the third wiring. (input terminal 52), and the other of the source and drain is connected to the sixth wiring (output terminal 55 ), and the third transistor has one of its source and drain connected to the second wiring (VS S), and the other of the source and drain is connected to the gate electrode of the second transistor. The gate electrode is connected to the fourth wiring (input terminal 53). One of the source and drain is connected to the second wiring (VSS), and The other terminal is connected to the sixth wiring (output terminal 55), and the gate electrode is connected to the fourth wiring (input terminal 53). ), and the fifth transistor has one of its source and drain connected to the second wiring (VS S), and the other of the source and drain is connected to the sixth wiring (output terminal 55). The gate electrode is connected to the seventh wiring (input terminal 54). In the transistor, one of the source and the drain is connected to the fifth wiring (input terminal 51). It is also possible to make it.

[0141] In the above shift register circuit, when either CK2 or CK3 goes high, In other words, during the non-selection period, By inputting VSS at regular intervals, noise can be reduced and the Since there is no transistor to be switched on, the deterioration of characteristics can be suppressed. Compared to the first embodiment, VSS is supplied to the output terminal 55 for twice the period shown in the non-selection period. Therefore, noise can be further reduced.

[0142] Below, some examples of possible configurations and operations of this embodiment will be described. The configuration and operation examples described are "means for solving the problems" and "best practice for carrying out the invention." The present invention is applicable to the "Best Mode" and "Example" and is subject to the modifications described in the first embodiment. Any of the possible configuration and operation examples can be applied to this embodiment.

[0143] As shown in FIG. 6, a capacitive element may be connected between nodeP and VSS or VDD. By connecting a capacitance element, the potential of nodeP can be stabilized.

[0144] As shown in FIG. 6, the capacitive element 33 is connected for bootstrap operation. , a bootstrap voltage is applied between the gate of the transistor 32 and the other of the source and drain. If there is a sufficient parasitic capacitance to operate, it may not be necessary. For example, a capacitance element may be formed between the amorphous semiconductor layer and the gate wiring layer. Alternatively, a capacitance element may be formed between the semiconductor layer and the wiring. When forming a capacitance element, a bottom gate transistor and a top gate transistor are used. However, because it is sandwiched between a thin GI film (gate insulating film), more This is advantageous since it allows a larger capacitance value to be obtained.

[0145] As shown in FIG. 6, the circuit 61 is not necessarily required. That is, the circuit 62 can be used to Since VSS is output at regular intervals, even if there is noise on nodeP, transistor 32 This is because it is sufficient to turn off the power supply. This makes it possible to reduce the number of elements. In this case, a capacitive element may be connected between nodeP and VSS or VDD.

[0146] The output of the next stage circuit 50 may be input to the input terminal of the circuit 62 shown in FIG. The output of the next stage circuit 50 may be input to the input terminal of the circuit 35, or the input of the circuit 61 may be input to the input terminal of the circuit 35. The output of the circuit 50 in the next stage may be input to the terminal and the input terminal of the circuit 62. By using the output of circuit 50, the actual shift register is synchronized rather than just to the control signal. Since it can be synchronized with the output of the shift register circuit, it is possible to obtain a voltage that is more suited to the operation of the shift register circuit. This is advantageous because it allows you to switch positions.

[0147] As shown in FIG. 6, a capacitive element may be connected between nodeP and VSS or VDD. By connecting a capacitance element, the potential of nodeP can be stabilized.

[0148] (Third embodiment) In this embodiment, in order to reduce noise in the output voltage during the non-selection period, V A configuration of a shift register circuit characterized by reducing noise by outputting SS; and The operation will be described with reference to FIGS. 2, 5, and 8 to 10. FIG.

[0149] The configuration and operation of the shift register circuit shown in FIG. 5 are the same as those described in the second embodiment. A variety of things can be used.

[0150] The configuration of the SR(1), which is the first stage circuit 50, will be described with reference to FIG. The circuit 50 shown includes an input terminal 51, an input terminal 52, an input terminal 53, an input terminal 54, and an output terminal 55, transistor 31, transistor 32, capacitance element 33, circuit 81, circuit 82, circuit It consists of 83.

[0151] Input terminal 51, input terminal 52, input terminal 53, input terminal 54, output terminal 55, transistor The stator 31, the transistor 32, and the capacitance element 33 are the same as those described in FIG. .

[0152] The circuit 81 outputs a low signal to node P when CK2 is high, and The circuit 82 is a circuit having a function of making the output floating when When the output is high and any of CK1, CK2, and CK3 is high, the output terminal When CK1, CK2, and CK3 are low, the output is floating. Then, when the output from the circuit 83 is Low and either CK2 or CK3 is When CK1 and CK2 are High, it outputs Low to output terminal 55. The circuit 83 has a function of making the output floating. When the voltage is close to or above VDD, a low signal is output to the circuit 82, and the voltage of node P This circuit outputs High to the circuit 82 in the case of VSS.

[0153] The connection relationship in FIG. 8 will be described. The gate of the transistor 31 is connected to the input terminal 51. One of the source and drain is connected to VDD, and the other is connected to the capacitance One electrode of the capacitance element 33, the gate of the transistor 32, the input terminal of the circuit 83, and the circuit 81 The source and drain of transistor 32 are connected to the output terminal of the One of the source and drain is connected to the input terminal 52, and the other of the source and drain is connected to the output terminal of the circuit 82. The input terminal 52 is connected to the other terminal of the capacitance element 33 and the output terminal 55. The input terminal 53 is connected to the input terminal of the circuit 81 and the input terminal of the circuit 82. The output of the circuit 83 is connected to the input terminal 54 of the circuit 82. The terminal is connected to the input terminal of the circuit 82 .

[0154] Regarding the operation of FIG. 8, with reference to the timing chart of this embodiment shown in FIG. The following will be explained in three periods: period T1, period T2, and period T3. The potential of OUT(1) and OUT(2) is VSS.

[0155] During period T1, SSP is High, CK1 is Low, CK2 is Low, and CK3 is H. At this time, the gate potential of the transistor 31 is VDD, and the source and drain potential is The potential of one of the two is VDD, and the potential of the other of the source and drain is VSS. The transistor 31 turns on, and the potential of node P starts to rise from VSS. The potential of P rises to a potential that is smaller than VDD by the threshold voltage of transistor 31. The potential of node P at this time is defined as Vn1. In the circuit 81, since CK2 is low, the output is floating. Since no charge is supplied to node P, the node P is floating. Since the potential of eP becomes Vn1, a low signal is output to the input terminal of the circuit 82. The circuit 82 The output of circuit 83 is Low, CK1 is Low, CK2 is Low, and CK3 is High. At this time, the gate potential of the transistor 32 is Vn1, and the source and drain The potential of one of the drains is VSS, and the potential of the other of the source and drain is VSS. Therefore, the transistor 32 is on. However, the potential of one of the source and drain Since the potential of the other of the source and drain is the same, and no charge moves, the current is No current flows and the potential does not change. The capacitance element 33 is connected to the potential of the output terminal 55, VSS This holds the potential difference between Vn1, which is the potential of node P.

[0156] During period T2, SSP is Low, CK1 is High, CK2 is Low, and CK3 is L. At this time, the gate potential of the transistor 31 is VSS, and the source and drain potential is VSS. The potential of one of them is VDD, and the potential of the other of the source and drain is Vn1. The transistor 31 is turned off. In the circuit 61, the CK2 is low, so the output is Since the potential of node P becomes Vn1, the input terminal of the circuit 82 The circuit 82 outputs a Low signal to the other circuit 83, and the CK1 and CK 2 is Low and CK3 is Low, so the output is floating. The gate potential of the transistor 32 is Vn1, one of the source and drain potentials is VDD, The potential of the other of the source and drain, that is, the output terminal 55, is VSS. The transistor 32 turns on, and the potential of the output terminal 55 starts to rise. The capacitance element 33 connected between the gate of the The potential difference maintained by the source and drain is maintained as is, so the potential of the other of the source and drain rises. At this time, the potential of node P is Vn2. When the potential of odeP rises to the sum of VDD and the threshold voltage of transistor 32, the output The rise in the potential of terminal 55 stops when it becomes VDD, the same as the potential of CK1. The base strap operation pulls the output terminal 55V up to VDD, which is the high potential of CK1. The potential of the electrode can be increased.

[0157] During period T3, SSP is Low, CK1 is Low, CK2 is Hight, and CK3 is At this time, the potential of node P is the same as that of the circuit 81 because CK2 is High. Since VSS is output from the The potential of OUT(1) is also VSS because the circuit 82 outputs VSS. At this time, the gate potential of the transistor 31 is VSS, and the potential of one of the source and drain The potential of the other of the source and drain is VSS. The potential of the gate of the transistor 32 is VSS, and the potential of one of the source and drain The potential of the other of the source and drain is VSS, and the potential of the transistor 3 2 is off.

[0158] Due to the operations in the periods T1, T2, and T3 described above, SSP is input in the period T1. In other words, when the SSP is turned on, OUT(1) is output during period T2. The shift register circuit is formed by connecting n stages of the circuit 50 which shifts the signal every n stages and outputs the signal. It is composed of.

[0159] The first stage circuit 50 is shown in FIG. 8, and the nth stage circuit 50 will be described with reference to FIG.

[0160] In FIG. 53, a transistor 31, a transistor 32, a capacitance element 33, a circuit 81, 82, circuit 83, input terminal 51, input terminal 52, input terminal 53, input terminal 54 and output The terminal 55 is the same as that described in FIG. The signal is characterized by being connected to the output terminal 55 of the previous stage circuit.

[0161] The transistors used in the shift register circuit shown in Figure 8 are N-channel transistors. However, it may be configured with only P-channel transistors. Of course, a combination of P-channel transistors and N-channel transistors may be used. The figure shows a shift register circuit in which all transistors are P-channel type. Please refer to 57 for further explanation.

[0162] In the circuit configuration shown in FIG. 57, a positive power supply VDD, a negative power supply SS, an input terminal 51, an input terminal 52, an input terminal 53, an input terminal 54, a transistor 551, a transistor 552, and a capacitor The capacitance element 553 can be the same as that in FIG. 55. In the circuit 571, CK2 is Lo When w, output High to nodeP, and when CK2 is High, the output is floating. The circuit 572 is a circuit having a function of switching the clock. This is a circuit that outputs a high signal to output terminal 55 when either is low.

[0163] The connection relationship in FIG. 57 will be described. The gate of the transistor 551 is connected to the input terminal 51. One of the source and drain is connected to the positive power supply VSS. The other is one electrode of the capacitor 553, the gate of the transistor 552, and the output of the circuit 571. The source and drain of transistor 552 are connected to the output terminal, i.e., node P. One of them is connected to the input terminal 52, and the other of the source and drain is connected to the output terminal of the circuit 572. The input terminal 52 is connected to the other electrode of the capacitor 553 and the output terminal 55. The input terminal 53 is connected to the input terminal of the circuit 571 and the input terminal of the circuit 572. The input terminal 54 is connected to a first input terminal of the circuit 572, and the input terminal 54 is connected to a first transistor of the circuit 572. and the second input terminal of the input terminal of the input terminal of the

[0164] Note that the gate of the transistor 551 and the source and drain of the transistor 552 The other may be connected to a power supply line, for example, a power supply line such as a positive power supply VDD or a negative power supply VSS, or It may be connected to another power supply line or to another signal line. The other of the source and drain of C1 may be connected to a signal line, for example, CK1, CK2, C It may be connected to signal lines such as K3, SSP, or other signal lines, or to other power lines. Good too.

[0165] Next, an example of the configuration of the circuit 81 shown in FIG. 8 will be described with reference to FIG.

[0166] In the circuit 81 shown in FIG. 9(a), the input terminal 53 and node P are the same as those in FIG. The transistor 91 is an N-channel transistor, and is made of an amorphous semiconductor, a polycrystalline The semiconductor layer 11 is made of a semiconductor or a single crystal semiconductor.

[0167] The connection relationship in FIG. 9(a) will be described. The gate of the transistor 91 is connected to the input terminal 53. One of the source and drain is connected to VSS, and the other of the source and drain is connected to VSS. The other side is connected to nodeP.

[0168] The operation of FIG. 9(a) will be described. When CK2 input from the input terminal 53 is at High level, When CK2 is low, transistor 91 turns on, outputting VSS to nodeP. In this case, the transistor 91 is turned off and nothing is output to the node P. Circuit 81 outputs Low when CK2 is High, and outputs Floating when CK2 is Low. The circuit configuration is not limited to the circuit configuration described above. It is not necessary to use a P-channel transistor, as long as the circuit configuration has the same function. An example of the configuration in this case is shown in Figure 61. Anyone skilled in the art can easily modify it.

[0169] One of the source and drain of the transistor 91 may be connected to a signal line. For example, it may be connected to signal lines such as CK1, CK2, CK3, SSP, or other signal lines. The gate of the transistor 91 may be connected to a power supply line. For example, it may be connected to a power supply line such as a positive power supply VDD or a negative power supply VSS, or to another power supply line. Alternatively, it may be connected to another signal line.

[0170] An example of the configuration of the circuit 82 shown in FIG. 8 will be described with reference to FIG. 9(b).

[0171] In the circuit 82 shown in FIG. 9(b), the input terminal 52, the input terminal 53, the input terminal 54, and OUT(1) is the same as in FIG. 8. Transistor 92, transistor 93, The resistor 94 and the transistor 95 are N-channel transistors, and are made of amorphous semiconductors. It is made of a crystalline semiconductor or a single crystal semiconductor. Vout is the output of the circuit 82. It is.

[0172] The connection relationship in FIG. 9B will be described. The gate of the transistor 95 is connected to Vout. One of the source and drain is connected to the input terminal 52, and one of the source and drain is connected to the input terminal 53. The other end is connected to the gate of transistor 92. The source and drain of transistor 92 One of the inputs is connected to VSS, and the other of the source and drain is connected to the output terminal 55. The gate of the transistor 93 is connected to the input terminal 53, and the source and drain of the transistor 93 are connected to the input terminal 53. One of them is connected to VSS, and the other of the source and drain is connected to the output terminal 55. The gate of the transistor 94 is connected to the input terminal 54, and one of the source and drain is connected to VSS, and the other of the source and drain is connected to an output terminal 55.

[0173] The operation of FIG. 9(b) will be described. When Vout input from the output of the circuit 83 is High, When the output is h, transistor 95 turns on and applies the CK1 signal to the gate of transistor 92. When Vout is low, transistor 95 is turned off and transistor 92 Since the CK1 signal is not transmitted to the gate of the transistor, the previous state is maintained. When the transistor 95 is turned on and the CK1 input from the input terminal 52 is high, the transistor Transistor 92 turns on and outputs VSS to OUT(1). When CK1 is low, The transistor 92 is turned off and nothing is output to OUT(1). When the CK2 input is high, transistor 93 turns on and VSS is applied to OUT(1). When CK2 is low, transistor 93 turns off and OUT(1) is not When the CK3 input from the input terminal 54 is High, the transistor When the transistor 94 is turned on, VSS is output to OUT(1), and CK3 is low, The resistor 94 is turned off and nothing is output to OUT(1). When the output of the circuit 83 is high and any of CK1, CK2, and CK3 is high, When CK1, CK2, and CK3 are low, it outputs a low signal to output terminal 55. The output from circuit 83 is low and CK2 and When either CK2 or CK3 is High, it outputs Low to output terminal 55. When 3 is low, the output becomes floating. The circuit configuration is not limited to the above-described circuit configuration, and any circuit configuration having the same function may be used.

[0174] One of the source and drain of the transistor 92 and the source and drain of the transistor 93 One of the drains of the transistor 93 and one of the source and drain of the transistor 94 are connected to a signal line. For example, the signal lines CK1, CK2, CK3, SSP, etc., or other signal lines may be connected. The source and drain of transistor 95 may be connected to the same power supply line or to another power supply line. One of the drains, the gate of transistor 92, the gate of transistor 93, The gate of 94 may be connected to a power supply line, for example, a positive power supply VDD, a negative power supply VSS, etc. It may be connected to a line, or another power line, or to another signal line.

[0175] Next, an example of the configuration of the circuit 83 shown in FIG. 8 will be described with reference to FIG.

[0176] In the circuit 83 shown in FIG. 10(a), node P and Vout are the same as those in FIG. The transistor 101 is an N-channel transistor and is made of an amorphous semiconductor or a polycrystalline semiconductor. The resistor element 102 is made of a resistor having a resistance component. Any linear or nonlinear element can be used as long as it has a resistance component. For example, a diode-connected transistor may be connected.

[0177] A configuration example in which a transistor is used as the resistance element 102 will be described with reference to FIG. Node P, Vout, transistor 101, positive power supply line VDD, and negative power supply V SS is the same as in FIG. 10. Transistor 481 is an N-channel transistor. The transistor is made of an amorphous semiconductor, a polycrystalline semiconductor, or a single crystal semiconductor. One of the source and drain of the transistor 481 is connected to the positive power supply VDD. The other input is connected to Vout, and the gate is connected to either the source or the drain. The Vout is connected to the VSS through the transistor 101 that is turned on. If no charge is supplied, the potential is VDD minus the threshold voltage of transistor 481. Thus, when node P goes low, transistor 101 turns off and the potential of Vout is the potential obtained by subtracting the threshold voltage of the transistor 481 from VDD, and node P is High. When the transistor 101 is turned on, the potential of Vout becomes the potential of VSS.

[0178] The connection relationship in Figure 10(a) will be described. The gate of the transistor 101 is connected to node P One of the source and drain of the transistor 101 is connected to one of the resistor elements 102. The other of the source and drain is connected to VSS. The other terminal of the resistance element 102 is connected to VDD.

[0179] The operation of FIG. 10(a) will be described. When the potential of node P is VSS and the transistor 10 When the voltage is equal to or greater than the sum of the threshold voltage of V and Vth, transistor 101 turns on and Vo VSS is output to ut. The potential of node P is equal to the threshold voltage of transistor 101 and VSS. If the voltage is less than the sum of the voltages, transistor 101 turns off and Vout is connected to a resistor. VDD is output through transistor 102. In this way, the potential of nodeP is VSS and the When the voltage is equal to or greater than the sum of the threshold voltage of the resistor 101 and the The voltage at node P is the sum of VSS and the threshold voltage of transistor 101. If the input terminal of the circuit 82 is lower than the threshold voltage, the circuit 82 is configured to output a high level. In addition, the circuit configuration is not limited to the circuit configuration described above, and any circuit configuration having the same function may be used. FIG. 62 shows the circuit configuration of FIG. 10 when P-channel transistors are used. Here is an example.

[0180] The other of the source and drain of the transistor 101 may be connected to a signal line. For example, it may be connected to signal lines such as CK1, CK2, CK3, SSP, or other signal lines. Alternatively, the gate of the transistor 101 may be connected to another power supply line. For example, it may be connected to a power supply line such as a positive power supply VDD or a negative power supply VSS, or to another power supply line. Alternatively, it may be connected to another signal line.

[0181] Another example of the configuration of the circuit 83 shown in FIG. 8 will be described with reference to FIG. 10(b).

[0182] As shown in the circuit 83 in FIG. 10(b), node P and Vout are the same as those in FIG. OUT(2) is the output of the next second stage circuit 50. For example, In this case, it is the output of the (n+1)th stage circuit 50. 103 is an N-channel transistor, and is made of an amorphous semiconductor, a polycrystalline semiconductor, or a single crystal The capacitor 104 is made of a crystalline semiconductor. .

[0183] The connection relationship in FIG. 10(b) will be described. The gate of the transistor 102 is OUT(2 ) and one of the source and drain is connected to VDD. The other is one of the source and drain of the transistor 103 and one of the potentials of the capacitor element 104. The gate of the transistor 103 is connected to node P, the source is connected to node Vout, and the The other electrode of the capacitor 104 is connected to VSS. and is connected.

[0184] The operation of FIG. 10(b) will be described. When the potential of node P is VSS and the transistor 10 When the voltage is equal to or greater than the sum of the threshold voltages of transistors 103 and 104, transistor 103 turns on and VSS The potential of node P is VSS and the threshold voltage of the transistor 103. If the voltage is less than the sum of When OUT2 is high, transistor 102 turns on and Vout is Outputs the difference between DD and the threshold voltage of transistor 102. OUT2 is Low. When this occurs, the transistor 102 turns off and the output becomes floating. When the potential of deP is close to VDD or higher, Vout outputs Low. When the potential of nodeP is VSS, Vout has the function of outputting High. In addition, the circuit configuration is not limited to the circuit configuration described above, and any circuit having the same function may be used. Any path configuration is acceptable.

[0185] The gates of the transistors 102 and 103 are connected to the power supply line. For example, it may be connected to a power supply line such as a positive power supply VDD or a negative power supply VSS, or to another power supply line. Alternatively, the source and drain of the transistor 103 may be connected to another signal line. The other of the two may be connected to a signal line, for example, CK1, CK2, CK3, SSP, etc. The power supply line may be connected to the power supply line or another signal line.

[0186] In the above-described shift register circuit, CK1, CK2 and C If any of K3 goes high, VSS can be supplied to output terminal 55. In other words, VSS is constantly supplied to the output terminal 55 during the non-selection period, so the potential is stable, noise can be eliminated, and there is no transistor that is constantly on. This can prevent the characteristics from deteriorating. Also, VSS is periodically applied to node P. By supplying a voltage Vcc to the transistor 32, the transistor 32 can be reliably turned off.

[0187] Below, some examples of possible configurations and operations of this embodiment will be described. The configuration and operation examples described are "means for solving the problems" and "best practice for carrying out the invention." The present invention is applicable to the "Best Mode" and "Example" and is subject to the modifications described in the first embodiment. Any of the possible configuration and operation examples can be applied to this embodiment.

[0188] As shown in FIG. 9, the gate of transistor 92 is floating when transistor 95 is off. Therefore, the potential is held in the gate capacitance of the transistor 92, but it cannot be held. If not, a capacitance element may be connected. In that case, the gate of the transistor 92 and VDD , or VSS.

[0189] As shown in FIG. 10(b), a capacitance element 104 is connected to Vout. If the connection destination has sufficient capacity, it may not be provided. By eliminating the connected capacitor element 104, higher speed operation is possible.

[0190] As shown in FIG. 10(b), the gate of the transistor 103 is connected to node P. However, the input terminal 51 may be connected. By connecting the input terminal 51, The period during which the transistor 102 and the transistor 103 are simultaneously on is eliminated, and the transistor 10 2, and since the through current through the transistor 103 is eliminated, malfunctions are less likely to occur, and This reduces power consumption.

[0191] (Fourth embodiment) In this embodiment, in order to reduce noise in the output voltage during the non-selection period, VSS is set to The configuration and operation of a shift register circuit characterized by reducing noise by outputting This will be described with reference to FIGS. 2, 5, 11 and 12.

[0192] The configuration and operation of the shift register circuit shown in FIG. 5 are the same as those described in the second embodiment. A variety of things can be used.

[0193] The configuration of the SR(1), which is the first stage circuit 50, will be described with reference to FIG. The circuit shown in FIG. 1 includes an input terminal 51, an input terminal 52, an input terminal 53, an input terminal 54, and an output terminal 55, transistor 31, transistor 32, capacitance element 33, circuit 111, circuit 82, circuit 83. Input terminal 51, input terminal 52, input terminal 53, input terminal 54 , output terminal 55, circuit 82, circuit 83, transistor 31, transistor 32, capacitance element 33, and nodeP are the same as those explained in FIG.

[0194] The circuit 111 is connected to the CK1, CK2 and CK3 when the output from the circuit 83 is high. When any of the following is High, CK1, CK2, and CK3 are output to nodeP. When the output from the circuit 83 is low, the output is floating. When CK2 is High, it outputs Low to nodeP. When CK2 is Low, When the input voltage is too high, the output becomes floating.

[0195] The connection relationship will be described with reference to FIG. 11. The gate of the transistor 31 is connected to the input terminal 51. One of the source and drain is connected to VDD, and the other is connected to the capacitance One electrode of the capacitance element 33, the gate of the transistor 32, the input terminal of the circuit 83, and the circuit 11 The source and drain of transistor 32 are connected to the output terminal of transistor 1, i.e., node P. One of the inputs is connected to the input terminal 52, and the other of the source and drain is connected to the output of the circuit 82. The input terminal 52 is connected to the other electrode of the capacitance element 33 and the output terminal 55. The input terminal 53 is connected to the input terminal of the circuit 82 and the input terminal of the circuit 111. The input terminal 54 is connected to the input terminal of the circuit 82 and the input terminal of the circuit 111. The output terminal of the circuit 83 is connected to the input terminal of the circuit 82, and the output terminal of the circuit 84 is connected to the input terminal of the circuit 111. It is connected to the input terminal of the circuit 111 .

[0196] Regarding the operation of FIG. 11, with reference to the timing chart of this embodiment shown in FIG. The following description will be given for periods T1, T2, and T3. And the potential of OUT(1) is VSS.

[0197] During period T1, SSP is High, CK1 is Low, CK2 is Low, and CK3 is H. At this time, the gate potential of the transistor 31 is VDD, and the source and drain potential is The potential of one of the two is VDD, and the potential of the other of the source and drain is VSS. The transistor 31 turns on, and the potential of node P starts to rise from VSS. The potential of P rises to a potential that is smaller than VDD by the threshold voltage of transistor 31. The potential of node P at this time is defined as Vn1. Since the potential of node P of the circuit 83 is Vn1, the input terminal of the circuit 82 and the The circuit 111 outputs a low signal to the input terminal of the circuit 83. Since CK2 is low and CK3 is high, the output is floating. 82 is when the output of circuit 83 is Low, CK1 is Low, CK2 is Low, and CK3 is High. Therefore, a low signal is output to the output terminal 55. The potential difference between VSS, which is the potential of node P, and Vn1, which is the potential of node P, is maintained.

[0198] During period T2, SSP is Low, CK1 is High, CK2 is Low, and CK3 is L. At this time, the gate potential of the transistor 31 is VSS, and the source and drain potential is VSS. The potential of one of them is VDD, and the potential of the other of the source and drain is Vn1. The transistor 31 is turned off. In the circuit 83, the potential of the node P becomes Vn1, so that the circuit 82 The circuit 111 outputs a low signal to the input terminal of the circuit 83 and the input terminal of the circuit 111. Since the input is Low, CK1 is High, CK2 is Low, and CK3 is Low, the output is The output of the circuit 82 is Low, the output of the circuit 83 is High, and the output of the CK2 is Low. Since CK3 is low and CK4 is low, the output is floating. The gate potential of the transistor 32 is Vn1, one of the source and drain potentials is VDD, The potential of the other of the drain and the drain, that is, the output terminal 55, is VSS. The transistor 32 turns on, and the potential of the output terminal 55 starts to rise. The capacitance element 33 connected between the gate and the other of the source and drain is In order to maintain the potential difference, the potential of the other of the source and drain increases. At this time, the potential of node P is Vn2. When the potential of odeP rises to the sum of VDD and the threshold voltage of transistor 32, the output The rise in the potential of terminal 55 stops when it becomes the same VDD as CK1. The trap operation causes the potential of output terminal 55 to rise to VDD, which is the high potential of CK1. can rise.

[0199] During period T3, SSP is Low, CK1 is Low, CK2 is Hight, and CK3 is At this time, the potential of node P is the same as that of the circuit 11 because CK2 is High. Since VSS is output from 1, it becomes VSS, and the circuit 83 outputs a High signal to the input terminal of the circuit 82. h is output. The potential of OUT(1) is also VSS because the circuit 82 outputs VSS. At this time, the gate potential of the transistor 31 is VSS, and one of the source and drain potentials is The potential of the other of the source and drain is VSS. The potential of the gate of the transistor 32 is VSS, and the potential of one of the source and drain is VSS. The potential of the transistor is VSS, and the potential of the other of the source and drain is VSS. 32 is off.

[0200] Due to the operations in the periods T1, T2, and T3 described above, SSP is input in the period T1. In other words, when the SSP is turned on, OUT(1) is output during period T2. The shift register circuit is formed by connecting n stages of the circuit 50 which shifts the signal every n stages and outputs the signal. It is composed of.

[0201] The transistors used in the shift register circuit shown in Figure 11 are N-channel transistors. Although the circuit was previously constructed using only P-channel transistors, it may be constructed using only P-channel transistors. Of course, P-channel and N-channel transistors can be combined. In a shift register circuit where all transistors are P-channel transistors, This will be described with reference to FIG.

[0202] In the circuit configuration shown in FIG. 58, a positive power supply VDD, a negative power supply VSS, an input terminal 51, an input terminal input terminal 52, input terminal 53, input terminal 54, transistor 551, transistor 552, and The capacitor 553 can be the same as that in FIG. 55. The same as that in FIG. 57 can be used. Circuit 581 is one of CK1, CK2, and CK3. This is a circuit that outputs High to output terminal 55 when either one is Low.

[0203] The connection relationship in Fig. 58 will be described. The gate of the transistor 551 is connected to the input terminal 51. One of the source and drain is connected to the positive power supply VSS. The other is one electrode of the capacitor 553, the gate of the transistor 552, and the output of the circuit 581. The source and drain of transistor 552 are connected to the output terminal, i.e., node P. One of them is connected to the input terminal 52, and the other of the source and drain is connected to the output terminal of the circuit 572. The input terminal 52 is connected to the other electrode of the capacitor 553 and the output terminal 55. The input terminal 53 is connected to the input terminal of the circuit 581 and the input terminal of the circuit 572. The input terminal 54 is connected to the first input terminal of the first transistor of the circuit 562. and the second input terminal of the input terminal of the input terminal of the

[0204] The gate of the transistor 551 and the source and drain of the transistor 552 The other may be connected to a power supply line, for example, a power supply line such as a positive power supply VDD or a negative power supply VSS, or may be connected to another power supply line or to another signal line. The other of the source and drain of 51 may be connected to a signal line, for example, CK1, CK2, It may be connected to signal lines such as CK3, SSP, or other signal lines, or to other power lines. This is also fine.

[0205] The first stage circuit 50 shown in FIG. 11 is shown, but for the nth stage circuit 56, see FIG. 54. In FIG. 54, a transistor 31, a transistor 32, a capacitance element 33, Circuit 111, circuit 82, circuit 83, input terminal 51, input terminal 52, input terminal 53, input terminal The input terminal 51 and the output terminal 55 are the same as those described in FIG. The input signal input from the input stage is connected to the output terminal 55 of the previous stage circuit. .

[0206] Next, an example of the configuration of the circuit 111 shown in FIG. 11 will be described with reference to FIG.

[0207] As shown in the circuit 111 shown in FIG. 5 and 11. Transistor 121, transistor The transistor 122, the transistor 123, the transistor 124, and the transistor 125 are N-channel It is a transistor made of amorphous semiconductor, polycrystalline semiconductor, or single crystal semiconductor. Vout is the output of the circuit 111.

[0208] The connection relationship in FIG. 12 will be described. The gate of the transistor 124 is connected to Vout. One of the source and drain of the transistor 124 is connected to the input terminal 52. The other of the gate and drain is connected to the gate of transistor 121. One of the source and drain of 21 is connected to VSS, and the other The gate of the transistor 122 is connected to the input terminal 53. One of the source and drain is connected to VSS, and the other is connected to nod The gate of the transistor 125 is connected to Vout, and the source and drain of the transistor 125 are connected to Vout. One of the drains is connected to the input terminal 54, and the other of the source and drain is connected to the transistor The gate of the transistor 123 is connected to one of the source and drain of the transistor 123. is connected to VSS, and the other of the source and drain is connected to nodeP.

[0209] The operation of FIG. 12 will be described. When Vout input from the output of the circuit 83 is High, In this case, the transistors 124 and 125 are turned on, and the transistor 121 The CK1 signal is transmitted to the gate of the transistor 123, and the CK3 signal is transmitted to the gate of the transistor 124. When Vout is low, transistor 124 and transistor 125 are off. However, since the CK1 signal is not transmitted to the gate of transistor 121, the previous state is maintained. Therefore, the CK3 signal is not transmitted to the gate of transistor 123, so the previous state is maintained. At this time, the transistor 124 is turned on, and the CK1 input from the input terminal 52 is When is High, the transistor 121 turns on and outputs VSS to node P, When K1 is low, transistor 121 is turned off and nothing is output to nodeP. When the CK2 input from the input terminal 53 is High, the transistor 122 is turned on. When CK2 is low, transistor 122 outputs VSS to nodeP. The transistor 125 is turned on and the input When the CK3 input from the input terminal 54 is High, the transistor 123 is turned on. When VSS is output to nodeP and CK3 is low, transistor 123 is turned off. , nothing is output to node P. Thus, the circuit 111 operates when the output of the circuit 83 is Hi. gh and any of CK1, CK2, and CK3 are High, When CK1, CK2, and CK3 are low, the output is floating. When the output from the circuit 83 is Low and CK2 is High, the output terminal 55, and when CK2 is low, the output becomes floating. In addition, the circuit configuration is not limited to the circuit configuration described above, and may be any circuit having the same function. Any circuit configuration is acceptable. Also, FIG. 63 shows an example of a configuration using a P-channel transistor. There are.

[0210] The other of the source and drain of the transistor 124 and the gate of transistor 122, and one of the source and drain of transistor 125 On the other hand, the gate of the transistor 123 may be connected to a signal line, for example, CK1, CK 2, CK3, SSP, or other signal lines, or other power supply lines. The other of the source and drain of the transistor 121 may be connected to the transistor The other of the source and drain of transistor 122 and the source and drain of transistor 123 The other may be connected to a signal line, for example, CK1, CK2, CK3, SSP, etc. , or may be connected to another signal line, or may be connected to another power supply line.

[0211] In the above-described shift register circuit, CK1, CK2 and C If any of K3 is high, VSS is supplied to output terminal 55 and node P. In other words, the output terminal 55 and node P are always connected during the non-selection period. Because VSS is supplied, the potential is stable, noise is eliminated, and the Since there is no transistor that is turned on, deterioration of characteristics can be suppressed.

[0212] Below, some examples of possible configurations and operations of this embodiment will be described. The configuration and operation examples described are "means for solving the problems" and "best practice for carrying out the invention." The present invention is applicable to the "Best Mode" and "Example" and is subject to the modifications described in the first embodiment. Any of the possible configuration and operation examples can be applied to this embodiment.

[0213] As shown in FIG. 12, a signal input to the gate of a transistor 121 is The signal input to the gate of transistor 92 may be the same as that input to the gate of transistor 93. The number of registers can be reduced.

[0214] As shown in FIG. 12, the gate of transistor 121 is in a low-state when transistor 124 is off. Therefore, the gate capacitance of the transistor 121 holds a potential, but the If the load is too large, a capacitance element may be connected. It is advisable to connect a capacitance element between this pin and VDD or VSS.

[0215] As shown in FIG. 12, the gate of transistor 123 is in a low-state when transistor 125 is off. Therefore, the potential is held in the gate capacitance of the transistor 123. If the load is too large, a capacitance element may be connected. It is advisable to connect a capacitance element between this pin and VDD or VSS.

[0216] Fifth embodiment In this embodiment, the shift register circuit described in the first to fourth embodiments is Some examples of circuit configurations when using this will be described below.

[0217] The pixels are scanned by the shift register circuit described in the first to fourth embodiments. An example of the configuration of a gate driver for this purpose will be described with reference to FIG. The timing chart is shown in Figure 14.

[0218] The gate driver circuit shown in FIG. 13 is the same as that described in the first to fourth embodiments. The gate signal lines G1 to G2 are connected to the gate signal The output signal OUT1 is output from the shift register circuit 131 via the signal line Gn. to OUTn are transmitted to the pixels as gate signals.

[0219] The shift register circuit 131 receives control signals SSP, CK1, CK2, and CK3. The timing is the same as in the first to fourth embodiments as shown in FIG. In addition, the positive power supply VDD and the negative power supply VSS are input as power supplies. The amplitude voltage of the control signal corresponds to the positive power supply VDD and the negative power supply VSS. As shown in FIG. 14, when SSP is input, OUT1 is selected in order (hereinafter, the scanning In this way, the output of the shift register circuit 131 is directly used as a gate signal. , and output to gate signal lines G1 to Gn.

[0220] Here, the potential of the positive power supply VDD is set higher than the maximum value of the pixel video signal, which will be described later. It is desirable to keep the potential of the negative power supply VSS lower than the minimum value of the video signal. This allows the video signal to be written to the pixels reliably, resulting in a display device with higher image quality. can be provided.

[0221] The gate driver described in FIG. 13 directly connects the output of the shift register circuit 131 to the gate. This allows the surface area of ​​the gate driver to be This is advantageous because the product is smaller. Also, the number of elements in the gate driver is reduced. This is advantageous since it can increase the yield.

[0222] The amplitude voltage of the output signal of the shift register circuit described in the first to fourth embodiments A gate driver that scans pixels by changing the voltage will be described with reference to FIG. Moreover, the timing chart at that time is shown in FIG.

[0223] The gate driver circuit shown in FIG. 15 is the same as that described in the first to fourth embodiments. The gate resistor circuit 151 and the level shift circuit 152 are included. The signals are output from the shift register circuit 151 via the gate signal lines G1 to Gn. The output signals OUT1 to OUTn are converted into gate signals via a level shift circuit 152. and transmits it to the pixel.

[0224] The level shift circuit 152 shown in FIG. 15 will be described with reference to FIGS. Also, the level shift circuit described in FIG. 50 is only the level shift circuit 152 shown in FIG. The present invention may be applied to other figures, best modes for carrying out the invention, and examples. do.

[0225] As shown in FIG. 50(a), the output OUT( n), and the power supply VDDH and negative power supply VSS, which have a higher potential than the maximum amplitude voltage of OUT(n). The semiconductor device includes at least a resistor element 502 including a resistance component and a transistor 501. The gate of the transistor 501 is connected to OUT(n), and one of the source and drain is connected to a negative The other of the source and drain is connected to one terminal of the resistor element 502. The other terminal of the resistor element 502 is connected to a power supply VDDH. The level shift circuit is characterized in that

[0226] As shown in FIG. 50(b), the output OUT( n), and the power supply VDDH and negative power supply VSS, which have a higher potential than the maximum amplitude voltage of OUT(n). The transistor 503, the transistor 504, and the inverter circuit 505 are included. The gate of the transistor 504 receives the signal OUT(n), and the gate of the transistor 503 receives the signal OUT(n). The gate receives OUT(n) through an inverter circuit 505 and inverts it to OUT(n). One of the source and drain of the transistor 504 is connected to the negative power supply VSS. One of the source and drain of the transistor 503 is connected to the power supply VDD. The other of the source and drain of the transistor 504 and the source and drain of the transistor 505 a level shift circuit, the other of the drains being connected to a gate signal line; It is.

[0227] The shift register circuit 151 receives control signals SSP, CK1, CK2, and CK3. The timing is the same as in the first to fourth embodiments as shown in FIG. In addition, the positive power supply VDD and the negative power supply VSS are input as power supplies, and the control The signal amplitude voltage corresponds to the positive power supply VDD and the negative power supply VSS. When SSP is input as shown in 6, OUT1 is selected in order (as follows, In this way, the output of the shift register circuit 151 is input to the level shift circuit 152. In this case, the amplitude of the output signal from the shift register circuit 151 is H igh is the potential of the positive power supply VDD, and Low is the potential of the negative power supply VSS.

[0228] The level shift circuit 152 receives the amplitude voltage of the output signal of the shift register circuit 151. For example, when a high signal is input, the potential of the positive power supply VDD changes to the positive The potential of the power supply VDDH. When a low is input, the potential of the negative power supply VSS changes to the negative power supply VSSL. The potential of the positive power supply VDDH is set to the potential of the positive power supply VDD. The potential of the negative power supply VSSL is higher than the potential of the negative power supply VSS. Also, only the High amplitude voltage may be changed, or only the Low amplitude voltage may be changed. This is also fine.

[0229] Here, the potential of the positive power supply VDDH is set to a value less than the maximum value of the video signal input to the pixel, which will be described later. It is desirable to keep the potential of the negative power supply VSS lower than the minimum value of the video signal. This ensures that the video signal is written to the pixels reliably, resulting in higher quality images. A display device can be provided.

[0230] The gate driver described in FIG. 15 level-shifts the output signal of the shift register circuit 151. The amplitude voltage is changed by passing the signal through a soft circuit 152 and output to the gate signal line. In this way, the shift register circuit 151 generates a control signal having a small amplitude voltage, This is advantageous because it can be driven by a single power source and consumes less power.

[0231] A control signal input to the shift register circuit described in the first to fourth embodiments This paper describes a type of gate driver that inputs the voltage to a shift register circuit via a level shift circuit. This will be described with reference to Fig. 17. The timing chart at that time is shown in Fig. 18.

[0232] The gate driver circuit shown in FIG. 17 is the same as that described in the first to fourth embodiments. The input terminal 171 is configured with a level shift circuit 172. The signals are output from the shift register circuit 151 via the gate signal lines G1 to Gn. The output signals OUT1 to OUTn are transmitted to the pixels as gate signals.

[0233] The level shift circuit 172 is a circuit for changing the amplitude voltage of the input signal. For example, the high potential of the input signal is set to a positive power supply, which is the power supply for the shift register circuit 171. The potential of the low side can be changed to the potential of the negative power supply VSS. In the case of 17, the control signals SSP, CK1, CK2 and The CK3 amplitude voltage can be changed to an amplitude voltage corresponding to the positive power supply VDD and the negative power supply VSS. In other words, the amplitude of the control signal is small, for example, the amplitude of the existing external circuit, The amplitude voltage of the control signal is shifted to the positive power supply VDD and the negative power supply VS through the level shift circuit 172. The amplitude voltage corresponding to S can be converted and input to the shift register circuit 171. By doing so, the gate driver shown in FIG. 17 can be driven regardless of the amplitude voltage of the external circuit. This eliminates the need to develop new external circuits, and reduces the cost of the display device. This is advantageous because

[0234] The shift register circuit 171 has an amplitude voltage corresponding to the positive power supply VDD and the negative power supply VSS. The voltage-changed SSP, CK1, CK2 and CK3 are input, and the timing is as shown in Figure 1. As shown in FIG. 8, the power supply is the same as that of the first to fourth embodiments. The positive power supply VDD and the negative power supply VSS are input. As shown in Figure 18, SSP is input. When the shift register circuit 171 is turned on, the output is selected from OUT1. The gate signals are output to the gate signal lines G1 to Gn as they are. The port signals are scanned in sequence.

[0235] Here, the potential of the positive power supply VDD is set to a value lower than the maximum value of the video signal input to the pixel, which will be described later. It is desirable to set the potential of the negative power supply VSS higher than the minimum value of the video signal. This ensures that the video signal is written to the pixels reliably, resulting in a higher quality display. A display device can be provided.

[0236] The source driver using the shift register circuit described in the first to fourth embodiments The driver circuit will be described with reference to FIG. 19. The timing chart is shown in FIG. .

[0237] The source driver circuit shown in FIG. 19 is the same as that described in the first to fourth embodiments. The shift register circuit 191 and the switching element 192 are included. The output signal of the resistor circuit 191 controls the switches 192 from SW1 to SWm in the first row. One terminal of the switch 192 is a video signal The other terminal of the switch 192 is connected to the source signal line. When the switching element 192 is turned on, a video signal can be output to the source signal line. As shown in Figure 20, the video signal changes according to the source signal line of the column that is turned on, so all columns Any video signal can be output to the source signal line. It is connected to the pixels so that a video signal can be transmitted to the pixels.

[0238] Here, the output signal of the shift register circuit 192 is the same as that of the first to fourth embodiments. As explained above, it is a 1-bit signal with High and Low, and the High potential is the positive power supply. The potential of VDD and the potential of Low are the potential of the negative power supply VSS. 2 is controlled by the output of the shift register circuit 191, so the potential of the positive power supply VDD The potential of the negative power supply VSS reliably turns on and off the switching element 192 regardless of the video signal. In other words, the potential of the positive power supply VDD must be set to a level that is equal to the potential of the video signal. Set the potential of the negative power supply VSS lower than the minimum value of the video signal potential. It is also desirable that the control signal input to the shift register circuit 191 be a positive voltage. The amplitude of the voltage must correspond to the potential of the power supply VDD and the potential of the negative power supply VSS.

[0239] It is desirable to configure the switching element 192 using an N-channel transistor. The gate of the N-channel transistor is connected to the output of the shift register circuit 191. Connect one of the source and drain to the video signal line, and connect the other of the source and drain to the In this way, when the output of the shift register circuit 191 is High, When it is low, it turns on the N-channel transistor. By configuring the switching element 192 with an N-channel transistor, This makes it possible to form a transistor using amorphous silicon. , a shift register circuit composed only of N-channel transistors and a switching element 19 This is advantageous because the pixel section and the pixel portion can be constructed on the same substrate.

[0240] In addition, in the present invention, there is no limitation on the type of transistor that can be used as a switching element. The transistor uses a non-single crystal semiconductor film, typically made of amorphous silicon or polycrystalline silicon. transistors, MOS transistors formed using semiconductor substrates or SOI substrates, junction transistors, transistors, bipolar transistors, transistors using organic semiconductors and carbon nanotubes A transistor, a transistor having a capacitance of 100 nm ... There is no limitation on the type of substrate to be used, and it may be a single crystal substrate, an SOI substrate, a quartz substrate, a glass substrate, or a resin substrate. etc. can be used freely.

[0241] Since transistors are simply used as switching elements, the polarity (conductivity type) is not important. There is no limitation, and either N-type or P-type transistors are acceptable. However, When a low current is desired, it is preferable to use a transistor with low off-state current. As a transistor with a low off-state current, a transistor having a channel formation region and a source region or Between the drain region and the gate electrode, there is a region where impurity elements that give a low concentration of conductivity are added (LDD region). There are transistors that have a gate insulating layer.

[0242] In addition, when the transistor operates with the source potential close to the low-potential power supply, The transistor is preferably an N-type transistor. For operation close to the top supply, the transistor is preferably P-type. By using this configuration, the absolute value of the voltage between the gate and source of the transistor is Since the N-type transistor can be made large, it is easy to operate the transistor as a switch. It can also be used as a CMOS switching element by using both P-type and P-type transistors. good.

[0243] Although there is one video signal line in FIG. 19, there may be multiple video signal lines. For example, if there are two video signal lines, the output signal of the shift register circuit 191 and controls the switching elements 192 to transmit different video signals to the respective switching elements 192. In this way, two switching elements 192 are turned on at the same time, and another video In other words, the same number of source signal lines can be used to output the same signal to different source signal lines. If there is a shift register, the number of stages of the shift register circuit 191 can be halved. This is advantageous because the area required for forming the circuit 191 can be reduced. The number of elements will also be reduced, which is expected to lead to improved yields.

[0244] As shown in FIG. 19, the output of a shift register circuit 191 and a switching element 192 A level shift circuit may be added between the two. In this way, the shift register circuit 191 The output of the shift register circuit 191 is shifted by a level shift circuit. The signal can be amplified and input to the switching element 192. By operating the start circuit 191 with a small amplitude voltage, power consumption can be reduced. Then, the output signal of the shift register circuit 191 is switched through a level shift circuit. By inputting this to the gate element 192, the amplitude voltage can be made larger than that of the video signal.

[0245] As shown in FIG. 19, the control signal input to the shift register circuit 191 is a level shift circuit. In this way, the display device of the present invention can be operated using an existing external circuit. In addition, a level shift circuit can be provided to the output of the shift register circuit 191. The paths may be connected.

[0246] Sixth embodiment In this embodiment, the shift register circuit described in the first to fourth embodiments is used. We will explain some examples of display device configurations using the gate driver and source driver. Reveal.

[0247] The shift register circuits described in the first to fourth embodiments are used as gate drivers. A configuration example of a display device when used as a control signal will be described with reference to FIG. Although signal lines, power lines, counter electrodes, etc. are not shown, they can be added as necessary. Gate drivers can also be added as necessary. The driver may be the gate driver described in the fifth embodiment.

[0248] The display device shown in FIG. 21 includes a gate driver 212, pixels 211, gate signal lines G1, The gate signal line Gn, the source signal line S1, and the source signal line Sm are included. A gate signal line for transmitting a gate signal which is an output of the gate driver 212 and a gate signal line for transmitting a gate signal from an external circuit The pixels 211 are controlled by source signal lines for transmitting video signals. do.

[0249] The pixel 211 has a display element such as a liquid crystal element, a light emitting element such as an FED element or an EL element, The switching elements, transistors, and video signals to control them It may include a capacitance element for holding a threshold voltage.

[0250] The gate driver 212 outputs a gate signal that selects which pixel 211 to write the video signal to. When selecting to write a video signal, The gate signal line G1 to the gate signal line Gn are selected in sequence. The amplitude voltage reached is an amplitude voltage greater than the maximum and minimum potentials of the video signal. If the video signal is a current, the buffer is determined by the current flow. It is desirable to set the amplitude voltage to be larger than the maximum and minimum values ​​of the potential of the source signal line. In addition, when a gate signal line is selected, a High signal is output from the gate driver 212. Yes, it outputs low when the gate signal line is not selected.

[0251] The source signal lines S1 to Sm are connected to the pixels via a video signal input from an external circuit. The video signal may be input as an analog signal. The input may be a digital signal, a current, or a voltage. Also, a source driver that outputs a video signal is formed as an internal circuit, and the source driver The output of the video signal input to the source signal line may be output to the source signal line. The video signals may be inputted in a line-sequential manner, in which all the columns are simultaneously transmitted, or in a single column or Alternatively, the signal may be divided and input in units of multiple columns using dot sequential driving.

[0252] An example of the configuration in which the source driver is formed as an internal circuit is shown in FIG. As shown in FIG. 1, a pixel 211, a gate driver 212, a gate signal line, and a source signal line are The same as that shown in FIG. 21 can be used. The source driver 221 outputs a video signal. It is a source driver for outputting video signals by point sequential drive or line sequential drive. The configuration of the source driver 221 is the same as that of the source driver described in the fifth embodiment. The configuration may be used.

[0253] As shown in the configuration example of the display device shown in FIG. 21, m columns of source signal lines are connected to m pixels. As display devices become higher resolution and larger, the video signal becomes The number of input signals, that is, the number of terminals input via external circuits or FPCs, etc., will increase significantly. Therefore, a certain gate signal line is selected by the gate driver (outputting High). The period during which the source signal is input is divided into several periods, and a video signal is input to a different source signal line during each divided period. Thus, the number of terminals through which the video signal is input is reduced. An example of the configuration of the signal input unit will be described with reference to FIG. The route is shown in Figure 47.

[0254] FIG. 46 shows an example of a video signal input section of the display device shown in FIG. 21. Other parts, such as the pixel 211 and the gate driver 212, can use similar parts. FIG. 46 explains a configuration example in which the source signal lines are divided into RGB. For convenience, the video signal input terminal is two terminals and the source signal line is six, but it is not limited to this. The rules are not fixed and can be changed as needed.

[0255] As shown in FIG. 46, a control signal line R, a control signal line G, a control signal line B, a video signal input terminal The S1 (RGB) terminal and the video signal input terminal S2 (RGB) are used to input control signals from the outside. The switching elements SW1R and SW2R are the input terminals for the control signal. It is a switching element that is turned on and off by line R. Switching element SW The switching element SW1G and the switching element SW2G are switches that are controlled to be on or off by a control signal line G. The switching elements SW1B and SW2B are controlled The source signal line S1 is a switching element that is controlled to be turned on or off by the source signal line S2. -R, source signal line S1-G, source signal line S1-B, source signal line S2-R, The source signal line S2-G and the source signal line S2-B are source signal lines for transmitting video signals to the pixels. This is Line No.

[0256] The connection relationship in FIG. 46 will be described. The video signal input terminal S1 (RGB) is One terminal of the switching element SW1R, one terminal of the switching element SW1G, and One terminal of the switching element SW1B is connected to the other terminal of the switching element SW1R. The other terminal of the switching element SW1G is connected to the source signal line S1-R. The other terminal of the switching element SW1B is connected to the source signal line S1-G. 1-B. Video signal input terminal S2 (RGB), switching element SW2 R, switching element SW2G, switching element SW2B, source signal line S1-R, The source signal line S1-G and the source signal line S1-B are connected in a similar manner.

[0257] Switching element SW1R, switching element SW1G, switching element SW1B, The switching element SW2R, the switching element SW2G, and the switching element SW2B are For example, it can be configured using an N-channel transistor. Connect one of the source and drain of the monitor to the video input terminal S1 (RGB). The other of the drains is connected to the source signal line S1-R, and the gate is connected to the control signal line R. By doing so, it can function as a switching element. By using a CMOS transistor, it is easy to use amorphous semiconductors. This is advantageous for low cost and large size. A general analog switch that connects a P-channel transistor in parallel may be used. Alternatively, any element or circuit that can be controlled to be turned on and off may be used.

[0258] FIG. 47 shows the timing when a video signal is written to the pixels 211 in the nth and (n+1)th rows. As explained above, the video signal is written in the nth row during the period ( The video signal input terminal S1 (R GB), the video signals S1-Rn, S1-Gn, and S1- Bn is input from an external circuit. The on / off of the switching element responds to the change in this video signal. By controlling the on / off of the video signal, one video signal input terminal can be used to connect the video This allows the number of video signal input terminals to be reduced. Cut.

[0259] The driving method shown in FIG. 46 is a gate drive method using transistors that use non-crystalline semiconductors. This is an effective means for a display device in which a light driver and pixels are formed on the same substrate. In the case of a display device in which only n columns of pixels, source signal lines, and gate signal lines are formed, At least m × n terminals are required to connect to external circuits. When formed on the same substrate, the input terminals are the control signals for driving the gate drivers and the power supply A terminal for inputting the number of rows and n terminals for n rows are required. In other words, an input terminal for almost n terminals is required. Here, if the n terminal can be made into a (1 / 3)n terminal as shown in Figure 46, The circuit size can be reduced.

[0260] The operation shown in FIG. 21 will be described. As described above, the gate driver 212 Then, a video signal can be written to the pixels 211 in the selected row. determines how much light is emitted or transmitted according to the video signal written into the Then, when the selection by the gate driver 212 is completed, the next selection is By using a capacitance element or the capacitance of a display element to hold a video signal, the luminance of light can be increased. In this way, active matrix driving can be realized.

[0261] As shown in the configuration examples of the display devices shown in FIGS. 21, 22, and 46, An example of the configuration of a display device in which a driver is arranged will be described with reference to FIG. Although not shown, source signal lines and pixels 211 are arranged.

[0262] As shown in FIG. 49, the gate drivers 212 output gate signals at the same timing. The gate driver is characterized by having outputs connected to each other on the same row. This gate driver 212 is the same as the gate driver 212 described in FIG. 21 and FIG. A variety of things can be used.

[0263] As shown in FIG. 49, one gate signal line is connected to the gate driver 212 arranged opposite to the Therefore, the driving method is the same as that of the gate driver 212, which is made of amorphous semiconductor. It is advantageous to configure the gate driver 212 using a transistor having a non-crystalline semiconductor. Transistors made of conductors have low charge mobility, and their performance is comparable to that of polycrystalline semiconductors and single-crystal semiconductors. It is significantly inferior to crystalline semiconductors. However, the manufacturing process is simple and it is suitable for large-scale production. Therefore, some of the internal circuits, such as the gate driver, are mounted on the same substrate as the pixels. The development of display devices mounted on a substrate is underway. However, When forming a gate driver using transistors with To achieve this, transistors with wider channel widths were required. This resulted in a larger area for forming the frame, making it difficult to narrow the frame and achieve high resolution. As shown in Figure 9, one gate signal line is driven by two gate drivers arranged opposite each other. By driving the gate signal lines, even if the current capacity is low, the gate signal lines can be scanned normally.

[0264] The gate driver described in FIG. 49 is the same as that described in the first to fourth embodiments. The shift register circuit described above does not need to be used. A gate driver formed by using a transistor made of a crystalline semiconductor is integrally formed. It is advantageous to show this on a display device.

[0265] Below, some configuration examples of the pixel 211 shown in FIG. 21, FIG. 22, and FIG. 46 will be described. do.

[0266] An example of the configuration of a pixel 211 using a liquid crystal element will be described with reference to FIG.

[0267] As shown in the pixel 211 in FIG. 23, a transistor 231, a capacitive element having two electrodes, A liquid crystal element 233 having two electrodes and a counter electrode 23 4. A source signal line, a gate signal line, and a common line which is the other electrode of the capacitor element 232 The source signal lines and gate signal lines are configured as shown in FIG. 21, FIG. 22, and FIG. 46. The source signal line carries an analog signal voltage as a video signal. This information shall be communicated.

[0268] The transistor 231 is an N-channel transistor that operates as a switch. A transistor that turns on when the potential of the output signal line becomes high and turns off when the potential becomes low. When the transistor 231 is turned on, the source signal line and one of the liquid crystal elements 233 are connected to each other. The source electrode and one electrode of the capacitor element 232 are electrically connected to each other. A video signal is directly applied to one electrode of the liquid crystal element 233 and one electrode of the capacitor element 232. Then, the transistor 231 is turned off, and the source signal line and the liquid crystal element 233 are connected to each other. One electrode of the capacitor 232 is electrically disconnected from one electrode of the capacitor 232. The supply and movement of charges to one electrode of the liquid crystal element 232 and one electrode of the liquid crystal element 233 are stopped. do.

[0269] The capacitance element 232 is connected to the source signal line via the turned-on transistor 231. The other electrode of the capacitor 232 is a constant potential. Because it is connected to a common line, the potential applied to one electrode can be maintained for a certain period of time. In addition, if the other electrode of the capacitor 232 is at a constant potential during operation, For example, it may be connected to the gate signal line of the previous row. Since the signal line is just after scanning, it is low for almost the entire row scanning period and is at a constant potential. Therefore, it can be used in place of a common line.

[0270] The other electrode of the liquid crystal element 233 is connected to a counter electrode 234 having a constant potential. The liquid crystal element changes its light transmittance depending on the potential difference between the electrode and the counter electrode 234. The potential of one electrode of the transistor 233 is transmitted via a source signal line and the transistor 231. Since the transmittance of the liquid crystal element 233 is determined by the video signal, the transmittance of the liquid crystal element 233 changes depending on the potential of the video signal. In the case of a display device using a liquid crystal element 233, a backlight is used. It is possible to use a reflective electrode, or to use a backlight and a reflective electrode together. The liquid crystal element 233 has a capacitance component and can hold a video signal. When the liquid crystal element 233 has a sufficient capacitance component for It is also possible to adopt a configuration in which no is provided.

[0271] A configuration example of a pixel 211 using a light-emitting element will be described with reference to FIG.

[0272] As shown in the pixel 211 in FIG. A capacitance element 243 having one electrode, a light-emitting element 244 having two electrodes, and other elements The counter electrode 245 is an electrode on one side of the substrate, and is composed of a power supply line, a source signal line, and a gate signal line. The source signal lines and the gate signal lines are the same as those explained in FIG. 21, FIG. 22 and FIG. 46. The source signal line is the same as the analog signal voltage or 1-bit The digital signal voltage of the

[0273] The transistor 241 is an N-channel transistor that operates as a switch. A transistor that turns on when the potential of the output signal line becomes high and turns off when the potential becomes low. When the transistor 241 is turned on, the source signal line and the gate of the transistor 242 The source signal line is electrically connected to one of the electrodes of the capacitor element 243. The demodulation signal is directly transmitted to the gate of the transistor 242 and one electrode of the capacitor 243. Then, the transistor 241 is turned off, and the source signal line and the transistor 242 The gate and one electrode of the capacitor 243 are electrically disconnected, and the transistor 2 The supply and transfer of charges to the gate of the transistor 42 and one electrode of the capacitor 243 is stopped.

[0274] Transistor 242 is an N-channel transistor that operates in the saturation and linear regions. When operating in the saturation region, the current that flows is determined by the potential applied to the gate. When operating in the axial region, the drive transistor is turned on or off depending on the potential applied to the gate. The power supply line is at a constant potential, which is higher than the potential of the counter electrode 245. Therefore, the source is on the other electrode side of the capacitor 243, and the drain is on the power supply line side.

[0275] The capacitance element 243 receives the bias current transmitted from the source signal line through the turned-on transistor 241. The capacitor 243 is a capacitor for storing a video signal. One electrode of the capacitor 243 is connected to a transistor The other electrode is connected to the gate of transistor 242 and the other electrode is connected to the source of transistor 242. In other words, the potential difference between the gate and source of the transistor 242 is held in the capacitor 243. Therefore, even if the potential of the source of the transistor 242 changes, the The potential of the gate of the transistor 242 also changes. The reason for connecting the resistor 242 to the source of the light emitting element 244 is that the current flowing through the light emitting element 244 described next In other words, during the video signal writing period (transistor During the period when the light emitting element 241 is on, the potential of one electrode of the light emitting element 244 is in a transient state. When the video signal writing period ends, the source potential of the transistor 242 changes. This is because the potential between the gate and the source changes, and the current value also changes. If the potential of one electrode of the light emitting element 244 can be kept steady during the writing period of the video signal, The other electrode of the capacitance element 243 may be connected to a power supply line or to a gate signal line of the previous row. Alternatively, it may be connected anywhere as long as it is at a constant potential.

[0276] The light emitting element 244 is a light emitting element whose luminance changes in proportion to the current flowing therethrough. The light emission luminance is determined in proportion to the current value determined by the transistor 242. The electrode is connected to a counter electrode 245. The counter electrode 245 is preferably at a constant potential. However, the potential may be changed in order to compensate for variations in the characteristics of transistor 242.

[0277] PIXEL CIRCUIT FOR COMPENSATING FOR CHANGE IN CHARACTERISTICS OF DRIVE TRANSISTOR AND PIXEL USING LIGHT-EMITTING DEVICE - Patent application An example of the configuration of 211 will be described with reference to FIG.

[0278] As shown in the pixel 211 in FIG. A transistor 253, a capacitance element 254 having two electrodes, and a light-emitting element 244 having two electrodes. , a counter electrode 245 which is the other electrode of the light emitting element 244, a power line, a source signal line, and a gate The source signal lines and gate signal lines are shown in FIG. 46. ​​The light emitting element 244 and the counter electrode 245 are The source signal line transmits an analog signal current as a video signal. This shall be the case.

[0279] The transistor 251 is an N-channel transistor that operates as a switch. A transistor that turns on when the potential of the output signal line becomes high and turns off when the potential becomes low. When the transistor 251 is turned on, the source signal line and the source of the transistor 252 One electrode of the capacitor 254 and one electrode of the light-emitting element 244 are electrically connected to each other. , the video signal transmitted from the source signal line flows. 1 is turned off, and the source signal line, the source of the transistor 252, and one of the capacitor elements 254 The electrode and one of the electrodes of the light emitting element 244 are electrically disconnected, and the video signal is not transmitted. It will no longer be achieved.

[0280] Transistor 252 is an N-channel transistor that acts as a switch. A transistor that turns on when the potential of the output signal line becomes high and turns off when the potential becomes low. When the transistor 252 is turned on, the power supply line and the gate of the transistor 253 are connected to the power supply line. The transistor 253 is electrically connected to the 2 is turned off, disconnecting the power supply line from the gate of transistor 253, and transistor The supply and transfer of charge to the gate of 252 is eliminated.

[0281] The transistor 253 is an N-channel transistor that operates in the saturation region. The gate voltage is determined by the current flowing through the gate 253. The signal line becomes High, turning on the transistors 251 and 252. During a write period in which a current, which is a video signal, is input from the signal line, transistor 25 3 is a diode connection. The video signal current flows like a current flowing from the power line. Therefore, the source is one electrode side of the light emitting element, and the drain is the power line side. During the write period of the O signal, the potential of the power supply line is the source potential of the transistor 253. is set to be equal to or lower than the sum of the potential of the counter electrode 256 and the threshold voltage of the light emitting element 244. If the potential difference is more than this, it may become too high to be the threshold voltage of the light emitting element 244. When the voltage is applied, a current sufficient for the light emitting element 244 to emit light starts to flow, and the light emitting element 244 emits light. This is because the video signal cannot be written accurately and the display quality is reduced. When a video signal is written, the gate of transistor 253 and The capacitance element 254 connected between the source and the transistor 253 is saturated. Since it operates in the region, if the potential difference between the source and drain is maintained, the current that flows is Thus, the writing of the video signal is completed, and the transistor 251 and the transistor When the transistor 252 is turned off, the gate of the transistor 253 is floating. When the potential of the power supply line is increased, a beam is supplied from the power supply line to the light emitting element 244 via the transistor 253. When the current starts to flow, the potential corresponding to the current flowing is The potential is applied to one electrode of the light emitting element 244, and the potential gradually increases. The potential of the source of the transistor 253 changes, but the capacitance element 254 Since the potential difference between the gate and source of transistor 253 is maintained, the gate potential of transistor 253 also changes at the same time. In other words, even if the potential of the power supply line increases and a current starts to flow through the light emitting element 244, Since the potential difference between the gate and source of the transistor 253 does not change, the light emitting element A current value corresponding to a video signal can be applied to 244.

[0282] The capacitance element 254 is provided to hold the potential difference between the gate and source of the transistor 253. As described above, one electrode of the capacitor 254 is connected to the transistor 2 The source of the transistor 53 is connected to one electrode of the light emitting element 244, and the other electrode of the transistor It is connected to 253 gates.

[0283] As described above, the power supply line is at a low potential during the video signal writing period. When the write period ends, the power supply line becomes high potential. In other words, it is a power supply line with two potential values. In order to drive this power line, the shift register described in the first to fourth embodiments is used. A register circuit may be used. This shift register circuit is configured to output a high signal in sequence. However, by connecting an inverter circuit that inverts High and Low, It can be used as a power line.

[0284] PIXEL CIRCUIT FOR COMPENSATING FOR CHANGE IN CHARACTERISTICS OF DRIVE TRANSISTOR AND PIXEL USING LIGHT-EMITTING DEVICE - Patent application An example of the configuration of 211 will be described with reference to FIG.

[0285] As shown in the pixel 211 in FIG. A transistor 263, a transistor 264, a capacitance element 265 having two electrodes, and a capacitance element 2 The other electrode of the light emitting element 244 is a constant potential wire 266, which is the other electrode of the light emitting element 244. 44, a counter electrode 245, a power supply line, a source signal line, and a gate signal line. The source signal lines and gate signal lines are configured as shown in FIG. 21, FIG. 22, and FIG. 46. The light emitting element 244 and the counter electrode 245 are the same as those described in FIG. The source signal line transmits an analog signal current as a video signal. This shall be done.

[0286] The transistor 261 and the transistor 262 are N-channel transistors that operate as switches. A transistor that turns on when the potential of the gate signal line is high and turns off when the potential of the gate signal line is low. The transistor 261 and the transistor 262 are turned on. When the source signal line and the gate of the transistor 263 and the gate of the transistor 264 are and one electrode of the capacitor 265 are electrically connected to the transistor 263. The video signal is a current that flows in from the source signal line, and the power line is connected to the light-emitting element. In order to set the potential of the transistor 263 higher than that of one electrode of the transistor The source of the transistor 264 is one electrode of the light emitting element. The drain of the transistor 262 is on the side of the transistor 264, and the drain of the transistor 264 is on the side of the power supply line.

[0287] The transistor 263 is an N-channel transistor that operates in the saturation region. The gate voltage is determined by the current flowing through the gate 263. When the signal line becomes High and the transistor 261 and the transistor 262 are turned on, The transistor 263 is diode-connected so that the video signal flows in from the source signal line. At that time, the potential of the gate of the transistor 263 is Since the gate and source of the transistor 264 are common to the transistor 265, The potential of the gate of the transistor 264 also becomes a potential corresponding to the video signal. The potential of the gate of the transistor 263 and the potential of the gate of the transistor 264 are connected to the capacitor 265 Thus, the gate signal line is set to low, and the transistor 26 When the transistors 261 and 262 are turned off, the transistors 263 and 26 The potential of the gate of the transistor 4 is held in the capacitor 265. The drain of the transistor 263 is floating. Therefore, no current flows to the light emitting element 244 through the transistor 263 .

[0288] The other electrode of the capacitor element 265, that is, a constant potential line 266, may be a power supply line or may be a It may be a gate signal line. It may also be one of the electrodes of the light emitting element 244. Even if the potential of one electrode of the light emitting element 244 changes, the gate and the source of the transistor 264 This allows a current corresponding to a video signal to flow through the light-emitting element without changing the potential difference between the can.

[0289] Seventh embodiment In this embodiment, the shift register circuit described in the first to fourth embodiments is An example of the configuration when the above-mentioned layout is used will be described.

[0290] The shift register circuit described in the first embodiment is formed using transistors with a bottom gate structure. A configuration example in which the above-described embodiment is implemented will be described with reference to FIG. However, the present invention is not limited to this configuration example of the shift register circuit shown in FIG. The present invention can also be applied to the shift register circuit described in the fourth embodiment. The present invention can also be applied to shift register circuits other than those described in the first to fourth embodiments. Cut.

[0291] FIG. 44 shows transistor 31, transistor 32, transistor 41, and transistor 42. , three control signal lines for transmitting control signals CK1, CK2, and CK3; a positive power supply V It consists of a power supply line that is the potential of the DD and two power supply lines that are the potential of the negative power supply VSS. In addition, the control signal line that transmits CK1 is set as the control signal line CK1, and the control signal line that transmits CK2 is set as the control signal line CK2. The control signal line is referred to as the control signal line CK2, and the control signal line transmitting CK3 is referred to as the control signal line CK3. The power supply line that has the potential of the positive power supply VDD is the power supply line VDD, and the power supply line that has the potential of the negative power supply VSS is the power supply line VDD. The power line is the power line VSS.

[0292] Some features of the configuration diagram of the shift register circuit shown in FIG. 44 will be described.

[0293] OUT(1), which is the output of the shift register circuit, and control signal line CK1 and control signal line CK2 Note that the power supply lines VDD and VSS are placed between the control signal line CK3 and the The control signal line CK1, the control signal line CK2, and the control signal line CK3 are a clock signal. Since it is a control signal line for transmitting a signal, the potential is constantly changing. If parasitic capacitance occurs between the control signal line, noise will occur due to fluctuations in the potential of the control signal line. Since OUT(1) is the input to the next stage of the shift register circuit, OUT If noise occurs in (1), the shift register circuit will be prone to malfunction. Therefore, by placing a power line with a constant potential between the control signal line and OUT(1), This reduces the effect of noise generated by the control signal lines on the operation of the shift register circuit. can.

[0294] A metal wiring layer and a control signal line for connecting the output of the transistor 32 and OUT(1) Between CK1, the control signal line CK2 and the control signal line CK3, the power supply line VDD, the power supply line VSS and As described above, the output of the transistor 32 is If noise occurs in the metal wiring layer that connects the output and OUT(1), the shift register This can cause the circuit to malfunction. Also, depending on the transistor layout, long wiring may be required. Therefore, by placing a power supply line and a transistor between the control signal line, noise can be reduced. It can be made less likely to occur.

[0295] The transistor 32 that performs the bootstrap operation is a U-shaped transistor. The transistor 32 is a transistor for supplying the positive power supply VDD of the output. Therefore, a high current capacity is required, so a U-shaped transistor requires a wide channel width. It can be taken.

[0296] The transistors 41 and 42 share one of the source and drain. This makes it possible to reduce the area required for constructing the shift register circuit. This is advantageous in that it is possible to provide a display device with higher resolution and narrower frame.

[0297] The power supply line and the control signal line have the same width. To prevent current from flowing, increase the wiring width to reduce wiring resistance and reduce the voltage drop caused by the instantaneous current. However, in the present invention, the control signal line is connected to the positive power supply VDD. Because it is used to output a voltage, a large amount of current flows instantaneously through the control signal line. Therefore, it is desirable to widen the wiring width of the control signal line. When the gap is narrowed to 100m, the voltage drop caused by the instantaneous current is large and the potential cannot be maintained. Therefore, the width of the control signal line is set to the width of the power supply line. It is desirable to make the line width equal to the power supply line in the shift register circuit of the present invention. Since the amount of current that flows is small, the wiring width of the control signal line may be made wider than the wiring width of the power supply line.

[0298] The shift register circuit described in the first embodiment is formed using transistors with a bottom gate structure. Another configuration example in which the first embodiment is implemented will be described with reference to FIG. The configuration of the shift register circuit described above is shown, but is not limited to this. The present invention can also be applied to the shift register circuits described in the first to fourth embodiments. The present invention can also be applied to shift register circuits other than those described in the first to fourth embodiments. can be done.

[0299] FIG. 45 shows transistor 31, transistor 32, transistor 41, and transistor 42. , three control signal lines for transmitting control signals CK1, CK2, and CK3; a positive power supply V It consists of a power supply line that is at the DD potential and two power supply lines that are at the negative power supply VSS potential. In addition, the control signal line that transmits CK1 is set as the control signal line CK1, and the control signal line that transmits CK2 is set as the control signal line CK2. The control signal line that transmits CK3 is referred to as the control signal line CK3. The power supply line that has the potential of the positive power supply VDD is the power supply line VDD, and the power supply line that has the potential of the negative power supply VSS is the power supply line VDD. The line is the power supply line VSS.

[0300] Some features of the configuration diagram of the shift register circuit shown in FIG. 45 will be described.

[0301] The transistors that make up the shift register circuit are arranged so that they are sandwiched between power lines that are at a constant potential. When using bootstrap operation, the floating node is Therefore, it is necessary to reduce noise. By sandwiching it between the lines, noise from the control signal lines and other circuits can be reduced. EXAMPLES

[0302] In this embodiment, a configuration example of a pixel will be described. FIG. 1 is a cross-sectional view of a pixel of a panel according to the present invention; 1 shows an example in which a light-emitting element is used as a display medium arranged in a pixel, and a transistor is used as a display medium arranged in the pixel.

[0303] In FIG. 24(A) and FIG. 24(B), 2400 is a substrate, 2401 is an undercoat film, 240 2 is a semiconductor layer, 2412 is a semiconductor layer, 2403 is a first insulating film, 2404 is a gate electrode, 2414 is an electrode, 2405 is a second insulating film, and 2406 is a source electrode or a drain electrode. 2407 is a first electrode, 2408 is a third insulating film, and 2409 is a light-emitting layer. 2410 is a transistor, 2415 is a light-emitting element, and 2417 is a second electrode. In FIG. 24, a transistor 2410 and a 24A and a capacitor 2411 are shown as representatives. The structure of FIG.

[0304] The substrate 2400 may be, for example, barium borosilicate glass or aluminoborosilicate glass. A glass substrate such as stainless steel, a quartz substrate, a ceramic substrate, or the like can be used. A metal substrate including a metal layer or a semiconductor substrate having an insulating film formed on the surface thereof may also be used. Alternatively, a substrate made of a flexible synthetic resin such as plastic may be used. The surface may be planarized by polishing using a CMP method or the like.

[0305] The base film 2401 is an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide. The undercoat film 2401 can prevent alkali such as Na contained in the substrate 2400 from being oxidized. The alkali metals and alkaline earth metals diffuse into the semiconductor layer 2402 and adversely affect the characteristics of the transistor 2410. In FIG. 24, the undercoat film 2401 is a single-layer structure. However, it may be formed in two or more layers. If diffusion is not a significant problem, the undercoat film 2401 does not necessarily have to be provided.

[0306] The semiconductor layer 2402 and the semiconductor layer 2412 are patterned crystalline semiconductor films. A crystalline semiconductor film can be formed by crystallizing an amorphous semiconductor film. The crystallization method can be laser crystallization, RTA, or furnace annealing. The thermal crystallization method using a furnace, the thermal crystallization method using a metal element that promotes crystallization, etc. The semiconductor layer 2402 has a channel forming region and an impurity element that imparts a conductivity type. The channel forming region and the pair of impurity regions are connected to each other. An impurity region to which an impurity element is added at a low concentration may be provided between the semiconductor layer 241. The entire region of 2 may be doped with an impurity element that imparts a conductivity type.

[0307] The first insulating film 2403 is made of silicon oxide, silicon nitride, silicon nitride oxide, or the like. The first insulating film 2403 may be a layer or a stack of multiple films. The semiconductor layer 2402 may be hydrogenated by using a film containing hydrogen.

[0308] The gate electrode 2404 and the electrode 2414 may be made of Ta, W, Ti, Mo, Al, Cu, Consists of an element selected from Cr and Nd, or an alloy or compound containing multiple of said elements. Single layer or laminate structures can be used.

[0309] The transistor 2410 includes a semiconductor layer 2402, a gate electrode 2404, and a semiconductor layer 2405. 24 and a first insulating film 2403 between the gate electrode 2404 and the first insulating film 2402. In the example, a transistor constituting a pixel is connected to a first electrode 2407 of a light emitting element 2415. Although only a connected transistor 2410 is shown, a configuration having multiple transistors may be used. In this embodiment, the transistor 2410 is a top-gate transistor. However, it is a bottom-gate transistor having a gate electrode below the semiconductor layer. Alternatively, a dual-gate transistor having gate electrodes above and below the semiconductor layer may be used. It's okay to have it.

[0310] The capacitance element 2411 has the first insulating film 2403 as a dielectric. The semiconductor layer 2412 and the electrode 2414 facing each other are configured as a pair of electrodes. In FIG. 24, one of a pair of electrodes of a transistor 2410 is used as a capacitor element of a pixel. The semiconductor layer 2412 is formed at the same time as the semiconductor layer 2402. The other electrode is a transistor In the example shown, the electrode 2414 is formed simultaneously with the gate electrode 2404 of 2410. The present invention is not limited to the above configuration.

[0311] The second insulating film 2405 may be a single layer or a multilayer of an inorganic insulating film or an organic insulating film. The inorganic insulating film can be a silicon oxide film formed by the CVD method or a SOG film. It is possible to use a silicon oxide film coated by the Spin On Glass (SpG) method. The organic insulating film can be polyimide, polyamide, BCB (benzocyclobutene), Films such as acrylic, positive-type photosensitive organic resin, and negative-type photosensitive organic resin can be used. .

[0312] The second insulating film 2405 is made of a skeletal structure of silicon (Si) and oxygen (O). The material may have at least hydrogen as a substituent. The organic group containing fluorine (e.g., alkyl group, aromatic hydrocarbon) is used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. and may be used.

[0313] The surface of the second insulating film 2405 may be treated with high density plasma to be nitrided. High density plasma can be produced by using high frequency microwaves, e.g. 2.45 GHz. The high density plasma is generated when the electron density is 1×10 11 cm -3 End 1×10 13 cm -3 and the electronic temperature is 0.2 eV or more and 2.0 eV or less (preferably In this way, a low electron temperature is used. The characteristic of high-density plasma is that the kinetic energy of activated species is low, which is different from conventional plasma processing. Compared to conventional plasma, it is possible to form a film with fewer defects and less plasma damage. During processing, the temperature of the substrate 2400 is set to 350° C. to 450° C. Also, high density plasma is used. In the generating device, the distance from the antenna generating the microwave to the substrate 2400 is The distance is 20 to 80 mm (preferably 20 to 60 mm).

[0314] Nitrogen (N2) and rare gas (containing at least one of He, Ne, Ar, Kr, and Xe) atmosphere In an atmosphere of nitrogen, hydrogen (H2) and rare gas, or ammonia (NH3) and rare gas The surface of the second insulating film 2405 is nitrided by the above-mentioned high density plasma treatment under a nitrogen atmosphere. The surface of the second insulating film 2405 formed by nitriding with high density plasma contains H and , He, Ne, Ar, Kr, and Xe. A silicon oxide film or a silicon oxynitride film is used as the substrate, and the surface of the film is treated with high-density plasma. The silicon nitride film is formed by processing the silicon nitride film. The hydrogen may be used to hydrogenate the semiconductor layer 2402 of the transistor 2410. Note that this hydrogenation treatment is performed in combination with the hydrogenation treatment using hydrogen in the first insulating film 2403 described above. It is also possible to combine a nitride film formed by the high density plasma treatment with a silicon nitride film. An insulating film may be formed as the second insulating film 2405 .

[0315] The first electrode 2406 may be made of Al, Ni, C, W, Mo, Ti, Pt, Cu, Ta, A single layer or multilayer made of one element selected from Au and Mn or an alloy containing multiple of said elements The structure can be used.

[0316] One or both of the first electrode 2407 and the second electrode 2417 are transparent electrodes. Transparent electrodes can be made of indium oxide containing tungsten oxide (IWO), oxide Indium Zinc Oxide with Tungsten Dioxide (IWZO), Indium with Titanium Dioxide Indium tin oxide (ITiO), titanium oxide-containing indium tin oxide (ITTiO), etc. Of course, indium tin oxide (ITO), indium zinc oxide (IZO) Alternatively, indium tin oxide doped with silicon oxide (ITSO) can be used.

[0317] The light-emitting layer uses multiple layers with different functions, such as a hole injection and transport layer, a light-emitting layer, and an electron injection and transport layer. It is preferable to configure the

[0318] The hole injection transport layer is made of an organic compound material having a hole transporting property and an electrode for the organic compound material. It is preferable that the insulating layer is formed of a composite material containing an inorganic compound material that exhibits electron acceptability. By using this structure, many holes can be generated in organic compounds that have few inherent carriers. Carriers are generated, resulting in excellent hole injection and transport properties. The driving voltage can be lowered compared to the conventional method. In addition, hole injection can be achieved without increasing the driving voltage. Since the injection transport layer can be made thick, short circuits in the light emitting element caused by dust, etc. can be suppressed. can be done.

[0319] As a hole-transporting organic compound material, 4,4',4''-tris[N-(3-methyl (N-phenylamino)triphenylamine (abbreviation: MTDATA), 1, 3,5-Tris[N,N-di(m-tolyl)amino]benzene (abbreviation: m-MTDAB) , N,N'-diphenyl-N,N'-bis(3-methylphenyl)-1,1'-biphenyl N-(1-naphthyl)-4,4'-diamine (TPD), 4,4'-bis[N-(1-naphthyl)-N -phenylamino]biphenyl (abbreviation: NPB), but is not limited to these. It will never happen.

[0320] Inorganic compounds that exhibit electron-accepting properties include titanium oxide, zirconium oxide, and vanadium oxide. tungsten oxide, rhenium oxide, ruthenium oxide, zinc oxide In particular, vanadium oxide, molybdenum oxide, tungsten oxide, and rhodium oxide are Aluminum is suitable because it can be vacuum deposited and is easy to handle.

[0321] The electron injecting and transporting layer is formed using an organic compound material having an electron transporting property. Tris(8-quinolinolato)aluminum (abbreviation: Alq3), tris(4-methyl-8-quinolinolato)aluminum Norinolato) aluminum (abbreviation: Almq3), but is not limited to these. It will never happen.

[0322] The light-emitting layer is made of 9,10-di(2-naphthyl)anthracene (abbreviation: DNA), 9,10- Di(2-naphthyl)-2-tert-butylanthracene (abbreviation: t-BuDNA), 4 ,4'-Bis(2,2-diphenylvinyl)biphenyl (abbreviation: DPVBi), coumarin 30, Coumarin 6, Coumarin 545, Coumarin 545T, Perylene, Rubrene, Perifurano 2,5,8,11-tetra(tert-butyl)perylene (abbreviation: TBP), 9 ,10-Diphenylanthracene (abbreviation: DPA), 5,12-Diphenyltetracene, 4-(Dicyanomethylene)-2-methyl-[p-(dimethylamino)styryl]-4H- Pyran (abbreviation: DCM1), 4-(dicyanomethylene)-2-methyl-6-[2-(decyl) 4-(dicyanomethoxy)-4H-pyran (abbreviation: DCM2), 2,6-bis[p-(dimethylamino)styryl]-4H-pyran (abbreviation: B isDCM) and the like. Liginato-N,C2']iridium(picolinate) (abbreviation: FIrpic), bis{2 -[3',5'-Bis(trifluoromethyl)phenyl]pyridinato-N,C2'}yl Ir(picolinate) (abbreviation: Ir(CF3ppy)2(pic)), tris(2-fluorophenyl) (phenylpyridinato-N,C2')iridium (abbreviation: Ir(ppy)3), bis(2-phenylpyridinato-N,C2')iridium (abbreviation: Ir(ppy)3), Phenylpyridinato-N,C2')iridium(acetylacetonate) (abbreviation: Ir(p py)2(acac)), bis[2-(2'-thienyl)pyridinato-N,C3']yl Ir(thp)2(acac)), bis(2- Phenylquinolinato-N,C2')iridium(acetylacetonate) (abbreviation: Ir( pq) 2(acac)), bis[2-(2'-benzothienyl)pyridinato-N,C3' ]Iridium(acetylacetonate) (abbreviation: Ir(btp)2(acac)) Compounds capable of emitting phosphorescence may also be used.

[0323] Other polymer electroluminescent materials that can be used to form the light-emitting layer include polyparaf Examples include polyphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene. Can be obtained.

[0324] In any case, the layer structure of the light-emitting layer may be changed, and a specific hole or electron injecting transport may be used. Instead of having a transmitting or luminescent layer, they have an electrode layer dedicated to this purpose or a luminescent The above-mentioned materials may be dispersed in the light emitting device, but the purpose of the light emitting device may be achieved. This is acceptable.

[0325] The other of the first electrode 2407 and the second electrode 2417 is formed of a material that does not transmit light. For example, alkali metals such as Li and Cs, and arsenic metals such as Mg, Ca, and Sr may be used. Alkaline earth metals, alloys containing these (Mg:Ag, Al:Li, Mg:In, etc.), In addition to these compounds (CaF2, CaN), rare earth metals such as Yb and Er can also be used. can.

[0326] The third insulating film 2408 is formed using the same material as the second insulating film 2405. The third insulating film 2408 is formed on the first electrode 2407 so as to cover the edge of the first electrode 2407. It is formed around the electrode 2407 and has the function of separating the light-emitting layer 2409 in adjacent pixels. Yes.

[0327] The light-emitting layer 2409 is composed of one or more layers. In this case, these layers are classified into a hole injection layer, a hole transport layer, a light emitting layer, a charge transport layer, and a charge transport layer from the viewpoint of carrier transport properties. The boundaries between the layers are not necessarily clear. It is not necessary to mix the layers together, and the interface may be unclear if the materials constituting each layer are mixed together. Each layer can be made of organic or inorganic materials. As the material, any of high molecular weight, medium molecular weight, and low molecular weight materials can be used.

[0328] The light emitting element 2415 includes a light emitting layer 2409 and a first electrode 2414 overlapping the light emitting layer 2409. The first electrode 2407 and the second electrode 2417 are One of the electrodes 2417 corresponds to an anode, and the other corresponds to a cathode. When a voltage greater than the threshold voltage is applied between the cathodes in forward bias, current flows from the anode to the cathode. The stream flows and emits light.

[0329] The configuration of Fig. 24(B) will be described. Note that the same parts as those in Fig. 24(A) are designated by the same reference numerals. FIG. 24B shows the second insulating film 24 in FIG. 24A. The insulating film 2418 is disposed between the second electrode 2405 and the third insulating film 2408. 16 and the first electrode 2406 through a contact hole provided in an insulating film 2418. Connected.

[0330] The insulating film 2418 can have a structure similar to that of the second insulating film 2405. The pole 2416 may be of similar construction to the first electrode 2406 . EXAMPLES

[0331] In this embodiment, an amorphous silicon (a-Si:H) film is used for the semiconductor layer of the transistor. FIG. 28 shows a top-gate transistor, and FIG. 29 and FIG. 30 show a top-gate transistor. The case of a bottom-gate transistor is shown in FIG.

[0332] The cross section of a top-gate transistor that uses amorphous silicon as the semiconductor layer is shown. As shown in FIG. 28(a), an undercoat film 2802 is formed on a substrate 2801. Furthermore, a pixel electrode 2803 is formed on the base film 2802. A first electrode 2804 made of the same material is formed in the same layer.

[0333] The substrate may be a glass substrate, a quartz substrate, a ceramic substrate, or the like. The film 2802 may be a single layer of aluminum nitride, silicon oxide, silicon oxynitride, or a laminate of these. It can be used.

[0334] In addition, a wiring 2805 and a wiring 2806 are formed on the base film 2802, and the pixel electrode 280 The end of the wiring 2805 is covered with the wiring 2806. An N-type semiconductor layer 2807 and an N-type semiconductor layer 2808 having a conductivity type are formed. A semiconductor layer 2809 is formed on the base film 2802 between the wiring 2805 and the wiring 2806. A part of the semiconductor layer 2809 is formed of an N-type semiconductor layer 2807 and an N-type semiconductor The semiconductor layer extends onto the layer 2808. Note that this semiconductor layer is made of amorphous silicon (a-Si). It is made of a semiconductor film having non-crystalline properties such as a microcrystalline semiconductor (μ-Si:H) or a microcrystalline semiconductor (μ-Si:H). A gate insulating film 2810 is formed on the semiconductor layer 2809. An insulating film 2811 made of the same material as the insulating film 2810 is also formed on the first electrode 2804. The gate insulating film 2810 is formed of a silicon oxide film, a silicon nitride film, or the like. I can.

[0335] A gate electrode 2812 is formed on the gate insulating film 2810. A second electrode 2813 made of the same material as the first electrode 2804 is formed on the insulating film 28 on the first electrode 2804. The first electrode 2804 and the second electrode 2813 are formed with the insulating film 28 interposed therebetween. A capacitor element 2819 is formed by sandwiching the pixel electrode 2803. An interlayer insulating film 2814 is formed to cover the driving transistor 2818 and the capacitor element 2819. There are.

[0336] An organic compound is formed on the interlayer insulating film 2814 and the pixel electrode 2803 located in the opening of the interlayer insulating film 2814. A layer 2815 and a counter electrode 2816 are formed, and the pixel electrode 2803 and the counter electrode 2816 A light emitting element 2817 is formed in a region where the layer 2815 containing an organic compound is sandwiched.

[0337] The first electrode 2804 shown in FIG. 28(a) is connected to the first electrode 282 as shown in FIG. 28(b). The first electrode 2820 may be formed of the same material as the wirings 2805 and 2806. It is formed by:

[0338] A semiconductor device using a bottom-gate transistor with amorphous silicon as the semiconductor layer. A partial cross-section of a panel of a semiconductor device is shown in Figure 29. A gate electrode 2903 is formed on a substrate 2901. In addition, a first electrode 2904 made of the same material as the gate electrode is formed in the same layer. The gate electrode 2903 is made of a high melting point metal such as Ti, Cr, Mo, W, or Ta. It is possible.

[0339] A gate insulating film 2905 is formed so as to cover the gate electrode 2903 and the first electrode 2904. The gate insulating film 2905 is made of a silicon oxide film, a silicon nitride film, or the like.

[0340] A semiconductor layer 2906 is formed on the gate insulating film 2905. A semiconductor layer 2907 made of the same material as that of the semiconductor layer 2906 is formed in the same layer. A quartz substrate, a ceramic substrate, or the like can be used.

[0341] On the semiconductor layer 2906, N-type semiconductor layers 2908 and 2909 having N-type conductivity are formed. An N-type semiconductor layer 2910 is formed on the semiconductor layer 2907. Wirings 2911 and 2912 are formed on 908, 2909, and 2910, respectively, and N-type semiconductor On the conductor layer 2910, a conductive layer 291 made of the same material as the wirings 2911 and 2912 is formed. 3 is formed.

[0342] A second electrode is formed of a semiconductor layer 2907, an N-type semiconductor layer 2910, and a conductive layer 2913. The second electrode and the first electrode 2904 sandwich a gate insulating film 2905. A capacitor element 2920 having a soldered structure is formed.

[0343] One end of the wiring 2911 is extended, and a pixel electrode is formed in contact with the upper part of the extended wiring 2911. 2914 has been formed.

[0344] The edge of the pixel electrode 2914, the driving transistor 2919, and the capacitor element 2920 are covered with An insulating layer 2915 is formed on the pixel electrode 2914. A layer 2916 containing the compound and a counter electrode 2917 are formed, and the pixel electrode 2914 and the counter electrode 2917 are A light emitting element 2918 is formed in the region where the layer 2916 containing an organic compound is sandwiched between the layer 917 and the organic compound layer 2916. is.

[0345] A semiconductor layer 2907 and an N-type semiconductor layer 2910 which are to become a part of the second electrode of the capacitance element are provided. In other words, the second electrode is the conductive layer 2913, and the first electrode 2904 and the conductive layer 2 A capacitor element having a structure in which a gate insulating film is sandwiched between the gate electrodes 913 may be used.

[0346] In FIG. 29(a), a pixel electrode 2914 is formed before a wiring 2911 is formed. As shown in FIG. 29(b), the second electrode 2921 made of the pixel electrode 2914 and the first A capacitor element 2920 having a structure in which a gate insulating film 2905 is sandwiched between electrodes 2904 is formed. can be done.

[0347] In FIG. 29, a transistor having an inverse staggered channel etch structure is shown. Of course, a transistor with a channel protection structure may also be used. This will be explained with reference to Figures 30(a) and (b).

[0348] The transistor with the channel protection structure shown in FIG. 30(a) has the channel protection structure shown in FIG. The region in which the channel of the semiconductor layer 2906 of the driving transistor 2919 having the etched structure is formed is The difference is that an insulating layer 3001 is provided on the region as an etching mask. Wherever possible, common symbols are used.

[0349] Similarly, the transistor with the channel protection structure shown in FIG. 30(b) has the same structure as that shown in FIG. The channel of the semiconductor layer 2906 of the driving transistor 2919 having the channel etch structure is formed. The difference is that an insulating layer 3001 is provided on the region to be etched, which serves as an etching mask. Other commonalities are indicated by common symbols.

[0350] The semiconductor layer (channel forming region, source region, etc.) of the transistor constituting the pixel of this embodiment By using an amorphous semiconductor film for the drain region, etc., the manufacturing cost can be reduced. For example, an amorphous semiconductor film can be applied by using the pixel configuration shown in FIG. It is possible.

[0351] The structure of a transistor and the structure of a capacitor element to which the pixel configuration of this embodiment can be applied are The present invention is not limited to the above-mentioned configuration, and various configurations of transistor structures and capacitive element structures may be used. can be used.

[0352] The contents described in this embodiment can be freely combined with the contents described in the first embodiment. Cut. EXAMPLES

[0353] In this embodiment, a method for manufacturing a semiconductor device including a transistor is described. A method for manufacturing a semiconductor device using the process will be described.

[0354] FIG. 31 is a diagram showing a structural example of a semiconductor device including a transistor. 31(B) corresponds to a cross-sectional view taken along the line ab in FIG. 31(A), and FIG. 31(C) corresponds to a cross-sectional view taken along the line ab in FIG. This corresponds to the cross-sectional view between cd in 1(A).

[0355] The semiconductor device shown in FIG. 31 is a semiconductor device provided on a substrate 4601 with an insulating film 4602 interposed therebetween. and a gate insulating film on the semiconductor films 4603a and 4603b. A gate electrode 4605 provided through 4604 and an insulating layer provided to cover the gate electrode The films 4606 and 4607 and the source or drain regions of the semiconductor films 4603a and 4603b A conductive film 4608 is provided on the insulating film 4607 and is electrically connected to the region. In FIG. 31, a part of the semiconductor film 4603a is used as a channel region. A channel transistor 4610a and a part of the semiconductor film 4603b are used as a channel region. In the example shown, a P-channel transistor 4610b is provided. However, the present invention is not limited to this configuration. For example, in FIG. 31, an LDD region is provided in an N-channel transistor 4610a. The P-channel transistor 4610b does not have an LDD region, but both have It is also possible to provide both of them without the above configuration.

[0356] In this embodiment, the substrate 4601, the insulating film 4602, the semiconductor films 4603a and 460 3b, at least one of the gate insulating film 4604, the insulating film 4606, and the insulating film 4607 A semiconductor film or an insulating film is formed by oxidizing or nitriding one of the layers using a plasma treatment. The insulating film is then oxidized or nitridized to produce the semiconductor device shown in FIG. By oxidizing or nitriding the semiconductor film or insulating film using plasma treatment, The surface of the semiconductor film or insulating film is modified and an insulating film is formed by CVD or sputtering. It is possible to form a denser insulating film compared to the conventional method, which suppresses defects such as pinholes. This makes it possible to improve the characteristics of the semiconductor device.

[0357] In this embodiment, the semiconductor films 4603a and 4603b or the gate The insulating film 4604 is subjected to plasma treatment, and the semiconductor films 4603a and 4603b or A method for manufacturing a semiconductor device by oxidizing or nitriding a gate insulating film 4604 is described. This will be described with reference to the drawings.

[0358] First, an edge of an island-shaped semiconductor film provided on a substrate is The following shows the case where the angle is set at a nearly right angle.

[0359] First, island-shaped semiconductor films 4603a and 4603b are formed on a substrate 4601 (FIG. 32( A) The island-shaped semiconductor films 4603a and 4603b are formed in advance on a substrate 4601. Silicon is deposited on the insulating film 4602 by sputtering, LPCVD, plasma CVD, or the like. Amorphous semiconductor film made of silicon-based material (e.g. SiGe1-x, etc.) The amorphous semiconductor film is crystallized, and the semiconductor film is selectively etched. The amorphous semiconductor film can be crystallized by a laser crystallization method, an RTA method, or the like. The thermal crystallization method uses a furnace annealing furnace, and the thermal crystallization method uses a metal element that promotes crystallization. The crystallization can be carried out by a method such as a crystallization method, a method using a combination of these methods, etc. In FIG. 32, the ends of the island-shaped semiconductor films 4603a and 4603b are formed in a shape close to a right angle (θ=85 ~100°).

[0360] Next, a plasma treatment is performed to oxidize or nitride the semiconductor films 4603a and 4603b. As a result, oxide films or insulating films 4603a and 4603b are formed on the surfaces of the semiconductor films 4603a and 4603b, respectively. 621a and 4621b (hereinafter also referred to as insulating films 4621a and 4621b) are formed. (FIG. 32(B)). For example, when Si is used as the semiconductor films 4603a and 4603b, The insulating film 4621a and the insulating film 4621b are formed of silicon oxide (SiOx) or silicon nitride. In addition, the semiconductor films 4603a and 4603b are formed by plasma treatment. After oxidizing b, it may be nitrided by performing plasma treatment again. Silicon oxide is formed in contact with the semiconductor films 4603a and 4603b, and the surface of the silicon oxide is Silicon oxynitride (SiNxOy) (x>y) is formed. Note that the plasma treatment When oxidizing the film, the film is oxidized in an oxygen atmosphere (e.g., oxygen (O2) and rare gas (He, Ne, Ar, Kr, Xe) atmosphere or oxygen, hydrogen (H2) and rare gas In contrast, plasma treatment is performed using a fluorine-containing atmosphere (a fluorine-containing atmosphere or a nitrous oxide and rare gas atmosphere). When nitriding the semiconductor film by processing, the semiconductor film is nitridized in a nitrogen atmosphere (for example, nitrogen (N2) and rare gas (Containing at least one of He, Ne, Ar, Kr, and Xe) atmosphere or nitrogen and hydrogen Plasma treatment is performed in a rare gas atmosphere or in a rare gas atmosphere containing NH3. For example, Ar can be used. Alternatively, a mixed gas of Ar and Kr can be used. Therefore, the insulating films 4621a and 4621b are formed by using the rare gas (He, Ne At least one of Ar, Kr, and Xe is included. The films 4621a and 4621b contain Ar.

[0361] In addition, the plasma treatment is performed in an atmosphere of the above gas with an electron density of 1×10 11 cm - 3 More than 1×10 13 cm -3 The plasma electron temperature is 0.5 eV to 1.5 eV. The plasma has a high electron density, and the target object formed on the substrate 4601 is Since the electron temperature near the object (here, the semiconductor films 4603a and 4603b) is low, It is possible to prevent damage caused by plasma to objects. In addition, the electron density of the plasma is 1 ×10 11 cm -3 Since the density is higher than 100%, the irradiated object is oxidized by plasma treatment. The oxide or nitride film formed by nitriding or nitriding is formed by CVD or sputtering. Compared to films formed by conventional methods, it is possible to form a dense film with excellent uniformity in thickness, etc. In addition, the electron temperature of the plasma is low at 1 eV or less, so it is different from conventional plasma processing and thermal oxidation methods. The oxidation or nitriding process can be performed at a relatively low temperature. For example, the strain point of the glass substrate is Even if plasma treatment is performed at a temperature 100 degrees or more lower than the temperature, oxidation or nitridation treatment can be performed sufficiently. It is possible to form plasma with a frequency of microwave (2. Unless otherwise specified below, the following applies: The Zuma processing is carried out under the above conditions.

[0362] Next, a gate insulating film 4604 is formed so as to cover the insulating films 4621a and 4621b. FIG. 32(C). The gate insulating film 4604 is formed by sputtering, LPCVD, or plasma CVD. Using the above, silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x>y), and nitride oxide A single layer structure of an insulating film containing oxygen or nitrogen, such as silicon (SiNxOy) (x>y), or For example, the semiconductor films 4603a and 4603b may be formed in a stacked structure. The semiconductor film 46 is formed by using Si as a material and oxidizing the Si by plasma processing. When silicon oxide is formed as insulating films 4621a and 4621b on the surfaces of 03a and 4603b, Silicon oxide is formed as a gate insulating film over the insulating films 4621a and 4621b. In FIG. 32B, the semiconductor films 4603a and 4603b are oxidized by plasma treatment. The insulating films 4621a and 4621b formed by oxidizing or nitriding have a sufficient thickness. In some cases, the insulating films 4621a and 4621b may be used as gate insulating films. It is Noh.

[0363] Next, a gate electrode 4605 and the like are formed on the gate insulating film 4604 to form an island-like The semiconductor films 4603a and 4603b are used as channel regions to form an N-channel transistor. A semiconductor device having a P-channel transistor 4610a and a P-channel transistor 4610b is fabricated. This is possible (Figure 32(D)).

[0364] In this manner, before the gate insulating film 4604 is provided on the semiconductor films 4603a and 4603b, The surfaces of the semiconductor films 4603a and 4603b are oxidized or nitrided by plasma treatment. As a result, the gate insulating film 4604 at the ends 4651a, 4651b, etc. of the channel region is This can prevent short circuits between the gate electrode and the semiconductor film caused by poor coverage of the gate electrode. In the case where the edge of the island-shaped semiconductor film has a shape close to a right angle (θ=85 to 100°), When a gate insulating film is formed to cover a semiconductor film by a CVD method, a sputtering method, etc., However, there is a risk of poor coverage due to a step in the gate insulating film at the end of the body film. The surface of the semiconductor film is oxidized or nitrided in advance by plasma treatment. As a result, it becomes possible to prevent defects such as insufficient coverage of the gate insulating film at the end portions of the semiconductor film.

[0365] In FIG. 32, after the gate insulating film 4604 is formed, a plasma treatment is performed. Therefore, the gate insulating film 4604 may be oxidized or nitrided. In this case, the semiconductor film 46 A gate insulating film 4604 (FIG. 33(A)) is formed to cover 4603a and 4603b. By performing plasma processing and oxidizing or nitriding the gate insulating film 4604, An oxide film or a nitride film (hereinafter, also referred to as an insulating film 4623) is formed on the surface of the insulating film 4604. (FIG. 33(B)). The plasma treatment conditions are the same as those in FIG. 32(B). The insulating film 4623 contains a rare gas used in the plasma treatment. For example, Ar is used. In the case where the insulating film 4623 is etched, Ar is contained in the insulating film 4623 .

[0366] In FIG. 33B, a plasma treatment is once performed in an oxygen atmosphere to form a gate insulating film. After the film 4604 is oxidized, it is nitrided by performing plasma treatment again in a nitrogen atmosphere. In this case, the semiconductor films 4603a and 4603b may be made of silicon oxide or silicon oxynitride. A silicon nitride film (SiOxNy) (x>y) is formed in contact with the gate electrode 4605. Then, a gate electrode 460 is formed on the insulating film 4623. 5, the island-shaped semiconductor films 4603a and 4603b are formed as channel regions. The N-channel transistor 4610a and the P-channel transistor 4610b used as In this way, a semiconductor device having a gate insulating layer can be manufactured (FIG. 33(C)). The surface of the gate insulating film is oxidized or nitrided by performing a plasma treatment on the film. This process modifies the surface of the gate insulating film and forms a dense film. The insulating film obtained by this method is compared with the insulating film formed by the CVD method or the sputtering method. Since it is dense and has few defects such as pinholes, it can improve the characteristics of transistors. Cut.

[0367] In FIG. 33, semiconductor films 4603a and 4603b are subjected to plasma treatment in advance. When the surfaces of the semiconductor films 4603a and 4603b are oxidized or nitrided by this, However, the semiconductor films 4603a and 4603b are not subjected to plasma treatment, and the gate insulating film 4 A method of performing plasma treatment after forming 604 may be used. By performing plasma processing before forming the gate insulating film, Even if a coating defect occurs due to a step or other reason, the semiconductor film exposed by the coating defect can be Since the semiconductor film can be oxidized or nitrided, the gate insulating film can be covered with a poor insulating film at the edge of the semiconductor film. This can prevent short circuits between the gate electrode and the semiconductor film caused by the above problems.

[0368] In this way, even if the edge of the island-shaped semiconductor film is formed at a nearly right angle, the semiconductor The semiconductor film or the gate insulating film is subjected to a plasma treatment to oxidize or By nitriding or nitriding, the problem of the gate insulating film at the edge of the semiconductor film caused by the poor coverage of the gate insulating film is eliminated. This makes it possible to prevent short circuits between the gate electrode and the semiconductor film.

[0369] Next, in the island-shaped semiconductor film provided on the substrate, the end portion of the island-shaped semiconductor film is tapered. The case where the groove is provided in a bar shape (θ=30 to 85°) is shown.

[0370] First, island-shaped semiconductor films 4603a and 4603b are formed on a substrate 4601 (FIG. 34( A) The island-shaped semiconductor films 4603a and 4603b are formed in advance on a substrate 4601. Silicon is deposited on the insulating film 4602 by sputtering, LPCVD, plasma CVD, or the like. Amorphous semiconductor film made of silicon-based material (e.g. SiGe1-x, etc.) The amorphous semiconductor film is then crystallized by laser crystallization, RTA, or furnace annealing. The thermal crystallization method using a metal element that promotes crystallization, etc. The insulating layer can be provided by crystallizing the semiconductor film and selectively removing the semiconductor film by etching. In FIG. 34, the end of the island-shaped semiconductor film is tapered (θ=30 to 85°). .

[0371] Next, a gate insulating film 4604 is formed so as to cover the semiconductor films 4603a and 4603b. (FIG. 34(B)). The gate insulating film 4604 is formed by sputtering, LPCVD, or plasma CV. Using the D method, silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x>y), nitride A single-layer structure of an insulating film containing oxygen or nitrogen, such as silicon oxide (SiNxOy) (x>y), or Alternatively, the insulating layer 10 may be provided in a laminated structure thereof.

[0372] Next, a plasma treatment is performed to oxidize or nitride the gate insulating film 4604, An oxide film or a nitride film (hereinafter, an insulating film 4624) is formed on the surface of the gate insulating film 4604. (also referred to as a "substrate") is formed (FIG. 34(C)). The plasma treatment conditions are the same as those described above. For example, the gate insulating film 4604 can be made of silicon oxide or silicon oxynitride (Si When OxNy) (x>y) is used, plasma treatment is performed in an oxygen atmosphere to form a gate insulating film 4 By oxidizing 604, the surface of the gate insulating film is To form a dense film with fewer defects such as pinholes compared to the gate insulating film formed On the other hand, the gate insulating film 4604 can be nitrided by performing plasma treatment in a nitrogen atmosphere. As a result, a silicon oxynitride (SiN xOy) (x>y) can be set. In addition, once plasma treatment is performed in an oxygen atmosphere, After oxidizing the gate insulating film 4604 by this, the gate insulating film 4604 is again subjected to plasma treatment in a nitrogen atmosphere. The insulating film 4624 may be nitrided by performing a plasma treatment. For example, when Ar is used, Ar is contained in the insulating film 4624. .

[0373] Next, a gate electrode 4605 and the like are formed on the gate insulating film 4604 to form an island-like The semiconductor films 4603a and 4603b are used as channel regions to form an N-channel transistor. A semiconductor device having a P-channel transistor 4610a and a P-channel transistor 4610b is fabricated. This is possible (Figure 34(D)).

[0374] In this way, by performing plasma treatment on the gate insulating film, an acid is formed on the surface of the gate insulating film. By providing an insulating film made of a fluorine or nitride film, the surface of the gate insulating film can be modified. The insulating film that has been oxidized or nitrided by plasma treatment can be used as a CVD or sputtering film. Compared to gate insulating films formed by the conventional method, the insulating film is dense and has fewer defects such as pinholes. In addition, the end of the semiconductor film can be tapered. As a result, the gate electrode and the semiconductor film are separated due to the insufficient coverage of the gate insulating film at the edge of the semiconductor film. Although it is possible to suppress short circuits in the conductor film, plasma treatment after forming the gate insulating film is required. By carrying out this process, it is possible to further prevent short circuits between the gate electrode and the semiconductor film. Cut.

[0375] Next, a method for manufacturing a semiconductor device different from that shown in FIG. 34 will be described with reference to the drawings. Specifically, this relates to a case where plasma processing is selectively performed on the end of a semiconductor film having a tapered shape. and show.

[0376] First, island-shaped semiconductor films 4603a and 4603b are formed on a substrate 4601 (FIG. 35( A) The island-shaped semiconductor films 4603a and 4603b are formed in advance on a substrate 4601. Silicon is deposited on the insulating film 4602 by sputtering, LPCVD, plasma CVD, or the like. Amorphous semiconductor film made of silicon-based material (e.g. SiGe1-x, etc.) The amorphous semiconductor film is crystallized, and resists 4625a and 4625b are used as masks. The amorphous semiconductor film can be formed by selectively etching the semiconductor film. The crystallization of the semiconductor film is performed by laser crystallization, RTA, or thermal crystallization using a furnace annealing oven. a thermal crystallization method using a metal element that promotes crystallization, or a combination of these methods. This can be achieved by a crystallization method such as the crystallization method.

[0377] Next, the resists 4625a and 4625b used for etching the semiconductor film are removed. Before this, plasma treatment is performed to selectively form the ends of the island-shaped semiconductor films 4603a and 4603b. By oxidizing or nitriding, the ends of the semiconductor films 4603a and 4603b are Then, an oxide film or a nitride film (hereinafter, also referred to as an insulating film 4626) is formed (FIG. 35(B)). The plasma treatment is performed under the above-mentioned conditions. It contains rare gases.

[0378] Next, a gate insulating film 4604 is formed so as to cover the semiconductor films 4603a and 4603b. (FIG. 35C) The gate insulating film 4604 can be provided in the same manner as described above.

[0379] Next, a gate electrode 4605 and the like are formed on the gate insulating film 4604 to form an island-like The semiconductor films 4603a and 4603b are used as channel regions to form an N-channel transistor. A semiconductor device having a P-channel transistor 4610a and a P-channel transistor 4610b is fabricated. This is possible (Figure 35(D)).

[0380] When the ends of the semiconductor films 4603a and 4603b are tapered, the semiconductor film 460 The ends 4652a and 4652b of the channel regions formed in parts of 4603a and 4603b are also tapered. The thickness of the semiconductor film and the gate insulating film change compared to the central part because the shape of the hole is changed. Therefore, in this study, the plasma treatment is used to The end of the channel region is selectively oxidized or nitrided to form a semiconductor layer that is to become the end of the channel region. By forming an insulating film on the conductive film, the transistor caused by the edge of the channel region The effects of can be reduced.

[0381] In FIG. 35, only the ends of the semiconductor films 4603a and 4603b are subjected to plasma treatment. In this example, oxidation or nitridation was performed, but of course, as shown in Figure 34 above, the gate insulation The film 4604 can also be oxidized or nitrided by plasma treatment (FIG. 37( A)).

[0382] Next, a method for manufacturing a semiconductor device, which is different from the above, will be described with reference to the drawings. 2 shows a case where plasma treatment is performed on a semiconductor film having a tapered shape.

[0383] First, island-shaped semiconductor films 4603a and 4603b are formed on a substrate 4601 in the same manner as described above. (Figure 36(A)).

[0384] Next, a plasma treatment is performed to oxidize or nitride the semiconductor films 4603a and 4603b. As a result, an oxide film or a nitride film ( Hereinafter, an insulating film 4627a and an insulating film 4627b are formed (FIG. 36B). The plasma treatment can be performed under the same conditions as described above. For example, the semiconductor film 4603a, When Si is used as 4603b, the insulating film 4627a and the insulating film 4627b are Silicon oxide or silicon nitride is formed. In addition, the semiconductor film 4603a, After oxidizing 4603b, it may be nitrided by performing plasma treatment again. In this case, silicon oxide or silicon oxynitride (Si OxNy) (x>y) is formed, and silicon nitride oxide (SiNxOy) is formed on the surface of the silicon oxide. (x>y) is formed. Therefore, the insulating films 4627a and 4627b are not subjected to plasma treatment. The rare gas used in the plasma treatment is The end of 4603b is also oxidized or nitrided at the same time.

[0385] Next, a gate insulating film 4604 is formed so as to cover the insulating films 4627a and 4627b ( FIG. 36(C). The gate insulating film 4604 is formed by sputtering, LPCVD, or plasma CVD. Silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x>y), and oxynitride are produced by the method described above. A single-layer structure of an insulating film containing oxygen or nitrogen, such as silicon carbide (SiNxOy) (x>y), or For example, the semiconductor films 4603a and 4603b may be formed in a stacked structure. The semiconductor film 4603a is then oxidized by plasma treatment using Si. When silicon oxide is formed as the insulating films 4627a and 4627b on the surfaces of the insulating films 4603a and 4603b, Silicon oxide is formed as a gate insulating film over the insulating films 4627a and 4627b.

[0386] Next, a gate electrode 4605 and the like are formed on the gate insulating film 4604 to form an island-like The semiconductor films 4603a and 4603b are used as channel regions to form an N-channel transistor. A semiconductor device having a P-channel transistor 4610a and a P-channel transistor 4610b is fabricated. This is possible (Figure 36(D)).

[0387] When the end of the semiconductor film is tapered, a channel region is formed in a part of the semiconductor film. The end of the region also has a tapered shape, which may affect the characteristics of the semiconductor element. Therefore, by oxidizing or nitriding the semiconductor film by plasma treatment, the channel The edge of the hole region is also oxidized or nitrided, so that the influence on the semiconductor element can be reduced.

[0388] In FIG. 36, only the semiconductor films 4603a and 4603b are oxidized by plasma treatment. Alternatively, the gate insulating film 46 may be nitrided as shown in FIG. It is also possible to oxidize or nitride 04 by performing plasma treatment (Figure 37(B)). In this case, a plasma treatment is once performed in an oxygen atmosphere to convert the gate insulating film 4604 into an oxygen-based insulating film. After the nitridation, the nitridation may be performed again by performing a plasma treatment in a nitrogen atmosphere. In this case, the semiconductor films 4603a and 4603b are made of silicon oxide (SiOx) or silicon oxynitride. (SiOxNy) (x>y) is formed, and silicon oxynitride (SiOxNy) is formed in contact with the gate electrode 4605. iNxOy) (x>y) is formed.

[0389] At this time, the dust 4673 can be removed by simple cleaning such as brush cleaning, and the like, by removing the dust from the surface of the insulating film 4674. In this way, the plasma treatment makes the Even if the dust is minute, it becomes easy to remove the dust attached to the insulating film or semiconductor film. This is an effect obtained by performing plasma processing, and is not limited to this embodiment. The same is true for the other embodiments.

[0390] In this way, the semiconductor film or the gate insulating film is oxidized or nitrided by performing plasma processing. By modifying the surface, it is possible to form a dense insulating film with good film quality. It is possible to easily remove dirt and other particles adhering to the surface of the film by cleaning. As a result, Even when a thin insulating film is formed, defects such as pinholes are prevented, and the insulating film can be formed in a thin film. This makes it possible to realize miniaturization and high performance of semiconductor elements.

[0391] In this embodiment, the semiconductor films 4603a and 4603b in FIG. The gate insulating film 4604 is subjected to plasma treatment, and the semiconductor films 4603a and 4603b are Alternatively, the gate insulating film 4604 is oxidized or nitrided by using a plasma treatment. The layer to be nitrided is not limited to the above. Alternatively, the insulating film 4606 or the insulating film 4607 may be subjected to plasma treatment. may be carried out.

[0392] The contents described in this embodiment may be freely combined with the contents described in embodiment 1 or embodiment 2. It is possible. EXAMPLES

[0393] In this embodiment, a mask pattern for manufacturing a semiconductor device including a transistor is An example will be described with reference to FIGS.

[0394] The semiconductor layers 5610 and 5611 shown in FIG. 41(A) are made of silicon or a material containing silicon. For example, a silicon film is preferably formed of a crystalline semiconductor such as a silicon film annealed by laser. Polycrystalline silicon and single crystal silicon crystallized by such methods are also used. By applying metal oxide semiconductors, amorphous silicon, and organic semiconductors that exhibit semiconducting properties, It is also possible.

[0395] In any case, the semiconductor layer formed first is formed on the entire surface or a part of the substrate having an insulating surface. (A region having an area larger than that determined as the semiconductor region of a transistor) Then, a mask pattern is formed on the semiconductor layer by photolithography. The semiconductor layer is etched using this mask pattern to produce a transistor. A semiconductor layer having a specific shape including a source region, a drain region and a channel forming region of the transistor. The semiconductor layers 5610 and 5611 are formed according to the appropriate layout. It is decided taking into consideration.

[0396] The photomask for forming the semiconductor layers 5610 and 5611 shown in FIG. 41(B). This mask pattern 5630 is The difference is whether the resist used in the photolithography process is positive or negative. When using a mask, the mask pattern 5630 shown in FIG. 41(B) is made as a light shielding portion. The mask pattern 5630 is a polygon with the apex A removed. In addition, at the bend B, the corner is bent in multiple stages so that it is not a right angle. The pattern of this photomask has, for example, a corner of the pattern (a right angle The corners of the triangle are removed so that one side is 10 μm or less.

[0397] The mask pattern 5630 shown in FIG. 41(B) has a shape similar to that of the semiconductor shown in FIG. In this case, the shape of the mask pattern 5630 is similar to that of the substrate layers 5610 and 5611. However, it is preferable to transfer the mask pattern 5630 so that the corners of the mask pattern 5630 are more rounded. That is, the pattern shape may be further narrowed than the mask pattern 5630. A rounded portion may be provided to make the surface smooth.

[0398] At least one silicon oxide or silicon nitride is formed on the semiconductor layers 5610 and 5611. One of the purposes of forming this insulating layer is to function as a gate insulating layer. Then, as shown in FIG. 42(A), a gate wiring 57 is provided so as to overlap a part of the semiconductor layer. 12, 5713, and 5714 are formed. The gate wiring 5712 corresponds to the semiconductor layer 5610. The gate wiring 5713 is formed corresponding to the semiconductor layers 5610 and 5611. In addition, the gate wiring 5714 is formed corresponding to the semiconductor layers 5610 and 5611. The wiring is formed by depositing a metal layer or a highly conductive semiconductor layer and then aligning the layers by photolithography. The shape is then formed on the insulating layer.

[0399] The photomask for forming the gate wiring is a mask pattern shown in FIG. This mask pattern 5731 is a corner portion (right-angled triangle). One side is 10μm or less, or the size is 1 / 2 or less and 1 / 5 or more of the line width of the wiring The corners are removed. The mask pattern 5731 shown in FIG. This is reflected in the gate wirings 5712, 5713, and 5714 shown in FIG. A shape similar to the mask pattern 5731 may be transferred, but the corners of the mask pattern 5731 may be The mask pattern 573 may be transferred so that the portion is more rounded. The pattern shape may be smoother than that of the gate electrode 1, and a rounded portion may be provided. The corners of the wirings 5712, 5713, and 5714 are 1 / 2 or less and 1 / 5 or more of the line width. The corners are rounded. The protruding parts are damaged by abnormal discharge during dry etching with plasma. In the recesses, the generation of fine powder is suppressed, and even if fine powder is generated during cleaning, it is not easily absorbed into the corners. As a result of washing away the dirt that tends to accumulate in the Yes.

[0400] The interlayer insulating layer is a layer formed next to the gate wirings 5712, 5713, and 5714. The insulating layer is made of inorganic insulating material such as silicon oxide, polyimide, acrylic resin, etc. The interlayer insulating layer and the gate wiring 5712, 5713, 5714 are formed using an organic insulating material. An insulating layer such as silicon nitride or silicon oxynitride may be interposed between 14 . In addition, an insulating layer such as silicon nitride or silicon oxynitride may be provided on the interlayer insulating layer. This insulating layer is highly resistant to exogenous metal ions, moisture, and other insulators that are bad for transistors. This makes it possible to prevent the semiconductor layer and the gate insulating layer from being contaminated by impurities.

[0401] The interlayer insulating layer has openings at predetermined positions. For example, the gate wiring and It is provided corresponding to the semiconductor layer. It is formed of one or more layers of metal or metal compound. The wiring layer is formed by forming a mask pattern using photolithography technology and etching. Then, as shown in FIG. 43(A), the semiconductor Wires 5815 to 5820 are formed so as to overlap with the layers. The wiring is not a straight line between specific elements, but is a flexibly connected line according to the layout constraints. It includes bends, and the line width changes at contacts and other areas. In the contact area, if the contact hole is equal to or larger than the wiring width, the wiring is formed in that area. It changes to widen.

[0402] The photomask for forming the wirings 5815 to 5820 is the one shown in FIG. In this case, the wiring is also at the corners. One side of the right triangle is 10μm or less, or 1 / 2 the line width of the wiring. The corners are removed to 1 / 5 or more of their original size, and the corners are rounded. In such wiring, the protruding parts are subject to the generation of fine powder due to abnormal discharge during dry etching using plasma. In the recesses, even if fine powder is generated during cleaning, it will not gather in the corners and will not be easily damaged. As a result of washing away the dirt, the yield can be expected to increase significantly. By making the corners of the wire rounded, it is expected that it will also conduct electricity. With many parallel wires, it is very convenient to wash away the dirt.

[0403] FIG. 43A shows N-channel transistors 5821 to 5824 and P-channel transistors 5822 to 5824. The N-channel transistors 5825 and 5826 are formed. A channel transistor 5825, an N-channel transistor 5824, and a P-channel The transistor 5826 constitutes inverters 5827 and 5828. The circuitry containing these transistors forms an SRAM. An insulating layer such as silicon nitride or silicon oxide may be formed.

[0404] The contents described in this embodiment may be freely combined with the contents described in the first to third embodiments. It is possible. EXAMPLES

[0405] In this embodiment, a structure in which a substrate on which pixels are formed is sealed will be described with reference to FIG. FIG. 25(A) shows a panel formed by sealing a substrate on which pixels are formed. 25(B) and 25(C) are top views of the casing at A-A' in FIG. 25(A), respectively. 25(B) and 25(C) are examples in which sealing is performed by different methods. do.

[0406] In FIG. 25(A) to FIG. 25(C), a display having a plurality of pixels is provided on a substrate 2501. A pixel portion 2502 is disposed, and a sealant 2506 is provided so as to surround the pixel portion 2502. A sealant 2507 is attached. The structure of the pixel is the same as that of the above-mentioned embodiment of the invention. For this purpose, the best mode or the configuration shown in the first embodiment can be used.

[0407] In the display panel of FIG. 25(B), the sealing material 2507 of FIG. 25(A) is A transparent counter substrate 2521 is attached using a sealant 2506 as an adhesive layer. The substrate 2501, the counter substrate 2521, and the sealant 2506 form a sealed space 2 On the opposing substrate 2521, a color filter 2520 and A protective film 2523 for protecting the capacitor is provided. The light emitted is emitted to the outside through the color filter 2520. The sealed space 2522 is filled with an inactive resin or liquid. The resin may be a light-transmitting resin in which a moisture-absorbing material is dispersed. The material filled in the sealed space 2522 and the opposing substrate 2521 is the same material. The attachment and sealing of the pixel portion 2502 may be performed at the same time.

[0408] In the display panel shown in FIG. 25(C), the sealant 2507 in FIG. 25(A) is The sealing material 2506 is used as an adhesive layer to form the sealing material 2504. 24 is attached, and the substrate 2501, the seal material 2506, and the sealing material 2524 are A sealed space 2508 is formed by this. The sealant 2524 has a moisture absorbent 25 09 is provided inside the sealed space 2508, and absorbs moisture, oxygen, etc. to keep the inside clean. This recess is made of a fine mesh. The cover material 2510 is covered with a hygroscopic material 2510. The cover material 2510 is permeable to air and moisture, but is The airtight space 2508 is filled with nitrogen or a rare gas such as argon. It is possible to fill the space with a resin or liquid if the resin or liquid is inactive.

[0409] An input terminal section 2511 for transmitting signals to a pixel section 2502 and the like is provided on a substrate 2501. The input terminal portion 2511 is connected to an FPC (flexible printed circuit) 251 Signals such as video signals are transmitted through the input terminal section 2511. The formed wiring and the wiring on the FPC2512 are bonded to a resin (anisotropic The electrical connections are made using ACF (acoustic conductive resin).

[0410] A driving circuit for inputting a signal to the pixel portion 2502 is provided on a substrate 2501 on which the pixel portion 2502 is formed. The driver circuit for inputting signals to the pixel portion 2502 may be integrated into an IC chip. Alternatively, the chip may be formed by a chip-on-glass (COG) method and connected to the substrate 2501. The IC chip is then attached using TAB (Tape Auto Bonding) or a printed circuit board. The semiconductor device may be disposed on the substrate 2501 .

[0411] This embodiment can be freely combined with the first to fourth embodiments. EXAMPLES

[0412] The present invention is applied to a display module in which a circuit for inputting a signal to a panel is mounted on the panel. It is possible.

[0413] FIG. 26 shows a display module in which a panel 2600 and a circuit board 2604 are combined. In FIG. 26, a controller 2605, a signal division circuit 2606, etc. are mounted on a circuit board 2604. The circuit formed on the circuit board 2604 is not limited to this. No. Any circuit can be formed as long as it generates signals to control the panel. good.

[0414] Signals output from these circuits formed on the circuit board 2604 are transmitted through the connection wiring 260 7 is entered into panel 2600.

[0415] The panel 2600 includes a pixel section 2601, a source driver 2602, and a gate driver 2603. The configuration of the panel 2600 is similar to that shown in the first and second embodiments. In FIG. 26, a substrate having a pixel portion 2601 and a semiconductor device 2602 are formed on the same substrate. In the example shown, a source driver 2602 and a gate driver 2603 are formed. However, the display module of the present invention is not limited to this. Only the gate driver 2603 is formed on one substrate, and the source driver is formed on a circuit board. Both the source driver and the gate driver may be formed on the circuit board. It's fine if you're there.

[0416] By incorporating such a display module, the display section of various electronic devices can be formed. Cut.

[0417] This embodiment can be freely combined with the first to fifth embodiments. EXAMPLES

[0418] In this embodiment, an electronic device according to the present invention will be described. video camera, digital camera, etc.), projector, head mounted display (go-camera, display), navigation systems, car stereos, personal computers data, game devices, mobile information terminals (mobile computers, mobile phones, e-books, etc.), An image reproducing device equipped with a recording medium (specifically, a Digital Versatile Di A device equipped with a display that can play back recording media such as DVDs and display the images. ) Representative examples of electronic devices are shown in Figure 27.

[0419] FIG. 27A shows a personal computer, which includes a main body 2711, a housing 2712, a display 2713, keyboard 2714, external connection port 2715, pointing mouse 27 16, etc. The present invention is applied to the display unit 2713. By using the present invention, The power consumption of the display unit can be reduced.

[0420] FIG. 27(B) shows an image reproducing device (specifically, a DVD reproducing device) equipped with a recording medium. A main body 2721, a housing 2722, a first display unit 2723, a second display unit 2724, and a recording medium. It includes a reading section 2725 (DVD, etc.), operation keys 2726, a speaker section 2727, etc. The first display unit 2723 mainly displays image information, and the second display unit 2724 mainly displays text information. The present invention is applied to the first display unit 2723 and the second display unit 2724. By using the present invention, it is possible to reduce the power consumption of the display unit.

[0421] FIG. 27C shows a mobile phone, which includes a main body 2731, a voice output unit 2732, and a voice input unit 27 33, a display unit 2734, an operation switch 2735, an antenna 2736, etc. This is applied to the display unit 2734. By using the present invention, the power consumption of the display unit can be reduced. It is possible.

[0422] FIG. 27D shows a camera, which includes a main body 2741, a display unit 2742, a housing 2743, and an external connection Connection port 2744, remote control receiver 2745, image receiver 2746, battery 2747, sound The voice input unit 2748 and the operation keys 2749 are included. The present invention is applied to the display unit 2742. By using the present invention, it is possible to reduce the power consumption of the display unit.

[0423] This embodiment can be freely combined with the first to sixth embodiments. [Explanation of symbols]

[0424] 10 Circuit 11 Input terminal 12 Input terminals 13 Input terminal 14 Output terminal 31 Transistor 32 Transistor 33 Capacitive element 34 Circuit 35 Circuit 41 Transistor 42 Transistor 50 circuits 51 Input terminal 52 Input terminal 53 Input terminal 54 Input terminal 55 Output terminal 61 Circuit 62 Circuits 71 Transistor 72 Transistor 73 Transistor 81 Circuit 82 Circuit 83 Circuit 91 Transistor 92 Transistor 93 Transistor 94 Transistor 95 Transistors 101 Transistor 102 Resistance element 102 Transistor 103 Transistor 104 Capacitive element 111 Circuit 121 Transistor 122 Transistor 123 Transistor 124 Transistor 125 Transistor 131 Shift Register Circuit 151 Shift Register Circuit 152 Level shift circuit 171 Shift Register Circuit 172 Level shift circuit 191 Shift Register Circuit 192 circuits 211 pixels 212 Gate Driver 221 Source Driver 231 Transistor 232 Capacitive element 233 Liquid crystal element 234 Counter Electrode 241 Transistor 242 Transistor 243 Capacitive element 244 Light-emitting element 245 Counter Electrode 251 Transistor 252 Transistor 253 Transistor 254 Capacitive element 261 Transistor 262 Transistor 263 Transistor 254 Transistor 264 Transistor 265 Capacitive Element 266 Constant Voltage Line 481 Transistor 501 Transistor 502 Resistance element 503 Transistor 504 Transistor 505 Circuit 551 Transistor 552 Transistor 553 Capacitive element 554 circuits 555 Circuit 561 Circuit 562 circuits 571 Circuit 572 circuits 573 Circuit 581 circuits 591 Transistor 592 Transistor 601 Transistor 602 Transistor 603 Transistor 2400 Board 2401 Base film 2402 Semiconductor layer 2403 Insulating film 2404 Gate electrode 2405 Insulating film 2406 Electrode 2407 Electrode 2408 Insulating film 2409 Light-emitting layer 2410 Transistor 2411 Capacitive element 2412 Semiconductor layer 2414 Electrode 2415 Light emitting element 2416 Electrode 2417 Electrode 2418 Insulating film 2501 Board 2502 Pixel section 2506 Sealing material 2507 Sealant 2508 Closed space 2509 Moisture absorbent 2510 Cover material 2511 Input terminal section 2512 FPC 2520 Color Filter 2521 Opposing substrate 2522 Closed space 2523 Protective film 2524 Sealant 2600 Panel 2601 Pixel section 2602 Source Driver 2603 Gate Driver 2604 Circuit Board 2605 Controller 2606 Signal splitting circuit 2607 Connection Wiring 2711 Main unit 2712 Case 2713 Display section 2714 Keyboard 2715 External connection port 2716 Pointing Mouse 2721 Main unit 2722 Case 2723 Display section 2724 Display section 2725 Recording medium reading unit 2726 Operation Key 2727 Speaker section 2731 Main unit 2732 Audio output section 2733 Audio input section 2734 Display section 2735 Operation switch 2736 Antenna 2741 Main unit 2742 Display section 2743 Case 2744 External connection port 2745 Remote control receiver 2746 Image receiving unit 2747 Battery 2748 Audio input section 2749 Operation key 2801 Board 2802 Base film 2803 Pixel electrode 2804 Electrode 2805 Wiring 2806 Wiring 2807 N-type semiconductor layer 2808 N-type semiconductor layer 2809 Semiconductor layer 2810 Gate insulating film 2811 Insulating film 2812 Gate electrode 2813 Electrode 2814 Interlayer insulating film 2815 Layer containing organic compounds 2816 Counter electrode 2817 Light emitting element 2818 Drive transistor 2819 Capacitive element 2820 electrode 2901 Board 2903 Gate electrode 2904 Electrode 2905 Gate insulating film 2906 Semiconductor layer 2907 Semiconductor layer 2908 N-type semiconductor layer 2909 N-type semiconductor layer 2910 N-type semiconductor layer 2911 Wiring 2912 Wiring 2913 Conductive layer 2914 Pixel electrode 2915 Insulating layer 2917 Counter electrode 2918 Light emitting element 2919 Drive transistor 2920 Capacitive element 2921 Electrode 3001 Insulation layer 4601 Substrate 4602 Insulating film 4603a Semiconductor film 4603b Semiconductor film 4604 Gate insulating film 4605 Gate electrode 4606 Insulating film 4607 Insulating film 4608 Conductive film 4610a N-channel transistor 4610b P-channel transistor 4621a Insulating film 4621b Insulating film 4623 Insulating film 4624 Insulating film 4625a Resist 4625b Resist 4626 Insulating film 4627a Insulating film 4627b Insulating film 4651a End of channel region 4651b End of channel region 4652a End of channel region 4652b End of channel region 4671 Membrane 4672 Insulating film 4673 Garbage 4674 Insulating film 4675 Insulating film 5401 N-channel transistor 5402 N-channel transistor 5403 P-channel transistor 5404 Capacitive element 5405 Resistor element 5502 Conductive layer 5503 Conductive layer 5504 Wiring 5505 Semiconductor layer 5506 Impurity region 5507 Impurity region 5508 Insulation layer 5509 Gate electrode 5510 Impurity region 5511 Impurity region 5512 Impurity region 5610 Semiconductor layer 5611 Semiconductor layer 5630 Mask Pattern 5712 Gate wiring 5713 Gate wiring 5714 Gate wiring 5731 Mask Pattern 5800 Decoder Type Gate Driver 5801 Input terminal 5802 2nd input terminal 5803 3rd input terminal 5804 Input terminal 5805 Level Shifter 5806 Buffer Circuit 5815 Wiring 5816 Wiring 5817 Wiring 5818 Wiring 5819 Wiring 5820 Wiring 5821 N-channel transistor 5822 N-channel transistor 5823 N-channel transistor 5824 N-channel transistor 5825 P-channel transistor 5826 P-channel transistor 5827 Inverter 5828 Inverter 5832 Mask Pattern 9000 Source Driver

Claims

1. A semiconductor device comprising first to sixth transistors, one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a first clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the second transistor is always electrically connected to a first wiring; a gate of the second transistor is always electrically connected to a first signal line; one of the source and the drain of the third transistor is always electrically connected to the gate signal line; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the gate of the fourth transistor is always electrically connected to the second signal line; one of the source and the drain of the fifth transistor is always electrically connected to the gate signal line; a gate of the fifth transistor is always electrically connected to the second signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate signal line; a gate of the sixth transistor is always electrically connected to a second clock signal line; A potential corresponding to the first clock signal line is input to a gate of the third transistor.

2. A semiconductor device comprising first to sixth transistors, one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a first clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the second transistor is always electrically connected to a first wiring; a gate of the second transistor is always electrically connected to a first signal line; one of the source and the drain of the third transistor is always electrically connected to the gate signal line; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the gate of the fourth transistor is always electrically connected to the second signal line; one of the source and the drain of the fifth transistor is always electrically connected to the gate signal line; a gate of the fifth transistor is always electrically connected to the second signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate signal line; a gate of the sixth transistor is always electrically connected to a second clock signal line; a potential corresponding to the first clock signal line is input to a gate of the third transistor; A semiconductor device, wherein a channel width of the first transistor is larger than a channel width of the second transistor.

3. A semiconductor device according to claim 1 or claim 2, and a pixel, the pixel includes a seventh transistor; One of the source and the drain of the seventh transistor is always electrically connected to a liquid crystal element; the other of the source and the drain of the seventh transistor is always electrically connected to a third signal line; A display device, wherein the gate of the seventh transistor is always electrically connected to the gate signal line.

Images