Semiconductor Device

Abstract

To provide an imaging apparatus with a light source.SOLUTION: In an imaging apparatus having a light emitting device and a photoelectric conversion device in a pixel, a pixel circuit has a function to output third data that is obtained by multiplying acquired first data by second data (weight). By calculating the third data externally, more detailed information on the subject for a specific wavelength can be obtained. It is also possible to read multiple pixels with appropriate weights together to output the difference data between pixels or other data, thereby eliminating the need for external calculations.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification etc. relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. More specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, a driving method thereof, or a manufacturing method thereof.

[0003] Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Further, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device. [Background technology]

[0004] A technology for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device in which a transistor that includes an oxide semiconductor and has an extremely low off-state current is used in a pixel circuit. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2011-119711 A Summary of the Invention [Problem to be solved by the invention]

[0006] Imaging devices are not only used as a means of converting visible light into an image, but are also used for a variety of purposes, such as personal authentication, defect analysis, medical diagnosis, and security. In these applications, in addition to visible light, short-wavelength light such as X-rays and long-wavelength light such as infrared light are used according to the purpose.

[0007] For visible light and infrared light, natural light or indoor light may be used, but it is becoming more common to use dedicated light sources. Light bulbs, LEDs, lasers, etc. are used as light sources, but there are issues with making them smaller and thinner when combined with an imaging device.

[0008] Therefore, an object of one embodiment of the present invention is to provide an imaging device having a light source. Another object is to provide an imaging device having a thin light source and capturing an image of light emitted from the light source and reflected from a subject. Another object is to provide an imaging device having a thin infrared light source. Another object is to provide an imaging device capable of performing product-sum calculations on a plurality of pixels.

[0009] Another object is to provide an imaging device with low power consumption. Another object is to provide an imaging device that can perform imaging at high speed. Another object is to provide an imaging device with high reliability. Another object is to provide a novel imaging device. Another object is to provide a method for operating the imaging device. Another object is to provide a novel semiconductor device or the like.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention relates to a thin imaging device having a light source or an imaging device capable of performing calculations.

[0012] One embodiment of the present invention is an imaging device having a first pixel, a second pixel, a first correlated double sampling circuit, a second correlated double sampling circuit, and an A / D conversion circuit, where the first pixel and the second pixel each have a light-emitting device and a photoelectric conversion device, the first pixel is electrically connected to the first correlated double sampling circuit, the second pixel is electrically connected to the first correlated double sampling circuit, the first correlated double sampling circuit is electrically connected to the second correlated double sampling circuit, and the second correlated double sampling circuit is electrically connected to the A / D conversion circuit, and the first pixel, the second pixel, the first correlated double sampling circuit, and the second correlated double sampling circuit have transistors having metal oxide in their channel formation regions.

[0013] The first pixel and the second pixel each have a first transistor as a transistor, and further a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first pixel and the second pixel each further have a first capacitor, a second capacitor, and a memory circuit. One of the source or drain of the first transistor is electrically connected to one electrode of the photoelectric conversion device, the other of the source or drain of the first transistor is electrically connected to one electrode of the first capacitor, and the one electrode of the first capacitor is electrically connected to one of the source or drain of the second transistor. The other of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor, one of the source or drain of the third transistor is electrically connected to one electrode of the second capacitor, one electrode of the second capacitor is electrically connected to the gate of the fourth transistor, one of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the fifth transistor, the other of the source or drain of the fifth transistor is electrically connected to the first correlated double sampling circuit, and the other electrode of the second capacitor is electrically connected to the memory circuit.

[0014] The memory circuit has a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, and the memory circuit further has a third capacitor, one of a source or a drain of the sixth transistor being electrically connected to one electrode of the third capacitor, one electrode of the third capacitor being electrically connected to a gate of the seventh transistor, one of a source or a drain of the seventh transistor being electrically connected to one of a source or a drain of the eighth transistor, the other of the source or a drain of the seventh transistor being electrically connected to one of a source or a drain of the ninth transistor, and one of a source or a drain of the ninth transistor being electrically connected to the other electrode of the second capacitor.

[0015] The other of the source or the drain of the fifth transistor included in the first pixel may be electrically connected to the other of the source or the drain of the fifth transistor included in the second pixel, and the gate of the fifth transistor included in the first pixel may be electrically connected to the gate of the fifth transistor included in the second pixel.

[0016] The first wavelength can be smaller than the second wavelength, and the light-emitting devices included in the first pixel and the second pixel can emit near-infrared light including the first wavelength and the second wavelength. The photoelectric conversion device included in the first pixel can have an absorption edge wavelength shorter than the second wavelength, and the photoelectric conversion device included in the second pixel can have an absorption edge wavelength equal to or greater than the second wavelength.

[0017] In addition, a configuration may be adopted in which the first wavelength is smaller than the second wavelength, the light-emitting device included in the first pixel emits near-infrared light having a peak at the first wavelength, the light-emitting device included in the second pixel emits near-infrared light having a peak at the second wavelength, the photoelectric conversion device included in the first pixel has an absorption edge wavelength shorter than the second wavelength, and the photoelectric conversion device included in the second pixel has an absorption edge wavelength equal to or greater than the second wavelength.

[0018] Alternatively, a configuration may be adopted in which the first wavelength is smaller than the second wavelength, the light emitting device of the first pixel emits near-infrared light having a peak at the first wavelength, the light emitting device of the second pixel emits near-infrared light having a peak at the second wavelength, and the photoelectric conversion devices of the first pixel and the second pixel have absorption edge wavelengths equal to or greater than the second wavelength. In this configuration, the first pixel may be provided with a first optical filter layer that selectively transmits light of the first wavelength and its vicinity, and the second pixel may be provided with a second optical filter layer that selectively transmits light of the second wavelength and its vicinity.

[0019] The first pixel, the second pixel, the first correlated double sampling circuit and the second correlated double sampling circuit may be provided between a first flexible substrate and a second flexible substrate opposing the first flexible substrate.

[0020] The metal oxide preferably contains In, Zn, and M (M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf). Effect of the Invention

[0021] By using one embodiment of the present invention, an imaging device having a light source can be provided. Alternatively, an imaging device having a thin light source and capable of capturing an image of light emitted from the light source and reflected from a subject can be provided. Alternatively, an imaging device having a thin infrared light source can be provided. Alternatively, an imaging device capable of performing product-sum calculations on a plurality of pixels can be provided.

[0022] Alternatively, it is possible to provide an imaging device with low power consumption. Alternatively, it is possible to provide an imaging device that can perform imaging at high speed. Alternatively, it is possible to provide an imaging device with high reliability. Alternatively, it is possible to provide a novel imaging device. Alternatively, it is possible to provide a method for operating the imaging device. Alternatively, it is possible to provide a novel semiconductor device or the like. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a block diagram illustrating an imaging device. [Diagram 2] 2A to 2C are diagrams illustrating a pixel array. [Diagram 3] FIG. 3 is a diagram illustrating a pixel circuit. [Figure 4] Fig. 4A is a diagram for explaining the rolling shutter method, and Fig. 4B is a diagram for explaining the global shutter method. [Diagram 5] FIG. 5 is a diagram illustrating the read circuit. [Figure 6] FIG. 6 is a timing chart illustrating the operation of the imaging device. [Figure 7] FIG. 7 is a block diagram illustrating the imaging device. [Figure 8] 8A to 8C are diagrams illustrating a light-emitting device and a photoelectric conversion device. [Figure 9] 9A to 9C are diagrams illustrating a pixel circuit. [Figure 10] 10A to 10C are diagrams illustrating a pixel circuit. [Figure 11] 11A to 11C are diagrams illustrating a pixel circuit. [Figure 12] 12A to 12C are diagrams illustrating a pixel circuit. [Figure 13] 13A and 13B are diagrams illustrating a pixel circuit. [Figure 14] 14A to 14C are diagrams illustrating the configuration of a pixel of an imaging device, the configuration of a photoelectric conversion device, and the configuration of a light emitting device. [Figure 15] FIG. 15 is a diagram illustrating the configuration of a pixel in an imaging device. [Figure 16] 16A to 16D are diagrams illustrating a transistor. [Figure 17] 17A1, 17A2, 17B1, and 17B2 are diagrams for explaining electronic devices. [Figure 18] 18A and 18B are diagrams illustrating an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, hatching of the same elements constituting the drawings may be omitted or changed as appropriate between different drawings.

[0025] In addition, even if a circuit diagram shows a single element, the element may be composed of multiple elements as long as there is no functional problem. For example, a transistor that operates as a switch may be connected in series or parallel in multiple units. Also, a capacitor (also called a capacitive element) may be divided and placed in multiple positions.

[0026] In addition, one conductor may have multiple functions such as wiring, an electrode, and a terminal, and in this specification, multiple names may be used for the same element. Even if elements are shown as being directly connected to each other on a circuit diagram, the elements may actually be connected to each other via multiple conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0027] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0028] One embodiment of the present invention is an imaging device having a light-emitting device and a photoelectric conversion device in a pixel. Light emitted by the light-emitting device and reflected by a subject is received by the photoelectric conversion device. Since an EL element is used for the light-emitting device, a thin imaging device with a light source can be formed.

[0029] It is also possible to provide a configuration in which a plurality of EL elements with different emission wavelengths are provided, and a configuration in which a plurality of photoelectric conversion devices with different light receiving wavelengths are provided, thereby making it possible to obtain information on the subject for a plurality of wavelengths.

[0030] The imaging device also has a function of outputting third data obtained by multiplying the first data acquired by the pixels by the second data (weight). By performing external calculations on the third data, more detailed information on the subject for a specific wavelength can be obtained. Furthermore, by collectively reading out multiple pixels to which appropriate weights have been assigned, it is also possible to output differential data between pixels, and external calculations can be omitted.

[0031] In addition, by using an element that emits infrared light as a light-emitting device, it can be used for applications such as biometric authentication, physical activity measurement, defect analysis of industrial products, selection of agricultural products, etc. In addition, by using a pixel circuit that can capture images using the global shutter method, it is possible to obtain images without distortion even of moving subjects.

[0032] <Imaging device> 1 is a block diagram illustrating an imaging device according to one embodiment of the present invention. The imaging device includes a pixel array 21 having pixels arranged in a matrix, a circuit 22 (row driver) having a function of selecting a row of the pixel array 21, a circuit 23 having a function of reading data from a pixel circuit 10, and a circuit 28 that supplies a power supply potential. The pixel includes the pixel circuit 10 and a light-emitting device 11.

[0033] The circuit 23 is a readout circuit, and may include a circuit 24 (first CDS circuit) for performing correlated double sampling on the output data of the pixel circuit 10, a circuit 25 (second CDS circuit) for performing correlated double sampling on the output data of the circuit 24, a circuit 26 (A / D conversion circuit or the like) having a function of converting analog data output from the circuit 25 into digital data, and a circuit 27 (column driver) having a function of selecting a column of the pixel array 21 from which data is to be read out. The circuit 23 may also include a current source circuit or the like.

[0034] It is also possible to adopt a configuration in which the pixel circuits 10 and the light-emitting devices 11 do not overlap. For example, as shown in Fig. 2A, the pixel circuits 10 and the light-emitting devices 11 may be arranged alternately at regular intervals. Also, as shown in Fig. 2B, the pixel circuits 10 and the light-emitting devices 11 may be arranged alternately for each row. As a modification of the configuration shown in Fig. 2B, the light-emitting devices 11 may be arranged to extend in one direction as shown by the dashed line.

[0035] 2C, a light emitting device 11 may be disposed between two adjacent pixel circuits 10. In this case, the light emitting device 11 is disposed to have an overlapping area with wiring connected to the pixel circuit 10. Note that although the same number of light emitting devices 11 as the pixel circuits 10 are illustrated in FIGS. 2A to 2C, the number of light emitting devices 11 may be different from the number of pixel circuits 10.

[0036] <Pixel circuit> 3 is a circuit diagram illustrating a pixel circuit 10 that can be used in the imaging device of one embodiment of the present invention. The pixel circuit 10 can include a photoelectric conversion device 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, a transistor 106, a capacitor 107, a capacitor 108, and a memory circuit 30. Note that a structure in which the capacitor 107 is not provided is also possible.

[0037] One electrode (cathode) of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102. The other of the source or drain of the transistor 102 is electrically connected to one electrode of the capacitor 107. One electrode of the capacitor 107 is electrically connected to one of the source or drain of the transistor 103. The other of the source or drain of the transistor 103 is electrically connected to one of the source or drain of the transistor 104. One of the source or drain of the transistor 104 is electrically connected to one electrode of the capacitor 108. One electrode of the capacitor 108 is electrically connected to the gate of the transistor 105. One of the source or drain of the transistor 105 is electrically connected to one of the source or drain of the transistor 106. The other electrode of the capacitor 108 is electrically connected to the memory circuit 30.

[0038] The memory circuit 30 may include a transistor 110 , a transistor 111 , a transistor 112 , a transistor 113 , and a capacitor 114 .

[0039] One of the source or drain of the transistor 110 is electrically connected to one electrode of the capacitor 114. One electrode of the capacitor 114 is electrically connected to the gate of the transistor 112. One of the source or drain of the transistor 112 is electrically connected to one of the source or drain of the transistor 111. The other of the source or drain of the transistor 112 is electrically connected to one of the source or drain of the transistor 113. The one of the source or drain of the transistor 113 is electrically connected to the other electrode of the capacitor 108.

[0040] Here, a wiring that connects the other of the source or drain of the transistor 102, one electrode of the capacitor 107, and one of the source or drain of the transistor 103 is referred to as a node FD1. A wiring that connects the other of the source or drain of the transistor 103, one of the source or drain of the transistor 104, one electrode of the capacitor 108, and the gate of the transistor 105 is referred to as a node FD2.

[0041] The node FD1 can function as a charge storage unit, and the node FD2 can function as a charge detection unit.

[0042] In the memory circuit 30, a wiring that connects one of the source or drain of the transistor 110, one electrode of the capacitor 114, and the gate of the transistor 112 is defined as a node NW1. A wiring that connects the other of the source or drain of the transistor 112, one of the source or drain of the transistor 113, and the other electrode of the capacitor 108 is defined as a node NW2.

[0043] The node NW1 can function as a data storage node, and the node NW2 can function as a data read node.

[0044] The other electrode (anode) of the photoelectric conversion device 101 is electrically connected to a wiring 121. The gate of the transistor 102 is electrically connected to a wiring 124. The gate of the transistor 103 is electrically connected to a wiring 125. The other of the source or drain of the transistor 104 and the other of the source or drain of the transistor 105 are electrically connected to a wiring 122. The gate of the transistor 104 is electrically connected to a wiring 126. The gate of the transistor 106 is electrically connected to a wiring 127. The other of the source or drain of the transistor 106 is electrically connected to a wiring 123. The other electrode of the capacitor 107 is electrically connected to a reference potential line such as a GND wiring.

[0045] In the memory circuit 30, the other of the source and the drain of the transistor 110 is electrically connected to a wiring 133. The other of the source and the drain of the transistor 111 is electrically connected to a wiring 134. The other of the source and the drain of the transistor 113 is electrically connected to a wiring 135. The other electrode of the capacitor 114 is electrically connected to a reference potential line such as a GND wiring.

[0046] The wirings 124, 125, 126, 127, 136, 137, and 138 can function as signal lines that control the conduction of each transistor.

[0047] 3, the cathode side of the photoelectric conversion device 101 is electrically connected to the transistor 102, and the nodes FD1 and FD2 are reset to high potential for operation, so the wiring 122 has a high potential (a higher potential than the wiring 121).

[0048] In the memory circuit 30, the transistor 112 and the transistor 113 operate as source followers and can read the potential of the node NW1 to the node NW2. The wiring 134 and the wiring 135 can function as power supply lines for operating the transistor 112, and the wiring 134 has a high potential (a higher potential than the wiring 135).

[0049] The wiring 123 can function as an output line. The wiring 133 in the memory circuit can function as a signal line for writing data (weight).

[0050] A photodiode can be used as the photoelectric conversion device 101. In one embodiment of the present invention, imaging is performed using infrared light. Therefore, the photoelectric conversion device 101 is a photodiode that can photoelectrically convert at least light in the infrared region.

[0051] For example, a photodiode having an organic photoconductive film in the photoelectric conversion layer can be used. The organic photoconductive film is a thin film, and can be bent if the supporting substrate is flexible. Therefore, it is suitable for forming a flexible imaging device. In addition, it is easy to increase the size of the imaging device. Note that a photoconductor having an organic photoconductive film may be used as the photoelectric conversion device 101.

[0052] In addition, a pn junction photodiode using single crystal silicon for the photoelectric conversion portion, a pin type photodiode using polycrystalline silicon or microcrystalline silicon for the photoelectric conversion layer, etc. may also be used. Alternatively, a photodiode having a material capable of photoelectric conversion of light in the infrared region, such as a compound semiconductor, may also be used.

[0053] Many of the materials that can be used for the photodiode or photoconductor are also sensitive to the visible light region, so that a visible light image can also be acquired. If visible light becomes noise when acquiring an infrared light image, it is preferable to provide an infrared transmission filter (a filter that blocks visible light) between the photoelectric conversion device 101 and the subject.

[0054] The transistor 102 has a function of controlling the potential of the node FD1. The transistor 103 has a function of controlling the potential of the node FD2. The transistor 104 has a function of resetting the potentials of the nodes FD1 and FD2. The transistor 105 functions as a source follower circuit and can output the potential of the node FD2 as image data to the wiring 123. The transistor 106 has a function of selecting a pixel to which image data is output.

[0055] It is preferable that the transistors 102, 103, and 104 are transistors that use a metal oxide in a channel formation region (hereinafter, referred to as OS transistors). OS transistors have an extremely low off-state current. By using OS transistors for the transistors 102, 103, and 104, the period during which charges can be held at the nodes FD1 and FD2 can be made extremely long. Therefore, a global shutter system in which charges are accumulated simultaneously in all pixels can be applied without complicating the circuit configuration or operation method.

[0056] <Operation mode of imaging device> Fig. 4A is a schematic diagram of the operation method of the rolling shutter method, and Fig. 4B is a schematic diagram of the global shutter method. En represents the exposure (accumulation operation) of the nth column (n is a natural number), and Rn represents the readout operation of the nth column. Fig. 4A and Fig. 4B show the operation from the 1st row (Line[1]) to the Mth row (Line[M]) (M is a natural number).

[0057] The rolling shutter method is an operation method in which exposure and data readout are performed sequentially, overlapping the readout period of one row with the exposure period of another row. Since the readout operation is performed immediately after exposure, imaging can be performed even with a circuit configuration in which the data retention period is relatively short. However, since one frame of image is composed of data that is not captured simultaneously, image distortion occurs when capturing a moving object.

[0058] On the other hand, the global shutter method is a method of operation in which all pixels are exposed simultaneously, data is stored in each pixel, and the data is read out row by row, making it possible to obtain images without distortion even when capturing a moving object.

[0059] When a pixel circuit uses a transistor with a relatively high off-state current, such as a transistor that uses Si in the channel formation region (hereinafter referred to as Si transistor), the rolling shutter method is used because the data potential tends to leak out from the charge storage section. To achieve the global shutter method using Si transistors, a separate memory circuit must be installed, and more complex operations must be performed at high speed. On the other hand, when an OS transistor is used in the pixel circuit, the data potential hardly leaks out from the charge storage section, so the global shutter method can be easily achieved.

[0060] It is preferable to use OS transistors as the transistors 110, 111, 112, and 113 in the memory circuit 30. By using an OS transistor as the transistor 110, the potential of the node NW1 can be held for an extremely long time. Therefore, if the same data is to be written to the node NW1, the frequency of writing the data can be reduced.

[0061] Furthermore, by using OS transistors as the transistors 111, 112, and 113, the potential of the node NW2 can be held for an extremely long time. Since the potential of the node NW2 can be held for a long time, the potential of the node FD2 can be stabilized, and reliable data can be read from the pixel circuit 10.

[0062] Note that OS transistors may also be used for other transistors included in the pixel circuit 10. Alternatively, any combination of OS transistors and Si transistors may be used. Alternatively, all the transistors may be OS transistors. Alternatively, all the transistors may be Si transistors. Examples of Si transistors include transistors having amorphous silicon and transistors having crystalline silicon (typically, low-temperature polysilicon, single crystal silicon, etc.).

[0063] An EL element can be used for the light-emitting device 11. An element that emits infrared light can be used as the EL element. In particular, an EL element that emits near-infrared light having a peak wavelength between 700 nm and 2500 nm is preferable. For example, light with a wavelength of 760 nm or thereabouts is easily absorbed by reduced hemoglobin in veins, so the position of veins can be detected by receiving reflected light from the palm or fingers and imaging it. This effect can be used for biometric authentication.

[0064] Moreover, by comparing the amount of light received at a wavelength that is highly absorbed by reduced hemoglobin and at a wavelength that is highly absorbed by oxygenated hemoglobin (for example, 940 nm), it is possible to detect areas of a living body where neural activity is active. This function can be used for analyzing brain function, etc. Similarly, by comparing the amount of light received at a wavelength that is highly absorbed by reduced hemoglobin and at a wavelength that is highly absorbed by oxygenated hemoglobin, it is also possible to measure blood oxygen concentration. If the target of infrared light absorption is glucose in the blood, it is also possible to measure blood sugar levels.

[0065] In addition, near-infrared light of an appropriate wavelength can be used for non-destructive testing such as inspecting food for foreign objects and analyzing defects in industrial products. In addition, by combining it with the global shutter method, highly accurate sensing is possible even if the subject is moving.

[0066] In the analysis of brain function, it is necessary to attach a relatively large-area imaging device (sensor) to the head, so it is preferable that the imaging device is flexible or that the flexible imaging device is formed on a curved surface that matches the shape of the head. In order to give flexibility to the imaging device, a method is used in which the imaging device is first completed on a hard substrate and then transposed onto a soft substrate.

[0067] In this case, since an organic resin such as polyimide is used for the buffer layer for peeling off the imaging device from the hard substrate, the process temperature of the transistors may be limited. This may result in a decrease in the electrical characteristics and reliability of the transistors. In addition, laser irradiation is required to form a transistor using polycrystalline silicon, and laser damage to the buffer layer and surrounding materials may cause peeling failure.

[0068] Therefore, when forming a flexible imaging device, it is preferable to use an OS transistor. Since an OS transistor can be formed at a relatively low temperature and does not require a laser irradiation process, it is free from the above problems and is suitable for a flexible imaging device.

[0069] Furthermore, by using an EL element as the light-emitting device 11, a thin imaging device with a light source can be realized, which makes it easy to mount the imaging device on various devices and improves portability.

[0070] <Readout circuit> 5 is a diagram illustrating a circuit 23 connected to a specific column of the pixel array 21. A current source circuit 29 is electrically connected to a wiring 123 to which data is output from the pixel circuit 10. In addition, a circuit 24 (first CDS circuit), a circuit 25 (second CDS circuit), a circuit 26 (A / D conversion circuit), and a circuit 27 (shift register) are connected to the wiring 123 in this order.

[0071] The circuit 24 may include a transistor 141 and a capacitor 143. The circuit 25 may include a transistor 142 and a capacitor 144.

[0072] One electrode of the capacitor 143 is electrically connected to the wiring 123. The other electrode of the capacitor 143 is electrically connected to one of the source or drain of the transistor 141. The one of the source or drain of the transistor 141 is electrically connected to one electrode of the capacitor 144. The other electrode of the capacitor 144 is electrically connected to one of the source or drain of the transistor 142. The one of the source or drain of the transistor 142 is electrically connected to the circuit 26. The circuit 26 is electrically connected to the circuit 27. The circuit 26 can have, for example, a comparator, a counter, an output section (OUT), and the like.

[0073] Here, a wiring that connects the other electrode of the capacitor 143, one of the source or drain of the transistor 141, and one electrode of the capacitor 144 is referred to as a node NC1. A wiring that connects the other electrode of the capacitor 144, one of the source or drain of the transistor 142, and the circuit 26 is referred to as a node NC2.

[0074] The other of the source or drain of the transistor 141 and the other of the source or drain of the transistor 142 are connected to a reference potential (V CDS ) can be electrically connected to a wiring capable of supplying the

[0075] <Image capture device output data> In the imaging device according to one embodiment of the present invention, the third data obtained by multiplying the first data acquired by the pixel by the second data (weight) can be output. The third data can be generated using the pixel circuit 10, the circuit 24, and the circuit 25, and unnecessary components are removed. This will be described below.

[0076] The third data is the no-exposure data (D r ), weighted data for no exposure (D r+w ), data with exposure (D r+x ), and weighted data with exposure (D r+x+w) to generate it.

[0077] The pixel circuit 10 is D r When the output is made, a current proportional to the function of formula (1) flows through the wiring 123. Here, r is the reset potential, V th is the threshold voltage of the transistor 105, and r corresponds to the potential of the node FD2 during reading.

[0078] (rV th ) 2 (1)

[0079] The pixel circuit 10 is D r+w When the signal is output, a current proportional to the function of formula (2) flows through the wiring 123. Here, w is a weight, and r+w corresponds to the potential of the node FD2 during reading.

[0080] (r+wV th ) 2 (2)

[0081] The pixel circuit 10 is D r+x When outputting, a current proportional to the function of formula (3) flows through the wiring 123. Here, x is the amount of change in potential due to exposure, and r+x corresponds to the potential of the node FD2 during readout.

[0082] (r+xV th ) 2 (3)

[0083] The pixel circuit 10 is D r+x+w When outputting, a current proportional to the function of formula (4) flows through the wiring 123. r+x+w corresponds to the potential of the node FD2 during reading.

[0084] (r+x+wV th ) 2 (4)

[0085] Here, the amount of change (difference) in the presence or absence of weighting is calculated for the cases without exposure and with exposure. Specifically, equation (2)-equation (1) and equation (4)-equation (3) are calculated.

[0086] (r+wV th ) 2 -(rV th ) 2 =w(2r+w-2V th ) (5)

[0087] (r+x+wV th ) 2 -(r+xV th ) 2 =w(2r+2x+w-2V th ) (6)

[0088] Furthermore, when calculating equation (6)-equation (5), the solution becomes 2wx, as shown in equation (7).

[0089] w(2r+2x+w-2V th )-w(2r+w-2V th )=2wx (7)

[0090] That is, information regarding the product of the exposure data (x) and the weight (w) can be extracted. The operation of outputting data corresponding to the above formulas (1) to (4) can be performed by pixel circuit 10. The operation of calculating data corresponding to formulas (5) and (6) can be performed mainly by circuit 24. The operation of calculating data corresponding to formula (7) can be performed mainly by circuit 25.

[0091] <Operation of the imaging device> Next, a specific example of the operation of the pixel circuit 10, the circuit 24, and the circuit 25 will be described with reference to the timing chart of Fig. 6. In the description of the timing chart in this specification, a high potential is represented by "H" and a low potential is represented by "L." It is assumed that "L" is constantly supplied to the wirings 121, 123, and 135, and "H" is constantly supplied to the wirings 122 and 134.

[0092] Although the operation of light emitting device 11 will not be described here, it is assumed that a power supply potential is supplied to light emitting device 11 so as to appropriately emit light at least during the accumulation operation period.

[0093] In period T1, when the potential of wiring 124 is set to "H", the potential of wiring 125 is set to "H", the potential of wiring 126 is set to "H", the potential of wiring 127 is set to "L", the potential of wiring 136 is set to "H", the potential of wiring 137 is set to "L", the potential of wiring 138 is set to "H", the potential of wiring 151 is set to "L", and the potential of wiring 152 is set to "L", transistors 102, 103, and 104 are turned on, and the potential of wiring 122 "H" (r: reset potential) is supplied to nodes FD1 and FD2 (reset operation).

[0094] In the memory circuit 30, the transistor 113 is turned on, and the potential "L" of the wiring 135 is written to the node NW2. At this time, "rL" is held in the capacitor 108. Furthermore, the transistor 110 is turned on, and the potential "w" supplied from the wiring 133 is written to the node NW1. Note that the writing of the weight to the node NW1 is not limited to the period T1, and may be performed before the weight is read out to the node NW2.

[0095] In period T2, when the potential of the wiring 124 is "H", the potential of the wiring 125 is "L", the potential of the wiring 126 is "L", the potential of the wiring 127 is "L", the potential of the wiring 136 is "L", the potential of the wiring 137 is "L", the potential of the wiring 138 is "H", the potential of the wiring 151 is "L", and the potential of the wiring 152 is "L", the transistors 103 and 104 become non-conductive and a reset potential "r" is held at the node FD2. In addition, the potential of the node FD1 changes by the potential "x" of the exposure amount in accordance with the operation of the photoelectric conversion device 101, and becomes "r+x" (accumulation operation).

[0096] In a period T3, when the potential of the wiring 124 is set to "L", the potential of the wiring 125 is set to "L", the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", the potential of the wiring 136 is set to "L", the potential of the wiring 137 is set to "L", the potential of the wiring 138 is set to "H", the potential of the wiring 151 is set to "L", and the potential of the wiring 152 is set to "L", the transistor 102 is turned off, and the potential of the node FD1 is determined and held. Also, the transistor 110 is turned off, and the potential of the node NW1 is held.

[0097] In this case, by using OS transistors with low off-state current as the transistors 102, 103, 104, and 110, unnecessary outflow of charge from the nodes FD1, FD2, and NW1 can be suppressed, and the retention time of each data can be extended.

[0098] In a period T4, when the potential of the wiring 124 is set to “L”, the potential of the wiring 125 is set to “L”, the potential of the wiring 126 is set to “L”, the potential of the wiring 127 is set to “H”, the potential of the wiring 136 is set to “L”, the potential of the wiring 137 is set to “L”, the potential of the wiring 138 is set to “H”, the potential of the wiring 151 is set to “H”, and the potential of the wiring 152 is set to “H”, the transistor 106 is turned on, and the source follower operation of the transistor 105 causes a function (rV th ) 2 A current proportional to the voltage Vcc flows through the wiring 123 (read operation 1). This operation corresponds to the above-mentioned formula (1).

[0099] Furthermore, the transistor 141 of the circuit 24 and the transistor 142 of the circuit 25 are turned on, and the reference potential “V CDS " is written.

[0100] In the period T5, when the potential of wiring 124 is set to "L", the potential of wiring 125 is set to "L", the potential of wiring 126 is set to "L", the potential of wiring 127 is set to "H", the potential of wiring 136 is set to "L", the potential of wiring 137 is set to "H", the potential of wiring 138 is set to "L", the potential of wiring 151 is set to "L", and the potential of wiring 152 is set to "H", in the memory circuit 30, the transistor 111 is turned on and the transistor 113 is turned off, and the potential "w" of the node NW1 is read out to the node NW2 due to the source follower operation of the transistor 112.

[0101] At this time, the potential of the node FD2 becomes "r-L+w" due to the capacitive coupling of the capacitor 108. Here, if "L"=0V, the potential of the node FD2 becomes "r+w". Therefore, due to the source follower operation of the transistor 105, a function including "r+w" (r+wV th )2 A current proportional to flows through the wiring 123. This operation corresponds to the above-mentioned formula (2).

[0102] In addition, in the circuit 24, the transistor 141 is turned off. At this time, the potential of the node NC1 is “V CDS When "=0V, the capacitive coupling of the capacitor 143 causes (r+wV th ) 2 -(rV th ) 2 =w(2r+w-2V th ) This operation corresponds to the above-mentioned formula (5).

[0103] In a period T6, when the potential of the wiring 124 is set to "L", the potential of the wiring 125 is set to "H", the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "H", the potential of the wiring 136 is set to "L", the potential of the wiring 137 is set to "L", the potential of the wiring 138 is set to "H", the potential of the wiring 151 is set to "H", and the potential of the wiring 152 is set to "L", the transistor 103 is turned on, and the potential of the node FD1, "r+x", is read out to the node FD2. Therefore, the source follower operation of the transistor 105 is performed as a function including "r+x" (r+xV th ) 2 A current proportional to flows through the wiring 123. This operation corresponds to the above-mentioned formula (3).

[0104] In the memory circuit 30, the transistor 111 is turned off and the transistor 113 is turned on, so that the potential "L" of the wiring 135 is written to the node NW2. At this time, the capacitor 108 holds "r+xL".

[0105] Also, the transistor 141 of the circuit 24 is turned on, and the node NC1 is supplied with the reference potential “V CDS " is written. Also, the transistor 142 of the circuit 25 becomes non-conductive. Therefore, the potential of the node NC2 becomes "V CDS -w(2r+w-2V th )” In other words, “V CDS If “=0V, the potential of node NC2 is “-w(2r+w-2V th)".

[0106] In the period T7, when the potential of wiring 124 is set to "L", the potential of wiring 125 is set to "H", the potential of wiring 126 is set to "L", the potential of wiring 127 is set to "H", the potential of wiring 136 is set to "L", the potential of wiring 137 is set to "H", the potential of wiring 138 is set to "L", the potential of wiring 151 is set to "L", and the potential of wiring 152 is set to "L", in the memory circuit 30, the transistor 111 is turned on and the transistor 113 is turned off, and the potential "w" of the node NW1 is read out to the node NW2 due to the source follower operation of the transistor 112.

[0107] At this time, the potential of the node FD2 becomes "r+x-L+w" due to the capacitive coupling of the capacitor 108. Here, if "L"=0V, the potential of the node FD2 becomes "r+x+w". Therefore, due to the source follower operation of the transistor 105, a function including "r+x+w" (r+x+wV th ) 2 A current proportional to flows through the wiring 123. This operation corresponds to the above-mentioned formula (4).

[0108] In addition, in the circuit 24, the transistor 141 is turned off. At this time, the potential of the node NC1 is “V CDS When "=0V, the capacitance coupling of the capacitor 143 causes (r+x+wV th ) 2 -(r+xV th ) 2 =w(2r+2x+w-2V th ) This operation corresponds to the above-mentioned formula (6).

[0109] In addition, the transistor 142 of the circuit 25 is turned off. At this time, the potential of the node NC2 is “V CDS When “=0V, the capacitive coupling of the capacitor 144 causes w(2r+2x+w-2V th )-w(2r+w-2V th )=2wx. This operation corresponds to the above-mentioned equation (7). Therefore, information regarding the product of the exposure data (x) and the weight (w) can be extracted from the circuit 25.

[0110] The above is an example of the specific operations of the pixel circuit 10, the circuit 24, and the circuit 25.

[0111] <Modifications of the Imaging Device> An imaging device according to one embodiment of the present invention may have a configuration shown in the block diagram in Fig. 7. The imaging device shown in Fig. 7 differs from the imaging device in Fig. 1 in that a readout gate line (wiring 128) and an output line (wiring 123) are shared by a plurality of pixel circuits 10. Note that Fig. 7 shows an example in which wiring such as an output line is shared by four pixels, but the number is not limited as long as it is two or more and the total number of pixels can be equally divided.

[0112] This configuration makes it possible to read out the information of the product of exposure data (x) and weight (w) obtained from multiple pixels all at once. In other words, it is possible to perform a product-sum operation using multiple pixels. Each of the multiple pixels can output data multiplied by an arbitrary weight. Therefore, by multiplying some of the multiple pixels by a weight with an inverted sign, it is possible to obtain the difference with other pixels without extracting the data externally.

[0113] This imaging device can also be operated according to the timing chart and explanation thereof shown in Fig. 6. The derived function is shown below. Note that when the number of pixels to be read out collectively is four, n is an integer from 1 to 4.

[0114] The current read out to the wiring 123 at time T4 is Σ n (rV th ) 2 is proportional to.

[0115] The current read out to the wiring 123 at time T5 is Σ n (r+w n -V th ) 2 is proportional to.

[0116] The current read out to the wiring 123 at time T6 is Σ n (r+x n -V th )2 is proportional to.

[0117] The current read out to the wiring 123 at time T7 is Σ n (r+x n +w n -V th ) 2 is proportional to.

[0118] Then, at the end of time T7, circuit 25 outputs Σ n (x n +w n ) can be obtained.

[0119] <Light emitting devices and imaging devices> Next, a combination of a light-emitting device and a photoelectric conversion device that each pixel can have will be described. Figures 8A to 8C are diagrams for explaining a first pixel 160, a second pixel 170, and an object 180. The first pixel 160 and the second pixel 170 can be applied to pixels in the pixel array 21. When one pixel is considered as a square, the size of one side is 1 mm or less, preferably 100 μm or less.

[0120] 8A shows a configuration in which a first pixel 160 has a photoelectric conversion device 101a, a second pixel 170 has a photoelectric conversion device 101b, and both pixels have light-emitting devices 11a. A portion of the light emitted from the light-emitting device 11a is absorbed by an object 180, and the light reflected by the object 180 is received by each pixel. The arrows in the figure indicate part of the path of the light.

[0121] When the central wavelengths to be imaged are wavelength A and wavelength B (wavelength A<wavelength B), the light-emitting device 11a can be an EL element that emits light with a broad wavelength distribution including wavelength A and wavelength B. Here, the absorption edge wavelength of the photoelectric conversion device 101a can be shorter than wavelength B, and the absorption edge wavelength of the photoelectric conversion device 101b can be longer than wavelength B.

[0122] The photoelectric conversion device 101a may be a photodiode using a semiconductor material having an absorption edge wavelength near wavelength A for the photoelectric conversion layer. The photoelectric conversion device 101b may be a photodiode using a semiconductor material having an absorption edge wavelength near wavelength B for the photoelectric conversion layer.

[0123] Alternatively, the photoelectric conversion layers of both the photoelectric conversion devices 101a and 101b may be formed of a semiconductor material having sensitivity to a wavelength range including wavelengths A and B. In this case, an optical filter that transmits wavelength A and its vicinity may be provided on the photoelectric conversion device 101a, and an optical filter that transmits wavelength B and its vicinity may be provided on the photoelectric conversion device 101b.

[0124] With such a combination, the first pixel 160 can obtain information on light near wavelength A and wavelengths shorter than that. Also, the second pixel 170 can obtain information on light near wavelength B and wavelengths shorter than that. In other words, by taking the difference between the information obtained by the second pixel 170 and the information obtained by the first pixel 160, data on wavelength B and its vicinity can be extracted.

[0125] By using the imaging device shown in Figure 1, it is possible to output weighted data of image data acquired by each pixel. Therefore, by taking that data externally and calculating the difference, it is possible to obtain only information on wavelength B and its vicinity.

[0126] Furthermore, by using the imaging device shown in FIG. 7, it is possible to obtain only information on wavelength B and its vicinity by adding appropriate weights to the pixels used in the difference calculation and reading them out collectively.

[0127] Although the above is an example in which light of two wavelengths is used, light of more wavelengths may be used.

[0128] 8B shows a configuration in which a first pixel 160 has a photoelectric conversion device 101a and a light-emitting device 11b, and a second pixel 170 has a photoelectric conversion device 101b and a light-emitting device 11b. An EL element that emits light having a peak at wavelength A can be used for the light-emitting device 11b. An EL element that emits light having a peak at wavelength B can be used for the light-emitting device 11c.

[0129] 8B, since the wavelength distribution of the light source is not broad, information on light having a peak at wavelength A can be directly obtained by the photoelectric conversion device 101a. Also, information on light having a peak at wavelength B can be directly obtained by the photoelectric conversion device 101b.

[0130] 8C shows a configuration in which the first pixel 160 has a light-emitting device 11b, the second pixel 170 has a light-emitting device 11c, and both pixels have a photoelectric conversion device 101b. The absorption edge wavelength of the photoelectric conversion device 101b is set to be equal to or longer than wavelength B, and the first pixel 160 and the second pixel 170 are operated with a time difference (T1, T2). With this operation, at T1, information on light having a peak at wavelength B can be directly obtained by the photoelectric conversion device 101b of the pixel 170. Also, at T2, information on light having a peak at wavelength A can be directly obtained by the photoelectric conversion device 101b of the pixel 160.

[0131] In the configurations shown in FIGS. 8B and 8C, it is not always necessary to perform a difference calculation, but by performing a difference calculation, noise components of unnecessary wavelengths may be reduced.

[0132] <Modification of pixel> 9A is a circuit diagram illustrating a pixel circuit 10 and a light-emitting device 11 that can be provided in a pixel of an imaging device according to one embodiment of the present invention. The pixel circuit 10 has the same configuration as that shown in FIG.

[0133] In this pixel, since there is no electrical connection between the pixel circuit 10 and the light emitting device 11, the input potential to the light emitting device 11 and the timing of light emission can be controlled independently. One electrode of the light emitting device 11 is electrically connected to a wiring 130. The wiring 130 has a function of supplying a forward bias to the light emitting device 11 to supply a potential for causing the light emitting device 11 to emit light. The other electrode of the light emitting device 11 is electrically connected to a reference potential line, such as a GND wiring.

[0134] 9B shows a configuration in which one electrode of the light-emitting device 11 is electrically connected to the wiring 122. This configuration can be used when the reset potentials of the nodes FD1 and FD2, the power supply potential supplied to the transistor 105, and the input potential of the light-emitting device 11 can be made common.

[0135] 9C, a transistor 109 may be added to the configuration of FIG. 9B. One of the source and the drain of the transistor 109 is electrically connected to one electrode of the light-emitting device 11. The other of the source and the drain of the transistor 109 is electrically connected to a wiring 122. The gate of the transistor 109 is electrically connected to a wiring 124. With this configuration, the light-emitting period can be limited to only the period during which the transistor 102 is conductive, thereby reducing power consumption. The periods during which the transistor 102 needs to be conductive are only the reset operation period and the accumulation operation period for the node FD1, and unnecessary light emission during a read operation period, etc. can be suppressed.

[0136] 10A, when the reset potentials of the nodes FD1 and FD2 are too high with respect to the appropriate potential to be input to the light-emitting device 11, a resistive element 115 may be electrically connected between one electrode of the light-emitting device 11 and the wiring 122. The resistive element 115 acts as a current limiting resistor and can limit the current flowing through the light-emitting device 11, thereby improving the reliability of the light-emitting device 11. The resistance value of the resistive element 115 may be selected appropriately according to the electrical characteristics of the light-emitting device 11.

[0137] 10B, the transistor 109 shown in FIG. 9C may be used instead of the resistor 115. In this configuration, the gate of the transistor 109 is electrically connected to a wiring 131. Therefore, by varying the potential of the wiring 131, the illuminance and light emission timing of the light-emitting device 11 can be arbitrarily controlled, and power consumption can be reduced.

[0138] 10C , a structure may be used in which a transistor 109 is provided, the other of the source and the drain of the transistor 109 is electrically connected to a wiring 130, and the gate of the transistor 109 is electrically connected to a wiring 124. In this structure, the input potential to the light-emitting device 11 is controlled by the wiring 130, and the timing of light emission is controlled by the wiring 124.

[0139] Note that, although Figures 9A to 9C and Figures 10A to 10C show a configuration in which the cathode of the photoelectric conversion device 101 is electrically connected to the transistor 102, a configuration in which the anode of the photoelectric conversion device 101 is electrically connected to the transistor 102 may also be used, as shown in Figures 11A to 11C and Figures 12A to 12C.

[0140] 11A to 11C and 12A to 12C, one electrode of the photoelectric conversion device 101 is electrically connected to a wiring 122, and the other electrode of the photoelectric conversion device 101 is electrically connected to one of the source and drain of the transistor 102. In addition, the other of the source and drain of the transistor 104 is electrically connected to a wiring 132.

[0141] 11A to 11C and 12A to 12C, the nodes FD1 and FD2 are reset to low potential for operation, and therefore the wiring 132 is set to a low potential (a potential lower than that of the wiring 122).

[0142] For an explanation of the connection form between the light emitting device 11 and its peripheral elements shown in FIGS. 11A to 11C and FIGS. 12A to 12C, the explanations of FIGS. 9A to 9C and FIGS. 10A to 10C can be referred to.

[0143] The OS transistor included in the imaging device may have a back gate. Fig. 13A shows a structure in which the back gate is electrically connected to the front gate, which has the effect of increasing the on-state current. Fig. 13B shows a structure in which the back gate is electrically connected to a wiring that can supply a constant potential, which can control the threshold voltage of the transistor.

[0144] 13A and 13B may be combined so that each transistor can operate appropriately. A pixel circuit may include a transistor that does not have a back gate. Note that the structure in which a transistor has a back gate can be applied to all pixel circuits and peripheral circuits described in this embodiment.

[0145] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0146] (Embodiment 2) In this embodiment, a structural example of an imaging device according to one embodiment of the present invention will be described.

[0147] 14A illustrates an example of a pixel structure of an imaging device. The pixel may have a laminated structure including a layer 510 having a light-emitting device 11 and a photoelectric conversion device 101, and a layer 520 having transistors and the like that constitute a pixel circuit 10. Each layer has a supporting substrate.

[0148] A light-emitting device (EL element) that utilizes electroluminescence can be applied as the light-emitting device 11 of the layer 510. The EL element has a layer (EL layer) containing a light-emitting compound between a pair of electrodes. When a potential difference larger than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side, and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the light-emitting material contained in the EL layer emits light.

[0149] Furthermore, EL elements are classified according to whether the light-emitting material is an organic compound or an inorganic compound. In general, the former are called organic EL elements and the latter are called inorganic EL elements.

[0150] When a voltage is applied to an organic EL element, electrons are injected from one electrode and holes are injected from the other electrode into the EL layer. When these carriers (electrons and holes) recombine, the light-emitting organic compound is excited, and light is emitted when the excited state returns to the ground state. Due to this mechanism, this type of light-emitting device is called a current-excited light-emitting device.

[0151] The EL layer can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0152] Inorganic EL elements are classified into dispersion-type inorganic EL elements and thin-film inorganic EL elements based on their device structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination light emission that utilizes donor and acceptor levels. Thin-film inorganic EL elements have a structure in which a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes the inner-shell electron transition of metal ions.

[0153] FIG. 14B shows the configuration of the light-emitting device 11 (EL element). The EL layer 300 can be composed of multiple layers, such as a layer 330, a light-emitting layer 320, and a layer 340. The layer 330 can have, for example, a layer containing a substance with high electron injection properties (electron injection layer) and a layer containing a substance with high electron transport properties (electron transport layer). The light-emitting layer 320 has, for example, a light-emitting compound. The layer 340 can have, for example, a layer containing a substance with high hole injection properties (hole injection layer) and a layer containing a substance with high hole transport properties (hole transport layer).

[0154] The EL layer 300 provided between the electrode 311 and the electrode 312 can function as a single light-emitting unit. Note that a plurality of light-emitting layers may be provided between the layer 330 and the layer 340. Note that the use of a light-transmitting conductive film for either the electrode 311 or the electrode 312 determines the light emission direction.

[0155] The light-emitting device 11 can emit light of various wavelengths depending on the material constituting the EL layer 300. In one embodiment of the present invention, a material that emits light having a peak in the near-infrared light (wavelength 720 to 2500 nm) is used as the material constituting the EL layer 300. For example, a material that emits light of 720 nm, 760 nm, 850 nm, 900 nm, 940 nm, or wavelengths close to these may be used depending on the application.

[0156] In one embodiment of the present invention, the light-emitting material (also referred to as a guest material or a dopant material) of the EL layer 300 preferably includes an organometallic iridium complex that emits near-infrared light. The organometallic iridium complex preferably has a dimethylphenyl skeleton and a quinoxaline skeleton. A representative example of the organometallic iridium complex is bis{4,6-dimethyl-2-[3-(3,5-dimethylphenyl)-2-quinoxalinyl-κN]phenyl-κC}(2,2',6,6'-tetramethyl-3,5-heptanedionato-κN)phenyl-κC. 2In one embodiment, the organometallic iridium complex can be an organometallic iridium complex, and the like. By using the organometallic iridium complex, an imaging element having high quantum efficiency or luminous efficiency can be provided.

[0157] In addition, as a substance (i.e., a host material) used to disperse the above-mentioned organometallic iridium complex, for example, in addition to compounds having an arylamine skeleton such as 2,3-bis(4-diphenylaminophenyl)quinoxaline (abbreviation: TPAQn) and NPB, carbazole derivatives such as CBP and 4,4',4''-tris(carbazol-9-yl)triphenylamine (abbreviation: TCTA), and metal complexes such as bis[2-(2'-hydroxyphenyl)pyridinato]zinc (abbreviation: Znpp2), bis[2-(2-hydroxyphenyl)benzoxazolato]zinc (abbreviation: Zn(BOX)2), bis(2-methyl-8-quinolinolato)(4-phenylphenolato)aluminum(III) (abbreviation: BAlq), and tris(8-quinolinolato)aluminum(III) (abbreviation: Alq3) are preferable. In addition, a polymer compound such as PVK can also be used.

[0158] As a material (host material) used to disperse the above-mentioned organometallic iridium complex, it is preferable to use N-(1,1'-biphenyl-4-yl)-N-[4-(9-phenyl-9H-carbazol-3-yl)phenyl]-9,9-dimethyl-9H-fluoren-2-amine (abbreviation: PCBBiF).

[0159] In addition, by forming the light-emitting layer 320 so as to contain the above-mentioned organometallic iridium complex (guest material) and the above-mentioned host material, the EL layer 300 can emit near-infrared phosphorescence with high luminous efficiency.

[0160] The photoelectric conversion device 101 included in the layer 510 may be a photodiode, a photoconductor, or the like. For example, the photoelectric conversion device 101 may be a stack of a layer 531, a layer 540, and a layer 532, as shown in FIG. 14C.

[0161] 14C is an example of an organic photoconductive film, in which layers 531 and 532 correspond to electrodes, one of which is transparent so that light can be introduced into the photoelectric conversion section. Layer 540 corresponds to the photoelectric conversion section, and has layers 541, 542, and 542.

[0162] One of the layers 541 and 543 in the photoelectric conversion portion can be a hole transport layer, and the other can be an electron transport layer. The layer 542 can be a photoelectric conversion layer.

[0163] For example, molybdenum oxide can be used as the hole transport layer, and for example, fullerenes such as C60 and C70, or derivatives thereof can be used as the electron transport layer.

[0164] The photoelectric conversion layer can be a mixed layer (bulk heterojunction structure) of n-type organic semiconductor and p-type organic semiconductor. Examples of materials for the photoelectric conversion layer include organic semiconductor materials such as copper (II) phthalocyanine (CuPc) and tetraphenyldibenzoperiflanthene (DBP).

[0165] Alternatively, a pn junction type photodiode formed using single crystal silicon, or a pin junction type photodiode formed using a thin film of single crystal silicon, microcrystalline silicon, polycrystalline silicon, or the like may be used as the photoelectric conversion device 101. Single crystal silicon, microcrystalline silicon, and polycrystalline silicon are sensitive to infrared light and are suitable for detecting infrared light.

[0166] The layer 520 is provided with elements such as transistors included in the pixel circuit 10. The layer 520 may also include some or all of the transistors included in the peripheral circuits described in Embodiment 1. The transistors are preferably OS transistors.

[0167] As a semiconductor material used for an OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium, for example, CAAC-OS or CAC-OS described later can be used. CAAC-OS has stable atoms constituting the crystal, and is suitable for transistors that emphasize reliability. In addition, CAC-OS has high mobility characteristics, and is suitable for transistors that operate at high speed.

[0168] OS transistors have a large energy gap in the semiconductor layer, and therefore exhibit extremely low off-current characteristics of a few yA / μm (current value per 1 μm of channel width). OS transistors also have characteristics different from Si transistors, such as the absence of impact ionization, avalanche breakdown, and short channel effects, and can form highly reliable circuits with high voltage resistance. OS transistors are also less susceptible to variations in electrical characteristics caused by non-uniformity in crystallinity, which is a problem with Si transistors.

[0169] The semiconductor layer of the OS transistor can be, for example, a film expressed as an In-M-Zn-based oxide containing indium, zinc, and M (one or more of metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, and hafnium). The In-M-Zn-based oxide can be typically formed by a sputtering method. Alternatively, it may be formed by an ALD (atomic layer deposition) method.

[0170] The atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide by the sputtering method preferably satisfies In≧M and Zn≧M. The atomic ratio of the metal elements of such a sputtering target is preferably In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. The atomic ratio of the semiconductor layer to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0171] The semiconductor layer is made of an oxide semiconductor with a low carrier density. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 Less than or equal to 1×10 15 / cm 3 Less than 1×10, more preferably 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Less than 1×10, more preferably 10 / cm 3 Less than 1 x 10 -9 / cm 3 The above oxide semiconductors can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and has stable characteristics.

[0172] Note that the composition is not limited to these, and may be appropriate depending on the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In order to obtain the required semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer.

[0173] When silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen vacancies increase and the semiconductor layer becomes n-type. For this reason, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry (SIMS)) is set to 2×10 18 atoms / cm 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0174] In addition, when an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, carriers may be generated, which may increase the off-state current of a transistor. For this reason, the concentration of an alkali metal or an alkaline earth metal in a semiconductor layer (concentration obtained by SIMS) is set to 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0175] In addition, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons that act as carriers are generated, and the carrier density increases, making the semiconductor layer more likely to be n-type. As a result, a transistor using an oxide semiconductor that contains nitrogen is likely to have normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer (concentration obtained by SIMS) is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0176] Furthermore, when hydrogen is contained in an oxide semiconductor constituting a semiconductor layer, it reacts with oxygen bonded to a metal atom to form water, which may form oxygen vacancies in the oxide semiconductor. When oxygen vacancies are present in a channel formation region in an oxide semiconductor, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies may function as donors and generate electrons that serve as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor that contains a large amount of hydrogen is likely to have normally-on characteristics.

[0177] A defect in which hydrogen has entered an oxygen vacancy can function as a donor for an oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Thus, an oxide semiconductor may be evaluated by its carrier concentration instead of its donor concentration. Thus, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor instead of the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration".

[0178] It is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0179] The semiconductor layer may have a non-single crystal structure. The non-single crystal structure includes, for example, a C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0180] An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and does not include a crystalline component, or an oxide film having an amorphous structure has, for example, a completely amorphous structure and does not include a crystalline portion.

[0181] The semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a single layer structure or a multilayer structure including two or more of the above-mentioned regions.

[0182] The following describes the structure of a cloud-aligned composite (CAC)-OS, which is one type of non-single crystal semiconductor layer.

[0183] CAC-OS is, for example, a material in which elements constituting an oxide semiconductor are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or thereabouts. Note that, hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or thereabouts, is also referred to as a mosaic or patch shape.

[0184] The oxide semiconductor preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0185] For example, the CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS may be specifically referred to as CAC-IGZO) is an indium oxide (hereinafter, InO X1 (X1 is a real number greater than 0).) or indium zinc oxide (hereinafter, In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (GaO X3 (X3 is a real number greater than 0). ) or gallium zinc oxide (Ga X4 Zinc Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into a mosaic shape, and the mosaic shape of InO X1 , or In X2 Zinc Y2 O Z2 However, the structure is such that the particles are uniformly distributed in the film (hereinafter, also referred to as a cloud-like structure).

[0186] In other words, CAC-OS is X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the first region is said to have a higher In concentration than the second region.

[0187] IGZO is a common name and may refer to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number).

[0188] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure, where multiple IGZO nanocrystals have a c-axis orientation and are connected without being oriented in the ab plane.

[0189] On the other hand, CAC-OS is a material composition of oxide semiconductor. CAC-OS is a material composition containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly distributed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0190] Note that the CAC-OS does not include a laminated structure of two or more films with different compositions, such as a two-layer structure consisting of a film mainly containing In and a film mainly containing Ga.

[0191] In addition, GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 In some cases, it may be difficult to observe a clear boundary between the region in which the main component is the

[0192] In addition, when one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. are contained instead of gallium, the CAC-OS has a configuration in which some regions observed to be in the form of nanoparticles mainly composed of the metal element and some regions observed to be in the form of nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0193] CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as a deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the more preferable it is, for example, 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0194] CAC-OS has the characteristic that no clear peaks are observed when it is measured using the θ / 2θ scan by the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. In other words, the X-ray diffraction measurement shows that there is no orientation in the ab plane direction or the c axis direction in the measurement area.

[0195] In addition, in the electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also called nano-beam electron beam) with a probe diameter of 1 nm, a ring-shaped region of high brightness (ring region) and multiple bright spots are observed in the ring region. Therefore, the electron beam diffraction pattern shows that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar direction and cross-sectional direction.

[0196] For example, in the case of CAC-OS of In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) revealed that GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 It can be seen that the region in which the main component is the crystalline silicon is unevenly distributed and mixed.

[0197] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, and has different properties from IGZO compounds. X3 The main components are In X2 Zinc Y2 O Z2 , or InO X1 The structure is such that the regions containing each element as the main component are separated from each other in a mosaic pattern.

[0198] Here, In X2 Zinc Y2 O Z2 , or InO X1 The area where GaO is the main component X3 This region has a higher electrical conductivity than the region where In is the main component. X2 Zinc Y2 O Z2 , or InO X1 When carriers flow through the region where In is the main component, the conductivity of the oxide semiconductor is expressed. X2 Zinc Y2 O Z2 , or InO X1 When the region mainly composed of is distributed in a cloud shape in the oxide semiconductor, high field-effect mobility (μ) can be achieved.

[0199] On the other hand, GaO X3 The region where the main components are In X2 Zinc Y2 O Z2 , or InOX1 This region has higher insulating properties than the region where GaO is the main component. X3 When a region containing these as main components is distributed in an oxide semiconductor, leakage current can be suppressed and favorable switching operation can be achieved.

[0200] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by X2 Zinc Y2 O Z2 , or InO X1 The conductivity caused by the MOSFET and the MOSFET's resistance to the MOSFET's resistance work in a complementary manner, resulting in a high on-state current (I on ), and high field-effect mobility (μ).

[0201] In addition, semiconductor elements using CAC-OS have high reliability, making CAC-OS suitable as a constituent material for various semiconductor devices.

[0202] It is preferable to use a flexible substrate for the supporting substrate of the layer 510 and the layer 520. When the supporting substrate has flexibility, a flexible imaging device can be configured. For example, it becomes easy to attach the imaging device to a part of a living body by closely contacting it.

[0203] Examples of materials that can be used for the flexible support substrate include polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, and cellulose nanofiber.

[0204] The supporting substrate of the layer 520 may be a semiconductor substrate such as a silicon wafer, a glass substrate, a ceramic substrate, or a metal substrate having an insulating surface. It is preferable to process these substrates thin enough to have flexibility. Depending on the application, a supporting substrate that does not have flexibility may be used.

[0205] For the support substrate of the layer 510, a substrate that is transparent to light of the wavelength to be used can be selected from the above materials.

[0206] When a semiconductor substrate such as a silicon wafer is used for the support substrate of the layer 520, a circuit for driving the pixel circuit, a circuit for reading out an image signal, an image processing circuit, and the like can be provided on the semiconductor substrate. Specifically, some or all of the transistors included in the circuits (pixel circuit 10, circuits 22, 23, 28, and the like) described in embodiment 1 can be provided on the support substrate. With this configuration, the elements constituting the pixel circuit and the peripheral circuits can be distributed over a plurality of layers and the elements or the elements and the peripheral circuits can be provided overlapping with each other, thereby reducing the area of ​​the imaging device.

[0207] Fig. 15 is a diagram illustrating an example of a cross section of the pixel shown in Fig. 14A. Layer 510 has the EL element shown in Fig. 14B as light-emitting device 11, and the organic photoconductive film shown in Fig. 14C as photoelectric conversion device 101. Layer 520 has OS transistors, and Fig. 15 illustrates the configuration shown in Fig. 9C as an example, with transistor 102 connected to photoelectric conversion device 101 and transistor 109 connected to light-emitting device 11.

[0208] In the light emitting device 11, the electrode 312 corresponds to the reference potential line (GND) shown in Fig. 9C. In the photoelectric conversion device 101, the layer 532 corresponds to the power supply line (wiring 121).

[0209] Fig. 16A shows details of an OS transistor. The OS transistor shown in Fig. 16A has a self-aligned structure in which an insulating layer is provided over a stack of an oxide semiconductor layer and a conductive layer, and a source electrode 205 and a drain electrode 206 are formed by providing grooves that reach the semiconductor layer.

[0210] The OS transistor can have a structure including a channel formation region, a source region 203, and a drain region 204 formed in an oxide semiconductor layer 207, as well as a gate electrode 201 and a gate insulating film 202. At least the gate insulating film 202 and the gate electrode 201 are provided in the groove. An oxide semiconductor layer 208 may be further provided in the groove.

[0211] As shown in FIG. 16B, the OS transistor may have a self-aligned structure in which a source region 203 and a drain region 204 are formed in a semiconductor layer using a gate electrode 201 as a mask.

[0212] Alternatively, as shown in FIG. 16C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 205 or the drain electrode 206 overlaps with the gate electrode 201.

[0213] Although the transistors 102 and 109 are shown to have a structure having a back gate 535, they may have a structure not having a back gate. The back gate 535 may be electrically connected to the front gate of a transistor provided opposite to the back gate, as shown in the cross-sectional view of the transistor in the channel width direction shown in Fig. 16D. Note that Fig. 16D shows the transistor in Fig. 16A as an example, but the same applies to transistors having other structures. In addition, a fixed potential different from that of the front gate may be supplied to the back gate 535.

[0214] Planarization films 551 and 552 are provided on the transistors 102 and 109. The planarization films 551 and 552 planarize uneven portions generated in the transistors and contact portions, and on the surface on which the light-emitting device 11 (electrode 311, EL layer 300, electrode 312) and the photoelectric conversion device 101 (layer 531, layer 540, layer 532) are provided.

[0215] A low-resistance conductive film such as a metal can be used for the electrode 311 and the layer 531. For example, the electrode 311 and the layer 531 can be formed using one or more of metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or alloys thereof, or metal nitrides thereof.

[0216] A light-transmitting conductive film that transmits near-infrared light can be used for the electrode 312 and the layer 532. For example, a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used for the electrode 312 and the layer 532.

[0217] In the pixel configuration shown in FIG. 15, light 601 is emitted to the outside from the light emitting device 11 included in the layer 510 , and reflected light 602 is received by the photoelectric conversion device 101 included in the layer 510 .

[0218] A protective layer 553 may be provided on the light-emitting device 11 and the photoelectric conversion device 101 to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting device 11 and the photoelectric conversion device 101. As the protective layer 553, it is preferable to use an inorganic insulating film such as silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, or DLC (Diamond Like Carbon).

[0219] It is also preferable to provide a sealing layer 570 between the protective layer 553 and the substrate 582 for sealing. In addition to an inert gas such as nitrogen or argon, the sealing layer 570 can be made of an ultraviolet curing resin or a thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), EVA (ethylene vinyl acetate), or the like. The sealing layer 570 may also contain a desiccant.

[0220] In addition, it is preferable to provide a light-shielding layer 571 between the protective layer 553 and the substrate 582 at the boundary between the light-emitting device 11 and the photoelectric conversion device 101 and in the vicinity thereof. A part of the light emitted from the light-emitting device 11 may be scattered or reflected by the sealing layer 570, the protective layer 553, the substrate 582, etc., and may be received by the photoelectric conversion device 101. By providing the light-shielding layer 571, it is possible to prevent such stray light not containing useful information from being received by the photoelectric conversion device 101. The light-shielding layer 571 is preferably formed of a metal having a high reflectance or a resin having a high absorbance for light of the wavelength to be used.

[0221] The substrates 581 and 582 are supporting substrates. When a flexible substrate is used as the substrates 581 and 582, a layer 591 is preferably provided between the substrate 581 and a region where a transistor or the like is provided. In addition, a layer 592 is preferably provided between the substrate 582 and a region where a sealing layer 570 is provided.

[0222] It is difficult to directly form structures (such as transistors) that require high formation temperatures and precise alignment on a flexible substrate, and they are generally first formed on a hard substrate and then transferred to the flexible substrate. Layers 591 and 592 are buffer layers for peeling the structures from the hard substrate, and can be made of a heat-resistant resin with a low linear expansion coefficient, such as polyimide. Note that the substrate 581 may not be provided, and the layer 591 may function as a supporting substrate. Alternatively, the substrate 582 may not be provided, and the layer 592 may function as a supporting substrate.

[0223] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0224] (Embodiment 3) In this embodiment, an example of an electronic device in which an imaging device according to one embodiment of the present invention can be used will be described.

[0225] FIG. 17A1 shows an infrared spectroscopic device for analyzing brain function. As shown in FIG. 17A2, the device is worn on the head of a human body. An imaging device 912 according to one embodiment of the present invention is flexible and can be attached to an inner curved surface of a helmet-type housing 911. Note that the imaging device 912 may be attached only to a necessary portion of the housing 911, not to the entire inner surface of the housing 911. The infrared spectroscopic device may include a data recording memory, a control LSI, a battery, and the like. Data can be retrieved and power can be supplied via an external interface 913.

[0226] In the infrared spectrometer, neural activity in the cerebral cortex can be detected by comparing (taking the difference between) the absorbance of infrared light having an absorption peak in oxyhemoglobin and the absorbance of infrared light having an absorption peak in reduced hemoglobin. Since the active part of the brain and the intensity of the activity can be known, the infrared spectrometer can be used to understand and study injuries and diseases. Since the imaging device 912 of one embodiment of the present invention has a light source and is thin, a thin and lightweight infrared spectrometer can be formed.

[0227] FIG. 17B1 shows an infrared spectrometer for analyzing brain functions that has the same basic functions as FIG. 17A1 but has a different shape and purpose. The infrared spectrometer has two imaging devices 922, a battery 923, and a wireless communication unit 924 built into a band 921. As shown in FIG. 17B2, the band 921 is attached to a part of the head by utilizing its elasticity. The band 921 is made of an elastic material such as resin or metal. Power can be supplied from the battery 923, and data can be transmitted and received via the wireless communication unit 924. The infrared spectrometer is small and lightweight, and can be used to detect activity in a specific part of the brain.

[0228] 18A shows a blood oxygen concentration meter. A finger is placed on a detection unit 932 provided in a housing 931, and an image is captured by an imaging device 934 provided directly below the detection unit 932. The image capture result is displayed on a display unit 933 provided on an upper portion of the housing 931. The blood oxygen concentration meter can calculate the oxygen concentration in blood from the difference in absorbance between oxyhemoglobin and deoxyhemoglobin for light of two different wavelengths. Since the imaging device 912 of one embodiment of the present invention has a light source and is thin, a thin and lightweight blood oxygen concentration meter can be formed.

[0229] FIG. 18B shows a food sorting device including a housing 941, an operation button 942, a display unit 943, a light-shielding hood 944, and the like. By bringing the light-shielding hood 944 provided around the light-receiving unit into close contact with a foodstuff to be inspected, such as fruit, and capturing an image, it is possible to detect foreign matter, insects, cavities, and decay inside the foodstuff. In addition, an infrared spectrum can be obtained from the difference between the multiple detected infrared lights, and it is also possible to detect the sugar content of the foodstuff. The food sorting device can sort defective products and grades, and determine the harvest time. The imaging device 945 of one embodiment of the present invention provided in the light-receiving unit does not require a light source, and therefore a thin, lightweight, and highly portable food sorting device can be formed at low cost.

[0230] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes. [Explanation of symbols]

[0231] 10: pixel circuit, 11: light emitting device, 11a: light emitting device, 11b: light emitting device, 11c: light emitting device, 21: pixel array, 22: circuit, 23: circuit, 24: circuit, 25: circuit, 26: circuit, 27: circuit, 28: circuit, 29: current source circuit, 30: memory circuit, 101: photoelectric conversion device, 101a: photoelectric conversion device, 101b: photoelectric conversion device, 102: transistor, 103: transistor, 104: transistor, 105: transistor, 106: transistor, 107: capacitor, 108: Capacitor, 109: transistor, 110: transistor, 111: transistor, 112: transistor, 113: transistor, 114: capacitor, 115: resistor, 121: wiring, 122: wiring, 123: wiring, 124: wiring, 125: wiring, 126: wiring, 127: wiring, 128: wiring, 130: wiring, 131: wiring, 132: wiring, 133: wiring, 134: wiring, 135: wiring, 136: wiring, 137: wiring, 138: wiring, 141: transistor, 142: transistor, 143: capacitor, 144: capacitor, 151: wiring, 152: wiring, 160: pixel, 170: pixel, 180: object, 201: gate electrode, 202: gate insulating film, 203: source region, 204: drain region, 205: source electrode, 206: drain electrode, 207: oxide semiconductor layer, 208: oxide semiconductor layer, 300: EL layer, 311: electrode, 312: electrode, 320: light-emitting layer, 330: layer, 340: layer, 510: layer, 520: layer, 531: layer, 532: layer, 535: back gate, 540: layer, 541: layer, 542: layer, 543 : layer, 551: planarization film, 552: planarization film, 553: protective layer, 570: sealing layer, 571: light-shielding layer, 581: substrate, 582: substrate, 591: layer, 592: layer, 601: light, 602: reflected light 911: housing, 912: imaging device, 913: external interface, 921: band, 922: imaging device, 923: battery, 924: wireless communication unit, 931: housing, 932: detection unit, 933: display unit, 934: imaging device, 941: housing, 942: operation button, 943: display unit, 944: light-shielding hood, 945: imaging device,

Claims

1. a first transistor to a ninth transistor, a photoelectric conversion device, and a first capacitor; one of a source and a drain of the first transistor is electrically connected to one electrode of the photoelectric conversion device; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the third transistor is electrically connected to a first wiring; one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to the first wiring; the other of the source and the drain of the fifth transistor is electrically connected to a second wiring; one of a source and a drain of the sixth transistor is electrically connected to a gate of the seventh transistor; the other of the source and the drain of the sixth transistor is electrically connected to a third wiring; one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor; the other of the source and the drain of the seventh transistor is electrically connected to one of the source and the drain of the ninth transistor; the other of the source and the drain of the eighth transistor is electrically connected to a fourth wiring; the other of the source and the drain of the ninth transistor is electrically connected to a fifth wiring; one electrode of the first capacitor is electrically connected to a gate of the fourth transistor; the other electrode of the first capacitor is electrically connected to the other of the source or the drain of the seventh transistor; Semiconductor device.

2. In claim 1, a second capacitor and a third capacitor; one electrode of the second capacitor is electrically connected to the other of the source or the drain of the first transistor; one electrode of the third capacitor is electrically connected to a gate of the seventh transistor; Semiconductor device.

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