Probe card PMIC and signal switch IC for efficient channel control

Abstract

We provide PMIC and signal switch IC for probe cards that support efficient channel control. [Solution] The switch IC according to the present invention includes a plurality of cores, each including a plurality of channels, a command decoder that receives and decodes an identifier (ID) and an instruction to form a control signal for controlling the plurality of cores and the plurality of channels, and a selector that provides a signal to control activity of the plurality of cores and the plurality of channels in response to the control signal output from the command decoder, and each of the plurality of channels is connected to a DUT (Device Under Test), and the instruction includes switch IC selection data, core selection data, and channel selection data in one frame, and supports an encoded instruction to hierarchically control the plurality of cores and the plurality of channels.

Description

[Technical field]

[0001] The present invention relates to a PMIC and a signal switch IC for a probe card, and more particularly to a PMIC and a signal switch IC for a probe card that efficiently supports channel control. [Background technology]

[0002] Fine patterns are formed on semiconductor wafers, which are then diced to form semiconductor dies, which are then packaged to form the final product. As semiconductor elements formed on the wafers become smaller, more dense, and more integrated, defect determination as to whether the semiconductor elements on the wafer perform their intended functions has become an important issue.

[0003] A probe card is a device that connects semiconductor chips to test equipment to test the operation of semiconductor devices formed on a wafer. The probe card has probe pins that are electrically connected to the semiconductor devices formed on the wafer, and the probe pins are electrically connected to the semiconductor devices to provide electrical signals and detect signals provided by the semiconductor devices.

[0004] Probe cards are equipped with multiple multi-channel PMICs (power management integrated circuits) and multi-channel signal switch ICs (hereinafter referred to as switch ICs) to solve the lack of measurement channels in equipment through multiplexing. During actual testing, to test a device under test (DUT), only the channel connected to the corresponding DUT is turned on or voltage is supplied, and other channels are set to be blocked, so that measurement can be performed only for the corresponding DUT. Even though more measurement channels are required per wafer as semiconductors become more miniaturized, testing costs can be reduced by developing new probe cards instead of purchasing new equipment.

[0005] To reduce test costs, multiplexing through a probe card has been applied, but the current extreme miniaturization of semiconductor processes requires very high multiplexing on the probe card, which ultimately means that a large number of switch ICs must be mounted on one probe card, and the time required to control each multiplexed channel is gradually increasing, so channel setting time is now considered to be one of the main factors that determine the throughput of semiconductor chips. Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in consideration of the above-mentioned problems in the conventional technology, and an object of the present invention is to provide a switch IC that is controlled by a signaling method that sets the state of each channel in a short time in order to obtain higher throughput. [Means for solving the problem]

[0007] In order to achieve the above object, according to one aspect of the present invention, a switch IC includes a plurality of cores, each including a plurality of channels; a command decoder that receives and decodes an identifier (ID) and an instruction to generate a control signal for controlling the plurality of cores and the plurality of channels; and a selector that provides a signal to control activity of the plurality of cores and the plurality of channels in response to the control signal output from the command decoder, each of the plurality of channels being connected to a DUT (Device Under Test), and the instruction includes switch IC selection data, OPCODE, core selection data, and channel selection data in one frame, and supports an encoded instruction to hierarchically control the plurality of cores and the plurality of channels.

[0008] In one embodiment, the switch IC is either a signal switch IC coupled to a signal processing DUT or a PMIC coupled to a power supply DUT. In one embodiment, the switch IC selection data, OPCODE, core selection data, and channel selection data are transmitted through a data bus in which multiple bits are transmitted in parallel. In one embodiment, the switch IC selection data is at least one bit of data, and the at least one bit of data of the switch IC selection data corresponds to a switch IC whose activity is controlled. In one embodiment, the core selection data is at least one bit of data, and the at least one bit of data of the core selection data corresponds to a core whose activity is to be controlled. In one embodiment, the channel selection data is at least one bit of data, the at least one bit of data of the channel selection data corresponding to a channel whose activity is controlled. In one embodiment, the channels selected by the channel selection data are equally selected for all cores selected by the core selection data, and the cores selected by the core selection data are equally selected for all switch ICs selected by the switch IC selection data. In one embodiment, the switch IC selection data, OPCODE, core selection data, and channel selection data consecutively form the one frame. Effect of the Invention

[0009] According to the present invention, the time consumed for inspecting semiconductor wafers for defects can be reduced, thereby improving semiconductor productivity.

[0010] The effects of the present invention are not limited to those mentioned above. Other effects not mentioned will be clearly understood by those skilled in the art from the following description. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing an overview of a switch IC 100 according to an embodiment of the present invention. [Diagram 2] 1 is a block diagram showing an overview of a probe card 10 including a plurality of switch ICs (100a, 100b, 100c, 100d) and a control unit 200 according to an embodiment, and automatic test equipment (ATE). [Diagram 3] 10A and 10B are diagrams for explaining an example of the operation of a plurality of switch ICs according to an embodiment. [Figure 4] FIG. 2 is a diagram showing an example of one frame of a signal to be transmitted. [Diagram 5] 4 is a timing diagram illustrating a command (CMD) output from an activation control unit 200 according to an embodiment. [Figure 6] This is a diagram showing switch ICs, cores, and channels activated by a command (CMD) with diagonal lines. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] A PMIC and a signal switch IC for a probe card supporting efficient channel control according to one embodiment of the present invention include a plurality of cores each including a plurality of channels, a command decoder for receiving and decoding an identifier (ID) and an instruction to generate a control signal for controlling the plurality of cores and the plurality of channels, and a selector for providing a signal for controlling the activity of the plurality of cores and the plurality of channels in response to the control signal output from the command decoder, each of the plurality of channels being connected to a DUT (Device Under Test), and the instruction includes switch IC selection data, OP CODE, core selection data, and channel selection data in one frame, and supports an encoded command to hierarchically control the plurality of cores and the plurality of channels.

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of the embodiments of the present invention will be described in detail with reference to the drawings.

[0014] The terms and words used in this specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings. They should be interpreted as meanings and concepts that correspond to the technical ideas of the present invention, based on the principle that the inventor can appropriately define the concepts of terms in order to best describe his / her invention. Therefore, it should be understood that the embodiments described in this specification and the configurations shown in the drawings are merely the most preferred embodiments of the present invention, and do not represent the entire technical ideas of the present invention, and therefore there may be various equivalents and modifications that can replace them at the time of filing of the present invention.

[0015] The terms used in this specification are used to describe specific embodiments and are not intended to limit the present invention. As used in this specification, the singular form "a," "an," or "the" can include the plural form unless the context clearly indicates otherwise.

[0016] The probe card 100 of the present invention will be described below with reference to the drawings. For a simple and clear description, an active high signaling scheme activated at a logic high state will be exemplified below. However, this is for illustrative purposes only, and it is of course possible to operate the probe card 100 in an active low signaling scheme activated at a logic low state, unlike the illustrated example.

[0017] 1 is a block diagram showing an overview of a switch IC 100 according to an embodiment of the present invention. Referring to FIG. 1, the switch IC 100 includes a plurality of cores (CORE0, CORE1, ..., COREk) each including a plurality of channels (CHO, CH1, ..., CHn), a command decoder 110 for receiving and decoding an identifier (ID) and a command (CMD) to generate control signals for controlling the plurality of cores (CORE0, CORE1, ..., COREk) and the plurality of channels (CHO, CH1, ..., CHn), and a selector 120 for providing signals for controlling the activity of the plurality of cores and the plurality of channels in response to the control signals output from the command decoder 110, each of the plurality of channels being connected to a DUT (Device Under Test), and a command is encoded to include switch IC selection data, core selection data, and channel selection data in one frame to hierarchically specify and control the plurality of cores and the plurality of channels.

[0018] 2 is a block diagram showing an overview of a probe card 10 and automatic test equipment (ATE) including a plurality of switch ICs (100a, 100b, 100c, 100d) and a control unit 200 according to an embodiment. Referring to FIG. 1 and FIG. 2, the probe card 10 includes a control unit 200 and a plurality of switch ICs 100 that are controlled by commands (CMD) provided from the control unit 200.

[0019] An automatic test equipment (ATE) is electrically connected to a DUT (not shown) to receive signals from the DUT and determine whether the DUT is defective based on a user's test vector. The ATE has its own signal protocol.

[0020] The ATE sends a command to the controller in the ATE's own signal protocol to test the DUT. The controller 200 receives and interprets the signal from the ATE, controls or selects a channel of the switch IC to test the corresponding DUT, and sends a signal to control the selected switch ICs (100a, 100b, 100c, 100d, ...). As an example, the controller 200 is implemented as a field programmable gate array (FPGA).

[0021] Measurement channels (not shown) of the ATE are connected to the channel inputs of the switch ICs (100a, 100b, 100c, 100d, ...) of the probe card 10, and the signals are multiplexed by the switch ICs and connected to a plurality of DUTs through a plurality of probe pins for probes. In one embodiment, the switch ICs (100a, 100b, 100c, 100d, ...) are implemented as analog multiplexers each having a unique identifier (ID). When testing a DUT, the probe card 10 tests the corresponding DUT by turning on the channel to which the DUT to be tested is connected and blocking the remaining channels.

[0022] As described above, each switch IC (100a, 100b, 100c, 100d, ...) includes multiple cores (CORE0, CORE1, ..., COREk), each of which includes multiple channels connected to the DUT, and each of the multiple cores (CORE0, CORE1, ..., COREk) includes n channels (CH0, CH1, ..., CHn).

[0023] Each switch IC is preferably k Each core contains multiple channels, preferably 2 n It contains (n ​​is a natural number) channels.

[0024] Fig. 3 is a diagram for explaining an example of the operation of a plurality of switch ICs according to an embodiment. Although the probe card 10 includes a plurality of switch ICs, for the sake of simple and clear explanation, an example will be described below in which the probe card 10 includes four switch ICs (100a, 100b, 100c, and 100d) as illustrated in Fig. 3, each switch IC 100 includes four cores (CORE0, CORE1, CORE2, and CORE3), and each core includes eight channels (CH0, CH1, ..., CH7).

[0025] However, this is merely an example for easy and concise explanation, and is not intended to limit the scope of the present invention. Therefore, each switch IC can include five or more cores or three or less cores, and each core can include nine or more channels or seven or less channels.

[0026] The operation of the switch ICs (100a, 100b, 100c, and 100d) will be described in detail below.

[0027] FIG. 4 is a diagram showing an example of one frame of a transmitted signal, and is a timing diagram showing an outline of a command (CMD) provided from the control unit 200 to each switch IC (100a, 100b, 100c, 100d).

[0028] 3 and 4, a command (CMD) provided by the control unit 200 includes an enable signal (WEN) and a plurality of data bits (DATA[0:3]). The plurality of data bits (DATA[0:3]) are transmitted through a parallel data bus. The control unit 200 also transmits a clock signal (CLK). Each of the plurality of data bits, the enable signal, and the clock signal are transmitted in parallel. In one embodiment, the control unit 200 also provides a clock signal (CLK), and the plurality of data bits (DATA[0:3]) are provided in synchronization with the clock signal (CLK) provided by the control unit 200.

[0029] The switch ICs 100a, 100b, 100c, and 100d are not activated by the enable signal WEN in a logic low state, but when the enable signal WEN is logic high, the switch ICs 100a, 100b, 100c, and 100d perform operations according to activation commands. However, this is only one embodiment, and it goes without saying that the switch ICs 100a, 100b, 100c, and 100d may be activated by the enable signal WEN in a logic low state as described above, and deactivated when the enable signal WEN is logic high.

[0030] A plurality of data bits (DATA[0:3]) includes switch IC selection data, OP CODE, core selection data, and channel selection data within one frame. In the embodiment illustrated in FIG. 3, data IC_0, IC_1, IC_2, and IC_3, which are data transmitted first through data bits [0:3], are switch IC selection data that control the activation of switch ICs (100a, 100b, 100c, and 100d), respectively.

[0031] The OP CODE transmitted next specifies the specific operation that the switch IC must perform. For example, the OP CODE specifies the operation that the switch IC must perform. The operation to be performed is specified by the user as which operation to perform among the functions supported by the switch IC, such as channel activation / deactivation, voltage supply, etc.

[0032] Next, CORE_0, CORE_1, CORE_2, and CORE_3 are core selection data that control the activation of the cores (CORE_0, CORE_1, CORE_2, and CORE_3) in the switch IC, respectively. Next, channel selection data included in each core is transmitted.

[0033] In the example shown in FIG. 4, data bit [1] (DATA[1]) includes switch IC selection data for activating the first switch IC (IC_1), core selection data for activating the first core (CORE_1) in the switch IC, channel selection data (CH_5) for activating the fifth channel, and channel selection data (CH_1) for activating the first channel within one frame.

[0034] As shown in FIG. 4, the data bits transmitted on the data bus include switch IC selection data, core selection data, and channel selection data, which are successively arranged to form one signal frame.

[0035] 5 is a timing diagram illustrating an outline of a command (CMD) output from activation control unit 200 according to an embodiment. Referring to FIGS. 1 to 3, the first bit of the command (CMD) transmitted to the data bus (DATA[0:3]) is an activation bit of a switch IC assigned to each data bit in the data bus. In the embodiment illustrated in FIG. 3, data bits DATA[0] and DATA[2] are in a logic high state, so that corresponding switch ICs 100a and 100c are activated.

[0036] Then, an OP CODE is transmitted over the data bus (DATA[0:3]). In the embodiment illustrated in Figure 5, the binary number 1001 is transmitted, which specifies the operation of activating / deactivating the channel.

[0037] Subsequently, core selection data is transmitted via the data bus (DATA[0:3]). In the embodiment illustrated in FIG 5, data bits DATA[0] and DATA[3] are in a logic high state, so that the corresponding cores CORE_0 and CORE_3 are activated.

[0038] Subsequently, channel selection data is transmitted over the data bus (DATA[0:3]). In the embodiment illustrated in FIG. 4, data bits DATA[1] and DATA[2] are in a logic high state, so that their corresponding channels CH_5 and CH_6 are activated.

[0039] FIG. 6 is a diagram showing the switch ICs, cores, and channels activated by the command (CMD) with diagonal lines, and Table 1 below is a table summarizing the switch ICs, cores, and channels activated in the embodiment of the command (CMD) illustrated in FIG. 5.

[0040] [Table 1]

[0041] 6 and Table 1, the fifth channel (CH5) and sixth channel (CH6) in the core 0 (CORE0) and core 3 (CORE) of the switch IC 100a are activated by the command (CMD) of one frame illustrated in FIG. 5, and the fifth channel (CH5) and sixth channel (CH6) in the core 0 (CORE0) and core 3 (CORE) of the switch IC 100c are activated, activating a total of eight channels. In this embodiment, the switch ICs, cores, and channels are activated hierarchically. That is, the switch ICs are activated by the switch IC selection data, and then the corresponding cores in all the switch ICs selected by the core selection data are activated, and the channels in all the cores activated by the channel selection data are activated, and are selected and activated in a hierarchical structure. This structural feature provides an advantage of operating faster than the conventional technology.

[0042] By specifying the channels to be activated in this manner, multiple target channels can be specified and activated more flexibly than in the conventional technology of specifying individual IDs, thereby reducing the number of times activation commands are sent and received, thereby reducing channel setup time and ultimately improving throughput.

[0043] In this embodiment, commands are provided in synchronization with the clock, which allows high-speed signal transmission and simplifies the decoding logic to set the state of each channel in a short time, thereby achieving high throughput in semiconductor production.

[0044] The terms and words used in the present specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings, but should be interpreted as having meanings and concepts that correspond to the technical ideas of the present invention, based on the principle that the inventor can appropriately define the concepts of terms in order to best describe his / her invention.

[0045] Therefore, it should be understood that the embodiments described in this specification and the configurations shown in the drawings are merely the most preferred embodiment of the present invention and do not represent the entire technical idea of ​​the present invention, and therefore there may be various equivalents and modifications that can replace them at the time of filing of the present invention.

[0046] The terms used in this specification are used to describe specific embodiments and are not intended to limit the present invention. As used in this specification, the singular form can include the plural form unless the context clearly indicates otherwise. [Explanation of symbols]

[0047] 10 Probe Card 100 Switch ICs 100a, 100b, 100c, 100d Switches 110 Command Decoder 120 (Core Channel) Selector 200 Control section ATE Automatic Test Equipment

Claims

1. A switch IC, A plurality of cores, each including a plurality of channels; a command decoder for receiving and decoding an identifier (ID) and a command to generate control signals for controlling the cores and the channels; a selector that provides signals that control activation of the cores and the channels in response to a control signal output from the command decoder; Each of the plurality of channels is connected to a DUT (Device Under Test), The command includes switch IC selection data, an OP CODE, core selection data, and channel selection data in one frame, and is encoded to hierarchically control the multiple cores and the multiple channels.

2. 2. The switch IC of claim 1, wherein the switch IC is either a signal switch IC connected to a signal processing DUT or a PMIC connected to a power supply DUT.

3. 2. The switch IC of claim 1, wherein the switch IC selection data, the OP CODE, the core selection data, and the channel selection data are transmitted through a data bus in which a plurality of bits are transmitted in parallel.

4. The switch IC selection data is at least one bit of data, The switch IC according to claim 1 , wherein the at least one bit of data of the switch IC selection data corresponds to a switch IC whose activity is controlled.

5. The core selection data is at least one bit of data, 5. The switch IC according to claim 4, wherein the at least one bit of the core selection data corresponds to a core whose activity is controlled.

6. the channel selection data is at least one bit of data; 6. The switch IC according to claim 5, wherein the at least one bit of data of the channel selection data corresponds to a channel whose activity is controlled.

7. the channels selected by the channel selection data are selected equally for all cores selected by the core selection data; The switch IC of claim 6, wherein the core selected by the core selection data is selected equally for all switch ICs selected by the switch IC selection data.

8. 2. The switch IC according to claim 1, wherein the switch IC selection data, the OP CODE, the core selection data, and the channel selection data are arranged in a continuous manner to form one frame.

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