Three-dimensional dynamic random access memory (DRAM) and method for forming same

Abstract

Embodiments herein relate to a three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In one embodiment, a film stack is formed on a substrate. The film stack includes a plurality of unit stacks. Each unit stack has, in order, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is recessed from the first opening to form a first lateral recess. A gate structure is formed in the first lateral recess and is disposed over a portion of the semiconductor layer. A second opening is formed through the film stack, disposed laterally from the location where the first opening was formed. A portion of the semiconductor layer is recessed from the second opening to form a second lateral recess. A capacitor is formed in the region where the second lateral recess is disposed and contacts a portion of the semiconductor layer.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments described herein relate generally to the field of semiconductor processing, and more particularly to three-dimensional (3D) dynamic random access memories (DRAMs) and methods for forming 3D DRAMs. [Background technology]

[0002]

[0002] Technological advances in semiconductor processing have resulted in integrated circuits reaching the physical limits of Moore's Law. These advances have led to new paradigms for devices and structures within integrated circuits. For example, various three-dimensional (3D) devices have been developed for integrated circuits. However, such 3D devices can bring several new challenges for processing and manufacturing. Summary of the Invention

[0003]

[0003] An embodiment of the present disclosure includes a method for semiconductor processing. A film stack is formed on a substrate. The film stack includes a plurality of unit stacks. Each unit stack has a first dielectric layer, a semiconductor layer disposed on the first dielectric layer, and a second dielectric layer disposed on the semiconductor layer. A first opening is formed through the film stack. The second dielectric layer is recessed from the first opening to form a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening is formed through the film stack. The second opening is disposed laterally from a location where the first opening is formed. The gate structure is disposed at a lateral location between the second opening and the location where the first opening is formed. A portion of the semiconductor layer is recessed from the second opening to form a second lateral recess. A capacitor is formed in the region where the second lateral recess is disposed. The capacitor contacts a portion of the semiconductor layer.

[0004]

[0004] An embodiment of the present disclosure includes a method for semiconductor processing. A film stack is formed on a substrate. The film stack includes a plurality of unit stacks. Each unit stack has a first layer and a second layer disposed on the first layer. A first opening is formed through the film stack. The first layer is recessed from the first opening to form a first lateral recess. A first conformal layer is formed in the first lateral recess. A first fill material is formed in the first lateral recess on the first conformal layer. The first conformal layer is recessed from the first opening to form a second lateral recess. A gate structure is formed in the second lateral recess and disposed above and below a semiconductor layer. The semiconductor layer is horizontally aligned with the second layer. A second opening is formed through the film stack. The second opening is disposed laterally from where the first opening was formed. A gate structure is disposed at a lateral location between the second opening and the location where the first opening was formed. The second layer is recessed from the second opening to form a third lateral recess to the semiconductor layer. A capacitor is formed in the region where the third lateral recess is located. The capacitor contacts the semiconductor layer.

[0005]

[0005] An embodiment of the present disclosure includes a method for semiconductor processing. A film stack is formed on a substrate. The film stack includes at least five layers. Each layer of the at least five layers is formed of a material selected from a group of materials including no more than three different materials. A vertically stacked symmetric DRAM pair is formed on the substrate using the film stack as a mold. Each symmetric DRAM pair of the vertically stacked symmetric DRAM pairs includes a contact, a first transistor, a second transistor, a first capacitor, and a second capacitor. The first transistor includes a first gate structure, a first source / drain region, and a second source / drain region. The first source / drain region contacts the contact. The second transistor includes a second gate structure, a third source / drain region, and a fourth source / drain region. The third source / drain region contacts the contact. The second transistor is symmetric to the first transistor about the contact. The first capacitor has a first outer plate, a first capacitor dielectric layer, and a first inner plate. The first outer plate contacts the second source / drain region. The second capacitor has a second outer plate, a second capacitor dielectric layer, and a second inner plate. The second outer plate contacts the fourth source / drain region.

[0006]

[0006] In a manner that allows the above-mentioned features of the present disclosure to be understood in detail, a more detailed description of the present disclosure briefly summarized above can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the attached drawings show only some embodiments, and therefore should not be considered as limiting the scope of the present disclosure, since the present disclosure may admit of other equally effective embodiments. [Brief description of the drawings]

[0007] FIG. 1 is a circuit schematic diagram of a dynamic random access memory (DRAM) cell according to some embodiments of the present disclosure. FIG. 2 is a perspective view of a symmetric DRAM pair according to some embodiments of the present disclosure. FIG. 3 is a perspective view of a symmetric DRAM pair according to some embodiments of the present disclosure. 4-12 are cross-sectional views of intermediate structures during a first method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 5A-5C are cross-sectional views of intermediate structures during a first method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 4 through 12 are cross-sectional views of intermediate structures during a first method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 7-12 are cross-sectional views of intermediate structures during a first method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 8A-8C are cross-sectional views of intermediate structures during a first method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 9-12 are cross-sectional views of intermediate structures during a first method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 10A-10C are cross-sectional views of intermediate structures during a first method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 11A-11C are cross-sectional views of intermediate structures during a first method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 4-12 are cross-sectional views of intermediate structures during a first method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 13-27 are cross-sectional views of intermediate structures during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 14-27 are cross-sectional views of intermediate structures during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 15-27 are cross-sectional views of intermediate structures during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 16-27 are cross-sectional views of intermediate structures during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 13 through 27 are cross-sectional views of intermediate structures during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure.

[0023] FIG. 18 is a cross-sectional view of an intermediate structure during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure.

[0023] FIG. 19 is a cross-sectional view of an intermediate structure during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure.

[0023] FIG. 13 through FIG. 27 are cross-sectional views of intermediate structures during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure.

[0023] FIG. 21 is a cross-sectional view of an intermediate structure during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure.

[0023] FIG. 13 through FIG. 27 are cross-sectional views of intermediate structures during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 13 through 27 are cross-sectional views of intermediate structures during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure.

[0023] FIG. 24 is a cross-sectional view of an intermediate structure during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure.

[0023] FIG. 25 is a cross-sectional view of an intermediate structure during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure.

[0023] FIG. 26 is a cross-sectional view of an intermediate structure during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 13 through 27 are cross-sectional views of intermediate structures during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 28 to 40 illustrate a first method for forming a 3D DRAM cell according to some embodiments of the present disclosure. 34 is a cross-sectional view of an intermediate structure during the method of FIG. 28 to 40 are diagrams illustrating a first process for forming a 3D DRAM cell according to some embodiments of the present disclosure. 3 4 is a cross-sectional view of an intermediate structure during the method of FIG. 28 to 40 are diagrams illustrating a first process for forming a 3D DRAM cell according to some embodiments of the present disclosure. 3 4 is a cross-sectional view of an intermediate structure during the method of FIG. 28 to 40 are diagrams illustrating a first process for forming a 3D DRAM cell according to some embodiments of the present disclosure. 3 4 is a cross-sectional view of an intermediate structure during the method of FIG. 28 to 40 are diagrams illustrating a first process for forming a 3D DRAM cell according to some embodiments of the present disclosure. 3 4 is a cross-sectional view of an intermediate structure during the method of FIG. 28 to 40 are diagrams illustrating a first process for forming a 3D DRAM cell according to some embodiments of the present disclosure. 3 4 is a cross-sectional view of an intermediate structure during the method of FIG. 28 to 40 are diagrams illustrating a first process for forming a 3D DRAM cell according to some embodiments of the present disclosure. 3 4 is a cross-sectional view of an intermediate structure during the method of FIG. 28 to 40 are diagrams illustrating a first process for forming a 3D DRAM cell according to some embodiments of the present disclosure. 3 4 is a cross-sectional view of an intermediate structure during the method of FIG. 28 to 40 are diagrams illustrating a first process for forming a 3D DRAM cell according to some embodiments of the present disclosure. 3 4 is a cross-sectional view of an intermediate structure during the method of FIG. 28 to 40 are diagrams illustrating a first process for forming a 3D DRAM cell according to some embodiments of the present disclosure. 3 4 is a cross-sectional view of an intermediate structure during the method of FIG. 28 to 40 illustrate a first process for forming a 3D DRAM cell according to some embodiments of the present disclosure. 3 4 is a cross-sectional view of an intermediate structure during the method of FIG. 28 to 40 are diagrams illustrating a first process for forming a 3D DRAM cell according to some embodiments of the present disclosure. 34 is a cross-sectional view of an intermediate structure during the method of FIG.

[0036] FIG. 40 illustrates a first process for forming a 3D DRAM cell according to some embodiments of the present disclosure. 3 4 is a cross-sectional view of an intermediate structure during the method of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008]

[0013] For ease of understanding, wherever possible, the same reference numbers have been used to designate identical elements that are common to several figures.

[0009]

[0014] FIELD OF THE DISCLOSURE The embodiments described herein relate generally to semiconductor processing, and in particular to methods of forming three-dimensional (3D) dynamic random access memories (DRAMs) and 3D DRAMs. According to various embodiments, a film stack is formed on a substrate. The film stack includes, for example, five or more layers, where each of the five or more layers is formed of a material selected from a group of three or less different materials, and in some embodiments, is formed of a material selected from a group of two or less different materials. The film stack is formed of one or more unit stacks, where each unit stack is formed of two or less different materials. The film stack is used as a mold to form a 3D DRAM device. In particular, the mold is used to form two or more vertically stacked symmetrical DRAM pairs. In processes using a mold, increasing the number of different materials used in the layers of the mold can result in increased processing costs, including using additional deposition and etching processes. By reducing the number of different materials used in the layers, such as by various embodiments described herein, the cost of processing can be reduced, such as by having fewer deposition and etching processes, thus resulting in a more cost-effective device. Furthermore, various numbers of vertically stacked symmetric DRAM pairs can be realized without adding additional different materials. Various embodiments herein can also realize single or double gate transistors for 3D DRAM.

[0010]

[0015] A variety of different embodiments are described below. While features of various embodiments may be described together in a process flow or system, the features may each be implemented separately or individually and / or in different process flows or different systems. Additionally, while various process flows are described as being performed sequentially, other embodiments may perform the process flows in different orders and / or with more or fewer operations. Additionally, while source and drain nodes and source and drain regions are described in various embodiments, such description may be more generally with respect to source / drain nodes or source / drain regions. Additionally, while in some embodiments, n-type transistors are described, more generally, any type of transistor may be implemented.

[0011]

[0016] 1 is a circuit schematic diagram of a dynamic random access memory (DRAM) cell according to some embodiments of the present disclosure. The DRAM cell includes an n-type transistor 2 and a capacitor 4. A drain node 6 of the n-type transistor 2 is electrically connected to a bit line (BL) node 8. A source node 10 of the n-type transistor 2 is electrically connected to a first terminal of the capacitor 4, and a second terminal (opposite the first terminal) of the capacitor 4 is electrically connected to a power supply node (e.g., a ground node). A gate node 12 of the n-type transistor 2 is electrically connected to a word line (WL) node.

[0012]

[0017] FIG. 2 is a perspective view of a symmetric DRAM pair according to some embodiments of the present disclosure. FIG. 2 depicts two DRAM cells that are symmetric along a vertical axis. For convenience, this may be referred to as a symmetric DRAM pair herein. As will become apparent from the following description, multiple symmetric DRAM pairs (e.g., two pairs, three pairs, etc.) may be stacked vertically in a DRAM structure. To avoid unnecessarily obscuring aspects of the drawing, one DRAM cell of the symmetric DRAM pair is labeled with a reference number. Those skilled in the art will readily appreciate the symmetrical components in the other DRAM cell of the symmetric DRAM pair.

[0013]

[0018] The DRAM cell includes an n-type transistor 22 and a capacitor 24. The n-type transistor 22 includes a semiconductor material 26 that forms an active region of the n-type transistor 22. The semiconductor material 26 may generally be, for example, p-type doped. A drain region 28 and a source region 30 are disposed within the semiconductor material 26, and a channel region exists within the semiconductor material 26 between the drain region 28 and the source region 30. The drain region 28 and the source region 30 are n-type doped in this embodiment. A gate dielectric layer 32 is disposed on the semiconductor material 26 (e.g., on a top surface of the semiconductor material 26), and a gate electrode 34 is disposed on the gate dielectric layer 32.

[0014]

[0019] The capacitor 24 includes an outer plate 36, a capacitor dielectric layer 38, and an inner plate 40. The outer plate 36 is a conductive material, such as a metal or a metal-containing material. The outer plate 36 generally has a shape such as a cylinder capped on one side or a rectangular prism capped on one side. The outer plate 36 generally extends laterally from the n-type transistor 22 and has a capped end that contacts the source region 30 of the n-type transistor 22 to electrically connect the source region 30 to the capacitor 24. The end of the outer plate 36 opposite the n-type transistor 22 is open. The capacitor dielectric layer 38 is a dielectric material conformally disposed along the inner surface of the outer plate 36. The dielectric material of the capacitor dielectric layer 38 can be a high dielectric constant (high-k) dielectric material (e.g., having a k value greater than 4.0). The inner plate 40 is a conductive material, such as a metal or a metal-containing material, that is disposed on the capacitor dielectric layer 38 and fills the remaining interior of the outer plate 36.

[0015]

[0020] A bitline contact 42 is disposed in lateral contact with drain region 28 of n-type transistor 22. Bitline contact 42 extends vertically, with the vertical axis along which the symmetric DRAM pair is symmetrical extending along bitline contact 42. A power contact 44 (e.g., a ground contact) is disposed in lateral contact with inner plate 40 of capacitor 24.

[0016]

[0021] FIG. 3 is a perspective view of a symmetrical DRAM pair according to some embodiments of the present disclosure. The 3D DRAM cell of FIG. 3 is similar to the 3D DRAM of FIG. 2, and common descriptions are omitted for simplicity. The DRAM cell includes an n-type transistor 52 and a capacitor 24. The n-type transistor 52 includes a semiconductor material 54 that forms an active region of the n-type transistor 52. The semiconductor material 54 may generally be p-type doped, for example. A drain region 56 and a source region 58 are disposed in the semiconductor material 54, and a channel region exists between the drain region 56 and the source region 58 in the semiconductor material 54. The drain region 56 and the source region 58 are n-type doped in this embodiment. An upper gate dielectric layer 60 is disposed on the semiconductor material 54 (e.g., on a top surface of the semiconductor material 54), and a lower gate dielectric layer 62 is disposed on the semiconductor material 54 opposite the upper gate dielectric layer 60 (e.g., on a bottom surface of the semiconductor material 54). An upper gate electrode 64 is disposed on (eg, overlapping) the upper gate dielectric layer 60 , and a lower gate electrode 66 is disposed on (eg, below) the lower gate dielectric layer 62 .

[0017]

[0022] The capped end of outer plate 36 contacts source region 58 of n-type transistor 52, electrically connecting source region 58 to capacitor 24. A bitline contact 42 is positioned laterally in contact with drain region 56 of n-type transistor 52.

[0018]

[0023] 4 to 12 are cross-sectional views of intermediate structures during a first method for forming a 3D DRAM cell according to some embodiments of the present disclosure. The 3D DRAM cell formed according to the first method of FIG. 4 to FIG. 12 may be as shown in FIG.

[0019]

[0024] Referring to FIG. 4, a film stack is deposited on a substrate 100. The film stack includes a number of unit stacks (e.g., two unit stacks in the illustrated embodiment) that are partially sacrificially used to form 3D DRAM cells. As will become apparent, this method forms two layers of 3D DRAM cells. In other embodiments, it may be possible to form further layers of 3D DRAM cells by repeating the unit stacks of the film stack. It may also be possible to form one layer of 3D DRAM cells by using one step of the unit stacks in the film stack.

[0020]

[0025] Substrate 100 may include any suitable semiconductor substrate, such as a bulk substrate or a semiconductor-on-insulator (SOI) substrate. In some embodiments, the semiconductor substrate is a bulk silicon wafer. Example substrate sizes include 200 mm diameter, 350 mm diameter, 400 mm diameter, and 450 mm diameter, among others. Substrate 100 may further include any layer (e.g., any number of other dielectric layers) or structure over the semiconductor substrate.

[0021]

[0026] The film stack includes a plurality of unit stacks. In this case, the unit stack includes a first dielectric layer 102, a semiconductor layer 104, and a second dielectric layer 106. The unit stack of the film stack is or is composed of the first dielectric layer 102, the semiconductor layer 104 on the first dielectric layer 102, and the second dielectric layer 106 on the semiconductor layer 104. In FIG. 4, two steps of this unit stack are stacked on the substrate 100. The first dielectric layers 102 can each be the same dielectric material. The second dielectric layers 106 can each be the same dielectric material. This is a dielectric material that is different from the dielectric material of the first dielectric layer 102 and has an etch selectivity with the dielectric material of the first dielectric layer 102. The semiconductor layers 104 can each be the same semiconductor material. As will become clear, the materials of the different layers generally allow the target layer to be selectively etched during processing. The film stack is used as a mold for forming a DRAM cell. In some embodiments, the first dielectric layer 102 is silicon oxide, the second dielectric layer 106 is silicon nitride, and the semiconductor layer 104 is silicon (e.g., amorphous silicon or polycrystalline silicon, which may be p-type doped) or InGaZnO. Each of the first dielectric layer 102, the semiconductor layer 104, and the second dielectric layer 106 may be deposited by any suitable deposition technique, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0022]

[0027] 5, an opening 108 is formed through the film stack (e.g., through the first dielectric layer 102, the semiconductor layer 104, and the second dielectric layer 106). The opening 108 may be formed using an anisotropic etch, such as a reactive ion etch (RIE).

[0023]

[0028] In FIG. 6, the second dielectric layer 106 is recessed from the opening 108 to form a recess 110 laterally from the opening 108. The recess process may be any suitable isotropic etch that selectively etches the second dielectric layer 106. For example, when the second dielectric layer 106 is silicon nitride, a high temperature phosphoric acid etch process may be used to recess the second dielectric layer 106. The multiple layers in the film stack (e.g., the first dielectric layer 102 and the semiconductor layer 104) may reduce the likelihood of collapse occurring when recessing the second dielectric layer 106.

[0024]

[0029] 7 shows a gate dielectric layer 112, a gate barrier and / or work function tuning ("barrier / tuning") layer 114, a gate electrode fill material 116, and a dielectric fill material 118. The gate dielectric layer 112 is formed on a surface of each semiconductor layer 104 exposed by the opening 108 and the lateral recess 110. The gate dielectric layer 112 can be any suitable dielectric material formed by any suitable process. In some embodiments, the gate dielectric layer 112 is an oxide formed by an oxidation process (e.g., by oxidizing the exposed surface of the semiconductor layer 104). In some embodiments, the gate dielectric layer 112 can be another material formed by a conformal deposition process, such as atomic layer deposition (ALD).

[0025]

[0030] A gate barrier / tuning layer 114 is then conformally formed along the surfaces of the lateral recesses 110, and a gate electrode fill material 116 is formed on the gate barrier / tuning layer 114. In some embodiments, the gate barrier / tuning layer 114 is formed using a conformal deposition process, such as ALD. The conformal deposition process may form a conformal layer on the surfaces (e.g., including the gate dielectric layer 112) defining the opening 108 and the lateral recesses 110. A conductive material of the gate electrode fill material 116 may then be deposited on the conformal layer by any suitable deposition process. A node isolation process is performed to remove a portion of the conductive material of the gate electrode fill material 116 and a portion of the conformal layer of the gate barrier / tuning layer 114 to form the gate barrier / tuning layer 114 and the gate electrode fill material 116 in each lateral recess 110. The node isolation process may include performing an anisotropic etch, such as RIE, followed by an isotropic etch selective to the material of the gate barrier / tuning layer 114 and the gate electrode fill material 116. The anisotropic etch may remove the conductive material of the gate electrode fill material 116 and the conformal layer of the gate barrier / tuning layer 114 between the vertical sidewall surfaces of the first dielectric layer 102 and the second dielectric layer 106 that define the opening 108. The isotropic etch may laterally recess the gate electrode fill material 116 and the gate barrier / tuning layer 114 to have vertical sidewalls that are offset from the vertical sidewall surfaces of the first dielectric layer 102 and the semiconductor layer 104 that define the opening 108. In some embodiments, the gate barrier / tuning layer 114 may be any suitable diffusion barrier material and / or any work function tuning material to tune the threshold voltage of the transistor, such as TiN. In some embodiments, the gate electrode fill material 116 may be any conductive material, such as a metal, such as tungsten.

[0026]

[0031] A dielectric fill material 118 is then formed in the lateral recesses 110 and the remaining unfilled portions of the opening 108. The dielectric fill material 118 can be any suitable dielectric material deposited by any suitable deposition process. In some embodiments, the dielectric fill material 118 is an oxide deposited by a conformal deposition, such as ALD, or a dielectric deposition process, such as flowable CVD (FCVD).

[0027]

[0032] In FIG. 8, openings 120 are formed through the film stack (e.g., through the first dielectric layer 102, the semiconductor layer 104, and the second dielectric layer 106). As will become apparent, each opening 120 is used in the formation of a capacitor that will be electrically connected with a respective transistor. The gate electrode fill material 116 and the gate barrier / tuning layer 114 are part of the respective transistor. Each opening 120 is located some lateral distance from the corresponding gate electrode fill material 116 and the gate barrier / tuning layer 114. The corresponding gate electrode fill material 116 and the gate barrier / tuning layer 114 are located at a lateral position between the respective opening 120 and the position where the opening 108 was formed (e.g., filled with the dielectric fill material 118). The openings 120 may be formed using an anisotropic etch, such as reactive ion etching (RIE).

[0028]

[0033] 9, the semiconductor layer 104 is recessed from each opening 120 to form a lateral recess 122 from each opening 120. The recess process may be any suitable isotropic etch that selectively etches the semiconductor layer 104. For example, when the semiconductor layer 104 is silicon, a tetramethylammonium hydroxide (TMAH) etching process or a dry plasma isotropic etch may be used to recess the semiconductor layer 104.

[0029]

[0034] The semiconductor layer 104 is doped at the vertical sidewall surfaces of the semiconductor layer 104 in each lateral recess 122 to form source regions 124. The source regions 124 may be doped with an n-type dopant. The doping may be performed using a gas phase dopant and / or a plasma assisted doping process.

[0030]

[0035] In FIG. 10, the lateral recess 122 is enlarged to form an enlarged lateral recess 126. The enlargement may include an isotropic etch that selectively etches the second dielectric layer 106 and an isotropic etch that selectively etches the first dielectric layer 102. The isotropic etch may be a wet or dry etch. In some examples where the first dielectric layer 102 is silicon oxide and the second dielectric layer 106 is silicon nitride, a high temperature phosphoric acid etch process or a dry plasma etch process may be used to etch the second dielectric layer 106, and a hydrofluoric acid based process (e.g., wet diluted hydrofluoric acid (dHF) or dry HF process) may be used to etch the first dielectric layer 102.

[0031]

[0036] FIG. 11 illustrates the formation of capacitors in the enlarged lateral recesses 126. Each capacitor includes an outer plate 130, a capacitor dielectric layer 132, and an inner plate 134. The outer plates 130 are conformally formed along the surfaces of the enlarged lateral recesses 126. In some embodiments, the outer plates 130 are formed using a conformal deposition process, such as ALD. The conformal deposition process may form a conformal layer on the surfaces defining the openings 120 and the enlarged lateral recesses 126 (e.g., including the respective sidewall surfaces of the semiconductor layer 104 in which the corresponding source regions 124 are disposed). A node isolation process is performed to remove portions of the conformal layer on the vertical sidewalls defining the openings 120 to form the outer plates 130 in each enlarged lateral recess 126. The node isolation process may include filling the opening 120 and the enlarged lateral recess 126 with a fill material, and performing appropriate anisotropic and isotropic etching processes to remove portions of the conformal layer from the vertical sidewalls defining the opening 120 (e.g., the vertical sidewalls of the first dielectric layer 102 and the second dielectric layer 106) and to remove the fill material.

[0032]

[0037] A capacitor dielectric layer 132 is then formed on the inner surface of each outer plate 130. The capacitor dielectric layer 132 may be formed by conformal deposition, such as ALD, that forms a conformal capacitor dielectric layer 132 within each opening 120 (e.g., along the vertical sidewalls of the first dielectric layer 102 and second dielectric layer 106 that define the opening 120) and on the inner surface of each outer plate 130.

[0033]

[0038] The inner plate 134 is then formed on the outer plate 130. The inner plate 134 may be formed by a conformal deposition, such as ALD, that forms the inner plate 134 on the capacitor dielectric layer 132. In one illustrated embodiment, the inner plate 134 fills the remaining unfilled portion of the enlarged lateral recess 126, although in some embodiments the inner plate 134 may not fill the remaining unfilled portion of the enlarged lateral recess 126. As illustrated, the inner plate 134 may be formed by a continuous material deposited in the respective openings 120 and the enlarged lateral recess 126. As described with respect to FIG. 1, the inner plates 134 may be electrically connected together by the continuous material that forms the inner plate 134, since the inner plates 134 form the terminals of the respective DRAM cells that are electrically connected to a power supply node (e.g., a ground node). In one illustrated embodiment, the material of the inner plate 134 does not fill the openings 120, and a conductive fill material 136 is formed in the unfilled portion of the openings 120. In some embodiments, the material of the inner plates 134 fills the remaining unfilled portions of the openings 120. The inner plates 134 are, for example, electrically connected together by the material of the inner plates 134 and / or the conductive fill material 136 forms a power node (e.g., a ground node) connected between the DRAM cells. In embodiments in which a conductive fill material 136 is used, the conductive fill material 136 may be deposited by any suitable deposition process, such as CVD or PVD.

[0034]

[0039] In some embodiments, the material of the outer plate 130 and the material of the inner plate 134 can be any conductive material, such as a metal or a metal-containing material, such as TiN. In some embodiments, the material of the capacitor dielectric layer 132 can be any dielectric material, and further can be any high-k dielectric material (e.g., having a k value greater than 4.0). In some embodiments, the conductive fill material 136 can be any conductive material, such as silicon germanium (e.g., doped silicon germanium).

[0035]

[0040] In FIG. 12, a drain region 138, a barrier layer 140, and a conductive fill material 142 are formed. An opening is formed through the dielectric fill material 118. The opening exposes the vertical sidewalls of the semiconductor layer 104. An etching process can be used to form the opening and expose the vertical sidewalls of the semiconductor layer 104. For example, the etching process can include anisotropic etching and / or isotropic etching. The gate dielectric layer 112 previously formed on the vertical sidewalls of the semiconductor layer 104 is removed by the etching process to expose the vertical sidewalls of the semiconductor layer 104.

[0036]

[0041] The lateral portions of the semiconductor layer 104 at each vertical sidewall exposed by the opening are doped to form a drain region 138. The drain region 138 may be doped with an n-type dopant. The doping may be performed using a gas phase dopant and / or a plasma assisted doping process. Once the drain region 138 is formed, a respective transistor is formed for the DRAM cell. For each DRAM cell, the transistor includes a source region 124 in the semiconductor layer 104, a drain region 138 in the semiconductor layer 104, a channel region in the semiconductor region 104 between the source region 124 and the drain region 138, and a gate structure disposed on the semiconductor layer 104 aligned over the channel region. The gate structure includes a gate dielectric layer 112 and a gate electrode fill material 116. This method may allow a very thin portion of the semiconductor layer 104 to be implemented for the channel region of the transistor.

[0037]

[0042] A barrier layer 140 is then formed in the opening. The barrier layer 140 is conformally formed along the surfaces of the opening, including along the exposed vertical sidewalls of the semiconductor layer 104 where the drain region 138 is located. In some embodiments, the barrier layer 140 is formed using a conformal deposition process, such as ALD. A conductive fill material 142 may then be deposited on the barrier layer 140 by any suitable deposition process. In some embodiments, the barrier layer 140 may be any suitable diffusion barrier material, such as TiN. In some embodiments, the conductive fill material 142 may be any conductive material, such as a metal, such as tungsten. The barrier layer 140 and the conductive fill material 142 generally form a contact, which may be a bitline node of a DRAM cell. This contact is along a vertical axis about which a symmetrical DRAM pair is symmetrical.

[0038]

[0043] 13 to 27 are cross-sectional views of intermediate structures during a second method for forming a 3D DRAM cell according to some embodiments of the present disclosure. The 3D DRAM cell formed according to the second method of FIGs. 13 to 27 may be as shown in FIG.

[0039]

[0044] Referring to FIG. 13, a film stack is deposited on a substrate 100. The film stack includes a number of unit stacks (e.g., two unit stacks in the illustrated embodiment) that are partially sacrificially used to form 3D DRAM cells. As will become apparent, this method forms two layers of 3D DRAM cells. In other embodiments, it may be possible to form further layers of 3D DRAM cells by repeating the unit stacks of the film stack. It may also be possible to form one layer of 3D DRAM cells by using one step of the unit stacks in the film stack.

[0040]

[0045] The film stack includes a plurality of unit stacks. In this case, the unit stack includes a sacrificial layer 202 and a dielectric layer 204. The unit stack of the film stack is or consists of a sacrificial layer 202 and a dielectric layer 204 on the sacrificial layer 202. In FIG. 13, two steps of this unit stack are stacked on the substrate 100. The sacrificial layers 202 can each be the same material. The dielectric layers 204 can each be the same dielectric material, which is a different dielectric material from the material of the sacrificial layer 202 and has an etch selectivity between them. As will become clear, the materials of the different layers generally allow the target layer to be selectively etched during processing. The film stack is used as a mold to form a DRAM cell. In some embodiments, sacrificial layer 202 is silicon, silicon germanium, doped silicon oxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or silicon nitride, and dielectric layer 204 is silicon oxide. Each of sacrificial layer 202 and dielectric layer 204 may be deposited by any suitable deposition technique, such as CVD or PVD.

[0041]

[0046] 14, an opening 206 is formed through the film stack (e.g., through the sacrificial layer 202 and the dielectric layer 204). The opening 206 may be formed using an anisotropic etch, such as RIE.

[0042]

[0047] 15, the dielectric layer 204 is recessed from the opening 206 to form a lateral recess 208 from the opening 206. The recession process may be any suitable isotropic etch that selectively etches the dielectric layer 204. For example, when the dielectric layer 204 is silicon oxide, a hydrofluoric acid based process (e.g., a wet dHF or dry HF process) may be used to etch the dielectric layer 204.

[0043]

[0048] In FIG. 16, a semiconductor layer 210 is formed filling the lateral recess 208. The semiconductor layer 210 may be formed using a conformal deposition, such as ALD, which conformally deposits the material of the semiconductor layer 210 along the surfaces that define the opening 206 and the lateral recess 208. An anisotropic etch may be used to remove the material of the semiconductor layer 210 from between the sidewalls of the sacrificial layer 202 that define the opening 206. The semiconductor layer 210 may be any semiconductor material. In some embodiments, the semiconductor layer 210 is silicon (e.g., amorphous silicon or polycrystalline silicon, which may be p-type doped) or InGaZnO.

[0044]

[0049] 17, the sacrificial layer 202 is recessed from the opening 206 to form a lateral recess 212 from the opening 206. In some embodiments, the sacrificial layer 202 is recessed to or beyond a corresponding vertical sidewall of the semiconductor layer 210 distal from the opening 206. The recession process may be any suitable isotropic etch that selectively etches the sacrificial layer 202. For example, when the sacrificial layer 202 is silicon nitride, a high temperature phosphoric acid etch process may be used to recess the sacrificial layer 202.

[0045]

[0050] FIG. 18 illustrates the conformal sacrificial material 214 and the dielectric fill material 216. The conformal sacrificial material 214 may be formed using a conformal deposition, such as ALD, which conformally deposits the material of the conformal sacrificial material 214 along the surfaces (e.g., the vertical sidewalls of the sacrificial layer 202 and the exposed surface of the semiconductor layer 210) that define the opening 206 and the lateral recess 212. The dielectric fill material 216 may be deposited on the conformally deposited material of the conformal sacrificial material 214 by any suitable deposition, such as ALD or FCV, thereby filling the remaining unfilled portions of the opening 206 and the lateral recess 212. An anisotropic etch may be used to remove the material of the conformal sacrificial material 214 and the dielectric fill material 216 from between the sidewalls of the semiconductor layer 210 that define the opening 206, for example. Conformal sacrificial material 214 can be any sacrificial material, such as a sacrificial dielectric material, and dielectric fill material 216 can be any dielectric material. In some embodiments, conformal sacrificial material 214 is silicon nitride and dielectric fill material 216 is silicon oxide.

[0046]

[0051] 19, lateral portions of the conformal sacrificial material 214 are recessed from the openings 206 to form lateral recesses 218 from the openings 206. The dielectric fill material 216 formed on each of the conformal sacrificial materials 214 may remain vertically disposed between the lateral recesses 218 formed by the recessed respective conformal sacrificial materials 214. The recession process may be any suitable isotropic etch that selectively etches the conformal sacrificial material 214. For example, a high temperature phosphoric acid etch process may be used to recess the conformal sacrificial material 214 when the conformal sacrificial material 214 is silicon nitride.

[0047]

[0052] 20 illustrates a gate dielectric layer 220, a gate barrier / tuning layer 222, a gate electrode fill material 224, and a dielectric fill material 226. The gate dielectric layer 220 is formed on the surfaces of the respective semiconductor layer 210 exposed by the opening 206 and the lateral recess 218. The gate dielectric layer 220 can be any suitable dielectric material formed by any suitable process. In some embodiments, the gate dielectric layer 220 is an oxide formed by an oxidation process (e.g., by oxidizing the exposed surfaces of the semiconductor layer 210). In some embodiments, the gate dielectric layer 220 can be another material formed by a conformal deposition process, such as ALD.

[0048]

[0053] A gate barrier / tuning layer 222 is then conformally formed along the surfaces of the lateral recesses 218, and a gate electrode fill material 224 is formed on the gate barrier / tuning layer 222. In some embodiments, the gate barrier / tuning layer 222 is formed using a conformal deposition process, such as ALD. The conformal deposition process may form a conformal layer on the surfaces (e.g., including the gate dielectric layer 220) defining the opening 206 and the lateral recesses 218. A conductive material of the gate electrode fill material 224 may then be deposited on the conformal layer by any suitable deposition process. A node isolation process is performed to remove a portion of the conductive material of the gate electrode fill material 224 and a portion of the conformal layer of the gate barrier / tuning layer 222 to form the gate barrier / tuning layer 222 and the gate electrode fill material 224 in the respective lateral recesses 208. The node isolation process may include performing an anisotropic etch, such as RIE, followed by an isotropic etch selective to the materials of the gate barrier / tuning layer 222 and the gate electrode fill material 224. The anisotropic etch may remove the conductive material of the gate electrode fill material 224 and the conformal layer of the gate barrier / tuning layer 222 between, for example, the vertical sidewall surfaces of the dielectric fill material 216 and the semiconductor layer 210 that define the opening 206. The isotropic etch may laterally recess the gate electrode fill material 224 and the gate barrier / tuning layer 222 to have vertical sidewalls that are offset from the vertical sidewall surfaces of the dielectric fill material 216 and the semiconductor layer 210 that define the opening 206. In some embodiments, the gate barrier / tuning layer 222 may be any suitable diffusion barrier material and / or any work function tuning material to tune the threshold voltage of the transistor, such as TiN. In some embodiments, the gate electrode fill material 224 may be any conductive material, such as a metal, such as tungsten.

[0049]

[0054] A dielectric fill material 226 is then formed in the lateral recesses 208 and the remaining unfilled portions of the opening 206. The dielectric fill material 226 can be any suitable dielectric material deposited by any suitable deposition process. In some embodiments, the dielectric fill material 226 is an oxide deposited by a conformal deposition, such as ALD, or an inductive deposition process, such as FCVD.

[0050]

[0055] In FIG. 21, openings 228 are formed through the film stack (e.g., through the sacrificial layer 202 and the dielectric layer 204). As will become apparent, each opening 228 is used in the formation of a capacitor that will be electrically connected to a respective transistor. The gate electrode fill material 224 and the gate barrier / tuning layer 222 are part of the respective transistor. Each opening 228 is located some lateral distance from the corresponding gate electrode fill material 224 and gate barrier / tuning layer 222. The corresponding gate electrode fill material 224 and gate barrier / tuning layer 222 are located at a lateral position between the respective opening 228 and the position where the opening 206 was formed (e.g., filled with the dielectric fill material 226). The openings 228 may be formed using an anisotropic etch, such as RIE.

[0051]

[0056] In FIG. 22 , the sacrificial layer 202 is recessed from each opening 228 to form a lateral recess 230 from each opening 228. In some embodiments, the sacrificial layer 202 is removed by a recess process. In some embodiments as shown, the recess process may also remove the conformal sacrificial material 214, such as when the sacrificial layer 202 and the conformal sacrificial material 214 are the same material. The recess process may be any isotropic etch that selectively etches the sacrificial layer 202. For example, when the sacrificial layer 202 is silicon nitride, a high temperature phosphoric acid etch process may be used to recess the sacrificial layer 202 and possibly also the conformal sacrificial material 214.

[0052]

[0057] FIG. 23 illustrates a conformal dielectric material 232 and a dielectric fill material 234. The conformal dielectric material 232 may be formed using a conformal deposition, such as ALD, which conformally deposits the material of the conformal dielectric material 232 along the surfaces (e.g., the dielectric layer 204, the dielectric fill material 216, and the exposed surfaces of the gate barrier / tuning layer 222) that define the opening 228 and the lateral recess 230. The dielectric fill material 234 may be deposited on the conformally deposited material of the conformal dielectric material 232 by any suitable deposition, such as ALD or FCV, thereby filling the remaining unfilled portions of the opening 228 and the lateral recess 230. An anisotropic etch may be used to remove the material of the conformal dielectric material 232 and the dielectric fill material 234, for example, from between the sidewalls of the dielectric layer 204 that define the opening 228. Conformal dielectric material 232 and dielectric fill material 234 can be any dielectric materials that can be selectively etched with respect to one another (e.g., the material of conformal dielectric material 232 is different from the material of dielectric fill material 234). In some embodiments, conformal dielectric material 232 is silicon nitride and dielectric fill material 234 is silicon oxide.

[0053]

[0058] 24, the dielectric layer 204 is recessed from the opening 228 to the respective semiconductor layer 210 to form a lateral recess 236 from the opening 228. The recess process may be any suitable isotropic etch that selectively etches the dielectric layer 204. For example, when the dielectric layer 204 is silicon oxide, a hydrofluoric acid based process (e.g., a wet dHF or dry HF process) may be used to etch the dielectric layer 204.

[0054]

[0059] The semiconductor layer 210 is doped at the vertical sidewall surfaces of the semiconductor layer 210 in each lateral recess 236 to form source regions 238. The source regions 238 may be doped with an n-type dopant. The doping may be performed using a gas phase dopant and / or a plasma assisted doping process.

[0055]

[0060] 25, the lateral recess 236 is enlarged to form an enlarged lateral recess 240. The enlargement may include an isotropic etch that selectively etches the conformal dielectric material 232. The isotropic etch may be a wet or dry etch. In some embodiments where the conformal dielectric material 232 is silicon nitride, a high temperature phosphoric acid etch process or a dry plasma etch process may be used to etch the conformal dielectric material 232.

[0056]

[0061] 26 illustrates the formation of capacitors within enlarged lateral recesses 240. Each capacitor includes an outer plate 130, a capacitor dielectric layer 132, and an inner plate 134, as described above with respect to FIG.

[0057]

[0062] In FIG. 27, the drain region 242, the barrier layer 140, and the conductive fill material 142 are formed. An opening is formed through the dielectric fill material 226. The opening exposes the vertical sidewalls of the semiconductor layer 210. An etching process can be used to form the opening and expose the vertical sidewalls of the semiconductor layer 210. For example, the etching process can include anisotropic etching and / or isotropic etching. The gate dielectric layer 220 previously formed on the vertical sidewalls of the semiconductor layer 210 is removed by the etching process to expose the vertical sidewalls of the semiconductor layer 210.

[0058]

[0063] The lateral portions of the semiconductor layer 210 at the respective vertical sidewalls exposed by the openings are doped to form drain regions 242. The drain regions 242 may be doped with an n-type dopant. The doping may be performed using a gas phase dopant and / or a plasma assisted doping process. Once the drain regions 242 are formed, a respective transistor is formed for the DRAM cell. For each DRAM cell, the transistor includes a source region 238 in the semiconductor layer 210, a drain region 242 in the semiconductor layer 210, a channel region in the semiconductor region 210 between the source region 238 and the drain region 242, a first (e.g., upper) gate structure disposed on the semiconductor layer 210 aligned above the channel region, and a second (e.g., lower) gate structure disposed below the semiconductor layer 210 aligned below the channel region. Each of the first and second gate structures includes a respective gate dielectric layer 220 and a respective gate electrode fill material 224.

[0059]

[0064] A barrier layer 140 and a conductive fill material 142 are then formed in the opening as described with respect to Figure 12. The barrier layer 140 and the conductive fill material 142 generally form a contact, which may be a bitline node of a DRAM cell, along a vertical axis about which a symmetrical DRAM pair is symmetric.

[0060]

[0065] 28 through 40 illustrate a first step for forming a 3D DRAM cell according to some embodiments of the present disclosure. 3 27A-27C are cross-sectional views of intermediate structures during the method of FIG. 25. A 3D DRAM cell formed according to the third method of FIG.

[0061]

[0066] Referring to FIG. 28, a film stack is deposited on a substrate 100. The film stack includes a number of unit stacks (e.g., two unit stacks in the illustrated embodiment) that are partially sacrificially used to form 3D DRAM cells. As will become apparent, this method forms two layers of 3D DRAM cells. In other embodiments, it may be possible to form further layers of 3D DRAM cells by repeating the unit stacks of the film stack. It may also be possible to form one layer of 3D DRAM cells by using one step of the unit stacks in the film stack.

[0062]

[0067] The film stack includes a plurality of unit stacks. In this case, the unit stack includes a sacrificial layer 302 and a semiconductor layer 304. The unit stack of the film stack is or consists of a sacrificial layer 302 and a semiconductor layer 304 on the sacrificial layer 302. In FIG. 28, two steps of this unit stack are stacked on the substrate 100. The sacrificial layers 302 can each be the same material. The semiconductor layers 304 can each be the same material, which is a different material from the material of the sacrificial layer 302 and has an etch selectivity between the material of the sacrificial layer 302. As will become apparent, the materials of the different layers generally allow the target layers to be selectively etched during processing. The film stack is used as a mold to form a DRAM cell. In some embodiments, the sacrificial layer 302 is silicon germanium, silicon oxide, doped silicon oxide, BPSG. 、B S G、 In some specific embodiments, the sacrificial layer 302 is amorphous or crystalline silicon germanium and the semiconductor layer 304 is amorphous or crystalline silicon. The sacrificial layer 302 and the semiconductor layer 304 may be deposited by any suitable deposition technique, such as CVD or PVD.

[0063]

[0068] In some embodiments, the sacrificial layer 302 and the semiconductor layer 304 are semiconductor materials, and further, are epitaxial or crystalline (e.g., single crystal) semiconductor materials. In some embodiments, a film stack can be formed by epitaxially growing the sacrificial layer 302 on the substrate 100, epitaxially growing the semiconductor layer 304 on the sacrificial layer, and repeatedly epitaxially growing the sacrificial layer 302 and the semiconductor layer 304 to implement a desired number of layers in the film stack. Using an epitaxial or crystalline (e.g., single crystal) material, such as silicon germanium, as the sacrificial layer 302 allows for the deposition of the sacrificial layer 302 and the semiconductor layer 304 by epitaxial growth. This allows the semiconductor layer 304 (as well as the active regions, including the source / drain regions and channel regions of the transistors, as will become apparent) to be crystalline (e.g., single crystal). In some particular embodiments, sacrificial layer 302 is epitaxial or crystalline (eg, single crystal) silicon germanium and semiconductor layer 304 is epitaxial or crystalline (eg, single crystal) silicon.

[0064]

[0069] In Figure 29, an opening 306 is formed through the film stack (e.g., through the sacrificial layer 302 and the semiconductor layer 304). The opening 306 may be formed using an anisotropic etch, such as RIE.

[0065]

[0070] In Figure 30, the sacrificial layer 302 is recessed from the opening 306 to form a lateral recess 308 from the opening 306. The recession process may be any suitable isotropic etch that selectively etches the sacrificial layer 302. For example, when the sacrificial layer 302 is silicon germanium, a mixture of hydrofluoric acid (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH) in a ratio of 1:2:3 (HF:H2O2:CH3COOH) may be used to etch the sacrificial layer 302.

[0066]

[0071] FIG. 31 illustrates a conformal sacrificial material 310 and a dielectric fill material 312. The conformal sacrificial material 310 may be formed using a conformal deposition, such as ALD, which conformally deposits the material of the conformal sacrificial material 310 along the surfaces (e.g., the vertical sidewalls of the sacrificial layer 302 and the exposed surface of the semiconductor layer 304) that define the opening 306 and the lateral recess 308. The dielectric fill material 312 may be deposited on the conformally deposited material of the conformal sacrificial material 310 by any suitable deposition, such as ALD or FCV, thereby filling the remaining unfilled portions of the opening 306 and the lateral recess 308. An anisotropic etch may be used to remove the material of the conformal sacrificial material 310 and the dielectric fill material 312 from between the sidewalls of the semiconductor layer 304 that define the opening 306, for example. Conformal sacrificial material 310 can be any sacrificial material, such as a sacrificial dielectric material, and dielectric fill material 312 can be any dielectric material. In some embodiments, conformal sacrificial material 310 is silicon nitride and dielectric fill material 312 is silicon oxide.

[0067]

[0072] In FIG. 32 , lateral portions of the conformal sacrificial material 310 are recessed from the openings 306 to form lateral recesses 314 from the openings 306. The dielectric fill material 312 formed on each of the conformal sacrificial materials 310 may remain vertically disposed between the lateral recesses 314 formed by the recessing of each of the conformal sacrificial materials 310. The recessing process may be any suitable isotropic etch that selectively etches the conformal sacrificial material 310. For example, a high temperature phosphoric acid etch process may be used to recess the conformal sacrificial material 310 when the conformal sacrificial material 310 is silicon nitride.

[0068]

[0073] 33 shows the gate dielectric layer 220, the gate barrier / tuning layer 222, the gate electrode fill material 224, and the dielectric fill material 226. The gate dielectric layer 220, the gate barrier / tuning layer 222, and the gate electrode fill material 224 are formed in the lateral recess 314 as described above with respect to FIG. 20, and the dielectric fill material 226 is formed in the opening 306 as described above with respect to FIG.

[0069]

[0074] In FIG. 34, openings 315 are formed through the film stack (e.g., through the sacrificial layer 302 and the semiconductor layer 304) as described above with respect to FIG. 21. As will become apparent, each opening 315 is used in the formation of a capacitor that will be electrically connected to a respective transistor. The gate electrode fill material 224 and the gate barrier / tuning layer 222 are part of a respective transistor. Each opening 315 is disposed some lateral distance from the corresponding gate electrode fill material 224 and gate barrier / tuning layer 222. The corresponding gate electrode fill material 224 and gate barrier / tuning layer 222 are disposed between each opening 315 and the opening. 3 06 is formed (eg, filled with dielectric fill material 226) and

[0070]

[0075] In FIG. 35, the sacrificial layer 302 is recessed from each opening 315 to form a lateral recess 316 from each opening 315. In some embodiments, the sacrificial layer 302 is removed by a recess process. In some embodiments as shown, the recess process may also remove the conformal sacrificial material 310, such as when the sacrificial layer 302 and the conformal sacrificial material 310 are the same material. The recess process may be any isotropic etch that selectively etches the sacrificial layer 302. For example, when the sacrificial layer 302 is silicon germanium, HF, H2O2, and CH3COOH may be mixed in a ratio of 1:2:3 (HF:H2O2:CH3COOH) to recess the sacrificial layer 302.

[0071]

[0076] 36 shows a conformal dielectric material 232 and a dielectric fill material 234 formed within the lateral recess 316. The conformal dielectric material 232 and the dielectric fill material 234 may be formed as described above with respect to FIG.

[0072]

[0077] 37, the sacrificial layer 304 is recessed from the opening 315 to form a lateral recess 318 from the opening 315. The recess process can be any suitable isotropic etch that selectively etches the semiconductor layer 304. For example, when the semiconductor layer 304 is silicon, a TMAH etching process or a dry plasma isotropic etch can be used to recess the semiconductor layer 304.

[0073]

[0078] As described with respect to FIG. 24, the semiconductor layer 304 is doped at the vertical sidewall surfaces of the semiconductor layer 304 in each lateral recess 318 to form source regions 238 .

[0074]

[0079] As described with respect to Figure 25, in Figure 38 the lateral recesses 318 are enlarged to form enlarged lateral recesses 240. Figure 39 shows the formation of capacitors within the enlarged lateral recesses 240. As described above with respect to Figure 11, each capacitor includes an outer plate 130, a capacitor dielectric layer 132, and an inner plate 134. As described with respect to Figure 27, in Figure 40 the drain region 242, barrier layer 140, and conductive fill material 142 are formed.

[0075]

[0080] Once the drain region 242 is formed, a respective transistor is formed for the DRAM cell. For each DRAM cell, the transistor includes a source region 238 in the semiconductor layer 304, a drain region 242 in the semiconductor layer 304, a channel region in the semiconductor region 304 between the source region 238 and the drain region 242, a first (e.g., upper) gate structure disposed on the semiconductor layer 304 aligned above the channel region, and a second (e.g., lower) gate structure disposed below the semiconductor layer 304 aligned below the channel region. Each of the first and second gate structures includes a respective gate dielectric layer 220 and gate electrode fill material 224. The barrier layer 140 and the conductive fill material 142 generally form a contact, which may be a bit line node of the DRAM cell. This contact is along a vertical axis about which the symmetrical DRAM pair is symmetrical.

[0076]

[0081] While the forgoing description is directed to exemplary embodiments of the present disclosure, other and further embodiments may be devised without departing from the basic scope of the disclosure, which scope is defined by the following claims.

Claims

1. 1. A method for semiconductor processing comprising: forming a film stack on a substrate, the film stack including a plurality of unit stacks, each unit stack having a first dielectric layer, a semiconductor layer disposed on the first dielectric layer, and a second dielectric layer disposed on the semiconductor layer; forming a first opening through the membrane stack; recessing the second dielectric layer from the first opening to form a first lateral recess; forming a gate structure disposed within the first lateral recess over a portion of the semiconductor layer; forming a second opening through the film stack, the second opening being laterally disposed from a location where the first opening was formed, the gate structure being disposed at a lateral location between the second opening and the location where the first opening was formed; recessing the portion of the semiconductor layer from the second opening to form a second lateral recess; enlarging the second lateral recess, including removing a portion of the first dielectric layer below the second lateral recess and a portion of the second dielectric layer above the second lateral recess; and forming a capacitor in a region where the enlarged second lateral recess is located, the capacitor contacting the portion of the semiconductor layer.

2. forming the capacitor conformally depositing a first plate along a surface of the enlarged second lateral recess; conformally depositing a capacitor dielectric layer along the first plate; and The method of claim 1 including depositing a second plate on the capacitor dielectric layer.

3. 2. The method of claim 1, further comprising forming a source / drain region in the portion of the semiconductor layer including doping the portion of the semiconductor layer through the second lateral recess, wherein a plate of the capacitor is formed in contact with the source / drain region in the portion of the semiconductor layer.

4. forming source / drain regions in the portion of the semiconductor layer, the source / drain regions including doping the portion of the semiconductor layer; and The method of claim 1 , further comprising forming contacts that extend through the film stack, the contacts contacting the source / drain regions.

5. 1. A method for semiconductor processing comprising: forming a film stack on a substrate, the film stack including a plurality of unit stacks, each unit stack having a first layer and a second layer disposed on the first layer; forming a first opening through the membrane stack; recessing the first layer from the first opening to form a first lateral recess; forming a first conformal layer within the first lateral recess; forming a first fill material over the first conformal layer and within the first lateral recess; recessing the first conformal layer from the first opening to form a second lateral recess; forming a gate structure disposed within the second lateral recess above and below the semiconductor layer, the semiconductor layer being horizontally aligned with the second layer; forming a second opening through the film stack, the second opening being laterally disposed from a location where the first opening was formed, the gate structure being disposed at a lateral location between the second opening and the location where the first opening was formed; recessing the second layer from the second opening to form a third lateral recess to the semiconductor layer; and forming a capacitor in a region where the third lateral recess is located, the capacitor in contact with the semiconductor layer.

6. recessing the second layer from the first opening to form a fourth lateral recess; and The method of claim 5 further comprising forming the semiconductor layer in the fourth lateral recess.

7. The method of claim 5 , wherein the second layer is a semiconductor material, and the semiconductor layer is a portion of the second layer.

8. 6. The method of claim 5, wherein the first layer is a first dielectric material and the second layer is a second dielectric material, the first dielectric material and the second dielectric material being selectively removable with respect to one another.

9. 6. The method of claim 5, wherein the first layer is a first dielectric material and the second layer is a second dielectric material different from the first dielectric material, and each of the first and second dielectric materials is selected from the group consisting of silicon nitride, silicon oxide, doped silicon oxide, borophosphosilicate glass (BPSG), and phosphosilicate glass (PSG).

10. The method of claim 5 , wherein the first layer is a first semiconductor material and the second layer is a second semiconductor material different from the first semiconductor material.

11. The method of claim 10 , wherein the first semiconductor material and the second semiconductor material are amorphous.

12. The method of claim 10 , wherein the first and second semiconductor materials are epitaxial or single crystalline.

13. forming the film stack epitaxially growing the first layer; and The method of claim 5 comprising epitaxially growing the second layer on the first layer.

14. 6. The method of claim 5, wherein the first layer is silicon germanium and the second layer is silicon.

15. 6. The method of claim 5, wherein the first layer is epitaxial silicon germanium and the second layer is epitaxial silicon.

16. 6. The method of claim 5, wherein the first layer is amorphous silicon germanium and the second layer is amorphous silicon.

17. recessing the first layer from the second opening to form a fourth lateral recess; forming a second conformal layer in the fourth lateral recess; and The method of claim 5 , further comprising forming a second fill material in the fourth lateral recess over the second conformal layer.

18. 20. The method of claim 17, further comprising: enlarging the third lateral recess including removing at least a portion of the second conformal layer, the capacitor being formed in the enlarged third lateral recess. forming vertically stacked symmetric DRAM pairs on the substrate using the film stack as a mold, each symmetric DRAM pair of the vertically stacked symmetric DRAM pairs comprising: contact, a first transistor including a first gate structure, a first source / drain region, and a second source / drain region, the first source / drain region in contact with the contact; a second transistor including a second gate structure, a third source / drain region, and a fourth source / drain region, the third source / drain region in contact with the contact, the second transistor being symmetrical to the first transistor about the contact; a first capacitor having a first outer plate, a first capacitor dielectric layer, and a first inner plate, the first outer plate being in contact with the second source / drain region; 6. The method of claim 1, further comprising a second capacitor having a second outer plate, a second capacitor dielectric layer, and a second inner plate, the second outer plate in contact with the fourth source / drain region.

Images