Semiconductor Device

Abstract

To provide a semiconductor device having a structure that can be manufactured with ease even when miniaturized, and capable of suppressing reduction in electric characteristics caused by the miniaturization.SOLUTION: A semiconductor device comprises: an oxide semiconductor layer; a first conductive substance provided so as to be contacted with the oxide semiconductor layer; and an insulator provided so as to be contacted with the first conductive substance. The oxide semiconductor layer, the first conductive substance and the insulator are provided with an opening. Lateral faces of the oxide semiconductor layer, the first conductive substance and the insulator are connected at the opening. The oxide semiconductor layer and the first conductive substance are electrically connected with a second conductive substance by a side contact.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, Manufacture, or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a memory device, a computing device, an imaging device, and The present invention relates to a method for driving these devices or a method for manufacturing these devices.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device or an electronic device may include a semiconductor device. [Background technology]

[0003] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology for constructing thin-film transistors (also called thin-film transistors (TFTs)) is attracting attention. It is widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. As another material for this, oxide semiconductors have been attracting attention.

[0004] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. There are. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165528 A Summary of the Invention [Problem to be solved by the invention]

[0006] The miniaturization of transistors is an essential technology for increasing the density of integrated circuits. As the size of the device becomes smaller, the manufacturing process becomes more difficult, and the on-current, threshold voltage, and S It is known that the electrical characteristics of transistors, such as the subthreshold voltage, deteriorate. In other words, the yield of integrated circuits tends to decrease as transistors become smaller. .

[0007] Therefore, one embodiment of the present invention is a structure that can be manufactured in a simple process even when miniaturized. Another object of the present invention is to provide a semiconductor device having the above-mentioned structure. One of the objects of the present invention is to provide a semiconductor device having a structure capable of suppressing the deterioration of Alternatively, a semiconductor device having a configuration capable of suppressing the deterioration of electrical characteristics that becomes more pronounced with miniaturization is provided. Another object of the present invention is to provide a semiconductor device with a high degree of integration. Another object of the present invention is to provide a semiconductor device in which deterioration of on-current is reduced. Another object is to provide a semiconductor device with low power consumption. It is an object of the present invention to provide a semiconductor device having high reliability. Another object of the present invention is to provide a semiconductor device that can retain data for a long time.

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer, a gate electrode layer, a source electrode layer, or a drain electrode layer. The present invention relates to a semiconductor device in which a layer is electrically connected to a wiring layer by a side contact.

[0010] In this specification, the term "side contact" refers to a contact in an opening formed in one of the elements. The side wall of one element contacts a part of the other element formed in the opening. This refers to a state in which an electrical connection is obtained between one element and another.

[0011] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer over an insulating surface and a second insulating film provided in contact with the oxide semiconductor layer. a first conductive material and an insulator provided in contact with the first conductive material; An opening is provided in the first conductive material and the insulator, and the oxide semiconductor layer and the first The side surfaces of the conductive material and the insulator are connected, and the oxide semiconductor layer and the first conductive material are connected to the second conductive material. and the second conductive object is in contact with the insulating surface. The opening has a truncated cone shape with a diameter that decreases toward the bottom.

[0012] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It should be noted that the numbers are added for the purpose of illustration only and are not intended to be limiting.

[0013] The insulator preferably contains aluminum oxide.

[0014] Another embodiment of the present invention is a semiconductor device including a first oxide semiconductor layer, a second oxide semiconductor layer, and a second oxide semiconductor layer over an insulating surface. a source electrode layer and a drain electrode layer in contact with a part of the stacked layer; The insulating surface and the stack are formed in contact with each other, and the source electrode layer and the drain electrode layer are formed in contact with each other. a third oxide semiconductor layer that is in contact with a portion of the gate insulating film formed on the third oxide semiconductor layer; a gate electrode layer formed on the gate insulating film; a source electrode layer; a drain electrode layer; and an insulating layer formed on the gate electrode layer. a first opening is provided in the stack, the drain electrode layer and the insulating layer; A third opening is provided in the gate electrode layer and the insulating layer, and the stack, the source, and the like are exposed through the first opening. The side surfaces of the source electrode layer and the insulating layer are continuous, and the second oxide semiconductor layer and the source electrode layer are The drain electrode layer and the insulating layer are electrically connected to the wiring of the first opening. The side surfaces of the second oxide semiconductor layer and the drain electrode layer are electrically connected to the second wiring. The gate electrode layer and the insulating layer are connected to each other at the third opening, and the gate electrode layer and the insulating layer are connected to each other at the third opening. The layer is electrically connected to a third wiring. The first opening, the second opening, and the third opening each have a diameter that decreases toward the bottom. The cone may have a truncated cone shape.

[0015] The top surface area of ​​the second oxide semiconductor layer is smaller than the top surface area of ​​the first oxide semiconductor layer. You may do so.

[0016] In addition, a region of the first oxide semiconductor layer that does not overlap with the second oxide semiconductor layer, a region of the source electrode layer, The region that does not overlap with the drain electrode layer and the region that does not overlap with the third oxide semiconductor layer are in contact with the third oxide semiconductor layer. It is preferable to have a structure in which

[0017] In addition, the first oxide semiconductor layer and the third oxide semiconductor layer are thicker than the second oxide semiconductor layer. It is also found that the energy of the conduction band minimum is close to the vacuum level in the range of 0.05 eV to 2 eV. preferable.

[0018] The first to third oxide semiconductor layers are In-M-Zn oxide layers (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf), and the first oxide semiconductor The conductor layer and the third oxide semiconductor layer have an atomic ratio of M to In that is equal to that of the second oxide semiconductor It is preferably larger than the layer.

[0019] The first to third oxide semiconductor layers each have crystals aligned along the c-axis. It is preferable.

[0020] The insulating layer preferably contains aluminum oxide. Effect of the Invention

[0021] By using one embodiment of the present invention, even if the device is miniaturized, it can be manufactured through a simple process. Alternatively, it is possible to provide a semiconductor device having a structure that can prevent a decrease in yield due to miniaturization. It is possible to provide a semiconductor device having a structure capable of suppressing the above-mentioned problems. It is possible to provide a semiconductor device having a configuration capable of suppressing the deterioration of electrical characteristics that occurs due to the Alternatively, a semiconductor device with high integration can be provided. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a highly reliable semiconductor device can be provided. It is possible to provide a semiconductor device that retains data even when the power source is cut off.

[0022] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. Effects other than these may also be included. The above is self-evident from the description, drawings, claims, etc. Other effects can be extracted from the claims and other descriptions. [Brief description of the drawings]

[0023] [Figure 1] 1A and 1B are a top view and a cross-sectional view of a transistor. [Diagram 2] FIG. 1 is a cross-sectional view of a transistor. [Diagram 3] FIG. 1 is a cross-sectional view of a transistor. [Figure 4] 1A and 1B are a top view and a cross-sectional view of a transistor. [Diagram 5] 1A to 1C are diagrams illustrating band structures of oxide semiconductor layers. [Figure 6] FIG. [Figure 7] FIG. 1 is a cross-sectional view of a transistor. [Figure 8] FIG. 1 is a cross-sectional view of a transistor. [Figure 9] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 10] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 11] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 12] 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device. [Figure 13] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 14] 1A to 1C are diagrams illustrating electronic devices to which a semiconductor device can be applied. [Figure 15] FIG. 1 is a cross-sectional view of a transistor. [Figure 16] 1A and 1B are a top view and a cross-sectional view of a transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The following explanations may be omitted.

[0025] In this specification, when it is explicitly stated that X and Y are connected, When X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are This includes the case where X and Y are directly connected. Here, X and Y are objects (e.g. For example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc. In this case, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence, but may be applied to any other connection relationship shown in a drawing or a sentence. This also includes connections other than those shown in the text.

[0026] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. It has the function of switching between these modes.

[0027] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if

[0028] In addition, when it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. (That is, there is another element or circuit between X and Y.) X and Y are functionally connected (i.e., there is another circuit between X and Y) When X and Y are functionally connected through a wire, and when X and Y are directly connected (i.e. , when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it should simply be "" is the same as if it were expressly stated that the

[0029] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The electrode functions as both components. The term "electrochemically connected" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0030] In this specification and the like, transistors can be formed using various substrates. The type of substrate is not limited to a specific one. An example of the substrate is a semiconductor substrate. Substrates (e.g. single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Includes plastic substrates, metal substrates, stainless steel substrates, and stainless steel foil. Substrates for bonding, tungsten substrates, substrates with tungsten foil, flexible substrates, bonding Examples include laminated films, paper containing fibrous materials, and base films. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. An example of a flexible substrate is polyethylene terephthalate (PET). ), polyethylene naphthalate (PEN), and polyethersulfone (PES). The materials used are plastics that can be used for bonding, and synthetic resins that have flexibility, such as acrylic. Examples of films include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Examples of base films include polyester, polyamide, polyvinyl chloride, etc. In particular, semiconductor substrates, single crystal substrates, Alternatively, by manufacturing transistors using SOI substrates, etc., the characteristics, size, We manufacture small-sized transistors with little variation in shape and current capacity. When a circuit is constructed using such transistors, the circuit can consume low power. This allows for increased power and higher circuit integration.

[0031] Note that a transistor is formed using a certain substrate and then transferred to another substrate. However, the transistor may be disposed on another substrate. In addition to the substrate on which the above-mentioned transistors can be formed, the substrates include paper substrates, cellophane substrates, and the like. substrates made of natural fibers (silk, cotton, hemp), synthetic fibers (nylon, Polyurethane, polyester) or regenerated fiber (acetate, cupra, rayon, regenerated These substrates include raw polyester, leather substrates, and rubber substrates. By using this, it is possible to form transistors with good characteristics and transistors with low power consumption. It is possible to manufacture devices that are less likely to break, have heat resistance, and are lighter or thinner.

[0032] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

[0033] 1A and 1B are a top view and a cross-sectional view of a transistor of one embodiment of the present invention. 1(A) is a top view, and the cross section taken along the dashed line A1-A2 shown in FIG. 1(A) corresponds to FIG. 1(B). FIG. 2 is a cross-sectional view taken along the dashed line A3-A4 in FIG. 1(A). In the top view of FIG. 1(A), some elements are omitted for clarity. The direction of the dashed dotted line A1-A2 is called the channel length direction, and the direction of the dashed dotted line A3-A4 is called the channel width direction. It may be referred to as.

[0034] The transistor 100 shown in FIGS. 1A, 1B, and 2 is formed on a substrate 110. A base insulating film 120, a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 formed on the base insulating film 2 and the oxide semiconductor layer 132 in that order, and The source electrode layer 140 and the drain electrode layer 150 are formed by the above-mentioned insulating film 120 and the The source electrode layer 140 and the drain electrode layer 150 are formed on the stack. A third oxide semiconductor layer 133 in contact with the gate electrode 131 and a gate insulating film 132 formed on the third oxide semiconductor layer An insulating film 160, a gate electrode layer 170 formed on the gate insulating film, and a source electrode layer 140, a drain electrode layer 150, and an insulating layer 180 formed on the gate electrode layer 170. has.

[0035] In addition, an insulating layer 185 made of an oxide may be formed on the insulating layer 180. The insulating layer 185 may be provided as necessary, and another insulating layer may be formed on top of it. In addition, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer The oxide semiconductor layers 133 are collectively referred to as oxide semiconductor layers 130.

[0036] A first opening 147 is provided in the stack, the source electrode layer 140 and the insulating layer 180. In the opening 147 of the first embodiment, the side surfaces of the stack, the source electrode layer 140 and the insulating layer 180 are continuous. In addition, a second opening 157 is formed in the stack, the drain electrode layer 150, and the insulating layer 180. In the second opening 157, the stack, the drain electrode layer 150 and the insulating layer are The side surface of the layer 180 is continuous. Also, a third opening is formed in the gate electrode layer 170 and the insulating layer 180. 177 is provided, and the gate electrode layer 170 and the insulating layer 18 are exposed in the third opening 177. The first opening 147, the second opening 157, and the third opening 177 are connected to each other. Each may have a truncated cone shape with a diameter that decreases towards the base.

[0037] In the first opening 147, the second oxide semiconductor layer 132 and the source electrode layer 140 is electrically connected to the first wiring 145 by a side contact. In the opening 157, the second oxide semiconductor layer 132 and the drain electrode layer 150 are The third opening 1 is electrically connected to the wiring 155 of the second opening 1 by a side contact. At 77, the gate electrode layer 170 is electrically connected to the third wiring 175 by a side contact. are connected to the network.

[0038] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. It is possible to use it.

[0039] As described above, the electrode layers such as the source electrode layer 140 and the wiring such as the first wiring 145 are sized Conventionally, an opening penetrating the electrode layer is Instead, an opening is provided in an insulating layer or the like formed on the electrode layer, and the opening Electrical connection is achieved by contacting a part of the wiring formed on the substrate with a part of the electrode layer.

[0040] However, as transistors become more miniaturized, the manufacturing process becomes more difficult, and the insulating layer The openings provided in the above-mentioned areas had poor opening quality and uneven depth. Therefore, the contact resistance between the electrode layer and the wiring is likely to vary between elements. In other words, the increasing difficulty of the manufacturing process due to the miniaturization of transistors is was a factor in gender inequality.

[0041] On the other hand, in one embodiment of the present invention, an opening penetrating the electrode layer is provided, and the electrode layer in the opening is In order to obtain an electrical connection by contacting the side wall of the electrode layer with a part of the wiring formed in the opening, This makes it possible to reduce the variation in the contact area between the electrodes and the wires. Since the variation in contact resistance between the layer and the wiring can be suppressed, the It is also possible to suppress variations in the electrical characteristics of the transistors.

[0042] In addition, when openings are provided in an insulating layer formed on the electrode layer, the etching conditions are strictly controlled. Rather than forming an opening so as not to penetrate the electrode layer in a controlled manner, the opening is formed so as to penetrate the electrode layer. For example, in the etching process, the electrode layer Even if the etching rate of the electrode is sufficiently smaller than that of the insulating layer, In the case where excessive etching of the electrode layer is permitted to form an opening, the degree of freedom of the etching conditions is increased. Therefore, the yield of the transistors can be improved. .

[0043] In one embodiment of the present invention, as shown in FIG. 1B, not only the electrode layer but also the second oxide semiconductor forming an opening through the conductor layer 132 and the first oxide semiconductor layer 131; As will be described later in detail, the second oxide semiconductor layer 132 and the first oxide semiconductor A part of the wiring layer is formed in the opening penetrating the layer 131, and the wiring layer is an electrode layer. and function as a source or a drain in the second oxide semiconductor layer 132. This allows the n-type region to be expanded.

[0044] Also, in the connection between the gate electrode layer 170 and the third wiring 175, the sub-layer as shown in FIG. By using double contact, it is possible to reduce the variation in the contact area between the electrode layer and the wiring. This makes it possible to suppress variations in contact resistance.

[0045] The configurations of the first opening 147 and the second opening 157 are not limited to the example shown in FIG. For example, as shown in FIG. 3A, a structure in which the second oxide semiconductor layer 132 is not penetrated As shown in FIG. 3B, a metal oxide semiconductor layer may be formed through the second oxide semiconductor layer 132. Alternatively, the first opening may not penetrate the first oxide semiconductor layer 131. The bottom of the second opening 157 is in the first oxide semiconductor layer 131 or the second oxide semiconductor layer 147. The structure may be such that the semiconductor layer 132 is located anywhere in the semiconductor layer 132. In this manner, the bottoms of the first opening 147 and the second opening 157 reach the underlying insulating film 120. The bottom of the third opening 177 is not limited to the example shown in FIG. Any of the insulating film 160, the third oxide semiconductor layer 133, and the base insulating film 120 The configuration may be such that the sensor is located at

[0046] A transistor according to one embodiment of the present invention has a structure shown in FIGS. 4(A) is a top view, and the cross section taken along the dashed line B1-B2 shown in FIG. 4(B). The cross section taken along the dashed line B3-B4 in FIG. 4(A) corresponds to FIG. 4(C). Equivalent.

[0047] The transistor 101 shown in FIGS. 4A, 4B, and 4C is a transistor having a lower layer formed on a substrate 110. A base insulating film 120, a first oxide semiconductor layer 131 formed on the base insulating film, the area of ​​a top surface of the first oxide semiconductor layer formed on the second oxide semiconductor layer is smaller than that of the first oxide semiconductor layer 131; A second oxide semiconductor layer 132 entirely overlapping the first oxide semiconductor layer 131, A source electrode in contact with a part of each of the semiconductor layer 131 and the second oxide semiconductor layer 132. layer 140 and the drain electrode layer 150, the first oxide semiconductor layer 131 and the second oxide A source electrode layer 140 and a drain electrode layer 150 are formed on the semiconductor layer 132. a third oxide semiconductor layer 133 in contact with the gate insulating film 131 and a gate insulating film 132 formed on the third oxide semiconductor layer 133; The gate insulating film 160 has a gate electrode layer 170 formed on the gate insulating film.

[0048] In addition, a region of the first oxide semiconductor layer 131 in contact with the source electrode layer 140 and a region of the drain The thickness of the region in contact with the electrode layer 150 is set to be equal to or larger than the thickness of the second oxide semiconductor layer 131. The thickness is thinner than the thickness of the region overlapping with the layer 132 .

[0049] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 16(A) is a top view, and the cross section taken along the dashed line A1-A2 shown in FIG. 6(B). In the transistor shown in FIG. 1, a gate electrode layer 170, a gate insulating film The top shapes of the third oxide semiconductor layer 160 and the third oxide semiconductor layer 133 are substantially the same. In the illustrated transistor, a gate electrode layer 170, a gate insulating film 160 and a third oxide The top surface shape of the gate electrode layer 170 is different from that of the semiconductor layer 133. The upper surface area of ​​the third oxide semiconductor layer 133 is smaller than that of the upper surface area of ​​the insulating film 160 and the upper surface area of ​​the third oxide semiconductor layer 133. By using this configuration, the gate leakage current can be reduced.

[0050] The transistor 101 has a top surface shape similar to that of the transistor 100 and the first oxide semiconductor layer 131. In the transistor 101, the shape of the gate electrode layer 170 is different. Since the first oxide semiconductor layer 131 remains on the entire surface of the substrate until the formation of the transistor, which requires high temperatures, In the manufacturing process of the capacitor 101, unnecessary release of oxygen from the insulating base film 120 can be suppressed. Therefore, the second oxide semiconductor layer in which the channel is formed can be formed from the base insulating film 120. This effectively supplies oxygen to the 132, improving the electrical characteristics of the transistor. can.

[0051] In addition, in the transistor of one embodiment of the present invention, the oxide semiconductor layer (the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132) overlapping the source electrode layer 140 or the drain electrode layer In the top view of FIG. 16A and FIG. 16B, The distance (ΔW) from the end of the source electrode layer 140 or the drain electrode layer 150 is set to 50 nm. The thickness is preferably 25 nm or less. Metallic material that is a constituent material of the source electrode layer 140 and the drain electrode layer 150 of oxygen contained therein Therefore, the amount of oxygen contained in the base insulating film 120, particularly It is possible to suppress unnecessary release of excess oxygen, and the oxide semiconductor layer is Oxygen can be efficiently supplied from the base insulating film 120 .

[0052] Next, components of the transistor 100 of one embodiment of the present invention will be described in detail. The components are also applicable to transistor 101.

[0053] The substrate 110 is not limited to being a simple support material, but may also be a substrate on which other devices such as transistors are formed. In this case, the gate electrode layer 170 of the transistor 100, the source electrode At least one of the layers 140 and the drain electrode layer 150 is electrically connected to the other devices described above. The input / output terminals may be electrically connected to each other.

[0054] The base insulating film 120 has a role of preventing the diffusion of impurities from the substrate 110 and also prevents oxidation. Therefore, the base insulating film 1 can serve to supply oxygen to the organic semiconductor layer 130. 20 is preferably an insulating film containing oxygen, and the insulating film contains more oxygen than the stoichiometric composition. As described above, the substrate 110 is preferably a thin film. In the case of a substrate having such a structure, the base insulating film 120 also functions as an interlayer insulating film. CMP (Chemical Mechanical Polishing) is used to make the surface flat. It is preferable to perform a planarization process by a method such as a shingle method.

[0055] In addition, in a region where a channel of the transistor 100 is formed, the oxide semiconductor layer 130 From the substrate 110 side, a first oxide semiconductor layer 131, a second oxide semiconductor layer 132, a third oxide semiconductor layer 133, and a The first oxide semiconductor layer 13 is a first oxide semiconductor layer 133. 1, a region that does not overlap with the second oxide semiconductor layer 132 and a region that does not overlap with the source electrode layer 140 The region that does not overlap with the drain electrode layer 150 and the region that does not overlap with the drain electrode layer 150 are connected to the third oxide semiconductor layer 133. Therefore, the second oxide semiconductor layer 132 is a semiconductor layer including the first oxide semiconductor layer 131 and the third oxide semiconductor layer. The oxide semiconductor layer 133 surrounds the insulating film 131 .

[0056] Here, for example, the second oxide semiconductor layer 132 is a first oxide semiconductor layer 131. and has a higher electron affinity (energy density from the vacuum level to the bottom of the conduction band) than the third oxide semiconductor layer 133. The electron affinity is the distance between the vacuum level and the top of the valence band. From the energy difference (ionization potential), the energy between the bottom of the conduction band and the top of the valence band It can be calculated by subtracting the difference (energy gap).

[0057] In this embodiment, the oxide semiconductor layer 130 is a stack of three layers. However, the oxide semiconductor layer 130 may be one layer, two layers, or four or more layers. In the case where the oxide semiconductor layer 130 is a single layer as shown in FIG. 15B. In the case of a two-layer structure, for example, the third oxide semiconductor layer 133 may not be provided. In the case of the above-mentioned structure, the second oxide semiconductor layer 132 and the first oxide semiconductor layer 131 are interchanged. In addition, as shown in FIG. 15C, the oxide semiconductor layer 130 may have three layers. However, the structure may be different from that shown in FIG. 1. In addition, when the number of layers is four or more, for example, In addition, a structure in which another oxide semiconductor layer is stacked on the three-layer stack described in this embodiment or Another oxide semiconductor layer may be inserted at any interface of the three-layer structure. do.

[0058] The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are The layer 132 includes one or more metal elements, and the energy of the conduction band minimum is, for example, The oxide semiconductor layer 132 has a refractive index of 0.05 eV, 0.07 eV, 0.1 eV, and 0.15 eV. and in the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV or less. It is preferable that the insulating film be formed using an oxide semiconductor having a temperature close to a vacuum level in the vicinity of the insulating film.

[0059] In such a structure, when an electric field is applied to the gate electrode layer 170, the oxide semiconductor layer 13 0, the second oxide semiconductor layer 132 has the smallest energy at the bottom of the conduction band. That is, a first oxide semiconductor layer 132 is formed between the second oxide semiconductor layer 132 and the gate insulating film 160. The third oxide semiconductor layer 133 is formed, so that the channel of the transistor is The structure is such that it does not come into contact with the insulating film.

[0060] The first oxide semiconductor layer 131 contains the metal element constituting the second oxide semiconductor layer 132. Since the second oxide semiconductor layer 132 and the base insulating film 120 are bonded to each other, The interface between the second oxide semiconductor layer 132 and the first oxide semiconductor layer 131 is different from that in the case of the first oxide semiconductor layer 131. The interface state is unlikely to be formed at the interface. The interface state may form a channel. Therefore, the threshold voltage of the transistor may vary. By providing the layer 131, the variation in electrical characteristics such as the threshold voltage of the transistor can be reduced. In addition, the reliability of the transistor can be improved.

[0061] The third oxide semiconductor layer 133 contains the metal element constituting the second oxide semiconductor layer 132. Since the second oxide semiconductor layer 132 and the gate insulating film 160 are formed by containing one or more of The interface between the second oxide semiconductor layer 132 and the third oxide semiconductor layer 13 Therefore, the third oxide semiconductor layer 3 is less likely to cause carrier scattering at the interface with the third oxide semiconductor layer 3. By providing the region 133, the field effect mobility of the transistor can be increased.

[0062] The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 may contain, for example, Al, T The second oxide semiconductor layer 132 is made of one of i, Ga, Ge, Y, Zr, Sn, La, Ce, and Hf. A material having an atomic ratio higher than 1. The amount is 5 times or more, preferably 2 times or more, and more preferably 3 times or more. The above elements are oxygen and Since the bond is strong, the oxide semiconductor layer has a function of suppressing oxygen vacancies from being generated. That is, the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are It can be said that oxygen deficiency is less likely to occur in this layer than in the organic semiconductor layer 132.

[0063] Note that the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor The layer 133 is made of at least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr In the case of an In-M-Zn oxide layer containing a metal such as In, Sn, La, Ce or Hf, The oxide semiconductor layer 131 of FIG. 1 is formed of In:M:Zn=x 1 :y 1 :z 1 [Atomic ratio], second acid The compound semiconductor layer 132 is In:M:Zn=x 2 :y2 :z 2 [Atomic ratio], third oxide semi The conductor layer 133 is In:M:Zn=x 3 :y 3 :z 3 [Atomic ratio], y 1 / x 1 oh Call y 3 / x 3 y 2 / x 2 It is preferable that y is larger than y. 1 / x 1 and y 3 / x 3 Yes 2 / x 2 More than 1.5 times, preferably more than 2 times, more preferably more than 3 times In this case, in the second oxide semiconductor layer 132, y 2 x 2 More than that, it's a tra The electrical characteristics of the transistor can be stabilized. 2 x 2 When it becomes more than three times , the field effect mobility of the transistor is reduced, so y 2 x 2 Less than three times the is preferred.

[0064] Note that in this specification, the atomic ratio used to describe the composition of an oxide semiconductor layer is based on the atomic ratio of the base material. The film is formed by sputtering using an oxide semiconductor material as a target. In this case, the deposition efficiency depends on the sputtering gas species and their ratio, the target density, and the deposition conditions. The composition of the oxide semiconductor film may differ from that of the base material target. Therefore, in this specification, the atomic ratio describing the composition of the oxide semiconductor layer is based on the atomic ratio of the base material. For example, when the sputtering method is used for film formation, the atomic ratio is 1:1. The In-Ga-Zn oxide film with an atomic ratio of 1:1:1 is an In-Ga-Zn oxide film with an atomic ratio of 1:1:1. This can be rephrased as an In-Ga-Zn oxide film formed using the material as a target. .

[0065] Zn and O in the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 When In and M are excluded, the atomic ratio of In is preferably less than 50 atomic %. M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is 7 The content of Zn and O in the second oxide semiconductor layer 132 is set to 5 atomic % or more. The atomic ratio of In and M, excluding the above, is preferably 25 atomic % or more of In. , M is less than 75 atomic %, more preferably In is 34 atomic % or more, and M is Less than 66 atomic%.

[0066] The thickness of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 is 1 nm or more. The thickness of the second oxide semiconductor layer is preferably 3 nm to 50 nm. The thickness of 132 is 1 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably More preferably, it is 10 nm or more and 50 nm or less.

[0067] A first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor The layer 133 is made of, for example, an oxide semiconductor containing indium, zinc, and gallium. In particular, when the second oxide semiconductor layer 132 contains indium, the carrier This is preferred because it increases the mobility.

[0068] In order to provide stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, The present invention relates to a method for manufacturing an oxide semiconductor layer, comprising: reducing an impurity concentration in the oxide semiconductor layer to make the oxide semiconductor layer intrinsic or substantially intrinsic; Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is But 1×10 17 / cm 3 Preferably less than 1 × 10 15 / cm 3 is less than More preferably, 1×10 13 / cm 3 It means that it is less than.

[0069] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels can become traps and degrade the electrical characteristics of a transistor. Therefore, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132 and the third oxide semiconductor layer The impurity concentration in the oxide semiconductor layer 133 and at the interface between the oxide semiconductor layer 133 and the oxide semiconductor layer 133 can be reduced. preferable.

[0070] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, a secondary ion beam (SIMS) In the case of oxide semiconductors, for example, The silicon concentration at a certain depth in the semiconductor layer or in a certain region of the oxide semiconductor layer is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1×10 18 atoms / cm 3 The fact that it has a portion that is less than In addition, the hydrogen concentration is preferably adjusted at a certain depth in the oxide semiconductor layer or at a certain concentration in the oxide semiconductor layer. In a certain region of the nitride semiconductor layer, 20 atoms / cm 3 Less than or equal to 5, preferably ×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below Lower, and more preferably 5×10 18 atoms / cm 3 The following parts are included: In addition, the nitrogen concentration is preferably, for example, at a certain depth in the oxide semiconductor layer or In a region of the oxide semiconductor layer, 19 atoms / cm 3 Less than, preferably 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 It has the following parts: is preferred.

[0071] In addition, when the oxide semiconductor layer contains crystals and contains silicon or carbon at a high concentration, the oxide In order to prevent the crystallinity of the oxide semiconductor layer from being reduced, For example, at a certain depth in the oxide semiconductor layer or in a certain region of the oxide semiconductor layer In this case, the silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than In addition, for example, at a certain depth of the oxide semiconductor layer, In a region of the oxide semiconductor layer, the carbon concentration is set to 1×10 19 atoms / cm 3 less than , preferably 5 x 10 18 atoms / cm 3 less than 1×10 18 at oms / cm 3 It is sufficient that the part is less than

[0072] In addition, a transistor using the purified oxide semiconductor layer as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is set to 0.1 V, 5 V or approximately 10V, the off-state current normalized by the transistor channel width It is possible to reduce the current density to several yA / μm to several zA / μm.

[0073] In addition, since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is It can be said that a structure that does not contact the gate insulating film like a gate insulating film is preferable. When a channel is formed at the interface between the insulating film and the oxide semiconductor layer, carrier scattering occurs at the interface. This can cause a decrease in the field effect mobility of the transistor. It is preferable that the region of the oxide semiconductor layer that serves as a channel is separated from the gate insulating film. .

[0074] Therefore, the oxide semiconductor layer 130 is divided into a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132. The stacked structure of the second oxide semiconductor layer 132 and the third oxide semiconductor layer 133 is 132, which has high field-effect mobility and stable electrical properties. A transistor having such a structure can be formed.

[0075] Next, the band structure of the oxide semiconductor layer 130 will be described. The energy gallium nitride semiconductor layer 131 and the third oxide semiconductor layer 133 are layers corresponding to the energy gallium nitride semiconductor layer 131 and the third oxide semiconductor layer 133. The In-Ga-Zn oxide having a peak at 3.5 eV corresponds to the second oxide semiconductor layer 132. The In-Ga-Zn oxide layer has an energy gap of 3.15 eV. The deposition is performed by forming a laminate corresponding to the nitride semiconductor layer 130 .

[0076] A first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor layer 13 The film thickness of each of the layers was set to 10 nm, and the energy gap was measured using a spectroscopic ellipsometer (HOR The measurements were performed using a IBA JOBIN YVON UT-300. The energy difference at the top of the valence band is measured by ultraviolet photoelectron spectroscopy (UPS). Photoelectron Spectroscopy (PHI Ver. Measurements were performed using saProbe.

[0077] FIG. 5(A) shows the energy difference between the vacuum level and the top of the valence band, and the energy gap of each layer. Schematic from the energy difference between the vacuum level and the conduction band minimum (electron affinity) calculated as the difference FIG. 5A shows a part of the band structure of the first oxide semiconductor layer 131 and 13 is a band diagram in the case where a silicon oxide film is provided in contact with the third oxide semiconductor layer 133. FIG. Here, Evac is the energy of the vacuum level, EcI1 and EcI2 are the energy The energy of the conduction band minimum, EcS1, is the energy of the conduction band minimum of the first oxide semiconductor layer 131. EcS2 is the energy of the bottom of the conduction band of the second oxide semiconductor layer 132, and EcS3 is the 3 is the energy of the conduction band minimum of the oxide semiconductor layer 133.

[0078] As shown in FIG. 5A, a first oxide semiconductor layer 131, a second oxide semiconductor layer 132, In the third oxide semiconductor layer 133, the energy of the conduction band minimum changes continuously. The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 are This can also be understood from the fact that the similar composition of the layers 133 facilitates mutual diffusion of oxygen. Therefore, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, the third oxide semiconductor layer Although the semiconductor layer 133 is a laminate of layers with different compositions, it is physically continuous. In the drawings, the interfaces of the laminates are indicated by dotted lines.

[0079] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, a U-shaped junction in which the energy of the conduction band edge changes continuously between layers) The layers are fabricated so that a well structure (U Shape Well) is formed. There are no impurities at the interface that would form defect levels such as trap centers or recombination centers. If impurities are mixed between the stacked oxide semiconductor layers, When the interface is in a non-uniform state, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface. It will disappear when combined.

[0080] In FIG. 5(A), the case where EcS1 and EcS3 are the same is shown. For example, if EcS1 has a higher energy than EcS3, In this case, a part of the band structure is shown in FIG. 5(B).

[0081] For example, when EcS1=EcS3, the first oxide semiconductor layer 131 and the third oxide semiconductor layer The compound semiconductor layer 133 has a composition of In:Ga:Zn=1:3:2, 1:3:3, 1:3:4, 1:3 the second oxide semiconductor layer 132 having an atomic ratio of In: In-Ga-Z with Ga:Zn=1:1:1, 5:5:6, or 3:1:2 (atomic ratio) In addition, when EcS1>EcS3, the first oxide can be used. The compound semiconductor layer 131 has an atomic ratio of In:Ga:Zn=1:6:4 or 1:9:6. The oxide semiconductor layer 132 of No. 2 has a composition of In:Ga:Zn=1:1:1, 5:5:6, or 3:1 :2 (atomic ratio), and the third oxide semiconductor layer 133 had In:Ga:Zn=1:3:2, 1: Using In-Ga-Zn oxide with an atomic ratio of 3:3, 1:3:4 or 1:3:6 It is possible.

[0082] 5A and 5B, the second oxide semiconductor layer 132 in the oxide semiconductor layer 130 This serves as a well, and in a transistor using the oxide semiconductor layer 130, It can be seen that the oxide semiconductor layer 130 is formed in the second oxide semiconductor layer 132. Since the energy of the conduction band edge changes continuously, it can also be called a U-shaped well. A channel formed in this manner can also be called a buried channel. .

[0083] Note that the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are made of silicon oxide. Trap levels due to impurities and defects can be formed near the interface with an insulating film such as a silicon film. The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are provided. 2 and the trap level. When the energy difference between S1 or EcS3 and EcS2 is small, the second oxide semiconductor layer An electron of 132 can cross the energy difference and reach the trap level. When the charge is trapped in the gate level, a negative fixed charge is generated at the interface of the insulating film, causing the transistor to malfunction. The threshold voltage is shifted in the positive direction.

[0084] Therefore, to reduce the variation in the threshold voltage of the transistor, EcS1 and EcS It is necessary to provide an energy difference between EcS2 and EcS3. The energy difference is preferably 0.1 eV or more, and more preferably 0.15 eV or more.

[0085] Note that the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer It is preferable that the conductor layer 133 contains a crystalline portion. In particular, the conductor layer 133 uses crystals oriented along the c-axis. This makes it possible to give the transistor stable electrical characteristics.

[0086] When an In-Ga-Zn oxide is used for the oxide semiconductor layer 130, the gate insulation of In is In order to prevent diffusion to the insulating film, the third oxide semiconductor layer 133 is It is preferable that the composition contains less In than the above.

[0087] The source electrode layer 140, the drain electrode layer 150, the first wiring 145, the second wiring 155, and It is preferable to use a conductive material that easily bonds with oxygen for the third wiring 175. For example, , Al, Cr, Cu, Ta, Ti, Mo, W, etc. can be used. In particular, titanium is easily bonded to oxygen, and the subsequent process temperature can be relatively high. It is more preferable to use W, which has a high melting point. The material also includes a material in which oxygen easily diffuses. The third wiring 175 may be a laminated layer such as Ti / Al / Ti.

[0088] When a conductive material that easily bonds with oxygen is brought into contact with an oxide semiconductor layer, the oxygen in the oxide semiconductor layer However, the oxygen diffuses into the conductive material, which is more likely to bond with oxygen. The transistor manufacturing process involves several heating steps. Due to the above phenomenon, the area of ​​the oxide semiconductor layer in contact with the source electrode layer or the drain electrode layer Oxygen vacancies occur in the film, and the small amount of hydrogen contained in the film combines with the oxygen vacancies. The region is made n-type. Therefore, the n-type region serves as the source or It can act as a drain.

[0089] The n-type region is shown in the enlarged cross-sectional view of the transistor in FIG. 1, in the vicinity of the source electrode layer 140). A boundary 135 indicated by a dotted line in the n-type semiconductor layer 132 is a boundary between an intrinsic semiconductor region and an n-type semiconductor region. In the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, The source electrode layer 140 and the area in contact with the first wiring 145 are n-type regions. Note that the boundary 135 is shown only diagrammatically and may not be clear in practice. In addition, in FIG. 6, a part of the boundary 135 extends laterally in the second oxide semiconductor layer 132. However, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are positioned as shown in FIG. The entire thickness direction of the region of the compound semiconductor layer 132 sandwiched between the source electrode layer 140 and the base insulating film 120 The body may also become n-type.

[0090] In one embodiment of the present invention, the first wiring 145 and the second wiring 155 are made of a first oxide semiconductor. The second oxide semiconductor layer 132 is embedded in the conductor layer 131. Therefore, the oxide semiconductor layer 131 and the oxide semiconductor layer 132 are formed in the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. The n-type region can be expanded. The n-type region can be the source (or By expanding the n-type region, the channel shape is a source electrode (or drain electrode), or a channel forming region and a first wiring 14 5 (or the second wiring 155) can be reduced, The electrical characteristics of the transistor can be improved.

[0091] In addition, when forming a transistor with an extremely short channel length, the occurrence of the oxygen vacancies causes The shaped region may extend in the channel length direction of the transistor. In this case, The electrical characteristics of transistors are difficult to control, such as threshold voltage shift and on / off control by gate voltage. Therefore, a transistor with a very short channel length is formed. In this case, a conductive material that easily bonds with oxygen is used for the source electrode layer and the drain electrode layer. However, this is not necessarily desirable.

[0092] In such a case, the source electrode layer 140 and the drain electrode layer 150 are made of the above-mentioned materials. It is also possible to use a conductive material that is less likely to bond with oxygen than the conductive material. For example, materials containing tantalum nitride, titanium nitride, gold, platinum, palladium or ruthenium. Note that when the conductive material is in contact with the second oxide semiconductor layer 132, In this case, the source electrode layer 140 and the drain electrode layer 150 are formed of the conductive material and the above-mentioned oxygen. Alternatively, a conductive material that is easily bonded to the conductive material may be laminated.

[0093] The gate insulating film 160 may be formed of aluminum oxide, magnesium oxide, silicon oxide, or nitride oxide. Silicon oxide, silicon nitride, silicon oxide, gallium oxide, germanium oxide, Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and The insulating film 160 may be made of a material containing at least one type of tantalum oxide. It may also be a laminate of the above materials.

[0094] The gate electrode layer 170 may include any of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, and Ru. A conductive film of Ag, Ta, W, or the like can be used. The gate electrode layer may be a laminate of the above materials. It's fine.

[0095] An insulating layer 180 is formed on the gate insulating film 160 and the gate electrode layer 170. It is preferable that the insulating layer is made of aluminum oxide. The aluminum membrane is a barrier that does not allow impurities such as hydrogen and moisture, as well as oxygen, to pass through the membrane. Therefore, the aluminum oxide film is used during and after the transistor manufacturing process. Later, the oxides of impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors, Prevents contamination of the semiconductor layer 130 with oxygen, which is the main component of the oxide semiconductor layer 130. Preventing emission from the oxide semiconductor layer and preventing unnecessary emission of oxygen from the base insulating film 120 In addition, the acid contained in the aluminum oxide film is suitable for use as a protective film having the above structure. Alternatively, the element can be diffused into the oxide semiconductor layer.

[0096] In addition, it is preferable that an insulating layer 185 is formed on the insulating layer 180. 85 includes magnesium oxide, silicon oxide, silicon oxynitride, silicon oxynitride, and nitrogen. silicon oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, An insulating film containing one or more of lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide Alternatively, the insulating layer 185 may be a laminate of the above materials.

[0097] Here, the insulating layer 185 preferably contains excess oxygen. The insulating layer containing excess oxygen is This refers to an insulating layer that can release oxygen by heat treatment or the like. Gas spectroscopy analysis showed that the amount of oxygen released was 1.0 x 10 19 atoms / cm 3 The oxygen released from the insulating layer passes through the gate insulating film 160. Since the ions can be diffused into the channel formation region of the oxide semiconductor layer 130 via the Even if oxygen vacancies occur in the channel formation region, oxygen can be compensated for. Therefore, stable electrical characteristics of the transistor can be obtained.

[0098] In order to increase the integration density of semiconductor devices, it is essential to miniaturize transistors. It is known that the electrical characteristics of transistors deteriorate as the channel width decreases. The on-current, which is a direct result of the shrinkage of the gate insulating film, is significantly reduced.

[0099] However, in the transistor according to one embodiment of the present invention, as described above, a channel is formed. A third oxide semiconductor layer 132 is disposed between the second oxide semiconductor layer 132 and the gate insulating film 160. Therefore, the interface between the channel formation layer and the gate insulating film This suppresses the scattering of carriers that occurs in the It is possible.

[0100] In the transistor of one embodiment of the present invention, the second oxide semiconductor layer in which a channel is formed Since the third oxide semiconductor layer 133 is formed so as to cover the second oxide semiconductor layer 132, The scattering of carriers can be suppressed on the side surfaces of the conductor layer 132 in the same manner as on the top surface.

[0101] Therefore, the transistor of one embodiment of the present invention has a channel width direction as shown in the cross-sectional view of FIG. The length (W T ) is applicable In a structure in which the thickness is reduced to the same level as the oxide semiconductor layer or less, The electrical properties are improved.

[0102] For example, in a transistor as shown in FIG. T If is small enough as above The electric field applied from the gate electrode layer 170 to the side surface of the second oxide semiconductor layer 132 is the second Since the second oxide semiconductor layer 132 is entirely covered with the second oxide semiconductor layer 132, the second oxide semiconductor layer 132 is also covered with the side surface and the upper surface. In other words, a channel equivalent to the channel formed in the transistor of one embodiment of the present invention is formed. The transistor can have a higher on-current than a conventional transistor.

[0103] When a channel region 137 as shown in FIG. 7 is formed in a transistor, the channel width is W T and the length of the side surface of the second oxide semiconductor layer 132 in the channel width direction (W S1 , W S2 ) (W T +W S1 +W S2 ) and the transistor is An on-current flows according to the channel width. T If is sufficiently small, the second oxide semiconductor Current flows across layer 132 .

[0104] In addition, W S1 =W S2 =W S When the on-state current of the transistor is increased, 0.3W S ≦W T ≦3W S (W T is 0.3W S More than 3W S (hereinafter) In addition, Or W T / W S = 0.5 to 1.5, and more preferably W T / W S =0.7 or more 1.3 or less. W T / W S If it is >3, the S value and off-state current may increase.

[0105] Therefore, the transistor of one embodiment of the present invention has a high performance when miniaturized. Even if the MOSFET is turned on, a sufficiently high on-current can be obtained.

[0106] In the transistor of one embodiment of the present invention, the second oxide semiconductor layer 132 is By forming the second oxide semiconductor layer on the conductor layer 131, it is possible to prevent the formation of an interface state. By making the layer 132 the middle layer of the three-layer structure, the influence of impurities from above and below can be eliminated. Therefore, the second oxide semiconductor layer 132 has a similar effect to the first oxide semiconductor layer. The above-described transistor is surrounded by the oxide semiconductor layer 131 and the third oxide semiconductor layer 133. In addition to improving the on-state current, it is possible to stabilize the threshold voltage and reduce the S value. Therefore, Icut (the current when the gate voltage VG is 0V) can be reduced, and power consumption In addition, the threshold voltage of the transistor is stabilized, The long-term reliability of the semiconductor device can be improved.

[0107] In addition, the transistor of one embodiment of the present invention includes an oxide semiconductor layer 130 and a substrate as shown in FIG. A conductive film 172 may be provided between the gate electrode 110 and the gate electrode 110. The conductive film is used as a second gate electrode. By using it, it is possible to further increase the on-current and control the threshold voltage. In order to increase the gate current, for example, the gate electrode layer 170 and the conductive film 172 are set to the same potential, and In order to control the threshold voltage, In this case, a constant potential different from that of the gate electrode layer 170 may be supplied to the conductive film 172 .

[0108] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0109] (Embodiment 2) In this embodiment, the method for manufacturing the transistor 100 illustrated in FIG. This will be described with reference to FIG. 9 to FIG.

[0110] The substrate 110 may be a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate can be used. Substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On In It is also possible to use a quartz crystal integrator substrate, on which semiconductor elements are mounted. The provided one may be used.

[0111] The base insulating film 120 is formed by plasma CVD (Chemical Vapor Deposition). Aluminum oxide, magnesium oxide, silicon oxide, etc. are deposited by the ion method or sputtering method. Silicon oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide oxides such as tantalum oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride The insulating film can be formed of a nitride insulating film such as SiO2 or a film made of a mixture of the above materials. Alternatively, the above-mentioned materials may be laminated, and at least the upper layer in contact with the oxide semiconductor layer 130 is an oxide. The oxide semiconductor layer 130 may be formed of a material containing excess oxygen, which may be a source of oxygen for the oxide semiconductor layer 130. preferable.

[0112] In addition, the insulating base film 120 is subjected to ion implantation, ion doping, plasma immersion ion implantation, etc. Oxygen may be added by using an on-implantation method or the like. This makes it easier to supply oxygen from the base insulating film 120 to the oxide semiconductor layer 130. It is possible.

[0113] Note that the surface of the substrate 110 is an insulator, and impurities are diffused into the oxide semiconductor layer 130 to be provided later. If there is no effect of diffusion, the base insulating film 120 may not be provided.

[0114] Next, a first oxide semiconductor film 3 which will become a first oxide semiconductor layer 131 is formed on the base insulating film 120. 31 and a second oxide semiconductor film 332 which will become the second oxide semiconductor layer 132 are formed by sputtering. CVD, MBE, ALD (Atomic Layer Deposition) The film is formed by using the SiO2 (Si) method or the PLD method (see FIG. 9(A)).

[0115] Next, the first oxide semiconductor film 331 and the second oxide semiconductor film 332 are selectively etched. The first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are formed by etching. (See FIG. 9(B)).

[0116] A continuous junction is formed in the stack of the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. In order to form the film, a multi-chamber deposition apparatus equipped with a load lock chamber (e.g. It is preferable to use a sputtering device to continuously laminate each layer without exposing them to the air. Each chamber in the sputtering device is designed to be free of water and other impurities that can affect oxide semiconductors. In order to remove as much as possible, high vacuum evacuation is performed using an adsorption type vacuum evacuation pump such as a cryopump. Ki (5 x 10 -7 Pa~1×10 -4 Pa) and the substrate on which the film is to be formed. It is preferable that the plate can be heated to 100°C or more, preferably 500°C or more. A combination of a polymer pump and a cold trap is used to extract carbon and water components from the exhaust system into the chamber. It is preferable to prevent gas containing moieties and the like from flowing backward.

[0117] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is also necessary to increase the purity of the sputtering gas. , the dew point is -40°C or less, preferably -80°C or less, more preferably -100°C or less By using a highly purified gas, moisture or the like is prevented from being taken into the oxide semiconductor layer as much as possible. This can be prevented.

[0118] The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and a thin film formed in a later step The third oxide semiconductor layer 133 can be formed using the material described in Embodiment 1. For example, the first oxide semiconductor layer 131 may have a composition of In:Ga:Zn=1:3:6, 1:3:4, In-Ga-Zn oxide with an atomic ratio of 1:3:3 or 1:3:2, the second oxide semiconductor The layer 132 is made of In-Ga with an atomic ratio of In:Ga:Zn=1:1:1 or 5:5:6. a-Zn oxide, and the third oxide semiconductor layer 133 has In:Ga:Zn=1:3:6, 1:3 Use In-Ga-Zn oxide with an atomic ratio of 1:4, 1:3:3 or 1:3:2. can be done.

[0119] In addition, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer The oxide semiconductor that can be used as the semiconductor layer 133 contains at least indium (In It is preferable that the alloy contains In (In) or zinc (Zn). Alternatively, the alloy may contain both In and Zn. In addition, in order to reduce variation in electrical characteristics of a transistor using the oxide semiconductor, Therefore, it is preferable to include a stabilizer therewith.

[0120] The stabilizers are gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, with other stabilizers The lanthanides lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0121] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. , Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In- Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, I n-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al -Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, I n-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy -Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide It is possible.

[0122] In addition, for example, In-Ga-Zn oxide is a material with In, Ga, and Zn as the main components. It means that the oxide contains metal elements other than In, Ga, and Zn. In this specification, a film made of In-Ga-Zn oxide is referred to as an IGZO film. Also called.

[0123] In addition, InMO 3 (ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It denotes a metallic element or elements. Also, In 2 SnO 5 (ZnO) n (n>0, and and n is an integer) may be used.

[0124] However, as described in detail in the first embodiment, the second oxide semiconductor layer 132 is The second oxide semiconductor layer 132 has a larger electron affinity than the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133. It is formed like this.

[0125] Note that the oxide semiconductor layer is preferably formed by a sputtering method. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc. can be used.

[0126] A first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor layer 13 When In-Ga-Zn oxide is used as 3, the atomic ratio of In, Ga, and Zn is as follows: For example, In:Ga:Zn=1:1:1, In:Ga:Zn=2:2:1, In:Ga: Zn=3:1:2, In:Ga:Zn=5:5:6, In:Ga:Zn=1:3:2, I n:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, In:Ga:Zn=1: 3:6, In:Ga:Zn=1:4:3, In:Ga:Zn=1:5:4, In:Ga: Zn=1:6:6, In:Ga:Zn=1:6:4, In:Ga:Zn=1:9:6, I Use either n:Ga:Zn=1:1:4 or In:Ga:Zn=1:1:2 It is possible.

[0127] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with the atomic ratio of In:Ga:Zn=A:B:C (A+B+C = 1), a, b, and c are in the vicinity of the oxide composition (aA) 2 +(bB) 2 + (cC) 2 ≦r 2 It means that the following condition is satisfied. For example, r can be set to 0.05. The same is true for other oxides.

[0128] The second oxide semiconductor layer 132 is a semiconductor layer including the first oxide semiconductor layer 131 and the third oxide semiconductor layer. The indium content is preferably higher than that of the semiconductor layer 133. The s orbitals of heavy metals contribute to carrier conduction, and by increasing the In content, Since more s orbitals overlap, oxides with a composition in which In is more abundant than Ga have the same composition as In and Ga. The mobility is higher compared to oxides with equal or lesser composition. Therefore, the second oxide By using an oxide with a high indium content for the semiconductor layer 132, a transistor with high mobility can be obtained. It is possible to realize the above-mentioned.

[0129] The structure of the oxide semiconductor film will be described below.

[0130] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0131] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0132] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor). Talline Oxide Semiconductor film, polycrystalline oxide semiconductor film The oxide semiconductor film includes a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0133] First, we will explain the CAAC-OS film.

[0134] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is so large that it fits inside a cube with one side less than 100 nm. Therefore, CAAC The crystal parts contained in the -OS film are cubic with one side less than 10 nm, 5 nm, or 3 nm. This includes cases where the size is small enough to fit inside the body.

[0135] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a ferromagnetic microscope, clear boundaries between the crystals, i.e., crystal boundaries, were observed. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0136] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation ) It can be confirmed that the metal atoms are arranged in layers in the crystal part. Each layer has a surface on which the CAAC-OS film is formed (also called a surface on which the film is formed) or a top surface having irregularities. The shape of the CAAC-OS film reflects this, and the CAAC-OS film is aligned parallel to the surface on which the film is formed or the top surface.

[0137] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). When the metal atoms were observed, they were found to be arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal parts. stomach.

[0138] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It is clear that there are

[0139] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, InGaZnO 4 CAAC-OS film with crystals In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak may appear in InGaZnO 4 It is assigned to the (009) plane of the crystal of This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0140] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS film in a direction perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This peak is , InGaZnO 4 It is attributed to the (110) plane of the InGaZnO crystal. 4 Single crystal oxidation of In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, the 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0141] From the above, it is considered that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. The crystal is regular, but has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which the crystal is formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of metal atoms arranged in a plane is parallel to the ab plane of the crystal.

[0142] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. is oriented in a direction parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is changed to the shape of the CAAC-OS film. It may not be parallel to the normal vector of the top or bottom surface.

[0143] In addition, the degree of crystallinity in the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The adjacent regions may have a higher degree of crystallinity than the regions adjacent the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region to which the impurities are added changes, resulting in partial In some cases, regions of differing crystallinity may be formed.

[0144] In addition, InGaZnO 4 Out-of-plane synthesis of CAAC-OS films with crystallites In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0145] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities include hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is contained in the oxide semiconductor film, the The impurities in the oxide semiconductor film may cause the atomic arrangement to be disturbed, which may result in a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0146] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0147] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called normally-on.) In addition, high purity intrinsic or substantially high purity The highly intrinsic oxide semiconductor film has few carrier traps. The transistors using the thin film have small fluctuations in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time when the charge is released is long, and it may behave as if it is a fixed charge. A transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. This may be the case.

[0148] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0149] Next, a microcrystalline oxide semiconductor film will be described.

[0150] In the microcrystalline oxide semiconductor film, crystal parts can be clearly seen in the TEM image. The crystal parts contained in the microcrystalline oxide semiconductor film may have a size of 1 nm or more and 100 nm or less. In particular, the size of the particles is between 1 nm and 10 nm. Nanocrystals (nc) are microcrystals with a diameter of 1 nm or less and 3 nm or less. The oxide semiconductor film having Al was formed by The nc-OS film is called a TE semiconductor film. In the M image, the grain boundaries may not be clearly visible.

[0151] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) is used to measure the nc-OS film using X-rays with a diameter larger than that of the crystals. When structural analysis was performed using the D instrument, the crystal plane In addition, the peaks indicating the probe size were not detected in the nc-OS film. Electron beam diffraction (also called selected area electron beam diffraction) uses an electron beam with a diameter (for example, 50 nm or more). ) a halo-like diffraction pattern is observed. On the other hand, the probe diameter is close to or smaller than the size of the crystal part (for example, 1 nm to 30 nm). When electron beam diffraction (also called nanobeam electron beam diffraction) is performed using an electron beam of In addition, when nanobeam electron diffraction is performed on the nc-OS film, a circular pattern is observed. In addition, a bright area (ring-shaped) may be observed for the nc-OS film. When nanobeam electron diffraction is performed, multiple spots are observed within the ring-shaped region. There is.

[0152] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0153] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CA The AC-OS film may be a laminate film having two or more kinds of films.

[0154] The CAAC-OS film can be formed, for example, by using a polycrystalline oxide semiconductor sputtering target. The film can be formed by sputtering. Ions collide with the sputtering target. When the sputtering target is heated, the crystal region in the sputtering target cleaves from the ab plane and is parallel to the ab plane. The particles may peel off as flat or pellet-like sputtered particles with a smooth surface. In this case, the plate-shaped or pellet-shaped sputtered particles are charged and do not agglomerate in the plasma. Therefore, the crystal state can be maintained while the metal oxide reaches the substrate and a CAAC-OS film can be formed.

[0155] The second oxide semiconductor layer 132 is an In-M-Zn oxide (wherein M is Ga, Y, Zr, La, C When the second oxide semiconductor layer 132 is formed of Nd, the second oxide semiconductor layer 132 is formed of Nd. In the sputtering target, the atomic ratio of metal elements is In:M:Zn=a 1 :b 1 : c 1 So, 、a 1 / b 1 is 1 / 3 or more and 6 or less, or even 1 or more and 6 or less, and c 1 / b 1 is preferably 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. 1 / b 1 By setting the value of 1 to 6, the second oxide semiconductor layer 132 can be formed using a CAAC-OS A typical example of the atomic ratio of the target metal elements is In:M :Zn=1:1:1, In:M:Zn=3:1:2, In:M:Zn=5:5:6 etc. do.

[0156] The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are made of In-M-Zn oxide. (M is Ga, Y, Zr, La, Ce, or Nd), the first oxide semiconductor A sputtering tantalum used for depositing the conductive layer 131 and the third oxide semiconductor layer 133. The atomic ratio of metal elements in the get is In:M:Zn=a 2 :b 2 :c 2 So, 、 a 2 / b 2 1 / b 1 Where c 2 / b 2 is between 1 / 3 and 6, and between 1 and 6 It is preferable that the temperature is less than or equal to c 2 / b 2 By setting the value to 1 or more and 6 or less, the first oxide The semiconductor layer 131 and the third oxide semiconductor layer 133 are likely to be formed as CAAC-OS films. A typical example of the atomic ratio of the metal elements in the target is In:M:Zn=1:3. :2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1 :3:6 etc.​

[0157] After the second oxide semiconductor layer 132 is formed, first heat treatment may be performed. The treatment is carried out at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and is carried out at a temperature of 100°C to 500°C. The treatment may be carried out in an atmosphere of an oxidizing gas, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. The atmosphere of the first heat treatment is an inert gas atmosphere, and the oxygen released after the heat treatment is performed is removed. In order to compensate for this, the first heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas. Therefore, the crystallinity of the second oxide semiconductor layer 132 can be improved, and the base insulating film 120 and the first Impurities such as hydrogen and water can be removed from the oxide semiconductor layer 131. Before etching for forming the oxide semiconductor layer 132, a first heating step may be performed.

[0158] Next, a source electrode layer is formed on the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. A first conductive film is formed to become the drain electrode layer 140 and the drain electrode layer 150. The material is Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy material whose main component is these. For example, a titanium film of 100 nm is formed by sputtering or the like. The tungsten film may also be formed by a CVD method.

[0159] Next, the first conductive film is etched so as to be divided on the second oxide semiconductor layer 132. A source electrode layer 140 and a drain electrode layer 150 are formed (see FIG. 9(C)). By overetching the first conductive film, a part of the second oxide semiconductor layer 132 is etched. It may also have an etched shape.

[0160] Next, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the source electrode layer 140 On the drain electrode layer 150, a third oxide semiconductor layer to be the third oxide semiconductor layer 133 is formed. A membrane 333 is formed.

[0161] Note that a second heat treatment may be performed after the third oxide semiconductor film 333 is formed. The heat treatment can be carried out under the same conditions as the first heat treatment. Impurities such as hydrogen and water can be removed from the third oxide semiconductor film 333. Hydrogen, water, and the like are further released from the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. Impurities can be removed.

[0162] Next, an insulating film 360 which is to become the gate insulating film 160 is formed on the third oxide semiconductor film 333. The insulating film 360 may be made of aluminum oxide, magnesium oxide, silicon oxide, or oxynitride. Silicon, silicon oxide nitride, silicon nitride, gallium oxide, germanium oxide, indium oxide tritium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and oxide The insulating film 360 may be a laminate of the above materials. The insulating film 360 may be formed by a method such as a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method. It can be formed using the above.

[0163] Next, a second conductive film 370 that will become the gate electrode layer 170 is formed on the insulating film 360 (FIG. 1 0(A)). The second conductive film 370 may be made of Al, Ti, Cr, Co, Ni, Cu, Uses Y, Zr, Mo, Ru, Ag, Ta, W, or alloy materials with these as the main components. The second conductive film 370 can be formed by a sputtering method, a CVD method, or the like. In addition, the second conductive film 370 may be a conductive film containing nitrogen. A laminate of a conductive film containing a material and a conductive film containing nitrogen may be used.

[0164] Next, the second conductive film 37 is formed using a resist mask for forming the gate electrode layer 170. 0 is selectively etched to form a gate electrode layer 170.

[0165] Next, the insulating film 360 is selected using the resist mask or the gate electrode layer 170 as a mask. Selective etching is performed to form the gate insulating film 160 .

[0166] Next, the third oxide semiconductor is formed using the resist mask or the gate electrode layer 170 as a mask. The oxide semiconductor film 333 is etched to form the third oxide semiconductor layer 133 (see FIG. 10B). ).

[0167] The second conductive film 370, the insulating film 360, and the third oxide semiconductor film 333 are etched. The coating may be performed for each layer or continuously.

[0168] Next, an insulating layer is formed on the source electrode layer 140, the drain electrode layer 150, and the gate electrode layer 170. The insulating layer 180 and the insulating layer 185 are formed (see FIG. 10(C)). The layer 185 can be formed using a material and a method similar to those of the base insulating film 120. It is particularly preferable to use aluminum oxide for the insulating layer 180 .

[0169] In addition, the insulating layer 180 is subjected to ion implantation, ion doping, plasma immersion ion implantation, etc. Oxygen may be added by implantation or the like. This makes it easier to supply oxygen from the insulating layer 180 to the oxide semiconductor layer 130. Cut.

[0170] Next, a third heat treatment may be performed under the same conditions as the first heat treatment. The third heat treatment can be performed by the following steps. Excess oxygen is easily released from the insulating layer 180, and oxygen vacancies in the oxide semiconductor layer 130 are reduced. It can be reduced.

[0171] Next, using a resist mask having an opening, the insulating layer 185, the insulating layer 180, the source electrode layer 140, a drain electrode layer 150, a second oxide semiconductor layer 132, and a first oxide semiconductor layer 140. The conductor layer 131 is selectively etched to form an opening 147 and an opening 157 (FIG. 11 At this time, the opening 177 shown in FIG. 2 is also formed in the same manner.

[0172] In addition, the insulating layer 185, the insulating layer 180, the source electrode layer 140, the drain electrode layer 150, the second The etching of the second oxide semiconductor layer 132 and the first oxide semiconductor layer 131 is performed layer by layer. The etching method may be dry etching, wet etching, or the like. Either a direct etching or a direct etching may be used, and a different etching method may be used for each layer.

[0173] Then, the first wiring 145 and the second wiring 155 are arranged to cover the opening 147 and the opening 157. The second oxide semiconductor layer 132 and the source electrode layer 140 are electrically connected to the first wiring 145. The second oxide semiconductor layer 132 and the drain electrode layer 150 are electrically connected to the second wiring 155. (See FIG. 11B). At this time, the opening 177 shown in FIG. A third wiring 175 is formed so as to cover the gate electrode layer 170, and the third wiring 175 and the gate electrode layer 170 are electrically connected to each other. Connect to the target.

[0174] The first wiring 145, the second wiring 155, and the third wiring 175 are connected to the source electrode layer. 140, the drain electrode layer 150, or the gate electrode layer 170 using the same material and method. It can be formed.

[0175] Through the above steps, the transistor 100 illustrated in FIG. 1 can be manufactured.

[0176] The metal film described in this embodiment is typically formed by a sputtering method or a plasma CVD method. However, it may be formed by other methods, for example, a thermal CVD method. An example of the thermal CVD method is MOCVD (Metal Organic Chemical Vapor Deposition). Examples include the ALD method and the vapor deposition method.

[0177] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0178] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the inside of the chamber is By reacting near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0179] In the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gases for the reaction are sequentially The gas may be introduced into the chamber and the film may be formed by repeating the gas introduction sequence. For example, By switching between the switching valves (also called high-speed valves), two or more types of raw materials can be mixed. The gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the multiple source gases. At the same time or after this, an inert gas (argon, nitrogen, etc.) is introduced to If an inert gas is introduced at the same time, the inert gas acts as a carrier gas. In addition, an inert gas may be introduced at the same time as the second raw material gas is introduced. In addition, instead of introducing an inert gas, the first source gas is discharged by evacuation, and then the second source gas is introduced. The first source gas may be adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later, forming a thin film. This process is repeated several times while controlling the gas introduction sequence until the desired thickness is formed. The thickness of the thin film can be adjusted by repeating the gas introduction sequence. The number of repetitions can be adjusted to allow precise film thickness adjustment, and fine F This is suitable for producing ET.

[0180] For example, when forming a tungsten film using a deposition system that uses ALD, the WF 6 G S and B 2 H 6 The gases are introduced repeatedly in sequence to form an initial tungsten film, and then WF 6 Gas and H 2 Gases are introduced simultaneously to form a tungsten film. 2 H 6 Instead of gas SiH 4 A gas may also be used.

[0181] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0182] (Embodiment 3) In this embodiment, a transistor according to one embodiment of the present invention is used, and a transistor is A semiconductor device (memory device) that can retain memory contents even under certain conditions and has no limit on the number of times it can be written to. An example of the device will be described with reference to the drawings.

[0183] FIG. 12A shows a cross-sectional view of the semiconductor device, and FIG. 12B shows a circuit diagram of the semiconductor device. .

[0184] The semiconductor device shown in FIG. 12(A) and FIG. 12(B) uses a first semiconductor material in the lower part. A transistor 3300 having a transistor 3200 and a second semiconductor material on top of the transistor 3300; and a capacitor 3400. The transistor 101 described in the first embodiment can be used.

[0185] The capacitor 3400 has one electrode connected to the source electrode layer or the drain electrode layer of the transistor 3300. A wiring layer electrically connected to the drain electrode layer, and the other electrode is connected to the gate electrode of the transistor 3300. The electrode layer and the dielectric are made of the same material as the insulating layer 180 and the insulating layer 185 of the transistor 3300. By using this structure, the transistor 3300 and the transistor 3301 can be formed at the same time.

[0186] Here, the first semiconductor material and the second semiconductor material have different energy gaps. For example, it is preferable that the first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon). and the second semiconductor material may be the oxide semiconductor described in Embodiment 1. Transistors using materials other than oxide semiconductors can easily operate at high speed. In addition, transistors using oxide semiconductors have electrical characteristics of low off-state current, which allows them to be charged for a long time. Allows retention.

[0187] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. In order to hold the resistance, a transistor including an oxide semiconductor as described in Embodiment 1 is used. Others include specific configurations of semiconductor devices, such as materials used in the semiconductor device and the structure of the semiconductor device. need not be limited to those shown here.

[0188] The transistor 3200 in FIG. 12A is made of a semiconductor material (e.g., crystalline silicon). A channel forming region is provided on a substrate 3000 including a semiconductor device, and the channel forming region is sandwiched between the semiconductor device and the semiconductor device. an impurity region provided in the semiconductor substrate, an intermetallic compound region in contact with the impurity region, and a channel forming region a gate insulating film provided on the gate electrode layer; and a gate electrode layer provided on the gate insulating film. In addition, in the drawings, the source electrode layer and the drain electrode layer may not be explicitly shown. For convenience, this state may be referred to as a transistor. In order to explain the connection relationship of the transistor, the source electrode including the source region and drain region is That is, in this specification, the source electrode layer and the drain electrode layer are sometimes referred to as a source electrode layer and a drain electrode layer. The description may include a source region.

[0189] An element isolation insulating layer 3100 is provided on a substrate 3000 so as to surround a transistor 3200. An insulating layer 3150 is provided to cover the transistor 3200. The element isolation insulating layer 3100 is formed by LOCOS (Local Oxidation of Silicon licon) and STI (Shallow Trench Isolation) It can be formed by using element isolation technology.

[0190] For example, when a crystalline silicon substrate is used, the transistor 3200 can operate at high speed. Therefore, by using the transistor as a readout transistor, The readout can be performed at high speed.

[0191] A transistor 3300 is provided on the insulating layer 3150, and its source electrode layer or drain The wiring electrically connected to the gate electrode layer serves as one electrode of the capacitor 3400. In addition, the electrode is electrically connected to the gate electrode layer of the transistor 3200.

[0192] The transistor 3300 illustrated in FIG. 12A has a channel formed in an oxide semiconductor layer. The transistor 3300 is a top-gate transistor. By using this, it is possible to retain memory contents for a long period of time. Semiconductor memory that does not require a refresh operation or that requires a very infrequent refresh operation Since it is possible to use the memory device as a storage device, power consumption can be reduced sufficiently.

[0193] In addition, an electrode 3250 is provided so as to overlap with the transistor 3300 with an insulating layer 3150 interposed therebetween. By applying an appropriate potential to this electrode as the second gate electrode, The threshold voltage of the transistor 3300 can be controlled. The long-term reliability can be improved. By operating the electrode 325 at the same potential as the electrode 325, the on-current can be increased. It is also possible to configure the number 0 not to be set.

[0194] As shown in FIG. 12A, a transistor 33 is formed on a substrate on which a transistor 3200 is formed. 3400 and a capacitor element 3400 can be formed, thereby increasing the integration degree of the semiconductor device. It is possible.

[0195] An example of a circuit configuration corresponding to FIG. 12(A) is shown in FIG. 12(B).

[0196] In FIG. 12B, a first wiring 3001 is connected to a source electrode layer of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode layer of the transistor 3200. The third wiring 3003 is connected to the source electrode layer of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the drain electrode layers of the transistor 33. 00 and the gate electrode layer of the transistor 3200. The other of the source electrode layer and the drain electrode layer of the transistor 3300 is a capacitor. The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. The element corresponding to the electrode 3250 is not shown in the figure. Not yet.

[0197] In the semiconductor device illustrated in FIG. 12B, the potential of the gate electrode layer of the transistor 3200 is held. By taking advantage of this feature, it is possible to write, store, and read information as follows: be.

[0198] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode layer of the transistor 3200 and and the capacitor 3400. That is, the gate electrode layer of the transistor 3200 A certain charge is applied (write). Here, two different potential levels are applied. Either a low-level charge or a high-level charge is given. After that, the potential of the fourth wiring 3004 is set to a value that turns off the transistor 3300. By applying a potential to the transistor 3300 to turn it off, the transistor 3200 The charge applied to the gate electrode layer is retained (retention).

[0199] Since the off-state current of the transistor 3300 is extremely small, the gate voltage of the transistor 3200 The charge in the pole layer is retained for a long period of time.

[0200] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, the transistor Depending on the amount of charge held in the gate electrode layer of the capacitor 3200, the second wiring 3002 has different potentials. In general, if the transistor 3200 is an n-channel type, then the transistor 320 The apparent threshold voltage V when a high-level charge is applied to the gate electrode layer of th_H In the figure, a low-level charge is applied to the gate electrode layer of the transistor 3200. The apparent threshold voltage V th_L This is because the apparent The low voltage is the voltage required to turn on the transistor 3200. Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L The potential V between 0By this, a gate electrode layer of the transistor 3200 is provided with For example, in writing, a high-level charge is applied. In this case, the potential of the fifth wiring 3005 is V 0 (>V th_H ) Then, Trans If a low level charge is applied, the fifth The potential of the wiring 3005 is V 0 ( <V th_L ), transistor 3200 is "off" Therefore, by determining the potential of the second wiring 3002, The information stored in the memory can be read out.

[0201] When memory cells are arranged in an array, only the information in a desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode layer The potential at which transistor 3200 is in the "off state" regardless of th_ H A smaller potential may be applied to the fifth wiring 3005. Regardless of the potential, transistor 3200 is in the "on" state, i.e., V th_L A larger potential may be applied to the fifth wiring 3005 .

[0202] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0203] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, Problems such as deterioration of the gate insulating film are unlikely to occur. In this device, there is no limit to the number of times that can be rewritten, which is an issue with conventional non-volatile memory, and it is reliable. Furthermore, the on and off states of transistors allow the writing and reading of information to be performed Since the data is written into the memory, high speed operation can be easily achieved.

[0204] As described above, a semiconductor device that realizes miniaturization and high integration and has excellent electrical characteristics is developed. An apparatus can be provided.

[0205] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0206] (Embodiment 4) In this embodiment, a transistor according to one embodiment of the present invention is used, and a transistor is A semiconductor device that can retain memory contents even under certain conditions and has no limit on the number of times it can be written to. A semiconductor device having a structure different from that shown in the third embodiment will be described.

[0207] FIG. 13 is an example of a circuit configuration of a semiconductor device. In the semiconductor device, the first wiring 4 The source electrode layer of the transistor 4300 is electrically connected to the second wiring 460. 0 and the gate electrode layer of the transistor 4300 are electrically connected to each other, and the transistor 4300 The drain electrode layer and the first terminal of the capacitor 4400 are electrically connected to each other. The transistor 4300 included in the semiconductor device may be the transistor described in Embodiment 1. The first wiring 4500 is a bit line, and the second wiring Line 4600 may function as a word line.

[0208] The semiconductor device (memory cell 4250) includes a transistor 3300 and a capacitor 3301 shown in FIG. The capacitance element 4400 can be connected in the same manner as the capacitance element 3400. The transistor 4300 can be manufactured in the same manner as the capacitor 3400 described in Embodiment 3. can be simultaneously produced.

[0209] Next, data is written and held in the semiconductor device (memory cell 4250) shown in FIG. The following describes how to do this.

[0210] First, a potential that turns on the transistor 4300 is supplied to the second wiring 4600. The transistor 4300 is turned on. As a result, the potential of the first wiring 4500 is The potential of the second wiring 4600 is then applied to the first terminal of the first wiring 4400 (write). is set as a potential at which the transistor 4300 is turned off, By setting the potential at the first terminal of the capacitor 4400 in this state, the potential at the first terminal of the capacitor 4400 is held (retained).

[0211] The transistor 4300 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 4300 is turned off, the capacitor 4400 The potential of the first terminal (or the charge stored in the capacitor 4400) is kept constant for an extremely long time. It is possible to hold the signal for a long time.

[0212] Next, reading of information will be described. When the transistor 4300 is turned on, The first wiring 4500 in the free state and the capacitor element 4400 are electrically connected to each other. Charge is redistributed between the capacitors 4400. As a result, the potential of the first wiring 4500 changes. The change in the potential of the first wiring 4500 is proportional to the change in the potential of the first terminal of the capacitor 4400 ( Alternatively, it takes a different value depending on the charge stored in the capacitor element 4400.

[0213] For example, the potential of the first terminal of the capacitance element 4400 is V, the capacitance of the capacitance element 4400 is C, The capacitance component of the first wiring 4500 before the charge is redistributed is CB. If the potential is VB0, the potential of the first wiring 4500 after the charge is redistributed is (CB× VB0+C×V) / (CB+C). Therefore, the state of memory cell 4250 is Assume that the potential of the first terminal of the capacitance element 4400 has two states, V1 and V0 (V1>V0). Then, the potential of the first wiring 4500 when the potential V1 is held is (=(CB×VB0+C ×V1) / (CB+C) is the potential of the first wiring 4500 when the potential V0 is maintained. It can be seen that it is higher than (=(CB×VB0+C×V0) / (CB+C)).

[0214] Then, the potential of the first wiring 4500 is compared with a predetermined potential, thereby reading out information. can be done.

[0215] In this manner, the semiconductor device (memory cell 4250) shown in FIG. Since the off-state current of the capacitor 4400 is extremely small, the charge stored in the capacitor 4400 is That is, no refresh operation is required, or The frequency of refresh operations can be reduced significantly, significantly reducing power consumption. In addition, even if there is no power supply, the contents stored in the memory can be preserved for a long period of time. It is possible to retain it.

[0216] The memory cell 4250 shown in FIG. 13 includes a drive circuit for driving the memory cell 4250. It is preferable to stack a substrate on which the memory cell 4250 and the driver circuit are formed. In this way, the semiconductor device can be miniaturized. The number of driving circuits is not limited.

[0217] The transistors included in the driver circuit are made of a different semiconductor material from the transistor 4300. For example, silicon, germanium, silicon germanium, silicon carbide, It is preferable to use a single crystal semiconductor. A transistor using such a semiconductor material is a transistor using an oxide semiconductor. This allows for faster operation than the conventional MOS transistor, and is suitable for use in configuring a drive circuit for the memory cell 4250. is doing.

[0218] As described above, a semiconductor device that realizes miniaturization and high integration and has excellent electrical characteristics is developed. An apparatus can be provided.

[0219] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0220] (Embodiment 5) The transistor described in the first embodiment is applicable to display devices, memory devices, CPUs, DSPs (Digital Signal Processors), and other devices. Intelligent Signal Processor), Custom LSI, PLD (Programmable LSI) ammable logic device), RF-ID (Radio Frequency Identification) It can be applied to semiconductor devices such as In this embodiment mode, examples of electronic devices including the above semiconductor device will be described.

[0221] Examples of electronic devices having the semiconductor device include televisions, display devices such as monitors, lighting devices, and photovoltaic devices. Personal computers, word processors, image reproduction devices, portable audio players Radios, tape recorders, stereos, telephones, cordless telephones, mobile phones, car phones , transceivers, radios, game consoles, calculators, personal digital assistants, electronic organizers, electronic books, electronic translations Translators, voice input devices, video cameras, digital still cameras, electric shavers, IC chips , microwave ovens and other high-frequency heating devices, electric rice cookers, electric washing machines, vacuum cleaners, air conditioners air conditioning equipment such as hair dryers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators refrigerators, electric freezers, electric refrigerator-freezers, freezers for DNA storage, radiation measuring devices, dialysis machines, X-ray Medical equipment such as diagnostic equipment, etc. Smoke detectors, heat detectors, gas alarms, Examples of such devices include alarm devices such as burglar alarm devices. In addition, emergency exit lights, traffic lights, conveyor belts, Examples of industrial equipment include elevators, escalators, industrial robots, and power storage systems. In addition, the vehicle is propelled by an engine using fuel or an electric motor using power from a non-aqueous secondary battery. The electronic device also includes moving objects that move around. , electric vehicles (EV), hybrid vehicles (HEV) that combine internal combustion engines and electric motors, Hybrid electric vehicles (PHEVs), tracked vehicles that use these tires and wheels as tracks, Motorized bicycles including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, Small or large ships, submarines, helicopters, aircraft, rockets, satellites, space probes Examples of electronic devices include spacecraft, planetary probes, and spacecraft. Some specific examples of these electronic devices are shown in Figure 14.

[0222] A television set 8000 shown in FIG. 14A includes a housing 8001 and a display unit 8002. It displays images on a display unit 8002 and outputs audio from a speaker unit 8003. The memory device including the transistor of one embodiment of the present invention can be used in the display unit 80. It is possible to use the device in a driver circuit for operating the .02.

[0223] The television device 8000 also includes a CPU 8004 for performing information communication and a memory. The CPU 8004 or the memory may include a transistor according to one embodiment of the present invention. A CPU and a storage device can be used.

[0224] The alarm device 8100 shown in FIG. 14(A) is a residential fire alarm, and includes a smoke or heat detection unit. 8102 and an example of an electronic device using a microcomputer 8101. The computer 8101 includes a memory device having a transistor according to one embodiment of the present invention and a CPU. .

[0225] In addition, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 shown in FIG. The sensor may be an electronic device including a transistor, a memory device, a CPU, or the like described in the above embodiment. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a CP In FIG. 14A, the CPU 8203 is In the illustrated example, the CPU 8203 is provided in the outdoor unit 8204. Alternatively, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The transistor according to one embodiment of the present invention may be used in a CPU of an air conditioner. This can reduce power consumption.

[0226] In addition, the electric refrigerator-freezer 8300 shown in FIG. 14A is a transistor shown in the above embodiment. Specifically, an electric freezer / refrigerator is an example of an electronic device that includes a processor, a memory device, or a CPU. The storage 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, and a CPU 830. In FIG. 14A, a CPU 8304 is provided inside a housing 8301. The transistor of one embodiment of the present invention is used for a CPU 8304 of an electric refrigerator-freezer 8300. This can help save power.

[0227] 14B and 14C show an example of an electric vehicle, which is an example of an electronic device. The power of the secondary battery 9701 is supplied to the circuit 97 The output is adjusted by the circuit 9702 and supplied to the driver 9703. The present invention is controlled by a processing unit 9704 having a ROM, RAM, CPU, etc. By using the transistor of one embodiment in the CPU of the electric vehicle 9700, power saving can be achieved. can be.

[0228] The driving device 9703 is a DC motor or an AC motor alone, or a motor and an internal combustion engine, The processing device 9704 is configured by combining the above. Information on driving (such as acceleration, deceleration, stopping, etc.) and information on driving (such as uphill and downhill slopes, Based on input information (load information, etc.), the circuit 9702 outputs a control signal. The electric energy supplied from the secondary battery 9701 is controlled by a control signal from the processor 9704. The output of the drive unit 9703 is controlled by adjusting the speed. Although not shown, it also has a built-in inverter that converts direct current to alternating current.

[0229] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. . [Explanation of symbols]

[0230] 100 transistors 101 Transistor 110 Substrate 120 Undercoat insulating film 130 Oxide semiconductor layer 131 First oxide semiconductor layer 132 Second oxide semiconductor layer 133 Third oxide semiconductor layer 135 Boundary 137 Channel Region 140 Source electrode layer 145 First Wiring 147 Opening 150 Drain electrode layer 155 Second Wiring 157 Opening 160 Gate insulating film 170 Gate electrode layer 172 Conductive Film 175 Third Wire 177 Opening 180 Insulating layer 185 Insulating Layer 331 First oxide semiconductor film 332 Second oxide semiconductor film 333 Third oxide semiconductor film 360 Insulating Film 370 Second conductive film 3000 boards 3001 First Wiring 3002 Second Wiring 3003 Third Wiring 3004 4th Wiring 3005 5th Wiring 3100 Element isolation insulating layer 3150 Insulation layer 3200 Transistors 3250 electrode 3300 Transistors 3400 Capacitive element 4250 memory cells 4300 Transistors 4400 Capacitive element 4500 1st Wiring 4600 Second Wiring 8000 Television Equipment 8001 Case 8002 Display section 8003 Speaker section 8004 CPU 8100 Alarm device 8101 Microcomputers 8102 Detector 8200 indoor unit 8201 Case 8202 Ventilator 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Case 8302 Refrigerator door 8303 Freezer door 8304 CPU 9700 Electric Vehicle 9701 Secondary battery 9702 Circuit 9703 Drive unit 9704 Processing Equipment

Claims

1. a first transistor having a first channel formation region including silicon; a second transistor having a second channel formation region including an oxide semiconductor; a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, a first insulating film on the first channel formation region; a first conductive layer provided on the first insulating film and functioning as a gate electrode of the first transistor; a second conductive layer serving as a first gate electrode of the second transistor; a second insulating film on the first conductive layer and the second conductive layer; an oxide semiconductor layer having the second channel formation region on the second insulating film; a third insulating film on the second channel formation region; a third conductive layer provided on the third insulating film and functioning as a second gate electrode of the second transistor; a fourth insulating film on the third conductive layer; a fourth conductive layer on the fourth insulating film; the first conductive layer is electrically connected to the oxide semiconductor layer via the fourth conductive layer; the fourth conductive layer is electrically connected to the oxide semiconductor layer through an opening penetrating the fourth insulating film; a bottom of the opening is located in the oxide semiconductor layer; In a cross-sectional view of the second transistor in a channel length direction, a length of the second conductive layer in the channel length direction is larger than a length of the third conductive layer in the channel length direction; In the cross-sectional view, the opening is provided at a position that does not overlap the second conductive layer.

2. a first transistor having a first channel formation region including silicon; a second transistor having a second channel formation region including an oxide semiconductor; a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, a first insulating film on the first channel formation region; a first conductive layer provided on the first insulating film and functioning as a gate electrode of the first transistor; a second conductive layer serving as a first gate electrode of the second transistor; a second insulating film on the first conductive layer and the second conductive layer; an oxide semiconductor layer having the second channel formation region on the second insulating film; a third insulating film on the second channel formation region; a third conductive layer provided on the third insulating film and functioning as a second gate electrode of the second transistor; a fourth insulating film on the third conductive layer; a fourth conductive layer on the fourth insulating film; the first conductive layer is electrically connected to the oxide semiconductor layer via the fourth conductive layer; the fourth conductive layer is electrically connected to the oxide semiconductor layer through an opening penetrating the fourth insulating film; the oxide semiconductor layer has a first thickness in a region overlapping with the opening and a second thickness in a region not overlapping with the opening; the first film thickness is smaller than the second film thickness; In a cross-sectional view of the second transistor in a channel length direction, a length of the second conductive layer in the channel length direction is greater than a length of the third conductive layer in the channel length direction; In the cross-sectional view, the opening is provided at a position that does not overlap the second conductive layer.

3. In claim 1 or 2, A semiconductor device comprising: a fifth conductive layer having a same material as the second conductive layer and having a region overlapping the fourth conductive layer in a cross-sectional view.

Images