Antiferroelectric thin film structure and electronic device including same

Abstract

To provide an antiferroelectric thin film structure and an electronic device including the same.SOLUTION: An antiferroelectric thin film structure includes a dielectric layer containing hafnium oxide (HfO2) and exhibiting an anti-ferroelectric phase, and an intercalating layer containing an oxide inserted within the dielectric layer. An electronic element to which the antiferroelectric thin film structure is applied can secure an operating voltage section with almost no hysteresis.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an antiferroelectric thin film structure and an electronic device including the same. [Background technology]

[0002] As electronic devices are down-scaling, the space that electronic circuits occupy within the electronic devices is also shrinking. This has led to a demand for smaller and more powerful electronic elements such as capacitors and transistors in electronic circuits. To this end, research into dielectric thin films with high dielectric constants that can exhibit desired operating characteristics even at thin thicknesses is ongoing. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved by the present invention is to provide an antiferroelectric thin film structure exhibiting a high dielectric constant.

[0004] Another problem to be solved by the present invention is to provide an electronic device utilizing an antiferroelectric thin film structure. [Means for solving the problem]

[0005] According to an embodiment, hafnium oxide (HfO 2 and an insertion layer, interposed within the dielectric layer and including an oxide.

[0006] The dielectric layer may contain Y, Al, Ti, Sr, Zr, La or N as a dopant.

[0007] The content of the dopant is 50% or less based on the total elements of the dielectric layer.

[0008] The oxide contained in the insertion layer is M x Oy where M is Al, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, or Lu.

[0009] The thickness of the insertion layer is also greater than 0% and less than or equal to 50% of the total thickness of the antiferroelectric thin film structure.

[0010] The dielectric layer may include a first dielectric layer located on the upper side of the insertion layer and a second dielectric layer located on the lower side of the insertion layer, and the thicknesses of the first dielectric layer and the second dielectric layer may be greater than zero.

[0011] According to an embodiment, there is provided an electronic device, comprising: a bottom electrode; an antiferroelectric thin film structure as described above disposed on the bottom electrode; and a top electrode disposed on the antiferroelectric thin film structure.

[0012] The bottom electrode may include a metal, a metal nitride, a metal oxide, or a combination thereof.

[0013] The lower electrode includes Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs. , Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, or U.

[0014] The dielectric layer may contain Y, Al, Ti, Sr, Zr, La or N as a dopant.

[0015] The content of the dopant is 50% or less based on the total elements of the dielectric layer.

[0016] The oxide contained in the insertion layer is M x O ywhere M is Al, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, or Lu.

[0017] The thickness of the insertion layer is also greater than 0% and less than or equal to 50% of the total thickness of the antiferroelectric thin film structure.

[0018] The electronic device may further include a transistor electrically connected to the bottom electrode.

[0019] According to an embodiment, an electronic device is provided that includes a semiconductor substrate; an antiferroelectric thin film structure as described above disposed on the semiconductor substrate; and an upper electrode disposed on the antiferroelectric thin film structure.

[0020] The dielectric layer may contain Y, Al, Ti, Sr, Zr, La or N as a dopant.

[0021] The content of the dopant is 50% or less based on the total elements of the dielectric layer.

[0022] The oxide contained in the insertion layer is M x O y where M is Al, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, or Lu.

[0023] The thickness of the insertion layer is also greater than 0% and less than or equal to 50% of the total thickness of the antiferroelectric thin film structure.

[0024] The electronic device may further include an insulating layer disposed between the semiconductor substrate and the antiferroelectric thin film structure.

[0025] The electronic device may further include a conductive layer disposed between the antiferroelectric thin film structure and the insulating layer.

[0026] The conductive layer includes Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs. , Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, or U.

[0027] The semiconductor substrate may include a source region, a drain region, and a channel region located between the source region and the drain region, and the antiferroelectric thin film structure may be disposed on the channel region.

[0028] The dielectric layer and the insertion layer also differ from each other in at least one of electric charge, partial charge, and asymmetric charge, so that an electric dipole is formed at the interface between the dielectric layer and the insertion layer.

[0029] According to an embodiment, there is provided a memory cell including a charge storage element comprising an antiferroelectric thin film structure as described above.

[0030] The charge storage element may be a capacitor or a floating gate.

[0031] According to an embodiment, an electronic device is provided that includes the memory cell. Effect of the Invention

[0032] The antiferroelectric thin film structure described above exhibits a wide hysteresis-free operating range and a high dielectric constant.

[0033] The above-described antiferroelectric thin film structures may be employed in a variety of electronic devices, such as transistors, capacitors, and integrated circuit devices.

[0034] An electronic device to which the above-described antiferroelectric thin film structure is applied can ensure an operating voltage range with almost no hysteresis. [Brief description of the drawings]

[0035] [Figure 1] 1 is a cross-sectional view showing a schematic structure of an antiferroelectric thin film structure according to an embodiment and an electronic device including the same. [Figure 2A] 2 is a graph illustrating the polarization hysteresis characteristics exhibited by the antiferroelectric thin film structure of the electronic device of FIG. 1 for different insertion layer thicknesses. [Figure 2B] 2 is a graph illustrating the polarization hysteresis characteristics exhibited by the antiferroelectric thin film structure of the electronic device of FIG. 1 for different insertion layer thicknesses. [Figure 3A] 2 is a graph showing capacitance hysteresis characteristics of the electronic device of FIG. 1 for different insertion layer thicknesses. [Figure 3B] 2 is a graph showing capacitance hysteresis characteristics of the electronic device of FIG. 1 for different insertion layer thicknesses. [Figure 4] 1 is a graph showing a schematic configuration of an electronic device according to a comparative example. [Diagram 5] 5 is a graph showing the capacitance hysteresis characteristic of the electronic device of FIG. 4 according to the composition of the dielectric layer. [Figure 6A] FIG. 11 is a cross-sectional view showing a schematic configuration of an electronic device according to another embodiment. [Figure 6B] 1 is a plan view showing a semiconductor device according to an embodiment; [Figure 6C] FIG. 6C is a cross-sectional view showing the AA′ cross section of FIG. 6B. [Figure 6D] FIG. 6C is a cross-sectional view showing the AA′ cross section of FIG. 6B. [Figure 7] FIG. 11 is a cross-sectional view showing a schematic configuration of an electronic device according to still another embodiment. [Figure 8] FIG. 11 is a cross-sectional view showing a schematic configuration of an electronic device according to still another embodiment. [Figure 9] 1 is a conceptual diagram illustrating a device architecture applied to an electronic device according to an embodiment; [Figure 10] 1 is a conceptual diagram illustrating a device architecture applied to an electronic device according to an embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. The described embodiments are merely examples, and various modifications are possible from such embodiments. Hereinafter, in the drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of explanation.

[0037] Hereinafter, the terms "upper" and "above" include not only what is directly above and in contact with something, but also what is above but not in contact with something.

[0038] Terms such as first, second, etc., may be used to describe various components, but are used only to distinguish one component from another, and are not intended to limit the materials or structures of the components.

[0039] The singular expression includes the plural expression unless the context clearly indicates otherwise. Furthermore, when a part "includes" a certain element, this does not mean to exclude other elements, but means that other elements may be further included, unless otherwise specified to the contrary.

[0040] In addition, terms such as "unit," "module," etc. used in the specification refer to a unit that processes at least one function or operation, and may be embodied in hardware or software, or a combination of hardware and software.

[0041] Use of the term "said" and similar referents can refer to both the singular and the plural.

[0042] The steps constituting the method may be performed in any suitable order unless expressly stated to be performed in the order described. In addition, the use of all exemplary terms (such as "for example") is merely intended to describe the technical idea in detail, and does not limit the scope of the claims, except as otherwise limited by the claims.

[0043] FIG. 1 is a cross-sectional view showing a schematic structure of an antiferroelectric thin film structure according to an embodiment and an electronic device including the same.

[0044] The antiferroelectric thin film structure 150 according to the embodiment is made of hafnium oxide (HfO 2 ) and exhibiting an anti-ferroelectric phase, and an insertion layer 130 inserted within the dielectric layer 120.

[0045] The electronic device 100 according to the embodiment includes a lower electrode 110 and an upper electrode 190 that are spaced apart from each other, and an antiferroelectric thin film structure 150 disposed therebetween. The electronic device 100 is also a capacitor.

[0046] The antiferroelectric thin film structure 150 is also proposed with a structure that exhibits a high dielectric constant and has an operating voltage range with little hysteresis.

[0047] Hafnium oxide (HfO 2 ) is a material used as a high-k dielectric material. 2Depending on the doping material and its amount, and / or the crystalline phase, and / or the stress state with the adjacent layers, the ferroelectric material exhibits para-electricity, ferro-electricity, or anti-ferroelectricity. For example, the ferroelectric material exhibits ferroelectricity in an orthorhombic crystalline phase, and the anti-ferroelectric material exhibits anti-ferroelectricity in a tetragonal crystalline phase. The dielectric constant and hysteresis characteristics differ depending on the state.

[0048] The antiferroelectric thin film structure 150 according to the embodiment is made of hafnium oxide (HfO) that exhibits an anti-ferroelectric phase so as to exhibit a high dielectric constant. 2 The dielectric layer 120 may be doped with Y, Al, Ti, Sr, Zr, La, or N. The doping amount is 50% or less of the total elements of the dielectric layer 120. For example, HfO doped with a doping agent (D) 2 Hf( 1-x )D x O 2 where x is equal to or less than 0.8. The amount of the dopant can be appropriately set according to the type of the dopant.

[0049] The insertion layer 130 is a layer embedded in the dielectric layer 120. If the region of the dielectric layer 120 is divided into a first dielectric layer 121 located on the upper side of the insertion layer 130 and a second dielectric layer 122 located on the lower side of the insertion layer 130, the thicknesses of the first dielectric layer 121 and the second dielectric layer 122 are both set to be greater than 0. The insertion layer 130 is also called a built-in field control layer. The built-in field is an electric field generated between the upper electrode 190 and the lower electrode 110 inside the dielectric layer 120, and is generated due to a work function difference at the electrode interface, a dielectric film defect of the dielectric layer 120, etc. Such a built-in field causes hysteresis. The insertion layer 130 can control the built-in field by forming an additional electric dipole or charge in the dielectric layer 120. For example, the intercalation layer 130 may create an electric field that offsets the built-in field.

[0050] The insertion layer 130 includes an oxide. The oxide included in the insertion layer 130 is M x O y where M is Al, Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, or Lu. O is oxygen, and x and y are real numbers greater than 0.

[0051] The above oxides have a band gap of 4 eV or more. The oxygen ratio of the oxides is 1.0 to 1.0 eV. 2 The charge (and / or partial charge) distribution in the oxide is different from the charge (and / or partial charge) distribution in hafnium oxide, and the oxide has an asymmetric charge distribution, which may result in the formation of additional electric dipoles and / or charges at the interface between the insertion layer 130 and the dielectric layer 120.

[0052] For example, in an exemplary embodiment, at least one of the oxidation numbers, electronegativities and / or electronic structures of the above oxides differs from that of dielectric layer 120, such that the band alignment and / or charge distribution of antiferroelectric thin film structure 150 is also different from that of the antiferroelectric thin film structure without insertion layer 130.

[0053] The thickness of the insertion layer 130 is more than 0% and less than 50% of the total thickness of the antiferroelectric thin film structure 150. The thickness of the insertion layer 130 is 1% or more, 3% or more, 5% or more, 30% or less, or 10% of the total thickness of the antiferroelectric thin film structure 150. The position of the insertion layer 130 is not particularly limited except that it is interposed inside the dielectric layer 120. For example, it may be disposed at any position within the dielectric layer 120, such as the upper side, the center, or the lower side. The material and thickness of the insertion layer 130 may be appropriately set to control the built-in field inside the dielectric layer 120 and reduce hysteresis.

[0054] The top electrode 190 and the bottom electrode 110 include a conductive material, for example, a metal, a metal nitride, a metal oxide, or a combination thereof.

[0055] The lower electrode 110 may be made of a material that provides an appropriate tensile stress to the interface with the dielectric layer 120 to cause the dielectric layer 120 to have an antiferroelectric phase. 2The crystalline phase of the ferroelectric material may be an orthorhombic crystalline phase that exhibits ferroelectricity, or a tetragonal crystalline phase that exhibits anti-ferroelectricity. The lower electrode 110 includes, for example, Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, or U. Here, the lower electrode 110 is an electrode located under the antiferroelectric thin film structure 150, which means that after the lower electrode 110 is manufactured, the antiferroelectric thin film structure 150 is formed thereon.

[0056] The thickness of the insertion layer 130 is a factor that affects the polarization and capacitance of the antiferroelectric thin film structure, and the experimental results relating to this will be described with reference to FIGS. 2A to 3B.

[0057] 2A and 2B are graphs illustrating the polarization hysteresis characteristics exhibited by the antiferroelectric thin film structure of the electronic device of FIG. 1 for different insertion layer thicknesses.

[0058] The polarization characteristic according to the applied voltage exhibits hysteresis characteristics, and the width of the operating section where there is almost no hysteresis is shown differently in the graphs of FIG. 2A and FIG. 2B.

[0059] The thicknesses of the insertion layers in FIG. 2A and FIG. 2B are t1 and t2, respectively, and t1 and t2 are both greater than 0% and less than 10% of the total thickness of the antiferroelectric thin film structure. <t2である。

[0060] It is confirmed that as the thickness of the insertion layer increases within the above range, the width of the operating section without hysteresis increases from OP1 to OP2, and the center of the operating section also moves toward 0 V. Therefore, it can be seen that the thickness of the insertion layer affects the degree of control of the built-in field and reduces hysteresis.

[0061] 3A and 3B are graphs illustrating the capacitance hysteresis characteristics of the electronic device of FIG. 1 for different insertion layer thicknesses.

[0062] 3A and 3B correspond to FIGS. 2A and 2B, respectively, and it can be seen that the hysteresis of capacitance also varies depending on the thickness of the insertion layer.

[0063] FIG. 4 is a graph showing a schematic configuration of an electronic device according to a comparative example, and FIG. 5 is a graph showing the capacitance hysteresis characteristic of the electronic device of FIG. 4 according to the composition of the dielectric layer.

[0064] The electronic device 10 of the comparative example includes a lower electrode 11, a dielectric layer 12, and an upper electrode 19, but does not include an insertion layer, unlike the embodiment.

[0065] Referring to the graph of FIG. 4, the composition of the dielectric layer 12, i.e., Hf 0.3 Zr 0.7 O 2 , Hf 0.5 Zr 0.5 O 2 , HfO 2 In each case, the capacitance value is different and the hysteresis characteristic is also different. As the Zr content increases, the capacitance increases, but the hysteresis also increases. In the comparative example, the capacitance is low, and the HfO 2 The composition alone can be applied as a capacitor.

[0066] In contrast, since the antiferroelectric thin film structure 150 of the embodiment has reduced hysteresis due to the presence of the insertion layer 130, the composition having both high capacitance and hysteresis as illustrated in FIG. 5 can also be used for the dielectric layer 120 and applied as a capacitor.

[0067] FIG. 6A is a cross-sectional view showing a schematic configuration of an electronic device according to another embodiment.

[0068] The electronic device 300 includes a structure in which the capacitor 101 and the transistor 200 are electrically connected, and is also a part of an electronic circuit realized by an integrated device.

[0069] The capacitor 101 includes the antiferroelectric thin film structure 150 provided in the electronic device 100 of FIG. 1, and has substantially the same configuration as the electronic device 100 of FIG.

[0070] The capacitor 101 may be electrically connected to the transistor 200 via a contact 20. The transistor 200 is also a field effect transistor. One of the electrodes 110 and 190 of the capacitor 101 may be electrically connected to one of the source SR and drain DR of the transistor 200 via the contact 20.

[0071] The transistor 200 includes a semiconductor substrate 210 having a source SR, a drain DR, and a channel CH, a gate electrode 290 disposed opposite the channel CH, and a gate insulating layer 220 disposed between the channel CH and the gate electrode 290.

[0072] The semiconductor substrate 210 includes a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), and may be modified into various forms such as silicon on insulator (SOI).

[0073] The semiconductor substrate 210 includes a source SR, a drain DR, and a channel CH electrically connected to the source SR and the drain DR. The source SR may be electrically connected to or in contact with one end of the channel CH, and the drain DR may be electrically connected to or in contact with the other end of the channel CH. That is, the channel CH may also be defined in a substrate region between the source SR and the drain DR in the semiconductor substrate 210.

[0074] The source SR, the drain DR, and the channel CH are formed by independently implanting impurities into different regions of the semiconductor substrate 210, and in this case, the source SR, the channel CH, and the drain DR may include the substrate material as a base material.

[0075] Additionally, the source SR and drain DR are formed of a conductive material, and for example, each independently includes a metal, a metal compound, or a conductive polymer.

[0076] The channel CH is not formed as a substrate base, but may be embodied as a separate material layer. In this case, for example, the channel CH may include not only semiconductor materials such as Si, Ge, SiGe, and III-V group, but also oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional materials (2D materials), quantum dots, and / or organic semiconductors. For example, oxide semiconductors include InGaZnO, etc., two-dimensional materials include TMDs (transition metal dichalcogenides) or graphene, and quantum dots include colloidal quantum dots and nanocrystal structures.

[0077] The gate electrode 290 may be disposed on the semiconductor substrate 210 and may be spaced apart from the semiconductor substrate 210 to face the channel CH. The gate electrode 290 may have a conductivity of 1 Mohm / square or less. The gate electrode 290 may include a metal, a metal nitride, a metal carbide, and / or polysilicon. For example, the metal may include aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and / or tantalum (Ta), and the metal nitride film may include a titanium nitride film (TiN film) and / or a tantalum nitride film (TaN film). The metal carbide may be a metal carbide doped (or contained) with aluminum and / or silicon, and may include TiAlC, TaAlC, TiSiC, or TaSiC, as a specific example. The gate electrode 290 may have a structure in which a plurality of materials are laminated, for example, a laminate structure of a metal nitride layer / metal layer such as TiN / Al, or a laminate structure of a metal nitride layer / metal carbide layer / metal layer such as TiN / TiAlC / W. The gate electrode 290 may include titanium nitride (TiN) or molybdenum (Mo), and the above examples may be modified in various ways.

[0078] The gate insulating layer 220 disposed between the semiconductor substrate 210 and the gate electrode 290 includes a paraelectric material or a high dielectric material and has a dielectric constant of 20 to 70. The gate insulating layer 220 includes silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, etc., or includes a 2D insulator such as h-BN (hexagonal boron nitride). For example, the gate insulating layer 220 can be silicon oxide (SiO 2 ), silicon nitride (SiN x ), and hafnium oxide (HfO 2 ), hafnium silicate (HfSiO 4 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO 3 ), zirconium oxide (ZrO 2), hafnium zirconium oxide (HfZrO 2 ), zirconium silicate (ZrSiO 4 ), tantalum oxide (Ta 2 O 5 ), titanium dioxide (TiO 2 ), strontium titanium oxide (SrTiO 3 ), yttrium oxide (Y 2 O 3 ), aluminum oxide (Al 2 O 3 ), Red Scandium Tantalum Oxide (PbSc 0.5 Ta 0.5 O 3 ), Red Zinc Niobate (PbZnNbO 3 ), etc. Also, the gate insulating layer 220 includes a metal nitride such as aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), or yttrium oxynitride (YON), a silicate such as ZrSiON, HfSiON, YSiON, or LaSiON, or an aluminate such as ZrAlON or HfAlON. Also, the gate insulating layer 220 may include the antiferroelectric thin film structure 150 described above. The gate insulating layer 220 can form a gate stack together with the gate electrode 290.

[0079] The contacts 20 comprise a suitable conductive material, such as tungsten, copper, aluminum, polysilicon, or the like.

[0080] The arrangement of the capacitor 101 and the transistor 200 may be modified in various ways. For example, the capacitor 101 may be disposed on the semiconductor substrate 210 as shown in the figure, or may be embedded in the semiconductor substrate 210 instead.

[0081] 6A illustrates an electronic device 300 having one capacitor 101 and one transistor 200, other embodiments of the electronic device may have such structures arranged in a two-dimensional repeating fashion. The electronic device 300 may be included in or form a memory cell, for example.

[0082] Referring to FIG. 6B, the semiconductor device D10 includes a field effect transistor, which includes a gate stack 230 including the gate electrode 290 and the gate insulating layer 220 of FIG. 6A, a substrate 210 including a source and a drain, a contact structure 20' arranged on the substrate 210 so as not to overlap with the gate stack 230, and a capacitor 101 arranged on the contact structure 20'. The semiconductor device D10 further includes a bit line structure 13 that electrically connects the field effect transistors to each other. FIG. 6B illustrates that the contact structure 20' and the capacitor 101 are repeatedly arranged along the X and Y directions, but is not limited thereto. For example, the contact structure 20' may be arranged along the X and Y directions, and the capacitor 101 may be arranged in a hexagonal shape such as a honeycomb structure.

[0083] Fig. 6C is a cross-sectional view of Fig. 6B taken along line A-A', showing an exemplary structure of a semiconductor device D10. Referring to Fig. 6C, a substrate 210 has a shallow trench isolation (STI) structure including an isolation layer 14. The isolation layer 14 includes a single or multiple insulating layers. The isolation layer 14 includes an isolation trench 14T in the substrate 210, and the isolation trench 14T is filled with an insulating material.

[0084] The substrate 210 further includes an active layer AC defined by the element isolation layer 14, and a gate line trench 230T, which may be aligned with the upper surface of the substrate 210 and extend in the X direction. The active layer AC has a long island shape having a long axis and a short axis. The long axis of the active layer AC may be aligned along a direction D3 parallel to the upper surface of the substrate 210, as shown in FIG. 6C. The gate line trench 230T may have a predetermined depth from the upper surface of the substrate 210 and may be aligned within or across the active layer AC. The gate line trench 230T may be provided in the element isolation layer 14, and the bottom of the gate line trench 230T provided in the element isolation layer 14 may be lower than the gate line trench 230T provided in the active layer AC.

[0085] A first source / drain 210ab and a second source / drain 210ab' may be disposed on the active layer AC and on both sides of the gate line trench 230T.

[0086] A gate stack 230 may be disposed in the gate line trench 230T. For example, a gate insulating layer 230a, a gate electrode 230b, and a gate capping layer 230c may be sequentially disposed in the gate line trench 230T. The gate insulating layer 230a and the gate electrode 230b may be the same as described above, and the gate capping layer 230c may include silicon oxide, silicon oxynitride, or silicon nitride. The gate capping layer 230c may be disposed on the gate electrode 230b to fill the remaining portion of the gate line trench 230T.

[0087] The bit line structure 13 may be disposed on the first source / drain 210ab. The bit line structure 13 may be aligned with an upper surface of the substrate 210 and extend in the Y direction. The bit line structure 13 is electrically connected to the first source / drain 210ab and includes a bit line contact 13a, a bit line 13b, and / or a bit line capping layer 13c sequentially formed on the substrate 210. For example, the bit line contact 13a includes polysilicon, the bit line 13b includes a metal material, and the bit line capping layer 13c includes an insulating material such as silicon nitride (SiN) and / or silicon oxynitride (SiON).

[0088] 6C, the bottom surface of the bit line contact 13a is shown to have the same height as the top surface of the substrate 210. However, the bit line contact 13a may be recessed to a predetermined depth from the top surface of the substrate 210, so that the bottom surface of the bit line contact 13a is lower than the top surface of the substrate 210.

[0089] Alternatively, the bit line structure 13 may include a bit line intermediate layer (not shown) between the bit line contact 13a and the bit line 13b. The bit line intermediate layer may include a metal silicide such as tungsten silicide or a metal nitride such as tungsten nitride. Also, a bit line spacer (not shown) may be further formed on a sidewall of the bit line structure 13. The bit line spacer may include an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride having a single layer or multi-layer structure. The bit line spacer may include an air space (not shown).

[0090] The contact structure 20' may be disposed on the second source / drain 210ab'. The contact structure 20' and the bit line structure 13 may be disposed on another source / drain of the substrate 210. The contact structure 20' has a structure in which a lower conductive pattern (not shown), a metal silicide layer (not shown), and an upper conductive pattern (not shown) are disposed on the second source / drain 210ab'. The contact structure 20' further includes a barrier layer (not shown) surrounding at least one of a bottom surface and a side surface of the upper contact pattern. In some embodiments, the lower conductive pattern includes a conductive and / or semiconductive material (e.g., polysilicon), and the upper conductive pattern includes a conductive material that is resistant to degradation and defect diffusion, such as a conductive metal nitride.

[0091] The capacitor 101 may be electrically connected to the contact structure 20′ and disposed on the substrate 210. For example, the capacitor 101 may include a lower electrode 110 electrically connected to the contact structure 20′, an antiferroelectric thin film structure 150 disposed on the lower electrode 110, and an upper electrode 190 disposed between the antiferroelectric thin film structure 150. The antiferroelectric thin film structure 150 may be disposed on the lower electrode 110 in parallel with a surface of the lower electrode 110.

[0092] An interlayer insulating film 15 may be disposed between the capacitor 101 and the substrate 210. The interlayer insulating film 15 may be disposed in a space between the capacitor 101 and the substrate 210. For example, the interlayer insulating film 15 covers wiring and / or electrodes such as the bit line structure 13, the contact structure 20′, and the gate stack 230 formed on or in the substrate 210. For example, the interlayer insulating film 15 surrounds the wall of the contact structure 20′. The interlayer insulating film 15 includes a first interlayer insulating film 15a surrounding the bit line contact 13a and a second interlayer insulating film 15b covering the top and side surfaces of the bit line 13b and the bit line capping layer 13c.

[0093] The lower electrode 110 of the capacitor 101 may be disposed on the interlayer insulating film 15 (e.g., the second interlayer insulating film 15b). When multiple capacitors 101 are disposed, bottom surfaces of the multiple lower electrodes 110 may be separated from each other by the etching stop layer 16. For example, the etching stop layer 16 may include an opening 16T, and the bottom surfaces of the lower electrodes 110 may be disposed in the opening 16T.

[0094] As shown in Fig. 6C, the lower electrode has a cylindrical shape or a bottomed cup shape. In another example, as shown in Fig. 6D, the lower electrode 110 has a columnar shape, for example, a circular cylinder, a rectangular column, or a polygonal column extending in the vertical direction (Z direction).

[0095] The capacitor 101 further includes a support layer (not shown) that supports the lower electrode 110 so that the lower electrode 110 does not tilt or collapse. The support layer may be disposed on a sidewall of the lower electrode 110, for example.

[0096] Although the above-described embodiment illustrates an electronic device in which the antiferroelectric thin film structure 150 is applied to a capacitor, the antiferroelectric thin film structure 150 of the embodiment can also be applied to a logic device.

[0097] FIG. 7 is a cross-sectional view showing a schematic configuration of an electronic device according to still another embodiment.

[0098] The electronic device 400 includes a semiconductor substrate 410 and an antiferroelectric thin film structure 150 disposed on the semiconductor substrate 410. An insulating layer 420 is provided between the semiconductor substrate 410 and the antiferroelectric thin film structure 150. An upper electrode 490 may be disposed on the antiferroelectric thin film structure 150.

[0099] The semiconductor substrate 410 includes a source SR, a drain DR, and a channel CH electrically coupled to the source SR and the drain DR, and is similar to the semiconductor substrate 210 of FIG.

[0100] The upper electrode 490 is also called a gate electrode. The upper electrode 490 includes the materials and structures exemplified as the materials of the gate electrode 290 in Fig. 6. For example, the upper electrode 490 includes a metal, a metal nitride, a metal carbide, and / or polysilicon and has a multi-layer structure.

[0101] The insulating layer 420 is a layer for suppressing or preventing electrical leakage, and includes a dielectric material. The insulating layer 420 includes a plurality of material layers having different dielectric constants. The insulating layer 420 includes SiO, AlO, HfO, ZrO, LaO, YO, MgO, or a two-dimensional insulator. As the two-dimensional insulator, a material such as h-BN (hexagonal boron nitride) may be used. The material of the insulating layer 420 is not limited thereto.

[0102] The electronic device 400 is also a logic transistor that utilizes the antiferroelectric thin film structure 150 for domain switching operations.

[0103] The anti-ferroelectric material included in the anti-ferroelectric thin film structure 150 includes ferroelectric domains in which electric dipoles are aligned, and in the absence of an external electric field, the remnant polarization exhibits a value of 0 or close to 0. When an external electric field is applied, the polarization direction of the anti-ferroelectric material can be switched.

[0104] The antiferroelectric thin film structure 150 according to the embodiment is made of HfO 2and includes a dielectric layer 120 exhibiting an antiferroelectric phase, and an insertion layer 130 inserted in the dielectric layer 120, i.e., disposed between the first dielectric layer 121 and the second dielectric layer 122. As a result, the antiferroelectric thin film structure 150 has a wide range in which it exhibits substantially non-hysteresis behavior characteristics in a polarization change caused by an external electric field. In other words, the antiferroelectric thin film structure 150 exhibits almost no hysteresis characteristics during a domain switching operation.

[0105] FIG. 8 is a cross-sectional view showing a schematic configuration of an electronic device according to still another embodiment.

[0106] Like the electronic device 400 in FIG. 7, the electronic device 500 of this embodiment is also a logic transistor that utilizes the antiferroelectric thin film structure 150 for domain switching operation.

[0107] The electronic device 500 includes a semiconductor substrate 510 and an antiferroelectric thin film structure 150 disposed on the semiconductor substrate 510. An insulating layer 520 is provided between the semiconductor substrate 510 and the antiferroelectric thin film structure 150, and a conductive layer 530 is provided between the insulating layer 520 and the antiferroelectric thin film structure 150. An upper electrode 590 is disposed on the antiferroelectric thin film structure 150. The upper electrode 590 is also called a gate electrode.

[0108] The semiconductor substrate 510 includes a source SR, a drain DR, and a channel CH electrically coupled to the source SR and the drain DR, and is similar to the semiconductor substrate 410 of FIG.

[0109] The conductive layer 530 disposed between the antiferroelectric thin film structure 150 and the insulating layer 520 can be set to a material that provides an appropriate tensile stress at the interface with the dielectric layer 120 and enables the dielectric layer 120 to have an antiferroelectric phase. The conductive layer 530 is made of, for example, Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, T. Contains e, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, or U.

[0110] In some embodiments, the conductive layer 530 is embodied as a floating gate, and the electronic device 500 is also a floating gate transistor (FGT). For example, the electronic device 500 may be configured to store (e.g., trap) charge and / or discharge charge from the conductive layer 530. In some embodiments, if negative charge is stored in the conductive layer 530, current flow is prevented or mitigated when a charge is applied to the top electrode 590. In some embodiments, the electronic device 500 may act as a charge (and / or data) storage cell, such as an erasable programmable read-only memory (EPROM) and / or an electrically erasable programmable read-only memory (EEPROM).

[0111] 9 and 10 are conceptual diagrams that show schematic element architectures applied to electronic devices according to the embodiments.

[0112] Referring to FIG. 9, the electronic device architecture 1000 includes a memory unit 1010, an arithmetic logic unit (ALU) 1020, and a control unit 1030. The memory unit 1010, the ALU 1020, and the control unit 1030 may be electrically connected to each other. For example, the electronic device architecture 1000 may be realized by one chip including the memory unit 1010, the ALU 1020, and the control unit 1030. Specifically, the memory unit 1010, the ALU 1020, and the control unit 1030 may be interconnected on-chip by metal lines and directly communicate with each other. The memory unit 1010, the ALU 1020, and the control unit 1030 may be monolithically integrated on one substrate to form one chip. An input / output device 2000 may be connected to the electronic device architecture (chip) 1000. Also, the memory unit 1010 may include both a main memory and a cache memory. Such an electronic device architecture (chip) 1000 may also be an on-chip memory processing unit.

[0113] The memory unit 1010, the ALU 1020 and / or the control unit 1030 each independently include electronic elements utilizing the antiferroelectric thin film structures described above. Such electronic elements may be logic transistors or capacitors.

[0114] 10, a cache memory 1510, an ALU 1520, and a control unit 1530 constitute a central processing unit (CPU) 1500, and the cache memory 1510 is a static random access memory (SRAM). A main memory 1600 and an auxiliary storage 1700 are provided separately from the CPU 1500, and an input / output element 2500 is also provided. The main memory 1600 is also a dynamic random access memory (DRAM), and may include an electronic element, such as a capacitor, that utilizes the above-mentioned antiferroelectric thin film structure.

[0115] In some cases, an electronic device architecture may be embodied in a form in which computing unit devices and memory unit devices are adjacent to each other on one chip without dividing the sub-units.

[0116] The above-mentioned antiferroelectric thin film structure and electronic device including the same have been described based on the embodiments shown in the drawings, but they are merely illustrative, and a person having ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the disclosed embodiments should be considered from an explanatory perspective, not a limiting perspective. The scope of the present specification is set forth in the claims, not the above description, and all differences within the scope equivalent thereto should be interpreted as being included in the present invention. [Explanation of symbols]

[0117] 13 Bit Line Structure 14 Element isolation layer 15 Interlayer insulating film 16 Etch stop layer 20 Contact 20' Contact Structure 100, 300, 400, 500 Electronic elements 101 Capacitor 110 Lower electrode 120 Dielectric layer 121 First dielectric layer 122 Second dielectric layer 130 Insertion Layer 150 Antiferroelectric thin film structures 190, 490, 590 upper electrode 200 Transistors 210, 410, 510 Semiconductor substrate 210ab 1st source / drain 210ab' 2nd source / drain 220 Gate insulating layer 230 Gate Stack 290 Gate electrode 420, 520 Insulation layer 530 Conductive Layer 1000 Electronic Element Architecture 1010 Memory Unit 1020, 1520 ALU 1030, 1530 control unit 1500 CPU 1510 Cache Memory 1600 Main memory 1700 Auxiliary Storage 2000, 2500 input / output elements

Claims

1. Hafnium oxide (HfO ２ a dielectric layer including the dielectric layer and exhibiting an antiferroelectric phase; an insertion layer inserted within the dielectric layer and including an oxide; The oxide contained in the insertion layer is M ｘ O ｙ It is expressed as, M is Al, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, or Lu; The oxygen ratio of the oxide is hafnium oxide (HfO ２ ) or less of the oxygen ratio, The composition of the dielectric layer is Hf （１－ｘ） Zr ｘ O ２ , 0.5≦x≦0.

8.

2. The thickness of the insertion layer is 2. The antiferroelectric thin film structure of claim 1, which is greater than 0% and less than or equal to 50% of the total thickness of said antiferroelectric thin film structure.

3. The dielectric layer is A first dielectric layer located on the upper side of the insertion layer and a second dielectric layer located on the lower side of the insertion layer, 2. The antiferroelectric thin film structure of claim 1, wherein the thickness of said first dielectric layer and said second dielectric layer is greater than zero.

4. A lower electrode; an antiferroelectric thin film structure according to any one of claims 1 to 3 disposed on said lower electrode; and an upper electrode disposed on said antiferroelectric thin film structure.

5. The lower electrode is 5. The electronic device of claim 4, comprising a metal, a metal nitride, a metal oxide, or a combination thereof.

6. The lower electrode is Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, C The electronic device according to claim 5, comprising e, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, or U.

7. The oxide contained in the insertion layer is M ｘ O ｙ It is expressed as, 5. The electronic device of claim 4, wherein M is Al, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, or Lu.

8. The thickness of the insertion layer is 5. The electronic device of claim 4, wherein the thickness of the antiferroelectric thin film structure is more than 0% and not more than 50% of the total thickness of the antiferroelectric thin film structure.

9. The electronic device of claim 4 , further comprising a transistor electrically connected to the bottom electrode.

10. A semiconductor substrate; An antiferroelectric thin film structure according to any one of claims 1 to 3, disposed on the semiconductor substrate; and an upper electrode disposed on said antiferroelectric thin film structure.

11. The oxide contained in the insertion layer is M ｘ O ｙ It is expressed as, 11. The electronic device of claim 10, wherein M is Al, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, or Lu.

12. The thickness of the insertion layer is 11. The electronic device of claim 10, wherein the thickness of the antiferroelectric thin film structure is more than 0% and not more than 50% of the total thickness of the antiferroelectric thin film structure.

13. 11. The electronic device of claim 10, further comprising an insulating layer disposed between said semiconductor substrate and said antiferroelectric thin film structure.

14. 14. The electronic device of claim 13, further comprising a conductive layer disposed between said antiferroelectric thin film structure and said insulating layer.

15. 15. The electronic device of claim 14, wherein the conductive layer comprises Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, or U.

16. the semiconductor substrate includes a source region, a drain region, and a channel region located between the source region and the drain region; The electronic device of claim 10 , wherein the antiferroelectric thin film structure is disposed over the channel region.

17. so that an electric dipole is formed at the interface between the dielectric layer and the insertion layer. The electronic device of claim 10 , wherein the dielectric layer and the insertion layer differ from each other in at least one of a charge, a partial charge, and an asymmetric charge.

18. A memory cell comprising a charge storage element comprising an antiferroelectric thin film structure according to any one of claims 1 to 3.

19. 20. The memory cell of claim 18, wherein the charge storage element is a capacitor or a floating gate.

20. 20. An electronic device comprising a memory cell according to claim 18.

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