Display device

Abstract

To provide a new gate driving mechanism for supplying gate signals.SOLUTION: A display device comprises: a display panel having subpixels arrayed in a matrix, gate lines extending in a row direction, and data lines extending in a column direction; a first gate driving portion that supplies gate signals for activating a subpixel of a first color to the subpixel of the first color through first gate lines of the gate lines; a second gate driving portion that supplies gate signals for activating a subpixel of a second color to the subpixel of the second color through second gate lines of the gate lines; a data driving portion that supplies data signals to the subpixels through the data lines; and a timing control portion that controls the first gate driving portion, the second gate driving portion, and the data driving portion. The subpixel includes a first subpixel of the first color and a second subpixel of the second color that share a first data line in a first row. The timing control portion controls the first gate driving portion independently from the second gate driving portion to consecutively supply the gate signals to the subpixel of the first color through the first gate lines.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a display device. [Background technology]

[0002] Patent Document 1 discloses a display device using double rate driving (DRD) in which two sub-pixels share one data line. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Korean Patent Publication No. 10-2020-0016100 Summary of the Invention [Problem to be solved by the invention]

[0004] The display device described in Patent Document 1 may be insufficient in terms of supplying gate signals to sub-pixels.

[0005] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a novel gate drive mechanism for supplying gate signals to sub-pixels. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a display panel having a plurality of sub-pixels arranged in a matrix, a plurality of gate lines extending in a row direction, and a plurality of data lines extending in a column direction; a first gate driver supplying a plurality of gate signals to the sub-pixels of a first color among the plurality of sub-pixels via a plurality of first gate lines among the plurality of gate lines to activate the sub-pixels of a first color among the plurality of sub-pixels; a second gate driver supplying a plurality of gate signals to the sub-pixels of a second color among the plurality of sub-pixels via a plurality of second gate lines among the plurality of gate lines to activate the sub-pixels of a second color among the plurality of sub-pixels; and A display device is provided, comprising: a data driver that supplies a plurality of data signals corresponding to the luminance of the plurality of sub-pixels to the plurality of sub-pixels; and a timing control unit that controls the first gate driver, the second gate driver, and the data driver, wherein the plurality of sub-pixels include a first sub-pixel of the first color and a second sub-pixel of the second color that share a first data line of the plurality of data lines in a first row, and the timing control unit controls the first gate driver independently of the second gate driver so as to continuously supply the gate signals to the sub-pixels of the first color via the plurality of first gate lines. Effect of the Invention

[0007] According to the present invention, it is possible to provide a gate drive mechanism suitable for a display device using a DRD. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a schematic configuration of a display device according to a first embodiment. [Diagram 2] 3 is an equivalent circuit diagram of a sub-pixel according to the first embodiment. FIG. [Diagram 3] FIG. 1 is a plan view showing a schematic configuration of a display panel according to a first embodiment. [Figure 4] 2 is a block diagram showing a schematic configuration of a timing control unit according to the first embodiment. FIG. [Diagram 5]2 is a block diagram showing a schematic configuration of a gate driver according to the first embodiment. FIG. [Figure 6] FIG. 2 is a circuit diagram showing connections between stages included in a first shift register and clock wiring according to the first embodiment. [Figure 7] FIG. 4 is a circuit diagram showing connections between stages included in a second shift register and clock wiring according to the first embodiment. [Figure 8] FIG. 2 is a circuit diagram showing connections between a stage included in a first shift register and a stage included in a second shift register, and clock wiring, according to the first embodiment. [Figure 9] 4 is a diagram showing the correspondence between the signal output terminals of the first GIP and the gate lines and the signal output terminals of the second GIP according to the first embodiment. FIG. [Figure 10] FIG. 11 is a diagram showing an example of transition between an on state and a hold state of a first GIP and a second GIP according to the first embodiment. [Figure 11] FIG. 11 is a diagram showing another example of transition between the on state and the hold state of the first GIP and the second GIP according to the first embodiment. [Figure 12] 3 is a block diagram showing a schematic configuration of a data driver according to the first embodiment. FIG. [Figure 13] 2 is a block diagram showing a schematic configuration of a similarity determination unit according to the first embodiment. FIG. [Figure 14] FIG. 2 is a block diagram showing a schematic configuration of a scheduler according to the first embodiment. [Figure 15] 3 is a block diagram showing a schematic configuration of a data selection unit according to the first embodiment. FIG. [Figure 16] 4 is a table showing an example of input to a scheduler according to the first embodiment. [Figure 17] 4 is a table showing an example of signals input to a data selection unit according to the first embodiment. [Figure 18] 4 is a table showing an example of input to a scheduler according to the first embodiment. [Figure 19] 4 is a table showing an example of signals input to a data selection unit according to the first embodiment. [Figure 20]4 is an example of an image displayed on the display device according to the first embodiment. [Figure 21] 3 is a schematic diagram showing the order in which sub-pixels of the display device according to the first embodiment are scanned. FIG. [Figure 22] 4 is a timing chart showing gate signals applied to gate lines of the display device according to the first embodiment. FIG. [Diagram 23] 3 is a schematic diagram showing the order in which sub-pixels of the display device according to the first embodiment are scanned. FIG. [Figure 24] 4 is a timing chart showing gate signals applied to gate lines of the display device according to the first embodiment. FIG. [Diagram 25] 3 is a schematic diagram showing the order in which sub-pixels of the display device according to the first embodiment are scanned. FIG. [Figure 26] 4 is a timing chart showing gate signals applied to gate lines of the display device according to the first embodiment. FIG. [Figure 27] 4 is a graph showing the relationship between the scanning time of the display device according to the first embodiment and the row of the sub-pixel to which the data signal is written. [Figure 28] FIG. 11 is a block diagram showing a schematic configuration of a similarity determination unit according to the second embodiment. [Figure 29] FIG. 11 is a block diagram showing a schematic configuration of a learning unit according to a second embodiment. [Diagram 30] 13 is a graph showing an adjusted threshold value according to the second embodiment. [Diagram 31] FIG. 11 is a block diagram showing a schematic configuration of a similarity determination unit according to the third embodiment. [Diagram 32] 13 is an example of an image displayed on the display device according to the third embodiment. [Diagram 33] 13 is a table showing an example of input to a scheduler according to the third embodiment. [Diagram 34] FIG. 11 is a schematic diagram showing the order in which sub-pixels of a display device according to a third embodiment are scanned. [Diagram 35] FIG. 11 is a timing chart showing gate signals applied to gate lines of a display device according to a third embodiment. [Diagram 36]13 is a table showing examples of an input register selection signal, an input enable signal, and an output register selection signal input to a data selection unit according to the fourth embodiment. [Figure 37] FIG. 13 is a block diagram showing a schematic configuration of a scheduler according to a fifth embodiment. [Figure 38] FIG. 13 is a block diagram showing a schematic configuration of a timing control unit according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Elements having common functions are designated by the same reference numerals throughout the drawings, and duplicated descriptions may be omitted or simplified.

[0010] [First embodiment] 1 is a block diagram showing a schematic configuration of a display device 10 according to the present embodiment. The display device 10 according to the present embodiment is an organic light-emitting diode display device, but is not limited thereto. For example, the display device 10 according to the present invention may be a liquid crystal display device. The display device 10 includes a display panel 100, a gate driver 200, a data driver 300, a power supply 400, and a timing controller 500.

[0011] The display panel 100 forms a display image of the display device 10. The display panel 100 includes a plurality of sub-pixels P arranged in a matrix in each pixel region defined by the intersection of gate lines GL1 to GLn extending in the row direction from a gate driver 200 and data lines DL1 to DLm (m, n are positive integers, the same applies below) extending in the column direction from a data driver 300. A pair of adjacent sub-pixels along each of the gate lines GL1 to GLn are arranged to share one of the data lines DL1 to DLm.

[0012] The gate driver 200 outputs gate signals to each of the gate lines GL1 to GLn in an order determined based on the gate control signal GCS. The gate driver 200 includes internal circuits such as a level shifter, a shift register, a delay circuit, and a flip-flop, and continuously generates control signals such as a gate start pulse signal GSP, a gate shift clock signal GSC, and a gate output enable signal GOE in response to the gate control signal GCS. The gate start pulse signal GSP controls the timing of the start of operation of the gate driver integrated circuit included in the gate driver 200. The gate shift clock signal GSC is a clock signal commonly input to the gate driver integrated circuits, and controls the shift timing of the scanning signal (gate signal). The gate output enable signal GOE specifies timing information of the gate driver integrated circuit. The gate driver 200 continuously generates gate signals by shifting the gate start pulse signal GSP in response to the gate shift clock signal GSC. The gate driver 200 also supplies the generated gate signals to each of the gate lines GL1 to GLn. Gate signals supplied via gate lines GL1 to GLn are used to activate each of a plurality of sub-pixels included in the display panel 100. The gate driver 200 controls the output width of the gate signal by a data enable signal DE whose output width is modulated by the timing controller 500 and a gate output enable signal GOE whose output width is changed by the data enable signal DE. The arrangement of the gate driver 200 is not limited to the form shown in FIG. 1. For example, the gate driver 200 may be arranged in non-display areas on both ends of the display panel 100.

[0013] The data driver 300 receives image data R'G'B'W' aligned by the timing controller 500 from the timing controller 500 for each row. The data driver 300 receives a data control signal DSC including a source start pulse signal SSP, a source shift clock signal SSC, and a source output enable signal SOE from the timing controller 500. The source start pulse signal SSP controls the timing of starting data sampling of the source driver integrated circuits included in the data driver 300. The source shift clock signal SSC is a clock signal that controls the timing of data sampling in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the signal from the data driver 300. The data driver 300 aligns image data RGBW using the data control signal DSC and converts it into an analog data voltage for each row. Note that the present invention can be applied not only to a display device whose image data format is RGBW, but also to an RGB display device that does not include a white subpixel and an RGBY display device that includes a yellow subpixel. Although RGBW is used in the following description, the present invention is not limited thereto.

[0014] Specifically, the data driver 300 samples the image data R'G'B'W' aligned in response to the source shift clock signal SSC for each row in each horizontal period in which the gate signal is supplied to each of the gate lines GL1 to GLn in response to the source output enable signal SOE, and converts the data into a data voltage DATA. The data driver 300 supplies the data voltage DATA, which is an analog signal, to each of the sub-pixels included in the display panel 100 via the data lines DL1 to DLm. The conversion period to the data voltage and the output period of the data driver 300 can be changed in response to the data enable signal DE whose output width is modulated by the timing control unit 500 and the source output enable signal SOE whose output width is changed by the data enable signal DE. The data driver 300 generates data voltages so that sub-pixels of the same color arranged in the data line direction continuously emit light for a predetermined number of rows, and continuously supplies the data voltages to each of the sub-pixels included in the display panel 100 via the data lines DL1 to DLm in synchronization with the output timing of the gate signal. The multiple data voltages supplied to the multiple sub-pixels correspond to the luminance of the multiple pixels, respectively.

[0015] The power supply 400 supplies a high-potential side power supply voltage VDD and a low-potential side power supply voltage VSS via a power supply line to each subpixel P. The power supply 400 also supplies a compensation voltage Vref to each subpixel P via a compensation power supply line CPL.

[0016] The timing control unit 500 generates signals for driving the sub-pixels P of the display panel 100 by double rate driving (DRD). The timing control unit 500 aligns image data RGBW so that sub-pixels of the same color arranged along the direction of the data lines DL1 to DLm emit light for a predetermined number of rows. The timing control unit 500 also aligns the input image data RGBW and then outputs the data to the data driver 300, thereby operating the sub-pixels P in different driving sequences for each frame and causing the sub-pixels of the same color to emit light continuously for a predetermined number of rows.

[0017] Furthermore, the timing control unit 500 generates a gate control signal GCS and a data control signal DSC using signals such as a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync. In order to drive the display device 10 by the DRD method, the timing control unit 500 transmits the generated gate control signal GCS to the gate driver 200 and the generated data control signal DSC to the data driver 300. The timing control unit 500 can generate the gate control signal GCS and the data control signal DSC so that sub-pixels P of the same color arranged along the direction of the data lines DL1 to DLm are caused to emit light continuously for a predetermined number of rows by the DRD method.

[0018] The connection relationship of the gate lines GL1 to GLn, the data lines DL1 to DLm, and the sub-pixels P included in the display device 10 will be described in detail with reference to FIG. 2. FIG. 2 is an equivalent circuit diagram of the sub-pixels P according to the present embodiment. Each of the sub-pixels P includes an organic light-emitting diode OLED, a driving element DT, a first switch element T1, a second switch element T2, a first capacitor C1, and a second capacitor C2. The sub-pixels P are connected to the data line DL, the gate line GL, a high-potential side power supply voltage VDD, a low-potential side power supply voltage VSS, and a compensation power supply line CPL. In the present embodiment, the organic light-emitting diode OLED has any one of red (R), green (G), blue (B), and white (W) emitting light constituting a pixel surface. The anode of the organic light-emitting diode OLED is connected to the power supply voltage VDD via the driving element DT, and the cathode of the organic light-emitting diode OLED is connected to the power supply voltage VSS.

[0019] The driving element DT, the first switch element T1 and the second switch element T2 may be composed of MOSFETs (metal oxide semiconductor field effect transistors). The gate of the driving element DT is connected to the source of the first switch element T1 via the first node N1, the drain of the driving element DT is connected to the power supply voltage VDD via the third node N3, and the source of the driving element DT is connected to the anode of the organic light emitting diode OLED via the second node N2. The gate of the first switch element T1 is connected to the gate line GL, and the drain of the first switch element T1 is connected to the data line DL. The first capacitor C1 is connected between the first node N1 and the second node N2. The gate of the second switch element T2 is connected to the gate line GL, the drain of the second switch element T2 is connected to the second node N2, and the source of the second switch element T2 is connected to the compensation power supply line CPL. The second switch element T2 supplies the compensation voltage Vref input via the compensation power line CPL to the second node N2 in response to the gate signal from the gate line GL, thereby compensating for the potential of the drain terminal of the driving element DT, which is the output terminal of the data voltage. A second capacitor C2 is connected to the compensation power line CPL to stabilize the compensation voltage Vref.

[0020] The level of the gate line GL determines whether the organic light emitting diode OLED is driven or not, and when the organic light emitting diode OLED is driven, its brightness is determined by the voltage of the data line DL. When the organic light emitting diode OLED is scanned (driven), the level of the gate line GL becomes a high level, and otherwise the level of the gate line GL becomes a low level. When the level of the gate line GL becomes a high level, the first switch element T1 is turned on, and a voltage based on the voltage of the data line DL is charged in the first capacitor C1. When the voltage of the first capacitor C1 exceeds the on threshold of the driving element DT, the driving element DT is turned on. The driving element DT in the on state supplies a drain current corresponding to the gate voltage, that is, the potential difference between the voltage of the data line DL and the compensation voltage Vref, from the power supply voltage VDD to the organic light emitting diode OLED. The organic light emitting diode OLED emits light in response to this drain current. The first capacitor C1 functions as a so-called storage capacitor, and holds the gate-source voltage of the driving element DT in a certain scanning frame until the next scanning frame, thereby maintaining the light emitting state or the off state of the organic light emitting diode OLED.

[0021] FIG. 3 is a plan view showing a schematic configuration of a display panel 100 according to the present embodiment. A pixel surface having a plurality of subpixels P arranged two-dimensionally is formed on the display panel 100. The plurality of subpixels P include a green subpixel G, a red subpixel R, a white subpixel W, and a blue subpixel B. The subpixels of each color are arranged in each pixel region defined by the intersection of gate lines GL1 to GLn and data lines DL1 to DLm. The subpixels P of each color are arranged in a column along the data line DL. As an example, the green subpixel G and the red subpixel R are arranged adjacent to each other, and one data line DL1 is provided between the green subpixel G and the red subpixel R. A pair of adjacent subpixels, the green subpixel G and the red subpixel R, in each row are connected to the same data line DL1 via the first switch element T1 of each subpixel. That is, the pair of subpixels, the green subpixel G and the red subpixel R, share one data line DL1. Similarly, the white subpixel W and the blue subpixel B are arranged adjacent to each other, and one data line DL2 is provided between the white subpixel W and the blue subpixel B. In each row, a pair of adjacent subpixels, the white subpixel W and the blue subpixel B, are connected to the same data line DL2 via the first switch element T1 of each subpixel. That is, a pair of subpixels, the white subpixel W and the blue subpixel B, share one data line DL2. By arranging data lines for all subpixels included in the display panel 100 as described above, the number of data lines DL1 to DLm arranged in the display panel 100 is half the total number of columns of subpixels.

[0022] The red subpixel R and the white subpixel W are arranged adjacent to each other, and a compensation power supply line CPL is provided between the red subpixel R and the white subpixel W. The subpixels of each color are connected to the compensation power supply line CPL via the second switch element T2 of each subpixel. The gates of the first switch element T1 and the second switch element T2 included in the red subpixel R and the white subpixel W of each row are connected to a first gate line among the gate lines GL1 to GLn, respectively. The gates of the first switch element T1 and the second switch element T2 included in the green subpixel G and the blue subpixel B arranged in the same row are connected to a second gate line different from the first gate line among the gate lines GL1 to GLn, respectively. For the subpixels of the other rows, two gate lines different from the first gate line and the second gate line are arranged in a similar connection relationship. By arranging the gate lines for all the subpixels included in the display panel 100 as described above, the number of gate lines GL1 to GLn arranged in the display panel 100 is double the total number of the rows of the subpixels. The arrangement order of the green subpixel G, the red subpixel R, the white subpixel W, and the blue subpixel B is not limited to that shown in FIG. 3 and can be changed as appropriate. In the present embodiment, the green subpixel G and the white subpixel W are arranged in odd-numbered columns, and the red subpixel R and the blue subpixel B are arranged in even-numbered columns, but the arrangement of the subpixels is not limited to this and can be changed as appropriate. In the present embodiment, the green subpixel G arranged in the odd-numbered columns and the red subpixel R arranged in the even-numbered columns share one data line DL1, and the white subpixel W arranged in the odd-numbered columns and the blue subpixel B arranged in the even-numbered columns share one data line DL2, but the pixel columns that share the data line are not limited to this and can be changed as appropriate. For example, the green subpixel G and the white subpixel W arranged in the odd-numbered columns can be configured to share one data line DL1, and the red subpixel R and the blue subpixel B arranged in the even-numbered columns can be configured to share one data line DL2.

[0023] 4 is a block diagram showing a schematic configuration of the timing control section according to this embodiment. The timing control section 500 includes a signal modulation section 510, a row memory section 520, a data control signal generation section 530, a gate control signal generation section 540, a similarity determination section 550, and a scheduler 560.

[0024] The signal modulation unit 510 modulates the pulse width of the data enable signal DE. For example, when scanning sub-pixels of the same color consecutively, the signal modulation unit 510 generates a modulated data enable signal tDE, A separate charging period can be set for each sub-pixel. The signal modulation unit 510 transmits a modulated data enable signal tDE to the row memory unit 520, the data control signal generation unit 530, and the gate control signal generation unit 540.

[0025] The row memory unit 520 stores image data RGBW in row units. For example, the row memory unit 520 stores image data RGBW(x) of the xth row (x is a positive integer, the same applies below). The row memory unit 520 transmits image data RGBW(x-1) of the (x-1)th row to the similarity determination unit 550. The row memory unit 520 aligns the image data RGBW based on the modulated data enable signal tDE received from the signal modulation unit 510. The row memory unit 520 transmits the aligned image data R'G'B'W' to the data driver 300.

[0026] The data control signal generator 530 generates a data control signal DSC using signals such as the modulated data enable signal tDE, the dot clock DCLK, and the vertical synchronization signal Vsync. Specifically, the data control signal generator 530 modulates the output width of the source output enable signal SOE using the modulated data enable signal tDE to adjust the charging period for each sub-pixel. In addition, the data control signal generator 530 transmits the generated source start pulse signal SSP and source shift clock signal SSC to the data driver 300.

[0027] The gate control signal generator 540 generates the gate control signal GCS using signals such as the modulated data enable signal tDE, the dot clock DCLK, and the horizontal synchronization signal Hsync. Specifically, the gate control signal generator 540 modulates the output width of the gate output enable signal GOE using the modulated data enable signal tDE to adjust the supply period of the gate signal for the sub-pixel. In addition, the gate control signal generator 540 transmits the generated source start pulse signal SSP and source shift clock signal SSC to the data driver 300.

[0028] The similarity determination unit 550 determines the similarity between two rows of image data and transmits the determination result RES to the scheduler 560. For example, the similarity determination unit 550 receives the (x-1)th row of image data RGBW(x-1) from the row memory unit 520 and determines whether it is similar to the xth row of image data RGBW(x). For example, the similarity determination unit 550 outputs 1 as the determination result RES when it determines that the image data between the two rows are similar to each other. On the other hand, the similarity determination unit 550 outputs 0 as the determination result RES when it determines that the image data between the two rows are not similar to each other.

[0029] The scheduler 560 generates a gate line designation signal GL_Num designating the number of the gate line GL to transmit the gate signal based on the determination result RES received from the similarity determination unit 550. The gate line designation signal GL_Num is transmitted to the modulation unit 510 to generate a modulated data enable signal tDE. The scheduler 560 also transmits a register selection signal RSS to the data driver 300 to designate a register in which the image data R'G'B'W' transmitted from the row memory unit 520 should be stored. The data driver 300 stores the image data R'G'B'W' in the designated register based on the received register selection signal RSS.

[0030] 5 is a block diagram showing a schematic configuration of the gate driver 200 according to this embodiment. The gate driver 200 includes a first level shifter 211, a second level shifter 212, first shift registers 221 and 222, and second shift registers 231 and 232.

[0031] The first level shifter 211 and the second level shifter 212 shift the TTL (Transistor-Transistor-Logic) level of the clock signal CLK1 input from the timing control unit 500. Specifically, the first level shifter 211 and the second level shifter 212 generate a signal for switching between a gate high voltage and a gate low voltage in order to transition a transistor included in the display panel 100 between an on state and an off state. The first level shifter 211 transmits the generated signal to the first shift register 221. The second level shifter 212 transmits the generated signal to the first shift register 222. In addition, the first level shifter 211 shifts the TTL level of the clock signal CLK2 input from the timing control unit 500. Specifically, the first level shifter 211 and the second level shifter 212 generate a signal for switching between a gate high voltage and a gate low voltage in order to transition a transistor included in the display panel 100 between an on state and an off state. The first level shifter 211 transmits the generated signal to the second shift register 231. The second level shifter 212 transmits the generated signal to the second shift register 232.

[0032] Each of the first shift registers 221 and 222 includes a plurality of stages. Each of the plurality of stages includes a Q node, a Qb node, a pull-up element, and a pull-down element. The first shift registers 221 and 222 are arranged in a gate-in-panel (GIP) manner in a non-display area outside the display area 110 of the display panel 100. For example, the first shift register 221 can be arranged in a non-display area adjacent to one short side (the left short side in FIG. 5) of the display area 110 in a plan view, as shown in FIG. 5. The first shift register 222 can be arranged in a non-display area adjacent to the other short side (the right short side in FIG. 5) of the display area 110 in a plan view, as shown in FIG. 5. The gate lines GL from the first shift register 221 and the gate lines GL from the first shift register 222 can have a structure in which they are connected to each other.

[0033] The first shift register 221 supplies a gate signal to the gate line GL based on a signal received from the first level shifter 211. The first shift register 222 supplies a gate signal to the gate line GL based on a signal received from the second level shifter 212. The first shift registers 221 and 222 receive a gate start signal VST1 from the timing control unit 500. The first shift registers 221 and 222 sequentially generate carry signals based on the received gate start signal VST1. The first shift registers 221 and 222 supply the generated carry signals as gate start signals to any of a plurality of stages included in the first shift registers 221 and 222. The first shift registers 221 and 222 receive a reset signal RST1 from the timing control unit 500 at the start of scanning one frame or the end of scanning one frame. By resetting the Q node via the reset signal RST1, the voltages of the Q node and the QB node of the first shift registers 221 and 222 can be stably maintained.

[0034] Each of the second shift registers 231 and 232 includes a plurality of stages. Each of the plurality of stages includes a Q node, a Qb node, a pull-up element, and a pull-down element. The second shift registers 231 and 232 are arranged in a gate-in-panel (GIP) manner in a non-display area outside the display area 110 of the display panel 100. For example, as shown in FIG. 5, the second shift register 231 can be arranged in a non-display area adjacent to one short side (the left short side in FIG. 5) of the display area 110 in a plan view so as to overlap with the first shift register 221. Also, as shown in FIG. 5, the second shift register 232 can be arranged in a non-display area adjacent to the other short side (the right short side in FIG. 5) of the display area 110 in a plan view so as to overlap with the first shift register 222. Also, the second shift registers 231 and 232 can be arranged in the same area as the first shift registers 221 and 222, respectively. That is, the gate driver 200 according to this embodiment may be configured such that the distance from the second shift registers 231 and 232 to the display area 110 is the same as the distance from the first shift registers 221 and 222 to the display area 110. Also, the gate lines GL from the second shift register 231 may be connected to the gate lines GL from the second shift register 232.

[0035] The second shift register 231 supplies a gate signal to the gate line GL based on the signal received from the first level shifter 211. The second shift register 232 supplies a gate signal to the gate line GL based on the signal received from the second level shifter 212. The second shift registers 231 and 232 receive a gate start signal VST2 from the timing control unit 500. Here, the timing at which the second shift registers 231 and 232 receive the gate start signal VST2 is different from the timing at which the first shift registers 221 and 222 receive the gate start signal VST1. The second shift registers 231 and 232 sequentially generate carry signals based on the received gate start signal VST2. The second shift registers 231 and 232 supply the generated carry signals as gate start signals to any of the multiple stages included in the second shift registers 231 and 232. The second shift registers 231 and 232 receive a reset signal RST2 from the timing control unit 500 at the start of scanning one frame or the end of scanning one frame. By resetting the Q node via the reset signal RST2, the voltages of the Q node and the QB node of the second shift registers 231 and 232 can be stably maintained. Here, the timing at which the second shift registers 231 and 232 receive the reset signal RST2 is different from the timing at which the first shift registers 221 and 222 receive the reset signal RST1. That is, the second shift registers 231 and 232 according to this embodiment operate independently of the first shift registers 221 and 222 in terms of the circuit configuration. Note that a common gate start signal can also be used as the gate start signal VST1 and the gate start signal VST2. However, when a common gate start signal is used, the stages of the shift registers wait in an ON state from when the gate start signal is input until the first clock is input. Therefore, from the viewpoint of operational stability, it is desirable to use the gate start signal VST1 and the gate start signal VST2, which are mutually independent signals.

[0036] 6 is a circuit diagram showing connections between stages included in the first shift registers 221 and 222 according to this embodiment and clock wiring. The first shift registers 221 and 222 include multiple stages. Each of the multiple stages includes a Q node, a Qb node, a pull-up element, and a pull-down element.

[0037] The pull-up elements of the first shift registers 221, 222 may be composed of transistors. The gates of the pull-up elements are electrically connected to the Q node. The sources or drains of the pull-up elements are electrically connected to the input terminal of the clock signal. The drains or sources of the pull-up elements are electrically connected to the source or drain of the pull-down element and the output terminal of the clock signal. The pull-up elements transition to an on state by the voltage of the Q node, and output the clock signal as a scanning signal (gate signal).

[0038] The pull-down elements of the first shift registers 221, 222 may be composed of transistors. The gates of the pull-up elements are electrically connected to the Qb node. The sources or drains of the pull-down elements are electrically connected to the drains or sources of the pull-up elements and the output terminals of the clock signals. The drains or sources of the pull-down elements are electrically connected to the low potential power supply GVSS. The pull-down elements transition to an on state by the voltage of the Qb node, and output the base voltage as a low level scan signal.

[0039] In each stage, when the pull-up element is in the on state, the pull-down element is in the off state. That is, when an on voltage that turns the pull-up element on is applied to the Q node, an off voltage that turns the pull-down element off is applied to the Qb node. This state is called the on state of the stage. Also, in each stage, when the pull-down element is in the on state, the pull-up element is in the off state. That is, when an on voltage that turns the pull-down element on is applied to the Qb node, an off voltage that turns the pull-up element off is applied to the Q node. This state is called the hold state of the stage.

[0040] The first stage STG1 including the Q(1) node and the Qb(1) node shown in FIG. 6 will be described below. The first shift registers 221, 222 receive a gate start signal VST1 from the Q(1) node, which indicates the start of the operation of the gate driver. The first stage STG1 includes three pull-up elements. The gate nodes of the three pull-up elements are commonly connected to the Q(1) node, and the three pull-up elements transition to an ON state by the voltage of the Q(1) node. The source or drain of the first pull-up element is connected to the input terminal of the carry shift clock signal CRCLK1, and the drain or source of the first pull-up element is connected to the output terminal C1 of the scan signal. Therefore, when the pull-up element transitions to an ON state by the voltage of the Q node, the carry shift clock signal CRCLK1 is output from the output terminal of the scan signal. The carry shift clock is a clock signal for generating a carry signal. The source or drain of the second pull-up element is connected to the input terminal of the scan shift clock signal SCCLK1, and the drain or source of the second pull-up element is connected to the output terminal S1 of the scan signal. Thus, when the pull-up element is transitioned to an on state by the voltage of the Q node, the scan shift clock signal SCCLK1 can be output from the output terminal of the scan signal. The scan shift clock signal is a clock signal for generating a scan signal having a pulse. For example, the scan shift clock signal SCCLK1 is a clock signal for generating a gate signal transmitted by the gate line GL1. The source or drain of the third pull-up element is connected to the input terminal of the scan shift clock signal SCCLK3, and the drain or source of the third pull-up element is connected to the output terminal S3 of the scan signal. Thus, when the pull-up element is transitioned to an on state by the voltage of the Q node, the scan shift clock signal SCCLK3 can be output from the output terminal of the scan signal. For example, the scan shift clock signal SCCLK3 is a clock signal for generating a gate signal transmitted by the gate line GL3.

[0041] The first stage STG1 also includes three pull-down elements. The gate nodes of the three pull-down elements are commonly connected to the Qb(1) node, and the three pull-down elements transition to an on-state by the voltage of the Qb(1) node. The drain or source of each of the three pull-down elements is connected to the low potential power supply GVSS, and the source or drain of each of the three pull-down elements is connected to the output terminals C1, S1, and S3 of the scan signal, respectively. Therefore, when the pull-down elements transition to an on-state by the voltage of the Qb node, a ground voltage as a low-level scan signal is output to the output terminals C1, S1, and S3, respectively.

[0042] The third stage STG3 including the Q(3) node and the Qb(3) node to the eleventh stage STG11 including the Q(11) node and the Qb(11) node shown in FIG. 6 may be configured in the same manner as the first stage STG1 described above. The Q(11) node included in the eleventh stage STG11 may be configured to receive a reset signal RST1. The first shift registers 221 and 222 may also be configured such that one Qb node is shared by two stages. For example, the Qb(1) node of the first stage STG1 and the Qb(3) node of the third stage STG3 may be configured as a first Qb common node (not shown), and the first stage STG1 and the third stage STG3 may be configured to share the first Qb common node. Similarly, the Qb(5) node of the fifth stage STG5 and the Qb(7) node of the seventh stage STG7 are configured as a second Qb common node (not shown), and the fifth stage STG5 and the seventh stage STG7 can be configured to share the second Qb common node. Similarly, the Qb(9) node of the ninth stage STG9 and the Qb(11) node of the eleventh stage STG11 are configured as a third Qb common node (not shown), and the ninth stage STG9 and the eleventh stage STG11 can be configured to share the third Qb common node. According to the above configuration, the area occupied by the arrangement of the Qb nodes is reduced. As a result, the circuit area occupied by the first shift registers 221 and 222 in the non-display area is reduced. Therefore, the bezel width of the display device 10 can be made smaller. Since the first shift registers 221 and 222 are shift registers independent of the second shift registers 231 and 232, the stages included in the first shift registers 221 and 222 do not share the Qb node with the stages included in the second shift registers 231 and 232.

[0043] 7 is a circuit diagram showing connections between the stages included in the second shift registers 231 and 232 according to this embodiment and clock wiring. The second shift registers 231 and 232 include multiple stages. Each of the multiple stages includes a Q node, a Qb node, a pull-up element, and a pull-down element.

[0044] The pull-up elements of the second shift registers 231, 232 may be composed of transistors. The gates of the pull-up elements are electrically connected to the Q node. The sources or drains of the pull-up elements are electrically connected to the input terminals of the clock signal. The drains or sources of the pull-up elements are electrically connected to the source or drains of the pull-down elements and the output terminals of the clock signal. The pull-up elements transition to an on state by the voltage of the Q node, and output the clock signal as a scanning signal.

[0045] The pull-down elements of the second shift registers 231, 232 may be composed of transistors. The gates of the pull-up elements are electrically connected to the Qb node. The sources or drains of the pull-down elements are electrically connected to the drains or sources of the pull-up elements and the output terminals of the clock signals. The drains or sources of the pull-down elements are electrically connected to the low-potential power supply GVSS. The pull-down elements transition to an on state by the voltage of the Qb node, and output the base voltage as a low-level scan signal.

[0046] In each stage, when the pull-up element is in the on state, the pull-down element is in the off state. That is, when an on voltage that turns the pull-up element on is applied to the Q node, an off voltage that turns the pull-down element off is applied to the Qb node. Also, in each stage, when the pull-down element is in the on state, the pull-up element is in the off state. That is, when an on voltage that turns the pull-down element on is applied to the Qb node, an off voltage that turns the pull-up element off is applied to the Q node.

[0047] The second stage STG2 including the Q(2) node and the Qb(2) node shown in FIG. 7 will be described below. The second shift registers 231 and 232 receive a gate start signal VST2 from the Q(2) node, which indicates the start of the operation of the gate driver. The gate start signal VST2 is a signal independent of the gate start signal VST1 applied to the first shift registers 221 and 222. The second stage STG2 includes three pull-up elements. The gate nodes of the three pull-up elements are commonly connected to the Q(2) node, and the three pull-up elements transition to an ON state by the voltage of the Q(2) node. The source or drain of the first pull-up element is connected to the input terminal of the carry shift clock signal CRCLK2, and the drain or source of the first pull-up element is connected to the output terminal C2 of the scan signal. Therefore, when the pull-up element transitions to an ON state by the voltage of the Q node, the carry shift clock signal CRCLK2 is output from the output terminal of the scan signal. The source or drain of the second pull-up element is connected to the input terminal of the scan shift clock signal SCCLK2, and the drain or source of the second pull-up element is connected to the output terminal S2 of the scan signal. Thus, when the pull-up element is transitioned to an on state by the voltage of the Q node, the scan shift clock signal SCCLK2 may be output from the output terminal of the scan signal. For example, the scan shift clock signal SCCLK2 is a clock signal for generating a gate signal transmitted by the gate line GL2. The source or drain of the third pull-up element is connected to the input terminal of the scan shift clock signal SCCLK4, and the drain or source of the third pull-up element is connected to the output terminal S4 of the scan signal. Thus, when the pull-up element is transitioned to an on state by the voltage of the Q node, the scan shift clock signal SCCLK4 may be output from the output terminal of the scan signal. For example, the scan shift clock signal SCCLK4 is a clock signal for generating a gate signal transmitted by the gate line GL4.

[0048] The second stage STG2 also includes three pull-down elements. The gate nodes of the three pull-down elements are commonly connected to the Qb(2) node, and the three pull-down elements transition to an on-state by the voltage of the Qb(2) node. The drain or source of each of the three pull-down elements is connected to the low potential power supply GVSS, and the source or drain of each of the three pull-down elements is connected to the output terminals C2, S2, and S4 of the scan signal, respectively. Therefore, when the pull-down elements transition to an on-state by the voltage of the Qb node, a ground voltage as a low-level scan signal is output to the output terminals C2, S2, and S4, respectively.

[0049] The fourth stage STG4 including the Q(4) node and the Qb(4) node to the twelfth stage STG12 including the Q(12) node and the Qb(12) node shown in FIG. 7 may be configured in the same manner as the second stage STG2 described above. The Q(12) node included in the twelfth stage STG12 may be configured to receive a reset signal RST2. The reset signal RST2 is a signal independent of the reset signal RST1 applied to the first shift registers 221 and 222. The second shift registers 231 and 232 may also be configured to share one Qb node between two stages. For example, the Qb(2) node of the second stage STG2 and the Qb(4) node of the fourth stage STG4 may be configured to be a fourth Qb common node (not shown), and the second stage STG2 and the fourth stage STG4 may be configured to share the fourth Qb common node. Similarly, the Qb(6) node of the sixth stage STG6 and the Qb(8) node of the eighth stage STG8 are configured as a fifth Qb common node (not shown), and the sixth stage STG6 and the eighth stage STG8 can be configured to share the fifth Qb common node. Similarly, the Qb(10) node of the tenth stage STG10 and the Qb(12) node of the twelfth stage STG12 are configured as a sixth Qb common node (not shown), and the tenth stage STG10 and the twelfth stage STG12 can be configured to share the sixth Qb common node. According to the above configuration, the area occupied by the arrangement of the Qb nodes is reduced. As a result, the circuit area in which the second shift registers 231 and 232 occupy the non-display area is reduced. Therefore, the bezel width of the display device 10 can be made smaller. Since the second shift registers 231 and 232 are shift registers independent of the first shift registers 221 and 222, the stages included in the second shift registers 231 and 232 do not share the Qb node with the stages included in the first shift registers 221 and 222.

[0050] FIG. 8 is a circuit diagram showing an example of connections between the stages included in the first shift registers 221 and 222 and the stages included in the second shift registers 231 and 232 and the clock wiring according to this embodiment.

[0051] As shown in FIG. 5, the second shift registers 231, 232 can be arranged so as to overlap the first shift registers 221, 222 in the non-display area of ​​the display panel 100 in a plan view. The first shift registers 221, 222 and the second shift registers 231, 232 can be implemented in a GIP format. For example, a case in which the first shift registers 221, 222 are implemented in the display panel 100 as the first GIP, and the second shift registers 231, 232 are implemented in the display panel as the second GIP will be described with reference to FIG. 8. In this example, the first GIP and the second GIP are arranged in the same circuit area sharing the same low potential power supply GVSS. Specifically, the second stage STG2 of the second GIP is arranged next to the third stage STG3 of the first GIP. The fifth stage STG5 of the first GIP and the fourth stage STG4 of the second GIP are arranged next to the fourth stage STG4 of the second GIP. In addition, the sixth stage STG6 of the second GIP is disposed next to the seventh stage STG7 of the first GIP. However, as described above, the first GIP and the second GIP are independent shift registers. Specifically, the first GIP and the second GIP do not share the input clock signals CRCLK and SCCLK. In addition, the first GIP receives a gate start signal VST1 and a reset signal RST1, and the second GIP receives a separate gate start signal VST2 and a reset signal RST2 that are independent from the gate start signal VST1 and the reset signal RST1, respectively. A carry signal input / output to the stage of the first GIP is transmitted to another stage of the first GIP, while a carry signal input / output to the stage of the first GIP is not transmitted to the stage of the second GIP. Similarly, a carry signal input / output to the stage of the second GIP is transmitted to another stage of the second GIP, while a carry signal input / output to the stage of the second GIP is not transmitted to the stage of the first GIP. That is, the first GIP is driven independently of the operation of the second GIP. Similarly, the second GIP is driven independently of the operation of the first GIP.

[0052] 9 is a diagram showing the correspondence between the signal output terminals of the first GIP and the second GIP and the gate lines according to this embodiment. According to this embodiment, the arrangement of the output terminals S1 to S16 of the scanning signals included in the first GIP and the second GIP does not correspond to the arrangement of the gate lines GL1 to GL16. That is, as shown in FIG. 9, the output line of the output terminal S3 of the first stage STG1 of the first GIP to the gate line GL3 intersects with the output line of the output terminal S2 of the second stage STG2 of the second GIP to the gate line GL2. In addition, the output line of the output terminal S5 of the third stage STG3 of the first GIP to the gate line GL5 intersects with the output line of the output terminal S2 of the second stage STG2 of the second GIP to the gate line GL2 and the output line of the output terminal S4 of the second stage STG2 of the second GIP to the gate line GL4. Also, the output line of the output terminal S7 of the third stage STG3 of the first GIP to the gate line GL7 crosses the output line of the output terminal S2 of the second stage STG2 of the second GIP to the gate line GL2, the output line of the output terminal S4 of the second stage STG2 of the second GIP to the gate line GL4, and the output line of the output terminal S6 of the fourth stage STG4 of the second GIP to the gate line GL6. Also, the output line of the output terminal S11 of the fifth stage STG5 of the first GIP to the gate line GL11 crosses the output line of the output terminal S10 of the sixth stage STG6 of the second GIP to the gate line GL10. Also, the output line of the output terminal S13 of the seventh stage STG7 of the first GIP to the gate line GL13 crosses the output line of the output terminal S10 of the sixth stage STG6 of the second GIP to the gate line GL10 and the output line of the output terminal S12 of the sixth stage STG6 of the second GIP to the gate line GL12. Furthermore, the output line of the output terminal S15 of the seventh stage STG7 of the first GIP to the gate line GL15 intersects with the output line of the output terminal S10 of the sixth stage STG6 of the second GIP to the gate line GL10, the output line of the output terminal S12 of the sixth stage STG6 of the second GIP to the gate line GL12, and the output line of the output terminal S14 of the eighth stage STG8 of the second GIP to the gate line GL14. That is, a straight line path connecting the output terminal of the gate signal supplied from the first GIP to the gate line corresponding to that output terminal can be configured to intersect with a straight line path connecting the output terminal of the gate signal supplied from the second GIP to the gate line corresponding to that output terminal.The output line from the output terminal S1 of the first stage STG1 of the first GIP to the gate line GL1 and the output line from the output terminal S9 of the fifth stage STG5 of the first GIP to the gate line GL9 do not intersect with the output line from the signal output terminal of the second GIP. Also, the output line from the output terminal S8 of the fourth stage STG4 of the second GIP to the gate line GL8 and the output line from the output terminal S16 of the eighth stage STG8 of the second GIP to the gate line GL16 do not intersect with the output line from the signal output terminal of the first GIP.

[0053] FIG. 10 is a diagram showing an example of transition between the on state and the hold state of the first GIP and the second GIP according to this embodiment. As described above, each stage included in the first GIP and the second GIP according to this embodiment is turned on or held according to the voltage applied to the pull-up element and the pull-down element. A stage in the hold state does not output a scan signal. On the other hand, a stage in the on state can output a scan signal. However, in order to prevent two or more scan signals or carry signals from being transmitted from the output terminal in the same clock, it is necessary to limit the number of stages in the on state. Specifically, for example, when the number of clocks input to the GIP is x, the number of stages in the on state must be less than 2x (x is a positive integer). The first GIP of this embodiment sequentially transitions the stages in the hold state to the on state via the carry signal. Also, the first GIP of this embodiment sequentially transitions the stages in the on state to the hold state via the carry signal. Similarly, the second GIP of this embodiment sequentially transitions the stages in the hold state to the on state via the carry signal. In addition, the second GIP of this embodiment sequentially transitions the stages in the on state to the hold state via the carry signal. The carry signal used in the first GIP is not transmitted to the second GIP. Therefore, the transition between the on state and the hold state of the stage of the first GIP is independent of the operation of the second GIP. Similarly, the carry signal used in the first GIP is not transmitted to the second GIP. Therefore, the transition between the on state and the hold state of the stage of the second GIP is independent of the operation of the first GIP.

[0054] FIG. 10 shows an example of transition between the on state and the hold state of each stage included in the first GIP and the second GIP. In this example, the first GIP transmits a scanning signal (gate signal) to the odd-numbered gate lines GL1, GL3, ..., GL31. For example, according to the arrangement of the subpixels shown in FIG. 3, the first GIP supplies a gate voltage to the first switch element T1 of the red subpixel R and the first switch element T1 of the white subpixel W via the odd-numbered gate lines. On the other hand, the second GIP transmits a scanning signal (gate signal) to the even-numbered gate lines GL2, GL4, ..., GL32. For example, according to the arrangement of the subpixels shown in FIG. 3, the second GIP supplies a gate voltage to the first switch element T1 of the green subpixel G and the first switch element T1 of the blue subpixel B via the even-numbered gate lines. Note that the gate lines connected to the first GIP are not limited to the odd-numbered gate lines, and the gate lines connected to the second GIP are not limited to the even-numbered gate lines. Depending on the circuit design of the gate driver, the first GIP and the second GIP can be connected to gate lines arranged at any positions.

[0055] In the example shown in Fig. 10, a predetermined number of scanning signals are successively transmitted through odd-numbered gate lines, and then a predetermined number of scanning signals are successively transmitted through even-numbered gate lines. For example, according to the arrangement of subpixels shown in Fig. 3, first, the first GIP supplies scanning signals successively through the odd-numbered gate lines to the red subpixels R and the white subpixels W arranged in each row of the display panel 100 over a predetermined number of rows. Next, the second GIP supplies scanning signals successively through the even-numbered gate lines to the green subpixels G and the blue subpixels B arranged in each row of the display panel 100 over a predetermined number of rows.

[0056] Specifically, in clock (1), the first, third, fifth, and seventh stages included in the first GIP and the second, fourth, sixth, and eighth stages included in the second GIP are in the on state. At this time, the first GIP is in a state in which a gate signal can be supplied through a group of gate lines (GL1, GL3, GL5, GL7, GL9, GL11, GL13, and GL15) corresponding to the on-state stages. Also, the second GIP is in a state in which a gate signal can be supplied through a group of gate lines (GL2, GL4, GL6, GL8, GL10, GL12, GL14, and GL16) corresponding to the on-state stages. Meanwhile, the ninth, eleventh, thirteenth, and fifteenth stages included in the first GIP and the tenth, twelfth, fourteenth, and sixteenth stages included in the second GIP are in the hold state. In clock (1), for example, the first GIP transmits a scanning signal from the third stage to the gate line GL5. As a result, the scanning signal is supplied to the red sub-pixel R and the white sub-pixel W electrically connected to the gate line GL5. No scanning signal is transmitted to the gate line GL from any stage other than the third stage. Note that the first GIP may transmit a scanning signal from the third stage to the gate line GL7 at a time between clock (1) and clock (2).

[0057] In clock (2), the first stage included in the first GIP is transitioned from an on state to a hold state. Meanwhile, in clock (2), the ninth stage included in the first GIP is transitioned from a hold state to an on state. Stages other than the first stage and the ninth stage included in the first GIP are maintained in the same state as in clock (1). At this time, the first GIP is in a state in which a gate signal can be supplied via the group of gate lines (GL5, GL7, GL9, GL11, GL13, GL15, GL17, GL19) corresponding to the on-state stage. In addition, all stages included in the second GIP are maintained in the same state as in clock (1). That is, the second GIP is in a state in which a gate signal can be supplied via the group of gate lines (GL2, GL4, GL6, GL8, GL10, GL12, GL14, GL16) corresponding to the on-state stage. In clock (2), the first GIP transmits a scanning signal from the fifth stage to the gate line GL9. As a result, the scanning signal is supplied to the red subpixel R and the white subpixel W electrically connected to the gate line GL9. No scanning signal is transmitted to the gate line GL from stages other than the fifth stage. Note that the first GIP may transmit a scanning signal from the fifth stage to the gate line GL11 at a time between clock (2) and clock (3).

[0058] At clock (3), the third stage included in the first GIP is transitioned from an on state to a hold state. Meanwhile, at clock (3), the eleventh stage included in the first GIP is transitioned from a hold state to an on state. Stages other than the third stage and the eleventh stage included in the first GIP and all stages included in the second GIP are maintained in the same state as in clock (2). At clock (3), the first GIP transmits a scanning signal from the seventh stage to the gate line GL13. As a result, the scanning signal is supplied to the red subpixel R and the white subpixel W electrically connected to the gate line GL13. The scanning signal is not transmitted to the gate line GL from the stages other than the seventh stage. Note that the first GIP may transmit a scanning signal from the seventh stage to the gate line GL15 at a time between clock (3) and clock (4).

[0059] At clock (4), the fifth stage included in the first GIP is transitioned from an on state to a hold state. Meanwhile, at clock (4), the thirteenth stage included in the first GIP is transitioned from a hold state to an on state. Stages other than the fifth stage and the thirteenth stage included in the first GIP and all stages included in the second GIP are maintained in the same state as in clock (3). At clock (4), the first GIP transmits a scanning signal from the ninth stage to the gate line GL17. As a result, the scanning signal is supplied to the red subpixel R and the white subpixel W electrically connected to the gate line GL17. The scanning signal is not transmitted from the stages other than the ninth stage to the gate line GL. Note that the first GIP may transmit a scanning signal from the ninth stage to the gate line GL19 at a time between clock (4) and clock (5).

[0060] At clock (5), the seventh stage included in the first GIP is transitioned from an on state to a hold state. Meanwhile, at clock (5), the fifteenth stage included in the first GIP is transitioned from a hold state to an on state. Stages other than the seventh stage and the fifteenth stage included in the first GIP and all stages included in the second GIP are maintained in the same state as in clock (4). At clock (5), the first GIP transmits a scanning signal from the eleventh stage to the gate line GL21. As a result, the scanning signal is supplied to the red subpixel R and the white subpixel W electrically connected to the gate line GL21. No scanning signal is transmitted from stages other than the eleventh stage to the gate line GL. Note that the first GIP may transmit a scanning signal from the eleventh stage to the gate line GL23 at a time between clock (5) and clock (6).

[0061] At clock (6), the second stage included in the second GIP is transitioned from an on state to a hold state. Meanwhile, at clock (6), the tenth stage included in the second GIP is transitioned from a hold state to an on state. Stages other than the second stage and the tenth stage included in the second GIP and all stages included in the first GIP are maintained in the same state as in clock (5). At clock (6), the second GIP transmits a scan signal from the fourth stage to the gate line GL6. As a result, the scan signal is supplied to the green subpixel G and the blue subpixel B electrically connected to the gate line GL6. No scan signal is transmitted to the gate line GL from stages other than the fourth stage. Note that the second GIP may transmit a scan signal from the fourth stage to the gate line GL8 at a time between clock (6) and clock (7).

[0062] At clock (7), the fourth stage included in the second GIP is transitioned from an on state to a hold state. Meanwhile, at clock (7), the twelfth stage included in the second GIP is transitioned from a hold state to an on state. Stages other than the fourth stage and the twelfth stage included in the second GIP and all stages included in the first GIP are maintained in the same state as in clock (6). At clock (7), the second GIP transmits a scan signal from the sixth stage to the gate line GL10. As a result, the scan signal is supplied to the green subpixel G and the blue subpixel B electrically connected to the gate line GL10. No scan signal is transmitted from the stages other than the sixth stage to the gate line GL. Note that the second GIP may transmit a scan signal from the sixth stage to the gate line GL12 at a time between clock (7) and clock (8).

[0063] At clock (8), the sixth stage included in the second GIP is transitioned from an on state to a hold state. Meanwhile, at clock (8), the fourteenth stage included in the second GIP is transitioned from a hold state to an on state. Stages other than the sixth and fourteenth stages included in the second GIP and all stages included in the first GIP are maintained in the same state as in clock (7). At clock (8), the second GIP transmits a scanning signal from the eighth stage to the gate line GL14. As a result, the scanning signal is supplied to the green subpixel G and the blue subpixel B electrically connected to the gate line GL14. No scanning signal is transmitted from stages other than the eighth stage to the gate line GL. Note that the second GIP may transmit a scanning signal from the eighth stage to the gate line GL16 at a time between clock (8) and clock (9).

[0064] At clock (9), the 8th stage included in the second GIP is transitioned from an on state to a hold state. Meanwhile, at clock (9), the 16th stage included in the second GIP is transitioned from a hold state to an on state. Stages other than the 8th stage and the 16th stage included in the second GIP and all stages included in the first GIP are maintained in the same state as in clock (8). At clock (9), the second GIP transmits a scan signal from the 10th stage to the gate line GL18. As a result, the scan signal is supplied to the green subpixel G and the blue subpixel B electrically connected to the gate line GL18. No scan signal is transmitted from stages other than the 10th stage to the gate line GL. Note that the second GIP may transmit a scan signal from the 10th stage to the gate line GL20 at a time after clock (9).

[0065] Fig. 11 is a table showing an example of the transition between the on state and the hold state of each stage included in the first GIP and the second GIP, which is different from the example shown in Fig. 10. Descriptions of the same configuration as in Fig. 10 may be omitted.

[0066] In the example shown in Fig. 11, a predetermined number of scanning signals are successively transmitted through the even-numbered gate lines, and then a predetermined number of scanning signals are successively transmitted through the odd-numbered gate lines. For example, according to the arrangement of subpixels shown in Fig. 3, the second GIP first supplies scanning signals successively through the even-numbered gate lines to the green subpixels G and blue subpixels B arranged in each row of the display panel 100 over a predetermined number of rows. Next, the first GIP supplies scanning signals successively through the odd-numbered gate lines to the red subpixels R and white subpixels W arranged in each row of the display panel 100 over a predetermined number of rows.

[0067] Specifically, in clock (1), the first, third, fifth, and seventh stages included in the first GIP and the second, fourth, sixth, and eighth stages included in the second GIP are in the ON state. Meanwhile, the ninth, eleventh, thirteenth, and fifteenth stages included in the first GIP and the tenth, twelfth, fourteenth, and sixteenth stages included in the second GIP are in the HOLD state. In clock (1), for example, the second GIP transmits a scanning signal from the fourth stage to the gate line GL6. As a result, the scanning signal is supplied to the green subpixel G and the blue subpixel B electrically connected to the gate line GL6. The scanning signal is not transmitted to the gate line GL from stages other than the fourth stage. Note that the second GIP may transmit a scanning signal from the fourth stage to the gate line GL8 at a time between clock (1) and clock (2).

[0068] At clock (2), the second stage included in the second GIP is transitioned from an on state to a hold state. Meanwhile, at clock (2), the tenth stage included in the second GIP is transitioned from a hold state to an on state. Stages other than the second stage and the tenth stage included in the second GIP and all stages included in the first GIP are maintained in the same state as in clock (1). At clock (2), the second GIP transmits a scan signal from the sixth stage to the gate line GL10. As a result, the scan signal is supplied to the green subpixel G and the blue subpixel B electrically connected to the gate line GL10. The scan signal is not transmitted to the gate line GL from the stages other than the sixth stage. Note that the second GIP may transmit a scan signal from the sixth stage to the gate line GL12 at a time between clock (2) and clock (3).

[0069] At clock (3), the fourth stage included in the second GIP is transitioned from an on state to a hold state. Meanwhile, at clock (3), the twelfth stage included in the second GIP is transitioned from a hold state to an on state. Stages other than the fourth stage and the twelfth stage included in the second GIP and all stages included in the first GIP are maintained in the same state as in clock (2). At clock (3), the second GIP transmits a scanning signal from the eighth stage to the gate line GL14. As a result, the scanning signal is supplied to the green subpixel G and the blue subpixel B electrically connected to the gate line GL14. The scanning signal is not transmitted to the gate line GL from the stages other than the eighth stage. Note that the second GIP may transmit a scanning signal from the eighth stage to the gate line GL16 at a time between clock (3) and clock (4).

[0070] At clock (4), the sixth stage included in the second GIP is transitioned from an on state to a hold state. Meanwhile, at clock (4), the fourteenth stage included in the second GIP is transitioned from a hold state to an on state. Stages other than the sixth and fourteenth stages included in the second GIP and all stages included in the first GIP are maintained in the same state as in clock (3). At clock (4), the second GIP transmits a scan signal from the tenth stage to the gate line GL18. As a result, the scan signal is supplied to the green subpixel G and the blue subpixel B electrically connected to the gate line GL18. No scan signal is transmitted from stages other than the tenth stage to the gate line GL. Note that the second GIP may transmit a scan signal from the tenth stage to the gate line GL20 at a time between clock (4) and clock (5).

[0071] At clock (5), the 8th stage included in the second GIP is transitioned from an on state to a hold state. Meanwhile, at clock (5), the 16th stage included in the second GIP is transitioned from a hold state to an on state. Stages other than the 8th stage and the 16th stage included in the second GIP and all stages included in the first GIP are maintained in the same state as in clock (4). At clock (5), the second GIP transmits a scan signal from the 12th stage to the gate line GL22. As a result, the scan signal is supplied to the green subpixel G and the blue subpixel B electrically connected to the gate line GL22. No scan signal is transmitted from stages other than the 12th stage to the gate line GL. Note that the second GIP may transmit a scan signal from the 12th stage to the gate line GL24 at a time between clock (5) and clock (6).

[0072] At clock (6), the first stage included in the first GIP is transitioned from an on state to a hold state. Meanwhile, at clock (6), the ninth stage included in the first GIP is transitioned from a hold state to an on state. Stages other than the first stage and the ninth stage included in the first GIP and all stages included in the second GIP are maintained in the same state as in clock (5). At clock (6), the first GIP transmits a scanning signal from the third stage to the gate line GL5. As a result, the scanning signal is supplied to the red subpixel R and the white subpixel W electrically connected to the gate line GL5. No scanning signal is transmitted from stages other than the third stage to the gate line GL. Note that the first GIP may transmit a scanning signal from the third stage to the gate line GL7 at a time between clock (6) and clock (7).

[0073] At clock (7), the third stage included in the first GIP is transitioned from an on state to a hold state. Meanwhile, at clock (7), the eleventh stage included in the first GIP is transitioned from a hold state to an on state. Stages other than the third stage and the eleventh stage included in the first GIP and all stages included in the second GIP are maintained in the same state as in clock (6). At clock (7), the first GIP transmits a scan signal from the fifth stage to the gate line GL9. As a result, the scan signal is supplied to the red subpixel R and the white subpixel W electrically connected to the gate line GL9. The scan signal is not transmitted to the gate line GL from the stages other than the fifth stage. Note that the first GIP may transmit a scan signal from the fifth stage to the gate line GL11 at a time between clock (7) and clock (8).

[0074] At clock (8), the fifth stage included in the first GIP is transitioned from an on state to a hold state. Meanwhile, at clock (8), the thirteenth stage included in the first GIP is transitioned from a hold state to an on state. Stages other than the fifth stage and the thirteenth stage included in the first GIP and all stages included in the second GIP are maintained in the same state as in clock (7). At clock (8), the first GIP transmits a scanning signal from the seventh stage to the gate line GL13. As a result, the scanning signal is supplied to the red subpixel R and the white subpixel W electrically connected to the gate line GL13. No scanning signal is transmitted from the stages other than the seventh stage to the gate line GL. Note that the first GIP may transmit a scanning signal from the seventh stage to the gate line GL15 at a time between clock (8) and clock (9).

[0075] At clock (9), the seventh stage included in the first GIP transitions from an on state to a hold state. Meanwhile, at clock (9), the fifteenth stage included in the second GIP transitions from a hold state to an on state. Stages other than the seventh stage and the fifteenth stage included in the first GIP and all stages included in the second GIP are maintained in the same state as in clock (8). At clock (9), the first GIP transmits a scan signal from the ninth stage to the gate line GL17. As a result, the scan signal is supplied to the red subpixel R and the white subpixel W electrically connected to the gate line GL17. No scan signal is transmitted from the stages other than the ninth stage to the gate line GL. Note that the first GIP may transmit a scan signal from the ninth stage to the gate line GL19 at a time after clock (9).

[0076] The gate driver according to the present embodiment includes first shift registers 221, 222 operating as a first GIP and second shift registers 231, 232 operating as a second GIP. The first GIP is connected to odd-numbered gate lines. Meanwhile, the second GIP is connected to even-numbered gate lines. During a period in which the first GIP transmits a scanning signal to an odd-numbered gate signal, a plurality of stages included in the first GIP can be transitioned between an on state and a hold state. Specifically, during a period in which the first GIP transmits a scanning signal to an odd-numbered gate signal, a certain stage is transitioned from an on state to a hold state and another stage is transitioned from a hold state to an on state. Meanwhile, during a period in which the first GIP transmits a scanning signal to an odd-numbered gate signal, the states of all stages included in the second GIP are not changed. Similarly, during a period in which the second GIP transmits a scanning signal to an even-numbered gate signal, a plurality of stages included in the second GIP can be transitioned between an on state and a hold state. Specifically, during a period in which the second GIP transmits a scan signal to an even-numbered gate signal, a certain stage is transitioned from an on state to a hold state and another stage is transitioned from a hold state to an on state. Meanwhile, during a period in which the second GIP transmits a scan signal to an even-numbered gate signal, the states of all stages included in the first GIP are not changed. That is, the first GIP is driven independently of the second GIP. Similarly, the second GIP is driven independently of the first GIP. The gate driver 200 according to the present embodiment can transmit scan signals to odd-numbered gate lines continuously over any number of rows of pixels by driving the first GIP independently of the second GIP. That is, the gate driver 200 can supply gate signals to the first switch elements T1 of a plurality of sub-pixels emitting the same color continuously over any number of rows. The gate driver 200 according to the present embodiment does not need to increase the number of stages in the on state in order to supply gate signals to a plurality of sub-pixels emitting the same color continuously over any number of rows. Therefore, there is no need to increase the number of input clocks to increase the number of stages that are on.Therefore, the display device 10 according to the present embodiment can write to sub-pixels emitting the same color continuously across a predetermined number of rows without increasing power consumption.

[0077] FIG. 12 is a block diagram showing a schematic configuration of the data driver 300 according to the present embodiment. The data driver 300 includes a data selector 310 and a data converter 320. The data selector 310 receives image data R'G'B'W' from the row memory 520 and receives a register selection signal RSS from the scheduler 560. The register selection signal RSS includes an input register selection signal IRSS, an input enable signal VALID, and an output register selection signal ORSS. The input register selection signal IRSS specifies a register in which the image data R'G'B'W' should be stored. The output register selection signal ORSS specifies a register in which the image data R'G'B'W' to be output is stored. The input enable signal VALID enables or disables the input register selection signal IRSS. The data selector 310 has a plurality of registers, and stores the image data R'G'B'W' received from the row memory 520 according to the register selection signal IRSS and the input enable signal VALID received from the scheduler 560. Specifically, when the input validation signal VALID is at a high level, the data selection unit 310 validates the register selection signal IRSS and stores the image data R'G'B'W' in the register specified by the register selection signal IRSS. The data selection unit 310 also transmits the image data R'G'B'W' stored in the register specified by the output register selection signal ORSS to the data conversion unit 320. The data conversion unit 320 converts the image data R'G'B'W' into analog data voltage DATA using a data control signal DSC and transmits it to each pixel via the data lines DL1 to GLm.

[0078] 13 is a block diagram showing a schematic configuration of the similarity determination section 550 according to this embodiment. The similarity determination section 550 includes a first difference calculation section 551, a second difference calculation section 552, a first accumulator 553, a second accumulator 554, a first threshold determination section 557, a second threshold determination section 558, and a reset determination section 559.

[0079] The first difference calculation unit 551 receives image data RGBW_O(x) of the xth row associated with the sub-pixel P arranged in the odd-numbered columns from the row memory unit 520. The received image data RGBW_O(x) is, for example, the RGBW values ​​of image data to be written to the green sub-pixel G and white sub-pixel W arranged in the xth row. The first difference calculation unit 551 also receives image data RGBW_O(x-1) of the x-1th row associated with the sub-pixel P arranged in the odd-numbered columns from the row memory unit 520. The received image data RGBW_O(x-1) is image data of the row immediately preceding the image data RGBW_O(x), and is, for example, the RGBW values ​​of image data to be written to the green sub-pixel G and white sub-pixel W arranged in the x-1th row. The first difference calculation unit 551 calculates a difference Diff_O between the received image data RGBW_O(x) of the xth row and the image data RGBW_O(x−1) of the x−1th row, and transmits the calculation result to the first accumulation unit 553 .

[0080] The first accumulator 553 receives data of the difference Diff_O between the RGBW value of the xth row and the RGBW value of the x-1th row in each odd-numbered column from the first difference calculator 551. The first accumulator 553 accumulates the difference Diff_O of the image data of each odd-numbered column received from the first difference calculator 551. For example, when the number of odd-numbered columns of sub-pixels included in the display panel 100 is m, the first accumulator 553 receives (m-1) difference values ​​corresponding to the number of odd-numbered columns for the difference Diff_O between the RGBW value of the xth row and the RGBW value of the x-1th row from the first difference calculator 551. The first accumulator 553 accumulates the (m-1) differences Diff_O between each column received from the first difference calculator 551. The first accumulator 553 transmits a value Sum_O obtained by accumulating the difference Diff_O to the first threshold value determiner 557. If the number of differences Diff_O of image data in odd-numbered columns is 1, the first accumulation unit 553 may be omitted.

[0081] The first threshold determination unit 557 receives an integrated value Sum_O of the difference Diff_O between the RGBW value of the xth row related to the odd-numbered column and the RGBW value of the x-1th row related to the odd-numbered column from the first integration unit 553. The first threshold determination unit 557 compares the received integrated value Sum_O with a predetermined threshold. When the first threshold determination unit 557 determines that the received integrated value Sum_O is less than the predetermined threshold, it determines that the image data of the xth row related to the odd-numbered column is similar to the image data of the x-1th row related to the odd-numbered column. On the other hand, when the first threshold determination unit 557 determines that the received integrated value Sum_O is equal to or greater than the predetermined threshold, it determines that the image data of the xth row related to the odd-numbered column is not similar to the image data of the x-1th row related to the odd-numbered column. The first threshold determination unit 557 transmits a signal RES_O(x) that is a result of the determination to the scheduler 560. For example, when the first threshold determination unit 557 determines that the image data in the xth row related to the odd-numbered columns is similar to the image data in the x-1th row related to the odd-numbered columns, it outputs 1 as the signal RES_O(x).On the other hand, when the first threshold determination unit 557 determines that the image data in the xth row related to the odd-numbered columns is not similar to the image data in the x-1th row related to the odd-numbered columns, it outputs 0 as the signal RES_O(x).

[0082] The second difference calculation unit 552 receives image data RGBW_E(x) of the xth row associated with the sub-pixel P arranged in the even-numbered columns from the row memory unit 520. The received image data RGBW_E(x) is, for example, the RGBW values ​​of image data written to the red sub-pixel R and blue sub-pixel B arranged in the xth row. The second difference calculation unit 552 also receives image data RGBW_E(x-1) of the x-1th row associated with the sub-pixel P arranged in the even-numbered columns from the row memory unit 520. The received image data RGBW_E(x-1) is image data of the row immediately preceding the image data RGBW_E(x), and is, for example, the RGBW values ​​of image data written to the red sub-pixel R and blue sub-pixel B arranged in the x-1th row. The second difference calculation unit 552 calculates the difference Diff_E between the received image data RGBW_E(x) of the xth row and the image data RGBW_E(x−1) of the x−1th row, and transmits the calculation result to the second accumulation unit 554.

[0083] The second accumulator 554 receives data of the difference Diff_E between the RGBW value of the xth row and the RGBW value of the x-1th row in each even column from the second difference calculator 552. The second accumulator 554 accumulates the difference Diff_E of the image data of each even column received from the second difference calculator 552. For example, when the number of sub-pixels in the even columns included in the display panel 100 is m, the second accumulator 554 receives (m-1) difference values ​​corresponding to the number of even columns for the difference Diff_E between the RGBW value of the xth row and the RGBW value of the x-1th row from the second difference calculator 552. The second accumulator 554 accumulates the (m-1) differences Diff_E between each column received from the second difference calculator 552. The second accumulator 554 transmits a value Sum_E obtained by accumulating the difference Diff_E to the second threshold value determiner 558. If the number of differences Diff_E of image data in even-numbered columns is 1, the second accumulator 554 may be omitted.

[0084] The second threshold determination unit 558 receives an integrated value Sum_E of the difference Diff_E between the RGBW value of the xth row related to the even columns and the RGBW value of the x-1th row related to the even columns from the second integration unit 554. The second threshold determination unit 558 compares the received integrated value Sum_E with a predetermined threshold. When the second threshold determination unit 558 determines that the received integrated value Sum_E is less than the predetermined threshold, it determines that the image data of the xth row related to the even columns is similar to the image data of the x-1th row related to the even columns. On the other hand, when the second threshold determination unit 558 determines that the received integrated value Sum_E is equal to or greater than the predetermined threshold, it determines that the image data of the xth row related to the even columns is not similar to the image data of the x-1th row related to the even columns. The second threshold determination unit 558 transmits a signal RES_E(x) that is a result of the determination to the scheduler 560. For example, when the second threshold determination unit 558 determines that the image data in the xth row related to the even columns is similar to the image data in the x-1th row related to the even columns, it outputs 1 as the signal RES_E(x).On the other hand, when the first threshold determination unit 557 determines that the image data in the xth row related to the even columns is not similar to the image data in the x-1th row related to the even columns, it outputs 0 as the signal RES_E(x).

[0085] The reset determination unit 559 generates a reset signal based on the horizontal synchronization signal Hsync. Specifically, the reset determination unit 559 transmits the reset signal RST to the first integrator 553 and the second integrator 554 at the timing when the horizontal synchronization signal Hsync transitions from a high level to a low level. The first integrator 553 and the second integrator 554 reset the integrated value of the difference of the image data to 0 in response to the received reset signal RST. In addition, the reset determination unit 559 transmits an enable signal RES_Enable to the first threshold determination unit 557 and the second threshold determination unit 558 at the timing when the horizontal synchronization signal Hsync transitions from a high level to a low level. The first threshold determination unit 557 and the second threshold determination unit 558 transmit signals RES_O(x) and RES_E(x), which are the results of the threshold determination, to the scheduler 560 in response to the received enable signal RES_Enable.

[0086] 14 is a block diagram showing a schematic configuration of a scheduler 560 according to the present embodiment. The scheduler 560 includes a buffer 561, a scanning order determination unit 562, a gate line determination unit 563, a register 564, and a selection signal determination unit 565.

[0087] Buffer 561 receives signals RES_O(x) and RES_E(x) which are the results of the threshold determination from similarity determination unit 550. Buffer 561 transmits the received signals RES_O(x) and RES_E(x) to scanning order determination unit 562. For example, buffer 561 stores signals RES_O and RES_E in the buffer up to an arbitrary number of rows, and transmits signals RES_O and RES_E for that number of rows to scanning order determination unit 562.

[0088] The scanning order determination unit 562 receives a signal RES, which is the result of threshold determination for an arbitrary number of rows, from the buffer 561. The scanning order determination unit 562 determines the number of rows to be continuously scanned for odd-numbered sub-pixel columns or even-numbered sub-pixel columns based on the received signal RES. The scanning order determination unit 562 transmits a signal C_Num indicating the number of rows to be continuously scanned to the gate line determination unit 563, the register 564, and the selection signal determination unit 565.

[0089] The gate line determination unit 563 receives a signal C_Num indicating the number of rows to be continuously scanned from the scanning order determination unit 562. The gate line determination unit 563 determines the order of gate lines to which gate signals are applied based on the signal C_Num. The gate line determination unit 563 transmits a gate line designation signal GL_Num to the signal modulation unit 510. The signal modulation unit 510 generates a data enable signal tDE modulated based on the gate line designation signal GL_Num, and the row memory unit 520 aligns the image data RGBW based on the modulated data enable signal tDE received from the signal modulation unit 510.

[0090] The register 564 receives and stores the signal C_Num indicating the number of rows to be scanned continuously from the scanning order determination unit 562. The signal C_Num stored in the register 564 is called when the scanning order determination unit 562 determines the number of rows to be scanned continuously for the next arbitrary number of rows. The scanning order determination unit 562 uses the signal C_Num received from the register 564 to determine the number of rows to be scanned continuously for the odd-numbered sub-pixel columns or the even-numbered sub-pixel columns. For example, the scanning order determination unit 562 determines the signal C_Num(x) indicating the number of rows to be scanned continuously based on the signal C_Num(x-1) outputted immediately before for the arbitrary number of rows. Specifically, when an upper limit is set for the number of rows to be scanned continuously, the gate line determination unit 563 corrects the signal C_Num(x) according to the signal C_Num(x-1). Furthermore, for example, when a continuous similarity is found between the signal C_Num(x-1) and the signal C_Num(x) for the sub-pixels in the odd columns, the gate line determination unit 563 determines to continuously scan the corresponding rows for the sub-pixels in the odd columns.

[0091] The selection signal determination unit 565 receives a signal C_Num indicating the number of rows to be scanned continuously from the scanning order determination unit 562. The selection signal determination unit 565 generates an input register selection signal IRSS, an output register selection signal ORSS, and an input enable signal VALID based on the signal C_Num. The input register selection signal IRSS specifies a register in which image data R'G'B'W' should be stored in the data selection unit 310 included in the data driver 300. The output register selection signal ORSS specifies a register in which image data R'G'B'W' to be output from the data selection unit 310 is stored. The input enable signal VALID enables or disables the input register selection signal IRSS. The selection signal determination unit 565 transmits the generated input register selection signal IRSS, output register selection signal ORSS, and input enable signal VALID to the data selection unit 310.

[0092] 15 is a block diagram showing a schematic configuration of data selection section 310 according to this embodiment. Data selection section 310 includes data division sections 311-1 to 311-m, first registers 312-1 to 312-m, second registers 313-1 to 313-m, and selection sections 314-1 to 314-m.

[0093] The data division units 311-1 to 311-m receive image data R'G'B'W' from the row memory unit 520 included in the timing control unit 500. The data division units 311-1 to 311-m also receive an input register selection signal IRSS and an input enable signal VALID from a selection signal determination unit 565 included in the scheduler 560. The data division units 311-1 to 311-m divide the received image data R'G'B'W' based on the received input register selection signal IRSS. Next, the data division units 311-1 to 311-m transmit the divided image data R'G'B'W' to the first registers 312-1 to 312-m or the second registers 313-1 to 313-m based on the received input register selection signal IRSS and input enable signal VALID.

[0094] When the input register selection signal IRSS designates the first registers 312-1 to 312-m and the input enable signal VALID validates the input register selection signal IRSS, the first registers 312-1 to 312-m store the divided image data R'G'B'W' received from the data division units 311-1 to 311-m. That is, the first registers 312-1 to 312-m function as a storage unit that stores image data. On the other hand, when the input register selection signal IRSS designates the first registers 312-1 to 312-m but the input enable signal VALID invalidates the input register selection signal IRSS, the first registers 312-1 to 312-m do not store the divided image data R'G'B'W' received from the data division units 311-1 to 311-m.

[0095] When the input register selection signal IRSS designates the second registers 313-1 to 313-m and the input enable signal VALID validates the input register selection signal IRSS, the second registers 313-1 to 313-m store the divided image data R'G'B'W' received from the data division units 311-1 to 311-m. That is, the second registers 313-1 to 313-m function as a storage unit that stores image data. On the other hand, when the input register selection signal IRSS designates the second registers 313-1 to 313-m but the input enable signal VALID invalidates the input register selection signal IRSS, the second registers 313-1 to 313-m do not store the divided image data R'G'B'W' received from the data division units 311-1 to 311-m.

[0096] The selection units 314-1 to 314-m receive an output register selection signal ORSS from a selection signal determination unit 565 included in the scheduler 560. The selection units 314-1 to 314-m transmit the divided image data R'G'B'W' (1 to m) stored in the first registers 312-1 to 312-m or the second registers 313-1 to 313-m designated by the output register selection signal ORSS to the data conversion unit 320. The data conversion unit 320 converts the received image data R'G'B'W' into analog data voltage DATA using a data control signal DSC, and transmits it to each pixel via the data lines DL1 to GLm.

[0097] An example of the operation of the data selection unit 310 in response to an input signal to the scheduler 560 will be described with reference to Fig. 16 and Fig. 17. Fig. 16 is a table showing an example of an input to the scheduler 560 according to this embodiment. Fig. 17 is a table showing an example of a signal input to the data selection unit 310 according to this embodiment.

[0098] FIG. 16 shows an example of values ​​of signals RES_O and RES_E input from the similarity determination unit 550 to the scheduler 560 for the x-7th row to the xth row. As shown in FIG. 16, in this example, the output signal RES_O of the similarity determination unit 550 for odd-numbered columns indicates 0 for the x-7th row. That is, the similarity determination unit 550 determines that the image data of the odd-numbered columns for the x-7th row is not similar to the image data of the odd-numbered columns of the previous row. Also, the output signal RES_O of the similarity determination unit 550 for odd-numbered columns indicates 1 for the x-6th row to the xth row. That is, the similarity determination unit 550 determines that the image data of the odd-numbered columns for the x-6th row to the xth row are similar to the image data of the odd-numbered columns of the previous row. On the other hand, the output signal RES_E of the similarity determination unit 550 for even-numbered columns all indicate 0. That is, the similarity determination section 550 determines that the image data in the even-numbered columns from the x-7th row to the xth row are not similar to the image data in the even-numbered columns of the previous row.

[0099] 17 shows an example of the input register selection signal IRSS, the input validation signal VALID, and the output register selection signal ORSS transmitted to the data selection unit 310 in the scan numbers 1 to 16. In this example, the image data (signals) of the odd-numbered columns from the x-6th row to the xth row are similar to the image data of the odd-numbered columns located one row above. Therefore, in the scan numbers 1 to 8, the aligned image data R'G'B'W' of the odd-numbered columns from the x-7th row to the xth row are inputted from the row memory unit 520 to the data selection unit 310 as input data 1 to 8. Next, in the scan numbers 9 to 16, the aligned image data R'G'B'W' of the even-numbered columns from the x-7th row to the xth row are inputted from the row memory unit 520 to the data selection unit 310 as input data 9 to 16.

[0100] The scheduler 560 generates an input register selection signal IRSS for specifying a register in which the odd-numbered columns of input data 1 to 8 are stored, based on the received signal RES_O. The scheduler 560 transmits the input register selection signal IRSS for specifying the first registers 312-1 to 312-m as registers in which the input data 1 to 8 should be stored, to the data selection unit 310. The scheduler 560 also generates an input register selection signal IRSS for specifying a register in which the even-numbered columns of input data 9 to 16 are stored, based on the received signal RES_E. The scheduler 560 transmits the input register selection signal IRSS for specifying the second registers 313-1 to 313-m as registers in which the input data 9 to 16 should be stored, to the data selection unit 310.

[0101] The scheduler 560 transmits 1 to the data selection unit 310 as the input validation signal VALID for the input data 1 corresponding to the odd-numbered column, and validates the input register selection signal IRSS that specifies that the input data 1 is to be stored in the first registers 312-1 to 312-m. Here, the scheduler 560 determines that the input data 1 to 8 are similar image data based on the received signal RES_O. Therefore, the scheduler 560 transmits 0 to the data selection unit 310 as the input validation signal VALID for the input data 2 to 8, and invalidates the input register selection signal IRSS that specifies that the input data 2 to 8 are to be stored in the first registers 312-1 to 312-m. As a result, the first registers 312-1 to 312-m are not updated, and the input data 1 is held. This configuration reduces the consumption of power required to update the data stored in the first registers 312-1 to 312-m. In this example, the timing control unit 500 may be configured not to transmit the input register selection signal IRSS to the data driver 300 during the scan numbers 2 to 8.

[0102] Next, the scheduler 560 transmits 1 to the data selection unit 310 as an input validation signal VALID for the input data 9 corresponding to the even-numbered column, and validates the input register selection signal IRSS that specifies that the input data 9 is to be stored in the second registers 313-1 to 313-m. Here, the scheduler 560 determines that the input data 9 to 16 are dissimilar image data based on the received signal RES_E. That is, the input data 9 stored in the second registers 313-1 to 313-m cannot be used as the input data 10 to 16. Therefore, the scheduler 560 transmits 1 to the data selection unit 310 as an input validation signal VALID for the input data 10 to 16, and validates the input register selection signal IRSS that specifies that the input data 10 to 16 is to be stored in the second registers 313-1 to 313-m.

[0103] The scheduler 560 transmits an output register selection signal ORSS to the data selection unit 310 in order to sequentially output the input data 1 to 16 as output data 1 to 16 to the data conversion unit 320. Specifically, the scheduler 560 transmits an output register selection signal ORSS designating the first registers 312-1 to 312-m for the scan numbers 1 to 8 to the data selection unit 310, and transmits an output register selection signal ORSS designating the second registers 313-1 to 313-m for the scan numbers 9 to 16 to the data selection unit 310.

[0104] In a display device using a DRD, subpixels of different colors share one data line. Therefore, every time the color of the scanned subpixel is switched, a discontinuity occurs in the signal (voltage) of the image data, resulting in an increase in power consumption of the display device 10. In order to reduce power consumption in a display device using a DRD, it is desirable to continuously scan subpixels of the same color to reduce the frequency of discontinuity in the signal (voltage) of the output image data. However, if the number of rows for continuously scanning subpixels of the same color is increased, a large time difference occurs between the writing of image data to other subpixels arranged in the same row. This large time difference can degrade the image quality of the displayed image. In particular, when a plurality of pixel rows display an area in which the pixels are dissimilar to each other, a large time difference occurs between the writing of image data to the plurality of subpixels arranged in the same row, which can degrade the image quality. On the other hand, when a plurality of pixel rows display an area in which the pixels are similar to each other, even if a large time difference occurs between the writing of image data to the plurality of subpixels arranged in the same row, the image quality is unlikely to degrade. The present invention determines the similarity between each pixel row of a display panel, and continuously scans subpixels of the same color based on the determination result. In a region where multiple pixel rows are similar to each other and image quality is unlikely to deteriorate even if a large time difference occurs between writing image data to multiple sub-pixels arranged in the same row, sub-pixels of the same color are scanned consecutively. Therefore, according to the present invention, it is possible to reduce power consumption while suppressing deterioration in the display image quality of a display device using a DRD.

[0105] Another example of the operation of the data selection unit 310 in response to the input signal to the scheduler 560 will be described with reference to Fig. 18 and Fig. 19. Fig. 18 is a table showing an example of the input to the scheduler 560 according to this embodiment. Fig. 19 is a table showing an example of the signal input to the data selection unit 310 according to this embodiment.

[0106] FIG. 18 shows an example of values ​​of signals RES_O and RES_E input from the similarity determination unit 550 to the scheduler 560 for rows x-15 to x-8. As shown in FIG. 18, in this example, the output signal RES_O of the similarity determination unit 550 for odd-numbered columns indicates all 0. That is, the similarity determination unit 550 determines that the image data of the odd-numbered columns for rows x-15 to x-8 are not similar to the image data of the odd-numbered columns of the previous row. Similarly, the output signal RES_E of the similarity determination unit 550 for even-numbered columns indicates all 0. That is, the similarity determination unit 550 determines that the image data of the even-numbered columns for rows x-15 to x-8 are not similar to the image data of the even-numbered columns of the previous row.

[0107] FIG. 19 shows an example of the input register selection signal IRSS, the input validation signal VALID, and the output register selection signal ORSS transmitted to the data selection unit 310 in the scan numbers 17 to 32. In this example, the image data of the odd columns in the x-15th row to the x-8th row is not similar to the image data of the odd columns in the previous and next rows. Similarly, the image data of the even columns in the x-15th row to the x-8th row is not similar to the image data of the even columns in the previous and next rows. Therefore, first, in the scan number 17, the aligned image data R'G'B'W' of the odd columns in the x-15th row is input from the row memory unit 520 to the data selection unit 310 as the input data 17. Next, in the scan numbers 18 to 19, the aligned image data R'G'B'W' of the even columns in the x-15th row to the x-14th row is input from the row memory unit 520 to the data selection unit 310 as the input data 18 to 19. Next, in scan numbers 20-21, the aligned image data R'G'B'W' of odd-numbered columns for rows x-14 to x-13 are input from row memory unit 520 to data selection unit 310 as input data 20-21. In the following scans, the columns to be scanned are switched every two rows, and aligned image data R'G'B'W' of even-numbered columns for rows x-13 to x-8 are input from row memory unit 520 to data selection unit 310 as input data 22-23, 26-27, and 30-31 in scan numbers 22-23, 26-27, and 30-31. Similarly, for scan numbers 24-25, 28-29 and 32, the aligned image data R'G'B'W' of odd-numbered columns for rows x-12 to x-8 are input from row memory unit 520 to data selection unit 310 as input data 24-25, 28-29 and 32.

[0108] The scheduler 560 generates an input register selection signal IRSS for specifying a register in which the odd-numbered columns of input data 17, 20-21, 24-25, 28-29, and 32 are stored, based on the received signal RES_O. The scheduler 560 transmits to the data selection unit 310 an input register selection signal IRSS for specifying the first registers 312-1 to 312-m as registers in which the input data 17, 20-21, 24-25, 28-29, and 32 should be stored. The scheduler 560 also generates an input register selection signal IRSS for specifying a register in which the even-numbered columns of input data 18-19, 22-23, 26-27, and 30-31 are stored, based on the received signal RES_E. The scheduler 560 transmits to the data selection unit 310 an input register selection signal IRSS that designates the second registers 313-1 to 313-m as registers in which the input data 18-19, 22-23, 26-27, and 30-31 should be stored.

[0109] The scheduler 560 transmits 1 to the data selection unit 310 as an input validation signal VALID for the input data 17, 20-21, 24-25, 28-29, and 32 corresponding to the odd-numbered columns, and validates the input register selection signal IRSS that specifies that the input data 17, 20-21, 24-25, 28-29, and 32 are stored in the first registers 312-1-312-m. Here, the scheduler 560 determines that the input data 1-8 are dissimilar image data based on the received signal RES_O. That is, the input data 17 stored in the second registers 313-1-313-m cannot be used as the input data 20-21, 24-25, 28-29, and 32. Therefore, the scheduler 560 transmits 1 to the data selection unit 310 as the input validation signal VALID for the input data 17, 20 to 21, 24 to 25, 28 to 29, and 32, and validates the input register selection signal IRSS, which specifies that the input data 17, 20 to 21, 24 to 25, 28 to 29, and 32 are to be stored in the first registers 312-1 to 312-m.

[0110] Similarly, the scheduler 560 transmits 1 to the data selection unit 310 as an input validation signal VALID for the input data 18-19, 22-23, 26-27, and 30-31 corresponding to the even-numbered columns, and validates the input register selection signal IRSS that specifies that the input data 18-19, 22-23, 26-27, and 30-31 are stored in the second registers 313-1-313-m. Here, the scheduler 560 determines that the input data 9-16 are dissimilar image data based on the received signal RES_E. That is, the input data 18 stored in the second registers 313-1-313-m cannot be used as the input data 19, 22-23, 26-27, and 30-31. Therefore, the scheduler 560 transmits 1 to the data selection unit 310 as the input validation signal VALID for the input data 18-19, 22-23, 26-27, and 30-31, and validates the input register selection signal IRSS, which specifies that the input data 18-19, 22-23, 26-27, and 30-31 are to be stored in the second registers 313-1-313-m.

[0111] The scheduler 560 transmits an output register selection signal ORSS to the data selection unit 310 in order to sequentially output the input data 17 to 32 as output data 17 to 32 to the data conversion unit 320. Specifically, the scheduler 560 transmits output register selection signals ORSS designating the first registers 312-1 to 312-m for the scan numbers 17, 20 to 21, 24 to 25, 28 to 29, and 32 to the data selection unit 310, and transmits output register selection signals ORSS designating the second registers 313-1 to 313-m for the scan numbers 18 to 19, 22 to 23, 26 to 27, and 30 to 31 to the data selection unit 310.

[0112] This makes it possible to suppress degradation of the display quality of a display device using a DRD.

[0113] The following describes the order of scanning sub-pixels that is changed based on an image displayed on the display device 10 according to this embodiment. FIG. 20 shows an example of an image displayed on the display device 10 according to this embodiment. The display panel 100 included in the display device 10 displays a plurality of pixel rows 1301-1324. The similarity determination unit 550 determines that the image data written to the sub-pixels arranged in the odd-numbered and even-numbered columns included in the pixel rows 1301-1309, 1313, and 1317 is not similar to the image data written to the sub-pixels arranged in the odd-numbered and even-numbered columns included in the pixel row located one row above these pixel rows. On the other hand, the similarity determination unit 550 determines that the pixel data written to the sub-pixels arranged in the odd-numbered and even-numbered columns included in the pixel rows 1310-1312, 1314-1316, and 1318-1324 is similar to the image data written to the sub-pixels arranged in the odd-numbered and even-numbered columns included in the pixel row located one row above these pixel rows.

[0114] FIG. 21 is a schematic diagram showing the order in which subpixels of the display device according to this embodiment are scanned. FIG. 21 shows four columns of subpixels in pixel rows 1301-1308 shown in FIG. 20. Specifically, FIG. 21 shows green subpixels G1-G8 and red subpixels R1-R8 sharing a data line DL1, and white subpixels W1-W8 and blue subpixels B1-B8 sharing a data line DL2. The similarity determination unit 550 has determined that the image data (image signals) of the pixel rows 1301-1308 are not similar for both odd-numbered columns and even-numbered columns. Therefore, the values ​​of the signals RES_O and RES_E for the pixel rows 1301-1308 input from the similarity determination unit 550 to the scheduler 560 are all 0. The scheduler 560 generates an input register selection signal IRSS, an input validation signal VALID, and an output register selection signal ORSS based on the received signals RES_O and RES_E. The scheduler 560 transmits the generated input register selection signal IRSS, input enable signal VALID, and output register selection signal ORSS to the data driver 300. The data driver 300 transmits image data (image signals) to the green sub-pixels G1 to G8, red sub-pixels R1 to R8, white sub-pixels W1 to W8, and blue sub-pixels B1 to B8 in an order specified by the received output register selection signal ORSS.

[0115] As shown in FIG. 21, in pixel rows 1301 to 1308, the green subpixels G and red subpixels R are scanned in the following order: First, the green subpixel G1 is scanned, followed by the red subpixel R1, which is in the same row as the green subpixel G1 and shares the data line DL1, but is included in a pixel column different from the pixel column of the green subpixel G. Then, the red subpixel R2, which is disposed one row below the red subpixel R1, is scanned. Then, the green subpixel G2, which is in the same row as the red subpixel R2 and shares the data line DL1, but is included in a pixel column different from the pixel column of the red subpixel R, is scanned. Then, the green subpixel G3, which is disposed one row below the green subpixel G2, is scanned. Then, the red subpixel R3, which is in the same row as the green subpixel G3 and shares the data line DL1, but is included in a pixel column different from the pixel column of the green subpixel G, is scanned. Then, the red subpixel R4, which is disposed one row below the red subpixel R3, is scanned. Then, the green subpixel G4, which shares the data line DL1 in the same row as the red subpixel R4 and is included in a pixel column different from the pixel column of the red subpixel R, is scanned. Then, the green subpixel G5, which is arranged in the row below the green subpixel G4, is scanned. Then, the red subpixel R5, which shares the data line DL1 in the same row as the green subpixel G5 and is included in a pixel column different from the pixel column of the green subpixel G, is scanned. Then, the red subpixel R6, which is arranged in the row below the red subpixel R5, is scanned. Then, the green subpixel G6, which shares the data line DL1 in the same row as the red subpixel R6 and is included in a pixel column different from the pixel column of the red subpixel R, is scanned. Then, the green subpixel G7, which is arranged in the row below the green subpixel G6, is scanned. Then, the red subpixel R7, which shares the data line DL1 in the same row as the green subpixel G7 and is included in a pixel column different from the pixel column of the green subpixel G, is scanned. Then, the red subpixel R8, which is arranged in the row below the red subpixel R7, is scanned. After that, the green subpixel G8, which shares the data line DL1 in the same row as the red subpixel R8 and is included in a pixel column different from the pixel column of the red subpixel R, is scanned.

[0116] As shown in FIG. 21, in pixel rows 1301 to 1308, the white subpixels W and blue subpixels B are scanned in the following order. First, the blue subpixel B1 is scanned, and then the white subpixel W1, which is in the same row as the blue subpixel B1 and shares the data line DL2, and is included in a pixel column different from the pixel column of the blue subpixel B, is scanned. Then, the white subpixel W2, which is arranged in the row below the white subpixel W1, is scanned. Then, the blue subpixel B2, which is in the same row as the white subpixel W2 and shares the data line DL2, and is included in a pixel column different from the pixel column of the white subpixel W, is scanned. Then, the blue subpixel B3, which is arranged in the row below the blue subpixel B2, is scanned. Then, the white subpixel W3, which is in the same row as the blue subpixel B3 and shares the data line DL2, and is included in a pixel column different from the pixel column of the blue subpixel B, is scanned. Then, the white subpixel W4, which is arranged in the row below the white subpixel W3, is scanned. Then, the blue subpixel B4, which shares the data line DL2 in the same row as the white subpixel W4 and is included in a pixel column different from the pixel column of the white subpixel W, is scanned. Then, the blue subpixel B5, which is arranged one row below the blue subpixel B4, is scanned. Then, the white subpixel W5, which shares the data line DL2 in the same row as the blue subpixel B5 and is included in a pixel column different from the pixel column of the blue subpixel B, is scanned. Then, the white subpixel W6, which is arranged one row below the white subpixel W5, is scanned. Then, the blue subpixel B6, which shares the data line DL2 in the same row as the white subpixel W6 and is included in a pixel column different from the pixel column of the white subpixel W, is scanned. Then, the blue subpixel B7, which is arranged one row below the blue subpixel B6, is scanned. Then, the white subpixel W7, which shares the data line DL2 in the same row as the blue subpixel B7 and is included in a pixel column different from the pixel column of the blue subpixel B, is scanned. Then, the white subpixel W8, which is arranged one row below the white subpixel W7, is scanned. After that, the blue subpixel B8, which shares the data line DL2 with the white subpixel W8 in the same row and is included in a pixel column different from the pixel column of the white subpixel W8, is scanned.

[0117] In this embodiment, the similarity determination unit 550 determines that the image data of pixel rows 1301 to 1308 are not similar. Based on this determination, the scheduler 560 generates an input register selection signal IRSS, an input enable signal VALID, and an output register selection signal ORSS so as to alternately scan two rows of subpixels of each color, and transmits the generated signals to the data driver 300. The data driver 300 writes image data to the green subpixels G1 to G8, the red subpixels R1 to R8, the white subpixels W1 to W8, and the blue subpixels B1 to B8 in the order specified by the received output register selection signal ORSS. In this embodiment, in the pixel rows 1301 to 1308 constituting an area in which the image data are dissimilar to each other, the number of rows in which subpixels of the same color are continuously scanned is reduced to reduce the time difference in writing image data to subpixels arranged in the same row. Specifically, in this embodiment, the subpixels of each color are alternately scanned two rows at a time, thereby reducing the time difference in writing image data between a plurality of subpixels arranged in the same row. Therefore, according to the present invention, when displaying dissimilar areas between pixel rows in a display device using a DRD, it is possible to suppress degradation of display image quality caused by the time difference in writing image data between multiple sub-pixels arranged in the same row.

[0118] Figure 22 is a timing diagram of gate signals applied to gate lines GL1 to GL16 by the gate driver 200 when scanning the sub-pixels of pixel rows 1301 to 1308 shown in Figure 20 of the display device 10 of this embodiment in the order shown in Figure 21.

[0119] During the period from time t0 to t1, no gate signal is applied to the gate lines GL1 to GL16. During the period from time t1 to t2, a gate signal is applied to the gate line GL2 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL2, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G1 and the first capacitor C1 of the green subpixel G1 via the first switch element T1 of the green subpixel G1. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G1. Similarly, when a gate signal is applied to the gate line GL2, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B1 and the first capacitor C1 of the blue subpixel B1 via the first switch element T1 of the blue subpixel B1. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B1.

[0120] In the period from time t2 to t3, a gate signal is applied to the gate line GL1 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL1, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R1 and the first capacitor C1 of the red subpixel R1 via the first switch element T1 of the red subpixel R1. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R1. Similarly, when the gate signal is applied to the gate line GL1, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W1 and the first capacitor C1 of the white subpixel W1 via the first switch element T1 of the white subpixel W1. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W1.

[0121] In the period from time t3 to t4, a gate signal is applied to the gate line GL3 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL3, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R2 and the first capacitor C1 of the red subpixel R2 via the first switch element T1 of the red subpixel R2. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R2. Similarly, when a gate signal is applied to the gate line GL3, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W2 and the first capacitor C1 of the white subpixel W2 via the first switch element T1 of the white subpixel W2. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W2.

[0122] In the period from time t4 to t5, a gate signal is applied to the gate line GL4 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL4, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G2 and the first capacitor C1 of the green subpixel G2 via the first switch element T1 of the green subpixel G2. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G2. Similarly, when a gate signal is applied to the gate line GL4, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B2 and the first capacitor C1 of the blue subpixel B2 via the first switch element T1 of the blue subpixel B2. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B2.

[0123] In the period from time t5 to t6, a gate signal is applied to the gate line GL6 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL6, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G3 and the first capacitor C1 of the green subpixel G3 via the first switch element T1 of the green subpixel G3. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G3. Similarly, when the gate signal is applied to the gate line GL6, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B3 and the first capacitor C1 of the blue subpixel B3 via the first switch element T1 of the blue subpixel B3. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B3.

[0124] In a period from time t6 to time t7, a gate signal is applied to the gate line GL5 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL5, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R3 and the first capacitor C1 of the red subpixel R3 via the first switch element T1 of the red subpixel R3. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R3. Similarly, when a gate signal is applied to the gate line GL5, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W3 and the first capacitor C1 of the white subpixel W3 via the first switch element T1 of the white subpixel W3. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W3.

[0125] In the period from time t7 to time t8, a gate signal is applied to the gate line GL7 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL7, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R4 and the first capacitor C1 of the red subpixel R4 via the first switch element T1 of the red subpixel R4. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R4. Similarly, when the gate signal is applied to the gate line GL7, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W4 and the first capacitor C1 of the white subpixel W4 via the first switch element T1 of the white subpixel W4. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W4.

[0126] In the period from time t8 to t9, a gate signal is applied to the gate line GL8 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL8, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G4 and the first capacitor C1 of the green subpixel G4 via the first switch element T1 of the green subpixel G4. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G4. Similarly, when a gate signal is applied to the gate line GL8, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B4 and the first capacitor C1 of the blue subpixel B4 via the first switch element T1 of the blue subpixel B4. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B4.

[0127] In the period from time t9 to t10, a gate signal is applied to the gate line GL10 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL10, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G5 and the first capacitor C1 of the green subpixel G5 via the first switch element T1 of the green subpixel G5. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G5. Similarly, when the gate signal is applied to the gate line GL10, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B5 and the first capacitor C1 of the blue subpixel B5 via the first switch element T1 of the blue subpixel B5. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B5.

[0128] In the period from time t10 to t11, a gate signal is applied to the gate line GL9 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL9, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R5 and the first capacitor C1 of the red subpixel R5 via the first switch element T1 of the red subpixel R5. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R5. Similarly, when the gate signal is applied to the gate line GL9, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W5 and the first capacitor C1 of the white subpixel W5 via the first switch element T1 of the white subpixel W5. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W5.

[0129] In the period from time t11 to t12, a gate signal is applied to the gate line GL11 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL11, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R6 and the first capacitor C1 of the red subpixel R6 via the first switch element T1 of the red subpixel R6. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R6. Similarly, when the gate signal is applied to the gate line GL11, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W6 and the first capacitor C1 of the white subpixel W6 via the first switch element T1 of the white subpixel W6. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W6.

[0130] In the period from time t12 to t13, a gate signal is applied to the gate line GL12 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL12, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G6 and the first capacitor C1 of the green subpixel G6 via the first switch element T1 of the green subpixel G6. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G6. Similarly, when the gate signal is applied to the gate line GL12, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B6 and the first capacitor C1 of the blue subpixel B6 via the first switch element T1 of the blue subpixel B6. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B6.

[0131] In the period from time t13 to t14, a gate signal is applied to the gate line GL14 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL14, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G7 and the first capacitor C1 of the green subpixel G7 via the first switch element T1 of the green subpixel G7. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G7. Similarly, when a gate signal is applied to the gate line GL14, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B7 and the first capacitor C1 of the blue subpixel B7 via the first switch element T1 of the blue subpixel B7. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B7.

[0132] In the period from time t14 to t15, a gate signal is applied to the gate line GL13 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL13, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R7 and the first capacitor C1 of the red subpixel R7 via the first switch element T1 of the red subpixel R7. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R7. Similarly, when the gate signal is applied to the gate line GL13, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W7 and the first capacitor C1 of the white subpixel W7 via the first switch element T1 of the white subpixel W7. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W7.

[0133] In the period from time t15 to t16, a gate signal is applied to the gate line GL15 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL15, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R8 and the first capacitor C1 of the red subpixel R8 via the first switch element T1 of the red subpixel R8. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R8. Similarly, when the gate signal is applied to the gate line GL15, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W8 and the first capacitor C1 of the white subpixel W8 via the first switch element T1 of the white subpixel W8. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W8.

[0134] In the period from time t16 to t17, a gate signal is applied to the gate line GL16 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL16, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G8 and the first capacitor C1 of the green subpixel G8 via the first switch element T1 of the green subpixel G8. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G8. Similarly, when a gate signal is applied to the gate line GL16, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B8 and the first capacitor C1 of the blue subpixel B8 via the first switch element T1 of the blue subpixel B8. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B8.

[0135] 22 in the period from time t1 to t17 based on the gate line designation signal GL_Num from the scheduler 560. The data driver 300 writes data signals to the green subpixel G and the red subpixel R via the shared data line DL1 in response to the gate signals applied to the gate lines GL1 to GL16 in the period from time t1 to t17. Furthermore, the data driver 300 writes data signals to the white subpixel W and the blue subpixel B via the shared data line DL2 in response to the gate signals applied to the gate lines GL1 to GL16 in the period from time t1 to t17.

[0136] According to the timing diagram shown in Fig. 22, the data driver 300 writes data signals to the green subpixels G1-G8, the red subpixels R1-R8, the white subpixels W1-W8, and the blue subpixels B1-B8 in the pixel rows 1301-1308 in the order shown in Fig. 21. That is, when scanning the subpixel region shown in Fig. 21, the subpixels of each color are alternately scanned two rows at a time, thereby reducing the time difference in writing image data between the subpixels arranged in the same row. Therefore, according to the present invention, when displaying dissimilar regions between pixel rows in a display device using a DRD, it is possible to suppress degradation of display image quality caused by the time difference in writing image data between the subpixels arranged in the same row.

[0137] FIG. 23 is a schematic diagram showing the order in which subpixels of the display device according to this embodiment are scanned. FIG. 23 shows four columns of subpixels in pixel rows 1309-1316 shown in FIG. 20. Specifically, FIG. 23 shows green subpixels G9-G16 and red subpixels R9-R16 sharing the data line DL1, and white subpixels W9-W16 and blue subpixels B9-B16 sharing the data line DL2. The similarity determination unit 550 has determined that the image data (image signals) of pixel rows 1310-1312 are similar to the image data of the pixel row immediately above in both odd-numbered and even-numbered columns. Thus, the values ​​of signals RES_O and RES_E for pixel rows 1310-1312 are all 1. On the other hand, the image data of pixel row 1309 is not similar to the image data of pixel row 1308 in both odd-numbered and even-numbered columns, so the values ​​of signals RES_O and RES_E for pixel row 1309 are 0. The similarity determination unit 550 has determined that the image data (image signals) of the pixel rows 1314 to 1316 are similar to the image data of the pixel row immediately above in both odd and even columns. Therefore, the values ​​of the signals RES_O and RES_E for the pixel rows 1314 to 1316 are all 1. On the other hand, the image data of the pixel row 1313 is not similar to the image data of the pixel row 1312 in both odd and even columns, so the values ​​of the signals RES_O and RES_E for the pixel row 1313 are 0. The scheduler 560 generates an input register selection signal IRSS, an input enable signal VALID, and an output register selection signal ORSS based on the received signals RES_O and RES_E. The scheduler 560 transmits the generated input register selection signal IRSS, input enable signal VALID, and output register selection signal ORSS to the data driver 300. The data driver 300 transmits image data (image signals) to the green sub-pixels G9 to G16, the red sub-pixels R9 to R16, the white sub-pixels W9 to W16, and the blue sub-pixels B9 to B16 in an order designated by the received output register selection signal ORSS.

[0138] As shown in FIG. 23, in pixel rows 1309 to 1316, the green subpixels G and the red subpixels R are scanned in the following order. First, the green subpixel G9 is scanned, followed by the green subpixel G10, which is disposed one row below the green subpixel G9. Then, the red subpixel R9, which is in the same row as the green subpixel G9 and shares the data line DL1 with the green subpixel G9, but is included in a pixel column different from the pixel column of the green subpixel G, is scanned. Then, the red subpixel R10, which is disposed one row below the red subpixel R9, is scanned. Then, the red subpixel R11, which is disposed one row below the red subpixel R10, is scanned. Then, the red subpixel R12, which is disposed one row below the red subpixel R11, is scanned. Then, the green subpixel G11, which is in the same row as the red subpixel R11 and shares the data line DL1 with the red subpixel R11, but is included in a pixel column different from the pixel column of the red subpixel R, is scanned. Then, the green subpixel G12 arranged in one row below the green subpixel G11 is scanned. Then, the green subpixel G13 arranged in one row below the green subpixel G12 is scanned. Then, the green subpixel G14 arranged in one row below the green subpixel G13 is scanned. Then, the red subpixel R13, which is in the same row as the green subpixel G13 and shares the data line DL1, and is included in a pixel column different from the pixel column of the green subpixel G, is scanned. Then, the red subpixel R14 arranged in one row below the red subpixel R13 is scanned. Then, the red subpixel R15 arranged in one row below the red subpixel R14 is scanned. Then, the red subpixel R16 arranged in one row below the red subpixel R15 is scanned. Then, the green subpixel G15, which is in the same row as the red subpixel R15 and shares the data line DL1, and is included in a pixel column different from the pixel column of the red subpixel R, is scanned. After that, the green subpixel G16 arranged in the row below the green subpixel G15 is scanned.

[0139] As shown in FIG. 23, in pixel rows 1309 to 1316, the white subpixels W and blue subpixels B are scanned in the following order. First, the blue subpixel B9 is scanned, followed by the blue subpixel B10, which is disposed one row below the blue subpixel B9. Then, the white subpixel W9, which shares the data line DL2 with the blue subpixel B9 and is included in a pixel column different from the pixel column of the blue subpixel B, is scanned. Then, the white subpixel W10, which is disposed one row below the white subpixel W9, is scanned. Then, the white subpixel W11, which is disposed one row below the white subpixel W10, is scanned. Then, the white subpixel W12, which is disposed one row below the white subpixel W11, is scanned. Then, the blue subpixel B11, which shares the data line DL2 with the white subpixel W11 and is included in a pixel column different from the pixel column of the white subpixel W, is scanned. Then, the blue subpixel B12 arranged in one row below the blue subpixel B11 is scanned. Then, the blue subpixel B13 arranged in one row below the blue subpixel B12 is scanned. Then, the blue subpixel B14 arranged in one row below the blue subpixel B13 is scanned. Then, the white subpixel W13, which shares the data line DL2 in the same row as the blue subpixel B13 and is included in a pixel column different from the pixel column of the blue subpixel B, is scanned. Then, the white subpixel W14 arranged in one row below the white subpixel W13 is scanned. Then, the white subpixel W15 arranged in one row below the white subpixel W14 is scanned. Then, the white subpixel W16 arranged in one row below the white subpixel W15 is scanned. Then, the blue subpixel B15, which shares the data line DL2 in the same row as the white subpixel W15 and is included in a pixel column different from the pixel column of the white subpixel W, is scanned. Then, the blue subpixel B16 arranged in the row below the blue subpixel B15 is scanned.

[0140] In this embodiment, the similarity determination unit 550 determines that the image data of pixel rows 1309 to 1312 are similar. The similarity determination unit 550 also determines that the image data of pixel rows 1313 to 1316 are similar. Based on these determinations, the scheduler 560 generates an input register selection signal IRSS, an input enable signal VALID, and an output register selection signal ORSS to alternately scan four rows of subpixels of each color, and transmits each of the generated signals to the data driver 300. The data driver 300 writes image data to the green subpixels G9 to G16, the red subpixels R9 to R16, the white subpixels W9 to W16, and the blue subpixels B9 to B16 in the order specified by the received output register selection signal ORSS.

[0141] In this embodiment, in pixel rows 1309-1312 and pixel rows 1313-1316 that form an area in which image data are similar to each other, the number of rows in which sub-pixels of the same color are scanned consecutively is increased to reduce the frequency of discontinuity in the signal (voltage) of the output image data. Specifically, in this embodiment, the sub-pixels of each color are alternately scanned in groups of four rows to reduce the frequency of discontinuity in the signal (voltage) of the output image data. For example, in the sub-pixel area shown in FIG. 21, when the green sub-pixels G1-G8 and the red sub-pixels R1-R8 connected to the data line DL1 are scanned, the color of the scanned sub-pixels is changed eight times. Similarly, in the sub-pixel area shown in FIG. 21, when the white sub-pixels W1-W8 and the blue sub-pixels B1-B8 connected to the data line DL2 are scanned, the color of the scanned sub-pixels is changed eight times. That is, when scanning the region of the subpixels shown in FIG. 21, discontinuity in the signal (voltage) of the image data transmitted by the data line DL1 and the data line DL2 may occur eight times. On the other hand, in the region of the subpixels shown in FIG. 23, when the green subpixels G9 to G16 and the red subpixels R9 to R16 connected to the data line DL1 are scanned, the color of the scanned subpixels is changed only four times. Similarly, in the region of the subpixels shown in FIG. 23, when the white subpixels W9 to W16 and the blue subpixels B9 to B16 connected to the data line DL2 are scanned, the color of the scanned subpixels is changed only four times. That is, when scanning the region of the subpixels shown in FIG. 23, discontinuity in the signal (voltage) of the image data transmitted by the data line DL1 and the data line DL2 may be reduced to four times. Therefore, the display device using the DRD drive according to the present invention can reduce power consumption when writing image data to the subpixels.

[0142] In addition, compared to the operation of writing image data to subpixels shown in Fig. 21, the operation of writing image data to subpixels shown in Fig. 23 has a larger time difference in writing image data to multiple subpixels arranged in the same row. However, the image data of pixel rows 1309 to 1312 and pixel rows 1313 to 1316 are similar to each other. Therefore, the influence of the time difference in writing image data to multiple subpixels arranged in the same row on the image quality of the area shown in Fig. 23 is smaller than the influence on the image quality of the area shown in Fig. 21. Therefore, the display device 10 using the DRD driving according to the present invention can reduce power consumption while suppressing deterioration in display image quality.

[0143] FIG. 24 is a timing diagram of gate signals applied to gate lines GL17 to GL32 by the gate driver 200 when scanning the sub-pixels of pixel rows 1309 to 1316 shown in FIG. 20 of the display device 10 of this embodiment in the order shown in FIG. 23.

[0144] In the period from time t18 to t19, a gate signal is applied to the gate line GL18 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL18, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G9 and the first capacitor C1 of the green subpixel G9 via the first switch element T1 of the green subpixel G9. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G9. Similarly, when a gate signal is applied to the gate line GL18, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B9 and the first capacitor C1 of the blue subpixel B9 via the first switch element T1 of the blue subpixel B9. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B9.

[0145] In the period from time t19 to t20, a gate signal is applied to the gate line GL20 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL20, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G10 and the first capacitor C1 of the green subpixel G10 via the first switch element T1 of the green subpixel G10. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G10. Similarly, when a gate signal is applied to the gate line GL20, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B10 and the first capacitor C1 of the blue subpixel B10 via the first switch element T1 of the blue subpixel B10. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B10.

[0146] In the period from time t20 to t21, a gate signal is applied to the gate line GL17 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL17, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R9 and the first capacitor C1 of the red subpixel R9 via the first switch element T1 of the red subpixel R9. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R9. Similarly, when a gate signal is applied to the gate line GL17, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W9 and the first capacitor C1 of the white subpixel W9 via the first switch element T1 of the white subpixel W9. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W9.

[0147] In the period from time t21 to t22, a gate signal is applied to the gate line GL19 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL19, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R10 and the first capacitor C1 of the red subpixel R10 via the first switch element T1 of the red subpixel R10. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R10. Similarly, when the gate signal is applied to the gate line GL19, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W10 and the first capacitor C1 of the white subpixel W10 via the first switch element T1 of the white subpixel W10. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W10.

[0148] In the period from time t22 to t23, a gate signal is applied to the gate line GL21 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL21, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R11 and the first capacitor C1 of the red subpixel R11 via the first switch element T1 of the red subpixel R11. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R11. Similarly, when the gate signal is applied to the gate line GL21, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W11 and the first capacitor C1 of the white subpixel W11 via the first switch element T1 of the white subpixel W11. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W11.

[0149] In the period from time t23 to t24, a gate signal is applied to the gate line GL23 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL23, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R12 and the first capacitor C1 of the red subpixel R12 via the first switch element T1 of the red subpixel R12. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R12. Similarly, when the gate signal is applied to the gate line GL23, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W12 and the first capacitor C1 of the white subpixel W12 via the first switch element T1 of the white subpixel W12. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W12.

[0150] In the period from time t24 to t25, a gate signal is applied to the gate line GL22 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL22, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G11 and the first capacitor C1 of the green subpixel G11 via the first switch element T1 of the green subpixel G11. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G11. Similarly, when a gate signal is applied to the gate line GL22, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B11 and the first capacitor C1 of the blue subpixel B11 via the first switch element T1 of the blue subpixel B11. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B11.

[0151] In the period from time t25 to t26, a gate signal is applied to the gate line GL24 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL24, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G12 and the first capacitor C1 of the green subpixel G12 via the first switch element T1 of the green subpixel G12. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G12. Similarly, when a gate signal is applied to the gate line GL24, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B12 and the first capacitor C1 of the blue subpixel B12 via the first switch element T1 of the blue subpixel B12. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B12.

[0152] In the period from time t26 to t27, a gate signal is applied to the gate line GL26 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL26, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G13 and the first capacitor C1 of the green subpixel G13 via the first switch element T1 of the green subpixel G13. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G13. Similarly, when a gate signal is applied to the gate line GL26, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B13 and the first capacitor C1 of the blue subpixel B13 via the first switch element T1 of the blue subpixel B13. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B13.

[0153] In the period from time t27 to t28, a gate signal is applied to the gate line GL28 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL28, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G14 and the first capacitor C1 of the green subpixel G14 via the first switch element T1 of the green subpixel G14. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G14. Similarly, when a gate signal is applied to the gate line GL28, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B14 and the first capacitor C1 of the blue subpixel B14 via the first switch element T1 of the blue subpixel B14. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B14.

[0154] In the period from time t28 to t29, a gate signal is applied to the gate line GL25 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL25, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R13 and the first capacitor C1 of the red subpixel R13 via the first switch element T1 of the red subpixel R13. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R13. Similarly, when the gate signal is applied to the gate line GL25, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W13 and the first capacitor C1 of the white subpixel W13 via the first switch element T1 of the white subpixel W13. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W13.

[0155] In the period from time t29 to t30, a gate signal is applied to the gate line GL27 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL27, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R14 and the first capacitor C1 of the red subpixel R14 via the first switch element T1 of the red subpixel R14. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R14. Similarly, when a gate signal is applied to the gate line GL27, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W14 and the first capacitor C1 of the white subpixel W14 via the first switch element T1 of the white subpixel W14. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W14.

[0156] In the period from time t30 to t31, a gate signal is applied to the gate line GL29 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL29, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R15 and the first capacitor C1 of the red subpixel R15 via the first switch element T1 of the red subpixel R15. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R15. Similarly, when the gate signal is applied to the gate line GL29, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W15 and the first capacitor C1 of the white subpixel W15 via the first switch element T1 of the white subpixel W15. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W15.

[0157] In the period from time t31 to t32, a gate signal is applied to the gate line GL31 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL31, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R16 and the first capacitor C1 of the red subpixel R16 via the first switch element T1 of the red subpixel R16. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R16. Similarly, when the gate signal is applied to the gate line GL31, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W16 and the first capacitor C1 of the white subpixel W16 via the first switch element T1 of the white subpixel W16. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W16.

[0158] In the period from time t32 to t33, a gate signal is applied to the gate line GL30 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL30, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G15 and the first capacitor C1 of the green subpixel G15 via the first switch element T1 of the green subpixel G15. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G15. Similarly, when a gate signal is applied to the gate line GL30, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B15 and the first capacitor C1 of the blue subpixel B15 via the first switch element T1 of the blue subpixel B15. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B15.

[0159] In the period from time t33 to t34, a gate signal is applied to the gate line GL32 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL32, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G16 and the first capacitor C1 of the green subpixel G16 via the first switch element T1 of the green subpixel G16. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G16. Similarly, when a gate signal is applied to the gate line GL32, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B16 and the first capacitor C1 of the blue subpixel B16 via the first switch element T1 of the blue subpixel B16. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B16.

[0160] 24 in the period from time t18 to t34 based on the gate line designation signal GL_Num from the scheduler 560. The data driver 300 writes data signals to the green subpixel G and the red subpixel R via the shared data line DL1 in response to the gate signals applied to the gate lines GL17 to GL32 in the period from time t18 to t34. Furthermore, the data driver 300 writes data signals to the white subpixel W and the blue subpixel B via the shared data line DL2 in response to the gate signals applied to the gate lines GL17 to GL32 in the period from time t18 to t34. According to the timing diagram shown in FIG. 24, the data driver 300 writes data signals to the green subpixels G9 to G16, red subpixels R9 to R16, white subpixels W9 to W16 and blue subpixels B9 to B16 in the pixel rows 1309 to 1316 in the order shown in FIG.

[0161] According to the timing diagram shown in Fig. 24, the data driver 300 writes data signals to the green subpixels G9 to G16, the red subpixels R9 to R16, the white subpixels W9 to W16, and the blue subpixels B9 to B16 in the pixel rows 1309 to 1316 in the order shown in Fig. 23. That is, when scanning the subpixel region shown in Fig. 23, the discontinuity of the image data signals (voltages) transmitted by the data lines DL1 and DL2 can be reduced to four times each. Therefore, the display device using the DRD driving according to the present invention can reduce the power consumption when writing image data to the subpixels.

[0162] FIG. 25 is a schematic diagram showing the order in which subpixels of the display device according to this embodiment are scanned. FIG. 25 shows four columns of subpixels in pixel rows 1317-1324 shown in FIG. 20. Specifically, FIG. 25 shows green subpixels G17-G24 and red subpixels R17-R24 sharing the data line DL1, and white subpixels W17-W24 and blue subpixels B17-B24 sharing the data line DL2. The similarity determination unit 550 has determined that the image data (image signals) of pixel rows 1318-1324 are similar to the image data of the pixel row immediately above in both odd-numbered and even-numbered columns. Thus, the values ​​of signals RES_O and RES_E for pixel rows 1318-1324 are all 1. On the other hand, the image data of pixel row 1317 is not similar to the image data of pixel row 1308 in both odd-numbered and even-numbered columns, so the values ​​of signals RES_O and RES_E for pixel row 1309 are 0. The scheduler 560 generates an input register selection signal IRSS, an input enable signal VALID, and an output register selection signal ORSS based on the received signals RES_O and RES_E. The scheduler 560 transmits the generated input register selection signal IRSS, input enable signal VALID, and output register selection signal ORSS to the data driver 300. The data driver 300 transmits image data (image signals) to the green sub-pixels G17 to G24, the red sub-pixels R17 to R24, the white sub-pixels W17 to W24, and the blue sub-pixels B17 to B24 in an order specified by the received output register selection signal ORSS.

[0163] As shown in FIG. 25, in pixel rows 1317 to 1324, the green subpixels G and the red subpixels R are scanned in the following order: First, the green subpixel G17 is scanned, followed by the green subpixel G18 arranged in the row below the green subpixel G17. Then, the green subpixel G19 arranged in the row below the green subpixel G18 is scanned. Then, the green subpixel G20 arranged in the row below the green subpixel G19 is scanned. Then, the red subpixel R17, which is in the same row as the green subpixel G17 and shares the data line DL1, but is included in a pixel column different from the pixel column of the green subpixel G, is scanned. Then, the red subpixel R18 arranged in the row below the red subpixel R17 is scanned. Then, the red subpixel R19 arranged in the row below the red subpixel R18 is scanned. Then, the red subpixel R20 arranged in the row below the red subpixel R19 is scanned. Then, the red subpixel R21 arranged in the row below the red subpixel R20 is scanned. Then, the red subpixel R22 arranged in the row below the red subpixel R21 is scanned. Then, the red subpixel R23 arranged in the row below the red subpixel R22 is scanned. Then, the red subpixel R24 arranged in the row below the red subpixel R23 is scanned. Then, the green subpixel G21, which shares the data line DL1 in the same row as the red subpixel R21 and is included in a pixel column different from the pixel column of the red subpixel R, is scanned. Then, the green subpixel G22 arranged in the row below the green subpixel G21 is scanned. Then, the green subpixel G23 arranged in the row below the green subpixel G22 is scanned. Then, the green subpixel G24 arranged in the row below the green subpixel G23 is scanned.

[0164] As shown in FIG. 25, in pixel rows 1317 to 1324, the white subpixel W and the blue subpixel B are scanned in the following order. First, the blue subpixel B17 is scanned, and then the blue subpixel B18 arranged in the row below the blue subpixel B17 is scanned. Then, the blue subpixel B19 arranged in the row below the blue subpixel B18 is scanned. Then, the blue subpixel B20 arranged in the row below the blue subpixel B19 is scanned. Then, the white subpixel W17, which shares the data line DL2 with the blue subpixel B17 and is included in a pixel column different from the pixel column of the blue subpixel B, is scanned. Then, the white subpixel W18 arranged in the row below the white subpixel W17 is scanned. Then, the white subpixel W19 arranged in the row below the white subpixel W18 is scanned. Then, the white subpixel W20 arranged in the row below the white subpixel W19 is scanned. Then, the white subpixel W21 arranged in the row below the white subpixel W20 is scanned. Then, the white subpixel W22 arranged in the row below the white subpixel W21 is scanned. Then, the white subpixel W23 arranged in the row below the white subpixel W22 is scanned. Then, the white subpixel W24 arranged in the row below the white subpixel W23 is scanned. Then, the blue subpixel B21, which shares the data line DL2 in the same row as the white subpixel W21 and is included in a pixel column different from the pixel column of the white subpixel W, is scanned. Then, the blue subpixel B22 arranged in the row below the blue subpixel B21 is scanned. Then, the blue subpixel B23 arranged in the row below the blue subpixel B22 is scanned. Then, the blue subpixel B24 arranged in the row below the blue subpixel B23 is scanned.

[0165] In this embodiment, the similarity determination unit 550 determines that the image data for pixel rows 1317 to 1324 are similar. Based on this determination, the scheduler 560 generates an input register selection signal IRSS, an input enable signal VALID, and an output register selection signal ORSS to alternately scan eight rows of subpixels of each color, and transmits each of the generated signals to the data driver 300. The data driver 300 writes image data for the green subpixels G17 to G24, the red subpixels R17 to R24, the white subpixels W17 to W24, and the blue subpixels B17 to B24 in the order specified by the received output register selection signal ORSS.

[0166] In this embodiment, in pixel rows 1317-1324 constituting an area in which image data are similar to each other, the number of rows in which sub-pixels of the same color are scanned consecutively is further increased to further reduce the frequency of discontinuity in the signal (voltage) of the output image data. Specifically, in this embodiment, sub-pixels of each color are alternately scanned by eight rows, thereby further reducing the frequency of discontinuity in the signal (voltage) of the output image data. For example, in the sub-pixel area shown in FIG. 23, when the green sub-pixels G9-G16 and the red sub-pixels R9-R16 connected to the data line DL1 are scanned, the color of the scanned sub-pixels is changed four times. Similarly, in the sub-pixel area shown in FIG. 23, when the white sub-pixels W9-W16 and the blue sub-pixels B9-B16 connected to the data line DL2 are scanned, the color of the scanned sub-pixels is changed four times. That is, when the area in which the sub-pixels shown in FIG. 23 are configured are scanned, discontinuity in the signal (voltage) of the image data transmitted by the data lines DL1 and DL2 may occur four times. On the other hand, in the subpixel region shown in FIG. 25, when the green subpixels G17-G24 and the red subpixels R17-R24 connected to the data line DL1 are scanned, the color of the scanned subpixels is changed only twice. Similarly, in the subpixel region shown in FIG. 25, when the white subpixels W17-W24 and the blue subpixels B17-B24 connected to the data line DL2 are scanned, the color of the scanned subpixels is changed only twice. That is, when the subpixel region shown in FIG. 25 is scanned, the discontinuity of the image data signals (voltages) transmitted by the data lines DL1 and DL2 can be reduced to two times each. Therefore, the display device using the DRD driving according to the present invention can further reduce the power consumption when writing image data to the subpixels.

[0167] 21 and 23, the time difference between the writing of image data to subpixels shown in FIG. 25 is larger for multiple subpixels in the same row. However, the image data from pixel rows 1317 to 1324 are similar to each other. Therefore, the influence of the time difference between the writing of image data to multiple subpixels in the same row on the image quality of the region shown in FIG. 25 is smaller than the influence of the time difference between the writing of image data to multiple subpixels in the same row on the image quality of the region shown in FIG. 21 and 23. Therefore, the display device 10 using the DRD driving according to the present invention can reduce power consumption while suppressing deterioration in display image quality.

[0168] When the image displayed on the display panel 100 is a still image, the degradation of display quality due to the time difference in writing image data to multiple sub-pixels arranged in the same row can be ignored. Therefore, when a still image is displayed on the display device 10, the number of rows for continuously scanning sub-pixels of the same color can be made the same as the number of pixel rows included in the display panel. For example, when the display device 10 is composed of 2160 rows of pixels, the sub-pixels of the same color can be continuously scanned across 2160 rows. This configuration further reduces the frequency of discontinuities in the signal (voltage) of the output image data, thereby reducing the power consumption of the display device 10.

[0169] Figure 26 is a timing diagram of gate signals applied to gate lines GL33 to GL48 by the gate driver 200 when scanning the sub-pixels of pixel rows 1317 to 1324 shown in Figure 20 of the display device 10 of this embodiment in the order shown in Figure 25.

[0170] In the period from time t35 to t36, a gate signal is applied to the gate line GL34 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL34, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G17 and the first capacitor C1 of the green subpixel G17 via the first switch element T1 of the green subpixel G17. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G17. Similarly, when a gate signal is applied to the gate line GL34, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B17 and the first capacitor C1 of the blue subpixel B17 via the first switch element T1 of the blue subpixel B17. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B17.

[0171] In the period from time t36 to t37, a gate signal is applied to the gate line GL36 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL36, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G18 and the first capacitor C1 of the green subpixel G18 via the first switch element T1 of the green subpixel G18. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G18. Similarly, when a gate signal is applied to the gate line GL36, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B18 and the first capacitor C1 of the blue subpixel B18 via the first switch element T1 of the blue subpixel B18. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B18.

[0172] In the period from time t37 to t38, a gate signal is applied to the gate line GL38 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL38, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G19 and the first capacitor C1 of the green subpixel G19 via the first switch element T1 of the green subpixel G19. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G19. Similarly, when a gate signal is applied to the gate line GL38, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B19 and the first capacitor C1 of the blue subpixel B19 via the first switch element T1 of the blue subpixel B19. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B19.

[0173] In a period from time t38 to t39, a gate signal is applied to the gate line GL40 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL40, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G20 and the first capacitor C1 of the green subpixel G20 via the first switch element T1 of the green subpixel G20. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G20. Similarly, when a gate signal is applied to the gate line GL40, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B20 and the first capacitor C1 of the blue subpixel B20 via the first switch element T1 of the blue subpixel B20. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B20.

[0174] In the period from time t39 to t40, a gate signal is applied to the gate line GL33 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL33, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R17 and the first capacitor C1 of the red subpixel R11 via the first switch element T1 of the red subpixel R17. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R17. Similarly, when the gate signal is applied to the gate line GL33, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W17 and the first capacitor C1 of the white subpixel W17 via the first switch element T1 of the white subpixel W17. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W17.

[0175] In the period from time t40 to t41, a gate signal is applied to the gate line GL35 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL35, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R18 and the first capacitor C1 of the red subpixel R18 via the first switch element T1 of the red subpixel R18. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R18. Similarly, when a gate signal is applied to the gate line GL35, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W18 and the first capacitor C1 of the white subpixel W18 via the first switch element T1 of the white subpixel W18. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W18.

[0176] In the period from time t41 to t42, a gate signal is applied to the gate line GL37 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL37, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R19 and the first capacitor C1 of the red subpixel R19 via the first switch element T1 of the red subpixel R19. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R19. Similarly, when a gate signal is applied to the gate line GL37, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W19 and the first capacitor C1 of the white subpixel W19 via the first switch element T1 of the white subpixel W19. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W19.

[0177] In the period from time t42 to t43, a gate signal is applied to the gate line GL39 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL39, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R20 and the first capacitor C1 of the red subpixel R20 via the first switch element T1 of the red subpixel R20. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R20. Similarly, when the gate signal is applied to the gate line GL39, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W20 and the first capacitor C1 of the white subpixel W20 via the first switch element T1 of the white subpixel W20. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W20.

[0178] In the period from time t43 to t44, a gate signal is applied to the gate line GL41 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL41, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R21 and the first capacitor C1 of the red subpixel R21 via the first switch element T1 of the red subpixel R21. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R21. Similarly, when the gate signal is applied to the gate line GL41, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W21 and the first capacitor C1 of the white subpixel W21 via the first switch element T1 of the white subpixel W21. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W21.

[0179] In the period from time t44 to t45, a gate signal is applied to the gate line GL43 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL43, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R22 and the first capacitor C1 of the red subpixel R22 via the first switch element T1 of the red subpixel R22. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R22. Similarly, when the gate signal is applied to the gate line GL43, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W22 and the first capacitor C1 of the white subpixel W22 via the first switch element T1 of the white subpixel W22. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W22.

[0180] In the period from time t45 to t46, a gate signal is applied to the gate line GL45 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL45, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R23 and the first capacitor C1 of the red subpixel R23 via the first switch element T1 of the red subpixel R23. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R23. Similarly, when the gate signal is applied to the gate line GL45, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W23 and the first capacitor C1 of the white subpixel W23 via the first switch element T1 of the white subpixel W23. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W23.

[0181] In the period from time t46 to t47, a gate signal is applied to the gate line GL47 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL47, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R24 and the first capacitor C1 of the red subpixel R24 via the first switch element T1 of the red subpixel R24. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R24. Similarly, when a gate signal is applied to the gate line GL47, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W24 and the first capacitor C1 of the white subpixel W24 via the first switch element T1 of the white subpixel W24. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W24.

[0182] In the period from time t47 to t48, a gate signal is applied to the gate line GL42 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL42, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G21 and the first capacitor C1 of the green subpixel G21 via the first switch element T1 of the green subpixel G21. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G21. Similarly, when a gate signal is applied to the gate line GL42, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B21 and the first capacitor C1 of the blue subpixel B21 via the first switch element T1 of the blue subpixel B21. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B21.

[0183] In the period from time t48 to t49, a gate signal is applied to the gate line GL44 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL44, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G22 and the first capacitor C1 of the green subpixel G22 via the first switch element T1 of the green subpixel G22. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G22. Similarly, when a gate signal is applied to the gate line GL44, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B22 and the first capacitor C1 of the blue subpixel B22 via the first switch element T1 of the blue subpixel B22. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B22.

[0184] In the period from time t49 to t50, a gate signal is applied to the gate line GL46 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL46, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G23 and the first capacitor C1 of the green subpixel G23 via the first switch element T1 of the green subpixel G23. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G23. Similarly, when the gate signal is applied to the gate line GL46, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B23 and the first capacitor C1 of the blue subpixel B23 via the first switch element T1 of the blue subpixel B23. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B23.

[0185] In the period from time t50 to t51, a gate signal is applied to the gate line GL48 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL48, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G24 and the first capacitor C1 of the green subpixel G24 via the first switch element T1 of the green subpixel G24. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G24. Similarly, when a gate signal is applied to the gate line GL48, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B24 and the first capacitor C1 of the blue subpixel B24 via the first switch element T1 of the blue subpixel B24. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B24.

[0186] 25 in the period from time t35 to t51 based on the gate line designation signal GL_Num from the scheduler 560. The data driver 300 writes data signals to the green subpixel G and the red subpixel R via the shared data line DL1 in response to the gate signals applied to the gate lines GL33 to GL48 in the period from time t35 to t51. Furthermore, the data driver 300 writes data signals to the white subpixel W and the blue subpixel B via the shared data line DL2 in response to the gate signals applied to the gate lines GL33 to GL48 in the period from time t35 to t51. According to the timing diagram shown in FIG. 26, the data driver 300 writes data signals to the green subpixels G17 to G24, red subpixels R17 to R24, white subpixels W17 to W24, and blue subpixels B17 to B24 in the pixel rows 1317 to 1324 in the order shown in FIG.

[0187] According to the timing diagram shown in Fig. 26, the data driver 300 writes data signals to the green subpixels G17-G24, the red subpixels R17-R24, the white subpixels W17-W24, and the blue subpixels B17-B24 in the pixel rows 1317-1324 in the order shown in Fig. 25. That is, when scanning the subpixel region shown in Fig. 25, the discontinuity of the image data signals (voltages) transmitted by the data lines DL1 and DL2 can be reduced to two times each. Therefore, the display device using the DRD driving according to the present invention can further reduce the power consumption when writing image data to the subpixels.

[0188] FIG. 27 is a graph showing the relationship between the scanning time of the display device 10 according to this embodiment and the row of the sub-pixel to which the data signal is written when the display image shown in FIG. 20 is displayed.

[0189] In this embodiment, the similarity determination unit 550 determines that the image data of the pixel rows 1301 to 1308 are not similar. Based on this determination, the data driver 300 alternately scans two rows of green subpixels G and two rows of red subpixels R in the image region of the pixel rows 1301 to 1308. Similarly, the data driver 300 alternately scans two rows of white subpixels W and two rows of blue subpixels B in the image region of the pixel rows 1301 to 1308. As a result, in the image region of the pixel rows 1301 to 1308, the time difference in writing image data between the green subpixels G and the red subpixels R arranged in the same row is 1 [au] as shown in FIG. 27. Similarly, in the image region of the pixel rows 1301 to 1308, the time difference in writing image data between the white subpixels W and the blue subpixels B arranged in the same row is 1 [au] as shown in FIG. 27.

[0190] The similarity determination unit 550 also determines that the image data of the pixel rows 1309 to 1312 and the pixel rows 1313 to 1316 are similar. Based on this determination, the data driver 300 alternately scans four rows of green subpixels G and four rows of red subpixels R in the image region of the pixel rows 1309 to 1316. Similarly, the data driver 300 alternately scans four rows of white subpixels W and four rows of blue subpixels B in the image region of the pixel rows 1309 to 1316. As a result, the time difference in writing image data between the green subpixels G and the red subpixels R arranged in the same row in the image region of the pixel rows 1309 to 1316 is 2 [au] as shown in FIG. 27. Similarly, the time difference in writing image data between the white subpixels W and the blue subpixels B arranged in the same row in the image region of the pixel rows 1309 to 1316 is 2 [au] as shown in FIG. 27.

[0191] The similarity determination unit 550 also determines that the image data from pixel rows 1317 to 1324 are similar. Based on this determination, the data driver 300 alternately scans eight rows of green subpixels G and eight rows of red subpixels R in the image region from pixel rows 1317 to 1324. Similarly, the data driver 300 alternately scans eight rows of white subpixels W and eight rows of blue subpixels B in the image region from pixel rows 1317 to 1324. As a result, the time difference between the writing of image data between the green subpixels G and the red subpixels R arranged in the same row in the image region from pixel rows 1317 to 1324 is 4 [au] as shown in FIG. 27. Similarly, the time difference between the writing of image data between the white subpixels W and the blue subpixels B arranged in the same row in the image region from pixel rows 1317 to 1324 is 4 [au] as shown in FIG. 27.

[0192] In this embodiment, the similarity of image data between pixel rows is determined, and the number of rows for continuously scanning sub-pixels of the same color is determined based on the determined similarity. In a region of a pixel row where the image data between the pixel rows are not similar, the number of rows for continuously scanning sub-pixels of the same color is set to be small. As a result, the time difference in writing image data between sub-pixels of other colors connected to a shared data line and arranged in the same row is reduced. Therefore, according to the present invention, when displaying a region where the pixel rows are not similar in a display device using a DRD, it is possible to suppress a deterioration in display image quality caused by the time difference in writing image data between a plurality of sub-pixels arranged in the same row. On the other hand, in a region of a pixel row where the image data between the pixel rows are similar, the influence on the display image quality caused by the time difference in writing image data between sub-pixels arranged in the same row is small. Therefore, in a region of a pixel row where the image data between the pixel rows are similar, the number of rows for continuously scanning sub-pixels of the same color is set to be large. That is, in a region of a pixel row where the image data between the pixel rows are similar, the discontinuity of the signal (voltage) of the image data transmitted through the data line is reduced. Therefore, the display device 10 using the DRD driving method according to the present invention can reduce power consumption while suppressing degradation in display image quality.

[0193] [Second embodiment] In this embodiment, a modified example of the similarity determination unit 550 according to the first embodiment will be described. The configurations and functions of a first difference calculation unit 551, a second difference calculation unit 552, a first accumulator 553, a second accumulator 554, a first threshold determination unit 557, a second threshold determination unit 558, and a reset determination unit 559 are similar to those of the first embodiment, and therefore description thereof will be omitted.

[0194] 28 is a block diagram showing a schematic configuration of the similarity determination section 550 according to this embodiment. The similarity determination section 550 according to this embodiment further includes a first threshold adjustment section 555 and a second threshold adjustment section 556.

[0195] The first threshold adjustment unit 555 receives an integrated value Sum_O of the difference between the RGBW value of the xth row related to the odd-numbered column and the RGBW value of the x-1th row related to the odd-numbered column from the first integration unit 553. The first threshold adjustment unit 555 adjusts the threshold set in the first threshold determination unit 557 to an appropriate value based on the received integrated value Sum_O. For example, the first threshold adjustment unit 555 adjusts the threshold set in the first threshold determination unit 557 to an optimal value using a machine learning method based on a trained model using training data, a classification method by clustering analysis that derives an optimal threshold from the integrated value input to the similarity determination unit 550, or the like. The first threshold adjustment unit 555 transmits the threshold Th_O adjusted to the optimal value to the first threshold determination unit 557. When the first threshold determination unit 557 determines that the integrated value Sum_O received from the first accumulator 553 is less than the threshold value Th_O adjusted to the optimal value, it determines that the image data in the xth row related to the odd-numbered columns is similar to the image data in the x-1th row related to the odd-numbered columns. On the other hand, when the first threshold determination unit 557 determines that the integrated value Sum_O received from the first accumulator 553 is equal to or greater than the threshold value Th_O adjusted to the optimal value, it determines that the image data in the xth row related to the odd-numbered columns is not similar to the image data in the x-1th row related to the odd-numbered columns.

[0196] Similarly, the second threshold adjustment unit 556 receives an integrated value Sum_E of the difference between the RGBW value of the xth row related to the even-numbered column and the RGBW value of the x-1th row related to the even-numbered column from the second integration unit 554. The second threshold adjustment unit 556 adjusts the threshold set in the second threshold determination unit 558 to an appropriate value based on the received integrated value Sum_E. For example, the second threshold adjustment unit 556 adjusts the threshold set in the second threshold determination unit 558 to an optimal value using a machine learning method based on a trained model using training data, a classification method by clustering analysis that derives an optimal threshold from the integrated value input to the similarity determination unit 550, or the like. The second threshold adjustment unit 556 transmits the threshold Th_E adjusted to the optimal value to the second threshold determination unit 558. When the second threshold determination unit 558 determines that the integrated value Sum_E received from the second accumulator 554 is less than the threshold value Th_E adjusted to the optimal value, it determines that the image data of the xth row related to the even columns is similar to the image data of the x-1th row related to the even columns. On the other hand, when the second threshold determination unit 558 determines that the integrated value Sum_E received from the second accumulator 554 is equal to or greater than the threshold value Th_E adjusted to the optimal value, it determines that the image data of the xth row related to the even columns is not similar to the image data of the x-1th row related to the even columns.

[0197] In this embodiment, the similarity determination unit 550 includes the first threshold adjustment unit 555 and the second threshold adjustment unit 556, but the present invention is not limited to the above configuration. For example, the first threshold adjustment unit 555 and the second threshold adjustment unit 556 can be configured as a single threshold adjustment unit. In this case, the single threshold adjustment unit receives the integrated values ​​Sum_O and Sum_E of the differences related to the odd-numbered columns and the even-numbered columns from both the first integration unit 553 and the second integration unit 554. The single threshold adjustment unit adjusts the thresholds set in the first threshold determination unit 557 and the second threshold determination unit 558 to optimal values ​​based on the received integrated values. The single threshold adjustment unit transmits the thresholds Th_O and Th_E adjusted to the optimal values ​​to the first threshold determination unit 557 and the second threshold determination unit 558, respectively.

[0198] FIG. 29 is a block diagram showing an example of the configuration of the first threshold adjustment unit 555 and the second threshold adjustment unit 556 according to this embodiment. In this embodiment, the first threshold adjustment unit 555 includes a neural network that receives a learning integrated value Sum_Learn, a learning threshold Th_learn, and an integrated value Sum_O of the difference between the RGBW value of the xth row related to the odd-numbered column and the RGBW value of the x-1th row related to the odd-numbered column. The first threshold adjustment unit 555 calculates the learning integrated value Sum_Learn, the learning threshold Th_learn, and the integrated value Sum_O from, for example, various image data, and reads the calculated values ​​as learning data. The first threshold adjustment unit 555 weights the received learning data to generate a learned model. The first threshold adjustment unit 555 adjusts the threshold set in the first threshold determination unit 557 to a threshold TH_O adjusted to an optimal value based on the generated learned model. Similarly, the second threshold adjustment unit 556 includes a neural network that receives the learning integrated value Sum_Learn, the learning threshold Th_learn, and an integrated value Sum_E of the difference between the RGBW value of the xth row related to the even-numbered column and the RGBW value of the x-1th row related to the even-numbered column. The second threshold adjustment unit 556 reads the learning integrated value Sum_Learn, the learning threshold Th_learn, and the integrated value Sum_E as learning data. The second threshold adjustment unit 556 weights the received learning data to generate a learned model. The second threshold adjustment unit 556 adjusts the threshold set in the second threshold determination unit 558 to the threshold TH_E adjusted to an optimal value based on the generated learned model.

[0199] FIG. 30 is a graph showing an example of the threshold adjusted by the similarity determination unit 550 according to the present embodiment. In the example shown in FIG. 30, the integrated value SUM of the difference between the RGBW values ​​between each row in the upper and lower parts of the display panel 100 is smaller than the integrated value SUM of the difference in the center part of the display panel 100. That is, the image data between each row in the upper and lower parts of the display panel 100 is more similar than the image data between each row in the center part of the display panel 100. However, in the example shown in FIG. 30, the first threshold determination unit 557 and the second threshold determination unit 558 are set with a default threshold Th_OGL that is smaller than the integrated value SUM of the difference in the upper and lower parts of the display panel 100. Therefore, when the threshold is not adjusted, the first threshold determination unit 557 and the second threshold determination unit 558 determine that the image data written to each row of the display panel 100 is not similar across the entire region based on the default threshold Th_OGL. Based on the determinations of the first threshold determination unit 557 and the second threshold determination unit 558, the scheduler 560 transmits signals IRSS, VALID, and ORSS to the data driver 300 to reduce the number of rows in which subpixels of the same color are continuously scanned in order to suppress deterioration of the display image quality. As a result, the frequency of discontinuities in the signal (voltage) of the output image data increases, increasing the power consumption of the display device 10.

[0200] In this embodiment, the first threshold adjustment unit 555 and the second threshold adjustment unit 556 included in the similarity determination unit 550 adjust the default threshold Th_OGL set in the first threshold determination unit 557 and the second threshold determination unit 558 to the thresholds TH_O and TH_E adjusted to optimal values, respectively, based on a learned model generated based on learning data. As a result of the first threshold adjustment unit 555 and the second threshold adjustment unit 556 changing the default threshold Th_OGL to the thresholds TH_O and TH_E adjusted to optimal values, respectively, the first threshold determination unit 557 and the second threshold determination unit 558 determine that the image data between the rows in the upper and lower parts of the display panel 100 are similar. Based on the determinations of the first threshold determination unit 557 and the second threshold determination unit 558, the scheduler 560 transmits signals IRSS, VALID, and ORSS to the data driver 300 so as to increase the number of rows in which subpixels of the same color are continuously scanned in order to reduce power consumption. As a result, the frequency with which the signal (voltage) of the output image data becomes discontinuous decreases, reducing the power consumption of the display device 10. Therefore, according to this embodiment, the power consumption when the display device using the DRD driving writes image data to the sub-pixels can be further reduced.

[0201] [Third embodiment] In this embodiment, another modified example of the similarity determination unit 550 according to the first embodiment will be described. Among the configurations and functions of the first difference calculation unit 551, the second difference calculation unit 552, the first accumulator 553, the second accumulator 554, the first threshold determination unit 557, the second threshold determination unit 558, and the reset determination unit 559, descriptions of parts similar to those in the first embodiment will be omitted.

[0202] 31 is a block diagram showing a schematic configuration of the similarity determination section 550 according to this embodiment. The similarity determination section 550 according to this embodiment includes a first difference calculation section 551, a second difference calculation section 552, a first accumulator 553, a second accumulator 554, a first threshold determination section 557, a second threshold determination section 558, and a reset determination section 559.

[0203] The second difference calculation unit 552 receives image data RGBW_E(x) of the xth row related to the sub-pixel P arranged in the even-numbered columns from the row memory unit 520. The first difference calculation unit 551 also receives image data RGBW_O(x-1, x-2, ..., xk) of the x-1th row to a predetermined number of rows k related to the sub-pixel P arranged in the odd-numbered columns from the row memory unit 520 (k is a positive integer less than x, the same applies below). Each of the received image data RGBW_O(x-1, x-2, ..., xk) is image data from one row before to k rows before the image data RGBW_O(x), and is, for example, the RGBW values ​​of image data to be written to the green sub-pixel G and the white sub-pixel W arranged in the x-1th row to the xkth row. The first difference calculation unit 551 calculates a difference Diff_O(1) between the received image data RGBW_O(x) of the xth row and the image data RGBW_O(x-1) of the x-1th row, and transmits the calculation result to the first accumulation unit 553. Similarly, the first difference calculation unit 551 calculates differences Diff_O(2) to Diff_O(k) between the received image data RGBW_O(x) of the xth row and each of image data RGBW_O(x-2) to RGBW_O(xk) of the x-2th row to the xkth row, and transmits the calculation result to the first accumulation unit 553.

[0204] The first accumulator 553 receives data of differences Diff_O(1) to Diff_O(k) between the RGBW value of the xth row and the RGBW values ​​of the x-1th to xkth rows in each odd-numbered column from the first difference calculator 551. The first accumulator 553 accumulates the differences of the image data of each odd-numbered column received from the first difference calculator 551. For example, when the number of columns of odd-numbered sub-pixels included in the display panel 100 is m, the first accumulator 553 receives (m-1) difference values ​​corresponding to the number of odd-numbered columns for the difference between the RGBW value of the xth row and the RGBW value of the x-1th row from the first difference calculator 551. The first accumulator 553 accumulates the difference between the RGBW value of the xth row and the RGBW value of the x-1th row received from the first difference calculator 551 for each of the (m-1) columns. The first accumulator 553 transmits a value Sum_O(1) obtained by accumulating the differences to the first threshold value determiner 557. Similarly, the first accumulator 553 receives (m-1) difference values ​​corresponding to the number of odd-numbered columns for each difference between the RGBW value of the xth row and each of the RGBW values ​​of the x-2th row to the xkth row from the first difference calculator 551. The first accumulator 553 accumulates the differences between the RGBW value of the xth row and each of the RGBW values ​​of the x-2th row to the xkth row received from the first difference calculator 551 for each of the (m-1) columns. The first accumulator 553 transmits each of the values ​​Sum_O(2) to Sum_O(k) obtained by accumulating the differences to the first threshold value determiner 557.

[0205] The first threshold value determination unit 557 receives integrated values ​​Sum_O(1) to Sum_O(k) of the difference Diff_O between the RGBW value of the xth row related to the odd-numbered columns and the RGBW values ​​of the x-1th to xkth rows related to the odd-numbered columns from the first integration unit 553. When the first threshold value determination unit 557 determines that the received integrated value for a certain row is less than a predetermined threshold, it determines that the image data of the xth row related to the odd-numbered columns is similar to the image data of the row related to the odd-numbered columns. For example, when the first threshold value determination unit 557 determines that the received integrated value Sum_O(k) is less than a predetermined threshold, it determines that the image data of the xth row related to the odd-numbered columns is similar to the image data of the xkth row related to the odd-numbered columns. On the other hand, when the first threshold value determination unit 557 determines that the received integrated value for a certain row is equal to or greater than the predetermined threshold, it determines that the image data of the xth row related to the odd-numbered columns is not similar to the image data of the row related to the odd-numbered columns. For example, when the first threshold determination unit 557 determines that the received integrated value Sum_O(k) is equal to or greater than a predetermined threshold, it determines that the image data of the xth row related to the odd-numbered columns is not similar to the image data of the xkth row related to the odd-numbered columns. The first threshold determination unit 557 transmits a signal RES_O(x) that is the result of the determination to the scheduler 560. When the first threshold determination unit 557 determines that the image data of a certain row related to the odd-numbered columns is similar to the image data of the xth row related to the odd-numbered columns, it transmits a signal Num_O that identifies the row together with the signal RES_O(x).

[0206] The second difference calculation unit 552 receives image data RGBW_E(x) of the xth row associated with the sub-pixel P arranged in the even-numbered columns from the row memory unit 520. The second difference calculation unit 552 also receives image data RGBW_E(x-1, x-2, ..., xk) of the x-1th row to a predetermined number of rows k associated with the sub-pixel P arranged in the even-numbered columns from the row memory unit 520. Each of the received image data RGBW_E(x-1, x-2, ..., xk) is image data from one row before to k rows before the image data RGBW_E(x), and is, for example, the RGBW values ​​of image data to be written to the red sub-pixels R and blue sub-pixels B arranged in the x-1th row to the xkth row. The second difference calculation unit 552 calculates a difference Diff_E(1) between the received image data RGBW_E(x) of the xth row and the image data RGBW_E(x-1) of the x-1th row, and transmits the calculation result to the second accumulation unit 554. Similarly, the second difference calculation unit 552 calculates differences Diff_E(2) to Diff_E(k) between the received image data RGBW_E(x) of the xth row and each of image data RGBW_E(x-2) to RGBW_E(xk) of the x-2th row to the xkth row, and transmits the calculation result to the second accumulation unit 554.

[0207] The second accumulator 554 receives data of differences Diff_E(1) to Diff_E(k) between the RGBW value of the xth row and the RGBW values ​​of the x-1th to xkth rows in each even column from the second difference calculator 552. The second accumulator 554 accumulates the differences of the image data of each even column received from the second difference calculator 552. For example, when the number of columns of the even-numbered sub-pixels included in the display panel 100 is m, the second accumulator 554 receives (m-1) difference values ​​corresponding to the number of even columns for the difference between the RGBW value of the xth row and the RGBW value of the x-1th row from the second difference calculator 552. The second accumulator 554 accumulates the difference between the RGBW value of the xth row and the RGBW value of the x-1th row received from the second difference calculator 552 for each of the (m-1) columns. The second accumulator 554 transmits the value Sum_E(1) obtained by accumulating the differences to the second threshold value determiner 558. Similarly, the second accumulator 554 receives (m-1) difference values ​​corresponding to the number of even columns for each difference between the RGBW value of the xth row and each of the RGBW values ​​of the x-2th row to the xkth row from the second difference calculator 552. The second accumulator 554 accumulates the differences between the RGBW value of the xth row and each of the RGBW values ​​of the x-2th row to the xkth row received from the second difference calculator 552 for each of the (m-1) columns. The second accumulator 554 transmits the values ​​Sum_E(2) to Sum_E(k) obtained by accumulating the differences to the second threshold value determiner 558.

[0208] The second threshold determination unit 558 receives integrated values ​​Sum_E(1) to Sum_E(k) of the difference Diff_E between the RGBW value of the xth row of the even-numbered column and the RGBW values ​​of the x-1th to xkth rows of the even-numbered columns from the second integration unit 554. When the second threshold determination unit 558 determines that the received integrated value for a certain row is less than a predetermined threshold, it determines that the image data of the xth row of the even-numbered column is similar to the image data of the row of the even-numbered column. For example, when the second threshold determination unit 558 determines that the received integrated value Sum_E(k) is less than a predetermined threshold, it determines that the image data of the xth row of the even-numbered column is similar to the image data of the xkth row of the even-numbered column. On the other hand, when the second threshold determination unit 558 determines that the received integrated value for a certain row is equal to or greater than the predetermined threshold, it determines that the image data of the xth row of the even-numbered column is not similar to the image data of the row of the even-numbered column. For example, when the second threshold determination unit 558 determines that the received integrated value Sum_E(k) is equal to or greater than a predetermined threshold, it determines that the image data of the xth row related to the even columns is not similar to the image data of the xkth row related to the even columns. The second threshold determination unit 558 transmits a signal RES_E(x) that is the result of the determination to the scheduler 560. Furthermore, when the second threshold determination unit 558 determines that the image data of a certain row related to the even columns is similar to the image data of the xth row related to the even columns, it transmits a signal Num_E that identifies the row together with the signal RES_E(x).

[0209] The following describes the order of scanning sub-pixels that is changed based on an image displayed on the display device 10 according to this embodiment. FIG. 32 shows an example of an image displayed on the display device 10 according to this embodiment. The display panel 100 included in the display device 10 displays a plurality of pixel rows 2501 to 2508. The similarity determination unit 550 according to this embodiment determines that pixel data written to sub-pixels arranged in odd-numbered columns included in a pixel row 2504 is similar to image data written to sub-pixels arranged in odd-numbered columns included in a pixel row 2501 that is located three rows above. The similarity determination unit 550 according to this embodiment also determines that pixel data written to sub-pixels arranged in odd-numbered columns included in a pixel row 2506 is similar to image data written to sub-pixels arranged in odd-numbered columns included in a pixel row 2504 that is located two rows above. On the other hand, the similarity determination unit 550 in this embodiment determines that the image data written to the sub-pixels arranged in the odd and even columns of pixel rows 2502, 2503, 2505, 2507, and 2508 is not similar to any of the image data written to the sub-pixels arranged in the odd and even columns of other pixel rows.

[0210] FIG. 33 is a table showing an example of input to the scheduler 560 according to this embodiment. FIG. 33 shows an example of values ​​of signals RES_O, Num_O, RES_E, and Num_E input from the similarity determination unit 550 according to this embodiment to the scheduler 560 for pixel row 2501 to pixel row 2508 shown in FIG. 32. As shown in FIG. 33, in this example, the similarity determination unit 550 transmits 1 for pixel row 2504 and pixel row 2506 to the scheduler 560 as the output signal RES_O for odd-numbered columns. Furthermore, the similarity determination unit 550 transmits a signal Num_O specifying the row determined to have similar image data together with the output signal RES_O for pixel row 2504 and pixel row 2506. Specifically, the similarity determination unit 550 according to this embodiment transmits a determination result indicating that the image data written to the sub-pixels arranged in the odd-numbered columns of the pixel row 2504 is similar to the image data written to the sub-pixels arranged in the odd-numbered columns of the pixel row 2501 to the scheduler 560. Similarly, the similarity determination unit 550 according to this embodiment transmits a determination result indicating that the image data written to the sub-pixels arranged in the odd-numbered columns of the pixel row 2506 is similar to the image data written to the sub-pixels arranged in the odd-numbered columns of the pixel row 2504 to the scheduler 560. On the other hand, the similarity determination unit 550 transmits 0 to the scheduler 560 as the signals RES_O and RES_E other than the output signal RES_O for the pixel rows 2504 and 2506. That is, the similarity determination unit 550 transmits to the scheduler 560 a determination result indicating that pixel data other than the image data written to the sub-pixels arranged in the odd columns of the pixel rows 2504 and 2506 is not similar to the image data of other pixel rows.

[0211] 33 from the similarity determination unit 550. The scheduler 560 generates an input register selection signal IRSS, an input enable signal VALID, an output register selection signal ORSS, and a gate line designation signal GL_Num based on the received signals RES_O, Num_O, RES_E, and Num_E. The scheduler 560 transmits the generated input register selection signal IRSS, input enable signal VALID, and output register selection signal ORSS to the data driver 300, and transmits the generated gate line designation signal GL_Num to the signal modulation unit 510. The gate driver 200 applies gate signals to the gate lines GL in a predetermined order based on the gate line designation signal GL_Num. The data driver 300 transmits image data to each sub-pixel via the data line DL in the order specified by the output register selection signal ORSS in synchronization with the gate signal from the gate driver 200 based on the received input register selection signal IRSS, input enable signal VALID, and output register selection signal ORSS.

[0212] Fig. 34 is a schematic diagram showing the order in which subpixels are scanned in the display device according to this embodiment. Fig. 34 shows four columns of subpixels in pixel rows 2501-2508 shown in Fig. 32. Specifically, Fig. 34 shows green subpixels G25-G32 and red subpixels R25-R32 which share data line DL1, and white subpixels W25-W32 and blue subpixels B25-B32 which share data line DL2.

[0213] As shown in FIG. 34, in pixel rows 2501 to 2508, the green subpixels G and the red subpixels R are scanned in the following order: first, the green subpixel G25 is scanned, followed by the green subpixel G28 arranged three rows below the green subpixel G25. Then, the green subpixel G30 arranged two rows below the green subpixel G28 is scanned. Then, the red subpixel R25, which is in the same row as the green subpixel G25 and shares the data line DL1, but is included in a pixel column different from the pixel column of the green subpixel G, is scanned. Then, the red subpixel R28 arranged three rows below the red subpixel R25 is scanned. Then, the red subpixel R30 arranged two rows below the red subpixel R28 is scanned. Then, the red subpixel R26 arranged four rows above the red subpixel R30 is scanned. Then, the green subpixel G26, which shares the data line DL1 in the same row as the red subpixel R26 and is included in a pixel column different from the pixel column of the red subpixel R, is scanned. Then, the green subpixel G27, which is arranged one row below the green subpixel G26, is scanned. Then, the red subpixel R27, which shares the data line DL1 in the same row as the green subpixel G27 and is included in a pixel column different from the pixel column of the green subpixel G, is scanned. Then, the red subpixel R29, which is arranged two rows below the red subpixel R27, is scanned. Then, the green subpixel G29, which shares the data line DL1 in the same row as the red subpixel R29 and is included in a pixel column different from the pixel column of the red subpixel R, is scanned. Then, the green subpixel G31, which is arranged two rows below the green subpixel G29, is scanned. Then, the red subpixel R31, which shares the data line DL1 in the same row as the green subpixel G31 and is included in a pixel column different from the pixel column of the green subpixel G, is scanned. Then, the red subpixel R32 arranged in the row below the red subpixel R31 is scanned, followed by the green subpixel G32 which shares the data line DL1 in the same row as the red subpixel R32 and is included in a pixel column different from the pixel column of the red subpixel R, and is scanned.

[0214] As shown in FIG. 34, in pixel rows 1301 to 1308, the white subpixels W and blue subpixels B are scanned in the following order. First, the blue subpixel B25 is scanned, followed by the blue subpixel B28 arranged three rows below the blue subpixel B25. Then, the blue subpixel B30 arranged two rows below the blue subpixel B28 is scanned. Then, the white subpixel W25, which is in the same row as the blue subpixel B25 and shares the data line DL2, but is included in a pixel column different from the pixel column of the blue subpixel B, is scanned. Then, the white subpixel W28 arranged three rows below the white subpixel W25 is scanned. Then, the white subpixel W30 arranged two rows below the white subpixel W28 is scanned. Then, the white subpixel W26 arranged four rows above the white subpixel W30 is scanned. Then, the blue subpixel B26, which shares the data line DL2 in the same row as the white subpixel W26 and is included in a pixel column different from the pixel column of the white subpixel W, is scanned. Then, the blue subpixel B27, which is arranged one row below the blue subpixel B26, is scanned. Then, the white subpixel W27, which shares the data line DL2 in the same row as the blue subpixel B27 and is included in a pixel column different from the pixel column of the blue subpixel B, is scanned. Then, the white subpixel W29, which is arranged two rows below the white subpixel W27, is scanned. Then, the blue subpixel B29, which shares the data line DL2 in the same row as the white subpixel W29 and is included in a pixel column different from the pixel column of the white subpixel W, is scanned. Then, the blue subpixel B31, which is arranged two rows below the blue subpixel B29, is scanned. Then, the white subpixel W31, which shares the data line DL2 in the same row as the blue subpixel B31 and is included in a pixel column different from the pixel column of the blue subpixel B, is scanned. Then, the white subpixel W32 arranged in the row below the white subpixel W31 is scanned, followed by the blue subpixel B32 which is in the same row as the white subpixel W32, shares the data line DL2, and is included in a pixel column different from the pixel column of the white subpixel W, being scanned.

[0215] In this embodiment, the similarity determination unit 550 compares the image data (signal) applied to each row with each of the image data applied to the other rows. According to this embodiment, the similarity determination unit 550 sequentially scans rows determined to have similar image data applied preferentially. Even if the rows determined to have similar image data applied are not consecutive, the number of rows for consecutively scanning sub-pixels of the same color can be increased. As a result, the frequency of discontinuity in the signal (voltage) of the output image data is reduced, and the power consumption of the display device 10 is reduced. Therefore, according to this embodiment, the power consumption when the display device using the DRD drive writes image data to the sub-pixels can be further reduced.

[0216] Fig. 35 is a timing diagram of gate signals applied to gate lines of the display device 10 according to this embodiment. Specifically, the sub-pixels of pixel rows 2501 to 2508 shown in Fig. 34 are scanned based on signals transmitted from the similarity determination unit 550 shown in Fig. 31 to the scheduler 560. The gate driver 200 applies gate signals to the gate lines GL49 to GL64 at the timing shown in Fig. 35.

[0217] During the period from time t52 to t53, no gate signal is applied to the gate lines GL49 to GL64. During the period from time t53 to t54, a gate signal is applied to the gate line GL50 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL50, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G25 and the first capacitor C1 of the green subpixel G25 via the first switch element T1 of the green subpixel G25. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G25. Similarly, when a gate signal is applied to the gate line GL50, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B25 and the first capacitor C1 of the blue subpixel B25 via the first switch element T1 of the blue subpixel B25. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B25.

[0218] In the period from time t54 to t55, a gate signal is applied to the gate line GL56 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL56, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G28 and the first capacitor C1 of the green subpixel G28 via the first switch element T1 of the green subpixel G28. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G28. Similarly, when a gate signal is applied to the gate line GL56, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B28 and the first capacitor C1 of the blue subpixel B28 via the first switch element T1 of the blue subpixel B28. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B28.

[0219] In the period from time t55 to t56, a gate signal is applied to the gate line GL60 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL60, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G30 and the first capacitor C1 of the green subpixel G30 via the first switch element T1 of the green subpixel G30. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G30. Similarly, when a gate signal is applied to the gate line GL60, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B30 and the first capacitor C1 of the blue subpixel B30 via the first switch element T1 of the blue subpixel B30. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B30.

[0220] In the period from time t56 to t57, a gate signal is applied to the gate line GL49 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL49, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R25 and the first capacitor C1 of the red subpixel R25 via the first switch element T1 of the red subpixel R25. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R25. Similarly, when the gate signal is applied to the gate line GL49, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W25 and the first capacitor C1 of the white subpixel W25 via the first switch element T1 of the white subpixel W25. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W25.

[0221] In the period from time t57 to t58, a gate signal is applied to the gate line GL55 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL55, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R28 and the first capacitor C1 of the red subpixel R28 via the first switch element T1 of the red subpixel R28. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R28. Similarly, when a gate signal is applied to the gate line GL55, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W28 and the first capacitor C1 of the white subpixel W28 via the first switch element T1 of the white subpixel W28. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W28.

[0222] During the period from time t58 to t59, a gate signal is applied to the gate line GL59 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL59, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R30 and the first capacitor C1 of the red subpixel R30 via the first switch element T1 of the red subpixel R30. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R30. Similarly, when the gate signal is applied to the gate line GL59, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W30 and the first capacitor C1 of the white subpixel W30 via the first switch element T1 of the white subpixel W30. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W30.

[0223] In the period from time t59 to t60, a gate signal is applied to the gate line GL51 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL51, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R26 and the first capacitor C1 of the red subpixel R26 via the first switch element T1 of the red subpixel R26. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R26. Similarly, when the gate signal is applied to the gate line GL51, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W26 and the first capacitor C1 of the white subpixel W26 via the first switch element T1 of the white subpixel W26. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W26.

[0224] In the period from time t60 to t61, a gate signal is applied to the gate line GL52 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL52, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G26 and the first capacitor C1 of the green subpixel G26 via the first switch element T1 of the green subpixel G26. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G26. Similarly, when a gate signal is applied to the gate line GL52, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B26 and the first capacitor C1 of the blue subpixel B26 via the first switch element T1 of the blue subpixel B26. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B26.

[0225] In the period from time t61 to t62, a gate signal is applied to the gate line GL54 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL54, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G27 and the first capacitor C1 of the green subpixel G27 via the first switch element T1 of the green subpixel G27. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G27. Similarly, when a gate signal is applied to the gate line GL54, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B27 and the first capacitor C1 of the blue subpixel B27 via the first switch element T1 of the blue subpixel B27. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B27.

[0226] In the period from time t62 to t63, a gate signal is applied to the gate line GL53 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL53, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R27 and the first capacitor C1 of the red subpixel R27 via the first switch element T1 of the red subpixel R27. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R27. Similarly, when the gate signal is applied to the gate line GL53, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W27 and the first capacitor C1 of the white subpixel W27 via the first switch element T1 of the white subpixel W27. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W27.

[0227] In the period from time t63 to t64, a gate signal is applied to the gate line GL57 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL57, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R29 and the first capacitor C1 of the red subpixel R29 via the first switch element T1 of the red subpixel R29. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R29. Similarly, when a gate signal is applied to the gate line GL57, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W29 and the first capacitor C1 of the white subpixel W29 via the first switch element T1 of the white subpixel W29. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W29.

[0228] In the period from time t64 to t65, a gate signal is applied to the gate line GL58 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL58, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G29 and the first capacitor C1 of the green subpixel G29 via the first switch element T1 of the green subpixel G29. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G29. Similarly, when a gate signal is applied to the gate line GL58, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B29 and the first capacitor C1 of the blue subpixel B29 via the first switch element T1 of the blue subpixel B29. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B29.

[0229] In the period from time t65 to t66, a gate signal is applied to the gate line GL62 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL62, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G31 and the first capacitor C1 of the green subpixel G31 via the first switch element T1 of the green subpixel G31. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G31. Similarly, when a gate signal is applied to the gate line GL62, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B31 and the first capacitor C1 of the blue subpixel B31 via the first switch element T1 of the blue subpixel B31. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B31.

[0230] In the period from time t66 to t67, a gate signal is applied to the gate line GL61 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL61, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R31 and the first capacitor C1 of the red subpixel R31 via the first switch element T1 of the red subpixel R31. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R31. Similarly, when the gate signal is applied to the gate line GL61, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W31 and the first capacitor C1 of the white subpixel W31 via the first switch element T1 of the white subpixel W31. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W31.

[0231] In the period from time t67 to t68, a gate signal is applied to the gate line GL63 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL63, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the red subpixel R32 and the first capacitor C1 of the red subpixel R32 via the first switch element T1 of the red subpixel R32. The data signal applied from the data line DL1 corresponds to image data for the red subpixel R32. Similarly, when the gate signal is applied to the gate line GL63, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the white subpixel W32 and the first capacitor C1 of the white subpixel W32 via the first switch element T1 of the white subpixel W32. The data signal applied from the data line DL2 corresponds to image data for the white subpixel W32.

[0232] In the period from time t68 to t69, a gate signal is applied to the gate line GL64 in synchronization with the modulated data enable signal tDE. When the gate signal is applied to the gate line GL64, a data signal is applied from the data line DL1 to a first node N1 between the gate of the driving element DT of the green subpixel G32 and the first capacitor C1 of the green subpixel G32 via the first switch element T1 of the green subpixel G32. The data signal applied from the data line DL1 corresponds to image data for the green subpixel G32. Similarly, when a gate signal is applied to the gate line GL64, a data signal is applied from the data line DL2 to a first node N1 between the gate of the driving element DT of the blue subpixel B32 and the first capacitor C1 of the blue subpixel B32 via the first switch element T1 of the blue subpixel B32. The data signal applied from the data line DL2 corresponds to image data for the blue subpixel B32.

[0233] 35 in the period from time t53 to t69 based on the gate line designation signal GL_Num from the scheduler 560. The data driver 300 writes data signals to the green subpixel G and the red subpixel R via the shared data line DL1 in response to the gate signals applied to the gate lines GL49 to GL64 in the period from time t53 to t69. Furthermore, the data driver 300 writes data signals to the white subpixel W and the blue subpixel B via the shared data line DL2 in response to the gate signals applied to the gate lines GL49 to GL64 in the period from time t53 to t69.

[0234] According to the timing diagram shown in FIG. 35, the data driver 300 writes data signals to the green subpixels G25-G32, the red subpixels R25-R32, the white subpixels W25-W32, and the blue subpixels B25-B32 in the pixel rows 2501-2508 in the order shown in FIG. 34. That is, when scanning the subpixel region shown in FIG. 34, the rows determined by the similarity determination unit 550 to have similar image data applied thereto are preferentially scanned in sequence. That is, according to this embodiment, even if the rows determined to have similar image data applied thereto are not consecutive, the number of rows in which subpixels of the same color are scanned consecutively can be increased. As a result, the frequency of discontinuity in the signal (voltage) of the output image data is reduced, and the power consumption of the display device 10 is reduced. Therefore, according to this embodiment, the power consumption when a display device using the DRD drive writes image data to subpixels can be further reduced.

[0235] [Fourth embodiment] In this embodiment, a modified example of the data selection unit 310 according to the first embodiment will be described. Descriptions of the configurations and functions of data division units 311-1 to 311-m, first registers 312-1 to 312-m, second registers 313-1 to 313-m, and selection units 314-1 to 314-m that are the same as those of the first embodiment will be omitted.

[0236] An example of the operation of the data selection unit 310 in response to an input signal to the scheduler 560 will be described with reference to Fig. 16 and Fig. 36. Fig. 36 is a table showing an example of a signal input to the data selection unit 310 according to this embodiment.

[0237] As shown in FIG. 16, in this example, as in the first embodiment, the output signal RES_O of the similarity determination unit 550 for odd columns indicates 0 for the x-7th row. That is, the similarity determination unit 550 determines that the image data of the odd columns for the x-7th row is not similar to the image data of the odd columns of the previous row. Also, the output signal RES_O of the similarity determination unit 550 for odd columns indicates 1 for the x-6th row to the xth row. That is, the similarity determination unit 550 determines that the image data of the odd columns for the x-6th row to the xth row are similar to the image data of the odd columns of the previous row. On the other hand, the output signals RES_E of the similarity determination unit 550 for even columns all indicate 0. That is, the similarity determination unit 550 determines that the image data of the even columns for the x-7th row to the xth row are not similar to the image data of the even columns of the previous row.

[0238] FIG. 36 shows an example of the input register selection signal IRSS, the input validation signal VALID, and the output register selection signal ORSS transmitted to the data selection unit 310 in the scan numbers 33 to 48. In this example, the image data (signals) of the odd columns in the x-6th row to the xth row are similar to the image data of the odd columns located one row above. In this embodiment, in the scan number 33, the aligned image data R'G'B'W' of the odd columns in the x-7th row is input from the row memory unit 520 to the data selection unit 310 as the input data 33. Next, in the scan number 34, the aligned image data R'G'B'W' of the even columns in the x-7th row is input from the row memory unit 520 to the data selection unit 310 as the input data 41. Next, in the scan numbers 35 to 40, the image data is not input from the row memory unit 520 to the data selection unit 310. Next, in scan numbers 41 to 47, the aligned image data R'G'B'W' of even-numbered columns for the x-6th row to the xth row are input as input data 42 to 48 from the row memory unit 520 to the data selection unit 310. Next, in scan number 48, no image data is input from the row memory unit 520 to the data selection unit 310.

[0239] The scheduler 560 generates an input register selection signal IRSS for specifying a register in which the odd-numbered string of input data 33 is stored, based on the received signal RES_O. The scheduler 560 transmits the input register selection signal IRSS for specifying the first registers 312-1 to 312-m as the registers in which the input data 33 should be stored, to the data selection unit 310. The scheduler 560 also generates an input register selection signal IRSS for specifying a register in which the even-numbered string of input data 41 to 48 is stored, based on the received signal RES_E. The scheduler 560 transmits the input register selection signal IRSS for specifying the first registers 312-1 to 312-m or the second registers 313-1 to 313-m as the registers in which the input data 41 to 48 should be stored, to the data selection unit 310.

[0240] The scheduler 560 transmits 1 to the data selection unit 310 as the input enable signal VALID for the input data 33 corresponding to the odd-numbered columns, and enables the input register selection signal IRSS that specifies that the input data 33 is to be stored in the first registers 312-1 to 312-m. Next, the scheduler 560 transmits 1 to the data selection unit 310 as the input enable signal VALID for the input data 41 corresponding to the even-numbered columns, and enables the input register selection signal IRSS that specifies that the input data 41 is to be stored in the second registers 313-1 to 313-m. Next, the scheduler 560 does not transmit the input data for the scan numbers 35 to 40, and transmits 0 to the data selection unit 310 as the input enable signal VALID. As a result, the first registers 312-1 to 312-m are not updated, and the input data 41 is held. This configuration reduces the consumption of power required to update the data stored in the first registers 312-1 to 312-m. In this example, the scheduler 560 transmits the input register selection signal IRSS that designates the second registers 313-1 to 313-m. However, when the scheduler 560 transmits 0 as the input validation signal VALID to the data selection unit 310, the scheduler 560 can omit the transmission of the input register selection signal IRSS.

[0241] Next, the scheduler 560 transmits 1 to the data selection unit 310 as the input enable signal VALID for each of the input data 42, 44, 46, 48 corresponding to the even-numbered columns, and enables the input register selection signal IRSS that specifies that the input data 42, 44, 46, 48 are stored in the first registers 312-1 to 312-m. The scheduler 560 also transmits 1 to the data selection unit 310 as the input enable signal VALID for each of the input data 43, 45, 47 corresponding to the even-numbered columns, and enables the input register selection signal IRSS that specifies that the input data 43, 45, 47 are stored in the second registers 313-1 to 313-m.

[0242] The scheduler 560 transmits an output register selection signal ORSS to the data selection unit 310 in order to sequentially output the input data 33 and the input data 41 to 48 to the data conversion unit 320 as the output data 33 to 48. Specifically, the scheduler 560 transmits an output register selection signal ORSS designating the first registers 312-1 to 312-m for the scan numbers 33 to 40, 42, 44, 46, and 48 to the data selection unit 310, and transmits an output register selection signal ORSS designating the second registers 313-1 to 313-m for the scan numbers 41, 43, 45, and 47 to the data selection unit 310. That is, for the scan numbers 33 to 40, the input data 33 stored in the first registers 312-1 to 312-m is output as the output data 33 to 40. In scan number 41, the input data 41 stored in the second registers 313-1 to 313-m during scan number 34 is output as output data 41. In scan number 42, the input data 42 stored in the first registers 312-1 to 312-m during scan number 41 is output as output data 42. In scan number 43, the input data 43 stored in the second registers 313-1 to 313-m during scan number 42 is output as output data 43. In scan number 44, the input data 44 stored in the first registers 312-1 to 312-m during scan number 43 is output as output data 42. In scan number 45, the input data 45 stored in the second registers 313-1 to 313-m during scan number 44 is output as output data 45. In scan number 46, the input data 46 stored in the first registers 312-1 to 312-m during scan number 45 is output as output data 46. In scan number 47, input data 47 stored in second registers 313-1 to 313-m during scan number 46 is output as output data 47. In scan number 48, input data 48 stored in first registers 312-1 to 312-m during scan number 47 is output as output data 48.

[0243] In this embodiment, the input data corresponding to the even-numbered columns is configured to be stored not only in the second registers 313-1 to 313-m but also in the first registers 312-1 to 312-m. Similarly, the input data corresponding to the odd-numbered columns can be configured to be stored not only in the first registers 312-1 to 312-m but also in the second registers 313-1 to 313-m. As in this embodiment, the input data stored in the registers can be changed arbitrarily. Also, it is possible to provide an additional register for each row. By providing an additional register, the capacity of the row memory section 520 included in the timing control section 500 can be reduced.

[0244] [Fifth embodiment] In this embodiment, a modified example of the scheduler 560 according to the first embodiment will be described. The configurations and functions of the buffer 561, the scanning order determination unit 562, the gate line determination unit 563, and the register 564 are the same, so description thereof will be omitted.

[0245] FIG. 37 is a block diagram showing a schematic configuration of a scheduler 560 according to the present embodiment. The scheduler 560 according to the present embodiment includes a buffer 561, a scanning order determination unit 562, a gate line determination unit 563, and a register 564. The scheduler 560 according to the present embodiment does not include a selection signal determination unit 565. Therefore, the register selection signal RSS is not transmitted from the scheduler 560 according to the present embodiment. Therefore, the data driver 300 according to the present embodiment does not include a data selection unit 310. In the present embodiment, an additional row memory unit (not shown) is provided in the timing control unit 500. All image data RGBW input to the timing control unit 500 are transmitted to the additional row memory unit. The signal modulation unit 510 according to the present embodiment transmits the aligned image data R'G'B'W' corresponding to the specified gate line from the additional row memory unit to the data driver 300 based on the gate line specification signal GL_Num received from the scheduler 560.

[0246] As described above, the scheduler 560 according to the present embodiment does not include the selection signal determination unit 565. In addition, the data driver 300 according to the present embodiment does not include the data selection unit 310. Therefore, according to the present embodiment, the structure of the display device 10 can be simplified.

[0247] [Sixth embodiment] In this embodiment, a modified example of the timing control unit 500 according to the first embodiment will be described. Descriptions of the configurations and functions of the signal modulation unit 510, the data control signal generation unit 530, the gate control signal generation unit 540, the similarity determination unit 550, and the scheduler 560 that are the same as those of the first embodiment will be omitted.

[0248] FIG. 38 is a block diagram showing a schematic configuration of a timing control unit 500 according to the present embodiment. The timing control unit 500 according to the embodiment includes a frame memory unit 570. The frame memory unit 570 stores image data RGBW in units of frames. For example, the frame memory unit 570 stores image data RGBW(x) of the xth frame. The frame memory unit 570 transmits image data RGBW(x-1) of the (x-1)th frame to the similarity determination unit 550. The frame memory unit 570 aligns the image data RGBW based on the modulated data enable signal tDE received from the signal modulation unit 510. The frame memory unit 570 transmits the aligned image data R'G'B'W' to the data driver 300.

[0249] The similarity determination unit 550 determines the similarity of image data between two frames, and transmits the determination result RES to the scheduler 560. For example, the similarity determination unit 550 receives image data RGBW(x-1) of the (x-1)th frame from the frame memory unit 570, and determines whether it is similar to image data RGBW(x) of the xth frame. For example, the similarity determination unit 550 outputs 1 as the determination result RES when it determines that image data of any two rows in the image data of two frames are similar to each other. On the other hand, the similarity determination unit 550 outputs 0 as the determination result RES when it determines that the image data of the two rows in the image data of two frames are not similar to each other.

[0250] The scheduler 560 generates a gate line designation signal GL_Num designating the number of the gate line GL to transmit the gate signal based on the determination result RES received from the similarity determination unit 550. The scheduler 560 also transmits a register selection signal RSS to the data driver 300 to designate a register in which the image data R'G'B'W' transmitted from the frame memory unit 570 should be stored. The data driver 300 stores the image data R'G'B'W' in the designated register based on the received register selection signal RSS.

[0251] As described above, the timing control unit 500 according to this embodiment determines the similarity between the image data (signals) of each frame displayed on the display panel 100. Next, the timing control unit 500 according to this embodiment generates a gate line specification signal GL_Num and a register selection signal RSS based on the determined similarity. According to this embodiment, it is possible to reduce power consumption while suppressing degradation in the display image quality of the display device 10 using the DRD based on the similarity between the image data (signals) of each frame displayed on the display panel 100.

[0252] When the image displayed on the display panel 100 is a still image, the degradation of the display quality due to the time difference in writing image data to the sub-pixels arranged in the same row does not occur at all or is negligibly small. Therefore, when a still image is displayed on the display device 10, the number of rows for continuously scanning sub-pixels of the same color can be made equal to the number of rows of pixels included in the display panel. For example, when the display device 10 is composed of 2160 rows of pixels, the green sub-pixel G and the blue sub-pixel B can be continuously scanned over 2160 rows during the first half of one frame period, and the red sub-pixel R and the white sub-pixel W can be continuously scanned over 2160 rows during the second half of one frame period. This configuration further reduces the frequency of discontinuity in the signal (voltage) of the output image data, thereby reducing the power consumption of the display device 10.

[0253] [Other variations] In each of the above-described embodiments, the order of scanning sub-pixels is determined based on the similarity between a plurality of image data (signals). On the other hand, when displaying an image with low luminance, such as when displaying black, discontinuity of the image signal does not occur, or even if discontinuity occurs, the degree of discontinuity may be negligible. For example, according to this modification, when the luminance of an image displayed on the display panel 100 is equal to or lower than a predetermined value, the number of rows in which sub-pixels of the same color are continuously scanned is reduced regardless of the result of the similarity determination. With this configuration, the time difference in writing image data to sub-pixels arranged in the same row is reduced. Specifically, as shown in FIG. 21, the time difference in writing image data between a plurality of sub-pixels arranged in the same row is reduced by alternately scanning two rows of sub-pixels of each color. According to this modification, it is possible to suppress the degradation of the display image quality caused by the time difference in writing image data without increasing the power consumption of the display device 10 using the DRD.

[0254] Furthermore, even if the similarity determination unit 550 determines that the image data (signals) are similar over a wide range, if the number of rows for continuously scanning subpixels of the same color is excessively large, the displayed image quality may deteriorate. Therefore, the timing control unit 500 can limit the number of rows for continuously scanning subpixels of the same color. For example, when the image displayed on the display device is a moving image, the timing control unit 500 can set the number of rows for continuously scanning subpixels of the same color to about one-fifth of the total number of rows of subpixels included in the display panel 100. In this example, when the display panel 100 includes 2160 rows of subpixels, the timing control unit 500 can limit the number of rows for continuously scanning subpixels of the same color to 432 rows.

[0255] The configurations of the parts and the contents of the signals described in each embodiment are not limited to those described above, and may be changed according to the application or purpose. Furthermore, configurations and signals obtained by combining each embodiment are all included in the present invention. In other words, the present invention is not limited to the above-mentioned embodiments, and may be modified based on the technical idea of ​​the present invention. For example, the present invention includes a configuration in which the above-mentioned embodiments are organically combined. [Explanation of symbols]

[0256] 10 Display device 200 Gate driver 221, 222 First shift register 231, 232 Second shift register 300 Data Drive Unit 310 Data Selection Section 500 Timing control section 550 Similarity determination unit 560 Scheduler

Claims

1. a display panel having a plurality of sub-pixels arranged in a matrix, a plurality of gate lines extending in a row direction, and a plurality of data lines extending in a column direction; a first gate driver that supplies a plurality of gate signals to the first color sub-pixels of the plurality of sub-pixels via a plurality of first gate lines of the plurality of gate lines to activate the first color sub-pixels of the plurality of sub-pixels; a second gate driver that supplies a plurality of gate signals to the second color sub-pixels of the plurality of sub-pixels via a plurality of second gate lines of the plurality of gate lines to activate the second color sub-pixels of the plurality of sub-pixels; a data driver supplying a plurality of data signals corresponding to luminance of the plurality of sub-pixels to the plurality of sub-pixels via the plurality of data lines; a timing control unit for controlling the first gate driver, the second gate driver and the data driver; Including, the plurality of sub-pixels include a first sub-pixel of the first color and a second sub-pixel of the second color that share a first data line of the plurality of data lines in a first row; the timing control unit controls the first gate driving unit independently of the second gate driving unit so as to continuously supply the gate signals to the sub-pixels of the first color via the plurality of first gate lines at a first scanning time and a second scanning time subsequent to the first scanning time; the timing control unit determines the number of rows of the first color sub-pixels to which the gate signals are successively supplied by the first gate driving unit based on a similarity between the data signal corresponding to the first color in the first row and the data signal corresponding to the first color in a row other than the first row. Display device.

2. the timing control unit causes the first gate driving unit to be in a state in which the gate signal can be supplied via a first group of gate lines among the plurality of first gate lines at the first scanning time; At the second scanning time, the first gate driver is set to a state in which the gate signal can be supplied via a second group of gate lines among the plurality of first gate lines; the second group of gate lines includes gate lines that are not included in the first group of gate lines; The display device according to claim 1 .

3. 3. The display device according to claim 2, wherein the timing control unit controls the first gate driving unit to supply the gate signal to the first subpixel via one of the gate lines of the first group at the first scanning time.

4. 4. The display device according to claim 2, wherein the timing control unit causes the second gate drive unit to be in a state in which the gate signals can be supplied via a predetermined group of gate lines among the plurality of second gate lines at the first scanning time and the second scanning time.

5. 5. The display device according to claim 4, wherein the timing control unit controls the second gate driving unit so as not to supply the gate signal to the sub-pixel of the second color at the first scanning time and the second scanning time.

6. 6. The display device according to claim 5, wherein the timing control unit controls the second gate driver independently of the first gate driver so as to continuously supply the gate signal to the subpixels of the second color via the plurality of second gate lines after the gate signal is supplied to the subpixels of the first color.

7. the timing control unit causes the second gate driving unit to be in a state in which the gate signals can be supplied via a third group of gate lines among the plurality of second gate lines at a third scanning time that is after the second scanning time; At a fourth scanning time next to the third scanning time, the second gate driver is set to a state in which the gate signal can be supplied via a fourth group of gate lines among the plurality of second gate lines; the fourth group of gate lines includes gate lines that are not included in the third group of gate lines; The display device according to claim 6.

8. 8. The display device according to claim 7, wherein the timing control unit controls the second gate driving unit to supply the gate signal to the second subpixel via any one of the gate lines of the third group at the third scanning time.

9. 9. The display device according to claim 8, wherein the timing control unit causes the first gate driving unit to be in a state in which the gate signals can be supplied via a predetermined group of gate lines among the plurality of first gate lines at the third scanning time and the fourth scanning time.

10. 10. The display device according to claim 9, wherein the timing control unit controls the first gate driving unit so as not to supply the gate signal to the subpixel of the first color at the third scanning time and the fourth scanning time.

11. the first subpixel of the first color is connected to the first data line and the first gate line corresponding to the first row; the second subpixel of the second color is connected to the first data line and the second gate line corresponding to the first row; the plurality of sub-pixels further includes a third sub-pixel of the first color and a fourth sub-pixel of the second color that share the first data line in a second row; the third subpixel of the first color is connected to the first data line and the first gate line corresponding to the second row; the fourth subpixel of the second color is connected to the first data line and the second gate line corresponding to the second row; The display device according to claim 1 .

12. the plurality of sub-pixels further includes a third sub-pixel of the first color and a fourth sub-pixel of the second color that share the first data line in a second row; When the timing control unit determines that the data signal of the first subpixel is similar to the data signal of the third subpixel, the timing control unit controls the first gate driving unit to supply the gate signal to the third subpixel subsequent to the first subpixel. The display device according to claim 1 .

13. 13. The display device of claim 12, wherein the timing control unit controls the first gate driver and the second gate driver to supply the gate signal to the second subpixel following the first subpixel when the timing control unit determines that the data signal of the first subpixel is not similar to the data signal of the third subpixel.

14. The display device of claim 13 , wherein the timing control unit controls the second gate driver to supply the gate signal to the fourth subpixel subsequent to the second subpixel.

15. The display device according to claim 12 , wherein the timing control unit determines whether the data signal of the first sub-pixel is similar to the data signal of the third sub-pixel within the same frame.

16. The display device according to claim 12 , wherein the timing control unit determines whether the data signal of the first sub-pixel is similar to the data signal of the third sub-pixel between a plurality of frames.

17. The display device of claim 12 , wherein the first row is adjacent to the second row.

18. The display device of claim 12 , wherein the first row is a row that is not adjacent to the second row.

19. 4. The display device according to claim 1, wherein the timing control unit supplies gate start signals, which start supplying the gate signals to the sub-pixels, to the first gate driving unit and the second gate driving unit at different timings.

20. 4 . The display device according to claim 1 , wherein the timing control unit supplies reset signals for resetting the voltages of the gate lines to the first gate driver and the second gate driver at different timings.

21. 4. The display device according to claim 1, wherein the timing control unit controls the first gate driving unit to limit the number of rows to which the gate signals are continuously supplied to the first color subpixels when an image displayed on the display panel is a moving image.

22. 4. The display device according to claim 1, wherein the timing control unit controls the first gate driving unit so as not to limit the number of rows to which the gate signals are continuously supplied to the first color subpixels when the image displayed on the display panel is a still image.

23. 13. The display device according to claim 12, wherein the timing control unit controls the first gate driving unit and the second gate driving unit to supply the gate signal to the second subpixel, following the first subpixel, regardless of the determination, when the luminance corresponding to an image displayed on the display panel is equal to or lower than a predetermined value.

24. The display device according to claim 1 , wherein the first gate driver and the second gate driver are arranged in the same region.

25. The display device according to claim 1 , wherein the first gate driver and the second gate driver are arranged in a gate-in-panel (GIP) manner.

26. 25. The display device of claim 24, wherein a straight line path connecting a first output end of the gate signal supplied from the first gate driver to the gate line corresponding to the first output end intersects with a straight line path connecting a second output end of the gate signal supplied from the second gate driver to the gate line corresponding to the second output end.

27. 26. The display device of claim 25, wherein a straight line path connecting a first output end of the gate signal supplied from the first gate driver to the gate line corresponding to the first output end intersects with a straight line path connecting a second output end of the gate signal supplied from the second gate driver to the gate line corresponding to the second output end.

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