Semiconductor Device

Abstract

To provide a semiconductor device capable of achieving miniaturization or higher integration.SOLUTION: A semiconductor device comprises a transistor and a capacitive element. The transistor comprises a metal oxide and a first conductor electrically connected to the metal oxide. The capacitive element comprises: a first insulator which is arranged on the metal oxide and through which a first conductor passes; a second insulator which is arranged on the first insulator and formed with an opening reaching the first insulator and the first conductor; a second conductor arranged in contact with an inner wall of the opening, the first insulator, and the first conductor; a third insulator arranged on the second conductor; and a fourth conductor arranged on the third insulator. The first insulator is higher in hydrogen transmission suppressing function than the second insulator.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a capacitor, a semiconductor device, a memory device, and a manufacturing method thereof. Another embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. device, lighting device, electro-optical device, power storage device, memory device, semiconductor circuit, imaging device, and electronic There are cases where the equipment and the like can be said to include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. An aspect of the present invention relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. This concerns the issue of the [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, and memories are mainly used. A CPU is a semiconductor integrated circuit (at least transistors and The semiconductor device is an assembly of semiconductor elements having a memory and on which electrodes serving as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards, such as printed circuit boards. They are mounted on printed wiring boards and used as components in a variety of electronic devices.

[0006] In addition, a transistor is formed using a semiconductor thin film formed on a substrate having an insulating surface. This technology is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (simply called displays). It is widely used in electronic devices such as transistors. Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used for this purpose, but other materials include Oxide semiconductors are attracting attention.

[0007] In addition, a transistor including an oxide semiconductor has a very low leakage current in a non-conducting state. For example, the leakage current of a transistor using an oxide semiconductor is known to be small. A low-power CPU that utilizes this characteristic has been disclosed (see Patent Document 1). In addition, for example, the leakage current of a transistor using an oxide semiconductor is low. The application of this technology has led to the disclosure of a storage device that can retain stored contents for a long period of time. (See Patent Document 2.) [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2011-151383 A Summary of the Invention [Problem to be solved by the invention]

[0009] One embodiment of the present invention provides a capacitor or a semiconductor device that can be miniaturized or highly integrated. An object of one embodiment of the present invention is to provide a capacitor or a semiconductor device with high productivity. One object of one embodiment of the present invention is to provide a capacitor having large capacitance. One embodiment of the present invention is a semiconductor device having favorable electrical characteristics. One object of the present invention is to provide a semiconductor device having high reliability. One of the objectives of the project is to provide a place where

[0010] One embodiment of the present invention is a semiconductor device or memory device capable of retaining data for a long period of time. One embodiment of the present invention is a semiconductor device having a high data writing speed. It is an object of one embodiment of the present invention to provide a device or a storage device that can reduce power consumption. It is an object of the present invention to provide a semiconductor device or memory device capable of suppressing One aspect of the present invention provides a semiconductor device or memory device having a large storage capacity per unit area. One object of the present invention is to provide a novel semiconductor device or memory device. One of the challenges is to

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0012] A metal oxide semiconductor layer is formed on a transistor having a metal oxide so as to at least partially overlap the transistor. By providing such a capacitance element, the area occupied by the semiconductor device can be reduced, and miniaturization or high integration can be achieved. Furthermore, an insulator is disposed on the transistor, and a gate insulating film formed on the insulator can be formed on the transistor. By providing a capacitor element so as to be embedded in the opening, the area occupied by the semiconductor device is reduced. In addition, the capacitance of the capacitive element can be increased.

[0013] Furthermore, a semiconductor device that suppresses the permeation of impurities such as water or hydrogen between the transistor and the capacitor element is provided. By providing an insulator that has the function of preventing impurities from This prevents the metal from being mixed into the transistor, providing transistors with good electrical characteristics and reliability. It is possible.

[0014] In addition, the transistor and the capacitor are connected through the insulator, which has the function of suppressing the permeation of impurities. A conductor is provided to electrically connect the terminals. The upper part of the conductor is shaped to have a curved surface. By this, the contact resistance between the conductor and the lower electrode of the capacitance element is reduced, and a good electrical connection is obtained for the semiconductor device. Characteristics can be given.

[0015] One aspect of the present invention is a thermal expansion module including a first insulator and a first insulating film disposed so as to penetrate the first insulator. a first conductor and an opening disposed on the first insulator and reaching the first insulator and the first conductor; A second insulator having an opening formed therein and connected to the inner wall of the opening, the first insulator, and the first conductor. a second conductor disposed on the second conductor; a third insulator disposed on the second conductor; a fourth conductor disposed on the first insulator and connected to the second conductor of the first insulator. The thickness of the region where the first conductor is formed is thinner than the thickness of the other region of the first insulator. A container having a curved surface at a portion of the insulator above the upper surface of the region in contact with the second conductor. It is a quantum element.

[0016] Another embodiment of the present invention is a semiconductor device including a transistor and a capacitor. a metal oxide and a first conductor electrically connected to the metal oxide; a first insulator disposed on the metal oxide and having a first conductor passing therethrough; a second insulating member disposed on the edge member and having an opening extending to the first insulating member and the first conductive member; a second insulator disposed in contact with the inner wall of the opening, the first insulator, and the first conductor; a conductor, a third insulator disposed on the second conductor, and a third insulator disposed on the third insulator; and a fourth conductor, the first insulator suppressing hydrogen permeation more than the second insulator. This is a semiconductor device with high functionality.

[0017] In the above, the first conductor is formed so as to be lower than the upper surface of the first insulator in a region where the first conductor is in contact with the second conductor. Preferably, the first guide has a curved surface at the upper portion. The conductor has a bottom surface below the top surface of the first insulator in a region where the first insulator contacts the second conductor. It is preferable that the angle between the first insulating layer and the side surface is 90° or more. The thickness of the first insulator in a region in contact with the second conductor is thinner than the thickness of the first insulator in the other region. This is also fine.

[0018] In the above, it is preferable that the first insulator contains aluminum and oxygen. In the above, the second insulator is disposed on the fifth insulator. and a sixth insulator having a compressive stress. and the other of the fifth insulator and the sixth insulator has a tensile stress. In the above, the fourth conductor is formed so as to fill the opening, and the fourth conductor The fourth conductor has a region overlapping the second insulator, and the average surface roughness of the upper surface of the region of the fourth conductor is In the above, the metal oxide is preferably a metal oxide having a thickness of 2 nm or less. It is preferable that the material contains M (M is Al, Ga, Y, or Sn) and Zn.

[0019] Another embodiment of the present invention is a method for forming a first insulator on a transistor having a metal oxide. forming a second insulator on the first insulator; and forming a second insulator on the first insulator. a first opening in the second insulator, the first opening reaching one of the source and drain of the transistor; forming a second opening reaching the other of the source and drain of the transistor; embedding a first conductor in the opening and a second conductor in the second opening; forming a third insulator on the insulator, the first conductor, and the second conductor; A third opening is formed by performing an etching process to reach the first insulator and the first conductor. and providing a third conductive material in contact with the inner wall of the third opening, the first insulator, and the first conductive material. forming a fourth insulator on the third conductor; and forming a fourth insulator on the third conductor. and forming a fourth conductor on the first insulator, the fourth conductor being thicker than the second insulator. Insulators that have high hydrogen permeability suppression properties are used, and the dry etching process At the stage where at least the upper surface of the first conductor is exposed, the etching gas contains carbon and fluorine, and a semiconductor device comprising a gas in which the atomic ratio of carbon is 50% or more of the atomic ratio of fluorine. This is a method for producing the above.

[0020] In the above, in the step of forming the third insulator, the third insulator is formed by using a PECVD method. A first silicon oxide film is formed, and a second oxide film is formed on the first silicon oxide film by APCVD. In the above, it is preferable to form a film of silicon carbide. In the step, a fourth conductor is formed, a fifth insulator is formed on the fourth conductor, and the fourth It is preferable to perform CMP processing so that the conductor is exposed. In the etching process, the etching gas contains argon, and the flow rate of argon is It is preferable that the flow rate of the entire gas is 90% or more.

[0021] In the above, the first insulator is formed by oxidizing a target containing aluminum. It is preferable that the film is formed by sputtering in an atmosphere containing The metal oxide is a tantalum oxide containing In, an element M (where M is Al, Ga, Y, or Sn), and Zn. It is preferable to form the film by a sputtering method using a target. Effect of the Invention

[0022] According to one embodiment of the present invention, a capacitor or a semiconductor device that can be miniaturized or highly integrated is provided. According to one embodiment of the present invention, a capacitor or a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a capacitor element having large capacitance can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Cut.

[0023] According to one embodiment of the present invention, a semiconductor device or a memory device capable of retaining data for a long period of time can be provided. According to one embodiment of the present invention, a semiconductor device capable of writing data at a high speed can be provided. According to one embodiment of the present invention, a device or a storage device can be provided that can reduce power consumption. According to one embodiment of the present invention, a semiconductor device or a memory device which can achieve the above can be provided. It is possible to provide a semiconductor device or memory device having a large storage capacity per unit area. According to one embodiment of the present invention, a novel semiconductor device or memory device can be provided.

[0024] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these are described in the specification. The above will become apparent from the description, drawings, claims, etc. From the above description, it is possible to extract other effects. [Brief description of the drawings]

[0025] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Diagram 2] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 3] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 18] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 19] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 20] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 24] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Diagram 25] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 26] FIG. 1 illustrates a range of atomic ratios of metal oxides according to one embodiment of the present invention. [Figure 27] FIG. 1 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 28] FIG. 1 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 29]FIG. 1 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Diagram 30] FIG. 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. [Diagram 31] 1A and 1B are a block diagram and a circuit diagram illustrating a configuration example of a memory device of one embodiment of the present invention. [Diagram 32] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device of one embodiment of the present invention. [Diagram 33] 1A to 1C are a block diagram and a circuit diagram illustrating a configuration example of a semiconductor device of one embodiment of the present invention, and a timing chart illustrating an operation example of the semiconductor device. [Diagram 34] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device of one embodiment of the present invention. [Diagram 35] 1A to 1C are a circuit diagram illustrating a configuration example of a semiconductor device of one embodiment of the present invention and a timing chart illustrating an operation example of the semiconductor device. [Diagram 36] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 37] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 38] FIG. 2 is a top view of a semiconductor wafer according to one embodiment of the present invention. [Figure 39] 1A and 1B are a flowchart illustrating an example of a manufacturing process of an electronic component and a schematic perspective view of the electronic component. [Diagram 40] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Diagram 41] 1 is an AFM image according to an embodiment of the present invention. [Diagram 42] 1 is a cross-sectional STEM image according to an embodiment of the present invention. [Diagram 43] 1 is a cross-sectional STEM image according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, the embodiments will be described with reference to the drawings. It is possible to carry out the invention in various forms without departing from the spirit and scope of the invention. It will be readily understood by those skilled in the art that various modifications may be made to the mode and details of the present invention. The present invention should not be construed as being limited to the description of the following embodiment.

[0027] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown in the drawings. The figures are merely schematic illustrations, and are not limited to the shapes or values ​​shown in the drawings. During the manufacturing process, layers and resist masks may become unintentionally damaged due to processes such as etching. However, in order to make it easier to understand, they may be omitted. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, when referring to the same function, In some cases, the pitch patterns are the same and no particular reference numerals are attached.

[0028] In addition, the invention is easily understood, particularly in top views (also called "plan views") and perspective views. In order to simplify the description, some of the components may be omitted. The above information may be omitted.

[0029] In addition, in this specification and the like, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second In addition, the terms "the" or "the third" may be used interchangeably in the description of the present specification. The ordinal numbers listed in the specification do not match the ordinal numbers used to identify an aspect of the present invention. There are cases.

[0030] In addition, in this specification, the words "above" and "below" indicating the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The above words and phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0031] For example, in the present specification, it is explicitly stated that X and Y are connected. The cases are when X and Y are electrically connected and when X and Y are functionally connected. The case where X and Y are directly connected and the case where X and Y are directly connected are both considered to be disclosed in this specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. The connections other than those shown in the drawings or text are also included in the drawings or text. Let us assume that.

[0032] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0033] An example of a direct connection between X and Y is The elements that function as When a diode, display element, light-emitting element, load, etc. is not connected between X and Y, An element (e.g., a switch, transistor, or capacitor) that allows electrical connection between X and Y. (capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.) In this case, X and Y are connected.

[0034] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function of being on / off controlled. A switch can be in a conductive state (on) or a non-conductive state (off) to allow current to flow. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, X This also includes the case where and Y are directly connected.

[0035] An example of a case where X and Y are functionally connected is the case where the functional connection between X and Y is possible. Circuits that perform the functions of the following: logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc. ), voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) (e.g., circuits that generate One or more devices (such as a synthesis circuit, memory circuit, or control circuit) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X is If the signal is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected and cases where X and Y are functionally connected. This also includes the case where Y is electrically connected.

[0036] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A channel forming region is formed between the source and drain through the channel forming region. In this specification and the like, the term "channel formation region" refers to a region through which a current can flow. , the region through which current mainly flows.

[0037] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0038] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode overlaps with the semiconductor (the part through which current flows). The source region or the channel region This refers to the distance between the drain (drain region or drain electrode) and the In the transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one value or the maximum value in the region where the channel is formed. , the minimum or average value.

[0039] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The area where the gate electrode overlaps with the electrode (the area where the current flows) forms a channel. This refers to the length of the part of the region where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. That is, The channel width of a transistor may not be determined to a single value. In the fine print, the channel width is any one value or the maximum value in the region where the channel is formed. , the minimum or average value.

[0040] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter also referred to as the "effective channel width") of the transistor in a top view The channel width indicated by the For example, when the gate electrode covers the side of the semiconductor, the effective channel width becomes In some cases, the effect of the channel width becomes larger than that of the conventional method. In a transistor in which the gate electrode covers the side surface of the semiconductor, the channel formed on the side surface of the semiconductor In this case, the ratio of the channel formation region may be larger than the apparent channel width. , the effective channel width becomes larger.

[0041] In such cases, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known accurately, Channel width is difficult to measure accurately.

[0042] Therefore, in this specification, the apparent channel width is referred to as the "enclosed channel width (SCW: S In addition, in this specification, In this document, when simply referring to channel width, it means enclosed channel width or apparent channel width. In this specification, when the term "channel width" is used, It may refer to the effective channel width. Note that channel length, channel width, and effective channel The channel width, apparent channel width, and enclosed channel width are determined by analyzing cross-sectional TEM images. The value can be determined, for example, by

[0043] The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor. Elements with a concentration of less than 0.1 atomic percent can be considered impurities. For example, The DOS (Density of States) of the semiconductor increases and the crystallinity decreases. When the semiconductor is an oxide semiconductor, the semiconductor characteristics may be deteriorated. The impurities to be changed include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, These include elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, for example: Hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Oxides In the case of a semiconductor, water may also function as an impurity. In some cases, oxygen vacancies may be formed due to the inclusion of impurities. In this case, impurities that change the properties of a semiconductor include, for example, oxygen and Group 1 elements excluding hydrogen. , Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0044] In this specification and the like, a silicon oxynitride film is a film having a composition containing more oxygen than nitrogen. For example, the oxygen content is preferably 55 atomic % or more and 65 atomic % or less. , nitrogen is 1 atomic % or more and 20 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen The concentration range of 0.1 atomic % to 10 atomic % is also called oxynitride. A silicon film is a film whose composition contains more nitrogen than oxygen. Preferably, nitrogen is 55 atomic % or more and 65 atomic % or less, oxygen is 1 atomic % or more and 20 atomic % or less, Silicon concentration is 25 atomic % to 35 atomic % and hydrogen concentration is 0.1 atomic % to 10 atomic % It refers to what is included in the range.

[0045] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to:

[0046] In addition, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." In addition, the term "conductor" can be replaced with "conductive film" or "conductive layer." In addition, the term "semiconductor" can be replaced with "semiconductor film" or "semiconductor layer." can.

[0047] In addition, the transistors shown in this specification and the like are not field-effect transistors unless otherwise specified. In addition, unless otherwise specified, the transistors shown in this specification and the like are n A transistor of this type is a channel type. Therefore, its threshold voltage (also called "Vth") shall be greater than 0 V unless otherwise stated.

[0048] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Almost parallel" means that the two straight lines are arranged at an angle of -30° to 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° to 100°. Therefore, it includes the case where the angle is between 85° and 95°. " refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0049] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0050] In this specification, the term "barrier film" refers to a film that prevents impurities such as hydrogen and oxygen from passing through. When the barrier film has conductivity, it is called a conductive barrier film. Sometimes I call.

[0051] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the active layer of a transistor, the metal An oxide may be called an oxide semiconductor. In other words, the transistor can be a transistor including an oxide or an oxide semiconductor.

[0052] (Embodiment 1) <Example of semiconductor device configuration> In the following, a semiconductor device including a transistor 400 and a capacitor 100 according to one embodiment of the present invention will be described. An example of a semiconductor device will now be described.

[0053] FIG. 1 is a cross-sectional view of a semiconductor device having a transistor 400 and a capacitor element 100. The capacitor element 100 is made of an insulator 4 having a function of suppressing the permeation of impurities such as water or hydrogen. The capacitor element 100 and the transistor 400 are disposed on the same side. The capacitors 400 are electrically connected by conductors 108b disposed through insulators 420. In this manner, the insulator 420 and the conductor 108b form a capacitor element 100 and a transistor. Since the transistor 400 is disposed between the insulator 420 and the conductor 108, the transistor 400 is b, the capacitance element 100 has an insulator 420 and a conductor 108b. It can also be said that

[0054] The transistor 400 includes an oxide 406, at least a portion of which is The oxide 406 functions as a channel formation region of the transistor 400. It is preferable that the transistor is disposed on the insulator 402 provided on the transistor. The photoresist 400 has a conductor 404 on an oxide 406, and the oxide 406 and the conductor 404 are There is an insulator 412 between the conductor 404 and the gate of the transistor 400. 404 and insulator 412 serves as a gate insulator corresponding to conductor 404. For example, The region of the oxide 406 that overlaps with the conductor 404 serves as a channel formation region of the transistor 400. The oxide 406 functions as a gate insulating film, and a portion of the region that does not overlap with the conductor 404 of the transistor 400 is The oxide 406 overlaps with the conductor 404, which functions as one of the source and drain regions. Another part of the region that is not connected to the source region is used as the other of the source region and drain region of the transistor 400. It works like this.

[0055] The oxide 406 is electrically connected to a region that functions as one of the source and drain regions. A conductor 108a is disposed so as to connect the source and drain regions of the oxide 406. The conductor 108b is disposed so as to be electrically connected to the region that functions as the other of the regions. Thus, the conductor 108a is one of the source and drain electrodes of the transistor 400. conductor 108b serves as the source and drain electrodes of transistor 400. In addition, the oxide 406, the insulator 412, and An insulator 410 is preferably disposed over the conductor 404. The conductor 108b is preferably formed so as to fill an opening formed in the insulator 410. It is.

[0056] In the channel formation region of the oxide 406 of the transistor 400, oxygen vacancies are reduced. By reducing impurities such as hydrogen or water, the transistor 400 can have good electrical characteristics. As a result, the reliability can be improved. The details will be described later.

[0057] <Example of capacitance element configuration> The capacitive element 100 includes an oxide 406, an insulator 412, a conductor 404, and an insulator 410. The insulator 422, the insulator 112, the insulator 114, and the insulator 116 are disposed on the insulator 422. The insulating material 420 is disposed in contact with the inner wall of the opening 115, the insulator 420, and the conductor 108b. A conductor 110, an insulator 130 disposed on the conductor 110, and a The conductor 120a and the conductor 120b are disposed on the substrate 120. 20a and conductor 120b may be collectively referred to as conductor 120.

[0058] Here, the conductor 110 functions as the lower electrode of the capacitive element 100, and the conductor 120 functions as the capacitor. The insulating material 130 functions as a dielectric for the capacitive element 100. The capacitive element 100 has an opening 115 that is not only a bottom surface but also a side surface. The upper electrode and the lower electrode face each other with a dielectric between them, and the capacitance per unit area is The deeper the opening 115, the greater the capacitance of the capacitor element 10. 0 can be increased. By increasing the capacitance, the miniaturization or high integration of semiconductor devices can be promoted. can be done.

[0059] The insulator 420 is formed by trapping impurities such as water or hydrogen from the upper layer, for example, the capacitor element 100. The insulator 420 can function as a barrier insulating film to prevent the insulator 420 from being mixed with the transistor 400. In the case of the above, an insulating material having a function of suppressing the permeation of impurities such as water or hydrogen can be used. It is preferable to use aluminum oxide, for example. It is possible to prevent impurities such as water from diffusing into layers below the insulator 420. The inductor 420 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule (N2 O, NO, NO2, etc.), and copper atoms and other impurities. In the following description, the term "insulating material" refers to a material having a function of suppressing the permeation of impurities. The same applies when describing materials. For example, the insulator 420 is insulator 422, The function of suppressing the permeation of water or hydrogen from either the body 112 or the insulator 114 is High is preferable.

[0060] Here, the insulator 420 is an oxide insulator formed by a sputtering method. It is preferable to use aluminum oxide, for example. 20, the insulator 410 is in contact with the insulator 420 via the surface of the insulator 410. By supplying oxygen to the insulator 410, the insulator 410 can be made in an oxygen-excess state. Oxygen can be supplied to the insulator 412 and the oxide 406 via the oxide layer 406 .

[0061] Additionally, the insulator 420 inhibits the permeation of oxygen (e.g., oxygen atoms or oxygen molecules). It is preferable to use an insulating material having the function of providing the insulating film, such as aluminum oxide. As a result, the upward diffusion of oxygen contained in the insulator 410, the oxide 406, etc. is suppressed. This allows oxygen to be effectively supplied to the oxide 406.

[0062] In this way, the insulator 420 is provided, and the channel forming region of the oxide 406 of the transistor 400 is By reducing oxygen vacancies and impurities such as hydrogen and water in the This gives the sta 400 good electrical properties and improves its reliability.

[0063] Also, the insulator 420 has an opening 11 in the insulator 422, the insulator 112, and the insulator 114. It is preferable that the insulating layer 5 functions as an etching stopper when the insulating layer 5 is formed. 420 includes at least one of an insulator 422, an insulator 112, and an insulator 114; It is preferable that the constituent elements and composition are different. For example, aluminum oxide is used. In this way, the insulator 420 functions as an etching stopper, The capacitance element 100 is formed in contact with the insulator 410, and the capacitance element 100 is formed in contact with the insulator 410. The impurities contained in the capacitor 100 enter the transistor 40 through the insulator 410. This can prevent the spread to 0.

[0064] At this time, the insulator 420 and the conductor 108b become the bottom of the opening 115. In this case, the opening 115 can be said to be an opening that reaches the insulator 420 and the conductor 108b. In addition, as shown in FIG. 1, the area of ​​the insulator 420 that overlaps with the opening 115, in other words, The thickness of the insulator 420 in the region in contact with the conductor 110 is the thickness of the insulator 420 in the other region. That is, the area of ​​the insulator 420 may have a recessed shape. do.

[0065] In addition, an insulator having the same elements as the insulator 420 is laminated on the insulator 420 by ALD. In this manner, the insulator 420 may be formed by the ALD method. By laminating, the transistor can be easily removed without the formation of gaps, cracks, pinholes, etc. This allows the insulating layer 400 to be covered against impurities such as hydrogen and water. The barrier properties of 20 can be improved more significantly.

[0066] It is preferable that an insulator 422 is disposed on the insulator 420. The insulator 422 may be For example, silicon oxynitride may be used. The conductor 108a and the conductor 108b are , so as to be embedded in the openings formed in the insulators 410, 420, and 422. Therefore, a part of the upper surface of the conductor 108a or the conductor 108b and The heights of the upper surfaces of the insulators 422 may be approximately the same.

[0067] Here, by providing the insulator 422, the conductor 108a and the conductor 108b are formed. Polishing processes (e.g., chemical mechanical polishing) to It is easy to perform processes such as chemical mechanical polishing (CMP). The body 422 is not necessarily provided as long as the conductor 108a and the conductor 108b can be formed. There is no need.

[0068] Openings provided in the insulators 410 and 420 and conductors embedded in the openings The cross-sectional shape of the conductor 108b is below the upper surface of the insulator 420 in the region in contact with the conductor 110. In other words, in the portion, the conductor 1 may have a reverse tapered shape. 08b may have a taper angle of 90° or more on the side. In some cases, the angle between the bottom surface and the side surface of the conductor 108b is 90° or more. In this portion, the side surface of the conductor 108b is approximately in contact with the upper surface of the insulator 402. It may be vertical.

[0069] The conductor 108b is located above the upper surface of the insulator 420 in the region in contact with the conductor 110. For example, the conductive body 108b has a curved surface in the portion. In this case, a curved surface may be provided between the side surface of the conductor 108b and the upper surface of the conductor 108b. That is, in the portion of the conductor 108b, the end of the side surface and the end of the top surface are preferably curved. It is preferable that the curve is continuous.

[0070] In this manner, the conductor 108b has a different shape between the portion above the insulator 420 and the portion below the insulator 420. In particular, it is preferable that the curved surface of the upper portion of the conductor 108b contacts the conductor 110. This can reduce the contact resistance between the conductor 108b and the conductor 110. Thus, either the source or drain of the transistor 400 and the lower electrode of the capacitive element 100 Therefore, the electrical connection between the capacitor 100 and the transistor 4 can be improved. 00 can be given good electrical characteristics.

[0071] The insulator 112 is disposed on the insulator 422, and the insulator 114 is disposed on the insulator 112. As described above, the depth of the opening 115, that is, the thickness of the insulator 112 and the insulator 114, By increasing the total, the capacitance of the capacitance element 100 can be increased. However, by increasing the thickness of the insulators 112 and 114, The internal stress of the body also increases, and the substrate may be warped. In the capacitor 100 shown in the embodiment, one of the insulators 112 and 114 is compressively stressed. and the other of the insulators 112 and 114 preferably has a tensile stress. In other words, the insulators 112 and 114 cancel each other's internal stresses by being stacked. It is preferable to reduce the internal stress of the entire laminated insulator.

[0072] The insulators 112 and 114 may be configured using the same type of elements. For example, Organosilane gas (e.g., TEOS (Tetra-Ethyl-Ortho-Silic In this case, the insulator 112 may be a silicon oxide film formed using a silicon oxide film formed using a silicon oxynitride (SiO2) or the like. The composition of the insulating material 114 is made different from the composition of the insulating material 112, and the directions of the internal stresses of the insulating material 114 and the insulating material 113 are made different from each other. For example, it is preferable to use the same type of organosilane gas (e.g., We have developed different types of chemical vapor deposition (CVD) using SiO2, TEOS, etc. Alternatively, the film may be formed by apor deposition.

[0073] If the internal stress is reduced to such an extent that the substrate does not warp, the insulator 112 Alternatively, only one of the insulating material 114 may be used.

[0074] Preferably, an insulator 116 is disposed on the insulator 114. The insulator 116 has an opening When etching is performed in 115, it functions as an etching stopper together with the conductor 110. Therefore, the insulator 116 has the same constituent elements, composition, etc. as the insulator 114. Preferably, the insulator 116 is different. For example, silicon nitride may be used as the insulator 116. In addition, the upper surface of the insulator 116 and the uppermost surface of the conductor 110 (the edge of the opening 115 of the conductor 110) It is preferable that the insulator 116 and the conductive member 117 are substantially the same. The body 110 includes the insulators 114, 112, 422, and 420. It is preferable that the insulator 116 is covered.

[0075] An opening 115 is formed in the insulator 422, the insulator 112, the insulator 114, and the insulator 116. Here, the side of the insulator 422, the side of the insulator 112, the side of the insulator 114, The side surface of the insulator 116 can be regarded as the inner wall of the opening 115. The top of 8b and the portion of insulator 420 that overlaps with opening 115 are referred to as the bottom of opening 115. This can be done.

[0076] As shown in FIG. 1, the cross-sectional shape of the opening 115 is such that the inner diameter becomes smaller as the opening 115 is deeper. In addition, the inner wall of the opening 115 has a cross-sectional shape that is approximately perpendicular to the upper surface of the insulator 402. The shape of the opening 115 as viewed from above may be rectangular or may be It may be a polygonal shape other than the above, or a polygonal shape with rounded corners. Alternatively, the opening 115 may be a circle including an ellipse. With this configuration, the capacitance element 100 and the transistor To increase the capacitance without increasing the occupation area of ​​a semiconductor device having the stator 400. can be done.

[0077] The conductor 110 is disposed in contact with the inner wall and the bottom surface of the opening 115. It functions as the lower electrode of the capacitor 100 and may be made of, for example, titanium nitride. For example, a conductive film that becomes the conductor 110 is formed by using an ALD method or a CVD method. As a result, even if the aspect ratio of the opening 115 is large, the conductor 110 can be formed with good coverage. Here, as described above, the upper part of the conductor 108b has a curved surface, and the By forming the conductor 110 from the conductive material 108b, the contact resistance between the conductor 110 and the conductive material 108b can be reduced. It can be reduced.

[0078] An insulator 130 is disposed over the conductor 110 and the insulator 116. The insulator 130 is It serves as a dielectric for the capacitive element 100 and may be, for example, hafnium oxide or hafnium silicate. (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate (Hf S x O y N z (x>0, y>0, z>0)), nitrogen doped hafnium aluminate HfAl x O y N z (x>0, y>0, z>0) or yttrium oxide It is preferable to use a high-k material. Even if the insulator 130 is made thick, the capacitance of the capacitance element 100 can be sufficiently ensured. By making the insulating layer 130 thicker, the leakage current between the conductor 110 and the conductor 120 is reduced. can be suppressed.

[0079] In addition, an insulating film that will become the insulator 130 is formed by using, for example, the ALD method or the CVD method. By this, even if the aspect ratio of the opening 115 is large, the insulator 130 can be formed with good coverage. In addition, the insulator 130 has a thickness in the region where it overlaps with the conductor 120. The thickness may be thicker than other layers.

[0080] In addition, the top surface of the conductor 110 is substantially aligned with the top surface of the insulator 116. Since the conductor 110 does not protrude from the opening 115, the insulator 130 can more reliably support the conductor 110. Since the conductor 110 and the conductor 120 can be covered, a short circuit between the conductor 110 and the conductor 120 can be prevented. Cut.

[0081] A conductor 120 is disposed on the insulator 130, covering the opening 115. As shown in FIG. The conductor 120 includes a conductor 120a and a conductor 120b disposed on the conductor 120a. It is preferable to use a laminated film of a and b. The conductor 120 functions as the upper electrode of the capacitor element 100. For example, titanium nitride is used as the conductor 120a, and tungsten is used as the conductor 120b. For example, the conductor 120 can be formed by using the ALD method or the CVD method. By forming a conductive film that will become the conductor 120a and a conductive film that will become the conductor 120b, an opening 115 The conductors 120a and 120b are formed with good coverage even if the aspect ratio of the conductors is large. It is possible.

[0082] The conductor 120 also has an area that protrudes from the opening 115 and overlaps with the insulator 116. In order to have such a region, the conductor 12 is preferably formed by using a photolithography method or the like. In this case, the insulator 116 of the conductor 120b is formed. The average surface roughness (Ra) of the upper surface of the region overlapping with is 4 nm or less, preferably 2 nm or less, more preferably In this manner, the upper surface of the conductor 120b is in contact with the opening 115. Since the area near the edge of the photolithography In particular, the electron beam is used for the exposure. When using a beam, the effect of diffuse reflection due to the unevenness of the upper surface of the metal film becomes more pronounced. In order to prevent this, it is preferable to improve the flatness of the region. By improving the flatness, photolithography can be performed more precisely.

[0083] In this specification, the average surface roughness (Ra) is defined as follows: The arithmetic mean roughness defined in ISO4287:1997 can be applied to curved surfaces. It is a three-dimensional extension of the 3D model, and is the average absolute value of the deviation from the reference plane to the specified plane. be expressed.

[0084] The average surface roughness (Ra) is the distance from the reference surface to the specified surface when the specified surface is expressed as Z = F (X, Y). It is expressed as the average of the absolute deviations of the

[0085]

number

[0086] Here, the designated surface is the surface to be measured for roughness, and has coordinates (X1, Y1, F(X1, Y1)),(X1,Y2,F(X1,Y2)),(X2,Y1,F(X2,Y1)),( Let the area be a rectangle represented by four points: X2, Y2, F(X2, Y2).

[0087] In addition, the area of ​​the rectangle formed by projecting the specified surface onto the XY plane is S0, and the height of the reference surface (the average The average surface roughness (Ra) was measured using an atomic force microscope (AFM). This can be measured using a Force Microscope.

[0088] The conductor 120 does not necessarily have to be a laminated film. For example, the conductors 120a and Alternatively, a configuration using either the conductor 120b or the conductor 120b may be used.

[0089] Preferably, an insulator 150 is disposed over the conductors 120 and the insulator 130 . The insulator 150 may be any of the insulators that can be used for the insulator 410.

[0090] In the above, the configuration of the capacitor element 100 formed on the conductor 108b has been described. As explained above, it is preferable that the connection portion 160 is also formed on the conductor 108a. 0, the conductor 108a of the transistor 400 and various circuit elements or wiring It can be easily connected to wires, etc.

[0091] The connection portion 160 includes an insulator 422, an insulator 112, an insulator 114, an insulator 116, and an insulator 130 and is formed to be embedded in an opening 117 formed in an insulator 150 . The connection portion 160 is disposed in contact with the inner wall of the opening 117, the insulator 420, and the conductor 108a. The conductor 162a is connected to the inner conductor 162b, and the conductor 162b is formed inside the conductor 162a. In the following description, the conductor 162a and the conductor 162b are collectively referred to as the conductor 162. This may be the case.

[0092] Here, the insulator 420 and the conductor 108a form the bottom of the opening 117. The opening 117 can be said to be an opening that reaches the insulator 420 and the conductor 108a. 1, the area of ​​the insulator 420 that overlaps with the opening 117, in other words, the insulator The thickness of the region of the insulator 420 in contact with the conductor 162a is the thickness of the insulator 420 other than the region. That is, the area of ​​the insulator 420 may have a recessed shape. do.

[0093] The conductor 108a has a similar structure to the conductor 108b. The cross-sectional shape of the opening provided in the insulator 420 and the conductor 108a embedded in the opening The shape of the insulator 420 is an inverted tapered portion below the upper surface of the region in contact with the conductor 162a. In other words, the side surface of the conductor 108a may have a tapered shape in this portion. In some cases, the par angle is 90° or more. It can also be said that the angle between the surface and the top surface of the insulator 402 may be greater than 90°. In this portion, the side surface of the conductor 108a is approximately perpendicular to the upper surface of the insulator 402. It's fine.

[0094] The conductor 108a is located above the upper surface of the insulator 420 in the region in contact with the conductor 162a. For example, the conductive body 108a has a curved surface in the portion. In the above, a curved surface is provided between the side surface of the conductor 108a and the upper surface of the conductor 108a. That is, in the portion of the conductor 108a, the end of the side surface and the end of the top surface are preferably It is preferable that the conductive body 108a is curved and continuous. In the portion, the conductive material 162a is not in contact with the conductive material 162a, in other words, the portion does not overlap with the opening 117. Therefore, no curved surface is formed.

[0095] In this manner, the conductor 108a has a different shape between the portion above the insulator 420 and the portion below the insulator 420. In particular, it is preferable that the curved surface of the upper portion of the conductor 108a contacts the conductor 162a. This makes it possible to reduce the contact resistance between the conductor 108a and the conductor 162a. This allows the potential between either the source or drain of transistor 400 and connection 160 to be This allows for good electrical connection.

[0096] The conductor 162 can have the same structure as the conductor 120. The conductor 62a has the same structure as the conductor 120a, and the conductor 162b has the same structure as the conductor 120b. It is preferable that the conductor 162 is not necessarily a laminated film. For example, A configuration using either the conductor 162a or the conductor 162b may be used.

[0097] Next, the constituent materials of the transistor 400, the capacitance element 100, the connection portion 160, etc. He explains.

[0098] [substrate] A substrate for forming a semiconductor device having the capacitance element 100 and the transistor 400 is For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. For example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (Yttria As for semiconductor substrates, for example, For example, semiconductor substrates such as silicon and germanium, or silicon carbide and silicon germanium A compound semiconductor consisting of gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, the semiconductor substrate having an insulating region therein, e.g. For example, there is the SOI (Silicon On Insulator) substrate. Examples of substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. There are substrates with nitrides, substrates with metal oxides, etc. Furthermore, there are substrates with insulators. Substrates with conductors or semiconductors, and semiconductor substrates with conductors or insulators , a substrate in which a semiconductor or an insulator is provided on a conductive substrate, etc. The elements provided on the substrate may be a capacitance element, a resistance element, or the like. These include resistors, switch elements, light-emitting elements, and memory elements.

[0099] A flexible substrate may be used as the substrate. The method of providing the transistor is to fabricate the transistor on a non-flexible substrate and then Another method is to peel off the capacitor and transfer it to a flexible substrate. It is preferable to provide a peeling layer between the substrate and the transistor. Alternatively, a sheet, film, foil, or the like may be used. The substrate may also be stretchable. The substrate may also have the property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate may have a property of not returning to its original shape. m or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less. By thinning the substrate, it is possible to fabricate semiconductor devices having transistors. In addition, by making the substrate thinner, it is possible to reduce the weight of the device when using glass, etc. It may also have elasticity or the ability to return to its original shape when bending or pulling is stopped. Therefore, it is necessary to reduce the shock applied to the semiconductor device on the board when it is dropped. That is, a robust semiconductor device can be provided.

[0100] The flexible substrate may be, for example, a metal, an alloy, a resin, or a glass. The fibers of these materials can be used. The lower the linear expansion coefficient of the flexible substrate, the better. The substrate is preferably a flexible substrate, since it is less likely to deform due to the environment. Expansion rate is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less The resin may be, for example, polyester, polyolefin, or poly. Amides (nylon, aramid, etc.), polyimides, polycarbonates, acrylics, etc. In particular, aramid has a low linear expansion coefficient and is therefore suitable as a flexible substrate. .

[0101] [Insulator] Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0102] The transistor is made of an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor, the electrical characteristics of the transistor can be stabilized. For example, 420, an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen is used. That's good.

[0103] Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include: Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neo Insulators containing zinc, hafnium or tantalum may be used in single or multilayer configurations.

[0104] For example, the insulator 420 may be aluminum oxide, hafnium oxide, magnesium oxide, or the like. , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide Metal oxides such as tantalum, neodymium oxide, or tantalum oxide, silicon oxide nitride, or nitride Silicon or the like may be used.

[0105] Insulator 402, insulator 412, insulator 410, insulator 422, insulator 112, insulator 1 14, the insulator 116 and the insulator 150 may be, for example, boron, carbon, nitrogen, oxygen, Fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, Rumanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum For example, the insulator 402 may be an insulator including a tantalum. Insulator 412, insulator 410, insulator 422, insulator 112, insulator 114, insulator 116, and The insulator 150 may be silicon oxide, silicon oxynitride, silicon nitride oxide, or , preferably comprising silicon nitride.

[0106] Insulator 412 and insulator 130 preferably comprise an insulator with a high dielectric constant. For example, the insulator 412 and the insulator 130 may be made of gallium oxide, hafnium oxide, zirconium oxide, or the like. Oxides containing ruthenium, aluminum and hafnium, oxide-nitride with silicon and hafnium, oxide-nitride with silicon and hafnium, and hafnium-containing oxide nitrides or silicon and hafnium-containing nitrides. Alternatively, the insulator 412 and the insulator 130 may be made of silicon oxide or silicon oxide. It is preferable that the insulating film has a laminated structure of silicon nitride and an insulator having a high relative dielectric constant. Silicon and silicon oxynitride are thermally stable and can be combined with high dielectric constant insulators. By combining these layers, it is possible to obtain a laminated structure that is thermally stable and has a high relative dielectric constant. For example, Insulator 412 and insulator 130 may be made of aluminum oxide, gallium oxide or By making the hafnium contact with the oxide 406, silicon oxide or silicon oxynitride It is possible to prevent silicon contained in the capacitor from being mixed into the oxide 406. For example, silicon oxide or silicon oxynitride is used in the insulator 412 and the insulator 130. By making the contact with the oxide 406, aluminum oxide, gallium oxide or A trap center is formed at the interface between hafnium oxide and silicon oxide or silicon oxynitride. The trap center may form a transistor by capturing electrons. In some cases, the threshold voltage can be shifted in the positive direction.

[0107] The insulator 410, the insulator 422, the insulator 112, the insulator 114, and the insulator 150 are It is preferable to have an insulator with a low dielectric constant. For example, the insulator 410, the insulator 422, The insulators 112, 114, and 150 are made of silicon oxide or silicon oxynitride. , silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, and oxide doped with carbon. silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or It is preferable that the insulating material 410, the insulating material 422, and the insulating material 112 are made of resin or the like. The insulator 114 and the insulator 150 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, or the like. Silicon, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, Silicon oxide doped with carbon and nitrogen or silicon oxide having voids, and a resin. It is preferable that the layer has a laminated structure. Silicon oxide and silicon oxynitride are thermally stable. Therefore, by combining it with resin, a laminated structure with thermal stability and low dielectric constant can be achieved. Examples of the resin include polyester, polyolefin, polyamide (naphthalene, etc.). Examples include: iron, aramid, polyimide, polycarbonate, or acrylic.

[0108] [conductor] Conductor 404, conductor 108a, conductor 108b, conductor 120b, and conductor 16 2b: Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium , molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium A metal element selected from aluminum, zirconium, beryllium, indium, ruthenium, etc. Materials containing one or more impurities such as phosphorus can also be used. Silicon is a semiconductor with high electrical conductivity, and silicides such as nickel silicide are It may be used.

[0109] In addition, the conductors, particularly the conductor 110, the conductor 120a, and the conductor 162a, , a conductive material containing a metal element and oxygen contained in a metal oxide applicable to oxide 406 Alternatively, the conductive material containing the above-mentioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium tin oxide, indium oxide containing tungsten oxide, indium oxide containing tungsten oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium zinc oxide, and silicon-doped indium tin oxide were used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the oxide 406. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator, etc.

[0110] In addition, a plurality of conductive layers made of the above materials may be laminated. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated material that combines the above-mentioned material containing a metal element and a conductive material containing nitrogen is In addition, the above-mentioned metal element-containing material, the conductive material containing oxygen, and the nitrogen A laminated structure in which the conductive material containing the element is combined with the conductive material containing the element may be used.

[0111] <Method of manufacturing a capacitor element> Next, a semiconductor device having the transistor 400 and the capacitor element 100 according to the present invention is fabricated. The manufacturing method will be described with reference to FIGS.

[0112] The method for manufacturing a semiconductor device includes forming an insulator 420 on a transistor 400 having an oxide 406. forming an insulator 422 on the insulator 420; and a first insulator 422 that reaches one of the source and drain of the transistor 400. An opening is formed in the first opening and a second opening is formed in the second opening that reaches the other of the source and drain of the transistor 400. and filling the first opening with a conductor 108a and the second opening with a conductor 108b. and forming an insulator 112 on the insulator 422, the conductor 108b, and the conductor 108a. Then, a process of forming the insulator 114 and the like and a dry etching process are performed to form the insulator 420 and forming an opening 115 reaching the conductor 108b; forming a conductor 110 in contact with the conductor 108b; forming an insulator 130 on the insulating layer 120; and forming a conductor 120 on the insulating layer 130. has.

[0113] The following mainly describes in detail a method for forming the capacitor element 100 on the transistor 400. An example of a method for manufacturing the transistor 400, that is, a method for forming the insulator 422, will be described. The process of embedding the conductors 108a and 108b in the openings will be described later. do.

[0114] Hereinafter, a conductor (such as a conductor film or a conductor layer) used in a semiconductor device according to the present embodiment will be described. ), insulator (can also be called an insulator film, an insulator layer, etc.), Conductors (which can also be called semiconductor films, semiconductor layers, etc.), oxides (which can also be called oxide films, oxide layers, etc.) The deposition of the SiO2 film can be performed by sputtering, CVD, molecular beam epitaxy (MBE), etc. BE:Molecular Beam Epitaxy, Pulsed Laser Deposition (PLD) It is performed using the Pulsed Laser Deposition (ALD) method or the ALD method. It is possible to do so.

[0115] The CVD method is a process that uses plasma (PECVD). Enhanced CVD method, Thermal CVD (TCVD) These methods are further classified into the VD method, which uses light, and the Photo CVD method, which uses light. Depending on the source gas, metal CVD (MCVD: Metal CVD) method, metal organic CVD method (MOCVD: Metal Organic CVD) method. Depending on the pressure in the deposition chamber, deposition is carried out under atmospheric pressure (APCVD: Atmospheric Pressure CVD). The Mospheric Pressure CVD method deposits films under reduced pressure below atmospheric pressure. LPCVD (Low Pressure CVD) method, etc. This can be done.

[0116] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the workpiece because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device ) may become charged up by receiving an electric charge from the plasma. When accumulated electric charges destroy wiring, electrodes, elements, etc., contained in a semiconductor device. On the other hand, in the case of thermal CVD, which does not use plasma, such plasma damage occurs. Since the thermal CVD method does not require any heat treatment, the yield of the semiconductor device can be increased. Since no plasma damage occurs in the film, a film with few defects can be obtained.

[0117] In addition, the ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with fewer defects can be produced. is obtained.

[0118] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is not easily affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it ideal for achieving high aspect ratios. However, the ALD method has a relatively low deposition rate. Because the deposition rate is slow, it can be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases this is preferable.

[0119] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, the film formation By changing the flow rate ratio of the source gas while heating, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition using a vacuum, the time required for deposition is shorter due to the time required for transportation and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0120] In addition, the sputtering method uses a direct current (DC) power supply for the sputtering power supply. ct Current) sputtering method, and the pulse D method, which applies a bias in a pulsed manner C sputtering method, RF (Radio Frequency) cy) A sputtering method may be used. Also, a magnet mechanism provided inside the chamber may be used. Netron sputtering method, bias sputtering method in which a voltage is applied to the substrate during film formation, A reactive sputtering method performed in a reactive gas atmosphere may also be used. PESP (parallel electron sputtering) is a deposition method using a sputtering device. ode sputtering, or facing target sputtering equipment. The membrane method, VDSP (vapor deposition sputtering), It may be used.

[0121] The film formed by the above method may be processed by lithography or the like. In the lithography method, the resist is first exposed through a mask. The regions are removed or left using a developer to form a resist mask. By etching through a resist mask, conductors, semiconductors, insulators, etc. can be obtained as desired. For example, KrF excimer laser light, ArF excimer laser light, The resist is removed using ultraviolet (EUV) light, X-rays, and other light sources. A resist mask can be formed by exposing the substrate to light. A liquid immersion technique may be used in which the substrate is exposed to light by filling the substrate with liquid (e.g., water). Alternatively, an electron beam or an ion beam may be used. In this case, the mask is not necessary. Note that the resist mask can be removed by ashing or other similar methods. Dry etching is performed, wet etching is performed, and after dry etching Wet etching is performed, or wet etching is performed followed by dry etching. It is possible to carry out the theory.

[0122] Moreover, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. When a hard mask is used, a hard mask is formed on the film to be processed (hereinafter, referred to as the processed film). First, an insulating film and a conductive film are formed as the hard mask material, and then a resist mask is formed on top of the insulating film and a hard mask is formed. The hard mask can be formed into a desired shape by etching the hard mask material. The etching of the film may be performed after removing the resist mask, or after removing the resist mask. In the latter case, the resist mask may be lost during etching. After etching the film to be processed, the hard mask may be removed by etching. On the other hand, if the hard mask material does not affect the post-process or can be used in the post-process, it is not necessary It is not necessary to remove the hard mask.

[0123] After forming the above mask, the film to be processed is processed by dry etching or wet etching. Dry etching is suitable for fine processing. .

[0124] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. : Capacitively Coupled Plasma (CAP) etching equipment is used. Hereinafter, this etching system will be referred to as a parallel plate dry etching system or CC system. It is sometimes called a P etching device. It is a capacitively coupled plasma etch device with parallel plate electrodes. The measuring device may be configured to apply a high-frequency power source to one of the parallel plate electrodes. A configuration in which a plurality of different high frequency power sources are applied to one of the parallel plate electrodes may also be used. Alternatively, a high-frequency power source having the same frequency may be applied to each of the parallel plate electrodes. A configuration in which high-frequency power sources with different frequencies are applied to each of the row and plate electrodes may also be used. A dry etching apparatus having a high-density plasma source can be used. The dry etching apparatus includes, for example, an inductively coupled plasma (ICP) A very coupled plasma etching apparatus or the like can be used.

[0125] First, the insulator 112 is formed on the conductor 108a, the conductor 108b, and the insulator 422. Then, an insulator 114 is formed on the insulator 112 (see FIG. 2). By adjusting the thickness of the insulator 114, the capacitance of the capacitor element 100 can be selected. Therefore, the insulator 112 and the insulator 113 can be adjusted to match the capacitance required for the capacitance element 100. The thickness of the film 114 may be set appropriately.

[0126] As described above, the insulators 112 and 114 are arranged so as to cancel each other's internal stresses. It is preferable that the insulator 112 has a compressive stress and the other has a tensile stress. The insulator 114 and the insulator 115 are formed to have different compositions by using different deposition methods. It is preferable.

[0127] In this embodiment, for example, silicon oxide is used as the insulator 112 and TEOS is used as the deposition gas. The film is formed by the PECVD method using silicon oxide as the insulator 114 and The film is formed by APCVD using TEOS.

[0128] In this way, the internal stress of the laminated film of the insulator 112 and the insulator 114 is reduced, and the warping of the substrate is prevented. By reducing the gap, when forming the opening 115 described later, the mask used in the process can be This allows for more precise exposure.

[0129] In addition, since the insulator 112 contacts the upper surfaces of the conductors 108a and 108b, The insulator 112 has a higher ability to oxidize the conductors 108a and 108b than the insulator 114. It is preferable that the value is low.

[0130] In this embodiment, the insulator 112 and the insulator 114 are formed into a two-layer structure. However, it is not limited to this. The internal stress must be reduced to such an extent that the board does not warp. Therefore, the insulator may have a structure of three or more layers, and either the insulator 112 or the insulator 114 may be formed of Alternatively, only one of the layers may be used as a single layer structure.

[0131] Next, the insulator 116 is deposited on the insulator 114. The insulator 116 is formed in the opening 115. When etching is performed, the conductive material 110 functions as an etching stopper. In addition, when a CMP process is performed in a later step, the insulator 116 is preferably Therefore, the insulator 116 functions as a stopper between the insulator 114 and the It is preferable that the constituent elements and composition of the insulating material 118 described later are different from those of the insulating material 118. When silicon oxynitride is used as the body 114 and the insulator 118, the insulator 116 is In this embodiment, the insulator 116 is formed by, for example, PECVD. Note that the insulator 116 is not necessarily provided.

[0132] Next, the insulator 118 is formed on the insulator 116 (see FIG. 3). The insulator 118 is It is preferable that the insulating layer 10 functions as a stopper for the CMP process in a later step. As the insulator 118, any insulator that can be used for the insulator 422 may be used. For example, when tungsten is used as the conductor 122A, oxide is used as the insulator 118. In this embodiment, the insulator 118 is formed by, for example, PECVD. Note that the insulator 118 is not necessarily provided.

[0133] Next, a conductor 122A serving as a hard mask and a hard mask The conductor 122A and the insulator 124A are formed as a film (see FIG. 4). This serves as a hard mask when forming the opening 115 in a later step. For example, a tungsten film is formed as the conductor 122A by sputtering. The insulator 124A is formed of silicon nitride by sputtering. It is also preferable that the conductive material 122A and the insulator 124A adjust the internal stress to reduce warpage of the substrate. It is.

[0134] Next, a resist mask is formed on the insulator 124A, and the resist mask is used to form a conductive layer. The dielectric 122A and the insulator 124A are etched to form the hard mask 122 and the hard A mask 124 is formed (see FIG. 5). The hard mask 122 and the hard mask 124 are is a hard mask for forming an opening 115, and an insulating layer is formed in the area overlapping the conductor 108b. The insulating body 124A has an opening that reaches the edge body 118. In addition, an organic coating film may be formed on the insulating body 124A. By forming an organic coating film between the insulator 124A and the resist mask, adhesion is improved. It may be possible to raise the

[0135] It is preferable to use dry etching for the etching. Examples of gases that can be used include C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, and SF6 gas. Gas such as CHF3 gas, Cl2 gas, BCl3 gas or SiCl4 gas, either singly or in combination. The above gases can be mixed and used. Alternatively, oxygen gas, helium gas, etc. can be added to the above gases. In addition, argon gas or hydrogen gas can be added as needed. The etching target (hard mask 122, hard mask 124 and organic coating film) The dry etching equipment can be selected from the above. A device can be used, but high-frequency power sources with different frequencies must be connected to each of the opposing electrodes. It is preferable to use a parallel plate type dry etching apparatus having such a structure.

[0136] Here, as described above, by reducing the warp of the substrate, the opening can be formed precisely. It is possible.

[0137] Next, the hard mask 122 and the hard mask 124 are used to etch the insulator 4 22, an opening 115 is formed in the insulator 112, the insulator 114, the insulator 116, and the insulator 118. The opening 115 is formed so as to overlap at least a portion of the conductor 108b (see FIG. 6). The opening 1 is formed at the conductor 108b and reaches the insulator 420. Since the aspect ratio of 15 is large, it is preferable to perform anisotropic etching. The etching process is similar to the formation of the hard mask 122 and the hard mask 124 shown in FIG. It is preferable to carry out the above steps continuously without exposing the mixture to the outside air.

[0138] For anisotropic etching to form the opening 115 with a large aspect ratio, dry etching is used. For the dry etching, it is preferable to use, for example, C4F6 gas, C5F6 Gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, Cl2 gas, BCl3 gas Gas such as SiCl4 or SiCl4 gas can be used alone or in combination of two or more gases. Alternatively, oxygen gas, helium gas, argon gas, hydrogen gas, etc. may be added to the above gas as appropriate. These etching gases can be added to the target to be etched (insulator 118, Cut appropriately according to the insulators 116, 114, 112, and 422. can be used instead.

[0139] The above-mentioned equipment can be used as the dry etching equipment, but the opposing electrodes themselves A parallel plate type dry etching device with a configuration in which high frequency power supplies with different frequencies are connected to each other is Since anisotropic etching can be performed relatively easily, this dry etching device is used. It is preferable that

[0140] When forming the opening 115, a curved surface is formed on the upper part of the conductor 108b as described above. In order to form a curved surface on the upper part of the conductor 108b, the dry etching process is preferably performed. In the step, when at least the upper surface of the conductor 108b is exposed, the ionized etching It is preferable to collide the gas with the upper surface of the conductor 108b. The top corners can be rounded off to form a curved surface.

[0141] In parallel plate dry etching equipment, a cathode drop is formed on the electrode on the side where the substrate is placed. At this time, the plasma generated in the chamber The positive ions contained in the etching gas are attracted to the self-bias and collide with the substrate. Therefore, by increasing the self-bias, the upper surface of the conductor 108b is more dense. By strongly bombarding the ions, it is relatively easy to form a curved surface on the upper part of the conductor 108b. To increase the self-bias, for example, a large voltage is applied to the electrode on the side where the substrate is placed. A force (e.g., a power greater than the power applied to the electrode facing the electrode) may be applied to the electrode. Here, as described above, high frequency power sources with different frequencies are connected to the opposing electrodes. By using a parallel plate type dry etching device with the above structure, The HF power supply for self-biasing and the FM power supply for self-biasing can be controlled independently. This can be done.

[0142] In addition, by lengthening the mean free path of the cations in the chamber, the cations can be The light can be incident at an angle close to perpendicular to the substrate surface. However, the positive ions can be collided with the bottom surface of the opening 115. To lengthen the mean free path of the electrons, for example, we need to increase the density of the plasma to a degree that does not make it too low. It is preferable to have a low pressure in the chamber.

[0143] In addition, by increasing the amount of cations in the chamber, the curvature of the upper part of the conductor 108b To increase the amount of cations in the chamber, e.g. For example, the etching gas may contain argon gas, which is easily ionized and has low reactivity. In this case, the flow rate of the argon gas should be 50% or more of the total flow rate of the etching gas. It is preferably 70% or more, and more preferably 90% or more.

[0144] In this way, at least the upper surface of the conductor 108b is exposed, and the ionized etchant The upper corners of the conductor 108b are then heated by blowing a gas into the upper surface of the conductor 108b. At this time, not only the upper part of the conductor 108b but also the Since the upper surface of the insulator 420 is also exposed to ion bombardment, the upper surface of the insulator 420 overlaps with the opening 115 of the insulator 420. The area where the insulator 420 is in contact with the insulating layer 420 may have a smaller thickness than other areas of the insulator 420. The region of interest 20 may have a concave shape.

[0145] In the above etching step, at least the upper surface of the conductor 108b is exposed. Therefore, it is preferable to add a gas containing a large amount of carbon to the etching gas. The carbon-rich gas contains carbon and fluorine, and the carbon atomic ratio is greater than the fluorine atomic ratio. It is preferable that the carbon content is 50% or more. Examples of such a carbon-rich gas include C4F6 gas, C5F6 gas, or C4F8 gas, either alone or in combination with two or more other gases, Alternatively, oxygen gas, helium gas, or argon gas may be used in combination with the above gas. Alternatively, hydrogen gas or the like can be added as appropriate.

[0146] By adding a gas containing a large amount of carbon and carrying out etching, the gas The carbon compounds are decomposed in the plasma and are deposited on the bottom surface of the opening 115. On the surface, the collision of positive ions and the deposition of carbon compounds occur in parallel. The carbon molecules collide with the insulator 420 through the deposited carbon molecules, and the carbon molecules overlap the opening 115 of the insulator 420. This can prevent the recessed area from being over-etched and penetrating the recessed area. Then, the opening 115 penetrates the insulator 420 and reaches the insulator 410 due to the collision of the positive ions. This can prevent the following:

[0147] In addition, when a gas containing a large amount of carbon as described above is added to the etching gas, the amount of oxygen is increased. It is preferable to add a nitrogen gas to the etching gas. By generating plasma in the existing atmosphere, the carbon contained in the carbon-rich gas is , which combines with oxygen to form carbon oxides. This results in the formation of carbon-rich gases, The amount of the carbon compounds produced is reduced. Increasing the flow rate increases the amount of carbon compounds, and increasing the flow rate of oxygen gas in the etching gas This reduces the amount of carbon compounds. Therefore, the amount of carbon-rich gas in the etching gas is The amount of carbon compounds deposited can be adjusted by adjusting the flow rate of the oxygen gas.

[0148] The carbon compounds also adhere to the inner wall of the opening 115. The carbon compound can function as a protective film for the inner wall of the opening 115. In order to prevent the inner wall of the opening 115 from being over-etched and the inner diameter of the opening 115 from being over-expanded, Therefore, in the etching step, the above carbon is added to the etching gas. By adding a gas containing a large amount of It is possible.

[0149] In addition, as the etching of the opening 115 progresses, the aspect ratio of the opening 115 increases. As the aspect ratio of the opening 115 increases, the carbon compound is absorbed deeper into the opening 115. This can be caused by penetration of the insulator 420 or bowing of the opening 115. This can cause defects in the shape, etc. As the etching progresses, the etching gas (e.g., the gas containing a large amount of carbon) is It is preferable to increase the flow rate of the gas in a stepwise manner. It is possible to supply the carbon compound to the same extent as at the shallow position of the port 115. The etching of the opening 115 is stopped at the top surface of the insulator 420 or in the film of the insulator 420. It is possible.

[0150] After etching, the hard mask 124 and the resist on the hard mask 124 are It is preferable to remove the mask. The resist mask is removed by ashing or other similar methods. A wet etching process is performed, or a dry etching process is performed. Dry etching is performed after wet etching or after wet etching. In addition, the resist can be removed during the etching process. The top mask and hard mask 124 may then be removed.

[0151] Next, a conductor 110A is deposited to cover the opening 115 and the hard mask 122 (FIG. 7). The conductor 110A will become the lower electrode of the capacitor element 100 in a later process. A is preferably formed in contact with the inner wall and bottom surface of the opening 115 having a large aspect ratio. For this reason, the conductor 110A is formed by a film forming method with good coating properties, such as the ALD method or the CVD method. In this embodiment, for example, the ALD method is used to form the nitride film. A titanium film is formed.

[0152] In addition, the conductor 110A is formed by a film forming method such as the ALD method. The conductor 110A can be formed with good coverage on the curved surface of the upper portion of the conductor 108b. This can reduce the contact resistance between the conductor 110 and the conductor 108b.

[0153] Next, a film of the filler 126 is formed on the conductor 110A (see FIG. 7). If the opening 115 can be filled to such an extent that the CMP process to be performed in the subsequent step can be performed, Therefore, a cavity may be formed in the opening 115. The filler 126 is an insulating material. In the present embodiment, for example, the filler 126 and the conductive material may be used. Then, a silicon oxide film is formed by using the APCVD method.

[0154] Next, a CMP process is performed to remove the layers above the insulator 116 and form the conductor 110. (See FIG. 8.) As described above, the insulators 118 and 116 are resistant to the CMP process. Since the CMP process functions as a stopper, the CMP process can be carried out in stages. For example, In the first stage, the filler 126, the conductor 110A, and the hard The mask 122 is removed, and the filler 126, the conductive material 127, and the conductive material 128 are removed. The conductive material 110A and the insulator 118 may then be removed.

[0155] As a result, the conductor 110 and the insulator 116 are in contact with each other at the edge of the opening 115. Therefore, the insulator 116 and the conductor 110 form the insulator 114, the insulator 112, the insulator The edge 422 and the insulator 420 may be covered.

[0156] Next, an etching process is performed to remove the filler 126 in the opening 115 (see FIG. 9). The etching process can be either wet etching or dry etching. Alternatively, a wet etch may be used to remove the filler 126 in the opening 115. In some cases, it may be easier to use a wet etching method. A hydrofluoric acid solution or the like may be used as the cleaning agent.

[0157] Here, as described above, insulator 114, insulator 112, insulator 422, and insulator 4 20 is covered by the insulator 116 and the conductor 110 and is therefore etched away. This can prevent the following:

[0158] Next, the insulator 130 is formed on the conductor 110 and the insulator 116 (see FIG. 10). The insulator 130 will become the dielectric of the capacitor element 100 in a later process. It is preferable that the conductive material 110 is formed in contact with the conductive material 110 provided on the inside of the opening 115 having a large area ratio. For this reason, the insulator 130 is preferably formed by a film forming method with good coating properties, such as an ALD method or a CVD method. In this embodiment, the film is preferably formed by using an oxidation method, for example, the ALD method. A film of hafnium is formed.

[0159] In addition, the insulator 130 is formed by a film forming method such as the ALD method, and the conductor 11 is formed with good coverage. By covering the upper electrode 100, it is possible to prevent a short circuit between the upper electrode and the lower electrode of the capacitor element 100. do.

[0160] In addition, the insulator 130 is made of the above-mentioned high-k material, particularly an oxide containing hafnium. In the case of a material containing a crystalline structure, a heat treatment may be performed to increase the dielectric constant. can.

[0161] Next, the conductor 120aA is formed on the insulator 130, and a conductor The conductor 120aA and the conductor 120bA are formed later (see FIG. 10). In this process, the conductor 120aA becomes the upper electrode of the capacitor element 100. It is preferable that the insulating material 130 is formed in contact with the insulating material 130 provided on the inside of the opening 115 having a large ratio. For this reason, the conductor 120aA is formed by a film forming method with good coating properties, such as the ALD method or the CVD method. In this embodiment, for example, the ALD method is used to form the nitride film. The conductor 120bA is formed by a deposition method with good embedding properties, such as a CVD method. In this embodiment, for example, a metal CVD method is used to form the film. A tungsten film is formed.

[0162] When the conductor 120bA is formed by using a metal CVD method, as shown in FIG. The average surface roughness of the upper surface of the conductor 120bA may become large. The area of ​​the conductor 120bA that overlaps with the vicinity of the center of the opening 115 is recessed to match the opening 115. This may be the case.

[0163] In this manner, the conductor 120aA and the conductor 120bA are formed, and thus the opening 115 Since the upper electrode of the capacitance element 100 can be provided in the insulating layer 100 with good embedding properties, the capacitance element 1 The capacitance of 00 can be increased.

[0164] In this embodiment, the conductor 120aA and the conductor 120bA have a two-layer structure. However, the present invention is not limited to this. If a terminal electrode can be provided, the conductor may have a structure of three or more layers. The conductor 120bA may have a single-layer structure on only one side.

[0165] Next, it is preferable to deposit a film 128 on the conductor 120bA (see FIG. 11). The film 128 preferably has a thickness that allows for the CMP process to be performed in the subsequent step. The film 128 may be made of an insulating material or a conductive material. For example, silicon oxynitride is deposited as the film 128 by using the PECVD method.

[0166] Next, a CMP process is performed to remove the film 128 and expose the upper surface of the conductor 120bA. (See FIG. 12.) At this time, the upper surface of the conductor 120bA is also subjected to the CMP process. In this manner, the conductor 120bB having improved flatness is formed on the conductor 120bA. By stacking the film 128 and performing a CMP process, the insulator of at least the conductor 120bB is The average surface roughness (Ra) of the upper surface of the region overlapping with 116 is 4 nm or less, preferably 2 nm or less. More preferably, the thickness of the upper surface of the conductor 120bB can be set to 1 nm or less. By reducing the average surface roughness of the conductor 120aA and the conductor 1 This allows for more precise photolithography of 20bB. When viewed from above, the area of ​​the conductor 120bA that overlaps with the vicinity of the center of the opening 115 is recessed. In such a case, the flatness of the region may not be improved.

[0167] If the upper surface of the conductor 120bB is sufficiently flat, the film 128 may be omitted. Alternatively, the CMP process may be performed directly on the conductor 120bA.

[0168] Next, an insulator 132A serving as a hard mask is formed on the conductor 120bB (FIG. 1 2. The insulator 132A is used to form the conductors 120a and 120b in a later step. In this embodiment, for example, the insulator 132A functions as a hard mask when Then, a silicon oxynitride film is formed by using the PECVD method.

[0169] Next, a resist mask is formed on the insulator 132A, and the resist mask is used to The edge 132A is etched to form the hard mask 132 (see FIG. 13). As shown in FIG. 1, by reducing the average surface roughness of the upper surface of the conductor 120bB, The resist mask can be formed relatively easily using a photolithography method. is a hard mask for forming the conductor 120a and the conductor 120b, and opening 1 The hard mask 132 is formed so as to cover the opening 115. It is preferable that the insulating layer 116 has an overlapping area with the insulating layer 116. Etching can be used.

[0170] Next, the conductor 120aA and the conductor 120bB are etched using a hard mask 132. Then, etching is performed to form the conductor 120a and the conductor 120b (see FIG. 13). The etching can be performed by wet etching or dry etching. In this embodiment, a dry etching process is performed. A capacitive element 100 is formed having an insulating material 130 and a conductive material 120 .

[0171] Next, an etching process is performed to remove the hard mask 132 (see FIG. 14). The etching may be a wet etching process or a dry etching process. In this embodiment, the wet etching process is performed. The upper part of the region not overlapping with the conductor 120 is removed by the wet etching process. As a result, the thickness of the region of the insulator 130 that overlaps with the conductor 120 may become thinner than that of the region of the insulator 130 that overlaps with the conductor 120. It may be thicker than the other areas.

[0172] Next, it is preferable to deposit an insulator 150 on the conductor 120 and the insulator 130. (See FIG. 15.) Here, the insulator 150 functions as an interlayer insulating film. For example, silicon oxynitride is deposited as the insulator 150 by the PECVD method.

[0173] Next, the insulator 422, the insulator 112, the insulator 114, the insulator 116, the insulator 130, and An opening 117 is formed in the insulator 150 (see FIG. 16). The opening 117 has at least A part of the insulating layer 420 is formed so as to overlap the conductor 108a. As described above, the opening 117 has a large aspect ratio, so it is anisotropic etching. It is preferable to carry out the following.

[0174] The opening 117 may be etched using the same method as the opening 115. It is possible to form an opening 117 with a large aspect ratio. In the region, a curved surface is formed on the upper part of the conductor 108a, similar to the conductor 108b described above. It is possible.

[0175] Next, the conductor 162a and the conductor 162b are formed so as to be embedded in the opening 117. (See FIG. 16.) The formation of the conductor 162a can be performed with reference to the description of the conductor 120a. The formation of the conductor 162b can be performed by referring to the description of the conductor 120b. In this manner, the connection portion 160 electrically connected to the conductor 108a can be formed. It can be formed.

[0176] In this manner, a semiconductor device including the transistor 400 and the capacitor 100 is manufactured. As shown in FIG. 2 to FIG. 16, the semiconductor device shown in this embodiment can be By using the method for manufacturing the semiconductor device, at least the capacitor element 100 is formed on the transistor 400. Since the electrodes are formed so as to overlap each other, the capacitance can be reduced without increasing the area occupied by the semiconductor device. In addition, the above-mentioned capacitor element and semiconductor device can be manufactured with high productivity. It can be manufactured.

[0177] <Modifications of the semiconductor device> The semiconductor device shown in this embodiment is not limited to that shown in FIG. Modifications of the semiconductor device shown in this embodiment mode will be described with reference to FIGS.

[0178] First, referring to FIG. 17(A) to FIG. 17(D), the structure in the vicinity of the conductor 108b is different from that in FIG. A different semiconductor device will now be described.

[0179] In the semiconductor device shown in FIG. 17A, the conductor 108b is connected to the conductor 108ba and the conductor 108 bb is a laminated structure, which is different from the semiconductor device shown in FIG. The body 108bb is a relatively electrically conductive material based on tungsten, copper, or aluminum. A conductive material having high conductivity may be used. The conductor 108ba may be water or hydrogen. It is preferable to use a conductive material that has the function of suppressing the permeation of impurities. tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. It is also preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen. The conductive material may be used in a single layer or a multilayer. Impurities such as hydrogen and water are absorbed by the conductors 108ba and 108bb. In addition, the conductor 108ba can be, for example, A By forming the film using the LD method or CVD method, the film can be formed with good coverage.

[0180] The semiconductor device shown in FIG. 17B includes an insulator 410 in which a conductor 108b is embedded, and The inner wall of the opening of the insulator 420 is covered with the insulator 109b, which is the same as the semiconductor device shown in FIG. Here, the insulator 109b is an insulator that can be used for the insulator 420. It is preferable to use an insulating material that prevents impurities such as water or hydrogen from passing through the insulating material 109b. It is preferable to use an insulating material having a function of suppressing the heat generation, such as aluminum oxide. This allows impurities such as hydrogen and water to be removed from the insulator 410. In addition, it is possible to prevent the conductor 108b from mixing with the oxide 406. The insulator 109b is formed by using, for example, an ALD method or a CVD method, so that the insulator 109b has good coverage. A film can be formed.

[0181] In the semiconductor device shown in FIG. 17C, a part of the conductor 108b does not overlap with the opening 115. In this way, the semiconductor device shown in this embodiment differs from the semiconductor device shown in FIG. The device has at least the opening 115, i.e., the capacitive element 100 is in contact with a portion of the conductor 108b. As shown in FIG. 17C, the opening 11 at the top of the conductor 108b is 5, a curved surface is formed, but the curved surface does not overlap with the opening 115 at the top of the conductor 108b. In the areas where there is no curved surface, the upper corners of the conductor 108b remain.

[0182] The semiconductor device shown in FIG. 17D has a corner remaining at the top of the conductor 108b. 1. The contact resistance between the conductor 110 and the conductor 108b is sufficiently reduced. If possible, the conductor 108b may have a corner at the top. To leave a corner at the top of 108b, for example, an opening 115 shown in FIG. In the process, the self-bias is reduced to reduce the number of ions colliding with the upper surface of the conductor 108b. The impact should be weakened.

[0183] Next, with reference to FIG. 18(A) to FIG. 18(E), the structure in the vicinity of the conductor 108a is compared with FIG. A different semiconductor device will now be described.

[0184] In the semiconductor device shown in FIG. 18A, the conductor 108a is a conductor 108aa and a conductor 108 The semiconductor device shown in FIG. 1 is different from the semiconductor device shown in FIG. 1 in that it has a laminated structure of ab. The body 108ab is a relatively electrically conductive material based on tungsten, copper, or aluminum. A conductive material having high conductivity may be used. The conductor 108aa may be made of water, hydrogen, or the like. It is preferable to use a conductive material that has the function of suppressing the permeation of impurities. tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. It is also preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen. The conductive material may be used in a single layer or a multilayer. Impurities such as hydrogen and water are absorbed by the conductors 108aa and 108ab. In addition, the conductor 108aa is, for example, A By forming the film using the LD method or CVD method, the film can be formed with good coverage.

[0185] The semiconductor device shown in FIG. 18B includes an insulator 410 in which a conductor 108a is embedded, and The inner wall of the opening of the insulator 420 is covered with the insulator 109a, which is the same as the semiconductor device shown in FIG. Here, the insulator 109a is different from the insulator device that can be used for the insulator 420. It is preferable to use an insulating material that prevents impurities such as water or hydrogen from passing through the insulating material 109a. It is preferable to use an insulating material having a function of suppressing the heat generation, such as aluminum oxide. This allows impurities such as hydrogen and water to be removed from the insulator 410. In addition, the inclusion of the insulating material 108a in the oxide 406 can be suppressed. The edge 109a is formed by using, for example, an ALD method or a CVD method, so that the edge 109a has good coverage. A film can be formed.

[0186] In the semiconductor device shown in FIG. 18C, the opening 117 overlaps the entire conductor 108a. 1. As shown in FIG. 18(C), the semiconductor device 108a is Since the entire portion of the conductor 108a overlaps the opening 117, no corners remain at the top of the conductor 108a, and the conductor 108a has a curved surface. is formed.

[0187] In the semiconductor device shown in FIG. 18(D), the opening 117 overlaps with the end of the upper surface of the conductor 108a. 1 in that the semiconductor device shown in FIG. Since the opening 117 does not overlap the edge of the upper surface of the conductor 108a, the upper part of the conductor 108a has a corner. As shown in FIG. 18(D), the central portion of the upper surface of the conductor 108a is It may become concave.

[0188] The semiconductor device shown in FIG. 18(E) is different in that a corner remains at the top of the conductor 108a. This is different from the semiconductor device shown in FIG. If the thickness can be reduced, the conductor 108a may have a corner at the top. In order to leave a corner at the top of the body 108a, for example, in the process of forming the opening 117, In this case, the self-bias is reduced to weaken the impact of ions colliding with the upper surface of the conductor 108a. Just make it better.

[0189] The semiconductor device shown in FIG. 1 has one transistor and one capacitor. However, the semiconductor device shown in this embodiment is not limited to this. As shown in FIG. 1, the transistor 400a and the capacitor 100a, and the transistor 400b and a capacitor 100b. and transistor 400b may share conductor 108a and connection portion 160. The transistor 400a and the transistor 400b shown in FIG. The description of the capacitance element 100a and the capacitance element 100b can be taken into consideration. The description in 00 can be taken into consideration.

[0190] The semiconductor device shown in FIG. 19 can be used, for example, in a memory cell of a storage device described later. The transistor 400a and the transistor 400b are connected to the conductor 108a and the connection By sharing 160, the top view of one set of transistor and capacitance element is Since the area occupied by the semiconductor device can be reduced, the semiconductor device can be highly integrated. Therefore, the storage capacity per unit area of ​​a storage device using the semiconductor device can be increased. It is possible to do so.

[0191] <Example of transistor configuration> Next, a configuration example of the above-mentioned transistor 400 will be described with reference to FIGS. 20 to 26. FIG. 20A is a top view of a transistor 400a according to one embodiment of the present invention. FIG. 20(B) is a cross-sectional view of the area indicated by the dashed line A1-A2 in FIG. FIG. 20C is a cross-sectional view of the transistor 400a in the channel length direction. 1A is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. The cross-sectional view in the channel width direction is shown. In the top view of FIG. 20(A), some of the layers are not shown for clarity. The channel length direction of the transistor is the direction parallel to the substrate. In the above, the source (source region or source electrode) and the drain (drain region or The channel width direction is the direction in which carriers move between the substrate and the drain electrode. It means a direction perpendicular to the channel length direction in a plane horizontal to the direction of the channel length.

[0192] As shown in FIGS. 20A, 20B, and 20C, the transistor 400a includes a conductor 310 ( The insulating material 302 is disposed on the conductor 310. The insulator 303 and the insulator 402 are arranged on the insulator 302, the insulator 303 and the insulator 402. The oxide 406a is placed on the oxide 406b, and the oxide 406b is placed on the oxide 406a. A conductor 416a1 and a conductor 416a2 are arranged on the upper surface of the insulating layer 406b at a distance from each other, and an oxide 406b, an oxide 406c disposed on the conductor 416a1 and the conductor 416a2; An insulator 412 disposed on the oxide 406c and at least partially overlapping the oxide 406b. The conductor 404 (conductor 404a, conductor 404b) disposed on the insulator 412 is 4b and conductor 404c).

[0193] As described above, the insulator 402, the oxide 406a, the oxide 406b, the oxide 406 c, the conductor 416a1, the conductor 416a2, the insulator 412, the conductor 404, etc. The insulator 410 is disposed on the insulating film 417a1. The conductor 108a and the conductor 108b are formed in the openings formed in the film 417a2. Although not shown in FIG. 20, an insulator 420 is disposed on the insulator 410 as described above. will be done.

[0194] The conductor 310 is provided in an opening formed in the insulator 301. A conductor 310a is formed in contact with the inner wall of the mouth, and a conductor 310b is formed further inside. Here, the height of the upper surfaces of the conductors 310a and 310b and the height of the upper surface of the insulator 301 are The height of the faces can be of the same order. The conductor 310 can function as one of the gate electrodes.

[0195] Here, the conductor 310a is made of a conductive material that is difficult for impurities such as water or hydrogen to permeate. In addition, for example, tantalum, tantalum nitride, ruthenium or ruthenium oxide is preferably used. It is preferable to use ruthenium or the like, and it may be a single layer or a multilayer structure. Impurities such as hydrogen and water diffuse from the lower layer of the body 401 through the conductor 310 to the upper layer. The conductor 310a can suppress the generation of hydrogen atoms, hydrogen molecules, water molecules, oxygen atoms, etc. molecules, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), It is preferable that at least one of the impurities such as copper atoms is difficult to penetrate. The same applies when describing a conductive material that is difficult for impurities to permeate. Since a has a function of suppressing oxygen permeation, the conductivity of the conductor 310b is reduced by oxidation. It is possible to prevent the deterioration.

[0196] The insulator 301 is disposed on an insulator 401 disposed on a substrate (not shown). The insulator 401 prevents impurities such as water or hydrogen from entering the transistor from the lower layer. The insulator 401 can function as a barrier insulating film to prevent impurities such as water or hydrogen from passing through. It is preferable to use an insulating material that is difficult to break down, such as aluminum oxide. This is preferable because it prevents impurities such as hydrogen and water from diffusing to layers above the insulator 401. The insulator 401 can suppress hydrogen atoms, hydrogen molecules, water molecules, and nitrogen atoms. It contains few impurities such as nitrogen atoms, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. In the following description, the term "insulating material through which impurities are hardly permeable" is used. The same is true when describing related materials.

[0197] In addition, the insulator 401 is difficult for oxygen (for example, oxygen atoms or oxygen molecules) to permeate. It is preferable to use an insulating material. This allows oxygen contained in the insulator 402 to be removed. This allows the oxide 406b to be effectively supplied with oxygen. It can be provided.

[0198] The insulator 303 has insulating properties that are difficult for impurities such as water or hydrogen, and oxygen to permeate. It is preferable to use a material such as aluminum oxide or hafnium oxide. This prevents impurities such as hydrogen and water from entering from the layer below the insulator 303. It is possible to suppress diffusion to layers above the insulator 303. The downward diffusion of the contained oxygen can be suppressed.

[0199] The insulator 402 is preferably formed using an insulator that releases oxygen when heated. Specifically, the thermal desorption spectrometry (TDS) Spectroscopy) showed that the amount of oxygen desorbed was 1.0×10 1 8 atoms / cm 3 More than 3.0×10 20 atoms / cm 3 That's all. It is preferable to use an insulator. The oxygen released by heating is also called "excess oxygen." By providing such an insulator 402 in contact with the oxide 406a, the oxide 406 In addition, the surface temperature of the membrane during the TDS analysis The temperature is preferably in the range of 100°C to 700°C, or 100°C to 500°C. stomach.

[0200] In addition, the concentration of impurities such as water, hydrogen, or nitrogen oxides in the insulator 402 is reduced. For example, the amount of hydrogen desorbed from the insulator 402 is preferably 50° C. to 100° C. in terms of TDS. In the range of 500°C, the amount of desorption converted into hydrogen molecules is Doing the math, it's 2 x 10 15 molecules / cm 2 Less than or equal to 1×10 15 Mol ecules / cm 2 Less than or equal to 5×10 14 molecules / cm 2 Below As long as it's below, that's fine.

[0201] The insulators 302, 303, and 402 can function as gate insulating films. Note that in the transistor 400a, the insulators 302, 303, and 402 is stacked on the insulating film 403. However, the present invention is not limited to this. For example, the gate insulating film may be made of an insulator 302 and an insulator 303. 403 and insulator 402 may be used in two or one layers.

[0202] Next, an oxide that can be used for oxide 406a, oxide 406b, and oxide 406c is This article describes metal oxides (hereinafter, also referred to as oxide semiconductors) that function as semiconductors. In this specification, metal oxides containing nitrogen are also referred to as metal oxides. Metal oxides containing nitrogen are also called metal oxynitrides (MEs). It may also be called tal oxynitride.

[0203] The metal oxides used as the oxide 406a, the oxide 406b, and the oxide 406c are at least It is preferable that the alloy contains at least indium. It is particularly preferable that the alloy contains indium and zinc. In addition to these, element M (element M is gallium, aluminum, silicon, phosphide, etc.) Uranium, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium, Tantalum , tungsten, or magnesium) It is preferable that

[0204] The metal oxide has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using metal oxides with a wide energy gap, The off-current of the transistor can be reduced.

[0205] Here, let us consider a case where the metal oxide contains indium, element M, and zinc. The atomic ratios of indium, element M, and zinc in the metal oxide are [In], [M] and [Zn].

[0206] The oxide 406a will be described below with reference to FIGS. 26(A), 26(B), and 26(C). The metal oxides that can be used for the oxide 406b and the oxide 406c include indium. A preferred range of the atomic ratio of element M to zinc will be described. 26(B) and 26(C) do not show the atomic ratio of oxygen.

[0207] In Figures 26(A), 26(B), and 26(C), the dashed lines indicate the ratio of [In]:[M ]:[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):2, The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):3, [I A line where the atomic ratio of [n]:[M]:[Zn]=(1+α):(1-α):4, and The line showing the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):5 is shown. vinegar.

[0208] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=2:1:β is The line where the atomic ratio is 1:1:β, [In]:[M]:[Zn ]=1:2:β atomic ratio line, [In]:[M]:[Zn]=1:3:β atomic ratio line The line showing the atomic ratio of [In]:[M]:[Zn]=1:4:β Represents a line.

[0209] In addition, the [In]:[M]: Metal oxides with an atomic ratio of [Zn]=0:2:1 and its neighboring values ​​form spinel-type crystals. Easy to structure.

[0210] In addition, multiple phases may coexist in a metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, For example, when the atomic ratio is close to [In]:[M]:[Zn]=0:2:1, the spinel In addition, the two phases of the hexagonal crystal structure and the layered crystal structure tend to coexist. When [M]:[Zn] is close to 1:0:0, the bixbyite-type crystal structure and layered structure When multiple phases coexist in a metal oxide, different crystal structures are formed. Between the crystal structures, grain boundaries may be formed.

[0211] Region A shown in FIG. 26(A) is a region of indium, element M, and zinc contained in a metal oxide. An example of a preferable range of the atomic ratio is shown.

[0212] By increasing the indium content of metal oxide, the carrier mobility of the metal oxide ( Therefore, metal oxides with a high indium content The carrier mobility is higher than that of metal oxides with a lower indium content.

[0213] On the other hand, when the content of indium and zinc in the metal oxide is low, the carrier mobility Therefore, the atomic ratio [In]:[M]:[Zn]=0:1:0 and its vicinity When it is near the value (for example, region C shown in FIG. 26(C)), the insulating property is high.

[0214] For example, the metal oxide used for the oxide 406b has high carrier mobility. On the other hand, the oxide 406a and the oxide The metal oxide used in 406c has a relatively high insulating property, as shown in region C in FIG. It is preferable that the atomic ratio is 1:1.

[0215] In particular, in the region B shown in FIG. 26(B), the carrier mobility is high and the reliability is high among the regions A. As a result, an excellent metal oxide with high thermal conductivity can be obtained.

[0216] In addition, in region B, [In]:[M]:[Zn]=4:2:3 to 4.1 and its vicinity Nearest values ​​are included. For example, [In]:[M]:[Zn]=5:3:4 In addition, in region B, [In]:[M]:[Zn]=5:1:6 and its neighboring values, and [In]:[M]:[Zn]=5:1:7, and neighboring values.

[0217] In addition, when In-M-Zn oxide is used as the metal oxide, the sputtering target It is preferable to use a target containing polycrystalline In-M-Zn oxide as the target. The atomic ratio of the metal oxide film is determined by the ratio of the metal atoms contained in the sputtering target. This includes a ±40% variation in the atomic ratio of metal elements. The composition of the sputtering target is In:Ga:Zn=4:2:4.1 [atomic ratio] In this case, the composition of the metal oxide film is In:Ga:Zn=4:2:3 [atomic ratio]. In addition, the composition of the sputtering target used for forming the metal oxide film may be When the composition is In:Ga:Zn=5:1:7 [atomic ratio], the composition of the metal oxide film is In some cases, the atomic ratio may be close to In:Ga:Zn=5:1:6.

[0218] The properties of metal oxides are not uniquely determined by the atomic ratio. Even if the ratio is the same, the properties of the metal oxide may differ depending on the formation conditions. When depositing a film of a silicide using a sputtering device, the atomic ratio of the target may deviate from the atomic ratio of the target. In addition, depending on the substrate temperature during film formation, the film may be formed with a higher concentration of [Zn] than the target. The [Zn] of the film may be small. Therefore, the region shown is a region where the metal oxide has a specific characteristic. The boundary between region A and region C is not strict. stomach.

[0219] In addition, it is preferable to use a metal oxide having a low carrier density for the transistor. In order to reduce the carrier density of the metal oxide, the impurity concentration in the metal oxide is reduced. In this specification and the like, the impurity concentration is low and the defect level density is low. The lower the degree of purity, the higher the purity of the oxide. The carrier density at 11 / cm 3 Less than 1 x 10 11 / cm 3 less than , and more preferably 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all. High-purity intrinsic or substantially high-purity intrinsic metal oxides have few carrier generation sources. Therefore, the carrier density can be reduced.

[0220] In addition, high-purity intrinsic or substantially high-purity intrinsic metal oxides have a low density of defect states. Therefore, the trap level density may also be low.

[0221] In addition, the charges trapped in the trap levels of metal oxides take a long time to disappear. Therefore, the trap level density is high. A transistor in which the channel formation region is formed in a metal oxide may have unstable electrical characteristics. There is a match.

[0222] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the metal oxide must be In order to reduce the impurity concentration in the metal oxide, it is effective to It is also preferable to reduce the concentration of impurities in the film. , alkaline earth metals, silicon, etc.

[0223] Here, the influence of each impurity in the metal oxide will be described.

[0224] When metal oxides contain silicon or carbon, which are group 14 elements, the metal oxide This leads to the formation of defect levels in the oxides. and secondary ion mass spectrometry (SIMS) of silicon and carbon near the interface with the metal oxide. Concentration obtained by secondary ion mass spectrometry 2 × 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0225] In addition, when alkali metals or alkaline earth metals are contained in metal oxides, defect levels are formed. Therefore, alkali metals or alkaline earth metals may form carriers. Transistors using the metal oxide contained therein tend to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide. Specifically, the alkali metal or alkali metal in the metal oxide obtained by SIMS The concentration of earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 at oms / cm 3 The following applies.

[0226] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. , oxygen deficiency (V o ) may be formed. o ) hydrogen enters the In some cases, electrons that are carriers are generated. In other cases, some of the hydrogen atoms are bonded to the metal atoms. It can combine with hydrogen to produce electrons, which are carriers. Transistors using metal oxides tend to be normally-on. It is preferable that the amount of hydrogen in the material is reduced as much as possible. The hydrogen concentration obtained by SIMS was 1×10 20 atoms / cm 3 Less than, preferred 1×10 19 atoms / cm 3 less than 5×10 18 atoms / c m 3 less than 1×10 18 atoms / cm 3 Less than.

[0227] In addition, oxygen vacancies (Vo ) is reduced by introducing oxygen into metal oxides. In other words, oxygen vacancies (V o ) is supplemented with oxygen And oxygen deficiency (V o ) disappears. Therefore, by diffusing oxygen into the metal oxide, Oxygen deficiency in transistors (V o ) and improve reliability.

[0228] As a method for introducing oxygen into a metal oxide, for example, a stoichiometric amount of oxygen may be added to the metal oxide. It is possible to provide an oxide that contains more oxygen than the stoichiometric composition. In the oxide, there is a region where oxygen is present in excess of the stoichiometric composition (hereinafter referred to as the excess oxygen region). In particular, when a metal oxide is used for a transistor, Providing an oxide having an excess oxygen region in an undercoat film near a transistor or an interlayer film Therefore, oxygen vacancies in the transistor can be reduced, and the reliability can be improved.

[0229] Metal oxide with sufficiently reduced impurities is used for the channel formation region of transistors. This makes it possible to impart stable electrical characteristics.

[0230] The metal oxide used for the oxide 406b is CAC (Cloud-Aligne In the following, the present invention will be described in detail. The CAC (Cloud-Aligned Coil) that can be used for the transistor shown in This article explains the configuration of the Multi-site OS.

[0231] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has a function of insulating in part and a function of semiconductor in the whole material. In addition, CAC-OS or CAC-metal oxide is used as the active layer of a transistor. When used in a layer, the conductive function is to allow the flow of electrons (or holes) that serve as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making the function of the material and the function of the material complement each other, the material can be switched (On / Off). ff function) to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, By separating the functions, the functionality of both can be maximized.

[0232] In addition, CAC-OS or CAC-metal oxide is a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a gap in the material. In addition, the conductive regions are observed as connected clouds with blurred edges. This may be the case.

[0233] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than one millimeter.

[0234] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide gap component due to the insulating region and a conductive region. In this configuration, when the carrier flows, In addition, carriers mainly flow in the narrow gap component. The component with a gap acts complementary to the component with a wide gap to produce a narrow gap. Carriers also flow to the wide gap component in conjunction with the component with a large gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field effect mobility can be obtained.

[0235] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a composite matrix.

[0236] The metal oxide may be a single crystal oxide semiconductor or a non-single crystal oxide semiconductor. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c-axi s aligned crystalline oxide semiconductor r), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), pseudo amorphous oxide semiconductor (a-like OS:am orphous-like oxide semiconductor) and amorphous acid Compound semiconductors.

[0237] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The nanocrystals are connected together to form a distorted crystal structure. In a region, a lattice arrangement is formed between a region having a uniform lattice arrangement and another region having a uniform lattice arrangement. This refers to the point where the direction of the

[0238] Nanocrystals are basically hexagonal, but are not limited to regular hexagons and may have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in the CAAC-OS, clear grain boundaries (grain bows) were observed even in the vicinity of the strain. In other words, the crystal grains are distorted due to the distortion of the lattice arrangement. This is because the CAAC-OS has a lattice structure in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms is shortened by the substitution of metal elements. This is believed to be because the distortion can be tolerated by changing the thickness of the material.

[0239] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter, the In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). Indium and element M tend to have a layered structure. When the element M in the (M,Zn) layer is replaced with indium, (In,M,Zn ) layer. Also, when the indium in the In layer is replaced with the element M, (In, M) layer.

[0240] CAAC-OS is a highly crystalline oxide semiconductor. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility caused by the grain boundaries occurs. In addition, the crystallinity of oxide semiconductors can be easily affected by impurities and defects. Therefore, CAAC-OS is an oxidized material with few impurities and defects (oxygen vacancies, etc.). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS has high heat resistance and reliability.

[0241] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. Sometimes it is indistinguishable from the body.

[0242] The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. A-like OS has voids or low density areas. e-OS has a lower crystallinity than nc-OS and CAAC-OS.

[0243] The oxide semiconductor has various structures and has different characteristics. The oxide semiconductors in The compound may have two or more of c-OS and CAAC-OS.

[0244] The metal oxide used for the oxide 406a and the oxide 406c is an element M (the element M is Al , Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf , Ta, W, Mg, V, Be, or Cu) The oxide 406a and the oxide 406c are, for example, an In-Ga-Zn oxide, an oxide Gallium, boron oxide, etc. can be used.

[0245] Here, in the metal oxide used for the oxide 406a and the oxide 406c, the constituent elements The atomic ratio of element M in the oxide 406b is the atomic ratio of element M in the metal oxide It is preferable that the atomic ratio of the oxide 406a and the oxide 406c is larger than that of the element M. In the metal oxide used in the present invention, the atomic ratio of element M to In is It is preferable that the atomic ratio of M is larger than the atomic ratio of In in the metal oxide.

[0246] In addition, the metal oxide used for the oxide 406a and the oxide 406c has a non-single crystal structure. The non-single crystal structure is preferably, for example, CAAC-OS, a polycrystalline structure, a microcrystalline structure, or The metal oxide used for the oxide 406a and the oxide 406c is C The oxide 406a and the oxide 406c may have an AAC structure. The metal oxide has multiple IGZO nanocrystals with c-axis orientation and no alignment in the ab plane. The crystal structure may be a layered structure in which the crystals are interconnected in parallel.

[0247] In addition, the metal oxide used for the oxide 406a and the oxide 406c is the same as that used for the oxide 406b. The oxide 406a and the oxide 406b may have higher crystallinity than the metal oxide used. The metal oxide used for the oxide 406c is, for example, an oxide formed in an atmosphere containing oxygen. This allows the oxide 406a and the oxide 406c to have high crystallinity. In addition, the shapes of the oxide 406a and the oxide 406c can be stabilized. Cut.

[0248] The above-mentioned metal oxide is used as the oxide 406c, and the conduction band minimum of the oxide 406c is It is preferable that the energy of the oxide 406b is higher than the conduction band minimum energy of the oxide 406b. In other words, the electron affinity of oxide 406c is greater than that of oxide 406b. Here, the electron affinity is defined as the energy difference between the vacuum level and the bottom of the conduction band. It refers to the difference in level.

[0249] Similarly, the above-mentioned metal oxide is used as the oxide 406a. The energy of the conduction band edge of the oxide 406b is higher than that of the oxide 406b. In other words, it is preferable that the electron affinity of the oxide 406a is smaller than that of the oxide 406b. It is preferably smaller than the electron affinity.

[0250] Here, in the oxide 406a, the oxide 406b, and the oxide 406c, The energy levels change gradually. In other words, the energy levels change continuously or are connected continuously. In order to achieve this, the boundary between the oxide 406a and the oxide 406b must be The defect level of the intermixed layer formed at the interface between oxide 406b and oxide 406c. It is advisable to lower the level density.

[0251] Specifically, the oxide 406a and the oxide 406b, and the oxide 406b and the oxide 406c are By having a common element other than oxygen (as the main component), a mixed layer with a low defect level density is formed. For example, when the oxide 406b is an In-Ga-Zn oxide, the oxide 406a, oxide 406c, In-Ga-Zn oxide, Ga-Zn oxide, oxide gas It is advisable to use lithium.

[0252] At this time, the main path of the carriers is the oxide 406b and its vicinity. At the interface between oxide 406a and oxide 406b, and at the interface between oxide 406b and oxide 406c Since the defect level density at the interface can be reduced, the effect of interface scattering on carrier conduction is small. Therefore, a high on-current can be obtained.

[0253] When an electron is captured in a trap level, the captured electron behaves like a fixed charge. Therefore, the threshold voltage of the transistor is shifted in the positive direction. By providing the oxide 406c, the trap level can be made farther away from the oxide 406b. This structure allows the threshold voltage of the transistor to be shifted in the positive direction. This can be prevented.

[0254] In this embodiment, the metal oxide used in the transistor has the above-mentioned three-layer structure. However, one embodiment of the present invention is not limited thereto. For example, the oxide 406a or the oxide 406 Alternatively, the oxide 406a may be formed on the upper or lower side of the oxide 406a. or oxide 406c, and a four-layer structure having one of the above-mentioned semiconductors on or under the oxide 406c. Alternatively, the oxide 406a may be formed on the oxide 406a, the oxide 406b may be formed on the oxide 406c, or the oxide 406c may be formed on the oxide 406a. At least two of the oxides 406a, 406b and 406c are provided on the upper surface of the oxide 406a. and an n-layer structure (n is an integer of 5 or more) having one of the semiconductors exemplified as the oxide 406c. It is also acceptable to use the number.

[0255] The transistor described in this embodiment has the oxide 406a, the oxide 406b, and It is preferable to have an oxide 406c.

[0256] The oxide 406a is preferably disposed on the top surface of the insulator 402. 06b is preferably disposed on top of oxide 406a.

[0257] The oxide 406b also has a first region, a second region, and a third region. The region is sandwiched between the first region and the second region in a top view. The transistor has a conductor 416a1 on and in contact with the first region of the oxide 406b. A conductor 416a2 is disposed on and in contact with the second region of the oxide 406b. Either the first region or the second region can function as a source region, and the other can function as a drain region. The third region of the oxide 406b can function as a channel forming region. do.

[0258] The oxide 406c is in contact with the third region of the oxide 406b and is connected to the oxide 406a and the oxide 406b. 06b, disposed on the conductors 416a1 and 416a2 and the barrier films 417a1 and 417a2. In addition, the oxide 406c is preferably placed between the oxide 406a and the oxide 406b. As shown in FIG. 20C, the oxide 406a and the oxide It is preferable that the side surface of 406b in the channel width direction is in contact with the oxide 406c. The conductor 404, which functions as the first gate electrode, functions as the first gate insulator. The third region of the oxide 406b is covered with an insulator 412 having a thickness of 100 nm. do.

[0259] The oxide 406c is disposed so as to entirely cover the oxide 406a and the oxide 406b. For example, the side surfaces of the oxide 406a and the oxide 406b in the channel length direction may be formed as oxide films. Alternatively, the insulating layer 406 may be configured to be in contact with the insulating layer 406c.

[0260] The conductor 416a1 and the conductor 416a2 are spaced apart from each other, and the upper surface of the oxide 406b is Here, the conductor 416a1 is preferably disposed in contact with the source electrode or the drain electrode. The conductor 416a1 can function as one of the source and drain electrodes, and the conductor 416a2 can function as one of the source and drain electrodes. It can function as the other of the two.

[0261] As shown in FIGS. 20A and 20B, one side end of the conductor 416a1 is made of an oxide. It is preferable that one side end of 406a and one side end of oxide 406b are approximately aligned. Similarly, one side end of the conductor 416a2 is connected to the other side end of the oxide 406a. It is preferable that the end of the oxide 406b is substantially aligned with the other end of the oxide 406b. As a result, the side surfaces of the oxide 406a and the oxide 406b are in contact with the conductor 416a1 and the conductor 41 Since the oxide 406a and the oxide 406b are not in contact with each other, oxygen is drawn to the side surfaces of the oxide 406a and the oxide 406b. In addition, the oxide 406a and the oxide Since the side surface of the oxide 406b is not in contact with the conductor 416a1 and the conductor 416a2, The insufficiency caused by the conductor 416a1 and the conductor 416a2 is observed from the side of the oxide 406b. It is possible to prevent impurities from entering.

[0262] Here, the side end of the conductor 416a1 and the side end of the conductor 416a2 facing each other The distance, i.e., the channel length of the transistor, is 10 nm to 300 nm, typically 20 The thickness should be between 1 nm and 180 nm.

[0263] In addition, the angle between the side and bottom surfaces of the conductor 416a1 and the conductor 416a2 facing each other is It is preferable that the conductor 416a1 and the conductor 416a2 have a taper angle of less than 90°. It is preferable that the angle between the side surface and the bottom surface of a2 facing each other is 45° or more and 75° or less. By forming the conductor 416a1 and the conductor 416a2 in this manner, the oxide 4 The 06c is formed with good coverage on the step portions formed by the conductors 416a1 and 416a2. As a result, the oxide 406c is broken, and the oxide 406b is This can prevent the insulator 412 and the like from contacting each other.

[0264] A barrier film 417a1 is disposed in contact with the upper surface of the conductor 416a1. It is preferable that a barrier film 417a2 is provided in contact with the upper surface of the barrier film 417a2. 1 and the barrier film 417a2 have the function of suppressing the permeation of impurities such as hydrogen and water and oxygen. The barrier film 417a1 and the barrier film 417a2 are made of, for example, aluminum oxide. As a result, the conductor 416a1 and the conductor 416a2 can be oxidized. In addition, the conductor 416a1 and the conductor 416b1 can prevent excess oxygen from being consumed. It is possible to prevent an increase in the electrical resistance of the conductor 416a2 due to oxidation. The electrical resistance can be measured using a two-terminal method. A configuration in which a1 and 417a2 are not provided is also possible.

[0265] In addition, in addition to the insulator 412 and the oxide 406c, a conductive material is provided between the conductor 404 and the conductor 416a1. Since the barrier film 417a1 is provided, the parasitic Similarly, the capacitance can be reduced by providing an insulating layer between the conductor 404 and the conductor 416a2. Since the conductive layer 412 has the barrier film 417a2 in addition to the oxide 406c, the conductive layer 40 Therefore, the parasitic capacitance between the conductor 416a2 and the conductor 416a2 can be reduced. The transistor shown in FIG.

[0266] The insulator 412 can function as a gate insulating film and is disposed on the top surface of the oxide 406c. The insulator 412 is preferably made of a material that releases oxygen when heated, similar to the insulator 402. It is preferable to form the insulator 412 using the oxide 406c. By providing it in contact with the upper surface, oxygen can be effectively supplied to the oxide 406b. In addition, similar to the insulator 402, the concentration of impurities such as water or hydrogen in the insulator 412 is reduced. It is preferable that the above is done.

[0267] The conductor 404 has a structure in which the conductor 404a, the conductor 404b, and the conductor 404c are laminated. The conductor 404a is preferably disposed on the insulator 412. A conductor 404b is disposed on top of the conductor 404c, and a conductor 404c is disposed on top of the conductor 404b. The oxide 406b overlaps the conductive material 412 and the conductive material 404. The side ends of the conductors 404a, 404b, and 404c are approximately aligned. 404 functions as the other gate electrode. The width of the body 404 in the channel length direction is 10 nm or more and 300 nm or less, preferably 20 nm or less. More than 180 nm.

[0268] In other words, one of the conductors 310 and 404 can function as a gate electrode, and the other can function as a gate electrode. The gate electrode and the back gate electrode function as a semiconductor chara. The back gate electrode is placed on either side of the gate electrode. Alternatively, the back gate electrode may be set to a ground potential or any other potential. By changing the gate electrode independently, the threshold voltage of the transistor can be changed. It can be made into a

[0269] The conductor 404a is preferably an oxide having electrical conductivity. For example, the oxide 406a In addition, a metal oxide that can be used as the oxide 406b or the oxide 406c can be used. In particular, the In-Ga-Zn oxides with high electrical conductivity and a metal atomic ratio of [In]:[Ga]:[Zn] = 4:2:3 to 4.1 and nearby values By providing such a conductor 404a, the conductor 404b and the conductor The conductor 404b and the conductor 404c are prevented from being oxidized. It is possible to prevent the electrical resistance from increasing. In addition, the oxide 406b is supplied with excess oxygen. It becomes possible to do so.

[0270] The conductor 404b is formed by doping the conductor 404a with an impurity such as nitrogen. A conductor capable of improving electrical conductivity is preferable. For example, the conductor 404b is made of titanium nitride. It is preferred.

[0271] Here, the conductor 404 having the function of a gate electrode is formed by the insulator 412 and the oxide 406c. The oxide 406b is formed on the upper surface of the oxide 406b in the vicinity of the third region and on the side surface in the channel width direction through the insulating film 404. Therefore, the electric field of the conductor 404 that functions as a gate electrode The upper surface of the oxide 406b in the vicinity of the third region and the side surface in the channel width direction are electrically surrounded by the oxide 406b. The electric field of the conductor 404 electrically surrounds the channel forming region. The structure of the transistor is called the surrounded channel (s-channel) structure. Therefore, the oxide 406b has a top surface in the vicinity of the third region and a side surface in the channel width direction. Since a large current can be passed between the source and drain, The current (on-current) during the pass-through can be increased. The upper surface and the side surface in the channel width direction in the vicinity are surrounded by the electric field of the conductor 404. This makes it possible to reduce the current (off current) when not conducting.

[0272] In addition, it is preferable that a barrier film 418 is provided on the conductor 404. The rear film 418 is preferably made of a material that is difficult for oxygen to permeate, such as aluminum oxide. This allows the excess oxygen in the surroundings to be used for oxidation of the conductor 404. In this way, the barrier film 418 serves as a gate electrode that protects the gate. The barrier film 418 functions as a cap.

[0273] [Insulator] The transistor is made of an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor, the electrical characteristics can be stabilized. For example, the insulator 4 01, and the insulator 420 has a function of suppressing the permeation of impurities such as hydrogen and oxygen. In addition, the insulator 303 may be made of an insulator that prevents impurities such as hydrogen and oxygen from passing through. The insulator 401, the insulator 303, and the insulator 420 is an insulating material that is less permeable to impurities such as water or hydrogen than the insulator 402. It is preferable to form the insulating film using the above method.

[0274] Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include: Aluminum oxide, aluminum oxynitride, magnesium oxide, gallium oxide, oxide gel Al, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, halide oxide Metal oxides such as fluorine or tantalum oxide, silicon oxide nitride, silicon nitride or Aluminum nitride or the like may be used in a single layer or in a multilayer structure.

[0275] The insulator 401 and the insulator 420 each contain aluminum oxide, so that the oxide 406a In addition, impurities such as hydrogen are prevented from being mixed into the oxide 406b and the oxide 406c. For example, the insulator 401 and the insulator 420 may include aluminum oxide. By this, the peroxide added to the oxide 406a, the oxide 406b, and the oxide 406c is The outward diffusion of excess oxygen can be reduced.

[0276] As insulator 301, insulator 302, insulator 303, insulator 402 and insulator 412 is, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon Nitride, phosphorus, argon, gallium, germanium, yttrium, zirconium, lanthanum If an insulator containing neodymium, hafnium or tantalum is used in a single layer or a multilayer, For example, the insulator 301, the insulator 302, the insulator 303, the insulator 402, and the insulator 412 preferably comprises silicon oxide or silicon oxynitride.

[0277] The insulators 302, 303, 402, and 412 form a gate insulator. Since it functions as a film, it is preferable to use an insulator with a high relative dielectric constant. For example, insulator 3 02, insulator 303, insulator 402 and insulator 412 are made of gallium oxide, hafnium oxide, oxides containing aluminum, aluminum and hafnium, oxides containing aluminum and hafnium oxides with silicon and hafnium, oxides with silicon and hafnium, or oxides with silicon and hafnium. It is preferable that the insulator 302 has an oxide nitride having nitrile or the like. 303, the insulator 402 and the insulator 412 are made of silicon oxide or silicon oxynitride, It is preferable that the insulating layer has a laminate structure of silicon oxide and an insulator having a high relative dielectric constant. Silicon nitride is thermally stable, so by combining it with an insulator with a high dielectric constant, It is possible to obtain a laminated structure that is thermally stable and has a high relative dielectric constant. For example, aluminum oxide By having gallium oxide or hafnium oxide on the oxide 406c side, silicon oxide Alternatively, silicon contained in silicon oxynitride is prevented from being mixed into the oxide 406b. Also, for example, silicon oxide or silicon oxynitride can be used as the oxide 406c. By having aluminum oxide, gallium oxide or hafnium oxide on the side, In some cases, trap centers are formed at the interface between the silicon or silicon oxynitride. The trap center captures electrons and increases the threshold voltage of the transistor in the positive direction. It may be possible to vary it.

[0278] The insulator 410 preferably has a low dielectric constant. 0 is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added Silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen It is preferable that the insulating layer has a silicon oxide or resin having holes. The body 410 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or fluorine. Silicon oxide doped with nitrogen, silicon oxide doped with carbon, and oxide doped with carbon and nitrogen. It is preferable that the insulating layer has a laminated structure of silicon oxide or silicon oxide having voids and a resin. Silicon oxide and silicon oxynitride are thermally stable, so they are suitable for use in combination with resin. By using the resin, it is possible to obtain a laminated structure that is thermally stable and has a low relative dielectric constant. For example, polyester, polyolefin, polyamide (nylon, aramid, etc.), poly Examples of suitable materials include polyimide, polycarbonate, and acrylic.

[0279] The barrier film 417a1 and the barrier film 417a2 are formed by removing impurities such as hydrogen and oxygen. Alternatively, an insulator having a function of suppressing the transmission of the barrier film 417a1 and the barrier The film 417a2 converts the oxide 406c and excess oxygen in the insulator 412 into the conductor 416. a1 and the conductor 416a2 can be prevented from diffusing therein.

[0280] The barrier film 417a1 and the barrier film 417a2 may be made of, for example, aluminum oxide. Magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Metal oxides such as lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide A material such as silicon nitride oxide or silicon nitride may be used.

[0281] [conductor] Conductor 404, Conductor 310, Conductor 416a1, Conductor 416a2, Conductor 108a The conductor 108b may be made of aluminum, chromium, copper, silver, gold, platinum, tantalum, or nickel. Kel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese 1 metal element selected from magnesium, zirconium, beryllium, indium, etc. Materials containing one or more impurities such as phosphorus can also be used. Silicon is a semiconductor with high electrical conductivity, and silicides such as nickel silicide are It may be used.

[0282] In addition, the conductive material containing the above-mentioned metal element and oxygen may be used. A conductive material containing a metal element and nitrogen may be used. For example, titanium nitride, tantalum nitride, etc. Alternatively, a conductive material containing nitrogen, such as indium tin oxide (ITO), may be used. tungsten oxide, indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing ingested indium, indium oxide containing titanium oxide, titanium oxide Indium tin oxide with silicon, indium zinc oxide, indium tin oxide with silicon Alternatively, indium gallium zinc oxide containing nitrogen may be used. .

[0283] In addition, a plurality of conductive layers made of the above materials may be laminated. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated material that combines the above-mentioned material containing a metal element and a conductive material containing nitrogen is In addition, the above-mentioned metal element-containing material, the conductive material containing oxygen, and the nitrogen A laminated structure in which the conductive material containing the element is combined with the conductive material containing the element may be used.

[0284] When an oxide is used for the channel formation region of a transistor, The laminated structure is made by combining the material containing the metal element and the conductive material containing oxygen. In this case, it is preferable to provide a conductive material containing oxygen on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, The released oxygen is easily supplied to the channel formation region.

[0285] For example, the conductor 310b may be made of a conductive material such as tungsten or polysilicon. The conductor 310a in contact with the insulator 401 may be made of, for example, titanium or nitride. A barrier layer (diffusion prevention layer) such as titanium or tantalum nitride can be used as a laminate or a single layer. This can be done.

[0286] The insulator 401 is made of an insulating material that is difficult for impurities to penetrate, and the conductive By using a conductive material that is difficult for impurities to penetrate into the body 310a, impurities in the transistor are prevented from This further suppresses the diffusion of the impurities, thereby further improving the reliability of the transistor. This can be done.

[0287] The barrier films 417a1, 417a2, and 418 are formed by removing the above-mentioned impurities. A conductive material that is difficult to penetrate may be used. When a conductive material is used for the oxygen film 418, oxygen is not easily released and / or is not easily absorbed. It is preferable to use a conductive material that is not easily damaged.

[0288] <How to fabricate a transistor> A method for manufacturing the transistor illustrated in FIG. 20 according to one embodiment of the present invention will be described below with reference to FIGS. This will be described with reference to FIG. 22. In FIG. 21 and FIG. 22, the dashed line A1- A cross-sectional view corresponding to the cross section of A2 and a cross-sectional view corresponding to the cross section of the dashed line A3-A4 shown in FIG. 20(C) 1 shows a cross-sectional view of the same.

[0289] In the following description, insulating materials for forming insulators and conductive materials for forming conductors are used. Conductive materials and oxides that function as oxide semiconductors are prepared by sputtering and spin coating. The method may be appropriately selected from the group consisting of a CVD method, an ALD method, an MBE method, and a PLD method. can.

[0290] First, the insulator 401 and the insulator 301 are formed in this order on a substrate (not shown). In terms of form, the substrate is a single crystal silicon substrate (p-type semiconductor substrate or n-type semiconductor substrate In this embodiment, the insulator 401 is formed by a sputtering method. An aluminum oxide film is formed using a CVD method as an insulator 301. A coating film is formed.

[0291] Also, for example, aluminum oxide is laminated on or under the insulator 401 by the ALD method. A silicide film may be formed.

[0292] Next, the insulator 301 includes an opening (such as a groove, trench or hole) that reaches the insulator 401. The opening may be formed by wet etching, but it is also preferable to form the opening by dry etching. In addition, the insulator 401 is formed by etching the insulator 301. Select an insulator that functions as an etching stopper film when etching is performed to form an opening. For example, it is preferable to use silicon oxide or silicon oxynitride for the insulator 301 that forms the opening. When silicon is used, the insulator 401 is made of silicon nitride, aluminum oxide, hafnium oxide, etc. At this time, the portion of the insulator 401 that overlaps with the opening of the insulator 301 is an edge. In some cases, a concave shape may be formed by the chalk.

[0293] Next, a conductive film that will become the conductor 310a and a conductive film that will become the conductor 310b are formed. In this embodiment, a nitride film formed by sputtering is used as the conductive film that becomes the conductor 310a. A laminated film of tantalum and titanium nitride formed by the ALD method is used. A tungsten film formed by CVD is used as the conductive film.

[0294] Next, a CMP process is performed to form a conductive film on the insulator 301 that will become the conductor 310a, and Then, the conductive film that will become the conductor 310b is removed (see FIGS. 21(A) and (B)). Only the conductor 310a and the conductor 310b remain, forming a conductor 310 having a flat upper surface. can be formed.

[0295] Next, the insulator 302 is formed on the insulator 301 and the conductor 310. Then, a silicon oxynitride film is formed as the insulator 302 by using a CVD method.

[0296] Next, the insulator 303 is formed on the insulator 302. In this embodiment, the insulator 303 and Then, a hafnium oxide film is formed using the ALD method.

[0297] Next, the insulator 402 is formed over the insulator 303. In this embodiment, the insulator 402 and Then, a silicon oxynitride film is formed by using a CVD method.

[0298] Next, a first heat treatment is preferably performed. The first heat treatment is performed at a temperature of 250° C. or higher and 650° C. or higher. The temperature may be set to 300° C. or higher and 500° C. or lower. When a wiring containing copper is provided under the transistor, the temperature of the first heat treatment is The first heat treatment is preferably performed at a temperature of 410° C. or less in an inert gas atmosphere. The first heat treatment may be performed under reduced pressure. In the present embodiment, the first heat treatment can remove impurities such as hydrogen and water. The heat treatment is carried out at 400°C in a nitrogen gas atmosphere.

[0299] Next, an oxide film 406A that becomes an oxide 406a is formed on the insulator 402, and the oxide film 40 An oxide film 406B that will become oxide 406b is formed on 6A (see FIG. 21(C)(D)). .

[0300] The oxide film 406A and the oxide film 406B are preferably formed by using a sputtering method. By forming the oxide film 406A and the oxide film 406B by the sputtering method, the density The sputtering gas is preferably a rare gas (typically argon). ), oxygen, or a mixture of rare gas and oxygen may be used appropriately. The gas may contain nitrogen. The film may be formed while the substrate is heated.

[0301] It is preferable that the sputtering gas is highly purified. The oxygen gas and argon gas used in the present invention have a dew point of -40°C or less, preferably -80°C or less, and Preferably, the gas is purified to a temperature of -100°C or lower, more preferably -120°C or lower. By using the above, it is possible to prevent moisture and the like from being absorbed into the oxide film 406A and the oxide film 406B. can be prevented as much as possible.

[0302] The chamber of the sputtering device is formed with oxide film 406A and oxide film 406 In order to remove as much water as possible, which is an impurity for B, a cryopump-type pump is used. A high vacuum (5×10 -7 Pa to 1×10 -4 (up to about Pa) Alternatively, a turbo molecular pump and a cold trap are combined to form an exhaust system. Be careful not to let any gases, especially those containing carbon or hydrogen, flow back into the chamber from the is preferred.

[0303] The power source for the sputtering device can be a DC power source, an AC power source, or an RF power source. That's good.

[0304] In addition, in the sputtering device, the target or magnet is rotated or moved. For example, the magnet unit may be swung up and down and / or left and right during film formation. For example, the target can be heated at a frequency of 0.1 Hz to 1 kHz to form an oxide film. A beat (or rhythm, beat, pulse, frequency, period, or cycle) below z Alternatively, the magnet unit can be rotated or oscillated at a frequency of 0.1 Hz or faster. It is sufficient to make it oscillate with a beat of 1 kHz or less.

[0305] In forming the oxide film 406A, the substrate temperature during the film formation is set to be equal to or higher than room temperature and equal to or lower than 400° C. For example, it is preferable that the temperature is equal to or higher than the vaporization temperature of water (e.g., 100°C) and that the maintenance of the device is performed. It is sufficient to appropriately select a temperature within a possible range that provides good stability and throughput.

[0306] In addition, in the formation of the oxide film 406A, the sputtering gas is a rare gas (typically, In the case of mixed gas, the total amount of the deposition gas is 100%. The proportion of oxygen gas in the body is preferably 70% or more, more preferably 80% or more, and 1 By using an oxide containing excess oxygen for the oxide film 406A, the subsequent processing Oxygen can be supplied to the oxide film 406B by the heat treatment.

[0307] In addition, the above-mentioned In-M-Zn oxide target was used as a target for forming the oxide film 406A. Here, the oxide film 406A is an In-M-Zn oxide target. The atomic ratio of In to element M is 406B of the In-M-Zn oxide target. It is preferable that the atomic ratio of In to the element M in the above formula is smaller than that in the above formula. For example, [In ]:[M]:[Zn]=1:3:4[atomic ratio] or a ratio close to that. It is preferred to use a metal oxide target.

[0308] In this embodiment, the oxide film 406A is formed in an atmosphere of about 100% oxygen gas. The substrate temperature was 200°C, and the atomic ratio of [In]:[Ga]:[Zn] was 1:3:4. The film is formed using an In-Ga-Zn oxide target.

[0309] In the formation of the oxide film 406B, the substrate temperature during the formation is set to 100° C. or higher and lower than 140° C. For example, it is preferable to use a temperature higher than the vaporization temperature of water (e.g., 100°C) and A temperature that provides good tenability and throughput may be appropriately selected within a possible range.

[0310] In addition, in the formation of the oxide film 406B, the sputtering gas is a rare gas (typically, In the case of mixed gas, the total amount of the deposition gas is 100%. The percentage of oxygen gas in the body is between 0% and 30%, preferably between 5% and 20%. do.

[0311] In addition, the above-mentioned In-M-Zn oxide target was used as a target for forming the oxide film 406B. Here, the oxide film 406B is an In-M-Zn oxide target. The atomic ratio of In to element M is the In-M-Zn oxide target of the oxide film 406A. It is preferable that the atomic ratio of In to the element M in the above formula is larger than that in the above formula. For example, [In ]:[M]:[Zn]=4:2:4.1[atomic ratio], or [In]:[M]:[Zn ]=5:1:7 [atomic ratio] or a metal oxide target with an atomic ratio close to that value It is preferable to use:

[0312] In the present embodiment, the oxide film 406B is formed using a rare gas having an oxygen gas ratio of about 10%. The substrate temperature was 130°C and the composition of the [In]:[Ga]:[Z The film was formed using an In-Ga-Zn oxide target with an atomic ratio of 4:2:4.1. conduct.

[0313] Next, a second heat treatment may be performed at a temperature of 250° C. or higher and 650° C. or lower. The second heat treatment is preferably performed at a temperature of 300° C. or higher and 500° C. or lower. or in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. The second heat treatment may be performed under reduced pressure or in an inert gas atmosphere. After heat treatment in an atmosphere, oxidizing gas is added at 10 ppm or more and 1 % or more, or 10% or more. In addition, the crystallinity of the oxide film 406B can be improved, and impurities such as hydrogen and water can be removed. In this embodiment, after processing in a nitrogen atmosphere at a temperature of 400° C. for 1 hour, Then, the resultant is subjected to a treatment in an oxygen atmosphere at a temperature of 400° C. for one hour.

[0314] Next, a conductive film that will become the conductors 416a1 and 416a2 is formed on the oxide film 406B. In this embodiment, a tantalum nitride film is used as the conductive film that becomes the conductors 416a1 and 416a2. Tantalum nitride is highly resistant to oxidation, so it can be easily formed in the subsequent process. This is preferable when the heat treatment is carried out in the presence of a solvent.

[0315] Next, barrier films 417a1 and 417a2 are formed on the conductive film that will become the conductors 416a1 and 416a2. In this embodiment, the films that become the barrier films 417a1 and 417a2 are formed. As a result, an aluminum oxide film is formed by the ALD method. This results in a dense, thin and uniform thickness with reduced defects such as cracks and pinholes. A film can be formed.

[0316] Next, using a photolithography method, the films that will become the barrier films 417a1 and 417a2 are Openings are formed that reach the conductive film that will become the conductors 416a1 and 416a2.

[0317] Next, a conductive film that will become the conductors 416a1 and 416a2 is formed by photolithography. Parts of the film that will become the barrier films 417a1 and 417a2 are selectively removed and processed into islands. In this manner, the island-shaped conductive film is formed from the conductive film that becomes the conductors 416a1 and 416a2. The barrier films 417a1 and 417a2 are formed from the films that will become the films 417a1 and 417a2. .

[0318] Next, the oxide film 406A and a part of the oxide film 406B are removed using the island-shaped conductive film as a mask. At this time, a part of the insulator 402 may be removed at the same time. In this manner, the island-shaped oxide 406a and the island-shaped oxide 406b can be formed. do.

[0319] The oxide film 406A and the oxide film 406B can be partially removed by dry etching or the like. This can be done by using a dry etching method or a wet etching method. Both etching methods may be used.

[0320] Next, the barrier films 417a1 and 417a2 are used as a mask to perform dry etching. By this etching process, a part of the island-shaped conductive film is selectively removed. The conductive film is separated into conductor 416a1 and conductor 416a2 (see FIGS. 21(E) and (F)).

[0321] Gases used for dry etching include, for example, C4F6 gas, C2F6 gas, and C4F8 Gas, CF4 gas, SF6 gas, or CHF3 gas, etc., can be used alone or in combination with two or more gases. Alternatively, oxygen gas, helium gas, argon gas or the like may be added to the above gas. In particular, when organic matter is generated by plasma, It is preferable to use a gas that can be used for the above-mentioned purposes. For example, C4F6 gas, C4F8 gas, or Helium gas, argon gas, or hydrogen gas is added to either CHF3 gas or CHF3 gas. It is preferable to use one that has been appropriately added.

[0322] In addition, when the conductor 416a1 and the conductor 416a2 are formed by dry etching, In the case where impurity elements such as residual components of the etching gas are attached to the exposed oxide 406b, For example, if a chlorine-based gas is used as an etching gas, chlorine and other substances may adhere to the surface. In addition, if a hydrocarbon gas is used as the etching gas, carbon, hydrogen, etc. may be attached. Therefore, it is necessary to reduce the impurity elements adhering to the exposed surface of the oxide 406b. The impurity elements can be reduced, for example, by diluting hydrofluoric acid with pure water. Cleaning with diluted hydrofluoric acid, cleaning with ozone, or with ultraviolet light The cleaning process may be performed by using a wire or the like. A plurality of cleaning processes may be combined.

[0323] Alternatively, a plasma treatment using an oxidizing gas may be performed. For example, nitrous oxide gas may be used. By performing the plasma treatment, the fluorine concentration in the oxide 406b is reduced. This also has the effect of removing organic matter from the sample surface.

[0324] In addition, the exposed oxide 406b may be subjected to oxygen doping treatment. A heat treatment may be performed to

[0325] Next, a third heat treatment may be performed. The third heat treatment may be performed under the same conditions as the second heat treatment. The third heat treatment can be performed under the following conditions. In this embodiment, the nitrogen atmosphere is used. After 30 minutes of treatment at 400°C in oxygen atmosphere, The treatment is carried out for 30 minutes at a temperature of 100°C.

[0326] Next, the insulator 402, the oxide 406a, the oxide 406b, the conductors 416a1 and 416a 2. An oxide film 406C that becomes an oxide 406c is formed on the barrier films 417a1 and 417a2. To film.

[0327] The oxide film 406C is formed by the sputtering method in the same manner as the oxide film 406A. It is preferable.

[0328] In forming the oxide film 406C, the substrate temperature during the film formation is set to be equal to or higher than room temperature and lower than 200° C. For example, the substrate temperature during film formation may be room temperature. It is preferable to perform film formation while cooling the substrate holder so that the temperature does not rise above the predetermined temperature.

[0329] In addition, in the formation of the oxide film 406C, the sputtering gas is a rare gas (typically, In the case of mixed gas, the total amount of the deposition gas is 100%. The proportion of oxygen gas in the body is preferably 70% or more, more preferably 80% or more, and 1 By using an oxide containing excess oxygen for the oxide film 406C, the subsequent processing The heat treatment can provide oxygen to the oxide 406b.

[0330] In addition, the above-mentioned In-M-Zn oxide target was used as the target for forming the oxide film 406C. Here, the In-M-Zn oxide target of the oxide film 406C can be used. The target may be the same as the In-M-Zn oxide target for the oxide film 406B. For example, [In]:[M]:[Zn]=4:2:4.1 [atomic ratio], or [In] :[M]:[Zn]=5:1:7[atomic ratio] or metals with atomic ratios close to that value An oxide target may be used. Also, the In-M-Zn oxide target of the oxide film 406C The ratio of the number of atoms of In to the element M is the same as that of the In-M-Zn oxide substrate in the oxide film 406B. A target having an atomic ratio of In to element M in the get may be used. For example, the atomic ratio of [In]:[M]:[Zn]=1:1:1 or a value close to that Metal oxide targets having a molecular weight ratio may also be used.

[0331] In this embodiment, the oxide film 406C is formed in an atmosphere of about 100% oxygen gas. The substrate temperature was room temperature, and the atomic ratio of [In]:[Ga]:[Zn] was 4:2:4.1. The film is formed using an In-Ga-Zn oxide target.

[0332] Next, an insulating film 412A is formed on the oxide film 406C. As 12A, a silicon oxynitride film is formed by the CVD method.

[0333] Next, a fourth heat treatment may be performed. The fourth heat treatment may be performed under the same conditions as the first heat treatment. The fourth heat treatment can be performed under the following conditions. In this embodiment, the fourth heat treatment is performed by removing nitrogen. Heat treatment is carried out in a gas atmosphere at a temperature of 400°C.

[0334] Next, a conductive film that will become the conductor 404a, a conductive film that will become the conductor 404b, and a conductive film that will become the conductor 404c are In this embodiment, a conductive film that becomes the conductor 404a is formed in this order. A metal oxide film formed by a sputtering method is used as a conductive film for the conductor 404b. The conductive film that becomes the conductor 404a is made of tungsten. The conductive film is formed by a sputtering method, so that the insulating film 412A is In particular, the conductive film that becomes the conductor 404a is made of an oxide 40 Since the insulating film 412A is provided on the third region that is to be the channel formation region of the insulating film 412B, This allows oxygen to be added to the area close to the insulator 412, which then changes the oxide 406b. It can provide oxygen effectively.

[0335] Next, a fifth heat treatment may be performed. The fifth heat treatment may be performed under the same conditions as the first heat treatment. The fifth heat treatment can be performed under the following conditions. This allows the oxygen added to the insulating film 412A by the tapping deposition to be diffused. Therefore, oxygen vacancies in the oxides 406a, 406b, and 406c can be reduced. Cut.

[0336] Next, a conductive film that will become the conductor 404a and a conductive film that will become the conductor 404b are formed by photolithography. A part of the conductive film that will become the conductor 404c is selectively removed to form the conductor 4 404a, conductor 404b, and conductor 404c, which function as a gate. (See Figures 21(G) and (H)).

[0337] Next, a film that will become a barrier film 418 in a later step is formed on the insulating film 412A and the conductor 404. The film that becomes the barrier film 418 functions as a gate cap. Aluminum oxide film formed by the ALD method is used.

[0338] Next, a film to be the barrier film 418, an insulating film 412A, and and a portion of the oxide film 406C are selectively removed to leave the barrier film 418, the insulator 412, and An oxide 406c is formed (see FIGS. 22(A) and (B)). By forming the barrier film 418, excess oxygen in the surroundings is used to oxidize the conductor 404. In the transistors shown in FIGS. The film 418, the insulator 412, and the oxide 406c are formed to overlap each other in a top view. However, the present invention is not limited to this. For example, the oxide 406c is a mixture of the oxide 406a and the oxide An oxide 406c may be formed in contact with the side surface of the insulating material 406b and the top surface of the insulating material 402. stomach.

[0339] Next, the insulator 410 is formed on the barrier film 418. This can be done using the sputtering method, CVD method, MBE method, PLD method, or ALD method. Alternatively, the spin coating method, the dip method, the droplet ejection method (inkjet method, etc.), Printing method (screen printing, offset printing, etc.), doctor knife method, roll coater method Alternatively, it can be carried out by using a curtain coater method or the like.

[0340] The insulator 410 is preferably formed by a CVD method. More preferably, the insulator 410 is formed by a plasma CVD method. The film is formed using a method.

[0341] The insulator 410 may be formed so that the upper surface is flat. For example, the insulator 410 The insulator 410 may have a flat upper surface immediately after deposition. After the coating, the insulator is removed from the top surface so that it is parallel to the reference surface, such as the back surface of the substrate. Such a process is called a flattening process. However, if the upper surface of the insulator 410 has flatness, the insulating layer 410 may be subjected to the MP treatment, dry etching, or the like. It's okay if you don't.

[0342] Next, the insulator 420 is formed on the insulator 410 by sputtering.

[0343] The insulator 420 is preferably formed by sputtering in an atmosphere containing oxygen. In this embodiment, the insulator 420 is formed by a sputtering method in an atmosphere containing oxygen. As a result, an aluminum oxide film is formed on the insulator 410 in contact with the insulator 420. Oxygen can be added, for example, as oxygen radicals. However, the state in which oxygen is added is not limited to this. Oxygen may be an oxygen atom or an oxygen imide. The oxygen may be diffused by a heat treatment or the like in a later process. Oxygen can be effectively supplied to the oxide 406b.

[0344] Note that the substrate is preferably heated when the insulator 420 is formed. The substrate temperature is preferably higher than 100° C. and lower than 300° C. By reducing the temperature, the water in the oxide 406b can be removed. This prevents water from adsorbing on the surface. By forming the insulator 420 while diffusing oxygen into the oxide 406b, It is possible.

[0345] Alternatively, the insulator 420 may be a laminated film, for example, aluminium oxide formed by further ALD. A film of minium may be formed.

[0346] Next, a sixth heat treatment may be performed. The sixth heat treatment may be performed under the same conditions as the second heat treatment. The sixth heat treatment can be performed under the following conditions. The added oxygen can be diffused. This causes oxide 406a and oxide 406 The oxygen vacancies in the insulator 420 and the oxide 406c can be reduced. The insulator 401 prevents oxygen from diffusing above and below the transistor. This allows oxygen to be effectively supplied to the oxide 406b. This can, for example, remove impurities such as hydrogen and water contained in the insulator 410. In this embodiment, the treatment is performed for 1 hour at a temperature of 400° C. in a nitrogen atmosphere, and then the Then, the mixture is treated in an oxygen atmosphere at 400° C. for 1 hour.

[0347] Next, the insulator 422 is formed on the insulator 420 (see FIGS. 22(C) and 22(D)). Body 422 may be provided with an insulator similar to insulator 410 .

[0348] Next, the insulator 422, the insulator 420, the insulator 410, the barrier film 417a1, and the barrier Openings reaching the conductor 416a1 and the conductor 416a2 are formed in the film 417a2. The opening is preferably formed by dry etching.

[0349] Next, a conductive film that will become the conductor 108a and the conductor 108b is formed so as to fill the opening. In this embodiment, a conductive film that becomes the conductor 108a and the conductor 108b is formed. The laminated film of titanium nitride formed by the ALD method and tungsten formed by the CVD method was used. do.

[0350] Next, the conductor 108a and the conductor 108b on the insulator 422 are removed by performing a CMP process. The conductive film that will become 8b is removed (see FIG. 22(E)(F)). As a result, the conductive film is left only in the opening. The conductive body 108a and the conductive body 108b remain, so that the conductive body 108a and the conductive body 108b have flat upper surfaces. The conductor 108b can be formed.

[0351] In this manner, the transistor 400a shown in FIG. 20 can be manufactured (FIG. 22(E )(F). ).

[0352] 2 and onward, the capacitor element 100 is formed as shown in FIG. A semiconductor device can be manufactured.

[0353] <Modifications of Transistor> The transistor described in this embodiment is not limited to that shown in FIG. Modifications of the transistor described in this embodiment will be described with reference to FIGS. 23 to 25. 23 to 25, like FIG. 20, (A) shows a transistor according to one embodiment of the present invention. FIG. 1B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. (C) is a cross-sectional view of the area indicated by the dashed line A3-A4 in (A). In the top view of A), some elements are omitted for clarity. In the above, the components denoted by the same reference numerals as those of the transistor 400a are the same as those of the transistor 400a. The corresponding description in 0a may be taken into consideration.

[0354] The transistor 400b shown in FIGS. 23A, 23B, and 23C includes an insulator 402, a barrier film 4 17a1, a barrier film 417a2, and a conductor 404, an insulator 408a and an insulating film 417b are formed on the conductor 404, etc. It differs from transistor 400a in that the body 408b is disposed therein.

[0355] The insulator 408a is made up of an oxide 406a, an oxide 406b, an oxide 406c, and a conductor 416. a1, 416a2, barrier films 417a1, 417a2, insulator 412, conductor 404, and The insulator 408a is provided to cover the insulating film 408 and the barrier film 418. For example, a part of the insulator 408a is preferably in contact with the upper surface of the insulator 402. It is preferable that the insulating layer 402 contacts the upper surface of the insulator 402 outside the region overlapping with the oxide 406a of the second insulating layer 402. Further, an insulator 408b is provided on the insulator 408a. a and the insulator 408b, like the insulator 420, are formed by removing impurities such as water or hydrogen from the upper layer. It can function as a barrier insulating film to prevent substances from contaminating transistors, etc.

[0356] Here, the insulator 408a is an oxide insulator formed by a sputtering method. It is preferable to use aluminum oxide as the insulator. By using 408a, the insulator 402 is connected to the insulator 408a via the surface of the insulator 402 that contacts the insulator 408a. By supplying oxygen to the insulator 402, the insulator 402 can be made in an oxygen-excess state. Thus, oxygen can be effectively supplied to oxide 406a, oxide 406b, and oxide 406c.

[0357] Furthermore, the insulator 408a is made of an insulating material that is difficult for oxygen to permeate, such as aluminum oxide. By using the above, oxygen added to the insulator 402 is prevented from diffusing upward during film formation. This allows oxygen to be added to the insulator 402 more efficiently. do.

[0358] Furthermore, it is preferable that the insulator 408b is an oxide insulator formed by an ALD method. It is preferable to use, for example, aluminum oxide. The insulator 408b has good coating properties and suppresses the formation of cracks, pinholes, etc. The insulator 408a and the insulator 408b are provided on the uneven surface. By using the insulator 408b formed by the ALD method, there are no breaks, cracks, or pinholes. The transistor can be covered with the insulator 408b without forming a hole or the like. Therefore, even if a step or the like occurs in the insulator 408a, it can be covered with the insulator 408b. Therefore, the laminated film of the insulator 408a and the insulator 408b is resistant to impurities such as hydrogen and water. This can improve the adhesiveness more significantly.

[0359] In this manner, the transistor is formed by the insulators 408a and 408b and the insulators 401 and , the structure sandwiched between the insulator 402 and the oxide 403 prevents oxygen from diffusing outward. A large amount of oxygen can be contained in oxide 406a, oxide 406b, and oxide 406c. Furthermore, hydrogen, water, or the like enters from above the insulator 408b and from below the insulator 401. The insulator 402, the oxide 406a, the oxide 406b, and the oxide 406c are prevented from being mixed with impurities. The impurity concentration in the oxide 406c can be reduced.

[0360] Next, a transistor 400c shown in FIGS. The transistor 400c includes an insulator 401 and an insulator 30 disposed on a substrate (not shown). 1, and is disposed so as to be embedded in an opening formed in the insulator 401 and the insulator 301. A conductor 310 is connected to an insulator 301, an insulator 302 is arranged on the conductor 310, and an insulating An insulator 303 is disposed on the body 302, and an insulator 402 is disposed on the insulator 303. and an oxide 406a disposed on the insulator 402, and at least a portion of the upper surface of the oxide 406a. The oxide 406b is disposed in contact with the other part of the oxide 406a. The oxide 406b is disposed on the other part of the oxide 406a. 406c, an insulator 412 disposed on the oxide 406c, and a A conductor 404 is disposed on the insulating member 419a. An insulator 412 is disposed on the insulating member 419a. The conductor 404, the insulator 419b arranged in contact with the side of the insulator 419a, and the oxide an insulator 409 disposed in contact with the upper surface of the object 406c and in contact with the side surface of the insulator 419b; Here, as shown in FIG. 24B, the upper surface of the insulator 419b is It is preferable that the upper surface of the insulator 409 is approximately the same as the upper surface of the conductive member 9a. The body 404, the insulator 419b, the oxide 406a, the oxide 406b, and the oxide 406c are It is preferable that the cover is provided.

[0361] Transistor 400c is a balun in that it does not have conductor 416a1 and conductor 416a2. The insulator 409 is not provided in the rear film 418 but is provided in the insulators 419a and 419b. and oxides 406a, 406b, 406c have regions 426a, 426b, 426c. The transistor 400 differs from the transistor 400a in that a transistor 6c is formed.

[0362] As shown in FIG. 24B, the region 426a is sandwiched between the region 426b and the region 426c. The regions 426b and 426c are regions whose resistance is reduced by forming the insulator 409. Regions 426b and 426c are regions that are more conductive than region 426a. An impurity element such as hydrogen or nitrogen is added to the deposition atmosphere of the insulator 409 . As a result, the doped impurity element is concentrated in the region of the oxide 406 that contacts the insulator 409. The impurity element then enters the oxygen vacancy, causing the carrier The density of the material increases and the resistance decreases.

[0363] Therefore, the regions 426b and 426c contain less hydrogen and nitrogen than the region 426a. It is preferable that at least one of the concentrations is large. The concentration of hydrogen or nitrogen is measured by SIMS or the like. etc. can be used for measurement.

[0364] The regions 426b and 426c are formed by removing oxygen vacancies or oxygen vacancies. The resistance is reduced by adding elements that are captured by the magnetrons. These include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Representative examples of rare gas elements are helium, neon, argon, krypton, and xenon. Thus, regions 426b and 426c may each contain one or more of the above elements. Alternatively, a configuration including a plurality of such elements may be used.

[0365] As shown in FIG. 24B, the region 426b and the region 426c are formed by removing the oxides 406a and 406b. The oxide is formed at least in the region of 406b and 406c that overlaps with the insulator 409. Region 426b of 406b can function as one of a source region and a drain region, and the oxide Region 426c of 406b can function as the other of the source and drain regions. Additionally, region 426a of oxide 406b can function as a channel formation region.

[0366] In the transistor 400c, as shown in FIG. 6c is a region of the oxide 406 in contact with the insulator 409, an insulator 419b, and an insulator 419c. It is preferable that the region 426b and the region 426c overlap with the vicinity of both ends of the substrate 12. The portion of the region 426c that overlaps with the conductor 404 is a so-called overlap region (Lov region). The structure with the Lov region functions as a chalcogenide (chalcogen activator) for the oxide 406. No high resistance region is formed between the channel formation region and the source and drain regions. , the on-state current and mobility of the transistor can be increased.

[0367] In addition, the position of the side surface of the insulator 412 when viewed from above perpendicularly to the substrate is the same as that of the insulator 412. It is preferable that the position of the insulator 419a is approximately the same as the position of the side of the conductor 404. It is preferable to form the insulator 419a by using the ALD method. The thickness of the film can be about 5 nm to 10 nm. Here, the insulator 419a suppresses the permeation of impurities such as water or hydrogen, and oxygen. It is preferable to use a functional insulating material, for example, aluminum oxide or oxide. It is preferable to use hafnium or the like.

[0368] The insulator 419b is in contact with the sides of the insulator 412, the conductor 404, and the insulator 419a. The upper surface of the insulator 419b is substantially aligned with the upper surface of the insulator 419a. It is preferable that the insulator 419b is formed by an ALD method. The thickness of the insulator 419b is set to about 1 nm or more and 20 nm or less, preferably 1 nm or more and 3 nm or less. The thickness of the film can be as low as 1 nm, for example.

[0369] Here, like the insulator 419a, the insulator 419b is free of impurities such as water or hydrogen, and It is preferable to use an insulating material having a function of suppressing the permeation of oxygen. It is preferable to use aluminum oxide or hafnium oxide. This can prevent oxygen in the insulator 412 from diffusing to the outside. This can prevent impurities such as hydrogen and water from penetrating into the oxide 406 through the insulating layer.

[0370] In this manner, by providing the insulators 419b and 419a, water or hydrogen The upper surface of the conductor 404 is an insulator having a function of suppressing the permeation of impurities such as oxygen. The side surfaces of the conductor 404 and the insulator 412 can be covered. The insulator 412 prevents impurities such as water or hydrogen from entering the oxide 406. In this manner, the insulator 419b protects the side surfaces of the gate electrode and the gate insulating film. The insulator 419a acts as a side barrier to protect the upper surface of the gate electrode. It functions as a.

[0371] The insulator 419b is formed by forming an insulating film using the ALD method and then performing anisotropic etching. In addition, the insulating film is connected to the side surfaces of the insulator 412, the conductor 404, and the insulator 419a. It is preferable to leave the portion to be in contact with the insulating film. In addition, at this time, the insulating body 419b can be easily formed on the conductor 404. By providing the insulator 419a, a part of the insulator 419a is removed by the anisotropic etching. Even if the insulator 419b is removed, the portion of the insulator 419b that is in contact with the insulator 412 and the conductor 404 remains sufficiently It is possible.

[0372] The insulator 409 includes an insulator 419a, an insulator 419b, an oxide 406a, and an oxide 406b. , oxide 406c, and insulator 402. Here, insulator 409 is In contact with the upper surfaces of the insulators 419a and 419b and in contact with the side surfaces of the insulators 419b The insulator 409 also serves to prevent impurities such as water or hydrogen, and oxygen from passing through. For example, the insulator 409 may be made of Silicon nitride, silicon oxynitride, silicon oxynitride, aluminum nitride, aluminum oxynitride It is preferable to use an insulator such as aluminum. Oxygen penetrates through the body 409 and fills the oxygen vacancies in the regions 426b and 426c. By supplying the electrons, it is possible to prevent the carrier density from decreasing. Impurities such as water or hydrogen penetrate into the region 426b and the region 426c, causing excessive This can prevent expansion towards 26a.

[0373] As shown in FIGS. 24A, 24B, and 24C, in the transistor 400c, , oxide 406a, oxide 406b, and oxide 406 Although the sides of the c are substantially the same, this embodiment is not limited to this. The oxide 406c may cover the side surfaces of the oxide 406a and the oxide 406b. At this time, the side surfaces of the oxide 406a and the oxide 406b in the channel width direction are in contact with the oxide 406c. In addition, the oxide 406a and the oxide 406b are preferably in contact with each other in the channel length direction. The side surface may be in contact with oxide 406c.

[0374] Next, a transistor 400d shown in FIGS. The transistor 400d can be fabricated in parallel with the transistor 400a described above. Transistor 400d is fabricated in parallel with transistor 400a. In this case, the transistor 400d can be manufactured without adding any additional steps.

[0375] The transistor 400d includes oxide layers 406 spaced apart from each other on an insulator 402. a1 and oxide 406a2, and oxide 406a1 arranged in contact with the upper surface of oxide 406a1. 6b1 and an oxide 406b2 disposed in contact with the upper surface of the oxide 406a2. The oxide 406c is formed on the top surface of the insulator 402, the side surfaces of the oxide 406a1 and the oxide 406a2. , and are disposed in contact with the side and top surfaces of the oxide 406b1 and the oxide 406b2. In this respect, it differs from transistor 400a.

[0376] The oxide 406a1 and the oxide 406a2, and the oxide 406b1 and the oxide 4 06b2 are the oxides 406a and 406b of the transistor 400a, respectively. The oxide 406a1 and the oxide 406b1 can be formed using the same materials. The oxide 406a2 and the oxide 406b2 form the conductor 310, the oxide 406c, and the insulating The conductive body 412 and the conductive body 404 are formed opposite each other with the conductive body 412 and the conductive body 404 interposed therebetween.

[0377] The conductor 416a1 is formed so as to overlap the oxide 406a1 and the oxide 406b1. The conductor 416a2 can be formed by the oxide 406a2 and the oxide 406b2. The oxide 406a1 and the oxide 406b1 can be formed to overlap each other. The oxide 406a2 and the oxide 406b2 form the source region or The drain region can function as either

[0378] The oxide 406c of the transistor 400d is the same as the oxide 406c of the transistor 400a. The oxide 406a1 and the oxide 406b can be formed using the same material. The region between the oxide 406a2, the oxide 406b1, and the oxide 406b2 is a chalcedony. It functions as a channel formation region.

[0379] The oxide 406c, which functions as the active layer of the transistor 400d, is As with oxide 406c of a, oxygen vacancies are reduced and impurities such as hydrogen and water are reduced. This causes the threshold voltage of transistor 400d to be greater than 0V, The off-current can be reduced, and Icut can be made very small. Here, Icut is The drain current when the voltage of the gate that controls the switching operation of the transistor is 0V In addition, the distance between the conductor 416a1 and the conductor 416a2 of the transistor 400d is is set to be greater than the distance between the conductor 416a1 and the conductor 416a2 of the transistor 400a. This makes the threshold voltage of the transistor 400d higher than that of the transistor 400a. , the off-current can be reduced and Icut can be made smaller.

[0380] The transistor 400d controls the back gate voltage of the transistor 400a, etc. For example, the top gate and the back gate of the transistor 400d can be connected to the source. The diode is connected between the source of transistor 400d and the back gate of transistor 400a. This configuration maintains the negative potential of the back gate of the transistor 400a. When the transistor 400d is held at 1 V, the voltage between the top gate and source of the transistor 400d and the back gate The voltage between the source and the drain becomes 0V. The Icut of the transistor 400d is very small. With this configuration, the transistors 400a and 400d are supplied with The negative potential of the back gate of the transistor 400a can be maintained for a long time without the need for a power supply. can be done.

[0381] As described above, according to one embodiment of the present invention, a capacitor element that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device having high productivity can be provided. According to one embodiment of the present invention, a capacitor or a semiconductor device can be provided. According to one embodiment of the present invention, a capacitor element having a large capacitance can be provided. According to one embodiment of the present invention, a semiconductor device having excellent electrical characteristics can be provided. As a result, a semiconductor device with excellent reliability can be provided.

[0382] The configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0383] (Embodiment 2) In this embodiment, a semiconductor device that functions as a memory device is described as one mode of the semiconductor device. This will be described with reference to FIGS.

[0384] [Storage device] The semiconductor device shown in FIG. 27 includes a transistor 300, a transistor 200, and a transistor Here, the transistor 200 and the capacitance element 360 are As the transistor 360, the transistor 400 (transistor 400a, The transistor 400b and the transistor 400c are also included, and the capacitance element 100 is used. In addition, the transistor 400d or the like can be used as the transistor 345. It is possible.

[0385] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. The transistor described in the above embodiment can be used. The transistor shown in the embodiment can be formed with a high yield even when miniaturized, so the transistor 20 By using such a transistor in a memory device, The transistor described in the above embodiment can be miniaturized or highly integrated. Since the off-state current is small, the use of this in a memory device allows the memory contents to be stored for a long period of time. This means that no refresh operation is required or that the data can be retained without any need for a refresh operation. Since the frequency of refresh operations is extremely low, the power consumption of the storage device can be significantly reduced. Cut.

[0386] The capacitive element 360 has an upper electrode and a lower electrode that are induced not only on the bottom surface of the opening but also on the side surfaces. This structure allows the capacitance per unit area to be increased. The higher the height of the capacitance element 360, the larger the capacitance of the capacitance element 360. In this way, the capacitance per unit area of ​​the capacitance element 360 can be increased. By doing so, when this is used in a memory device, the area occupied by the capacitive element can be reduced and the memory device can be used for a long time. It is possible to retain the stored contents for a long time, so no refresh operation is required. Or, in a storage device where the frequency of refresh operations is extremely low, This allows the miniaturization or high integration of memory devices. It can be measured.

[0387] In FIG. 27, a wiring 3001 is electrically connected to the source of a transistor 300. The line 3002 is electrically connected to the drain of the transistor 300. 03 is electrically connected to one of the source and drain of the transistor 200, and the wiring 30 3004 is electrically connected to the gate of the transistor 200, and the wiring 3006 is 00 and the gate of the transistor 300. The other of the source and drain of the transistor 200 is connected to one of the electrodes of the capacitor 360. The wiring 3005 is electrically connected to the other electrode of the capacitor 360. The wiring 3007 is electrically connected to the source of the transistor 345, and the wiring 3008 is electrically connected to the source of the transistor 345. is electrically connected to the gate of the transistor 345, and the wiring 3009 is The wiring 3010 is electrically connected to the drain and back gate of the transistor 345. Here, the wiring 3006, the wiring 3007, the wiring 3008, and the wiring 3009 is electrically connected.

[0388] In this way, by connecting the transistor 200 and the transistor 345, As shown in the embodiment, transistor 345 supplies the back gate voltage of transistor 200 In addition, the transistor 200 and the transistor 345 can be controlled by the power supply. The negative potential of the back gate of the transistor 200 can be maintained for a long time without the need for a power supply. do.

[0389] The semiconductor device shown in FIG. 27 has a characteristic that the potential of the gate of the transistor 300 can be held. By having this, it is possible to write, hold, and read information, as shown below.

[0390] In addition, the memory device shown in FIG. 27 has a memory cell array arranged in a matrix. In addition, one transistor 345 can be configured by multiple transistors 200. Therefore, the back gate voltage of the transistor 345 can be controlled. The number can be less than that of Jista 200.

[0391] The writing and holding of information will be described. First, the potential of the wiring 3004 is changed to that of the transistor. This brings the transistor 200 into a conducting state. Thus, the potential of the wiring 3003 is applied to the gate of the transistor 300 and the potential of the capacitor 360. The gate of the transistor 300 is connected to a node FG that is electrically connected to one of the electrodes. A certain charge is applied to the gate (write). Here, two different potential levels are applied. Either the low level charge or the high level charge is given. After that, the potential of the wiring 3004 is changed so that the transistor 200 is turned off. By setting the potential at node FG such that transistor 200 is turned off, a charge is stored in node FG. To be held (retained).

[0392] When the off-state current of the transistor 200 is small, the charge of the node FG is retained for a long period of time. It will be held.

[0393] Next, the reading of information will be described. A predetermined potential (constant potential) was applied to the wiring 3001. In this state, when an appropriate potential (read potential) is applied to the wiring 3005, the wiring 3002 becomes The potential depends on the amount of charge held in the gate FG. In the case of a transistor of the type, when a high level charge is applied to the gate of the transistor 300, The apparent threshold voltage V th_H A low level voltage is applied to the gate of the transistor 300. The apparent threshold voltage V under load th_L Because it will be lower. Here, the apparent threshold voltage is the voltage required to make the transistor 300 "conductive." This refers to the required potential of the wiring 3005. Therefore, the potential of the wiring 3005 is V th _H and V th_L By setting the potential between these two points as V0, the charge applied to node FG can be determined. For example, in a write operation, a high-level charge is applied to node FG. In this case, the potential of the wiring 3005 is V0 (>V th_H ), then transistor 300 is On the other hand, if a low-level charge is applied to node FG, The potential of the wiring 3005 is V0( <V th_L ), transistor 300 is "non-conducting" Therefore, by determining the potential of the wiring 3002, the node FG is kept in the "state". The information stored in the memory can be read.

[0394] <Memory device structure> The semiconductor device of one embodiment of the present invention includes a transistor 300 as shown in FIG. The transistor 200 and the capacitor 360 are The transistor 345 is provided above the transistor 300, and the capacitance element 360 is provided above the transistor 300. The resistor 300 is disposed above the transistor 200 and the transistor 345 .

[0395] The transistor 300 is disposed on a substrate 311, and includes a conductor 316, an insulator 315, and a substrate 316. A semiconductor region 313 consisting of a part of 311 and functioning as a source region or a drain region. The semiconductor device has a low resistance region 314a that is capable of performing a low resistance change and a low resistance region 314b that is capable of performing a low resistance change.

[0396] Transistor 300 can be either p-channel or n-channel.

[0397] A region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a source region, or In the low resistance region 314a which becomes the drain region, and the low resistance region 314b, etc., It is preferable that the semiconductor material contains a silicon-based semiconductor, and it is preferable that the semiconductor material contains single crystal silicon. Or Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide) It may be made of materials such as gallium aluminum arsenide (GaAlAs) or Silicon with effective mass controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, GaAs and GaAlAs may be used to form a transistor. The Sta 300 is a HEMT (High Electron Mobility Transistor) stor) may also be used.

[0398] The low resistance region 314a and the low resistance region 314b are formed by applying a semiconductor In addition to the conductive material, elements that impart n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. The material contains an element that imparts electrical conductivity to the mold.

[0399] The conductor 316 that functions as the gate electrode is made of arsenic, phosphorus, or the like that imparts n-type conductivity. An element, or a semiconductor material such as silicon that contains an element that gives it p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used. .

[0400] In addition, the threshold voltage can be adjusted by determining the work function depending on the conductor material. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, tungsten or aluminum is used as the conductor. It is preferable to use metal materials such as tungsten as the lamination layer. This is preferable from the viewpoint of thermal stability.

[0401] Note that the transistor 300 shown in FIG. 27 is just an example, and the present invention is not limited to this structure. Appropriate transistors may be used depending on the configuration and driving method.

[0402] Covering the transistor 300 are an insulator 320, an insulator 322, an insulator 324, and an insulator 326. The edge members 326 are stacked in order.

[0403] The insulators 320, 322, 324, and 326 may be, for example, an acid. silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used.

[0404] The insulator 322 serves to eliminate a step caused by the transistor 300 and the like provided below. For example, the upper surface of the insulator 322 may have a function as a planarizing film. In order to improve flatness, the surface is flattened by a planarization process using a chemical mechanical polishing (CMP) method or the like. It may be possible.

[0405] The insulator 324 is also provided with a substrate 311 or a transistor 300, etc. A film having a barrier property to prevent diffusion of hydrogen and impurities is formed in the area where the sta 200 is provided. It is preferable to use

[0406] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, a semiconductor having an oxide semiconductor such as the transistor 200 can be used. When hydrogen diffuses into a semiconductor element, the characteristics of the semiconductor element may deteriorate. Between the transistor 300 and the transistor 200 and the transistor 345, It is preferable to use a film that suppresses hydrogen diffusion. Specifically, the film that suppresses hydrogen diffusion is The film has a small amount of hydrogen desorption.

[0407] The amount of desorption of hydrogen can be analyzed, for example, by using thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorption from the insulator 324 was measured by TDS analysis at 50° C. to 50° C. In the range of 0°C, the amount of desorption converted into hydrogen atoms is converted into the area of ​​the insulator 324. So, 10 x 10 15 atoms / cm 2 Less than or equal to 5×10 15 atoms / cm 2 The following is acceptable.

[0408] It is preferable that the insulator 326 has a lower relative dielectric constant than the insulator 324. For example, The relative dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the body 326 is preferably 0.7 times or less than the relative dielectric constant of the insulator 324, and more preferably 0.6 times or less. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance between the wirings can be reduced. can be reduced.

[0409] In addition, the insulators 320, 322, 324, and 326 are made of transistors. A conductor 328 and a conductor 330 are embedded in the insulating layer 200. The conductor 328 and the conductor 330 function as plugs or wiring. In addition, the conductor having the function of a plug or wiring is a single structure that is integrated with multiple structures. In addition, in this specification and the like, a wiring and a In other words, when a part of the conductor functions as a wiring, In some cases, part of the conductor may function as the plug.

[0410] The materials of the plugs and wiring (the conductors 328 and 330, etc.) are metal. Conductive materials such as metals, alloys, metal nitrides, or metal oxides are applied in a single layer or in a Materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, can be used. It is preferable to use any high melting point material, and it is preferable to use tungsten. It is preferable to form the conductive member from a low resistance material such as aluminum or copper. By using this material, the wiring resistance can be reduced.

[0411] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. In the insulating layer 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring. , conductor 328, and conductor 330 may be formed using materials similar to those of the conductor 320.

[0412] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen as the conductor 356. In particular, the insulator 350 having a barrier property against hydrogen is useful. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300, the transistor 200, and the transistor 345 are provided with a barrier layer. 300 from transistor 200 and transistor The diffusion of hydrogen into the 345 can be suppressed.

[0413] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the overall conductivity. In this case, the tantalum nitride layer having a barrier property against hydrogen is It is preferable that the insulating body 350 has a structure in which the insulating body 350 is in contact with the insulating body 350.

[0414] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. In this case, on the insulator 354, the insulator 210, the insulator 212, the insulator 214, and the insulator The insulators 210, 212, 214, and 216 are stacked in this order. Either the insulating material 216 or the insulating material 218 is made of a material having a barrier property against oxygen or hydrogen. is preferred.

[0415] For example, the insulator 210 and the insulator 214 may include, for example, a substrate 311 or a transistor. The transistor 200 or the transistor 345 is provided from the region where the transistor 300 is provided. It is preferable to use a film having a barrier property that prevents diffusion of hydrogen and impurities in the region where the semiconductor device is to be disposed. Therefore, the same material as the insulator 324 can be used.

[0416] As an example of a film that has a barrier property against hydrogen, silicon nitride formed by CVD method is used. Here, a semiconductor element having an oxide semiconductor, such as the transistor 200, However, the diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. The diffusion of hydrogen is suppressed between the transistor 300 and the transistors 200 and 345. It is preferable to use a film that suppresses the diffusion of hydrogen. The film should have a small amount of separation.

[0417] In addition, as a film having a barrier property against hydrogen, for example, the insulator 210 and the insulator 214 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable that

[0418] In particular, aluminum oxide is highly resistant to oxygen and water, which can cause fluctuations in the electrical characteristics of transistors. It has a high blocking effect that does not allow impurities such as oxygen and moisture to pass through the membrane. Aluminum oxide is highly resistant to hydrogen, moisture, etc. during and after the transistor manufacturing process. This can prevent impurities from entering the transistor 200 and the transistor 345. In addition, the oxygen from the oxide constituting the transistor 200 and the transistor 345 is Therefore, the transistor 200 and the transistor 345 can suppress the emission. It is suitable for use as a protective film against

[0419] For example, the insulators 212 and 216 may be made of the same material as the insulator 320. In addition, by using a material with a relatively low dielectric constant as the interlayer film, For example, the insulator 212 and the insulator 216 can reduce the parasitic capacitance. As the insulating film, a silicon oxide film, a silicon oxynitride film, or the like can be used.

[0420] Also, the insulating material 210, the insulating material 212, the insulating material 214, and the insulating material 216 are formed The opening contains a conductor 218 and the conductors and transistors that make up the transistor 200. The conductor 218 is embedded in the transistor 345. 00 and the capacitor element 360 or the transistor 200; The transistor 200 and the transistor 345 function as wiring. The conductor 218 functions as a wiring connected to the lock gate. The conductor 330 may be formed using a material similar to that of the conductor 330.

[0421] In particular, the layer of conductor 218 in contact with insulator 214 acts as a barrier against oxygen, hydrogen, and water. In this configuration, the transistor 300 and Transistor 200 and transistor 345 act as barriers to oxygen, hydrogen, and water. The transistor 300 can be completely isolated from the transistor 301 by a layer having a reflective property. This can suppress the diffusion of hydrogen into the gate 200 and the transistor 345.

[0422] Above the insulator 216, the transistor 200 and the transistor 345 are provided. The transistor 200 and the transistor 345 are the same as those in the previous embodiment. A transistor included in the semiconductor device described above may be used. For example, the transistor 200 Examples of the transistors include transistor 400a, transistor 400b, and transistor 400c. The transistor 345 may be a transistor 400d or the like. In FIG. 27, a transistor 400a is used as the transistor 200. In the example shown in FIG. 27, a transistor 400d is used as the transistor 345. The transistor 200 and the transistor 345 are merely examples, and the structure is not limited thereto. Appropriate transistors may be used depending on the circuit configuration and driving method.

[0423] In addition, an insulator 230 and an insulator 232 are provided on the insulator 216 and the conductor 218. At least one of the insulator 230 and the insulator 232 is It is preferable to use a material that has a barrier property against oxygen and hydrogen.

[0424] For example, the insulator 230 and the insulator 232 may include, for example, a substrate 311 or a transformer. The transistor 200 or the transistor 345 is provided from the region where the transistor 300 is provided. It is preferable to use a film having a barrier property that prevents diffusion of hydrogen and impurities in the region where the semiconductor device is to be disposed. Therefore, the same material as the insulator 324 can be used.

[0425] As an example of a film that has a barrier property against hydrogen, silicon nitride formed by CVD method is used. Here, a semiconductor element having an oxide semiconductor, such as the transistor 200, However, the diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. The diffusion of hydrogen is suppressed between the transistor 300 and the transistors 200 and 345. It is preferable to use a film that suppresses the diffusion of hydrogen. The film should have a small amount of separation.

[0426] The openings formed in the insulator 230 and the insulator 232 are filled with the conductor 219. The conductor 219 is a back gate electrode of the transistor 200 and a The conductor 219 functions as a back gate electrode of the transistor 345. The transistor 300 is electrically connected to the capacitor 360 or the transistor 200. The conductor 219 functions as a plug or wiring. It may be provided using materials similar to those of the body 330 .

[0427] The backgate electrode of transistor 200 and the backgate electrode of transistor 345 The top gate electrode of transistor 200 and the top gate electrode of transistor 345 By providing an insulator 230 and an insulator 232 between the electrodes, the transistor 200 is The parasitic capacitance between the back gate electrode and the top gate electrode of the transistor 200, The parasitic capacitance between the back gate electrode of transistor 345 and the top gate electrode of transistor 345 The amount can be reduced.

[0428] An insulator 280 is provided above the transistor 200 and the transistor 345. It is preferable that an excess oxygen region is formed in the insulator 280. When an oxide semiconductor is used for the transistor 200 and the transistor 345, By providing an insulator having an excess oxygen region in an interlayer film or the like near the transistor 345, To reduce oxygen vacancies in the oxides of the transistors 200 and 345 In addition, the transistor 200 and the transistor 301 can improve reliability. The insulator 280 covering 45 may function as a planarizing film that covers the uneven shape underneath. stomach.

[0429] As an insulator having an excess oxygen region, specifically, an oxide insulator in which a part of oxygen is released by heating is used. It is preferable to use oxides that release oxygen when heated. The amount of oxygen released, calculated as oxygen atoms, is 1.0×10 18 atoms / cm 3 Above, I prefer 3.0×10 20 atoms / cm 3 The oxide film is as above. The surface temperature of the membrane during the analysis was 100°C to 700°C, or 100°C to 500°C. A range of 00°C or less is preferred.

[0430] For example, such a material may include silicon oxide or silicon oxynitride. It is preferable to use a metal oxide. Silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen. Silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0431] An insulator 282 is provided on the insulator 280. The insulator 282 is resistant to oxygen and hydrogen. It is preferable to use a material that has a barrier property against the insulator 282. The insulator 282 may be made of the same material as 214. For example, the insulator 282 may be made of aluminum oxide. It is preferable to use metal oxides such as titanium oxide, hafnium oxide, and tantalum oxide.

[0432] In particular, aluminum oxide is highly resistant to oxygen and water, which can cause fluctuations in the electrical characteristics of transistors. It has a high blocking effect that does not allow impurities such as oxygen and moisture to pass through the membrane. Aluminum oxide is highly resistant to hydrogen, moisture, etc. during and after the transistor manufacturing process. This can prevent impurities from entering the transistor 200 and the transistor 345. In addition, the oxygen from the oxide constituting the transistor 200 and the transistor 345 is Therefore, the transistor 200 and the transistor 345 can suppress the emission. It is suitable for use as a protective film against

[0433] In addition, in the case where the transistor 400a is provided as the transistor 200, When the transistor 400d is provided as the transistor 345, the insulator 230 is connected to the insulator 401. The edge 232 is connected to the insulator 301, the insulator 220 is connected to the insulator 302, and the insulator 222 is connected to the insulator 303. 03, insulator 224 is connected to insulator 402, insulator 280 is connected to insulator 410, and insulator 282 is connected to insulator 402. corresponds to the insulator 420. Therefore, the description of the corresponding structure in the previous embodiment should be referred to. It is possible.

[0434] Moreover, an insulator 286 is provided on the insulator 282. The insulator 286 is This corresponds to the insulator 422 shown in the embodiment. The description can be taken into consideration.

[0435] In addition, the insulator 220, the insulator 222, the insulator 224, the insulator 280, the insulator 282, and The conductor 246 and the conductor 248 are embedded in the openings formed in the insulator 286. The conductor 246 and the conductor 248 are the same as the conductor 108a shown in the previous embodiment. conductor 108b, etc. Therefore, the description of the corresponding configuration shown in the above embodiment can be taken into consideration.

[0436] The conductor 246 and the conductor 248 are connected to the capacitive element 360, the transistor 200, the transistor 345, or a plug or wiring electrically connected to the transistor 300. The conductor 246 and the conductor 248 are connected to the conductor 328 and the conductor 33. It can be provided using the same materials as in 0.

[0437] Next, a capacitor 360 is provided on the transistor 200. 2A through openings formed in insulators 286, 288, 290, and 292. Here, the insulator 286 is embedded in the insulator 422, and the insulator 28 8 to insulator 112, insulator 290 to insulator 114, insulator 292 to insulator 116, Therefore, the description of the corresponding configurations shown in the previous embodiment should be taken into consideration. Other configurations of the capacitance element 360 can also be described in the above embodiment. The configuration of the capacitance element 100 described above can be taken into consideration.

[0438] An insulator 294 is provided on the capacitor element 360. The insulator 294 is The insulator 294 may function as a flattening film that covers the uneven shape. 1 corresponds to the insulator 150 shown in FIG. 1. Therefore, the description of the corresponding structure shown in the previous embodiment should be referred to. It is possible.

[0439] Insulators 288, 290, 292, and 294 are provided with openings. A conductor 296 and a conductor 298 are provided so as to be embedded. The conductor 298 is a plug that electrically connects to the transistor 200 or the transistor 345. The conductor 296 and the conductor 298 function as a wiring. This corresponds to the conductor 162a and the conductor 162b shown in the embodiment. The description of the corresponding configuration shown in the embodiment can be taken into consideration.

[0440] In addition, by dividing a large-area substrate into individual semiconductor elements, multiple semiconductor devices can be manufactured into chips. Dicing lines (scribe lines, dividing lines, or The dividing method is as follows: After forming grooves (dicing lines) on the substrate to separate the semiconductor elements, In some cases, the semiconductor device is cut at the in-line and divided (divided) into a number of semiconductor devices. For example, FIG. The structure 500 shown in FIG.

[0441] For example, as shown in structure 500, transistor 200 or transistor 345 may be In the vicinity of a region overlapping with a dicing line provided on the outer edge of the memory cell having an insulating Insulator 280, insulator 224, insulator 222, insulator 220, insulator 232, insulator 230, and An opening is provided in the insulator 216. In addition, the insulator 280, the insulator 224, the insulator 222, the insulator An insulator is provided to cover the sides of the edge 220, the insulator 232, the insulator 230 and the insulator 216. 282 shall be set forth.

[0442] That is, the insulator 214 and the insulator 282 are in contact with each other at the opening. By forming the insulating body 214 and the insulating body 282 using the same material and method, the adhesion is improved. For example, aluminum oxide can be used.

[0443] This structure allows the insulator 214 and the insulator 282 to separate the insulator 280 and the transistor 20. 0, and transistor 345. The insulator 282 has a function of suppressing the diffusion of oxygen, hydrogen, and water. The substrate is divided into a plurality of circuit regions each having a semiconductor element formed thereon. Even if the chips are processed, impurities such as hydrogen or water may enter the chips from the side of the cut substrate. Diffusion to transistor 200 or transistor 345 can be prevented.

[0444] In addition, this structure allows excess oxygen in the insulator 280 to migrate to the insulators 282 and 222. Therefore, the excess oxygen in the insulator 280 can be prevented from diffusing out of the insulator 280. The oxide on which the channel of the transistor 200 or the transistor 345 is formed is The oxygen is supplied to the transistor 200 or the transistor 345. This reduces the oxygen vacancies in the oxide in which the channel is formed. The oxide on which the channel of the transistor 200 or the transistor 345 is formed is then subjected to a defect-preventing process. It is possible to obtain an oxide semiconductor having a low potential density and stable characteristics. The fluctuation of the electrical characteristics of the transistor 200 or the transistor 345 is suppressed, and the reliability is improved. It can be raised.

[0445] In the semiconductor device shown in FIG. 27, the gate of the transistor 300 is connected to the conductor 2. 46 and the other of the source and drain of the transistor 200 via the conductor 248. Although the semiconductor device shown in this embodiment has a structure in which the electrodes are electrically connected, the semiconductor device is not limited to this structure. For example, as shown in FIG. The source and drain of 200 are not electrically connected to the other, and the conductor 246 and the conductor 24 8, the conductor 296, and the conductor 298 are electrically connected to the wiring 3011. It may be possible to make it.

[0446] The above is a description of the configuration example. By using this configuration, In a semiconductor device using a transistor, the fluctuation of electrical characteristics is suppressed and the reliability is improved. Alternatively, a semiconductor device including a transistor including an oxide semiconductor can be In the transistor having an oxide semiconductor, power consumption can be reduced. In a semiconductor device using the capacitor, miniaturization or high integration can be achieved. It is possible to provide thin and highly integrated semiconductor devices with good productivity.

[0447] <Memory cell array structure> Next, an example of the memory cell array of this embodiment is shown in FIG. The memory cell array is constructed by arranging the memory cells in a matrix. In addition, the transistor 345 shown in FIG. 27 is omitted in FIG. 29. When the memory devices shown in FIG. 27 are arranged in a matrix, a part of the rows is extracted. FIG.

[0448] Also, FIG. 29 differs from FIG. 27 in the configuration of the transistor 300. In the case of the sintered body 300, a semiconductor region 313 (a part of a substrate 311) in which a channel is formed has a convex shape. The side and top surfaces of the semiconductor region 313 are connected to the conductor 31 via the insulator 315. The conductor 316 is made of a material that adjusts the work function. Such a transistor 300 utilizes the protruding portion of the semiconductor substrate, so that the FI It is also called an N-type transistor. In addition, the mass that contacts the top of the convex portion to form the convex portion is In this embodiment, a part of the semiconductor substrate is processed to form an insulating layer. The case where the convex portion is formed by processing the SOI substrate is shown, but the convex semiconductor film is formed by processing the SOI substrate. You may do so.

[0449] In the memory device shown in FIG. 29, a memory cell 600a and a memory cell 600b are arranged adjacent to each other. The memory cell 600a and the memory cell 600b are configured as follows: The transistor 200 and the capacitor element 360 are included. 003, the wiring 3004, the wiring 3005, and the wiring 3006. Similarly, in the memory cell 600a and the memory cell 600b, the transistor 300 A node where the gate of the capacitor 360 is electrically connected to one of the electrodes of the capacitor 360 is referred to as a node FG. The wiring 3002 is shared by the adjacent memory cells 600a and 600b. This is the wiring.

[0450] When memory cells are arranged in an array, the information in the desired memory cell is read. For example, if the memory cell array is a NOR type, the information must be read. By making the transistor 300 of the memory cell that is not overflowing non-conductive, the desired memory cell In this case, the charge on the node FG is not affected by the charge. The potential at which transistor 300 is in a "non-conducting state," i.e., V th_H Lower voltage The potential may be applied to the wiring 3005 connected to the memory cell from which data is not read. For example, when the memory cell array is configured as a NAND type, memory cells from which information is not read By making the transistor 300 conductive, only the information of the desired memory cell is read out. In this case, the transistor 300 can be " The potential at which the device is in a "conducting state," that is, V th_L Higher voltages do not read information This may be provided to the wiring 3005 connected to the memory cell.

[0451] By using this structure, a semiconductor device including a transistor having an oxide semiconductor This makes it possible to suppress the fluctuation of electrical characteristics and improve reliability. In a semiconductor device using a transistor having a compound semiconductor, it is possible to reduce power consumption. In addition, in a semiconductor device including a transistor having an oxide semiconductor, Alternatively, a miniaturized or highly integrated semiconductor device can be achieved. can be provided with high productivity.

[0452] The configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0453] (Embodiment 3) In this embodiment, the present invention is applied to a display controller IC, a source driver IC, etc. A frame memory including a semiconductor device according to one embodiment of the present invention will be described.

[0454] The frame memory is provided with, for example, 1T (transistor) 1C (capacitor) type memory cells. A DRAM (dynamic random access memory) with a higher capacity can be applied. A memory device in which an OS transistor is used in a memory cell (hereinafter referred to as an “OS memory”) ) can be used. Here, as an example of the OS memory, a 1T1C type memory cell Here, we will explain a RAM having such a function. They call it "Dynamic Oxide Semiconductor RAM (DOSRAM)." Figure 30 shows an example of the configuration of DOSRAM.

[0455] < <dosram1400>> The DOSRAM 1400 includes a controller 1405, row circuits 1410, column circuits 1415, A memory cell and sense amplifier array 1420 (hereinafter referred to as "MC-SA array 1420") (Call.)

[0456] The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, and a column selector 14 13, the sense amplifier driver circuit 1414. The column circuit 1415 is a global sense The global sense amplifier array 1416 includes an input / output circuit 1417. 416 has a plurality of global sense amplifiers 1447. The MC-SA array 1420 Memory cell array 1422, sense amplifier array 1423, global bit line GBLL , with GBLR.

[0457] (MC-SA Array 1420) The MC-SA array 1420 connects the memory cell array 1422 to the sense amplifier array 142 The global bit lines GBLL and GBLR are In the DOSRAM 1400, the bit line structure is A hierarchical bit line structure is adopted, which is made up of hierarchical local bit lines and global bit lines. For example, when the semiconductor device shown in FIG. 28 is used in a DOSRAM 1400, The array 1422 is formed of a layer including the transistor 200 and the capacitance element 360, and the sense amplifier The array 1423 may be constructed from a layer including the transistor 300 .

[0458] The memory cell array 1422 is a local memory cell array having N pieces (N is an integer of 2 or more). 1425 <0> —1425 <n-1>FIG. 31(A) shows a local memory cell array. The local memory cell array 1425 includes a plurality of memory cells 1 445, a plurality of word lines WL, and a plurality of bit lines BLL and BLR. In the example, the structure of the local memory cell array 1425 is an open bit line type, but It may be of the blocked bit line type.

[0459] FIG. 31B shows an example of the circuit configuration of the memory cell 1445. The memory cell 1445 is a transistor. The transistor MW1 has a capacitance element CS1 and terminals B1 and B2. The gate of transistor MW1 is electrically connected to the word line. a first terminal electrically connected to the bit line and a second terminal electrically connected to the first terminal of the capacitance element CS1; The second terminal of the capacitance element CS1 is electrically connected to the terminal B2. A constant voltage (for example, a low power supply voltage) is input to the terminal B2. For example, in FIG. When the semiconductor device shown in FIG. 8 is used in the DOSRAM 1400, a transistor MW1 is used as the transistor The transistor 200 can be used, and the capacitive element 360 can be used as the capacitive element CS1.

[0460] Transistor MW1 has a back gate that is electrically connected to terminal B1. Therefore, the voltage at terminal B1 controls the threshold voltage of transistor MW1. For example, the voltage at terminal B1 is a fixed voltage (e.g., a constant negative voltage). Alternatively, the voltage at the terminal B1 may be changed depending on the operation of the DOSRAM 1400. stomach.

[0461] The back gate of transistor MW1 is connected to the gate, source, or drain of transistor MW1. Alternatively, the transistor MW1 may be provided with a back gate. It's not necessary.

[0462] The sense amplifier array 1423 includes N local sense amplifier arrays 1426 <0> - 1426 <n-1>The local sense amplifier array 1426 has one switch amplifier. The array 1444 includes a plurality of sense amplifiers 1446. The sense amplifiers 1446 include a bit The sense amplifier 1446 precharges the bit line pair. The function of this bit line pair is to amplify the voltage difference between the bit lines, and to hold this voltage difference. The switch array 1444 selects a bit line pair and connects the selected bit line pair to a global bit line. It has the function of establishing electrical continuity between the line pairs.

[0463] Here, a bit line pair is a pair of two bit lines that are compared simultaneously by a sense amplifier. Global bit line pairs are compared simultaneously by a global sense amplifier. A bit line pair is a pair of global bit lines. The global bit line pair can be called a pair of global bit lines. In the bit line pair, the bit line BLL and the bit line BLR form a bit line pair. The BLL and the global bit line GBLR form a global bit line pair. They are also referred to as a global bit line pair (BLL, BLR) and a global bit line pair (GBLL, GBLR).

[0464] (Controller 1405) The controller 1405 has a function of controlling the overall operation of the DOSRAM 1400 . The controller 1405 performs logical operations on command signals input from the outside and determines the operation mode. The row circuit 1410 and the column circuit 1420 are provided to determine the operation mode. A function for generating the control signal of 415, a function for holding the address signal input from the outside, The EEPROM has a function of generating an external address signal.

[0465] (row circuit 1410) The row circuit 1410 has the function of driving the MC-SA array 1420. The word line driver circuit 1412 has a function of decoding the address signal. A selection signal is generated to select the word line WL of the row to be accessed.

[0466] The column selector 1413 and the sense amplifier driver circuit 1414 are connected to the sense amplifier array 142. The column selector 1413 is a circuit for driving the bit line of the column to be accessed. The column selector 1413 has a function of generating a selection signal for selecting The switch array 1444 of each local sense amplifier array 1426 is controlled. A plurality of local sense amplifier arrays 1 The 426 is independently driven.

[0467] (column circuit 1415) The column circuit 1415 has a function of controlling the input of the data signal WDA[31:0], The data signal WDA[31:0] has the function of controlling the output of RDA[31:0]. data signal RDA[31:0] is a write data signal, and data signal RDA[31:0] is a read data signal.

[0468] The global sense amplifier 1447 supplies power to the global bit line pair (GBLL, GBLR). The global sense amplifier 1447 is electrically connected to the global bit line pair (GB It has the function of amplifying the voltage difference between the G-channel LL and the G-channel LR, and the function of maintaining this voltage difference. Data can be written to and read from the global bit line pair (GBLL, GBLR) by input This is performed by the output circuit 1417.

[0469] The write operation of the DOSRAM 1400 will be briefly described. Then, data is written to the global bit line pair. The address signal is held by the global sense amplifier array 1416. The switch array 1444 of the Calsense amplifier array 1426 switches the global bit The data on the line pair is written to the bit line pair of the target column. 26 amplifies and holds the written data. In 1425, the word line WL of the target row is selected by the row circuit 1410, and the selected row The data held in the local sense amplifier array 1426 is written to the memory cell 1445 of the do.

[0470] The following is an overview of the read operation of the DOSRAM1400. A row of the local memory cell array 1425 is specified. In the row 1425, the word line WL of the target row is selected, and the de-energization of the memory cell 1445 is performed. The local sense amplifier array 1426 writes data to the bit lines. The voltage difference between the bit line pair is detected as data and stored. The address signal is specified among the data held in the local sense amplifier array 1426. The data of the corresponding column is written to the global bit line pair. The global sense amplifier 1416 detects and holds the data of the global bit line pair. The data held in the amplifier array 1416 is output to the input / output circuit 1417. The operation is completed.

[0471] In order to rewrite data by charging and discharging the capacitance element CS1, the DOSRAM1400 has In principle, there is no limit to the number of times it can be rewritten, and data can be written and rewritten with low energy. In addition, since the circuit configuration of the memory cell 1445 is simple, it is possible to read out a large capacity It is easy to

[0472] The transistor MW1 is an OS transistor. Since it is small, it is possible to suppress leakage of electric charge from the capacitance element CS1. Therefore, the retention time of DOSRAM1400 is much longer than that of DRAM. This reduces the frequency of refresh operations, and therefore reduces the power required for refresh operations. By using DOSRAM1400 as frame memory, the display controller IC, In addition, the power consumption of the source driver IC can be reduced.

[0473] The MC-SA array 1420 has a stacked structure, which allows the local sense amplifier array The bit line can be shortened to a length similar to that of the 1426. This reduces the bit line capacitance, and the storage capacitance of the memory cell 1445 can be reduced. In addition, the local sense amplifier array 1426 can be provided with a switch array 1444. This allows the number of long bit lines to be reduced. This reduces the load on the display controller IC and the source The energy consumption of the driver IC can be reduced.

[0474] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0475] (Embodiment 4) In this embodiment, a transistor (OS One example of a semiconductor device that uses a transistor is the FPGA (Field Programmable Gate Array). This embodiment describes the FPGA (configurable gate array). The OS memory is applied to the application memory and registers. FPGA is called "OS-FPGA".

[0476] The OS memory includes at least a capacitance element and an OS transistor that controls the charging and discharging of the capacitance element. Since the OS transistor has a very small off-state current, S memory has excellent retention characteristics and can function as a non-volatile memory.

[0477] FIG. 32(A) shows an example of the configuration of an OS-FPGA. 110 is a multi-context architecture that supports context switching and fine-grained power management for each PLE. It is possible to perform normally-off (NOFF) computing by performing gating. The OS-FPGA 3110 includes a controller 3111, a word driver 3112, a data driver 3113, and a It has a driver 3113 and a programmable area 3115.

[0478] The programmable area 3115 includes two input / output blocks (IOBs) 3117, a core 3 The IOB 3117 has a number of programmable input / output circuits. 19 includes a plurality of logic array blocks (LABs) 3120, a plurality of switch array blocks The LAB3120 has multiple PLE3121. FIG. 32(B) shows an example in which the LAB3120 is configured with five PLE3121s. As shown in Fig. C, the SAB3130 has multiple switch blocks (SB ) 3131. The LAB3120 has its own input terminal and 4( It is connected to the LAB3120 in the up, down, left, right (left and right) directions.

[0479] SB3131 will be described with reference to FIG. 33(A) to FIG. 33(C). The SB3131 shown in A) has data, datab, and signals context[1:0], The signal word[1:0] is input. data and datab are configuration The logic of data and datab is complementary. OS-FPGA31 The number of contexts in the 10 is 2, and the signal context[1:0] is the context selection signal. The signal word[1:0] is a word line selection signal. The wiring to which these signals are input is the word line.

[0480] SB3131 is a PRS (Programmable Routing Switch) 3133[0], 3 PRS3133[0] and 3133[1] can store complementary data. The PRS3133[0] and PRS3133[1] have a configuration memory (CM) that can be used to When there is no distinction between RS3133[1] and PRS3133, it is called PRS3133. It seems that.

[0481] Figure 33(B) shows an example of the circuit configuration of PRS3133[0]. RS3133[1] has the same circuit configuration. PRS3133[0] and PRS3133 [1] differs from [1] in the input context selection signal and word line selection signal. ext[0], word[0] are input to PRS3133[0], and the signal context [1], word[1] is input to PRS3133[1]. For example, In this case, when the signal context[0] becomes "H", PRS3133[0] becomes active. Become a Tib.

[0482] PRS3133[0] includes CM3135 and Si transistor M31. Transistor M31 is a pass transistor controlled by CM3135. The memory circuits 3137 and 3137B are the same. The memory circuit 3137 has the same circuit configuration as the memory circuit 3137. , and MO32. The memory circuit 3137B includes a capacitance element CB31, an OS transistor M Has OB31 and MOB32.

[0483] The OS transistors MO31, MO32, MOB31, and MOB32 have back gates. , and these back gates are each electrically connected to a power supply line that supplies a fixed voltage.

[0484] The gate of the Si transistor M31 is the node N31, and the gate of the OS transistor MO32 is the The gate of the OS transistor MOB32 is at node N32, and the gate of the OS transistor MOB32 is at node NB32. Nodes N32 and NB32 are charge storage nodes of the CM3135. The MO32 controls the conduction state between the node N31 and the signal line for the signal context[0]. The OS transistor MOB32 controls the conduction between the node N31 and the low-potential power supply line VSS. Control the state.

[0485] The logic of the data held in the memory circuits 3137 and 3137B is complementary. Therefore, either the OS transistor MO32 or MOB32 is turned on.

[0486] An example of the operation of PRS3133[0] will be described with reference to FIG. 33(C). Configuration data has already been written to PRS3133[0]. The node N32 is at "H" and the node NB32 is at "L".

[0487] While signal context[0] is low, PRS3133[0] is inactive. During this period, even if the input terminal of PRS3133[0] transitions to "H", the Si transistor The gate of register M31 is kept at "L" and the output terminal of PRS3133[0] is also kept at "L". Will be maintained.

[0488] PRS3133[0] is active while signal context[0] is high. When the signal context[0] transitions to "H", the configuration stored in the CM3135 is The gate of the Si transistor M31 transitions to "H" due to the configuration data.

[0489] When the input terminal transitions to "H" while PRS3133[0] is active, Since the OS transistor MO32 of the memory circuit 3137 is a source follower, The gate voltage of the Si transistor M31 rises due to the switching. The OS transistor MO32 of the 3137 loses its driving capability, and the gate of the Si transistor M31 The object becomes floating.

[0490] The CM3135 is a multi-context device that supports the PRS3133. It also has the functions of a grass plant.

[0491] Figure 34 shows an example of the configuration of the PLE3121. The PLE3121 uses a LUT (look-up table). (Bulb) block 3123, register block 3124, selector 3125, CM3126 The LUT block 3123 selects the internal data according to the inputs inA-inD. The selector 3125 selects the configuration stored in the CM3126 and outputs it. Depending on the application data, the output of the LUT block 3123 or the register block 312 Select output 4.

[0492] The PLE3121 is electrically connected to the power supply line for the voltage VDD via the power switch 3127. The power switch 3127 is turned on and off according to the configuration stored in the CM3128. Each PLE 3121 has a power switch 312 By providing the 7, fine-grained power gating is possible. This feature allows the power gating of unused PLE3121s after a context switch. Since the standby power consumption can be reduced by 100%, standby power consumption can be reduced effectively.

[0493] To achieve NOFF computing, the register block 3124 is The non-volatile registers in the PLE3121 are free registers with OS memory. This is a flip-flop (hereinafter referred to as [OS-FF]).

[0494] The register block 3124 includes OS-FFs 3140[1] and 3140[2]. Signals user_res, load, and store are OS-FF3140[1], 3140[ The clock signal CLK1 is input to the OS-FF3140[1] and The clock signal CLK2 is input to the OS-FF 3140[2]. An example of the configuration of 3140 is shown below.

[0495] The OS-FF3140 includes an FF3141 and a shadow register 3142. The clock signal is input to the node CK. The signal user_res is input to node R. The signal user_res is a reset signal. Node D is the data input node, and node Q is the data output node. Node Q and node QB have a complementary relationship in logic.

[0496] The shadow register 3142 functions as a backup circuit for the FF 3141. The store register 3142 stores the data of the nodes Q and QB in accordance with the signal store. Also, in response to the signal load, the backed up data is written to nodes Q and QB. Return.

[0497] The shadow register 3142 includes inverter circuits 3188 and 3189, a Si transistor M37, MB37, memory circuits 3143, 3143B. The memory circuit 3137 of the PRS3133 has the same circuit configuration as the memory circuit 3137 of the PRS3133. 143 includes a capacitance element C36, an OS transistor MO35, and an OS transistor MO36. The memory circuit 3143B includes a capacitance element CB36, an OS transistor MOB35, an OS transistor MOB36, and an OS transistor MOB37. The nodes N36 and NB36 are connected to the OS transistors MO36 and MOB36. Node N3 is the gate of transistor MOB36 and is a charge storage node. 7, NB37 are the gates of Si transistors M37, MB37.

[0498] The OS transistors MO35, MO36, MOB35, and MOB36 have a back gate. , and these back gates are each electrically connected to a power supply line that supplies a fixed voltage.

[0499] An example of the operation method of the OS-FF 3140 will be described with reference to FIG.

[0500] (backup) When a "H" signal store is input to the OS-FF3140, the shadow register 31 Node N36 backs up the data of node Q. When data is written, it becomes "L", and the data of node QB is written to node NB36. Then, power gating is performed and the power switch Turn off 3127. The data on nodes Q and QB of FF3141 will be lost, but the power will be off. Even if this is the case, the shadow register 3142 holds the backed up data.

[0501] (Recovery) Turn on the power switch 3127 to supply power to the PLE3121. Then, " When a "H" signal load is input to the OS-FF 3140, the shadow register 3142 Write the backed up data back to FF3141. Node N36 is "L", so Therefore, the node N37 is maintained at "L" and the node NB36 is at "H", so that the node NB 37 becomes "H". Therefore, node Q becomes "H" and node QB becomes "L". This causes the OS-FF3140 to return to the state it was in during backup operation.

[0502] Combining fine-grained power gating with the backup / recovery operation of the OS-FF3140 can effectively reduce the power consumption of the OS-FPGA3110. By combining them, the power consumption of the OS-FPGA3110 can be effectively reduced.

[0503] An error that can occur in the memory circuit includes a soft error caused by the incidence of radiation. Soft errors are caused by alpha rays emitted from materials such as those constituting the memory and package, or by secondary cosmic ray neutrons generated when primary cosmic rays incident from space on the atmosphere react with the nuclei of atoms existing in the atmosphere. When these irradiate transistors, electron-hole pairs are generated, resulting in malfunction such as the inversion of data held in the memory. An OS memory using OS transistors has high soft error tolerance. Therefore, by mounting an OS memory, a highly reliable OS-FPGA3110 can be provided.

[0504] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments.

[0505] (Embodiment 5) In this embodiment, an example of a CPU including a semiconductor device according to one aspect of the present invention, such as the storage device described above, will be described.

[0506] <Configuration of CPU> The semiconductor device 5400 shown in FIG. 36 has a CPU core 5401, a power management unit 5421, and a peripheral circuit 5422. The power management unit 5421 has a power controller 5402 and a power switch 5403. The peripheral circuit 5 422 has a cache 5404 having a cache memory and a bus interface (BU SI / F) 5405 and Debug Interface (Debug I / F) 5406 The CPU core 5401 is connected to a data bus 5423, a control device 5407, a PC (processor), gram counter) 5408, pipeline register 5409, pipeline register 54 10, ALU (Arithmetic logic unit) 5411, and registers The CPU core 5401 and the peripheral circuits 5404 and the like are included. Data is exchanged with 422 via a data bus 5423.

[0507] The semiconductor device (cell) includes a power controller 5402, a control device 5407, and many other components. This can be applied to many logic circuits. In particular, it is possible to configure them using standard cells. As a result, the small semiconductor device 5400 can be applied to all logic circuits that can be implemented. In addition, a semiconductor device 5400 capable of reducing power consumption can be provided. In addition, it is possible to provide a semiconductor device 5400 capable of improving the operating speed. It is possible to provide a semiconductor device 5400 capable of reducing the fluctuation of the

[0508] The semiconductor device (cell) includes a p-channel Si transistor and the oxide semiconductor device described in the above embodiment. The channel forming region includes an oxide semiconductor (preferably an oxide containing In, Ga, and Zn). By using a transistor and applying the semiconductor device (cell) to the semiconductor device 5400, It is possible to provide a small-sized semiconductor device 5400. In addition, it is possible to provide a semiconductor device capable of reducing power consumption. In addition, the semiconductor device 5400 can be provided with an improved operating speed. In particular, by using only p-channel type Si transistors, manufacturing costs can be reduced. This can be easily suppressed.

[0509] The control unit 5407 includes a PC 5408, a pipeline register 5409, and a pipeline register 5408. register 5410, ALU 5411, register file 5412, cache 5404, buffer The power control interface 5405, the debug interface 5406, and the power By controlling the operation of the controller 5402 in an integrated manner, the input application and other programs can be It has the ability to decode and execute instructions contained in the program.

[0510] The ALU 5411 has a function of performing various arithmetic operations such as arithmetic operations and logical operations.

[0511] The cache 5404 has a function of temporarily storing frequently used data. PC5408 is a register having the function of storing the address of the next instruction to be executed. Although not shown in FIG. 36, the cache 5404 includes a cache memory operation A cache controller is provided to control the

[0512] The pipeline register 5409 is a register that has the function of temporarily storing instruction data. It is.

[0513] The register file 5412 has a number of registers including general-purpose registers. Data read from the on-chip memory or data obtained as a result of the ALU5411 arithmetic processing It is possible to store data, etc.

[0514] The pipeline register 5410 stores data used in the arithmetic processing of the ALU 5411, Has the function of temporarily storing data obtained as a result of the ALU5411 arithmetic processing. It is a register.

[0515] The bus interface 5405 is connected to the semiconductor device 5400 and to the outside of the semiconductor device 5400. It functions as a data path between various devices. The interface 5406 is used to input commands for controlling debugging to the semiconductor device 5400. It functions as a signal path.

[0516] The power switch 5403 is a power controller 540 It has the function of controlling the supply of power supply voltage to various circuits other than 2. Each circuit belongs to a different power domain. The power switch 5403 controls whether or not the power supply voltage is supplied. The controller 5402 has a function of controlling the operation of the power switch 5403 .

[0517] The semiconductor device 5400 having the above configuration is capable of performing power gating. The flow of the power gating operation will be described with an example.

[0518] First, the CPU core 5401 determines the timing to stop the supply of power voltage based on the power controller. Then, the CPU core 5401 sets the register of the power controller 5402. Next, the semiconductor device 5402 is instructed to start power gating. The various registers and cache 5404 included in 400 start to save data. The power supply to various circuits other than the power controller 5402 of the semiconductor device 5400 is The supply of voltage is stopped by the power switch 5403. Then, an interrupt signal is generated to By inputting the data to the controller 5402, the power supply to various circuits of the semiconductor device 5400 is The supply of the power supply voltage is started. Note that a counter is provided in the power controller 5402. The timing at which the supply of the power supply voltage is started is determined by the counter, without depending on the input of an interrupt signal. Then, various registers and caches 5404 determine the data. The return of data begins. Instruction execution in Controller 5407 then resumes.

[0519] Such power gating can be applied to the entire processor or to a part of the processor. It can be done in one or more logic circuits. This allows for fine-grained spatial and temporal analysis of power consumption. Reductions can be made.

[0520] When power gating is performed, the information held by the CPU core 5401 and the peripheral circuit 5422 is It is preferable to be able to evacuate information in a short period of time. This allows the power to be turned on and off in a short period of time. This makes it possible to achieve greater power saving effects.

[0521] In order to evacuate the information held by the CPU core 5401 and the peripheral circuit 5422 in a short period of time, It is preferable that the flip-flop circuit can save data within the circuit (backup possible) In addition, the SRAM cell can store data within the cell. (called a backup-capable SRAM cell). The flop circuit and the SRAM cell are made of an oxide semiconductor (preferably containing In, Ga, and Zn). It is preferable to have a transistor having a channel formation region made of a thin film of a ferroelectric material. The low off-state current of transistors allows for the development of backup flip-flop circuits and SRAM cells can retain information for long periods without power. The high switching speed of SRAM cells may be capable of short-term data storage and restoration.

[0522] An example of a flip-flop circuit capable of backing up will be described with reference to FIG.

[0523] The semiconductor device 5500 shown in FIG. 37 is an example of a flip-flop circuit capable of backing up. The semiconductor device 5500 includes a first memory circuit 5501, a second memory circuit 5502, and The semiconductor device 5500 includes a third memory circuit 5503 and a reading circuit 5504. The potential difference between potential V1 and potential V2 is supplied to the In the following, the potential V1 is at a low level, and the potential V2 is at a high level. A configuration example of the semiconductor device 5500 will be described below by taking the case where the terminal V2 is at a high level as an example. It shall be so.

[0524] The first memory circuit 5501 stores the following data during a period in which a power supply voltage is supplied to the semiconductor device 5500: When a signal D containing data is input, the data is held. During a period in which a power supply voltage is supplied to the semiconductor device 5500, the first memory circuit 550 A signal Q including the stored data is output from the first memory circuit 55. 01 holds data during the period when the power supply voltage is not supplied to the semiconductor device 5500. In other words, the first memory circuit 5501 is called a volatile memory circuit. It is possible.

[0525] The second memory circuit 5502 reads the data stored in the first memory circuit 5501. The third memory circuit 5503 has a function of storing (or saving) the second memory. A function to read and store (or save) data held in the memory circuit 5502 The read circuit 5504 has the second memory circuit 5502 or the third memory circuit 55 The data held in the memory 5503 is read out and stored in the first memory circuit 5501 (or restored). It has the function of

[0526] In particular, the third memory circuit 5503 is configured to store a power supply voltage when the semiconductor device 5500 is not supplied with the power supply voltage. During this period, the data held in the second memory circuit 5502 is read and stored ( or evacuate.

[0527] As shown in FIG. 37, the second memory circuit 5502 includes a transistor 5512 and a capacitor 55 The third memory circuit 5503 includes a transistor 5513 and a transistor 55 15 and a capacitor 5520. The reading circuit 5504 includes a transistor 5510 and , a transistor 5518, a transistor 5509, and a transistor 5517. do.

[0528] The transistor 5512 outputs a current according to the data stored in the first memory circuit 5501. The transistor 5512 has a function of charging and discharging a load to a capacitor 5519. A charge according to the data held in the memory circuit 5501 is quickly transferred to the capacitor element 5519. It is preferable that the transistor 5512 is a crystalline silicon. Silicon (preferably polycrystalline silicon, more preferably single crystal silicon) is placed in the channel forming region. It is desirable to include it in the region.

[0529] The transistor 5513 is turned on or off depending on the charge held in the capacitor 5519. The transistor 5515 is turned on when the transistor 5513 is turned on. When the capacitor 5520 is in the ON state, the capacitor 5520 is charged and discharged in response to the potential of the wiring 5544. It is preferable that the off-state current of the transistor 5515 is extremely small. The transistor 5515 is formed using an oxide semiconductor (preferably an oxide semiconductor containing In, Ga, and Zn). It is preferable that the channel forming region contains a nitride.

[0530] The connection relationship of each element will be specifically described as follows. The source and drain of the transistor 5512 One of the terminals is connected to the first memory circuit 5501. The other of the drain and the drain is one electrode of a capacitor 5519, a gate of a transistor 5513, and a gate of a transistor 5518. The other electrode of the capacitor 5519 is , and is connected to a wiring 5542. One of the source and drain of the transistor 5513 is , and is connected to a wiring 5544. The other of the source and drain of the transistor 5513 is , connected to one of the source and drain of the transistor 5515. The other of the source and drain of the transistor 515 is connected to one electrode of a capacitor element 5520 and The other electrode of the capacitor 5520 is connected to the gate of the capacitor 5510. One of the source and drain of the transistor 5510 is connected to a wiring 5541. The other of the source and drain of the transistor 5510 is connected to a transistor The source of the transistor 5518 is connected to one of the source and drain of the transistor 5518. The other of the drain and the source is connected to one of the drain and the source of a transistor 5509. The other of the source and drain of the transistor 5509 is connected to the source of the transistor 5517. The transistor is connected to one of the source and drain of the first memory circuit 5501. The other of the source and drain of 5517 is connected to a wiring 5540. In this case, the gate of the transistor 5509 is connected to the gate of the transistor 5517. However, the gate of transistor 5509 is not necessarily the gate of transistor 5517. The input / output terminals 11 and 12 may not be connected to each other.

[0531] The transistor described in the above embodiment can be used as the transistor 5515. Since the off-state current of the transistor 5515 is small, the semiconductor device 5500 can be powered for a long period of time. The switching characteristics of the transistor 5515 allow the data to be stored without a power supply. Because of this, the semiconductor device 5500 can perform high speed backup and recovery. can.

[0532] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0533] (Embodiment 6) In this embodiment, one embodiment of a semiconductor device according to one aspect of the present invention is shown in FIG. 38 and FIG. 9 will be used to explain.

[0534] <Semiconductor wafers, chips> FIG. 38(A) shows a top view of the substrate 711 before the dicing process is performed. The substrate 711 may be, for example, a semiconductor substrate (also called a "semiconductor wafer"). A plurality of circuit regions 712 are provided on the substrate 711. A semiconductor device or the like according to one embodiment of the present invention can be provided in the semiconductor device.

[0535] Each of the multiple circuit regions 712 is surrounded by an isolation region 713. A separation line (also called a "dicing line") 714 is set at a position where the separation line overlaps with the separation line. By cutting the substrate 711 along 714, a chip 715 including a circuit region 712 is formed on the substrate. The chip 715 can be cut out from the chip 711. An enlarged view of the chip 715 is shown in FIG.

[0536] In addition, a conductive layer, a semiconductor layer, or the like may be provided in the separation region 713. By providing a semiconductor layer, etc., ESD that may occur during the dicing process is mitigated, and the dicing This prevents the yield reduction caused by the dicing process. For the purposes of cooling the substrate, removing shavings, preventing static electricity, etc., carbon dioxide gas is dissolved in the The cutting is performed while supplying pure water with reduced resistivity to the cutting portion. By providing the above, the amount of pure water used can be reduced. The production cost can be reduced, and the productivity of the semiconductor device can be increased.

[0537] <Electronic components> An example of an electronic component using the chip 715 will be described with reference to FIGS. 39(A) and 39(B). The electronic components are also called semiconductor packages or IC packages. Electronic components have multiple standards and names depending on the terminal direction, terminal shape, etc. There is.

[0538] The electronic component is assembled with the semiconductor device shown in the above embodiment in the assembly process (post-process). The semiconductor device is then assembled with other components to complete the device.

[0539] The following process will be described with reference to the flow chart shown in FIG. After forming a semiconductor device according to one embodiment of the present invention on the substrate 711, the back surface ( The back surface (the surface on which semiconductor devices are not formed) is ground (step By thinning the substrate 711 by grinding, it is possible to miniaturize electronic components. Cut.

[0540] Next, a "dicing step" is performed to separate the substrate 711 into a plurality of chips 715 (step Then, the separated chips 715 are bonded onto individual lead frames in the "Die-Piece Process" (S722). The die bonding process is then performed (step S723). The bonding between the lead frame and the P715 can be done by resin or tape. Select the appropriate method according to the product. Note that an interposer is used instead of a lead frame. A chip 715 may be bonded onto the substrate.

[0541] Next, the leads of the lead frame and the electrodes on the chip 715 are connected with thin metal wires (wires). ) to perform the "wire bonding process" for electrical connection (step S724). For the thin wire, silver wire, gold wire, etc. can be used. Wire bonding is, for example, For example, ball bonding or wedge bonding can be used.

[0542] The wire-bonded chip 715 is sealed with epoxy resin or the like in the "sealing process." The electronic components are then sealed in a mold (step S725). The inside of the chip 715 is filled with resin, and the wires connecting the chip 715 and the leads are protected from mechanical external forces. This can protect the device and reduce deterioration of characteristics (reduced reliability) caused by moisture, dust, etc. This can be done.

[0543] Next, a "lead plating process" is carried out to plate the leads of the lead frame (step (Step S726). The plating process prevents the leads from rusting and is used later for mounting on a printed circuit board. The leads are then cut and shaped. Then, a "molding process" is carried out (step S727).

[0544] Next, a "marking process" is carried out to print (mark) the surface of the package. Then, the "inspection section" checks whether the external appearance is good, whether there is a malfunction, etc. (step S728). After going through the "process" (step S729), the electronic component is completed.

[0545] A perspective schematic diagram of the completed electronic component is shown in FIG. As an example of a component, a schematic perspective view of a QFP (Quad Flat Package) is shown below. The electronic component 750 shown in FIG. 39(B) has leads 755 and a chip 715. The electronic component 750 may include multiple chips 715.

[0546] The electronic component 750 shown in FIG. 39(B) is mounted on, for example, a printed circuit board 752. A plurality of such electronic components 750 are assembled together, and each is electrically connected to a printed circuit board 752. The completed board (mounted board 754) is then completed. The mounting board 754 is used in electronic devices and the like.

[0547] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0548] (Embodiment 7) <Electronic equipment> The semiconductor device according to one embodiment of the present invention can be used in various electronic devices. Specific examples of electronic devices using a semiconductor device according to one embodiment of the present invention will be described.

[0549] FIG. 40(A) is an external view showing an example of an automobile. The automobile 2980 has a body 2981. 2982, a dashboard 2983, and lights 2984. The vehicle 2980 is equipped with an antenna, a battery, etc.

[0550] The information terminal 2910 shown in FIG. 40(B) includes a housing 2911, a display unit 2912, a microphone 29 17, speaker unit 2914, camera 2913, external connection unit 2916, and operation switch The display unit 2912 includes a display panel and a touch panel using a flexible substrate. The information terminal 2910 also includes an antenna, The information terminal 2910 is, for example, a smartphone, a mobile phone, a tablet, Used as a notebook type information terminal, tablet type personal computer, e-book terminal, etc. It is possible.

[0551] A notebook personal computer 2920 shown in FIG. 40(C) includes a housing 2921, a display 2922, a keyboard 2923, and a pointing device 2924. The notebook personal computer 2920 is provided with an antenna, a battery, and a It is equipped with a battery, etc.

[0552] The video camera 2940 shown in FIG. 40(D) ​​includes a housing 2941, a housing 2942, a display unit 2 943, an operation switch 2944, a lens 2945, and a connection part 2946. The operation switch 2944 and the lens 2945 are provided in the housing 2941. 43 is provided in a housing 2942. Also, a video camera 2940 is provided in a housing 2941. An antenna, a battery, etc. are provided inside. The housing 2941 and the housing 2942 are connected. The angle between the housing 2941 and the housing 2942 is the angle between the housing 2941 and the housing 2942 at the connection part 2946. The structure can be changed by the housing 2942 relative to the housing 2941. Depending on the angle, the orientation of the image displayed on the display unit 2943 can be changed, and the image can be displayed / hidden. It is possible to switch between the above.

[0553] FIG. 40E shows an example of a bangle-type information terminal. The information terminal 2950 includes a display unit 2952 and the like. The display unit 2952 is supported by a curved housing 2951. The display unit 2952 is provided with a display panel using a flexible substrate. It is possible to provide an information terminal 2950 that is flexible, lightweight, and easy to use.

[0554] FIG. 40F shows an example of a wristwatch-type information terminal. The information terminal 2960 has a housing 2961. , display unit 2962, band 2963, buckle 2964, operation switch 2965, input / output The information terminal 2960 is provided with an antenna on the inside of the housing 2961. The information terminal 2960 is equipped with a mobile phone, electronic mail, text browsing, and writing. Various applications such as music playback, Internet communication, and computer games can be executed.

[0555] The display surface of the display unit 2962 is curved, and display can be performed along the curved display surface. The display unit 2962 is also equipped with a touch sensor, and can be used to touch the screen with a finger or a stylus. For example, the icon 2967 displayed on the display unit 2962 can be operated by By touching it, an application can be started. In addition to setting the time, you can also turn the power on and off, turn wireless communication on and off, and activate silent mode. It can have various functions such as turning on and off the power saving mode, turning on and off the power saving mode, etc. For example, the operating system installed in the information terminal 2960 controls the operation switch 2 You can also set the 965's functions.

[0556] In addition, the information terminal 2960 is capable of performing short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, hands-free communication is possible. The information terminal 2960 also has an input / output terminal 2966, and can communicate with other information terminals. Data can be exchanged directly through the terminal and connector. Charging can also be performed via the input / output terminal 2966. This may be achieved by wireless power supply.

[0557] For example, a memory device using the semiconductor device of one embodiment of the present invention can be used for the control information of the above-mentioned electronic devices. The semiconductor device according to one aspect of the present invention can store information, control programs, and the like for a long period of time. By using the device, highly reliable electronic equipment can be realized.

[0558] The configuration shown in this embodiment mode may be appropriately combined with the configurations described in other embodiment modes or examples. It is possible to implement these measures together. EXAMPLES

[0559] In this example, a semiconductor device according to one embodiment of the present invention is a transistor 4 shown in FIG. 00, a capacitance element 100, and a cell having a connection portion 160 are arranged in a matrix. The semiconductor device was then examined using a scanning transmission electron microscope (STEM). ning Transmission Electron Microscope The results of the observation using the semiconductor device fabricated in this example will be described. The transistor had a configuration similar to that of the transistor 400a shown in FIG.

[0560] The method of manufacturing the capacitor element 100 and the connection portion 160 will be described with reference to FIGS. For a method for manufacturing the transistor 400a, see the description in FIG. 21 and 22 can be taken into consideration.

[0561] First, the transistor 400a was fabricated. First, a thermally oxidized GaN substrate with a thickness of 400 nm was used. A silicon substrate on which a film was formed was prepared.

[0562] Next, as the insulator 401, an aluminum oxide film having a thickness of 40 nm was deposited by RF sputtering. A film of minium was formed.

[0563] Next, a silicon oxynitride film having a thickness of 150 nm is formed as an insulator 301 by using the PECVD method. Next, a conductor 310 is embedded in the insulator 301 by a damascene method. An opening was formed.

[0564] Next, a conductive film having a thickness of 40 nm was formed by sputtering to become the conductor 310a. Next, a tantalum nitride film having a thickness of 5 nm was formed as a conductive film to be the conductor 310b. A film was formed by laminating titanium nitride and tungsten with a thickness of 250 nm on top of it. The tungsten was deposited by metal CVD. Then, the conductive film is subjected to a CMP process to form a conductor 310a and a conductor 310b in the opening of the insulator 301. And a conductor 310b was formed.

[0565] Next, as the insulator 302, a silicon oxynitride film having a thickness of 10 nm is formed by using the PECVD method. Next, a hafnium oxide film with a thickness of 20 nm was formed as the insulator 303 by the ALD method. Next, a 30 nm thick oxide film was formed as the insulator 402 by using the PECVD method. A silicon nitride film was formed.

[0566] Next, a heat treatment was performed at 400° C. for 1 hour in an oxygen atmosphere.

[0567] Next, a 5 nm thick In-Ga oxide film 406A was formed by DC sputtering. The oxide film 406A was formed using a mixture of In:Ga:Zn=1: A 3:4 atomic ratio target was used, and 45 sccm of oxygen gas was used as the deposition gas. The membrane pressure was 0.7 Pa (measured using a miniature gauge MG-2 manufactured by Canon Anelva). ), the deposition power was 500 W, the substrate temperature was 200 °C, and the target-substrate distance was It was set to 60mm.

[0568] Furthermore, without exposing to the outside air, the oxide film 406B was formed by DC sputtering. The In-Ga-Zn oxide film was deposited to a thickness of 15 nm. The target was In:Ga:Zn=4:2:4.1 [atomic ratio], and the deposition gas was A. The deposition pressure was 0.7 Pa (capacity 1000 MPa). The measurement was performed using a miniature gauge MG-2 manufactured by Non-Anelva. The substrate temperature was 130° C., and the target-substrate distance was 60 mm.

[0569] Next, heat treatment was performed in a nitrogen atmosphere at 400°C for 1 hour, and then in an oxygen atmosphere at 400°C for 1 hour. A heat treatment was performed for 1 hour.

[0570] Next, a conductive film that will become the conductors 416a1 and 416a2 is formed by DC sputtering. A tantalum nitride film having a thickness of 20 nm was formed using this method.

[0571] Next, a film having a thickness of 5 nm is deposited by the ALD method to become the barrier films 417a1 and 417a2. A 100 mm thick aluminum oxide film was formed.

[0572] Next, a conductor that functions as a hard mask is deposited using a DC sputtering method. A 15 nm tantalum nitride film was deposited.

[0573] Next, the oxide film 406A, the oxide film 406B, and the conductive film that will become the conductors 416a1 and 416a2 are , and the films to be the barrier films 417a1 and 417a2 are dry-etched to remove the oxide 40 6a, oxide 406b, conductor 416a1, conductor 416a2, barrier film 417a1, and A barrier film 417a2 was formed.

[0574] Next, a 5 nm thick In-GaAs oxide film 406C was formed by DC sputtering. The oxide film 406C was formed using a mixture of In:Ga:Zn=1: A 3:2 [atomic ratio] target was used, and 45 sccm of oxygen gas was used as the deposition gas. The membrane pressure was 0.7 Pa (measured using a miniature gauge MG-2 manufactured by Canon Anelva). ), the deposition power was 500 W, the substrate temperature was 130 °C, and the target-substrate distance was It was set to 60mm.

[0575] Next, a silicon oxynitride film having a thickness of 10 nm is formed as the insulating film 412A by using the PECVD method. A film was formed.

[0576] Next, a conductive film having a thickness of 100 nm was formed by DC sputtering to form the conductive body 404b. A titanium nitride film having a thickness of nm was then formed. A tungsten film having a thickness of 30 nm was formed by a deposition method. A conductor corresponding to conductor 404a of 0a is not formed in this embodiment.

[0577] Next, a conductive film that will become the conductor 404b and the conductor 4 The conductive film that becomes 04c is processed to form conductors 404b and 404c.

[0578] Next, a 7 nm thick aluminum oxide film was deposited by ALD to form a barrier film 418. A film of Zn was formed.

[0579] Next, a film to be the barrier film 418, an insulating film 412A, and and the oxide film 406C is processed to form a barrier film 418, an insulator 412, and a conductor 404c. Formed.

[0580] Next, a silicon oxynitride film having a thickness of 310 nm is deposited as the insulator 410 by using the PECVD method. Then, the insulator 410 was subjected to CMP processing to flatten the upper surface of the insulator 410. It has become.

[0581] Next, as the insulator 420, an aluminum oxide film having a thickness of 40 nm was deposited by RF sputtering. The deposition gas was argon gas at 25 sccm and oxygen gas at 2 The deposition pressure was set to 0.4 Pa, the deposition power to 2500 W, and the substrate temperature to The temperature was 250° C. and the target-substrate distance was 60 mm.

[0582] Next, a heat treatment was carried out at 350° C. for 1 hour in an oxygen atmosphere.

[0583] Next, as the insulator 410, a silicon oxynitride film having a thickness of 100 nm is formed by using the PECVD method. A film was formed.

[0584] Next, a photolithography method using a hard mask is performed to form a layer that reaches the conductor 416a1. An opening reaching the conductor 416a1 and an opening reaching the conductor 416a2 were formed.

[0585] Next, as a conductive film for the conductors 108a and 108b, titanium nitride having a thickness of 20 nm and A 150 nm thick tungsten film was then formed on top of the titanium nitride. The tungsten film was formed using the metal CVD method. The film is CMP processed to form an opening reaching the conductor 416a1 and a hole reaching the conductor 416a2. A conductor 108a and a conductor 108b are formed inside the opening.

[0586] In this manner, the transistor 400a was formed. Next, a capacitance element was formed as follows. 100 were made.

[0587] First, silicon oxide having a thickness of 250 nm is deposited as the insulator 112 by using the PECVD method. The insulator 112 was formed using ...

Claims

1. A semiconductor layer; a first insulating layer having a recess on the semiconductor layer; a first conductive layer electrically connected to the semiconductor layer and penetrating the first insulating layer; a second insulating layer located on the first insulating layer and having an opening; a second conductive layer having a region in contact with an inner wall of the opening, a region in contact with the recess, a region in contact with an upper surface of the first conductive layer, and a region not in contact with the upper surface of the first conductive layer; the opening has a region overlapping the recess and a region overlapping the first conductive layer, the first conductive layer has a curved surface portion in a region where the second conductive layer contacts an upper surface of the first conductive layer; In a region where the second conductive layer is not in contact with an upper surface of the first conductive layer, the first conductive layer does not have a curved surface portion; The curved surface portion is located above an upper surface of the first insulating layer.

2. In claim 1, the second insulating layer includes a third insulating layer and a fourth insulating layer disposed on the third insulating layer; one of the third insulating layer and the fourth insulating layer has a compressive stress; The other of the third insulating layer and the fourth insulating layer has a tensile stress.

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