Display device

Abstract

To provide a display device in which cracks of a substrate and an inorganic layer generated at an outer peripheral area of the display device are reduced.SOLUTION: The display device comprises a first substrate that comprises: a first substrate which includes a display area having a plurality of sub-pixels and a non-display area enclosing the display area and is formed of one of transparent conducting oxide and an oxide semiconductor; an inorganic layer disposed on the first substrate; a planarization layer disposed on the inorganic layer; a bank disposed on the planarization layer; an adhesive layer disposed on the inorganic layer, the planarization layer, and the bank; and a second substrate disposed on the adhesive layer. The bank includes a first bank disposed in an area overlapping the first substrate and a second bank disposed to enclose the first bank, the inorganic layer, the planarization layer, and a side surface of the first substrate. Therefore, the display device may improve a moisture permeation characteristic and may reduce cracks generated at an outer peripheral area.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a display device, and more particularly, to a display device that does not use a plastic substrate, has improved moisture permeability, and reduces crack generation in an outer periphery region. [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light emitting displays (OLEDs), which emit light themselves, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Display devices are now used in a wide variety of applications, including not only computer monitors and TVs but also personal portable devices. Research is currently underway into display devices that have a large display area while being reduced in volume and weight.

[0004] In recent years, flexible display devices that are manufactured by forming display elements, wiring, etc. on a flexible substrate such as plastic, which is a flexible material, and are capable of displaying images even when folded or rolled up, have been attracting attention as the next generation of display devices. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device using one of a transparent conductive oxide layer and an oxide semiconductor layer as a substrate instead of a plastic substrate.

[0006] Another object of the present invention is to provide a display device in which cracks occurring in a substrate and an inorganic layer at an outer periphery of the display device are reduced.

[0007] It is still another object of the present invention to provide a display device having a reduced bezel area by removing a sealing member.

[0008] The object of the present invention is not limited to the above-mentioned objects, and other objects not mentioned herein will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0009] In order to solve the above-mentioned problems, a display device according to an embodiment of the present invention includes a display area including a plurality of sub-pixels and a non-display area surrounding the display area, and includes a first substrate made of one of a transparent conductive oxide and an oxide semiconductor, an inorganic layer disposed on the first substrate, a planarization layer disposed on the inorganic layer, a bank disposed on the planarization layer, an adhesive layer disposed on the inorganic layer, the planarization layer and the bank, and a second substrate disposed on the adhesive layer, and the bank includes a first bank disposed in an area overlapping with the first substrate, and a second bank disposed to surround sides of the first bank, the inorganic layer, the planarization layer and the first substrate. Therefore, the moisture permeability of the display device is improved, and the occurrence of cracks in an outer region can be reduced.

[0010] Further details of the embodiments are included in the detailed description and the drawings. Effect of the Invention

[0011] The present invention can easily control moisture permeability and improve flexibility by using a transparent conductive oxide layer and an oxide semiconductor layer as a substrate of a display device.

[0012] In the present invention, the banks are disposed on the outer side of the first substrate, making it possible to easily separate the temporary substrate.

[0013] The present invention can reduce cracks occurring in the inorganic layer and the first substrate from the outer periphery of the display device, thereby improving the reliability of the display device.

[0014] According to the present invention, the non-display area can be reduced by removing the sealing material disposed on the outer periphery of the display device.

[0015] The effects of the present invention are not limited to the above-mentioned examples, and various other effects are included within the scope of the present invention. [Brief description of the drawings]

[0016] [Figure 1] 1 is a plan view of a display device according to an embodiment of the present invention; [Diagram 2] 1 is a schematic cross-sectional view of a display device according to an embodiment of the present invention; [Diagram 3] 1 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present invention. [Figure 4] 1 is an enlarged plan view of a display device according to an embodiment of the present invention; [Diagram 5] 5 is a cross-sectional view taken along the line VV' in FIG. [Figure 6a] 5A to 5C are cross-sectional views illustrating a manufacturing process of a display device according to an embodiment of the present invention. [Figure 6b] 1 is a cross-sectional view of a display device according to an embodiment of the present invention. [Figure 7a] 5A to 5C are cross-sectional views illustrating a manufacturing process of a display device according to another embodiment of the present invention. [Figure 7b] FIG. 11 is a cross-sectional view of a display device according to another embodiment of the present invention. [Figure 8a] 5A to 5C are cross-sectional views illustrating a manufacturing process of a display device according to still another embodiment of the present invention. [Figure 8b] 11 is a cross-sectional view of a display device according to still another embodiment of the present invention. [Figure 9a] 5A to 5C are cross-sectional views illustrating a manufacturing process of a display device according to still another embodiment of the present invention. [Figure 9b] 11 is a cross-sectional view of a display device according to still another embodiment of the present invention. [Figure 10a] 5A to 5C are cross-sectional views illustrating a manufacturing process of a display device according to still another embodiment of the present invention. [Figure 10b]11 is a cross-sectional view of a display device according to still another embodiment of the present invention. [Figure 11a] 5A to 5C are cross-sectional views illustrating a manufacturing process of a display device according to still another embodiment of the present invention. [Figure 11b] 11 is a cross-sectional view of a display device according to still another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The advantages and features of the present invention, as well as the methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms, and the embodiments are provided solely for the purpose of making the disclosure of the present invention complete and fully conveying the scope of the invention to those skilled in the art to which the present invention pertains.

[0018] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, and the present invention is not limited to the illustrated matters. The same reference symbols refer to the same components throughout the specification. In addition, when describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When "includes," "has," "is made," etc. are used in the present invention, other parts may be added since "only" is not used. When a component is expressed in the singular, it includes the plural unless otherwise explicitly stated.

[0019] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0020] When describing a positional relationship, for example when describing the positional relationship of two parts using "on top of," "at the top of," "at the bottom of," "next to," etc., since "immediately" or "directly" is not used, one or more other parts may be located between the two parts.

[0021] When an element or layer is referred to as "on" another element or layer, this includes the case where the element or layer is directly on top of the other element, or has other layers or elements interposed therebetween.

[0022] In addition, although the terms "first", "second" and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical concept of the present invention.

[0023] Like reference numbers refer to like elements throughout the specification.

[0024] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the area and thickness of the components shown.

[0025] The respective features of the various embodiments of the present invention may be partially or fully combined or combined with each other, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0026] Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0027] Fig. 1 is a plan view of a display device according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view of the display device according to an embodiment of the present invention. For convenience of explanation, Fig. 1 shows only a first substrate 101, a plurality of flexible films 160, and a plurality of printed circuit boards 170 among various components of a display device 100.

[0028] 1 and 2, the first substrate 101 is a support member for supporting other components of the display device 100. The first substrate 101 may be made of any one of a transparent conductive oxide and an oxide semiconductor. For example, the first substrate 101 may be made of a transparent conducting oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (ITZO), etc.

[0029] Also, the first substrate 101 may be made of an oxide semiconductor material made of indium (In) and gallium (Ga), for example, a transparent oxide semiconductor such as indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), etc. However, the types of transparent conductive oxides and oxide semiconductors are merely examples, and the first substrate 101 may be made of other transparent conductive oxides and oxide semiconductor materials not described herein, and is not limited thereto.

[0030] Meanwhile, the first substrate 101 may be formed by depositing a transparent conductive oxide or an oxide semiconductor to a thin thickness. Thus, the first substrate 101 may have flexibility by being formed to a thin thickness. In addition, the display device 100 including the first substrate 101 having flexibility may be embodied as a flexible display device 100 that can display an image even if it is folded or rolled up. For example, if the display device 100 is a foldable display device, the first substrate 101 may be folded or unfolded around a folding axis. As another example, if the display device 100 is a rollable display device, the display device may be stored by being rolled up on a roller. Thus, the display device 100 according to an embodiment of the present invention may be embodied as a flexible display device 100 such as a foldable display device or a rollable display device using the first substrate 101 having flexibility.

[0031] In addition, the display device 100 according to an embodiment of the present invention may perform a laser lift off (LLO) process using the first substrate 101 formed of a transparent conductive oxide or oxide semiconductor. The LLO process refers to a process of separating the first substrate 101 from a temporary substrate below the first substrate 101 using a laser during the manufacturing process of the display device 100. Thus, the first substrate 101 may also be referred to as a functional thin film, a functional thin film layer, a functional substrate, etc., in that it is a layer for an easier LLO process. The LLO process will be described in more detail below.

[0032] The first substrate 101 includes a display area AA and a non-display area NA.

[0033] The display area AA is an area for displaying an image. In order to display an image, a pixel unit 120 consisting of a plurality of sub-pixels may be disposed in the display area AA. For example, the pixel unit 120 may be composed of a plurality of sub-pixels each including a light emitting element and a driving circuit, and may display an image.

[0034] The non-display area NA is an area where no image is displayed, and is an area where various wirings, driving ICs, etc. for driving the sub-pixels arranged in the display area AA are arranged. For example, various driving ICs such as gate driver ICs and data driver ICs may be arranged in the non-display area NA.

[0035] A plurality of flexible films 160 are disposed at one end of the first substrate 101. The plurality of flexible films 160 are electrically connected to one end of the first substrate 101. The plurality of flexible films 160 are films in which various components are disposed on a ductile base film, and which supply signals to a plurality of sub-pixels in the display area AA. The plurality of flexible films 160 have one end disposed in the non-display area NA of the first substrate 101, and can supply data voltages, etc. to a plurality of sub-pixels in the display area AA. Meanwhile, although the number of the plurality of flexible films 160 is illustrated as four in FIG. 1, the number of the plurality of flexible films 160 may be variously changed according to a design, and is not limited thereto.

[0036] Meanwhile, driving ICs such as gate driver ICs and data driver ICs may be disposed on the flexible films 160. The driving IC is a component that processes data for displaying an image and driving signals for processing the data. The driving IC may be disposed in a manner such as chip on glass (COG), chip on film (COF), tape carrier package (TCP), etc., depending on a mounting method. For convenience of explanation, the present specification has been described as a chip on film type in which the driving IC is mounted on the flexible films 160, but the present invention is not limited thereto.

[0037] The printed circuit board 170 is connected to the plurality of flexible films 160. The printed circuit board 170 is a component that supplies signals to the driving IC. Various components for supplying various driving signals, such as driving signals and data voltages, to the driving IC may be disposed on the printed circuit board 170. Meanwhile, although FIG. 1 shows two printed circuit boards 170, the number of printed circuit boards 170 may be variously changed according to design and is not limited thereto.

[0038] 2, an inorganic layer 110 is disposed on a first substrate 101. The inorganic layer 110 may be a plurality of inorganic layers including a lower buffer layer 116, an upper buffer layer 111, a gate insulating layer 112, and a passivation layer 113, which will be described later. The inorganic layer 110 will be described in detail later with reference to FIGS. 4 to 6b.

[0039] A bank 115 is disposed on the inorganic layer 110. The bank 115 may be disposed to surround the first substrate 101 in the non-display area NA. A more detailed description of the bank 115 will be provided below in detail with reference to Figures 4 to 6b.

[0040] The pixel unit 120 is disposed on the inorganic layer 110. The pixel unit 120 may be disposed to correspond to the display area AA. The pixel unit 120 includes a plurality of sub-pixels to display an image. The plurality of sub-pixels of the pixel unit 120 are the minimum units constituting the display area AA, and a light emitting element and a driving circuit may be disposed in each of the plurality of sub-pixels. For example, the light emitting element of each of the plurality of sub-pixels may include, but is not limited to, an organic light emitting element including an anode, an organic light emitting layer, and a cathode, or an LED including an N-type and P-type semiconductor layer and a light emitting layer. The driving circuit for driving the plurality of sub-pixels may include, but is not limited to, a driving element such as a thin film transistor and a storage capacitor. In the following description, for convenience of explanation, it is assumed that the light emitting element of each of the plurality of sub-pixels is an organic light emitting element, but is not limited to this.

[0041] Meanwhile, the display device 100 may be configured in a top emission or bottom emission manner depending on the direction in which light emitted from the light emitting elements is emitted.

[0042] The top emission type is a type in which light emitted from the light emitting element is emitted to the upper part of the first substrate 101 on which the light emitting element is disposed. In the case of the top emission type, a reflective layer may be formed under the anode in order to cause the light emitted from the light emitting element to proceed to the upper part of the first substrate 101, i.e., to the cathode side.

[0043] In the bottom emission type, light emitted from the light emitting element is emitted to the bottom of the first substrate 101 on which the light emitting element is disposed. In the bottom emission type, in order to cause the light emitted from the light emitting element to travel to the bottom of the first substrate 101, the anode may be made of only a transparent conductive material, and the cathode may be made of a metal material with high reflectivity.

[0044] In the following description, for convenience of explanation, it is assumed that the display device 100 according to the embodiment of the present invention is a bottom emission type display device, but the present invention is not limited thereto.

[0045] The adhesive layer 130 is disposed to cover the pixel unit 120. The adhesive layer 130 functions to adhere the first substrate 101 and the second substrate 140, and seals the pixel unit 120 to protect the light emitting element of the pixel unit 120 from external moisture, oxygen, impact, etc. The adhesive layer 130 may be configured in a face seal manner. For example, the adhesive layer 130 may be formed by applying an ultraviolet or heat curing sealant to the front surface of the pixel unit 120. However, the structure of the adhesive layer 130 may be formed in various manners and materials, and is not limited thereto.

[0046] Meanwhile, the second substrate 140 made of a metal material having a high modulus and strong corrosion resistance is disposed on the adhesive layer 130. For example, the second substrate 140 may be made of a material having a high modulus of about 200 to 900 MPa, and may be made of a metal material such as aluminum (Al), nickel (Ni), chromium (Cr), or an alloy material of iron (Fe) and nickel, which is highly corrosion resistant and can be easily processed into a foil or thin film. Thus, by forming the second substrate 140 from a metal material, the second substrate 140 can be realized in an ultra-thin film form, and strong protection against external impacts and scratches can be provided.

[0047] A polarizing plate 150 is disposed under the first substrate 101. The polarizing plate 150 selectively transmits light and can reduce reflection of external light incident on the first substrate 101. Specifically, in the display device 100, various metal materials applied to semiconductor elements, wiring, light emitting elements, etc. are formed on the first substrate 101. Thus, external light incident on the first substrate 101 side may be reflected from the metal materials, and the visibility of the display device 100 may be reduced due to the reflection of the external light. In this case, the polarizing plate 150 that prevents reflection of external light may be disposed under the first substrate 101 to improve the outdoor visibility of the display device 100. However, the polarizing plate 150 may be omitted depending on the embodiment of the display device 100.

[0048] Meanwhile, although not shown in the drawing, a barrier film may be disposed together with the polarizer 150 under the first substrate 101. The barrier film may protect the pixel unit 120 including the light emitting element by minimizing the penetration of moisture and oxygen from the outside of the first substrate 101 into the first substrate 101. However, the barrier film may be omitted depending on the embodiment of the display device 100, and is not limited thereto.

[0049] In the following, for a more detailed description of the sub-pixels of the pixel portion 120, reference will be made to both FIGS.

[0050] FIG. 3 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present invention.

[0051] 3, a driving circuit for driving a light emitting element OLED of a plurality of sub-pixels SP includes a first transistor TR1, a second transistor TR2, a third transistor TR3, and a storage capacitor SC. In order to drive the driving circuit, a plurality of wirings including a gate line GL, a data line DL, a high potential power line VDD, a sensing line SL, and a reference line RL are arranged on a first substrate 101.

[0052] Each of a first transistor TR1, a second transistor TR2 and a third transistor TR3 included in a driving circuit of one sub-pixel SP includes a gate electrode, a source electrode and a drain electrode.

[0053] The first transistor TR1, the second transistor TR2, and the third transistor TR3 may be P-type thin film transistors or N-type thin film transistors. For example, in a P-type thin film transistor, holes flow from a source electrode to a drain electrode, so that a current can flow from the source electrode to the drain electrode. In an N-type thin film transistor, electrons flow from a source electrode to a drain electrode, so that a current can flow from the drain electrode to the source electrode. In the following description, it is assumed that the first transistor TR1, the second transistor TR2, and the third transistor TR3 are N-type thin film transistors in which a current flows from a drain electrode to a source electrode, but the present invention is not limited thereto.

[0054] The first transistor TR1 includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is connected to a first node N1, the first source electrode is connected to an anode of the light emitting element OLED, and the first drain electrode is connected to a high potential power line VDD. The first transistor TR1 may be turned on when the voltage of the first node N1 is higher than a threshold voltage, and may be turned off when the voltage of the first node N1 is lower than the threshold voltage. When the first transistor TR1 is turned on, a driving current may be transferred to the light emitting element OLED through the first transistor TR1. Thus, the first transistor TR1 that controls the driving current transferred to the light emitting element OLED may also be referred to as a driving transistor.

[0055] The second transistor TR2 includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is connected to the gate line GL, the second source electrode is connected to the first node N1, and the second drain electrode is connected to the data line DL. The second transistor TR2 can be turned on or off based on a gate voltage from the gate line GL. When the second transistor TR2 is turned on, the data voltage from the data line DL can be charged to the first node N1. Therefore, the second transistor TR2 that is turned on or off by the gate line GL can also be called a switching transistor.

[0056] The third transistor TR3 includes a third active layer, a third gate electrode, a third source electrode, and a third drain electrode. The third gate electrode is connected to the sensing line SL, the third source electrode is connected to the second node N2, and the third drain electrode is connected to the reference line RL. The third transistor TR3 may be turned on or off based on a sensing voltage from the sensing line SL. When the third transistor TR3 is turned on, the third transistor TR3 may transmit a reference voltage from the reference line RL to the second node N2 and the storage capacitor SC. Therefore, the third transistor TR3 may also be referred to as a sensing transistor.

[0057] Meanwhile, in FIG. 3, the gate line GL and the sensing line SL are shown as separate lines, but the gate line GL and the sensing line SL may be embodied as one line and are not limited thereto.

[0058] The storage capacitor SC is connected between the first gate electrode and the first source electrode of the first transistor TR1. That is, the storage capacitor SC may be connected between the first node N1 and the second node N2. The storage capacitor SC may maintain a potential difference between the first gate electrode and the first source electrode of the first transistor TR1 while the light emitting element OLED emits light, thereby allowing a constant driving current to be supplied to the light emitting element OLED. The storage capacitor SC may include a plurality of capacitor electrodes, and, for example, one of the plurality of capacitor electrodes may be connected to the first node N1 and the other may be connected to the second node N2.

[0059] The light emitting element OLED includes an anode, a light emitting layer, and a cathode. The anode of the light emitting element OLED is connected to the second node N2, and the cathode is connected to the low potential power line VSS. The light emitting element OLED emits light by receiving a driving current from the first transistor TR1.

[0060] Meanwhile, in FIG. 3, the driving circuit of the sub-pixel SP of the display device 100 according to one embodiment of the present invention is described as having a 3T1C structure including three transistors and one storage capacitor SC, but the number and connection relationship of the transistors and storage capacitor SC may be variously changed depending on the design and is not limited thereto.

[0061] FIG. 4 is an enlarged plan view of a display device according to an embodiment of the present invention. FIG. 5 is a cross-sectional view taken along line V-V' in FIG. 4. FIG. 6a is a cross-sectional view for explaining a manufacturing process of a display device according to an embodiment of the present invention. FIG. 6b is a cross-sectional view of a display device according to an embodiment of the present invention at a step before an LLO process. FIG. 4 is an enlarged plan view of a red sub-pixel SPR, a white sub-pixel SPW, a blue sub-pixel SPB, and a green sub-pixel SPG constituting one pixel. In FIG. 4, for convenience of explanation, the bank 115 is omitted, and the frames of a plurality of color filters CF are indicated by thick solid lines. FIGS. 6a and 6b are cross-sectional views taken along line VI-VI' in FIG. 1, and FIG. 6a is a cross-sectional view showing a state before an LLO process is performed during a manufacturing process of a display device according to an embodiment of the present invention. 4 to 6b, a display device 100 according to an embodiment of the present invention includes a first substrate 101, an inorganic layer 110, a planarization layer 114, a bank 115, a first transistor TR1, a second transistor TR2, a third transistor TR3, a storage capacitor SC, a light emitting device OLED, a gate line GL, a sensing line SL, a data line DL, a reference line RL, a high potential power line VDD, a plurality of color filters CF, an adhesive layer 130, and a second substrate 140.

[0062] 4, the subpixels SP include a red subpixel SPR, a green subpixel SPG, a blue subpixel SPB, and a white subpixel SPW. For example, the red subpixel SPR, the white subpixel SPW, the blue subpixel SPB, and the green subpixel SPG may be sequentially arranged in the row direction. However, the arrangement order of the subpixels SP is not limited thereto.

[0063] Each of the sub-pixels SP includes a light-emitting region and a circuit region. The light-emitting region is a region that can independently emit light of one color, and a light-emitting element OLED may be disposed in the light-emitting region. Specifically, a region exposed from the bank 115 in a region where the color filters CF and the anode AN overlap each other and through which light emitted from the light-emitting element OLED can travel to the outside may be defined as the light-emitting region. For example, referring to both FIG. 4 and FIG. 5, the light-emitting region of the red sub-pixel SPR may be a region exposed from the bank 115 in a region where the red color filter CFR and the anode AN overlap, the light-emitting region of the green sub-pixel SPG may be a region exposed from the bank 115 in a region where the green color filter CFG and the anode AN overlap, and the light-emitting region of the blue sub-pixel SPB may be a blue light-emitting region that emits blue light and is exposed from the bank 115 in a region where the blue color filter CF and the anode AN overlap. In this case, the light-emitting region of the white sub-pixel SPW in which a separate color filter CF is not disposed may be a white light-emitting region that emits white light and overlaps with a portion of the anode AN exposed from the bank 115.

[0064] The circuit region is the remaining region excluding the light-emitting region, and may include a driving circuit DP for driving a plurality of light-emitting elements OLED and a plurality of wirings for transmitting various signals to the driving circuit DP. The circuit region in which the driving circuit DP, the plurality of wirings, and the bank 115 are arranged may be a non-light-emitting region. For example, the circuit region may include a driving circuit DP including a first transistor TR1, a second transistor TR2, a third transistor TR3, and a storage capacitor SC, a plurality of high potential power supply wirings VDD, a plurality of data wirings DL, a plurality of reference wirings RL, a plurality of gate wirings GL, a sensing wiring SL, and the bank 115.

[0065] 3 to 6b, an inorganic layer 110 is disposed on a first substrate 101. The inorganic layer 110 may include a plurality of layers made of inorganic materials disposed on the first substrate 101. For example, the inorganic layer 110 may include, but is not limited to, a lower buffer layer 116, an upper buffer layer 111, a gate insulating layer 112, and a passivation layer 113. The inorganic layer 110 may be disposed so as to expose an end of the first substrate 101. For example, the end of the inorganic layer 110 may be disposed inside the end of the first substrate 101. However, without being limited thereto, the end of the inorganic layer 110 may coincide with the end of the first substrate 101.

[0066] A lower buffer layer 116 is disposed on the first substrate 101. The lower buffer layer 116 can prevent moisture and / or oxygen that has penetrated from the outside of the first substrate 101 from diffusing. The moisture permeability of the display device 100 can be controlled by controlling the thickness and stacking structure of the lower buffer layer 116. In addition, the lower buffer layer 116 can prevent the first substrate 101 made of a transparent conductive oxide or oxide semiconductor from coming into contact with other components such as the pixel unit 120, causing a short circuit. The lower buffer layer 116 can be made of an inorganic material, and can be, for example, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0067] On the lower buffer layer 116, a plurality of high potential power supply lines VDD, a plurality of data lines DL, a plurality of reference lines RL, and a light shielding layer LS are arranged.

[0068] The high potential power supply wirings VDD, the data wirings DL, the reference wirings RL, and the light shielding layer LS may be disposed in the same layer on the first substrate 101 and may be made of the same conductive material. For example, the high potential power supply wirings VDD, the data wirings DL, the reference wirings RL, and the light shielding layer LS may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0069] The multiple high potential power supply wirings VDD are wirings that transmit a high potential power supply voltage to each of the multiple subpixels SP. The multiple high potential power supply wirings VDD may extend in the column direction between the multiple subpixels SP, and two subpixels SP adjacent to each other in the row direction may share one of the multiple high potential power supply wirings VDD. For example, one high potential power supply wiring VDD is disposed on the left side of the red subpixel SPR and can supply a high potential power supply voltage to the first transistor TR1 of each of the red subpixel SPR and the white subpixel SPW. The other high potential power supply wiring VDD is disposed on the right side of the green subpixel SPG and can supply a high potential power supply voltage to the first transistor TR1 of each of the blue subpixel SPB and the green subpixel SPG.

[0070] The data lines DL extend in the column direction between the subpixels SP and transmit data voltages to each of the subpixels SP. The data lines DL include a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4. The first data line DL1 is disposed between the red subpixel SPR and the white subpixel SPW and can transmit a data voltage to the second transistor TR2 of the red subpixel SPR. The second data line DL2 is disposed between the first data line DL1 and the white subpixel SPW and can transmit a data voltage to the second transistor TR2 of the white subpixel SPW. The third data line DL3 is disposed between the blue subpixel SPB and the green subpixel SPG and can transmit a data voltage to the second transistor TR2 of the blue subpixel SPB. The fourth data line DL4 is disposed between the third data line DL3 and the green subpixel SPG and can transmit a data voltage to the second transistor TR2 of the green subpixel SPG.

[0071] The multiple reference wirings RL extend in the column direction between the multiple subpixels SP and transmit a reference voltage to each of the multiple subpixels SP. The multiple subpixels SP constituting one pixel can share one reference wiring RL. For example, one reference wiring RL is disposed between the white subpixel SPW and the blue subpixel SPB, and can transmit a reference voltage to the third transistors TR3 of the red subpixel SPR, the white subpixel SPW, the blue subpixel SPB, and the green subpixel SPG.

[0072] 4 and 5, a light-shielding layer LS is disposed on the lower buffer layer 116. The light-shielding layer LS is disposed to overlap at least the first active layer ACT1 of the first transistor TR1 among the plurality of transistors TR1, TR2, and TR3, and can block light incident on the first active layer ACT1. If light is irradiated onto the first active layer ACT1, a leakage current occurs, and the reliability of the first transistor TR1, which is a driving transistor, may decrease. In this case, if the light-shielding layer LS made of an opaque conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof is disposed to overlap the first active layer ACT1, it can block light incident on the first active layer ACT1 under the first substrate 101, thereby improving the reliability of the first transistor TR1. However, without being limited thereto, the light-shielding layer LS may also be disposed to overlap the second active layer ACT2 of the second transistor TR2 and the third active layer ACT3 of the third transistor TR3.

[0073] Meanwhile, in the drawings, the light-shielding layer LS is shown as a single layer, but the light-shielding layer LS may be formed of multiple layers. For example, the light-shielding layer LS may be composed of multiple layers arranged to overlap each other between the inorganic layers 110, i.e., with at least one of the lower buffer layer 116, the upper buffer layer 111, the gate insulating layer 112, and the passivation layer 113 sandwiched therebetween.

[0074] An upper buffer layer 111 is disposed on the plurality of high potential power supply wirings VDD, the plurality of data wirings DL, the plurality of reference wirings RL, and the light shielding layer LS. The upper buffer layer 111 can reduce the penetration of moisture or impurities through the first substrate 101. For example, the upper buffer layer 111 can be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. Also, the upper buffer layer 111 may be omitted depending on the type of the first substrate 101 or the type of transistor, but is not limited thereto.

[0075] A first transistor TR1, a second transistor TR2, a third transistor TR3, and a storage capacitor SC are disposed on the upper buffer layer 111 in each of the sub-pixels SP.

[0076] First, the first transistor TR1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0077] The first active layer ACT1 is disposed on the upper buffer layer 111. The first active layer ACT1 may be made of a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon. For example, when the first active layer ACT1 is made of an oxide semiconductor, the first active layer ACT1 may include a channel region, a source region, and a drain region, and the source region and the drain region may be conductive regions, but are not limited to this.

[0078] A gate insulating layer 112 is disposed on the first active layer ACT1. The gate insulating layer 112 is a layer for insulating the first gate electrode GE1 and the first active layer ACT1, and may be made of an insulating material. For example, the gate insulating layer 112 may be made of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0079] The first gate electrode GE1 is disposed so as to overlap the first active layer ACT1 on the gate insulating layer 112. The first gate electrode GE1 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0080] A first source electrode SE1 and a first drain electrode DE1 are disposed on the gate insulating layer 112 and spaced apart from each other. The first source electrode SE1 and the first drain electrode DE1 may be electrically connected to the first active layer ACT1 through a contact hole formed in the gate insulating layer 112. The first source electrode SE1 and the first drain electrode DE1 may be disposed in the same layer as the first gate electrode GE1 and may be formed of the same conductive material, but are not limited thereto. For example, the first source electrode SE1 and the first drain electrode DE1 may be made of, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0081] The first drain electrode DE1 is electrically connected to a high potential power supply line VDD. For example, the first drain electrodes DE1 of the red subpixel SPR and the white subpixel SPW may be electrically connected to the high potential power supply line VDD on the left side of the red subpixel SPR. The first drain electrodes DE1 of the blue subpixel SPB and the green subpixel SPG may be electrically connected to the high potential power supply line VDD on the right side of the green subpixel SPG.

[0082] At this time, an auxiliary high potential power line VDDa may be further disposed to electrically connect the first drain electrode DE1 to the high potential power line VDD. One end of the auxiliary high potential power line VDDa may be electrically connected to the high potential power line VDD, and the other end of the auxiliary high potential power line VDDa may be electrically connected to the first drain electrodes DE1 of the sub-pixels SP. For example, when the auxiliary high potential power line VDDa is made of the same material as the first drain electrode DE1 in the same layer, one end of the auxiliary high potential power line VDDa may be electrically connected to the high potential power line VDD through a contact hole formed in the gate insulating layer 112 and the upper buffer layer 111, and the other end of the auxiliary high potential power line VDDa may extend to the first drain electrode DE1 side and be integrated with the first drain electrode DE1.

[0083] In this case, the first drain electrode DE1 of the red subpixel SPR and the first drain electrode DE1 of the white subpixel SPW, which are electrically connected to the same high potential power line VDD, may be connected to the same auxiliary high potential power line VDDa, and the first drain electrode DE1 of the blue subpixel SPB and the first drain electrode DE1 of the green subpixel SPG may also be connected to the same auxiliary high potential power line VDDa, but the first drain electrode DE1 and the high potential power line VDD may be electrically connected in other manners and are not limited thereto.

[0084] The first source electrode SE1 may be electrically connected to the light-shielding layer LS through a contact hole formed in the gate insulating layer 112 and the upper buffer layer 111. In addition, a portion of the first active layer ACT1 connected to the first source electrode SE1 may be electrically connected to the light-shielding layer LS through a contact hole formed in the upper buffer layer 111. If the light-shielding layer LS is floating, the threshold voltage of the first transistor TR1 may vary, which may affect the operation of the display device 100. Therefore, the light-shielding layer LS may be electrically connected to the first source electrode SE1 to apply a voltage to the light-shielding layer LS without affecting the operation of the first transistor TR1. However, although it has been described herein that both the first active layer ACT1 and the first source electrode SE1 are in contact with the light-shielding layer LS, the present invention is not limited thereto, and only one of the first source electrode SE1 and the first active layer ACT1 may be in direct contact with the light-shielding layer LS.

[0085] Meanwhile, in FIG. 5, the gate insulating layer 112 is shown to be formed on the front surface of the first substrate 101, but the gate insulating layer 112 may be patterned to overlap only the first gate electrode GE1, the first source electrode SE1, and the first drain electrode DE1, and is not limited thereto.

[0086] The second transistor TR2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0087] A second active layer ACT2 is disposed on the upper buffer layer 111. The second active layer ACT2 may be made of a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon. For example, when the second active layer ACT2 is made of an oxide semiconductor, the second active layer ACT2 may include a channel region, a source region, and a drain region, and the source region and the drain region may be conductive regions, but are not limited to this.

[0088] A second source electrode SE2 is disposed on the upper buffer layer 111. The second source electrode SE2 may be integrated with the second active layer ACT2 and electrically connected to each other. For example, a semiconductor material may be formed on the upper buffer layer 111, and a portion of the semiconductor material may be made conductive to form the second source electrode SE2. Thus, the portion of the semiconductor material that is not made conductive may become the second active layer ACT2, and the portion that is made conductive may become the second source electrode SE2. However, the second active layer ACT2 and the second source electrode SE2 may be formed separately, and are not limited thereto.

[0089] The second source electrode SE2 is electrically connected to the first gate electrode GE1 of the first transistor TR1. The first gate electrode GE1 may be electrically connected to the second source electrode SE2 through a contact hole formed on the gate insulating layer 112. Therefore, the first transistor TR1 may be turned on or off by a signal from the second transistor TR2.

[0090] A gate insulating layer 112 is disposed on the second active layer ACT2 and the second source electrode SE2, and a second drain electrode DE2 and a second gate electrode GE2 are disposed on the gate insulating layer 112.

[0091] A second gate electrode GE2 is disposed on the gate insulating layer 112 to overlap the second active layer ACT2. The second gate electrode GE2 may be electrically connected to the gate line GL, and the second transistor TR2 may be turned on or off based on a gate voltage transmitted to the second gate electrode GE2. The second gate electrode GE2 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0092] Meanwhile, the second gate electrode GE2 may extend from the gate line GL. That is, the second gate electrode GE2 may be integrated with the gate line GL, and the second gate electrode GE2 and the gate line GL may be formed of the same conductive material. For example, the gate line GL may be made of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0093] The gate line GL is a line that transmits a gate voltage to each of the sub-pixels SP, and may extend in the row direction across the circuit regions of the sub-pixels SP. The gate line GL is arranged to extend in the row direction and may intersect with the high potential power supply lines VDD, the data lines DL, and the reference lines RL that extend in the column direction.

[0094] The second drain electrode DE2 is disposed on the gate insulating layer 112. The second drain electrode DE2 may be electrically connected to the second active layer ACT2 through a contact hole formed in the gate insulating layer 112 and may be electrically connected to one of the data lines DL through a contact hole formed in the gate insulating layer 112 and the upper buffer layer 111. For example, the second drain electrode DE2 of the red subpixel SPR may be electrically connected to the first data line DL1, and the second drain electrode DE2 of the white subpixel SPW may be electrically connected to the second data line DL2. For example, the second drain electrode DE2 of the blue subpixel SPB may be electrically connected to the third data line DL3, and the second drain electrode DE2 of the green subpixel SPG may be electrically connected to the fourth data line DL4. The second drain electrode DE2 may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0095] The third transistor TR3 includes a third active layer ACT3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3.

[0096] A third active layer ACT3 is disposed on the upper buffer layer 111. The third active layer ACT3 may be made of a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon. For example, when the third active layer ACT3 is made of an oxide semiconductor, the third active layer ACT3 includes a channel region, a source region, and a drain region, and the source region and the drain region may be conductive regions, but are not limited to this.

[0097] A gate insulating layer 112 is disposed on the third active layer ACT3, and a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3 are disposed on the gate insulating layer 112.

[0098] A third gate electrode GE3 is disposed on the gate insulating layer 112 to overlap the third active layer ACT3. The third gate electrode GE3 may be electrically connected to the sensing line SL, and the third transistor TR3 may be turned on or off based on a sensing voltage transmitted to the third transistor TR3. The third gate electrode GE3 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0099] Meanwhile, the third gate electrode GE3 may extend from the sensing line SL. That is, the third gate electrode GE3 may be integrated with the sensing line SL, and the third gate electrode GE3 and the sensing line SL may be formed of the same conductive material. For example, the sensing line SL may be made of, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0100] The sensing line SL is a line that transmits a sensing voltage to each of the sub-pixels SP and extends in the row direction between the sub-pixels SP. For example, the sensing line SL may be extended in the row direction at the boundaries between the sub-pixels SP and intersect with the high potential power supply lines VDD, the data lines DL, and the reference lines RL that extend in the column direction.

[0101] The third source electrode SE3 may be electrically connected to the third active layer ACT3 through a contact hole formed in the gate insulating layer 112. The third source electrode SE3 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0102] Meanwhile, a portion of the third active layer ACT3 in contact with the third source electrode SE3 may be electrically connected to the light-shielding layer LS through a contact hole formed in the upper buffer layer 111. That is, the third source electrode SE3 may be electrically connected to the light-shielding layer LS with the third active layer ACT3 interposed therebetween. Therefore, the third source electrode SE3 and the first source electrode SE1 may be electrically connected to each other through the light-shielding layer LS.

[0103] The third drain electrode DE3 may be electrically connected to the third active layer ACT3 through a contact hole formed in the gate insulating layer 112. The third drain electrode DE3 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0104] The third drain electrode DE3 may be electrically connected to a reference line RL. For example, the third drain electrodes DE3 of the red subpixel SPR, the white subpixel SPW, the blue subpixel SPB, and the green subpixel SPG constituting one pixel may be electrically connected to the same reference line RL. That is, a plurality of subpixels SP constituting one pixel may share one reference line RL.

[0105] In this case, an auxiliary reference line RLa may be disposed to transmit the reference line RL extending in the column direction to the sub-pixels SP arranged side by side in the row direction. The auxiliary reference line RLa may extend in the row direction to electrically connect the reference line RL to the third drain electrodes DE3 of the sub-pixels SP. One end of the auxiliary reference line RLa may be electrically connected to the reference line RL through contact holes formed in the upper buffer layer 111 and the gate insulating layer 112. The other end of the auxiliary reference line RLa may be electrically connected to the third drain electrodes DE3 of the sub-pixels SP. In this case, the auxiliary reference line RLa may be integrated with the third drain electrodes DE3 of the sub-pixels SP, and a reference voltage from the reference line RL may be transmitted to the third drain electrode DE3 through the auxiliary reference line RLa. However, the auxiliary reference line RLa may be formed separately from the third drain electrode DE3, and is not limited thereto.

[0106] A storage capacitor SC is disposed in the circuit region of the sub-pixels SP. The storage capacitor SC stores a voltage between the first gate electrode GE1 and the first source electrode SE1 of the first transistor TR1 so that the light emitting element OLED continues to maintain the same state during one frame. The storage capacitor SC includes a first capacitor electrode SC1 and a second capacitor electrode SC2.

[0107] In each of the plurality of subpixels SP, a first capacitor electrode SC1 is disposed between the lower buffer layer 116 and the upper buffer layer 111. The first capacitor electrode SC1 may be disposed closest to the first substrate 101 among the conductive components disposed on the first substrate 101. The first capacitor electrode SC1 may be integrated with the light shielding layer LS and may be electrically connected to the first source electrode SE1 through the light shielding layer LS.

[0108] The upper buffer layer 111 is disposed on the first capacitor electrode SC1, and the second capacitor electrode SC2 is disposed on the upper buffer layer 111. The second capacitor electrode SC2 may be disposed to overlap the first capacitor electrode SC1. The second capacitor electrode SC2 may be integrated with the second source electrode SE2, and may be electrically connected to the first gate electrode GE1 as the second source electrode SE2. For example, a semiconductor material may be formed on the upper buffer layer 111, and a portion of the semiconductor material may be made conductive to form the second source electrode SE2 and the second capacitor electrode SC2. Thus, the portion of the semiconductor material that is not made conductive may function as the second active layer ACT2, and the portion that is made conductive may function as the second source electrode SE2, and may be the second capacitor electrode SC2. As described above, the first gate electrode GE1 is electrically connected to the second source electrode SE2 through a contact hole formed in the gate insulating layer 112. Thus, the second capacitor electrode SC2 may be integrated with the second source electrode SE2, and may be electrically connected to the second source electrode SE2 and the first gate electrode GE1.

[0109] In summary, the first capacitor electrode SC1 of the storage capacitor SC may be integrated with the light-shielding layer LS and electrically connected to the light-shielding layer LS, the first source electrode SE1, and the third source electrode SE3. The second capacitor electrode SC2 is the second source electrode SE2, which may be integrated with the second active layer ACT2 and electrically connected to the second source electrode SE2 and the first gate electrode GE1. Therefore, the first capacitor electrode SC1 and the second capacitor electrode SC2 overlapping with the upper buffer layer 111 sandwiched therebetween may keep the voltages of the first gate electrode GE1 and the first source electrode SE1 of the first transistor TR1 constant while the light-emitting element OLED emits light, thereby maintaining the light-emitting element OLED in the same state.

[0110] A passivation layer 113 is disposed on the first transistor TR1, the second transistor TR2, the third transistor TR3, and the storage capacitor SC. The passivation layer 113 is an insulating layer for protecting the components below the passivation layer 113. For example, the passivation layer 113 may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. Also, the passivation layer 113 may be omitted depending on the embodiment.

[0111] A plurality of color filters CF are disposed in the light emitting regions of the sub-pixels SP on the passivation layer 113. As described above, the display device 100 according to an embodiment of the present invention is a bottom emission type in which light emitted from the light emitting element OLED is directed toward the lower portion of the light emitting element OLED and the first substrate 101, so a plurality of color filters CF may be disposed below the light emitting element OLED. The light emitted from the light emitting element OLED passes through the plurality of color filters CF to be embodied as light of various colors.

[0112] The color filters CF include a red color filter CFR, a blue color filter CFB, and a green color filter CFG. The red color filter CFR may be disposed in an emission region of a red subpixel SPR among the subpixels SP, the blue color filter CFB may be disposed in an emission region of a blue subpixel SPB, and the green color filter CFG may be disposed in an emission region of a green subpixel SPG.

[0113] A planarization layer 114 is disposed on the passivation layer 113 and the plurality of color filters CF.

[0114] The planarization layer 114 is an insulating layer that planarizes an upper portion of the first substrate 101 on which the first transistor TR1, the second transistor TR2, the third transistor TR3, the storage capacitor SC, the plurality of high potential power supply lines VDD, the plurality of data lines DL, the plurality of reference lines RL, the plurality of gate lines GL, and the plurality of sensing lines SL are arranged. The planarization layer 114 may be made of an organic material, for example, an acrylic-based single layer or multiple layers, but is not limited thereto.

[0115] A light-emitting element OLED is disposed in the light-emitting region of each of the sub-pixels SP. A light-emitting element OLED is disposed on the planarization layer 114 of each of the sub-pixels SP. The light-emitting element OLED includes an anode AN, an emitting layer EL, and a cathode CA.

[0116] An anode AN is disposed on the planarization layer 114 in the light emitting region. The anode AN supplies holes to the light emitting layer EL and is made of a conductive material with a high work function, and may also be referred to as an anode AN. The anode AN may be made of a transparent conductive material such as, but not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0117] Meanwhile, the anode AN may extend toward the circuit region. A portion of the anode AN may extend from the light emitting region toward the first source electrode SE1 of the circuit region and may be electrically connected to the first source electrode SE1 through a contact hole formed in the planarization layer 114 and the passivation layer 113. Thus, the anode AN of the light emitting element OLED may extend to the circuit region and be electrically connected to the first source electrode SE1 of the first transistor TR1 and the second capacitor electrode SC2 of the storage capacitor SC.

[0118] An emitting layer EL is disposed on the anode AN in the emitting region and the circuit region. The emitting layer EL may be formed as one layer across the plurality of sub-pixels SP. That is, the emitting layers EL of the plurality of sub-pixels SP may be connected to each other to be integrated. The emitting layer EL may be composed of one emitting layer, or may have a structure in which a plurality of emitting layers emitting light of different colors are stacked. The emitting layer EL may further include organic layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0119] A cathode CA is disposed on the light-emitting layer EL in the light-emitting region and the circuit region. The cathode CA supplies electrons to the light-emitting layer EL and may be made of a conductive material with a low work function. The cathode CA may be formed as one layer across the sub-pixels SP. That is, the cathodes CA of the sub-pixels SP may be connected to each other and integrated. The cathode CA may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), etc., or an ytterbium (Yb) alloy, and may further include a metal doping layer, but is not limited thereto. Meanwhile, although not shown in FIG. 4 and FIG. 6a, the cathode CA of the light-emitting element OLED may be electrically connected to a low-potential power supply line VSS and may be supplied with a low-potential power supply voltage.

[0120] A bank 115 is disposed between the anode AN and the light-emitting layer EL. The bank 115 is disposed so as to overlap the display area AA and cover the edge of the anode AN. The bank 115 is disposed at the boundary between adjacent sub-pixels SP, and can reduce color mixing of light emitted from the light-emitting element OLED of each of the plurality of sub-pixels SP. The bank 115 may be made of an insulating material, for example, but is not limited to, polyimide.

[0121] Meanwhile, the bank 115 may include a first bank 115a and a second bank 115b. The first bank 115a and the second bank 115b may be integrally formed of the same material. The first bank 115a is disposed in a region overlapping with the first substrate 101, and the second bank 115b is disposed in a region not overlapping with the first substrate 101. Thus, the second bank 115b may be disposed to surround the side of the first bank 115a, the inorganic layer 110, the planarization layer 114, and the first substrate 101. Since the first bank 115a is disposed in a region overlapping with the first substrate 101, the bank 115 shown in FIG. 5 corresponds to the first bank 115a. The bank 115 disposed in the non-display area NA will be described in detail below with reference to FIGS. 6a and 6b.

[0122] 6b, in the non-display area NA, a polarizer 150, a first substrate 101, an inorganic layer 110, a planarization layer 114, a bank 115, a cathode CA, an adhesive layer 130, and a second substrate 140 are sequentially arranged. The non-display area NA shown in FIG. 6b is a non-display area NA on a side of the first substrate 101 except for one side where a flexible film 160 is arranged.

[0123] First, referring to Fig. 6a for explaining the manufacturing process, the temporary substrate SUB is disposed under the first substrate 101 with an area larger than that of the first substrate 101 so as to cover the lower surface of the first substrate 101. The temporary substrate SUB is a substrate for supporting the first substrate 101 and components disposed on the first substrate 101 during the manufacturing process of the display device 100. The temporary substrate SUB may be made of a material having rigidity. For example, the temporary substrate SUB may be made of glass, but is not limited thereto.

[0124] A sacrificial layer SL is disposed on the temporary substrate SUB. The sacrificial layer SL is a layer formed to easily separate the temporary substrate SUB and the first substrate 101. Thus, the sacrificial layer SL may be disposed in the same area as the first substrate 101, but may be formed in an area smaller than that of the temporary substrate SUB. A laser may be irradiated onto the sacrificial layer SL below the temporary substrate SUB to dehydrogenate the sacrificial layer SL, and the temporary substrate SUB and the sacrificial layer SL may be separated from the first substrate 101. For example, the sacrificial layer SL may be made of hydrogenated amorphous silicon, or amorphous silicon that has been hydrogenated and doped with impurities.

[0125] A first substrate 101 is disposed on the sacrificial layer SL. The first substrate 101 may be disposed to completely overlap the sacrificial layer SL and have the same area.

[0126] The inorganic layer 110 is disposed on the first substrate 101. An end of the inorganic layer 110 may be located inside an end of the first substrate 101 in the non-display area NA. However, without being limited thereto, the end of the inorganic layer 110 may be located on the same plane as the end of the first substrate 101.

[0127] The planarization layer 114 is disposed on the inorganic layer 110. An end of the planarization layer 114 may be located inside the end of the inorganic layer 110 in the non-display area NA.

[0128] A bank 115 is disposed on the temporary substrate SUB, the first substrate 101, the inorganic layer 110, and the planarization layer 114. The bank 115 is disposed so as to cover the front surface of the temporary substrate SUB. In this case, a region of the bank 115 that overlaps with the first substrate 101 may be defined as a first bank 115a, and a region that does not overlap with the first substrate 101 may be defined as a second bank 115b. Thus, the second bank 115b may be in direct contact with the temporary substrate SUB in the non-display region NA.

[0129] A cathode CA, an adhesive layer 130, and a second substrate 140 may be disposed on the bank 115. The adhesive layer 130 may contact the bank 115 in an area where the cathode CA is not disposed. Thus, a portion of the second bank 115b contacts the adhesive layer 130, and another portion does not contact the adhesive layer 130.

[0130] Then, the first substrate 101 and the temporary substrate SUB can be separated through an LLO process. The sacrificial layer SL can be made of hydrogenated amorphous silicon, or amorphous silicon that has been hydrogenated and doped with impurities, and when a laser is irradiated from below the temporary substrate SUB toward the temporary substrate SUB and the sacrificial layer SL, the hydrogen in the sacrificial layer SL is dehydrogenated, and the sacrificial layer SL and the temporary substrate SUB can be separated from the first substrate 101.

[0131] In addition, the temporary substrate SUB disposed outside the first substrate 101 and the second bank 115b may be separated in the LLO process. If a layer made of a material with low laser absorption is disposed in the outer region of the sacrificial layer, the laser irradiated during LLO passes through the layer as it is, so that separation of the temporary substrate may be difficult due to the adhesive force with the temporary substrate. Even if the layer is separated from the temporary substrate SUB, cracks may occur, and cracks may also occur in the inorganic layer and the first substrate. However, the bank 115, i.e., the second bank 115b, is made of polyimide, which is a material with relatively high laser absorption, and can absorb the laser. Therefore, the second bank 115b is broken or deformed into a cracked state in the LLO process. Therefore, the portion of the temporary substrate SUB that contacts the second bank 115b may be easily separated in the LLO process.

[0132] When the above-mentioned LLO process is completed, the first substrate 101 and the second bank 115b remain as shown in Fig. 6b. As described above, the second bank 115b is deformed into a broken or cracked state during the LLO process. Thus, the portion of the second bank 115b that contacts the adhesive layer 130 remains as it is while being attached to the adhesive layer 130, whereas the portion that does not contact the adhesive layer 130 can be removed in the process of removing the temporary substrate SUB. That is, the portion of the second bank 115b that does not contact the adhesive layer 130 falls due to an external force, so that finally, only the second bank 115b that contacts the adhesive layer 130 remains as shown in Fig. 6b.

[0133] Next, a polarizing plate 150 is disposed below the second bank 115b and the first substrate 101.

[0134] 6b, the second bank 115b may be disposed on the same layer as the first substrate 101 outside the first substrate 101. The second bank 115b may be disposed to surround the first bank 115a, the planarization layer 114, the inorganic layer 110, and the first substrate 101 in the non-display region, and may be disposed in the non-display region NA on the side other than the side on which the flexible film 160 is disposed.

[0135] An end of the second bank 115b may be located on the same plane as an end of the adhesive layer 130. As described above, since the adhesive layer 130 may be in a state in which it is holding the broken or cracked second bank 115b, the end of the second bank 115b may be located on the same plane as an end of the adhesive layer 130. However, if a portion of the second bank 115b falls further, the end of the second bank 115b may be located inside the end of the adhesive layer 130.

[0136] The first bank 115a and the second bank 115b may have different densities. As described above, the second bank 115b is subjected to the LLO process without a sacrificial layer located therebelow, whereas the first bank 115a is subjected to the LLO process with a sacrificial layer located therebelow. Thus, in the case of a laser directed toward the first bank 115a, the sacrificial layer absorbs most of the laser, so the first bank 115a can be maintained as a single layer without breaking or cracking. However, in the case of the second bank 115b, since the sacrificial layer is not located therebelow and the material of the second bank 115b has a relatively high laser absorption rate, the second bank 115b can break or crack during the LLO process. Thus, the second bank 115b may ultimately be in a state where the first bank 115a has cracks, or may be in a state where the material constituting the first bank 115a has broken down and the powder has gathered. Thus, the density of the second bank 115b may be different from, and less than, the density of the first bank 115a.

[0137] In the display device 100 according to an embodiment of the present invention, the first substrate 101 is formed of either a transparent conductive oxide or an oxide semiconductor, thereby reducing the thickness of the display device 100. Conventionally, a plastic substrate has been mainly used as a substrate for a display device, but since the plastic substrate is formed by coating and curing a substrate material at a high temperature, it takes a long time and it is difficult to form the substrate thinly below a certain thickness. In contrast, the transparent conductive oxide and oxide semiconductor can be formed thinly through a deposition process such as sputtering. Therefore, in the display device 100 according to an embodiment of the present invention, the first substrate 101 supporting various components of the display device 100 is formed of a transparent conductive oxide layer or an oxide semiconductor layer, thereby reducing the thickness of the display device 100 and realizing a slim design.

[0138] In addition, in the display device 100 according to an embodiment of the present invention, the first substrate 101 is formed of a transparent conductive oxide or an oxide semiconductor, thereby improving the flexibility of the display device 100 and reducing stress generated when the display device 100 is deformed. Specifically, when the first substrate 101 is formed of a transparent conductive oxide layer or an oxide semiconductor, the first substrate 101 can be formed as a thin film. In this case, the first substrate 101 may also be referred to as a first transparent thin film layer. Thus, the display device 100 including the first substrate 101 may have high flexibility, and the display device 100 may be easily bent or rolled up. Thus, in the display device 100 according to an embodiment of the present invention, the first substrate 101 is formed of either a transparent conductive oxide layer or an oxide semiconductor layer, thereby improving the flexibility of the display device 100 and reducing stress generated when the display device 100 is deformed, thereby minimizing the occurrence of cracks in the display device 100.

[0139] In addition, in the display device 100 according to an embodiment of the present invention, the first substrate 101 is formed of either a transparent conductive oxide layer or an oxide semiconductor layer, so that the possibility of static electricity generation in the first substrate 101 can be reduced. If the first substrate 101 is made of plastic and static electricity is generated, the static electricity may damage various wirings and driving elements on the first substrate 101 or affect driving, thereby degrading display quality. Instead, if the first substrate 101 is formed of a transparent conductive oxide layer or an oxide semiconductor layer, the generation of static electricity in the first substrate 101 can be minimized, and a configuration for blocking and discharging static electricity can be simplified. Therefore, in the display device 100 according to an embodiment of the present invention, the first substrate 101 is formed of either a transparent conductive oxide layer or an oxide semiconductor layer, which are less likely to generate static electricity, so that damage and degradation of display quality due to static electricity can be minimized.

[0140] In addition, in the display device 100 according to an embodiment of the present invention, the first substrate 101 is formed of one of a transparent conductive oxide and an oxide semiconductor, and thus it is possible to minimize the penetration of external moisture, oxygen, etc., into the inside of the display device 100 through the first substrate 101. When the first substrate 101 is formed of a transparent conductive oxide layer or an oxide semiconductor, the first substrate 101 is formed in a vacuum environment, and thus the possibility of foreign matter generation is significantly low. Even if foreign matter is generated, the size of the foreign matter is small, and therefore it is possible to minimize the penetration of moisture and oxygen into the inside of the display device 100. Therefore, in the display device 100 according to an embodiment of the present invention, the first substrate 101 is formed of a transparent conductive oxide or an oxide semiconductor having a low possibility of foreign matter generation and excellent moisture permeability, and thus it is possible to improve the reliability of the light emitting device OLED including the organic layer and the display device 100.

[0141] In addition, in the display device 100 according to an embodiment of the present invention, the first substrate 101 may be formed of either a transparent conductive oxide or an oxide semiconductor, and a thin and inexpensive barrier film may be attached to the lower part of the first substrate 101. If the first substrate 101 is made of a material with low moisture permeability, such as plastic, a thick and expensive high-performance barrier film may be attached to complement the moisture permeability. However, in the display device 100 according to an embodiment of the present invention, the first substrate 101 is formed of either a transparent conductive oxide or an oxide semiconductor with excellent moisture permeability, and therefore a thin and inexpensive barrier film may be attached to the lower part of the first substrate 101. Therefore, in the display device 100 according to an embodiment of the present invention, the first substrate 101 may be formed of either a transparent conductive oxide or an oxide semiconductor with excellent moisture permeability, thereby reducing the manufacturing cost of the display device.

[0142] In addition, in the display device 100 according to an embodiment of the present invention, the first substrate 101 may be formed of either a transparent conductive oxide or an oxide semiconductor, and a laser lift off (LLO) process may be performed. When manufacturing the display device 100, a temporary substrate SUB having a sacrificial layer formed thereon may be attached under the first substrate 101, and then the pixel unit 120 may be formed on the first substrate 101. The sacrificial layer may be, for example, hydrogenated amorphous silicon, or amorphous silicon that has been hydrogenated and doped with impurities. After the manufacturing of the display device 100 is completed, a laser is irradiated under the temporary substrate SUB, whereby hydrogen in the sacrificial layer is dehydrogenated, and the sacrificial layer and the temporary substrate SUB may be separated from the first substrate 101. At this time, the transparent conductive oxide and the oxide semiconductor are materials that can be subjected to the LLO process with the sacrificial layer and the temporary substrate SUB, so that the first substrate 101 and the temporary substrate SUB may be easily separated from each other even if the first substrate 101 is formed of either a transparent conductive oxide or an oxide semiconductor. Therefore, in the display device 100 according to one embodiment of the present invention, since the first substrate 101 is composed of one of a transparent conductive oxide layer or an oxide semiconductor that can be subjected to the LLO process, the display device 100 can be easily manufactured using existing processes and equipment.

[0143] Meanwhile, as described above, when the first substrate made of one of the transparent conductive oxide layer or the oxide semiconductor is used, the first substrate can be disposed in the entire region of the display device for the LLO process. That is, the first substrate can be disposed in the entire display region and non-display region of the display device. In this case, the first substrate and the inorganic layer are disposed so as to extend to the outermost region of the display device. However, when the first substrate and the inorganic layer are disposed in the outermost region in this manner, the first substrate and the inorganic layer can be easily cracked and damaged by an external impact. In addition, when an external force is applied to the boundary of the second substrate having a relatively high rigidity, the first substrate and the inorganic layer can be cracked and damaged in the region corresponding to the boundary of the second substrate. Therefore, moisture permeation through the inorganic layer can be a problem, and reliability can be reduced. In addition, when a crack occurs in the first substrate and the inorganic layer, the crack can propagate to other components, and especially when the crack propagates to wiring or circuit configuration, driving failure can occur.

[0144] In the display device 100 according to an embodiment of the present invention, the bank 115 is configured to include the inorganic layer 110, the planarization layer 114, and the second bank 115b disposed to surround the side of the first substrate 101. Thus, during the LLO process, the LLO process can be easily performed through the temporary substrate SUB through which the laser transmits light and the second bank 115b which absorbs the laser. In this case, the bank 115 can be made of a material having a high absorption rate for the laser. If the planarization layer made of an acrylic resin, which is a material having a low absorption rate for the laser, is in direct contact with the temporary substrate, the laser passes through most of the temporary substrate and the planarization layer, so that separation between the temporary substrate and the planarization layer may not be easy. However, as in the display device 100 according to an embodiment of the present invention, if the bank 115 made of polyimide, which is a material having a high absorption rate for the laser, is in direct contact with the temporary substrate SUB, the laser passing through the temporary substrate SUB is absorbed by the bank 115, and the bank 115 may break or crack. Therefore, in the process of removing the temporary substrate SUB, only the second bank 115b in contact with the adhesive layer 130 remains, and the portion not in contact with the adhesive layer 130 can be removed.

[0145] Therefore, in the display device 100 according to an embodiment of the present invention, the display device 100 can be easily manufactured by performing the LLO process without disposing the first substrate 101 and the inorganic layer 110 on the outer periphery of the display device 100.

[0146] Therefore, in the display device 100 according to an embodiment of the present invention, the first substrate 101 and the inorganic layer 110 do not need to be disposed at the outer periphery of the display device 100. In addition, the first substrate 101 and the inorganic layer 110 do not need to be disposed in an area corresponding to the boundary of the second substrate 140. As a result, the first substrate 101 and the inorganic layer 110 are not damaged or cracked due to an impact from the outside of the display device 100 and a stress applied to the boundary of the second substrate 140. Therefore, the reliability of the display device 100 according to an embodiment of the present invention can be improved, and the occurrence of driving failures due to cracks can also be reduced.

[0147] Furthermore, in the display device 100 according to an embodiment of the present invention, the bezel area can be reduced by removing the sealing material disposed outside the second bank 115b and the adhesive layer 130. In general, in a display device, a sealing material is disposed so as to surround the side surfaces of the pixel unit and the adhesive layer. Thus, the bezel is increased by the area where the sealing material is disposed. In the display device 100 according to an embodiment of the present invention, the bank disposed outside the adhesive layer 130 is removed in the LLO process for removing the temporary substrate SUB, so that the need for disposing the sealing material can be eliminated and the bezel area can be reduced compared to the case where the sealing material is disposed.

[0148] 7a is a cross-sectional view for explaining a manufacturing process of a display device according to another embodiment of the present invention. FIG. 7b is a cross-sectional view of a display device according to another embodiment of the present invention. The display device 700 of FIG. 7a and FIG. 7b is different from the display device 100 of FIG. 1 to FIG. 6a only in the bank 715 and the adhesive layer 730, and other configurations are substantially the same, so that a duplicated description will be omitted.

[0149] To illustrate the manufacturing process of the display device 700, referring to FIG. 7a, a bank 715 is disposed on the temporary substrate SUB, the first substrate 101, the inorganic layer 110 and the planarization layer 114.

[0150] The bank 715 includes a first bank 715a and a second bank 715b. In the bank 715, a region that overlaps with the first substrate 101 may be defined as the first bank 715a, and a region that does not overlap with the first substrate 101 may be defined as the second bank 715b.

[0151] The first bank 715a and the second bank 715b may be spaced apart from each other.

[0152] An end of the first bank 715a may be disposed inside an end of the inorganic layer 110. An end of the second bank 715b may be disposed so as to contact the temporary substrate SUB in the non-display area NA. Thus, a part of the upper surface of the inorganic layer 110 and the first substrate 101 may be exposed between the first bank 715a and the second bank 715b.

[0153] The second bank 715b may be disposed spaced apart from the first substrate 101. For example, the width W of the space between the first substrate 101 and the second bank 715b may be 100 μm or less. The second bank 715b may also be disposed spaced apart from the inorganic layer 110 disposed on the inner end of the first substrate 101.

[0154] A cathode CA, an adhesive layer 730, and a second substrate 140 may be disposed on the bank 715. The adhesive layer 730 may be formed to fill a space between the second bank 715b and the first substrate 101 and the inorganic layer 110. For example, the adhesive layer 730 may cover the side surfaces of the first bank 715a, the top surface of the temporary substrate SUB exposed by the first bank 715a, the inorganic layer 110, and the side surfaces of the first substrate 101.

[0155] Then, the first substrate 101 and the temporary substrate SUB can be separated through an LLO process. In the region where the first substrate 101 is disposed, the sacrificial layer SL exists between the first substrate 101 and the temporary substrate SUB, so that the first substrate 101 and the temporary substrate SUB can be easily separated.

[0156] The second bank 715b is deformed in the LLO process to a state in which it is broken or cracked, so that the portion of the temporary substrate SUB in contact with the second bank 715b can be easily separated in the LLO process.

[0157] When the above-mentioned LLO process is completed, the first substrate 101 and the second bank 715b remain as shown in Fig. 7b. As described above, the second bank 715b is deformed into a broken or cracked state during the LLO process. Thus, the portion of the second bank 715b that contacts the adhesive layer 730 remains as it is while being attached to the adhesive layer 730, whereas the portion that does not contact the adhesive layer 730 can be removed together with the second bank 715b in the process of removing the temporary substrate SUB. That is, the portion of the second bank 715b that does not contact the adhesive layer 730 falls due to an external force, so that finally, only the second bank 715b that contacts the adhesive layer 730 remains as shown in Fig. 7b.

[0158] In the LLO process, the temporary substrate SUB and the adhesive layer 730 can also be easily separated. The temporary substrate SUB and the adhesive layer 730 are attached by the adhesive force of the adhesive layer 730, and as described above, when the width W of the space between the first substrate 101 and the second bank 715b is 100 μm or less, the contact area between the adhesive layer 730 and the temporary substrate SUB is small, so that the temporary substrate SUB and the adhesive layer 730 can be easily separated.

[0159] Then, the polarizer 150 is disposed under the second bank 715b and the first substrate 101. Meanwhile, the adhesive layer 730 may be embodied in a shape that protrudes between the first substrate 101 and the second bank 715b. For example, the adhesive layer 730 may have a shape that protrudes in a direction that fills the gap between the first substrate 101 and the second bank 715b, and may actually protrude to a thickness of about several tens of nm from the lower surface of the second bank 715b and the first substrate 101. Thus, the polarizer 150 may flatten the protruding shape of the adhesive layer 730.

[0160] In a display device 700 according to another embodiment of the present invention, the bank 715 is configured to include a second bank 715b disposed on the outside of the first substrate 101, and the LLO process can be performed without disposing the first substrate 101 and the inorganic layer 110 on the outer periphery of the display device 700, thereby improving reliability and reducing the occurrence of driving defects due to cracks.

[0161] In addition, in the display device 700 according to another embodiment of the present invention, the sealant disposed outside the second bank 715b and the adhesive layer 730 can be removed to reduce the bezel area.

[0162] In addition, in the display device 700 according to another embodiment of the present invention, the second bank 715b and the inorganic layer 110 are spaced apart from each other, thereby reducing cracks in the inorganic layer 110 that occur at the periphery of the display device 700. As described above, the second bank 715b may be broken or cracked during the LLO process. At this time, cracks may propagate to the inorganic layer due to scattered material from the second bank. Therefore, in the display device 700 according to another embodiment of the present invention, the inorganic layer 110 is prevented from being cracked or damaged by scattered material from the bank 715 that occurs during the LLO process by spaced apart from the second bank 715b.

[0163] 8a is a cross-sectional view for explaining a manufacturing process of a display device according to another embodiment of the present invention. FIG. 8b is a cross-sectional view of a display device according to another embodiment of the present invention. The display device 800 of FIG. 8a and FIG. 8b is different from the display device 100 of FIG. 1 to FIG. 6a only in the planarization layer 814, the bank 815, and the adhesive layer 830, and other configurations are substantially the same, so that the duplicated description will be omitted.

[0164] To explain the manufacturing process, referring to FIG. 8 a , a planarization layer 814 is disposed on the temporary substrate SUB, the first substrate 101 and the inorganic layer 110 .

[0165] An end of the planarization layer 814 may be located outside ends of the inorganic layer 110 and the first substrate 101 in the non-display area NA. For example, the planarization layer 814 may cover the side surfaces of the first substrate 101 and the inorganic layer 110 on the inorganic layer 110, and may be disposed so as to contact the temporary substrate SUB outside the first substrate 101.

[0166] A bank 815 is disposed on the planarization layer 814 .

[0167] In the bank 815, the area that overlaps with the first substrate 101 may be defined as a first bank 815a, and the area that does not overlap with the first substrate 101 may be defined as a second bank 815b.

[0168] The first bank 815a and the second bank 815b may be spaced apart from each other.

[0169] An end of the first bank 815a may be disposed on the planarization layer 814 inside an end of the inorganic layer 110 and an end of the first substrate 101. For example, the first bank 815a may contact the planarization layer 814 disposed on the inorganic layer 110 and the first substrate 101.

[0170] The second bank 815b may be disposed on the same layer as the first substrate 101, outside the first substrate 101. Also, one end of the second bank 815b may be disposed on the planarization layer 814. Thus, the second bank 815b may cover an end of the planarization layer 814. At this time, the second bank 815b may be disposed so as to contact the planarization layer 814 and the temporary substrate SUB. Thus, the end of the second bank 815b may contact the temporary substrate SUB, outside the planarization layer 814 disposed in the non-display region NA.

[0171] Thus, a portion of the top surface of the planarization layer 814 may be exposed between the first bank 815a and the second bank 815b.

[0172] A cathode CA, an adhesive layer 830, and a second substrate 140 may be disposed on the bank 815. The adhesive layer 830 may be formed to fill a space between the first bank 815a and the second bank 815b.

[0173] Then, the first substrate 101 and the temporary substrate SUB can be separated through an LLO process. In the region where the first substrate 101 is disposed, the sacrificial layer SL exists between the first substrate 101 and the temporary substrate SUB, so that the first substrate 101 and the temporary substrate SUB can be easily separated.

[0174] The second bank 815b is deformed into a broken or cracked state during the LLO process, so that the portion of the temporary substrate SUB in contact with the second bank 815b can be easily separated during the LLO process.

[0175] Furthermore, when the second bank 815b is disposed on the temporary substrate SUB so as to be in contact with the planarization layer 814, the second bank 815b can absorb light transmitted through the temporary substrate SUB and the planarization layer 814. Thus, the interface between the second bank 815b and the planarization layer 814 can be separated in the process of removing the temporary substrate SUB.

[0176] When the above-mentioned LLO process is completed, the first substrate 101 and the second bank 815b remain as shown in Fig. 8b. As described above, the second bank 815b is deformed into a broken or cracked state during the LLO process. Thus, the portion of the second bank 815b that contacts the adhesive layer 830 remains as it is while being attached to the adhesive layer 830, whereas the portion that does not contact the adhesive layer 830 can be removed together with the second bank 815b in the process of removing the temporary substrate SUB. That is, the portion of the second bank 815b that does not contact the adhesive layer 830 falls due to an external force, so that finally, only the second bank 815b that contacts the adhesive layer 830 remains as shown in Fig. 8b.

[0177] Next, a polarizing plate 150 is disposed below the second bank 815b, the planarizing layer 814, and the first substrate 101.

[0178] 8b, since the planarization layer 814 in contact with the temporary substrate SUB is removed in the LLO process, a first space 880, which is an empty space surrounded by the first substrate 101, the polarizer 150, the second bank 815b, and the planarization layer 814, may be present as shown in FIG. 8b. However, without being limited thereto, the first space 880 may be filled with an adhesive layer used in the bonding process of the polarizer 150.

[0179] The planarization layer 814 may surround the side surface of the inorganic layer 110 in a region overlapping with the inorganic layer 110 and the first substrate 101 .

[0180] A cathode CA, an adhesive layer 830, and a second substrate 140 may be disposed on the bank 815. The adhesive layer 830 may fill a space between the first bank 815a and the second bank 815b. For example, the adhesive layer 830 may cover an upper surface of the planarization layer 814 exposed between the first bank 815a and the second bank 815b.

[0181] In a display device 800 according to another embodiment of the present invention, the bank 815 is configured to include a second bank 815b disposed on the outside of the first substrate 101, and the LLO process can be performed without disposing the first substrate 101 and the inorganic layer 110 on the outer periphery of the display device 800, thereby improving reliability and reducing the occurrence of driving defects due to cracks.

[0182] In addition, in the display device 800 according to another embodiment of the present invention, the sealant disposed outside the second bank 815b and the adhesive layer 830 may be removed to reduce the bezel area.

[0183] In addition, in the display device 800 according to the still further embodiment of the present invention, the second bank 815b and the inorganic layer 110 are spaced apart from each other, thereby reducing cracks in the inorganic layer 110 that occur at the periphery of the display device 800. As described above, the second bank 815b may be broken or cracked during the LLO process. At this time, cracks may propagate to the inorganic layer due to scattered material from the second bank. Therefore, in the display device 800 according to the still further embodiment of the present invention, the inorganic layer 110 is prevented from being cracked or damaged by scattered material from the bank 815 that occurs during the LLO process by spaced apart from the second bank 815b.

[0184] In the display device 800 according to still another embodiment of the present invention, the planarization layer 814 fills the space exposed by the first substrate 101 and the second bank 815b, so that the LLO process can be performed more easily. That is, when the planarization layer 814 contacts the temporary substrate SUB on the outside of the first substrate 101, the temporary substrate SUB and the first substrate 101 can be easily separated without miniaturizing the width W of the space separating the first substrate 101 and the second bank 815b to 100 μm or less. Therefore, since it is not necessary to adjust the process margin for securing the space between the first substrate 101 and the second bank 815b, the manufacturing process of the display device 800 can be facilitated.

[0185] 9A is a cross-sectional view for explaining a manufacturing process of a display device according to another embodiment of the present invention. FIG 9B is a cross-sectional view of a display device according to another embodiment of the present invention. The display device 900 of FIG 9A and FIG 9B is different from the display device 100 of FIG 1 to FIG 6A only in the bank 915 and the adhesive layer 930, and other configurations are substantially the same, so that a duplicated description will be omitted.

[0186] To explain the manufacturing process, referring to FIG. 9 a , a bank 915 is disposed on the temporary substrate SUB, the first substrate 101 , the inorganic layer 110 and the planarization layer 114 .

[0187] The bank 915 includes a first bank 915a and a second bank 915b. In the bank 915, a region that overlaps with the first substrate 101 may be defined as the first bank 915a, and a region that does not overlap with the first substrate 101 may be defined as the second bank 915b.

[0188] The first bank 915a includes a first portion 915a-1 connected to the second bank 915b, and a second portion 915a-2 spaced apart from the first portion 915a-1 and disposed closer to the display area AA than the first portion 915a-1.

[0189] The first portion 915a-1 of the first bank 915 may be disposed on the first substrate 101 exposed by the inorganic layer 110. That is, the first portion 915a-1 may cover an end of the first substrate 101. Also, the first portion 915a-1 may be disposed spaced apart from the planarization layer 114. In this case, if an end of the inorganic layer 110 protrudes outward beyond an end of the planarization layer 114, the first portion 915a-1 may also be disposed spaced apart from the inorganic layer 110.

[0190] The second portion 915a-2 of the first bank 915 may be disposed in a region overlapping with the first substrate 101. In this case, an end of the second portion 915a-2 may be disposed between an end of the cathode CA and an end of the planarization layer 114. As shown in Figures 9a and 9b, the second portion 915a-2 may be disposed in a region overlapping with the cathode CA.

[0191] The second bank 915b may be disposed so as to be in contact with the temporary substrate SUB. At this time, the second bank 915b may be disposed so as to be connected to the first portion 915a-1 disposed on the first substrate 101.

[0192] A cathode CA, an adhesive layer 930, and a second substrate 140 may be disposed on the bank 915. The adhesive layer 930 may be formed to fill a space between the first portion 915a-1 and the inorganic layer 110.

[0193] Then, the first substrate 101 and the temporary substrate SUB can be separated through an LLO process. In the region where the first substrate 101 is disposed, the sacrificial layer SL exists between the first substrate 101 and the temporary substrate SUB, so that the first substrate 101 and the temporary substrate SUB can be easily separated.

[0194] The second bank 915b is deformed in the LLO process to a state in which it is broken or cracked, so that the portion of the temporary substrate SUB in contact with the second bank 915b can be easily separated in the LLO process.

[0195] When the above-mentioned LLO process is completed, the first substrate 101 and the second bank 915b remain as shown in Fig. 9b. As described above, the second bank 915b is deformed into a broken or cracked state during the LLO process. Thus, the portion of the second bank 915b that contacts the adhesive layer 930 remains as it is while being attached to the adhesive layer 930, whereas the portion that does not contact the adhesive layer 930 can be removed together with the second bank 915b in the process of removing the temporary substrate SUB. That is, the portion of the second bank 915b that does not contact the adhesive layer 930 falls due to an external force, so that finally, only the second bank 915b that contacts the adhesive layer 930 remains as shown in Fig. 9b.

[0196] Next, a polarizing plate 150 is disposed below the second bank 915b and the first substrate 101.

[0197] In a display device 900 according to another embodiment of the present invention, the bank 915 is configured to include a second bank 915b disposed on the outside of the first substrate 101, and the LLO process can be performed without disposing the first substrate 101 and the inorganic layer 110 on the outer periphery of the display device 900, thereby improving reliability and reducing the occurrence of driving defects due to cracks.

[0198] In addition, in the display device 900 according to another embodiment of the present invention, the sealant disposed outside the second bank 915b and the adhesive layer 930 may be removed to reduce the bezel area.

[0199] In addition, in the display device 900 according to the still further embodiment of the present invention, the second bank 915b and the inorganic layer 110 are spaced apart from each other, thereby reducing cracks in the inorganic layer 110 that occur at the periphery of the display device 900. As described above, the second bank 915b may be broken or cracked during the LLO process. At this time, cracks may propagate to the inorganic layer due to scattered material from the second bank. Therefore, in the display device 900 according to the still further embodiment of the present invention, the inorganic layer 110 is prevented from being cracked or damaged by scattered material from the bank 915 that occurs during the LLO process by spaced apart from the second bank 915b.

[0200] In addition, in the display device 900 according to the third embodiment of the present invention, the bank 915 is disposed to cover an end of the first substrate 101, so that the LLO process can be easily performed. Referring to FIG. 9a, the upper surface of the temporary substrate SUB is in contact only with the sacrificial layer SL and the bank 915, and is not in contact with other organic layers or adhesive layers. Thus, in the LLO process, the temporary substrate SUB can be easily separated from the first substrate 101 in the region where the first substrate 101 and the sacrificial layer SL are disposed, and can be easily separated from the second bank 915b in the region where the second bank 915 is disposed. Thus, in the display device 900 according to the third embodiment of the present invention, the LLO process can be easily performed due to the arrangement of the first substrate 101 and the bank 915, and defects due to removal of other components are not generated.

[0201] 10a is a cross-sectional view for explaining a manufacturing process of a display device according to another embodiment of the present invention. FIG. 10b is a cross-sectional view of a display device according to another embodiment of the present invention. The display device 1000 of FIG. 10a and FIG. 10b is different from the display device 900 of FIG. 9a and FIG. 9b only in the bank 1015, the inorganic layer 1010, the planarization layer 1014, and the adhesive layer 1030. The other configurations are substantially the same, so that the duplicated description will be omitted.

[0202] To explain the manufacturing process, referring to FIG. 10a, a temporary substrate SUB, a first substrate 101, on which an inorganic layer 1010 is disposed.

[0203] The inorganic layer 1010 may be disposed adjacent to an end of the cathode CA disposed in the non-display area NA so that the area of ​​the first substrate 101 exposed may be increased.

[0204] A planarization layer 1014 is disposed on the inorganic layer 1010. The planarization layer 1014 may be disposed so as to cover an end of the inorganic layer 1010. The planarization layer 1014 may be disposed so as to overlap an upper surface of the inorganic layer 1010 and a portion of the first substrate 101 exposed by the inorganic layer 1010. Thus, the planarization layer 1014 may be disposed so as to seal the inorganic layer 1010 and surround the upper surface and side surfaces of the inorganic layer 1010.

[0205] A bank 1015 is disposed on the planarization layer 1014. The bank 1015 includes a first bank 1015a and a second bank 1015b. The first bank 1015a may be disposed in a region overlapping with the first substrate 101. In this case, an end of the first bank 1015a may be disposed between an end of the cathode CA and an end of the planarization layer 1014. As shown in Figures 10a and 10b, the first bank 1015a may be disposed in a region overlapping with the cathode CA.

[0206] The second bank 1015b may be disposed so as to be in contact with the temporary substrate SUB. In this case, the second bank 1015b may be disposed on the first substrate 101 exposed by the inorganic layer 1010. That is, the second bank 1015b may cover an end of the first substrate 101. In addition, the second bank 1015b may be disposed spaced apart from the planarization layer 1014. For example, one surface of the temporary substrate SUB may be exposed between the planarization layer 1014 and the second bank 1015b.

[0207] A cathode CA, an adhesion layer 1030 and a second substrate 140 may be disposed on the bank 1015 .

[0208] The adhesive layer 1030 may be formed to fill a space between the second bank 1015b and the planarization layer 1014. For example, the adhesive layer 1030 may cover the side surfaces of the second bank 1015b, the side surfaces of the planarization layer 1014, and the top surface of the temporary substrate SUB exposed by the second bank 1015b and the planarization layer 1014.

[0209] Then, the first substrate 101 and the temporary substrate SUB can be separated through an LLO process. In the region where the first substrate 101 is disposed, the adhesive layer 1030, the planarization layer 1014, and the first substrate 101 are removed together with the temporary substrate SUB in the region where the second bank 1015a contacts the first substrate 101, and the first substrate 101 and the temporary substrate SUB can be easily separated from each other in the remaining region.

[0210] The second bank 1015b is deformed in the LLO process to a state in which it is broken or cracked, so that the portion of the temporary substrate SUB in contact with the second bank 1015b can be easily separated in the LLO process.

[0211] Next, a polarizing plate 150 is disposed below the second bank 1015b and the first substrate 101.

[0212] 10b, a polarizer 150 is disposed under the first substrate 101. In this case, in FIG. 10b, the polarizer 150 is shown to be disposed protruding toward the adhesive layer 1030, but is not limited thereto, and the area from which the first substrate 101 has been removed may be filled with an adhesive that bonds the first substrate 101 and the polarizer 150.

[0213] In a display device 1000 according to another embodiment of the present invention, the bank 1015 is configured to include a second bank 1015b disposed on the outside of the first substrate 101, and the LLO process can be performed without disposing the first substrate 101 and the inorganic layer 1010 on the outer periphery of the display device 1000, thereby improving reliability and reducing the occurrence of driving defects due to cracks.

[0214] In addition, in the display device 1000 according to another embodiment of the present invention, the sealant disposed outside the second bank 1015b and the adhesive layer 1030 can be removed to reduce the bezel area.

[0215] In addition, in the display device 1000 according to the still further embodiment of the present invention, the second bank 1015b and the inorganic layer 1010 are spaced apart from each other, thereby reducing cracks in the inorganic layer 1010 that occur at the outer periphery of the display device 1000. As described above, the second bank 1015 may be broken or cracked during the LLO process. At this time, cracks may propagate to the inorganic layer due to scattered material from the second bank. Therefore, in the display device 1000 according to the still further embodiment of the present invention, the inorganic layer 1010 is spaced apart from the second bank 1015b to prevent the inorganic layer 1010 from being cracked or damaged due to scattered material from the bank 1015 that occurs during the LLO process.

[0216] In particular, in the display device 1000 according to another embodiment of the present invention, the planarization layer 1014 is disposed to cover an end of the inorganic layer 1010, thereby reducing damage to the inorganic layer 1010. Even if the inorganic layer and the second bank are separated from each other at the outer periphery of the display device, cracks may still propagate to the inorganic layer. Therefore, in the display device 1000 according to another embodiment of the present invention, the planarization layer 1014 is disposed to cover an end of the inorganic layer 1010 at the outer periphery of the display device 1000, thereby more efficiently protecting the inorganic layer 1010 from external impacts and flying material from the bank 1015.

[0217] 11a is a cross-sectional view for explaining a manufacturing process of a display device according to another embodiment of the present invention. FIG 11b is a cross-sectional view of a display device according to another embodiment of the present invention. The display device 1100 of FIG 11a and FIG 11b is different from the display device 1000 of FIG 10a and FIG 10b only in the planarization layer 1114, the second bank 1115b, and the adhesive layer 1130. The other configurations are substantially the same, so that the duplicated description will be omitted.

[0218] To explain the manufacturing process, referring to FIG. 11 a , a planarization layer 1114 is disposed on the temporary substrate SUB, the first substrate 101 and the inorganic layer 1010 .

[0219] The planarization layer 1114 may be disposed to cover an end of the inorganic layer 1010. Thus, the planarization layer 1114 may be disposed to overlap an upper surface of the inorganic layer 1010 and a portion of the first substrate 101 exposed by the inorganic layer 1010. Thus, the planarization layer 1114 may be disposed to seal the inorganic layer 1010 and surround the upper surface and side surfaces of the inorganic layer 1010.

[0220] A bank 1115 is disposed on the planarization layer 1114. The bank 1115 includes a first bank 1115a and a second bank 1115b.

[0221] The first bank 1015 a can be disposed in a region overlapping with the first substrate 101 .

[0222] The second bank 1115b may be disposed so as to be in contact with the temporary substrate SUB. At this time, the second bank 1115b may be disposed on the first substrate 101 exposed by the inorganic layer 1010. That is, the second bank 1115b may cover an end of the first substrate 101. The second bank 1115b may be in contact with a side surface of the planarization layer 1114, and one end of the second bank 1115b may be disposed on the first substrate 101 and the planarization layer 1114 exposed by the inorganic layer 1010.

[0223] In addition, the second bank 1115b may be disposed apart from the first bank 1015a. For example, the bank 1115 may be formed to expose a portion of the upper surface of the planarization layer 1114 between the first bank 1015a and the second bank 1115b. The cathode CA, the adhesion layer 1130, and the second substrate 140 may be disposed on the bank 1115.

[0224] The adhesive layer 1130 may be formed to fill the space between the first bank 1015a and the second bank 1115b, and may contact a surface of the planarization layer 1114 exposed between the first bank 1015a and the second bank 1115b.

[0225] Then, the first substrate 101 and the temporary substrate SUB can be separated through an LLO process. In the region where the first substrate 101 is disposed, the planarization layer 1114 and the region where the second bank 1115b contacts the first substrate 101 are removed together with the temporary substrate SUB, and the first substrate 101 and the temporary substrate SUB can be easily separated from each other in the remaining region.

[0226] The second bank 1115b is deformed in the LLO process to a state in which it is broken or cracked, so that the portion of the temporary substrate SUB in contact with the second bank 1115b can be easily separated in the LLO process.

[0227] Next, a polarizing plate 150 is disposed below the second bank 1115b and the first substrate 101.

[0228] 11b, a polarizer 150 is disposed under the first substrate 101. In FIG. 11b, the polarizer 150 is shown to be disposed protruding toward the second bank 1115b and the planarization layer 1114, but is not limited thereto, and the area from which the first substrate 101 has been removed may be filled with an adhesive that bonds the first substrate 101 and the polarizer 150.

[0229] In a display device 1100 according to another embodiment of the present invention, the bank 1115 is configured to include a second bank 1115b disposed on the outside of the first substrate 101, and the LLO process can be performed without disposing the first substrate 101 and the inorganic layer 1010 on the outer periphery of the display device 1100, thereby improving reliability and reducing the occurrence of driving defects due to cracks.

[0230] In addition, in the display device 1100 according to another embodiment of the present invention, the sealant disposed outside the second bank 1115b and the adhesive layer 1130 can be removed to reduce the bezel area.

[0231] In addition, in the display device 1100 according to the still further embodiment of the present invention, the second bank 1115b and the inorganic layer 1010 are spaced apart from each other, thereby reducing cracks in the inorganic layer 1010 that occur at the periphery of the display device 1100. As described above, the second bank 1115b may be broken or cracked during the LLO process. At this time, cracks may propagate to the inorganic layer due to scattered material from the second bank. Therefore, in the display device 1100 according to the still further embodiment of the present invention, the inorganic layer 1010 is prevented from being cracked or damaged by scattered material from the bank 1115 that occurs during the LLO process by spaced apart from the second bank 1115b.

[0232] In particular, in the display device 1100 according to another embodiment of the present invention, the planarization layer 1114 is disposed to cover an end of the inorganic layer 1010, thereby reducing damage to the inorganic layer 1010. Even if the inorganic layer and the second bank are separated from each other at the outer periphery of the display device, cracks may still propagate to the inorganic layer. Therefore, in the display device 1100 according to another embodiment of the present invention, the planarization layer 1114 is disposed to cover an end of the inorganic layer 1010 at the outer periphery of the display device 1100, thereby more efficiently protecting the inorganic layer 1010 from external impacts and flying material from the bank 1115.

[0233] Furthermore, in the display device 1100 according to another embodiment of the present invention, the planarization layer 1114, rather than the adhesive layer 1130, is disposed to contact the first substrate 101, which may allow for an easier LLO process.

[0234] A display device according to an embodiment of the present invention can be described as follows.

[0235] A display device according to an embodiment of the present invention includes a display area including a plurality of sub-pixels and a non-display area surrounding the display area, and includes a first substrate made of one of a transparent conductive oxide and an oxide semiconductor, an inorganic layer disposed on the first substrate, a planarization layer disposed on the inorganic layer, a bank disposed on the planarization layer, an adhesive layer disposed on the inorganic layer, the planarization layer and the bank, and a second substrate disposed on the adhesive layer, and the bank includes a first bank disposed in an area overlapping with the first substrate and a second bank disposed to surround a side of the first bank.

[0236] According to another feature of the present invention, the second bank can be disposed to surround side surfaces of the inorganic layer, the planarization layer, and the first substrate.

[0237] According to yet another feature of the invention, the second bank may be disposed outside the first substrate and on the same layer as the first substrate.

[0238] According to another feature of the present invention, the display device may further include a flexible film disposed on one side of the non-display area on the first substrate, and the second bank may be disposed in the non-display area on a side other than the side on which the flexible film is disposed.

[0239] According to yet another feature of the invention, the terminus of the second bank may be flush with or inboard of the terminus of the adhesive layer.

[0240] According to yet another feature of the invention, the first bank and the second bank may have different densities.

[0241] According to yet another feature of the present invention, the second bank may include a cracked portion.

[0242] According to yet another feature of the invention, the second bank may be in a state where the crushed powder is collected.

[0243] According to yet another aspect of the present invention, the first bank and the second bank may be integrated.

[0244] According to another aspect of the present invention, the first bank and the second bank may be spaced apart from each other.

[0245] According to another aspect of the present invention, the second bank may be spaced apart from the first substrate and the inorganic layer, and the adhesive layer may fill a space between the second bank, the first substrate, and the inorganic layer.

[0246] According to another aspect of the present invention, the width of the space between the first substrate and the second bank may be 100 μm or less.

[0247] According to another feature of the present invention, one end of the second bank is disposed on the planarization layer, and the adhesive layer fills the space between the first bank and the second bank, so that the first substrate and the second bank can be spaced apart from each other.

[0248] According to another aspect of the present invention, the planarization layer may be disposed to cover an end of the inorganic layer and to be spaced apart from the second bank.

[0249] According to another aspect of the present invention, the adhesive layer can fill a space between the second bank and the planarization layer.

[0250] According to another aspect of the present invention, the first bank may include a first portion connected to the second bank, and a second portion spaced apart from the first portion and disposed closer to the display area than the first portion.

[0251] According to another feature of the present invention, the first portion and the inorganic layer are separated from each other, the adhesive layer fills the space between the first portion and the inorganic layer, and an end of the inorganic layer may protrude outward beyond an end of the planarization layer.

[0252] According to another aspect of the present invention, the planarization layer may be made of an acrylic-based material, and the bank may be made of polyimide. According to another feature of the present invention, an end of the first substrate and an end of the inorganic layer may be located inside an end of the second substrate.

[0253] Although the embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications can be made within the scope of the technical idea of ​​the present invention. Therefore, the embodiments disclosed in the present invention are for illustration purposes, not for limiting the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative and not restrictive in all respects. The scope of protection of the present invention should be interpreted according to the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

Claims

1. a first substrate including a display area including a plurality of sub-pixels and a non-display area surrounding the display area, the first substrate being made of either a transparent conductive oxide or an oxide semiconductor; an inorganic layer disposed on the first substrate; a planarization layer disposed on the inorganic layer; a bank disposed on the planarization layer; an adhesion layer disposed on the inorganic layer, the planarization layer, and the bank; a second substrate disposed on the adhesive layer; the bank includes a first bank arranged in a region overlapping the first substrate, and a second bank supported by the adhesive layer and arranged so as to surround a side surface of the first bank; The second bank is disposed so as to surround side surfaces of the inorganic layer, the planarization layer, and the first substrate.

2. The display device according to claim 1 , wherein the second bank is disposed outside the first substrate and on the same layer as the first substrate.

3. The display device further includes a flexible film disposed on one side of the non-display area on the first substrate, The display device of claim 1 , wherein the second bank is disposed in the non-display region on a side other than the one side on which the flexible film is disposed.

4. The display device according to claim 1 , wherein an end of the second bank is on the same plane as an end of the adhesive layer or is located inside the end of the adhesive layer.

5. The display device of claim 1 , wherein the first bank and the second bank have different densities.

6. The display device according to claim 1 , wherein the second bank includes a cracked portion.

7. The display device according to claim 1 , wherein the second bank is in a state where crushed powder is gathered.

8. The display device according to claim 1 , wherein the first bank and the second bank are integrated together.

9. The display device of claim 1 , wherein the first bank and the second bank are spaced apart from each other.

10. the second bank is spaced apart from the first substrate and the inorganic layer; The display device of claim 9 , wherein the adhesive layer fills a space between the second bank, the first substrate, and the inorganic layer.

11. The display device of claim 10 , wherein a width of a space between the first substrate and the second bank is 100 μm or less.

12. one end of the second bank is disposed on the planarization layer; the adhesive layer fills a space between the first bank and the second bank; The display device of claim 9 , wherein the first substrate and the second bank are spaced apart from each other.

13. The display device of claim 9 , wherein the planarization layer covers an end of the inorganic layer and is spaced apart from the second bank.

14. The display device of claim 9 , wherein the adhesive layer fills a space between the second bank and the planarization layer.

15. The display device of claim 1 , wherein the first bank includes a first portion connected to the second bank and a second portion spaced apart from the first portion and disposed closer to the display area than the first portion.

16. The first portion is spaced apart from the inorganic layer, the adhesive layer fills a space between the first portion and the inorganic layer; The display device according to claim 15 , wherein an end of the inorganic layer protrudes outward beyond an end of the planarizing layer.

17. The display device of claim 1 , wherein the planarization layer is made of an acrylic-based material, and the bank is made of polyimide.

18. The display device according to claim 1 , wherein an end of the first substrate and an end of the inorganic layer are located inside an end of the second substrate.

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