Display device

Abstract

To provide a display device with high reliability by achieving high mobility in an oxide semiconductor.SOLUTION: A first oxide member is formed on a base material member. First heat treatment is performed to grow crystal from a surface toward an inside to form a first oxide crystal member at least partially in contact with the base material member. A second oxide member is formed on the first oxide crystal member. Second heat treatment is performed to grow crystal using the first oxide crystal member as a seed. A high mobility transistor is formed using a laminated oxide material in which a second oxide crystal member is provided. A driver circuit is formed on the same substrate using the transistor.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a display device using an oxide semiconductor, a manufacturing method thereof, and a display device. Regarding electronic devices. [Background technology]

[0002] As typified by liquid crystal display devices, transistors formed on glass substrates are amorphous. It is made of amorphous silicon, polycrystalline silicon, etc. Although the resulting transistor has low field-effect mobility, it can be used on large glass substrates. In addition, although the field effect mobility of a transistor using polycrystalline silicon is high, the glass substrate is However, it has a drawback that it is not suitable for large area applications.

[0003] A transistor using an oxide semiconductor is manufactured in place of a transistor using silicon. The technology is attracting attention for its application to electronic and optical devices. For example, oxide semiconductors A transistor was fabricated using zinc oxide and In-Ga-Zn-O oxide, and the transistor was used for a display device. Technologies used for pixel switching elements and the like are disclosed in Patent Documents 1 and 2. do. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0005] The transistors that form the channel region in the oxide semiconductor are transistors that use amorphous silicon. The field effect mobility is higher than that of amorphous silicon transistors. The field effect mobility of a sta 2 / Vs, whereas oxide semiconductors The field effect mobility of the transistor used is 10 to 20 cm 2 / Vs is obtained. It is possible to form an active layer using oxide semiconductors by sputtering, etc., and polycrystalline silicon Unlike the transistor used, it can be easily manufactured without using a laser device.

[0006] Using such an oxide semiconductor, a transistor can be formed on a glass substrate or a plastic substrate. This is expected to be applied to liquid crystal displays, organic electroluminescence displays, electronic paper, etc. .

[0007] On the other hand, large display devices are becoming more and more common. Even in home televisions, the diagonal of the display screen is Televisions in the 40- to 50-inch range are also beginning to become popular, and their popularity is expected to accelerate in the future. As mentioned above, transistors using oxide semiconductors are amorphous. Since it has a field effect mobility 10 times higher than that of silicon transistors, it is suitable for large display devices. Even in this case, sufficient performance can be obtained as a pixel switching element.

[0008] However, not only do the pixels form, but the driver circuits also consist of transistors using oxide semiconductors. When trying to configure a semiconductor device using a conventional oxide semiconductor transistor, the performance is insufficient. Specifically, in order to increase the current capacity of a transistor, It is necessary to further increase the field effect mobility by several times. 2 / Vs acid When a driver is constructed using transistors using nitride semiconductors, the size of the display device is The display size is less than 20 inches, and a separate driver is required to configure a display device larger than that. There was a need. [Means for solving the problem]

[0009] One embodiment of the present invention disclosed in this specification is a semiconductor device having a plurality of pixels, a plurality of signal lines, and a plurality of running lines over an insulating substrate. In an active matrix display device having scanning lines, a field effect transfer layer is formed on the insulating substrate. Degree is at least 50cm 2 / Vs or more, preferably 100cm 2 Oxidation with Vs or more a gate driver having a transistor made of a semiconductor material and including the transistor as one of its components; The display device has a source line driving analog switch.

[0010] The display device has a size of at least 20 inches.

[0011] One embodiment of the present invention disclosed in this specification is a semiconductor device having a plurality of pixels, a plurality of signal lines, and a plurality of running lines over an insulating substrate. In an active matrix display device having scanning lines, a field effect transfer layer is formed on the insulating substrate. Degree is at least 50cm 2 / Vs or more, preferably 100cm 2 Oxidation with Vs or more a gate driver having a transistor made of a semiconductor material and including the transistor as one of its components; The display device has a source driver.

[0012] The display device has a size of at least 20 inches.

[0013] One of the means for improving the field effect mobility described above is to form an oxide member on a base member. The crystals grow from the surface toward the inside by heat treatment, and the crystals are at least partially in contact with the base member. forming a first oxide crystal member having a thickness of 100 nm, and stacking a second oxide crystal member on the first oxide crystal member; In particular, a first oxide crystal member and a second oxide crystal member are provided in layers. The first oxide crystal member has a common c-axis. The c-axis is oriented perpendicular to the surface of the material. The elements in the plane are the same. The c-axis direction of the first oxide crystal member is the same in the depth direction. I will.

[0014] In the above-mentioned manufacturing method, the crystal-oriented lower surface of the first oxide crystal member is slightly in contact with the base member. The oxide member is provided in contact with the oxide film in part or in whole. By appropriately adjusting the treatment conditions, the crystal orientation of the lower surface of the first oxide crystal member can be achieved. The surface is provided in contact with the base member at least partially or entirely.

[0015] In the above-mentioned manufacturing method, annealing is performed after the oxide member is formed, and a second oxide film is formed on the upper surface of the oxide member. Then, the first oxide crystal portion and the second oxide semiconductor layer are formed on the first oxide crystal portion. The first oxide crystal portion is grown toward the surface of the second oxide semiconductor layer. The material corresponds to a seed crystal for the second oxide semiconductor layer. It is important that a polycrystalline layer is formed as a component.

[0016] The higher the crystallinity of the oxide semiconductor layer, the higher the field-effect mobility of the transistor. This can be achieved.

[0017] In addition, the higher the crystallinity of the oxide semiconductor layer, the better the transistor Therefore, the amount of change in the threshold voltage can be suppressed, and high reliability can be achieved.

[0018] In addition, the higher the crystallinity of the oxide semiconductor layer, the lower the temperature dependence of the electrical characteristics of the transistor. For example, the amount of change in the on-current or off-current in the temperature range from -30°C to 120°C can be suppressed.

[0019] In the above-mentioned configuration, the oxide crystal member has a crystal having a c-axis orientation in contact with a base member. One of the features of the present invention is that it is a polycrystalline material.

[0020] The technical idea of ​​the present invention is to add a second metal to the oxide semiconductor, but to add a second metal to the oxide semiconductor. By intentionally removing the impurities such as water and hydrogen, the oxide semiconductor itself can be made highly pure. In other words, the water or hydrogen that constitutes the donor level is removed, and then the oxide is formed. By reducing the oxygen vacancy and providing sufficient oxygen to the main component material that constitutes the oxide semiconductor, The first object is to highly purify the oxide semiconductor.

[0021] By forming an oxide semiconductor film, 20 cm -3 Hydrogen at this level is detected by SIMS (secondary ion This is measured by mass spectrometry. The water or hydrogen that causes this donor level is intentionally removed, In addition, oxygen (one of the components of oxide semiconductors) is also reduced when water or hydrogen is removed. ) is added to the oxide semiconductor to purify it and make it electrically i-type (intrinsic). ) semiconductor.

[0022] In addition, in the technical concept of the present invention, the amount of water and hydrogen in the oxide semiconductor is as small as possible. The less carriers there are, the better. In other words, the carrier density is 1×1 0 12 cm -3 less than the measurement limit, more preferably 1.45 × 10 10 cm -3 less than Furthermore, from the viewpoint of the technical concept of the present invention, it is ideal that the value is close to zero or is zero. In particular, oxide semiconductors are treated with oxygen, nitrogen, or ultra-dry air (water content of 20 ppm or less, Preferably, the concentration is 1 ppm or less, and more preferably 10 ppb or less, in air. By performing a heat treatment at 50°C or less, preferably 550°C to 750°C, The pure water or hydrogen can be removed to achieve high purification. By removing impurities such as ZnO, the oxide semiconductor can be highly purified, and the carrier density can be increased. 1×10 12 cm -3 less than the measurement limit, more preferably 1.45 × 10 10 cm - 3 It can be less than.

[0023] Furthermore, the heat treatment is performed at a high temperature of 450°C to 850°C, preferably 600°C to 700°C. In this case, the oxide semiconductor can be highly purified and crystallized. Oxide that grows from the surface of a semiconductor toward the inside and has polycrystalline regions with c-axis orientation It becomes a semiconductor.

[0024] The oxide semiconductor used in the present invention is an oxide semiconductor having a polycrystalline region having the c-axis orientation. The second oxide semiconductor is provided on the seed crystal, and the second oxide semiconductor is grown at a temperature of 450° C. or higher and 850° C. or lower. or by performing heat treatment at a temperature of 550° C. or higher and 750° C. or lower, the second oxide semiconductor is The seed crystal and the second oxide layer can be grown to a polycrystalline region having a c-axis orientation similar to that of the first oxide. Ideal axial growth, or epitaxial growth, in which the c-axes of semiconductors are coaxial, is also required. It is possible to do so.

[0025] In addition, the second oxide semiconductor, which is coaxial with the seed crystal, can be grown by solid phase growth only by heat treatment after film formation. The second oxide semiconductor is formed while being heated at a temperature of 200° C. to 600° C., typically. By sputtering, the crystals can be grown while being deposited. When the substrate is heated to 200° C. or higher and 600° C. or lower during the deposition of the oxide semiconductor film by the CVD method, It can be epitaxially or axially grown.

[0026] Furthermore, by reducing, and preferably eliminating, carriers in the oxide semiconductor, In the transistor, the oxide semiconductor functions as a path through which carriers pass. As a result, oxide semiconductors are highly purified i-type (intrinsic) semiconductors, and have no carriers. By making the amount of the transistor extremely small, the off-state current of the transistor is extremely low. This is the technical concept behind the oxide semiconductor used in the present invention.

[0027] In addition, the oxide semiconductor functions as a path and does not have carriers. If the i-type (intrinsic) is highly purified so that there is no or very little carrier, the carriers will The electron affinity χ and Fermi level of the oxide semiconductor, Ideally, the Fermi level should match the intrinsic Fermi level, and the source and drain electrodes should be By appropriately selecting the work function, carriers can be injected from the source electrode and the drain electrode. This makes it possible to fabricate n-type and p-type transistors appropriately. do.

[0028] The oxide crystal member and the oxide member are all metal oxides and are quaternary metal oxides. In-Sn-Ga-Zn-O films, ternary metal oxide In-Ga-Zn-O films, I n-Sn-Zn-O film, In-Al-Zn-O film, Sn-Ga-Zn-O film, Al-Ga -Zn-O film, Sn-Al-Zn-O system, and In-Zn-O film, which is a binary metal oxide, Sn-Zn-O film, Al-Zn-O film, Zn-Mg-O film, Sn-Mg-O film, In-M Metal oxide films such as Zn-O, In-O, Sn-O, and Zn-O can be used. In addition, for example, the In-Sn-Ga-Zn-O film is a film formed by doping with indium (In) It means an oxide film containing tin (Sn), gallium (Ga), and zinc (Zn). The stoichiometric ratio is not particularly important.

[0029] The oxide crystal member and the oxide member are InMO3(ZnO). m (m>0, and The thin film can be expressed as a sintered material (m is not a natural number), where M is Ga, Al, It represents one or more metal elements selected from the group consisting of Mn and Co. For example, M represents Ga, Examples include Ga and Al, Ga and Mn, or Ga and Co.

[0030] Alternatively, an oxide semiconductor material represented by In-ABO may be used, where A is Group 13 elements such as gallium (Ga) and aluminum (Al), silicon (Si) and germanium (Ge) Represents one or more elements selected from the group 14 elements, such as germanium (Ge). In addition, B is one or more elements selected from the group 12 elements represented by zinc (Zn). Represents an element. The contents of In, A, and B are optional, including the case where the content of A is zero. On the other hand, the contents of In and B are not zero. That is, the above notation includes In-Ga In the present specification, the term In-Ga-Zn-O and In-Zn-O is used. The oxide semiconductor material represented by O is InGaO3(ZnO). m (m>0 and m is natural The fact that m is not a natural number can be confirmed by using ICP-MS analysis and RBS analysis. It can be confirmed.

[0031] In addition, one of the processes for high purification is to use an atmosphere that contains almost no hydrogen or moisture. Under air (nitrogen atmosphere, oxygen atmosphere, dry air atmosphere (for example, moisture dew point -40℃ Hereinafter, the first heat treatment is preferably performed at a temperature of −50° C. or lower (dew point). This process is also called dehydration or dehydrogenation, in which H, OH, and the like are eliminated from the oxide semiconductor layer. The heating process can be performed by heating the material in an inert atmosphere and then switching to an oxygen-containing atmosphere. When the above process is performed or when heat treatment is performed in an oxygen atmosphere, it can be called an oxidation treatment.

[0032] The first heat treatment is a heating method using an electric furnace, and a GRTA (Gas Tunneling and Atomic Radiation) method using heated gas. Rapid Thermal Annealing (LRTA) using lamp light (La Use instantaneous heating methods such as the mp Rapid Thermal Anneal method. In addition, the first heat treatment can be performed simultaneously with heating by irradiating light of 450 nm or less. The oxide semiconductor layer that has been subjected to the first heat treatment for purification may be The thermal desorption spectroscopy (TDS) was performed on the oxide semiconductor layer after the treatment. Even when measurements were taken up to 450°C using CT, at least one of the two water peaks was observed. The heating conditions are such that the single peak that appears around 300°C is not detected. TDS analysis of a transistor using an oxide semiconductor layer that has been subjected to heat treatment for purification Even when measurements were taken up to 450°C, the water peak that appears at around 300°C was not detected. stomach.

[0033] The first heat treatment is performed at a high temperature in order to grow crystals without a polycrystalline layer serving as a seed for crystal growth. It is preferable to heat the substrate at room temperature for a short period of time so that crystal growth occurs only from the surface. When the surface of the oxide semiconductor layer is flat, a good plate-like polycrystalline layer can be obtained. It is desirable that the underlying member, for example the insulating layer or the substrate, be as flat as possible. By increasing the height, it becomes easier to form a polycrystalline layer that contacts the entire surface of the base material, which is useful. For example, the surface roughness is 1μm, which is the same flatness as a commercially available silicon wafer. The height difference in an area of ​​1 m square measured by AFM is 1 nm or less, preferably 0.2 nm. .

[0034] The polycrystalline layer is formed by the In electron clouds in the oxide semiconductor overlapping and connecting with each other. Therefore, a transistor with a polycrystalline layer has a high field effect transfer Mobility can be achieved.

[0035] A method of growing crystals further using the flat polycrystalline layer formed by the first heat treatment as a seed. One example is shown below using Figures 1(A), 1(B), and 1(C).

[0036] The process sequence is as follows: after a first oxide semiconductor layer is formed on a base member, a high-purity The first heat treatment is carried out for the purpose of purifying the material, and the second heat treatment is carried out in the same process as the first heat treatment for the purpose of purifying the material. A polycrystalline layer having a uniform crystal orientation is formed on the surface of the first oxide semiconductor layer, and a second An oxide semiconductor layer is stacked. A second heat treatment is then performed for crystallization. The second oxide semiconductor layer is crystallized using the polycrystalline layer on the surface of the first oxide semiconductor layer as a seed. The procedures are carried out in the following order.

[0037] In the first heat treatment, crystal growth occurs from the surface without the presence of a crystal layer that serves as a seed for crystal growth. In contrast, the second heat treatment allows crystal growth because of the presence of a plate-shaped polycrystalline layer that serves as a seed. It is preferable to heat the mixture at the lowest possible temperature for a long period of time, since this will give good crystallinity. The crystallization direction caused by the heat treatment is from bottom to top and from the substrate side to the surface side (recrystallization direction). The crystal orientation in the first heat treatment is different from that in the first heat treatment. The polycrystalline layer obtained by the process is heated again in a second heat treatment, which further improves the crystallinity. .

[0038] FIG. 1A shows a first oxide semiconductor layer formed on a base member 500. The first heat treatment is performed using oxygen, nitrogen, Or in an ultra-dry air atmosphere, 450°C to 850°C, preferably 550°C to 750°C The heating process is performed at temperatures below 100°C. The temperature is increased in an inert atmosphere, and then changed to an oxygen-containing atmosphere midway. The heat treatment may be performed under an atmospheric air or under an oxygen atmosphere. After the heat treatment, the first oxide semiconductor layer has a c-axis oriented in a direction perpendicular to the surface. This results in first oxide crystal member 501 which is a flat polycrystal.

[0039] FIG. 1B is a cross-sectional view immediately after the formation of the second oxide semiconductor layer 502. The metal oxide semiconductor layer 502 is formed by sputtering, and the metal oxide target is In2O 3:Ga2O3:ZnO=1:1:2 [molar ratio] metal oxide target, In2 A metal oxide target with a molar ratio of O3:Ga2O3:ZnO=1:1:4 was used. That's good.

[0040] FIG. 1C is a cross-sectional view after the second heat treatment. The polycrystalline layer of the oxide crystal member 501 is used as a seed to guide the surface of the second oxide semiconductor layer 502. The crystal grows upwards, forming a second oxide crystal member 503b, and the crystal members are aligned along the c-axis. It has an orientation.

[0041] The second heat treatment also serves to remove H, OH, and the like from the oxide semiconductor layer. This can also be called hydrogenation, where the temperature is raised under an inert atmosphere, then switched to an oxygen-containing atmosphere. When heat treatment is performed under an oxygen atmosphere, it is also called oxidation treatment. You can call.

[0042] In addition, the polycrystalline layer obtained in the first heat treatment is heated again in the second heat treatment, so The resulting third oxide crystal member 503a has significantly improved crystallinity.

[0043] The hydrogen concentration in the oxide semiconductor layer is 1×10 18 cm -3 Below, 1×10 16 cm -3 below, Further, it is preferable that the carrier density of the oxide semiconductor layer is substantially 0. 12 cm -3 less than the measurement limit, more preferably 1.45 × 10 10 cm -3 is less than That is, the carrier density of the oxide semiconductor layer is close to zero. The electron transport energy is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. The hydrogen concentration in the nitride semiconductor layer can be measured by secondary ion mass spectrometry (SIMS). The carrier density can be measured by Hall effect measurement. Carrier density is measured using CV (Capacitance-Voltage-Measurement) It can be calculated from the measurement results of (a) and (b) of Equation 1.

[0044]

number

[0045] In FIG. 1C, a third oxide crystal member 503 is provided on the base member 500. The first oxide crystal member 503a and the second oxide crystal member 503b are laminated in this order. The materials of the crystal member 501 and the second oxide crystal member 503b have a c-axis orientation perpendicular to the surface. As long as the desired polycrystal can be obtained, there is no particular limitation, and different materials may be used. Materials containing the same components may be used. "Containing the same components" means having the same elements. .

[0046] In the case of using an oxide semiconductor material containing the same components, In addition, the boundary between the third oxide crystal member 503a and the second oxide crystal member 503b becomes unclear. This results in a single-layer structure.

[0047] Thus, a laminate of the third oxide crystal member 503a and the second oxide crystal member 503b is obtained. The polycrystalline layer can be grown by two separate heat treatments.

[0048] In FIG. 1A, the surface of the first oxide semiconductor layer is a plate-like layer having a relatively uniform crystal orientation. The plate crystal layer grows in the depth direction from the surface, so it is not affected by the underlying material. It can be formed.

[0049] The first oxide semiconductor layer, for example, an In-Ga-Zn-O film, has a relatively uniform crystal orientation on its surface. The mechanism by which the In-Ga-Zn crystalline layer is formed is explained below as an example. The zinc contained in the -O film diffuses and gathers near the surface, becoming the seed for crystal growth. The length of the crystal growth is greater in the lateral direction (parallel to the surface) than in the depth direction (perpendicular to the surface). Since the crystal growth is stronger than that of the ab plane, a flat polycrystalline layer is formed. The axis direction is the ab plane direction, which is the most likely direction for crystallization. Also, the ab planes of each crystal are aligned. In addition, the area above the surface of the In-Ga-Zn-O film is free space. These results were obtained by measuring TDS up to 450℃. In this case, In and Ga were not detected, but zinc peaks were detected under vacuum heating conditions, especially around 300°C. This is inferred from the fact that it has been confirmed that TDS is released from the atmosphere. It has been confirmed that zinc release is detected at temperatures around 200°C.

[0050] The oxide semiconductor film is formed in two steps, and a polycrystalline layer serving as a seed for crystal growth is formed. By forming the film again and then growing the crystal, a thick plate-like crystal layer can be formed. Nonetheless, the methods disclosed herein are extremely useful.

[0051] In addition, regardless of the material of the base material, the ab plane is parallel to the surface, and the It is also useful to be able to obtain a crystalline layer that has a c-axis orientation.

[0052] In addition, devices using metal oxides, typically In-Ga-Zn-O films, are not suitable for single-crystal Si This is completely different from devices that use silicon carbide, silicon carbide, or GaN. It is.

[0053] Known wide-gap semiconductors are SiC (3.26 eV) and GaN (3.39 eV). However, SiC and GaN are expensive materials. Processing temperatures of 1500°C or higher are required, making it virtually impossible to form a thin film on a glass substrate. It is.

[0054] In addition, SiC and GaN are only available as single crystals, and control by PN junction is required, making it possible to obtain a more complete single crystal. Therefore, there is a possibility that trace amounts of impurities may be mixed in during the manufacturing process. By introducing the electrons, they become donors or acceptors, so there is no lower limit to the carrier concentration. On the other hand, metal oxides can exist in any crystal structure, whether amorphous, polycrystalline, or single crystal. It is possible to use φ without using PN junction control. MS Against χ OS +1 / 2E g OS , φ MD Against χ OS +1 / 2Eg OS and the work functions of the source and drain, and the metal oxide. Using the electron affinity and energy band width of the compound, band control equivalent to a PN junction can be achieved. This is one of the characteristics of metal oxides.

[0055] The band gap of metal oxides, typically In-Ga-Zn-O films, is also approximately equal to that of single crystal silicon. It is three times wider and is a cheaper material than SiC, with lower manufacturing costs.

[0056] The band gap of In-Ga-Zn-O is 3.05 eV. The electron energy distribution f(E) in a solid is given by the following formula: It is known to follow the Mi-Dirac statistics.

[0057]

number

[0058] In ordinary semiconductors where the carrier density is not extremely high (not degenerate), the following relationship holds: do.

[0059]

number

[0060] Therefore, the Fermi-Dirac distribution in equation (1) can be expressed as the Boltzmann distribution in the following equation: is approximated.

[0061]

number

[0062] Using equation (3), we calculate the intrinsic carrier density (n i ) gives the following formula:

[0063]

number

[0064] Then, in equation (4), we add the effective densities of state (Nc, Nv) of Si and In-Ga-Zn-O, The intrinsic carrier density was calculated by substituting the value of the gate gap (Eg). The results are shown in Table 1. .

[0065] [Table 1]

[0066] It can be seen that In-Ga-Zn-O has an extremely low intrinsic carrier density compared to Si. When the band gap of IGZO is selected to be 3.05 eV, the Si and In-Ga-Zn- In O, we assume that the intrinsic carrier concentration approximately follows the Fermi-Dirac distribution law, The former has a carrier density about 10 17 I'd say it's twice as big.

[0067] In addition, oxide semiconductors are formed into thin films by sputtering at temperatures ranging from room temperature to 400°C. The maximum process temperature can be set to 300°C or higher and 800°C or lower. When the maximum temperature of the semiconductor device is set to be equal to or lower than the distortion point of the glass, the semiconductor device can be formed on a large-area glass substrate. Therefore, for industrialization, the maximum process temperature must be between 300℃ and 800℃. It is important to be able to fabricate wide bandgap metal oxides.

[0068] Metal oxides reported so far are either amorphous or polycrystalline. In the past, only single crystals were obtained by treatment at high temperatures of about 1500°C. As described above, after forming the flat-plate polycrystal of the metal oxide, the flat-plate polycrystal of the metal oxide is Thin polycrystalline films with c-axis orientation can be grown at relatively low temperatures by using a seed crystal as a crystal growth medium. If thicker polycrystalline films can be produced, wider industrial applications will be possible. To obtain this, it is preferable that the substrate has high flatness and smoothness. The unevenness causes local c-axis deviation, and as the crystal growth progresses, the c-axis of the neighboring crystals becomes misaligned. This is because any difference in the orientation of the crystals will result in defects such as crystal dislocations. Effect of the Invention

[0069] A transistor using an oxide semiconductor layer having a plate-shaped crystal layer has high field-effect mobility. In addition, a transistor having a low off-state current can be realized. To provide a semiconductor device with low power consumption by realizing a so-called normally-off switching element. This can be done. [Brief description of the drawings]

[0070] [Figure 1] FIG. 1 is a cross-sectional view showing one embodiment of the present invention. [Diagram 2] 1A to 1C are cross-sectional views showing a process of one embodiment of the present invention. [Diagram 3] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 4] 1A to 1C are diagrams illustrating one embodiment of a display device according to one embodiment of the present invention. [Diagram 5] 10A to 10C are diagrams illustrating timing charts of a display device according to one embodiment of the present invention. [Figure 6] 1A to 1C are diagrams illustrating one embodiment of a display device according to one embodiment of the present invention. [Figure 7] FIG. 13 is a diagram showing the delay of a gate line. [Figure 8] FIG. 13 is a diagram showing writing to a source line; [Figure 9] FIG. 1 is a diagram showing an example of a shift register. [Figure 10] FIG. 4 is a diagram showing the timing of a shift register. [Figure 11] FIG. 13 is a diagram showing writing to a source line; [Figure 12] FIG. 13 is a diagram showing writing to a source line; [Figure 13] FIG. 1 is a longitudinal cross-sectional view of a bottom-gate transistor including an oxide semiconductor. [Figure 14] FIG. 14 is an energy band diagram (schematic diagram) taken along the line A-A' of FIG. 13. [Figure 15] (A) shows a state in which a positive potential (+VG) is applied to the gate (G1), and (B) shows a state in which a negative potential (-VG) is applied to the gate (G1). [Figure 16] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 17] 1A to 1C are cross-sectional views showing a process of one embodiment of the present invention. [Figure 18] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 19] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 20] FIG. 1 is a cross-sectional view showing one embodiment of the present invention. [Figure 21] FIG. 1 illustrates an example of an electronic device. [Figure 22] FIG. 1 illustrates an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0071] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0072] (Embodiment 1) An embodiment of the present invention is shown in FIG. 4. FIG. 4(A) shows a pixel section 1502 on a glass substrate 1501. 1503 and 1504 are built in, and an analog switch 150 is used to drive the source line. The display device has a built-in analog switch 1505 for driving the source line. This is for the following reasons. For example, in the case of a full HD display device, the source signal line is 1920xR. If the source driver is not formed on the same board, this terminal The terminals of the source driver are connected to the respective terminals. There was a problem that poor contact of the terminals was likely to occur. Reducing the number of terminals is effective in reducing poor contact. Therefore, an analog switch array is formed on the same substrate, and each terminal of RGB is time-division The purpose is to selectively connect the source driver at each of the four terminals to reduce the number of terminals.

[0073] FIG. 4B shows an equivalent circuit of the analog switch 1505. In the example shown in FIG. The terminals connected to the outside of the display device are 1920 output terminals of the source driver and 1920 switch terminals. The total number of terminals is 1,923, which is about one third of the original number. These are connected to FPCs 1506, 1507, 1508, and 1509. The source driver connected to the log switch runs three times faster than when time-sharing is used. The write time to the source signal line must be reduced by a third. In order to reduce the time required to write to the signal line, the transistors used in the analog switches are It is important to improve the current capability of the

[0074] FIG. 5(A) shows the timing when time division is performed. If the source line writing only needs to be done during one line period, time division is performed. In this case, writing must be done in less than 1 / 3 of one line period. In recent years, display devices have been equipped with 2x, 4x, and other speeds to improve the characteristics of moving images. This is because television broadcasts are at 1x speed, but the frame rate is It creates an image between the frame and the frame, improving the detail of the image.

[0075] For this reason, the display device must operate at 2x or 4x. In FIG. 5(A), the pulse width a of the gate clock is This corresponds to one horizontal line period, and the writing to the source line must be completed within this period. As shown in Fig. 5(B), the value of is 15.3 μs at 1x speed (frame frequency 60 Hz), At 2x speed (frame frequency 120Hz) it is 7.63μs, at 4x speed (frame frequency 24 0Hz) ​​it is 3.81μs.

[0076] The display device must finish writing to the source line within this writing time. These requirements can be met by improving the mobility of semiconductor transistors. This type of display device can be a liquid crystal display device, an organic electroluminescence display device, an electronic paper display device, etc. This is applicable to display devices that are configured using transistors such as those described above.

[0077] (Embodiment 2) FIG. 6 shows an embodiment of a display device with a built-in source driver. A pixel section 1702, gate drivers 1703 and 1704, and a source driver 1706 are disposed on a substrate 1701. This is an example in which the gate drivers 1703 and 1704 and the source driver 1705 are built in. Signals are supplied to 705 via FPCs 1706 and 1707. By placing 1704 on both the left and right sides of the display device and driving the pixels, It is possible to drive it with a driving capacity of 1.

[0078] FIG. 6B shows a glass substrate 1711 on which a pixel section 1712 and a gate driver 1713 are mounted. , 1714, 1715, and 1716 are provided above and below the display device, and source drivers 1717 and 171 This is an example where 8, 1719, and 1720 are arranged on the left and right. Signals are supplied from FPCs 1721, 1722, 1723, and 1724. By positioning the driver, each driver has the capacity to drive 1 / 4 of the display. If the display device has full bi-vision specifications, the driver can If the device has the capability of HD (quarter high vision), it can be driven. The field-effect mobility of a transistor using an oxide semiconductor is improved to 50 cm 2 / Vs or more, preferably 100cm 2 / Vs is a full high-definition TV of about 100 inches. It is also possible to drive a liquid crystal display device at double the speed.

[0079] (Embodiment 3) The calculation results when an analog switch is used to drive the source line are shown below. Assume a 100-inch LCD display device with a frame frequency of 240Hz (4x speed). As mentioned above, at 4x speed, source line writing must be done in 0.7 μs or less. The size of the transistor element used in the sampling analog switch at this time is is L / W=3μm / 1500μm, and the field effect mobility is 100cm 2 / Vs, threshold 1. 5V. The sheet resistance of the source signal line was set to 0.01Ω / □, and the source line resistance was set to 2. The source line potential is expected to be 1.08KΩ, the source line capacitance is 18.5pF, and the line width is 6μm. The goal is to be able to write up to 99.9% of the value.

[0080] Figure 7 shows the relationship between the gate line rise time and the size of the display device. If the upper limit is set to 0.5 μs, the delay time of the gate line will not meet the requirement even if the gate is 100 inches. In this calculation, the sheet resistance of the gate line is 0.1Ω / □ and the capacitance is 41.3pF. , and the line width is 23 μm.

[0081] Figure 8 shows the result of the source line write calculation. While the sampling pulse is high, The input signal and the written source line potential are brought closer together. In Fig. 8, the sampling pulse, the input signal, and the voltage at the point farthest from the input on the source line are As shown in Figure 8, the potential of the source line is 0. This shows that 99.9% of the data can be written in 2 μs. By improving the mobility of the transistor using It has a built-in switch and can drive a 100-inch full HD display device at 4x speed. Here, the size of the display device was assumed to be 100 inches, but this size However, the size is not limited to 100 inches, and a size of 100 inches or less is also possible. By improving the display quality and reducing wiring resistance, a size of 100 inches or more is possible.

[0082] (Embodiment 4) We also show the calculation results when a shift register type source driver is used to drive the source line. The shift register used was a set-reset type shift register as shown in Figure 9. The source driver was assumed to be arranged as shown in FIG. The sampling is 960 points simultaneously. This is one-fourth the area of ​​full HD. To write with one source driver, the sampling points are 960xRGB=28 80 points. To simultaneously sample 960 points, the number of stages of the shift register required is The timing chart is shown in Fig. 10(A). The period in which the source driver clock frequency is set is shown in FIG. 10(B). It is the reciprocal of twice the period of B.

[0083] The required clock frequency is 579kHz when operating the display device at 1x speed, and 579kHz when operating at 2x speed. At 1.15MHz, at 4x speed it is 2.31MHz. The field effect mobility is 100cm 2 / Vs, the shift register can operate under these conditions. The time allowed for loading is 0.43μs at 1x speed, 0.22μs at 2x speed, and 0.4μs at 4x speed. The delay time of the source line is a problem, although there is no problem with the source driver's performance. In this case, the source line condition is 50 inches for a 100 inch display. Since the drive is equivalent to a switch, the sheet resistance of the source signal line is set to 0.01Ω / □ and the source line resistance is set to The resistance was 1.04 KΩ, the source line capacitance was 9.3 pF, and the line width was 20 μm.

[0084] Figure 11 shows the delay time of the source line. In the case of a 100-inch screen, the wiring delay is 30 ns, so Writing must be completed within about 60% of the allowable time. Figure 11 shows the display size of 10 inches and the frame frequency of 4 Here, the data is the most accurate data of the sampling pulse, input signal, and source line. The potential at a point away from the input is shown. Writing is done during the high period of the sampling pulse. The input signal and the source line potential are set to be the same. The input signal reaches 99.9% in about 0.07μs, and the 10-inch model operates at 4x speed. This shows that it is possible.

[0085] Figure 12 shows the results when the frame frequency is 120Hz, double speed, and the display device is 100 inches. The calculation results are shown below. The conditions other than the frequency are the same as above. Here, the sampling pulse and The signal voltage at the input and the source line at the farthest point from the input are shown. The write is performed while the pulse is high, and the input signal and the source line potential are set to the same. It works. It reaches 99.9% in about 0.13μs from the rising edge of the input signal. In this case, even if the display device is 100 inches, 99.9% of the writing can be completed within the specified time. This shows that the mobility is 100 cm 2 / Vs If available, use source driver It is built in and can operate at double speed even when the display size is 100 inches. It becomes Noh.

[0086] (Embodiment 5) In this embodiment, an example of manufacturing a transistor will be described with reference to FIGS.

[0087] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a photomask is applied. A gate electrode layer 401 is provided by a photolithography process using a photoresist.

[0088] The substrate 400 is preferably a glass substrate that can be mass-produced. The glass substrate used as the plate 400 may be distorted if the temperature of the heat treatment to be performed in the subsequent process is high. The substrate 400 may be made of, for example, aluminosilicate. Glass materials such as borosilicate glass, aluminoborosilicate glass, and barium borosilicate glass In addition, it contains more barium oxide (BaO) than boron oxide. By doing so, a more practical heat-resistant glass can be obtained. It is preferable to use a glass substrate containing the same.

[0089] In addition, an insulating layer serving as a base layer may be provided between the substrate 400 and the gate electrode layer 401. The layer has a function of preventing the diffusion of impurity elements from the substrate 400, and is made of silicon nitride, silicon oxide, A laminate structure of one or more layers selected from silicon nitride oxide or silicon oxynitride. It can be formed.

[0090] A metal conductive layer can be used as the gate electrode layer 401. The elements are selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or the elements mentioned above. It is preferable to use an alloy containing the above elements or an alloy combining the above elements. For example, A three-layer stack of an aluminum layer on a titanium layer, and a titanium layer on the aluminum layer. A layer structure, or an aluminum layer on a molybdenum layer and a molybdenum layer on the aluminum layer. Of course, the metal conductive layer may be a single layer or It may be a two-layer structure or a laminated structure of four or more layers. It is preferable to select a material for the pole layer 401 that can withstand the heat treatment temperature.

[0091] Next, a gate insulating layer 402 is formed on the gate electrode layer 401. The gate insulating layer 402 is A silicon oxide layer, a silicon nitride layer, a hafnium oxide layer, etc. are formed by using a plasma CVD method or a sputtering method. A silicon oxynitride layer, a silicon nitride oxide layer, or a silicon nitride oxide layer can be formed as a single layer or a stacked layer. For example, a silicon nitride film and a silicon oxide film are stacked. The thickness of the gate insulating layer 402 is 50 nm or more. The upper limit is 200 nm.

[0092] In this embodiment mode, the gate insulating layer 402 is formed by a high density plasma apparatus. Here, the high-density plasma device is 1×10 11 / cm 3 A plasma density of more than For example, a device that applies microwave power of 3kW to 6kW to generate plasma. This allows the deposition of an insulating film.

[0093] The chamber is filled with monosilane gas (SiH4), nitrous oxide (N2O), and rare gas as material gases. A gas is introduced to generate high-density plasma at a pressure of 10 Pa to 30 Pa, and the plasma is then applied to insulating materials such as glass. An insulating film is formed on a substrate having a surface. Then, the supply of monosilane gas is stopped and the substrate is exposed to air. Nitrous oxide (N2O) and rare gases are introduced to perform plasma treatment on the insulating film surface without exposing it to heat. It may be performed on the surface of the insulating film by introducing at least nitrous oxide (N2O) and a rare gas. The plasma treatment is performed after the formation of the insulating film. It is an insulating film that can ensure reliability even if it is thin, for example, less than 100 nm. .

[0094] When forming the gate insulating layer 402, monosilane gas (SiH4) and nitrogen are introduced into the chamber. The flow ratio of nitrogen oxide (N2O) should be in the range of 1:10 to 1:200. The rare gases introduced into the bar include helium, argon, krypton, and xenon. Among them, it is preferable to use argon, which is inexpensive.

[0095] In addition, the insulating film obtained by the high-density plasma device can be formed with a consistent thickness. The insulating film obtained by the high-density plasma device has excellent step coverage. The thickness can be precisely controlled.

[0096] The insulating film obtained by the above process sequence is different from the insulating film obtained by the conventional parallel plate type PCVD apparatus. The etching rates are significantly different when the same etchant is used. The insulating film obtained by the parallel plate type PCVD equipment is 10% or more or 20% slower and more efficient. The insulating film obtained using a high-density plasma device can be said to be a dense film.

[0097] In this embodiment, the gate insulating layer 402 is formed to a thickness of 100 nm by a high density plasma device. A silicon oxynitride film (also called SiOxNy, where x>y>0) is used.

[0098] Next, a first oxide semiconductor layer having a thickness of 2 nm to 15 nm is formed on the gate insulating layer 402. The first oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere. The gas is spatulated under an oxygen atmosphere or a mixture of a rare gas (typically argon) and oxygen. It can be formed by the TA method.

[0099] In addition, before, during, or after the formation of the oxide semiconductor film, It is preferable to remove the moisture remaining in the sputtering device. For this purpose, it is preferable to use an adsorption type vacuum pump. It is preferable to use an on-pump or titanium sublimation pump. For example, a turbo pump with a cold trap may be used. The deposition chamber of the sputtering apparatus evacuated using the gas is filled with hydrogen atoms, water (H2O), and other hydrogen gases. Since compounds containing atoms are exhausted, the impurities contained in the oxide semiconductor film formed in the deposition chamber are The concentration of pure substances can be reduced.

[0100] In this embodiment, an oxide semiconductor target (In-Ga- Zn-O oxide semiconductor target (In2O3:Ga2O3:ZnO=1:1:2[m The distance between the substrate and the target was 170 mm, the pressure was 0.4 Pa, Direct current (DC) power supply 0.5 kW, oxygen only, argon only, or argon and oxygen atmosphere The first oxide semiconductor layer was formed to a thickness of 5 nm using a SiO 2 gas as the oxide semiconductor target. A target with a composition ratio of In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] or In2O3:Ga2O3:ZnO=1:1:4 [molar ratio] In this embodiment, a target that is intentionally bonded by performing a heat treatment later can be used. In order to crystallize the semiconductor, it is preferable to use an oxide semiconductor target that is easily crystallized.

[0101] The relative density of the oxide semiconductor in the oxide semiconductor target is 80% or more, preferably 9 It is preferable to set the relative density to 5% or more, and more preferably 99.9% or more. By using the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced. A transistor with high characteristics and high reliability can be obtained.

[0102] In addition, before the first oxide semiconductor layer was formed, the inner wall of the sputtering apparatus, the surface of the target, and the -Preheating is performed to remove any moisture or hydrogen remaining in the target material. The preheating process involves heating the inside of the deposition chamber to 200°C to 600°C under reduced pressure. or by repeatedly introducing and exhausting nitrogen or an inert gas while heating.

[0103] Next, the first oxide semiconductor layer is subjected to a first heat treatment to be at least partially crystallized. The temperature of the first heat treatment is 450° C. or more and 850° C. or less. The heating time is 1 minute or more. The first heat treatment is performed for 24 hours or less. A first oxide semiconductor layer 403 is formed (see FIG. 2A). The crystal layer has an ab plane on its surface and has a c-axis orientation perpendicular to the surface. In the embodiment, the first heat treatment causes the first oxide semiconductor layer to become crystalline (CG Here is an example of a crystal that is grown using a ZnO-based ZnSe (also called a co-growing crystal).

[0104] In the first heat treatment, nitrogen, oxygen, helium, neon, argon, or the like is used. It is preferable that the rare gas does not contain water, hydrogen, etc. The purity of nitrogen, oxygen, or rare gas such as helium, neon, or argon is preferably 6N or more. It is preferable to use a dry air atmosphere with H2O of 20 ppm or less. The first heat treatment may be carried out under reduced pressure.

[0105] In this embodiment, the first heat treatment is performed at 700° C. for 1 hour in a dry air atmosphere. Perform processing.

[0106] In addition, the inside of the furnace is in a nitrogen atmosphere during the heating of the first heat treatment, and in an oxygen atmosphere during the cooling. The atmosphere may be switched to a nitrogen atmosphere, and after dehydration or dehydration is performed in a nitrogen atmosphere, Then, the atmosphere is changed to an oxygen atmosphere to supply oxygen to the inside of the first oxide semiconductor layer. It can be made into I type.

[0107] Next, at least a first oxide semiconductor layer 403 was formed on the first oxide semiconductor layer 403 which was a flat polycrystal. A second oxide semiconductor layer 4 having a thickness of 10 μm or less is formed. Note that the thickness of the second oxide semiconductor layer 404 is determined based on the thickness of the oxide semiconductor layer 404. The user can determine the optimum film thickness depending on the device to be manufactured. For example, In the case of manufacturing a transistor, the first oxide semiconductor layer 403 and the second oxide semiconductor layer 4 The total film thickness of 04 is 10 nm or more and 200 nm or less.

[0108] The second oxide semiconductor layer 404 is made of a quaternary metal oxide, In-Sn-Ga-Zn -O film, ternary metal oxide In-Ga-Zn-O film, In-Sn-Zn-O film, In-Al-Zn-O film, Sn-Ga-Zn-O film, Al-Ga-Zn-O film, Sn-A In-Zn-O film, Sn-Zn-O film, and Al-Zn-O film are binary metal oxides. -Zn-O film, Zn-Mg-O film, Sn-Mg-O film, In-Mg-O film, and In-O film For example, an oxide semiconductor film such as a Sn—O film or a Zn—O film can be used.

[0109] The first oxide semiconductor layer 403 and the second oxide semiconductor layer 404 are made of a material containing the same component. Use materials with the same crystal structure and close lattice constants (mismatch of 1% or less). When materials containing the same components are used, the subsequent crystallization In this case, crystal growth can be easily performed using the polycrystalline layer of the first oxide semiconductor layer 403 as a seed. In the case of materials containing the same components, the interface properties such as adhesion and electrical properties are also good. .

[0110] Next, a second heat treatment is performed to grow crystals using the crystal layer of the first oxide semiconductor layer 403 as a seed. The temperature of the second heat treatment is 450° C. or higher and 850° C. or lower, preferably 550° C. or higher. The heating temperature is set to 650°C or less. The heating time is set to 1 minute or more and 24 hours or less. Thus, the second oxide semiconductor layer is crystallized. 30 can be obtained (see Figure 2(C)).

[0111] The plate-like crystal is preferably a single crystal whose c-axis is oriented perpendicular to the surface of the oxide semiconductor layer. In addition, even if the material is not a single crystal, the a-axis and b-axis of each crystal are preferably aligned in the channel forming region. In addition, it is preferable that the oxide semiconductor layer is a polycrystalline body having a c-axis oriented perpendicular to the surface of the oxide semiconductor layer. Note that when the base surface of the oxide semiconductor layer has irregularities, the plate-like crystals become polycrystalline.

[0112] In addition, the steps of FIG. 2(A), FIG. 2(B), and FIG. 2(C) are explained in a generalized manner. In order to clarify the above, enlarged schematic diagrams are shown in FIG. 1(A), FIG. 1(B), and FIG. 1(C).

[0113] FIG. 1A shows a first heat treatment for crystallization on a base member 500. FIG. 1(A) corresponds to FIG. 2(A), and the oxide crystal member 501 is an underlying member. 500 corresponds to the gate insulating layer 402. FIG. 1B corresponds to FIG. 2B. 1C is a cross-sectional view immediately after the deposition of the second oxide semiconductor layer 502. FIG. 1C is a cross-sectional view of the semiconductor device after the second heat treatment. The third oxide crystal member 503a is made of a crystal layer having a higher degree of orientation. When the first oxide member and the second oxide member are made of oxide semiconductor materials containing the same components, As shown in FIG. 1(C), the second oxide crystal member 503a is grown on the crystal layer of the third oxide crystal member 503a as a nucleus. The crystals grow upwards towards the surface of the member, forming a second oxide crystal member 503b. The crystal members have a c-axis orientation. Therefore, the third oxide layer is shown by the dotted line in FIG. 1(C). The boundary between the first oxide crystal member and the second oxide crystal member becomes unclear. As a result, the inside of the second oxide member immediately after the film formation is highly purified and becomes a layer containing amorphous matter.

[0114] Next, an oxide semiconductor stack 43 including a first oxide semiconductor layer and a second oxide semiconductor layer is formed. 0 is processed into an island-shaped oxide semiconductor stack 431 by a photolithography process (FIG. 2(D) ). In addition, a resist mask for forming the island-shaped oxide semiconductor stack 431 was If the resist mask is formed by the inkjet method, the photoresist can be formed by the inkjet method. Since no mask is used, manufacturing costs can be reduced.

[0115] Next, the gate insulating layer 402 and the island-shaped oxide semiconductor stack 431 are formed by a sputtering method or the like. After forming a metal conductive film, a resist mask is formed by a photolithography process. Selective etching is performed to form the metal electrode layer.

[0116] Metal conductors that will later become source and drain electrodes (including wiring formed in the same layer) The material of the conductive film is a metal material such as Al, Cu, Cr, Ta, Ti, Mo, or W, or The metal layer is made of an alloy material containing the metal material. A high melting point metal layer such as Cr, Ta, Ti, Mo, or W is laminated on one or both sides of the upper surface. In addition, Si, Ti, Ta, W, Mo, Cr, Nd, Sc, Y, etc. l) Uses an Al material that contains elements that prevent the formation of hillocks and whiskers in the film. This makes it possible to improve heat resistance.

[0117] For example, the metal conductive film may be a titanium layer, an aluminum layer on the titanium layer, and a titanium film on the aluminum layer. A three-layer laminate structure in which a titanium layer is laminated on a molybdenum layer, or an aluminum layer on a molybdenum layer and the aluminum layer on the molybdenum layer It is preferable to use a three-layer laminate structure in which a molybdenum layer is laminated on a gold layer. The metal conductive film is a two-layer laminated structure of an aluminum layer and a tungsten layer, and the other is a copper layer and a tungsten layer. Two-layer laminated structure with a tin layer and a molybdenum layer, two-layer laminated structure with an aluminum layer and a molybdenum layer It is also possible to use a laminated structure. Of course, the metal conductive film may be a single layer or a laminated structure of four or more layers. It is also possible to use the following.

[0118] Next, the resist mask is removed, and a resist mask is formed by a photolithography process. Then, the source electrode layer 405a and the drain electrode layer 405b are formed by selectively etching the source electrode layer 405a and the drain electrode layer 405b. After the formation, the resist mask is removed (see FIG. 2(E)). In the roughening process, only a part of the island-shaped oxide semiconductor stack 431 is etched, and the groove (concave) is formed. In some cases, the oxide semiconductor layer may have a gate insulating film.

[0119] As shown in FIG. 2E, the gate electrode layer 401 is connected to a source electrode layer 405a (or Another feature is that the source electrode layer has a region overlapping with the drain electrode layer 405b. The edge of 405a and the step of the gate insulating layer 402, that is, the flat surface of the gate insulating layer in the cross-sectional view, The area between the point where the flat surface changes to the tapered surface (here, the L shown in Figure 2(E)) OV territory L OV The region is located at the grain boundary caused by the unevenness of the edge of the gate electrode layer. This is important to keep the rear from drifting.

[0120] In addition, the source electrode layer 405a or the drain electrode layer 405b is formed on the side surface of the oxide semiconductor stack 432. The crystal layer in contact with the electrode layer 405b may become amorphous.

[0121] In addition, a resist pattern for forming the source electrode layer 405a and the drain electrode layer 405b was formed. The resist mask may be formed by an ink-jet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0122] In order to reduce the number of photomasks and steps used in the photolithography process, The resist pattern is formed by a multi-tone mask, which is an exposure mask that allows the light to be projected at multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further changed by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. The corresponding photolithography process can also be eliminated, making it possible to simplify the process.

[0123] Next, an oxide insulating layer 407 serving as a protective insulating film in contact with part of the oxide semiconductor layer is formed. .

[0124] The oxide insulating layer 407 has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The layer 407 can be formed by appropriately using a method that does not allow impurities such as water and hydrogen to be mixed into the layer 407 . In this embodiment, a silicon oxide film having a thickness of 300 nm is formed as the oxide insulating layer 407 by a sputtering method. The substrate temperature during film formation may be set to room temperature or higher and 300° C. or lower. The temperature is set to 100°C in this embodiment. The deposition of silicon oxide film by sputtering method is performed using rare gas (typically a In a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixture of rare gas (typically argon) and oxygen. The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used to emit oxygen and nitrogen. Silicon oxide can be formed by sputtering in a low-resistance oxide semiconductor. The oxide insulating layer 407 formed in contact with the substrate layer is made of an inorganic insulating film, typically a silicon oxide film. A silicon nitride oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like is used. Furthermore, a protective insulating layer such as a silicon nitride film or an aluminum nitride film is formed on the oxide insulating layer 407. It may be possible to do so.

[0125] In addition, the oxide insulating layer 407 and the gate insulating layer 402 are A contact hole is formed through the gate electrode layer 401, and the contact hole is electrically connected to the gate electrode layer 401 to apply a gate potential. A connection electrode for forming the gate insulating layer 402 may be formed over the oxide insulating layer 407. After that, a contact hole is formed to reach the gate electrode layer 401, and a source electrode layer or A connection electrode is formed from the same material as the drain electrode layer, and an oxide insulating layer 407 is formed on the connection electrode. Then, a contact hole reaching the connection electrode is formed in the oxide insulating layer 407. An electrode for applying a gate potential is formed on the oxide insulating layer 407. It may be possible to do so.

[0126] Through the above steps, a transistor 470 is formed (see FIG. 3B). 3B illustrates an example of a top view of the transistor 470. Note that FIG. 3B illustrates the transistor 470 along the dashed line C in FIG. This corresponds to the cross-sectional view taken along line 1-C2.

[0127] In the transistor 470, the upper surface of the gate electrode layer in the channel formation region is flattened. The source electrode layer or the drain electrode layer has an oxide member with a c-axis oriented perpendicular to the Another feature is that the oxide layer overlaps the unevenness caused by the edge of the gate electrode layer. In the present embodiment, the oxide semiconductor member (the oxide semiconductor stack 432) is used to prevent unevenness in the substrate. The grain boundary is in the region where the recesses collide, resulting in a polycrystal. By forming the v region, the carriers are transferred to the grain boundaries caused by the unevenness of the edge of the gate electrode layer. Therefore, in the transistor 470, the source The electrode layer or the drain electrode layer is provided over the flat portion of the gate electrode. It has a polar layer and an overlap.

[0128] It is needless to say that the structure of the transistor 470 shown in FIG. No. A top-gate transistor or a bottom-gate transistor is sufficient. For example, the etching damage during the formation of the source electrode layer and the drain electrode layer in FIG. 2(E) can be prevented. In order to protect the channel, an oxide insulating layer overlapping the channel formation region is provided as a channel stopper. A channel stop type transistor may be used.

[0129] In addition, an electrode layer capable of functioning as a back gate is provided over the oxide insulating layer 407. The potential of the back gate may be a fixed potential, for example, 0 V or a ground potential. The implementation can be appropriately determined. In addition, by controlling the gate voltage applied to the back gate, The threshold voltage can be controlled by the In addition, the threshold voltage can be set to negative. For example, the enhancement transistor can be used as a depletion transistor. The inverter circuit (hereafter called the The driver circuit can be configured as an EDMOS circuit. The logic circuit section includes at least one of a switch section and a buffer section. The circuit configuration includes an OS circuit.

[0130] The operating principle of a bottom-gate transistor using an oxide semiconductor is described below. Reveal.

[0131] FIG. 13 is a longitudinal cross-sectional view of a transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on the gate insulating film (GI) via the gate insulating film. A source electrode (S) and a drain electrode (D) are provided. An oxide insulating layer overlapping the channel formation region of the oxide semiconductor layer (OS) on the drain electrode (D) It has.

[0132] FIG. 14 shows an energy band diagram (schematic diagram) in the cross section taken along line AA' shown in FIG. FIG. 14(A) shows the case where the voltage between the source and drain is equipotential (VD=0V). FIG. 14(B) shows the case where a positive potential (VD>0) is applied to the drain with respect to the source. In Fig. 7, black circles (●) represent electrons and white circles (○) represent holes, each of which has a charge (-q, +q).

[0133] FIG. 15 shows an energy band diagram (schematic diagram) in the cross section taken along line B-B' in FIG. FIG. 15(A) shows the state when the gate voltage is 0V. +VG) is applied, and carriers (electrons) flow between the source and drain. FIG. 15B shows the state where a negative potential (−VG) is applied to the gate (G1). 4 shows the case where the transistor is turned on and in the off state (no minority carriers flow).

[0134] The thickness of the oxide semiconductor is about 50 nm, and the oxide semiconductor is highly purified, so The concentration of toner is 1×10 18 / cm 3 If the temperature is less than 1000° C., the depletion layer will spread over the entire oxide semiconductor. In other words, it can be regarded as a fully depleted state.

[0135] Figure 16 shows the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). Indicates the relationship.

[0136] Since metals are degenerate, the conduction band and the Fermi level coincide. Semiconductors are generally n-type, in which case the Fermi level (Ef) is located in the middle of the band gap. It is located away from the intrinsic Fermi level (Ei) and closer to the conduction band. It is known that hydrogen is a donor in semiconductors and is one of the factors that cause them to become n-type.

[0137] In contrast, the oxide semiconductor according to the present invention can remove n-type impurities, such as hydrogen, from the oxide semiconductor. By removing impurities from the oxide semiconductor, the oxide semiconductor is highly purified so that it contains as few impurities as possible other than the main component. It is more pure (type I) or is intended to be pure. By removing impurities such as hydrogen and water as much as possible, the product is highly purified. The characteristic of this is that it is an I-type (intrinsic semiconductor) or close to it. The Fermi level (Ef) can be made to be the same as the intrinsic Fermi level (Ei).

[0138] Oxide semiconductors have a band gap (Eg) of 3.05 eV to 3.15 eV. When the band gap (Eg) of an oxide semiconductor is 3.15 eV, the electron affinity (χ) The source and drain electrodes are made of titanium (Ti). The charge function is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, At the interface between the two layers, no Schottky barrier is formed for electrons.

[0139] In other words, when the work function of the metal (φM) is equal to the electron affinity of the oxide semiconductor (χ), When the two come into contact, an energy band diagram (schematic diagram) like that shown in FIG. 14(A) is shown.

[0140] In FIG. 14(B), the black circles (●) represent electrons. When a positive potential is applied to the drain, Electrons cross the barrier (h) and are injected into the oxide semiconductor, where they flow toward the drain. In the case of a positive drain, the barrier height (h) changes depending on the gate voltage and the drain voltage. When a rain voltage is applied, the barrier height in FIG. 14(A) without voltage application, i.e. The barrier height (h) is smaller than half the band gap (Eg).

[0141] At this time, the electrons pass through the gate insulating film and the highly purified oxide semiconductor as shown in FIG. The electrons move through the lowest energetically stable portion on the oxide semiconductor side at the interface with the body.

[0142] In FIG. 15B, a negative potential (reverse bias) is applied to the gate electrode (G1). When the current is increased, the number of holes, which are minority carriers, is essentially zero, so the current approaches zero. The value becomes

[0143] In this way, the oxide semiconductor is highly purified so that impurities other than the main component are not included as much as possible. By making it intrinsic (I type) or substantially intrinsic, the interface characteristics with the gate insulating film are improved. Therefore, it is necessary to consider the gate insulating film separately from the bulk characteristics. For example, the VHF band to Insulating film produced by CVD using high-density plasma generated at power supply frequencies in the microwave range Alternatively, it is preferable to use an insulating film formed by a sputtering method.

[0144] The oxide semiconductor is highly purified while maintaining a good interface between the oxide semiconductor and the gate insulating film. By doing so, the transistor characteristic channel width W is 1×10 4Channel length in μm Even with a 3 μm element, the off-current is 10 -13 A or less, and subthreshold The switching value (S value) is 0.1V / dec. (gate insulating film thickness 100nm) It is fully expected.

[0145] In this way, the oxide semiconductor is highly purified so that impurities other than the main component are not included as much as possible. This allows a transistor with high mobility to be formed, improving the operation of the transistor. It is possible.

[0146] (Embodiment 6) In the fifth embodiment, the first oxide member and the second oxide member contain the same component. In this embodiment, a case where an oxide semiconductor material having a different composition is used is described. Indicates the combination.

[0147] In this embodiment, a metal oxide tertiary oxide having an In:Zn=1:1 [atomic ratio] containing no Ga is used. An example in which a bottom gate type oxide semiconductor layer is formed to a thickness of 5 nm is shown. In the case of forming a transistor, since an oxide of Ga is an insulator, Therefore, the field effect transfer was improved by using the In-Zn-O film rather than the In-Ga-Zn-O film. The degree can be increased.

[0148] Next, a first heat treatment is performed. Depending on the materials of the first oxide semiconductor layer and the base member 520 and the heating temperature, The first heat treatment causes crystal growth from the surface, depending on the temperature, heating time, and other conditions. The first oxide crystal member 531, which is polycrystalline, is formed up to the interface with the base member 520 (FIG. 17). See (A). ).

[0149] Examples of the base member 520 include an oxide layer, a metal layer, and a nitride layer. The heat treatment produces a relatively crystalline layer on the surface of the first oxide semiconductor layer, regardless of the material of the base member. The first oxide crystal member 531, which is a polycrystal with a uniform orientation, grows in the depth direction from the surface. In addition, the first oxide crystal member 531 has a c-axis oriented in a direction perpendicular to the surface. .

[0150] Next, FIG. 17(B) shows a process in which a second oxide member 532 is formed on the first oxide crystal member 531. In this embodiment, the second oxide member 532 is an In- Ga-Zn-O oxide semiconductor target (In2O3:Ga2O3:ZnO=1:1: 2 [molar ratio]) to form a 50 nm thick In-Ga-Zn-O film.

[0151] After the second oxide member 532 is formed, a second heat treatment is performed. As shown in FIG. 17(C), the crystal growth is performed. The crystal layer of the first oxide crystal member 531 is used as a seed to grow upward toward the surface of the second oxide member. Crystal growth occurs and the second oxide crystal member 533b is formed.

[0152] The first oxide crystal member 531 obtained by the first heat treatment is again heated by a second heat treatment. As a result of being heated, the crystallinity of the third oxide crystal member 533a is further improved.

[0153] The second oxide crystal member 532 is an oxide semiconductor having a different composition from that of the first oxide crystal member 531. In order to use a conductive material, as shown in FIG. 17(C), the third oxide crystal member 533a and the The second heat treatment also forms a boundary between the oxide crystal members 533b. Most of the first oxide semiconductor layer, including the vicinity of the interface with the gate insulating layer, is polycrystalline.

[0154] The structure of FIG. 17C includes a first oxide crystal member 533a and a second oxide crystal member 533b on a base member 520. The oxide crystal member 533b is laminated in this order. This can increase the field effect mobility of the transistor. By using an In-Zn-O film, which is easier to crystallize than a Zn-O film, as a seed for crystal growth, The crystal growth can be efficiently performed in the upward direction, and the In-Ga-Zn-O film can be made polycrystalline. do.

[0155] In addition, when the second oxide crystal material to be grown is the same as the first oxide crystal material to be the base, This is called homoepitaxy. The second oxide crystal material to be grown and the first oxide crystal material to be grown are called homoepitaxy. When the oxide crystal materials are different, it is called heteroepitaxy. Depending on the material selected, either is possible.

[0156] The conditions of the first heat treatment and the second heat treatment are within the ranges of conditions described in the fifth embodiment. do.

[0157] In addition, this embodiment mode can be freely combined with the fifth embodiment mode.

[0158] (Embodiment 7) In this embodiment, a transistor is fabricated that includes a laminated oxide material having a c-axis oriented crystal layer. A semiconductor device having a display function is provided by using the transistor in a pixel portion and further in a driver circuit. A case where a transistor is used as a driving circuit (also called a display device) will be described. A part or the whole of the circuit is formed on the same substrate as the pixel section to form a system on panel. This can be done.

[0159] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0160] The display device also includes a panel in which the display element is sealed. An element substrate corresponding to one form before the display element is completed in the process of manufacturing the display device. Regarding the display device, the device substrate comprises means for each of a plurality of pixels for supplying a current to the display element. Specifically, the element substrate may be in a state where only pixel electrodes of the display elements are formed, After forming the conductive layer that will become the pixel electrode, but before etching to form the pixel electrode. It can be in any form, and any shape is applicable.

[0161] In this specification, the display device refers to an image display device or a display device.

[0162] In this embodiment, a liquid crystal display device will be described as an example of a semiconductor device which is one embodiment of the present invention. First, the appearance and cross section of a liquid crystal display panel, which corresponds to one embodiment of a semiconductor device, will be described with reference to FIG. FIG. 18A shows a c-axis oriented crystal layer formed on a first substrate 4001. The transistors 4010 and 4011 include a stacked oxide material having the following structure as a semiconductor layer: A crystal element 4013 is sealed between a second substrate 4006 and a sealing material 4005. 18(B) is a cross-sectional view taken along line MN in FIG. 18(A). .

[0163] A pixel portion 4002, a signal line driver circuit 4003, and a scanning A sealant 4005 is provided so as to surround the line driver circuit 4004. A second substrate 4002 is disposed on the signal line driver circuit 4003 and the scanning line driver circuit 4004. 006 is provided. Therefore, the pixel portion 4002, the signal line driver circuit 4003, and the scanning line The driver circuit 4004 is formed on a first substrate 4001, a sealant 4005, and a second substrate 4006. Therefore, it is sealed together with the liquid crystal layer 4008 .

[0164] A pixel portion 4002 and a signal line driver circuit 4003 are provided on a first substrate 4001. The scanning line driver circuit 4004 has a plurality of transistors. A transistor 4010 included in the scanning line driver circuit 4002 and a transistor The transistors 4010 and 4011 are illustrated. An insulating layer 40 is formed on the transistors 4010 and 4011. 20, 4021 are provided.

[0165] The transistors 4010 and 4011 have a c-axis oriented crystal layer as described in the fifth embodiment. A transistor including a stacked oxide material can be used. The transistors 4010 and 4011 are n-channel transistors.

[0166] The oxide semiconductor layer of the transistor 4011 for the driver circuit is formed over the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping the panel formation region. By providing the semiconductor layer at a position overlapping the channel formation region, It is possible to reduce the amount of change in the threshold voltage of the transistor 4011. The potential of the gate electrode layer of the transistor 4011 may be the same as that of the gate electrode layer of the transistor 4011 or may be different. The conductive layer 4040 may also function as a second gate electrode layer. The potential may be GND, 0V, or may be floating.

[0167] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are overlapped. The portion where the pixel electrode layer 4030 is formed corresponds to the liquid crystal element 4013. The layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between layers 4032 and 4033 .

[0168] The second substrate 4006 can be made of glass or plastic. The stick is made of FRP (Fiberglass-Reinforced Plast ics) plate, PVF (polyvinyl fluoride) film, polyester film or Acrylic resin film can be used. Aluminum foil can also be used with PVF film. Alternatively, a sheet having a structure sandwiched between two films such as polyester film may be used.

[0169] Also, 4035 is a columnar spacer obtained by selectively etching the insulating layer. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031, A spherical spacer may be used. 1 is electrically connected to a common potential line provided on the same substrate as the transistor 4010. In addition, the common connection portion is used to connect the opposing electrode layer via conductive particles disposed between the pair of substrates. The conductive particles can be used as a sealing material. Include in 4005.

[0170] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. Since the liquid crystal display is optically isotropic, no alignment treatment is required, and the viewing angle dependency is small.

[0171] In addition, if a liquid crystal that exhibits a blue phase is used, rubbing treatment of the alignment film is not required. This prevents electrostatic damage caused by the soldering process, and prevents the LCD display from being damaged during the manufacturing process. This reduces the number of defects and damages to the device, thereby improving the productivity of liquid crystal display devices. In particular, a transistor including an oxide semiconductor layer can be easily damaged by static electricity. The electrical characteristics of the transistor may vary significantly and deviate from the design range. A liquid crystal display device having a transistor using a blue phase liquid crystal material is provided. is more effective.

[0172] Note that the liquid crystal display device shown in this embodiment is an example of a transmission type liquid crystal display device. The device can be applied to both a reflective liquid crystal display device and a semi-transmissive liquid crystal display device.

[0173] In the liquid crystal display device shown in this embodiment mode, a polarizing plate is provided on the outer side (the viewing side) of the substrate. In this example, a colored layer and an electrode layer for use in a display element are provided on the side of the substrate in this order. The laminated structure of the polarizing plate and the colored layer is not limited to the embodiment, and the polarizing plate may be provided in the same manner. The thickness may be appropriately set depending on the material of the colored layer and the manufacturing process conditions. A light-shielding layer that functions as a light-shielding matrix may be provided.

[0174] In this embodiment, in order to reduce the surface unevenness of the transistor and To improve reliability, the transistor is covered with an insulating layer ( The insulating layer 4020 and the insulating layer 4021 are used to cover the insulating layer. It is designed to prevent the intrusion of airborne organic matter, metals, water vapor and other contaminating impurities. The protective layer is preferably a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like, which is formed by sputtering. A silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer The insulating film 11 may be formed of a single layer of aluminum oxide or a single layer of aluminum nitride oxide. Although the protective layer is formed by sputtering in the example shown, the method is not particularly limited and may be formed by various methods. stomach.

[0175] Here, an insulating layer 4020 having a laminated structure is formed as a protective layer. A silicon oxide layer is formed as the first layer of the first insulating film by sputtering. By using the above, it is possible to prevent hillocks on the aluminum layer used as the source electrode layer and the drain electrode layer. It is effective in stopping.

[0176] In addition, an insulating layer is formed as the second layer of the protective layer. A silicon nitride layer is formed by sputtering. When a silicon nitride layer is used as a protective layer, Ions such as thorium penetrate into the semiconductor region and change the electrical properties of the transistor. It is possible to suppress the above.

[0177] In addition, an insulating layer 4021 is formed as a planarizing insulating layer. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. are used. In addition, by laminating multiple insulating layers made of these materials, 4021 may be formed.

[0178] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0179] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, In the step of bonding, the semiconductor layer may be annealed (at 300° C. to 400° C.) at the same time. By combining the firing process of the edge layer 4021 with the annealing process of the semiconductor layer, a semiconductor device can be efficiently manufactured. It becomes possible to do so.

[0180] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material may be used.

[0181] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0182] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0183] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0184] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. 30, and the terminal electrode 4016 is formed from the same conductive layer as the transistors 4010, 4011. The source electrode layer and the drain electrode layer are formed from the same conductive layer as the source electrode layer and the drain electrode layer.

[0185] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive layer 4019. The electrodes are electrically connected to each other.

[0186] In FIG. 18, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. However, the present embodiment is not limited to this configuration. The pixel portion 4002 may be formed and mounted on the same substrate as the pixel portion 4002, or may be mounted as a part of a signal line driver circuit or Alternatively, only a part of the scanning line driver circuit may be formed and mounted on the same substrate as the pixel portion 4002 .

[0187] If necessary, a color filter is provided for each pixel. A polarizing plate and a diffusing plate are provided on the outside of the first and second substrates 4001 and 4006. The source is composed of cold cathode fluorescent lamps and LEDs, forming a liquid crystal display module.

[0188] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0189] Through the above steps, a highly reliable liquid crystal display device can be manufactured.

[0190] In addition, the method for producing a laminated oxide material having a c-axis oriented crystal layer shown in the fifth embodiment is used. By fabricating a transistor for a driving circuit of a liquid crystal display device using the This allows the starter to be normally off, thereby saving power.

[0191] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0192] (Embodiment 8) The appearance and cross section of a light-emitting display panel (also called a light-emitting panel) which corresponds to one form of a semiconductor device This will be described with reference to FIG. 19. FIG. 19(A) shows a c-axis oriented crystal formed on a first substrate. A transistor and a light-emitting element including a laminated oxide material having a crystal layer formed on a second substrate are FIG. 19(B) is a plan view of the panel sealed with a sealant between the panels. This corresponds to the cross-sectional view taken along line HI of FIG.

[0193] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0194] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of transistors. In FIG. 19B, a transistor 4510 included in a pixel portion 4502 and a signal line driver A transistor 4509 included in the circuit 4503a is illustrated.

[0195] The transistors 4509 and 4510 have a c-axis oriented crystal layer as described in the fifth embodiment. A highly reliable transistor including a laminated oxide material can be applied. In this figure, the transistors 4509 and 4510 are n-channel transistors.

[0196] A channel of an oxide semiconductor layer of a transistor 4509 for a driver circuit is formed over an insulating layer 4544. A conductive layer 4540 is provided in a position overlapping with the hole formation region. By placing the conductor layer at a position that overlaps with the channel formation region, The amount of change in the threshold voltage of the transistor 4509 can be reduced. 40 may have the same potential as the gate electrode layer of the transistor 4509 or may have a different potential. Alternatively, the conductive layer 4540 may function as a second gate electrode layer. may be GND, 0V, or floating.

[0197] The transistor 4509 is in contact with a semiconductor layer including a channel formation region as an insulating layer. The insulating layer 4541 is the oxide insulating layer 441 shown in Embodiment 5. The same materials and methods as those used in 07 may be used. In this embodiment, the insulating layer 4544 is covered with the insulating layer 4544, which functions as a planarizing insulating layer. The oxide insulating layer 407 described in Embodiment 5 is used as the edge layer 4541 by a sputtering method. A silicon oxide layer is formed.

[0198] In addition, an insulating layer 4544 is formed as a planarization insulating layer over the insulating layer 4541. The insulating layer 44 may be formed of the same material and by the same method as the insulating layer 4021 shown in the seventh embodiment. Here, acrylic is used as the insulating layer 4544.

[0199] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. The light emitting element 4511 is configured with a first electrode layer 4517, an electroluminescent layer 45 12, the second electrode layer 4513 has a stacked structure, but is not limited to the structure shown. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from 4511. This can be done.

[0200] The partition 4520 is formed using an organic resin layer, an inorganic insulating layer, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0201] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0202] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer A protective layer may be formed over 4513 and the partition wall 4520. The protective layer may be a silicon nitride layer, A silicon oxynitride layer, a DLC layer, or the like can be formed.

[0203] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0204] The connection terminal electrode 4515 is a conductive layer that is the same as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from the source voltages of the transistors 4509 and 4510. The positive electrode layer and the drain electrode layer are formed from the same conductive layer.

[0205] The connection terminal electrode 4515 is connected to a terminal of the FPC 4518a via an anisotropic conductive layer 4519. The electrodes are electrically connected to each other.

[0206] The second substrate is not transparent to light, and is located in the direction of light extraction from the light emitting element 4511. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0207] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's good.

[0208] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0209] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured.

[0210] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0211] (Embodiment 9) An example of electronic paper will be shown as one mode of a semiconductor device.

[0212] The laminated oxide material having a c-axis oriented crystal layer obtained by the method shown in the fifth embodiment includes The transistors used in the design drive electronic ink by using elements that are electrically connected to switching elements. The electronic paper may be used for an electrophoretic display device (electrophoretic display). It is also called a digital display, and has the same readability as paper, low power consumption compared to other display devices, This has the advantage that it can be made thin and lightweight.

[0213] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. In addition, the first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0214] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0215] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0216] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. For example, the c-axis oriented liquid crystal of the fifth embodiment Active matrix obtained by transistors including laminated oxide materials having crystalline layers A substrate can be used.

[0217] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0218] FIG. 20 shows an active matrix type electronic paper as an example of a semiconductor device. The transistor 581 used in the device is the same as the transistor described in Embodiment 5. The transistors can be fabricated easily and have high reliability, including stacked oxide materials with c-axis oriented crystal layers. It is.

[0219] The electronic paper in FIG. 20 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0220] The transistor 581 is a bottom-gate transistor, and an insulating layer in contact with a semiconductor layer The source electrode layer or the drain electrode layer of the transistor 581 is covered with a first The electrode layer 587 is in contact with the insulating layers 583 and 585 through openings and is electrically connected. Between the first electrode layer 587 and the second electrode layer 588, there are a black area 590a and a white area A spherical particle 589 having a region 590b and including a cavity 594 filled with liquid around it. The spherical particle 589 is surrounded by a filling material such as resin. It is filled with filler material 595 (see FIG. 20).

[0221] The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is a common potential The conductive particles disposed between the pair of substrates are electrically connected to the wires by using a common connection portion. The second electrode layer 588 and a common potential line can be electrically connected via the insulating layer 586 .

[0222] Also, instead of the twist ball, an electrophoretic element can be used. and a 10μm to 20μm diameter nanoparticle that contains positively charged white nanoparticles and negatively charged black nanoparticles. Microcapsules with a diameter of about 0 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, the microcapsules emit white light. White particles and black particles move in opposite directions, allowing the display to be white or black. A display element that applies this principle is an electrophoretic display element, commonly known as electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display, the image that was displayed can be retained. Therefore, a semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0223] Through the above steps, highly reliable electronic paper can be manufactured.

[0224] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0225] (Embodiment 10) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames; mobile phones (also called mobile phones or mobile phone devices); Examples include game machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. do.

[0226] In this embodiment, an electronic device equipped with the display device obtained in any one of the seventh to ninth embodiments is provided. An example of the device will be described with reference to FIGS.

[0227] FIG. 21(A) shows a notebook-type PC manufactured by mounting at least a display device as one component. A personal computer, comprising a main body 3001, a housing 3002, a display unit 3003, and a keyboard. The liquid crystal display device shown in the seventh embodiment is configured as a notebook PC. The type of personal computer has

[0228] FIG. 21(B) shows a portable information terminal ( The main body 3021 is a display unit 3023 and an external interface 3025. , operation buttons 3024, etc. are provided. In addition, a stylus 302 is provided as an accessory for operation. Note that the portable information terminal has the light-emitting display device described in Embodiment 8.

[0229] FIG. 21C shows an electronic device manufactured by mounting the electronic paper shown in the ninth embodiment as one component. FIG. 21C shows an electronic book 2700. For example, the electronic book 270 The 0 is composed of two housings, a housing 2701 and a housing 2703. The housing 2703 is integrated into one electronic device by the shaft 2711. This structure allows the book to be opened and closed like a paper book. It becomes possible to carry out the following.

[0230] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display unit (display unit 2705 in FIG. 21C) and An image can be displayed on the display portion (the display portion 2707 in FIG. 21C).

[0231] FIG. 21C shows an example in which an operating unit and the like are provided in the housing 2701. For example, The housing 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. A keyboard and a pointing device may be provided on the rear of the housing. On the front or side, there are terminals for external connections (earphone terminal, USB terminal, or AC adapter and USB Equipped with a terminal that can be connected to various cables such as USB cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to function as an electronic dictionary. It is also possible to use the following.

[0232] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0233] FIG. 21(D) shows a mobile phone manufactured by mounting at least a display device as a part. The device is made up of two housings, a housing 2800 and a housing 2801. The housing 2801 has a front A display panel 2802, a speaker 2803, a microphone 2804, a pointing device The camera includes a seat 2806, a camera lens 2807, and an external connection terminal 2808. The housing 2801 includes a solar cell 2810 for charging the portable information terminal, an external memory storage The antenna is built into the housing 2801. .

[0234] The display panel 2802 is equipped with a touch panel, and in FIG. The multiple operation keys 2805 are indicated by dotted lines. It also implements a boost circuit to boost the input voltage to the voltage required for each circuit.

[0235] The display direction of the display panel 2802 changes appropriately depending on the usage mode. The camera lens 2807 is located on the same surface as the camera 2802, so video calls are possible. The speaker 2803 and the microphone 2804 are not limited to voice calls, but can also be used for video calls. , recording, playback, etc. are possible. Furthermore, the housing 2800 and the housing 2801 can be slid apart, As shown in Figure 21(D), the device can be folded from the unfolded state to the folded state, making it easy to carry. Suitable miniaturization is possible.

[0236] The external connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. A recording medium can be inserted into the memory slot 2811 to accommodate larger amounts of data storage and transfer. do.

[0237] In addition to the above functions, it also has infrared communication function, TV reception function, etc. Good too.

[0238] FIG. 21(E) shows a digital camera manufactured by mounting at least a display device as one component. There is a main body 3051, a display unit (A) 3057, an eyepiece unit 3053, an operation switch 3054, It is composed of a display unit (B) 3055, a battery 3056, and the like.

[0239] FIG. 22 shows a television device 9600. The television device 9600 has a housing A display unit 9603 is built into the 9601. The display unit 9603 displays images. In addition, in this embodiment, the housing 9601 is supported by a stand 9605. This shows the composition of the

[0240] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0241] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0242] In the display portion 9603, the transistor described in Embodiment 5 is used as a switching element of a pixel. A plurality of display units 9603 are arranged on the same insulating substrate as the display unit 9603 as a driving circuit. A high-mobility transistor shown in FIG. 5 is arranged.

[0243] This embodiment mode can be freely combined with any one of the embodiment modes 1 to 9. [Explanation of symbols]

[0244] 400 Substrates 401 Gate electrode layer 402 Gate insulating layer 403 First oxide semiconductor layer 404 Second oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 407 Oxide insulating layer 430 Oxide Semiconductor Stacking 431 Island-shaped oxide semiconductor stack 432 Oxide Semiconductor Stacking 470 Transistors 500 Base material 501 First oxide crystal member 502 Oxide semiconductor layer 503a Oxide crystal material 503b Oxide crystal material 504 Amorphous layer 520 Base material 531 Oxide Crystal Materials 532 Oxide Materials 533a Oxide crystal materials 533b Oxide crystal materials 580 Substrate 581 Transistor 583 Insulating Layer 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 596 Board 1501 Glass substrate 1502 Pixel section 1503 Gate Driver 1504 Gate Driver 1505 Analog Switch 1506 FPC 1507 FPC 1508 FPC 1509 FPC 1701 Glass substrate 1702 Pixel section 1703 Gate Driver 1704 Gate Driver 1705 Source Driver 1706 FPC 1707 FPC 1711 Glass substrate 1712 Pixel section 1713 Gate Driver 1714 Gate Driver 1715 Gate Driver 1716 Gate Driver 1717 Source Driver 1718 Source Driver 1719 Source Driver 1720 Source Driver 1721 FPC 1722 FPC 1723 FPC 1724 FPC 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 2800 Chassis 2801 Case 2802 Display Panel 2803 Speaker 2804 Microphone 2805 Operation key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 Solar Cell 2811 External memory slot 3001 Main unit 3002 Case 3003 Display section 3004 Keyboard 3021 Main unit 3022 Stylus 3023 Display section 3024 Operation button 3025 External Interface 3051 Main unit 3053 Eyepiece 3054 Operation switch 3055 Display section (B) 3056 Battery 3057 Display section (A) 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive layer 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4040 Conductive layer 4501 Board 4502 Pixel section 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4505 Sealing material 4506 Board 4507 Filling material 4509 Transistor 4510 Transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive layer 4520 Bulkhead 4540 Conductive layer 4541 Insulation layer 4544 Insulation layer 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control device

Claims

1. A driver circuit and a pixel portion are provided on a substrate. the driver circuit includes a first transistor including a first oxide semiconductor layer; The pixel section has a plurality of pixels arranged in a matrix, At least one of the pixels includes a second transistor having a second oxide semiconductor layer and a pixel electrode electrically connected to the second transistor; a first conductive layer that is disposed under the second oxide semiconductor layer and has a region that functions as a gate electrode of the second transistor; the second oxide semiconductor layer has a first region overlapping an upper surface of the first conductive layer and a second region inclined to follow a slope of a side surface of the first conductive layer; The first region has a crystal portion oriented along a c-axis, The second region has a crystal portion oriented along a c-axis, A display device, wherein the orientation of the c-axis in the first region and the orientation of the c-axis in the second region are different directions.

2. A driving circuit and a pixel portion are provided on a substrate. the driver circuit includes a first transistor including a first oxide semiconductor layer; The pixel section has a plurality of pixels arranged in a matrix, At least one of the pixels includes a second transistor having a second oxide semiconductor layer and a pixel electrode electrically connected to the second transistor; a first conductive layer that is disposed under the second oxide semiconductor layer and has a region that functions as a gate electrode of the second transistor; the second oxide semiconductor layer has a first region overlapping an upper surface of the first conductive layer and a second region inclined to follow a slope of a side surface of the first conductive layer; The first region has a crystal portion oriented along a c-axis, The second region has a crystal portion oriented along a c-axis, the direction of the c-axis in the first region and the direction of the c-axis in the second region are different directions, The display device, wherein the drive circuit is electrically connected to the first conductive layer.

Images