Integrated circuit element and method of manufacture thereof

Abstract

To provide an integrated circuit device including a non-volatile vertical-type memory device, and a method of manufacturing the same.SOLUTION: An integrated circuit device 100A includes: a channel layer 150 extending vertically in a channel hole CHH penetrating a conductive line CL and an insulating layer 110 which horizontally extend on a substrate; a charge trap pattern 134P interposed between the conductive line and the channel layer; and a dummy charge trap pattern 134D interposed between the insulating layer and the channel layer. A manufacturing method includes: forming a channel hole; removing a part of a mold layer; forming mold indent; forming a preliminary dielectric pattern in the mold indent; oxidizing the preliminary dielectric pattern to form a first blocking dielectric pattern; forming a charge trap layer in the channel hole; removing the mold layer to form a conductive space; removing a portion of the charge trap layer via the conductive space; and forming a plurality of charge trap patterns and a plurality of dummy charge trap patterns.SELECTED DRAWING: Figure 3B

Description

[Technical field]

[0001] The present invention relates to an integrated circuit device and a method for manufacturing the same, and more particularly to an integrated circuit device having a non-volatile vertical memory device and a method for manufacturing the same. [Background technology]

[0002] Due to the increase in capacity and high integration of integrated circuit elements, vertical memory elements have been proposed that stack multiple memory cells vertically on a substrate to increase memory capacity. When increasing the cell stacking density along the vertical direction in a vertical memory element, the spacing between adjacent cells in the vertical direction is reduced, and there is a risk that the reliability of the integrated circuit element will decrease due to cell interference caused by charge diffusion between adjacent cells. Summary of the Invention [Problem to be solved by the invention]

[0003] The technical problem that the technical concept of the present invention aims to solve is to provide an integrated circuit device having a structure that can suppress cell interference caused by charge diffusion between adjacent cells and improve reliability even when the spacing between vertically adjacent cells is relatively narrow in a highly scaled vertical memory device.

[0004] Another technical problem that the technical concept of the present invention aims to solve is to provide a method for manufacturing an integrated circuit device that can easily and efficiently form a structure that suppresses cell interference due to charge diffusion between adjacent cells, even when the spacing between vertically adjacent cells is relatively narrow in a highly scaled vertical memory device. [Means for solving the problem]

[0005] According to one aspect of the technical concept of the present invention, an integrated circuit device includes a conductive pattern extending in a horizontal direction on a substrate parallel to a main surface of the substrate, an insulating film extending in the horizontal direction on the substrate parallel to the conductive pattern, a channel film extending in a vertical direction perpendicular to the main surface of the substrate within a channel hole penetrating the conductive pattern and the insulating film, a charge storage pattern interposed between the conductive pattern and the channel film within the channel hole, and a dummy charge storage pattern interposed between the insulating film and the channel film within the channel hole.

[0006] According to another aspect of the present invention, an integrated circuit device includes a plurality of conductive patterns extending on a substrate in a horizontal direction parallel to a main surface of the substrate and overlapping each other along a vertical direction perpendicular to the main surface, a plurality of insulating films interposed between each of the plurality of conductive patterns and extending in the horizontal direction, a channel film extending in the vertical direction within a channel hole penetrating the plurality of conductive patterns and the plurality of insulating films, a plurality of charge trap patterns interposed between the plurality of conductive patterns and the channel film within the channel hole and spaced apart from each other, and a plurality of insulating films interposed between the plurality of conductive patterns and the channel film and spaced apart from each other at positions spaced apart from the plurality of charge trap patterns. a plurality of dummy charge trapping patterns interposed between an insulating film and the channel film and spaced apart from each other; and a plurality of blocking dielectric patterns including a first pattern portion and a plurality of second pattern portions, the plurality of first pattern portions being disposed one by one between each of the plurality of insulating films and interposed between the plurality of conductive patterns and the plurality of charge trapping patterns, the plurality of second pattern portions surrounding a portion of each of the plurality of conductive patterns and filling a space between each of the plurality of charge trapping patterns and the plurality of dummy charge trapping patterns.

[0007] According to still another aspect of the present invention, an integrated circuit device includes a lower conductive line and an upper conductive line extending in parallel to each other in a horizontal direction on a substrate, an insulating film interposed between the lower conductive line and the upper conductive line and extending in the horizontal direction, a channel film formed in a channel hole extending in a vertical direction through the lower conductive line, the upper conductive line, and the insulating film, a lower charge trap pattern interposed between the lower conductive line and the channel film in the channel hole, an upper charge trap pattern interposed between the upper conductive line and the channel film in the channel hole and spaced apart in the vertical direction from the lower charge trap pattern, and a lower charge trap pattern interposed between the insulating film and the channel film, a lower first blocking dielectric pattern interposed between the lower conductive line and the channel film; an upper first blocking dielectric pattern interposed between the upper conductive line and the channel film; a lower second blocking dielectric pattern interposed between the lower conductive line and the lower first blocking dielectric pattern and filling a lower separation space between the lower charge trap pattern and the dummy charge trap pattern; and an upper second blocking dielectric pattern interposed between the upper conductive line and the upper first blocking dielectric pattern and filling an upper separation space between the upper charge trap pattern and the dummy charge trap pattern.

[0008] According to yet another aspect of the present invention, an integrated circuit device includes a plurality of conductive lines extending on a substrate in a horizontal direction parallel to a main surface of the substrate and overlapping each other along a vertical direction perpendicular to the main surface, a plurality of insulating films interposed between each of the plurality of conductive lines and extending in the horizontal direction, a channel film extending in the vertical direction within a channel hole penetrating the plurality of conductive lines and the plurality of insulating films, a plurality of charge trap patterns interposed between the plurality of conductive lines and the channel film within the channel hole and spaced apart from each other, and a plurality of insulating films and a channel film at a position spaced apart from the plurality of charge trap patterns. a plurality of dummy charge trapping patterns interposed and spaced apart from each other; a plurality of first blocking dielectric patterns disposed one by one between each of the plurality of insulating films and interposed between the plurality of conductive lines and the plurality of charge trapping patterns; a plurality of second blocking dielectric patterns surrounding a portion of each of the plurality of first blocking dielectric patterns and a portion of each of the plurality of conductive lines and including a portion filling a space between each of the plurality of charge trapping patterns and the plurality of dummy charge trapping patterns; and a tunneling dielectric film interposed between the plurality of first blocking dielectric patterns and the channel film.

[0009] In accordance with an embodiment of the present invention, a method for manufacturing an integrated circuit device includes forming a structure in which a plurality of insulating films and a plurality of mold films are stacked on a substrate, forming a channel hole penetrating the structure, removing portions of the mold films through the channel hole to form a plurality of mold indentations connected to the channel hole, forming a sacrificial film and a preliminary dielectric pattern filling the interior of each of the mold indentations, and oxidizing the preliminary dielectric pattern to form a first blocking dielectric pattern, forming a charge storage film in the channel hole, forming a tunneling dielectric film on the charge storage film in the channel hole, and forming a channel film on the tunneling dielectric film in the channel hole, and removing the mold films to form conductive spaces between each of the insulating films, removing the sacrificial film through the conductive spaces and removing portions of the charge storage film to form a plurality of separation spaces separating the charge storage film into a plurality of charge storage patterns and a plurality of dummy charge storage patterns, forming a second blocking dielectric pattern filling the plurality of separation spaces and covering inner walls of the conductive spaces, and forming a conductive pattern on the second blocking dielectric pattern in the conductive spaces.

[0010] In another aspect of a method for manufacturing an integrated circuit device according to the technical concept of the present invention, a structure is formed on a substrate, in which a plurality of insulating films and a plurality of mold films are stacked one on top of the other. A channel hole is formed penetrating the structure. A plurality of mold indentations are formed by removing portions of the plurality of mold films through the channel holes, the plurality of mold indentations being connected to the channel holes. A first blocking dielectric pattern is formed inside each of the plurality of mold indentations. A charge trapping film is formed to cover the first blocking dielectric pattern within the channel holes. The plurality of mold films are removed to form conductive spaces exposing the first blocking dielectric pattern. A portion of the charge trapping film is removed through the conductive spaces to form a plurality of separation spaces separating the charge trapping film into a plurality of charge trapping patterns and a plurality of dummy charge trapping patterns. The plurality of separation spaces are filled to form a second blocking dielectric pattern covering the first blocking dielectric pattern within the conductive spaces. A conductive line is formed within the conductive spaces.

[0011] In a method of manufacturing an integrated circuit device according to still another aspect of the present invention, a structure is formed on a substrate, in which a plurality of insulating films and a plurality of mold films are stacked one on top of the other. A channel hole is formed penetrating the structure. Portions of the mold films are removed through the channel hole to form a plurality of mold indentations connected to the channel hole. A sacrificial film and a preliminary dielectric pattern are formed to fill the interior of each of the mold indentations. A charge trapping film is formed in the channel hole to cover the preliminary dielectric pattern. The mold films are removed to form conductive spaces exposing the preliminary dielectric pattern. Portions of the charge trapping film are removed through the conductive spaces to form a plurality of separation spaces separating the charge trapping film into a plurality of charge trapping patterns and a plurality of dummy charge trapping patterns. The preliminary dielectric pattern is oxidized through the conductive space to form a first blocking dielectric pattern. The separation spaces are filled to form a second blocking dielectric pattern covering the first blocking dielectric pattern in the conductive space. A conductive line is formed in the conductive space. [Brief description of the drawings]

[0012] [Figure 1] 2 is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to an embodiment of the present invention. [Diagram 2] FIG. 1 is a plan view showing major components of an integrated circuit device according to an embodiment of the present invention. [Figure 3A] 3 is a cross-sectional view taken along line X1-X1' in FIG. 2. [Figure 3B] FIG. 3B is an enlarged cross-sectional view of the dotted line area indicated by BX1 in FIG. 3A. [Figure 4A] 2 is a schematic cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 4B] 2 is a schematic cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Diagram 5] 2 is a schematic cross-sectional view of an integrated circuit device according to still another embodiment of the present invention; [Figure 6A] 2 is a schematic cross-sectional view of an integrated circuit device according to still another embodiment of the present invention; [Figure 6B] FIG. 6B is an enlarged cross-sectional view of the dotted line area indicated by BX2 in FIG. 6A. [Figure 7] 2 is a schematic cross-sectional view of an integrated circuit device according to still another embodiment of the present invention; [Figure 8A] 2 is a schematic cross-sectional view of an integrated circuit device according to still another embodiment of the present invention; [Figure 8B] FIG. 8B is an enlarged cross-sectional view of the dotted line area marked BX3 in FIG. 8A. [Figure 9] 2 is a schematic cross-sectional view of an integrated circuit device according to still another embodiment of the present invention; [Figure 10A] 2 is a schematic cross-sectional view of an integrated circuit device according to still another embodiment of the present invention; [Figure 10B] 2 is a schematic cross-sectional view of an integrated circuit device according to still another embodiment of the present invention; [Figure 11A]11 is a planar layout diagram of a main region of an integrated circuit device according to still another embodiment of the present invention; FIG. [Figure 11B] FIG. 11B is a schematic perspective view of a portion of the integrated circuit element illustrated in FIG. 11A. [Figure 11C] 11B is a schematic cross-sectional view of a portion of the integrated circuit element illustrated in FIG. 11A. [Figure 12A] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12B] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12C] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12D] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12E] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12F] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12G] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12H] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12I] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12J] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12K] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12L]1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12M] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 13A] 4A to 4C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to another embodiment of the present invention; [Figure 13B] 4A to 4C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to another embodiment of the present invention; [Figure 13C] 4A to 4C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to another embodiment of the present invention; [Figure 13D] 4A to 4C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to another embodiment of the present invention; [Figure 13E] 4A to 4C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to another embodiment of the present invention; [Figure 13F] 4A to 4C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to another embodiment of the present invention; [Figure 13G] 4A to 4C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to another embodiment of the present invention; [Figure 13H] 4A to 4C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to another embodiment of the present invention; [Figure 13I] 4A to 4C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to another embodiment of the present invention; [Figure 14A] 10A to 10C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to still another embodiment of the present invention; [Figure 14B]10A to 10C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to still another embodiment of the present invention; [Figure 14C] 10A to 10C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to still another embodiment of the present invention; [Figure 14D] 10A to 10C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to still another embodiment of the present invention; [Figure 15A] 10A to 10C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to still another embodiment of the present invention; [Figure 15B] 10A to 10C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to still another embodiment of the present invention; [Figure 16] 10A to 10C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to still another embodiment of the present invention; [Figure 17A] 10A to 10C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to still another embodiment of the present invention; [Figure 17B] 10A to 10C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to still another embodiment of the present invention; [Figure 17C] 10A to 10C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to still another embodiment of the present invention; [Figure 18A] 10A to 10C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to still another embodiment of the present invention; [Figure 18B] 10A to 10C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to still another embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to refer to the same components, and redundant description thereof will be omitted.

[0014] 1 is an equivalent circuit diagram of a memory cell array MCA of an integrated circuit device according to an embodiment of the present invention, which illustrates an equivalent circuit diagram of a vertical NAND flash memory device having a vertical channel structure.

[0015] Referring to Fig. 1, the memory cell array MCA includes a plurality of memory cell strings MS. The memory cell array MCA may include a plurality of bit lines BL (BL1, BL2, ..., BLm), a plurality of word lines WL (WL1, WL2, ..., WLn-1, WLn), at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL. A plurality of memory cell strings MS are formed between the plurality of bit lines BL (BL1, BL2, ..., BLm) and the common source line CSL.

[0016] Each of the memory cell strings MS includes a string select transistor SST, a ground select transistor GST, and a number of memory cell transistors MC1, MC2, ..., MCn-1, MCn. The drain regions of the string select transistors SST are connected to bit lines BL (BL1, BL2, ..., BLm), and the source regions of the ground select transistors GST are connected to a common source line CSL. The common source line CSL is also a region where the source regions of the ground select transistors GST are commonly connected.

[0017] The string selection transistor SST is connected to a string selection line SSL, and the ground selection transistor GST is connected to a ground selection line GSL. The memory cell transistors MC1, MC2, ..., MCn-1, MCn are respectively connected to a plurality of word lines WL (WL1, WL2, ..., WLn-1, WLn).

[0018] FIG. 2 is a plan view showing the main components of an integrated circuit element 100A according to an embodiment of the present invention, FIG. 3A is a cross-sectional view taken along line X1-X1' in FIG. 2, and FIG. 3B is an enlarged cross-sectional view of the dotted area marked BX1 in FIG. 3A.

[0019] 2, 3A, and 3B, an integrated circuit element 100A includes a substrate 102 having an active region AC. A memory cell array MCA is formed on the active region AC of the substrate 102. The memory cell array MCA has a circuit configuration as described with reference to FIG.

[0020] The substrate 102 has a main surface 102M extending in the X-direction and the Y-direction. In an exemplary embodiment, the substrate 102 includes Si, Ge, or SiGe. In another exemplary embodiment, the substrate 102 includes a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0021] A plurality of conductive lines CL extend along the XY plane in a horizontal direction parallel to the main surface 102M on the substrate 102, and are arranged to be spaced apart from one another in a vertical direction (Z direction) perpendicular to the main surface 102M of the substrate 102 and overlap one another. In this specification, the "conductive line CL" is referred to as a "conductive pattern CL", and it should be understood that the "conductive line CL" and the "conductive pattern CL" refer to the same component. A plurality of insulating films 110 extend in the horizontal direction on the substrate 102. The plurality of insulating films 110 are interposed between each of the plurality of conductive lines CL.

[0022] A plurality of channel holes CHH are formed through the plurality of conductive lines CL and the plurality of insulating films 110, and a plurality of channel structures CHS1 extend in the vertical direction (Z direction) in the plurality of channel holes CHH. Each of the plurality of channel structures CHS1 includes a semiconductor pattern 120 in contact with the substrate 102 and partially filling the channel hole CHH, a channel film 150 in contact with the semiconductor pattern 120 and extending in the vertical direction (Z direction) in the channel hole CHH, a buried insulating film 156 filling the internal space of the channel film 150, and a drain region 158 in contact with the channel film 150 and filling the upper part of the inlet side of the channel hole CHH. In an exemplary embodiment, the channel film 150 has a cylindrical shape having an internal space, and the internal space of the channel film 150 is filled with the buried insulating film 156. The channel film 150 is made of doped polysilicon or undoped polysilicon. The buried insulating film 156 is made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an exemplary embodiment, the buried insulating film 156 can be omitted, in which case the channel film 150 has a pillar structure without an internal space. The drain region 158 is made of a doped polysilicon film. The drain regions 158 are insulated from each other by the insulating pattern 114. The insulating pattern 114 can also be made of an oxide film, a nitride film, or a combination thereof.

[0023] The channel structures CHS1 include a plurality of charge trapping patterns 134P and a plurality of dummy charge trapping patterns 134D. The terms "charge trapping pattern" and "dummy charge trapping pattern" used in this specification are referred to as "charge storing pattern" and "dummy charge storing pattern", respectively, and the terms "charge trapping pattern" and "charge storing pattern" are used to have the same meaning. The charge trapping patterns 134P are interposed between the conductive line CL and the channel film 150 in the channel hole CHH while being spaced apart from each other. The dummy charge trapping patterns 134D are interposed between the insulating film 110 and the channel film 150 at positions spaced apart from the charge trapping patterns 134P. The dummy charge trapping patterns 134D are spaced apart from each other, and one charge trapping pattern 134P is interposed between each of the dummy charge trapping patterns 134D. The charge trap patterns 134P and the dummy charge trap patterns 134D extend along a straight line in the channel hole CHH that extends in a direction away from the substrate 102, and are alternately arranged one by one along the straight line. The charge trap patterns 134P and the dummy charge trap patterns 134D have the same width in the horizontal direction. The charge trap patterns 134P and the dummy charge trap patterns 134D each have a constant width along the straight line. For example, the charge trap patterns 134P and the dummy charge trap patterns 134D each have a width of about 3 to 10 nm in the horizontal direction.

[0024] The minimum separation distance in the horizontal direction between the multiple charge trapping patterns 134P and the channel film 150 is substantially the same as the minimum separation distance between the multiple dummy charge trapping patterns 134D and the channel film 150. The multiple charge trapping patterns 134P and the multiple dummy charge trapping patterns 134D are also made of a silicon nitride film.

[0025] The length W1 of the charge trapping pattern 134P in the vertical direction is equal to or less than the length Lg1 of the conductive line CL and is equal to or more than half the length Lg1 of the conductive line CL. The charge trapping pattern 134P does not include a portion of the conductive line CL facing a corner closest to the insulating film 110. Therefore, it is possible to minimize adverse effects on the charge trapping pattern 134P caused by the electric field concentrated at the corner of the conductive line CL.

[0026] A plurality of first blocking dielectric patterns 132B are disposed between the plurality of conductive lines CL and the channel structure CHS1. The plurality of first blocking dielectric patterns 132B are disposed between the plurality of insulating films 110, one by one. A portion of each of the plurality of first blocking dielectric patterns 132B vertically overlaps the plurality of insulating films 110. The plurality of first blocking dielectric patterns 132B are respectively interposed between the conductive line CL and the charge trapping pattern 134P. The sidewall of each of the plurality of first blocking dielectric patterns 132B facing the channel film 150 contacts the sidewall of the charge trapping pattern 134P facing the conductive line CL, and extends in a straight line with the sidewall of the plurality of insulating films 110 facing the channel film 150. The plurality of first blocking dielectric patterns 132B are also composed of a silicon oxide film. The horizontal width of each of the plurality of first blocking dielectric patterns 132B is about 3 to 10 nm, for example, about 3 to 5 nm.

[0027] A second blocking dielectric pattern 162 surrounding a portion of the first blocking dielectric pattern 132B and a portion of the conductive line CL is formed between each of the insulating layers 110. The second blocking dielectric pattern 162 may include a first portion 162A interposed between the conductive line CL and the insulating layer 110, a second portion 162B interposed between the first blocking dielectric pattern 132B and the insulating layer 110, a third portion 162C interposed between the charge trapping pattern 134P and the dummy charge trapping pattern 134D, and a fourth portion 162D interposed between the conductive line CL and the first blocking dielectric pattern 132B. The first portion 162A, the second portion 162B, the third portion 162C, and the fourth portion 162D of the second blocking dielectric pattern 162 are connected together. The third portion 162C of the second blocking dielectric pattern 162 may fill the space between the charge trapping patterns 134P and the dummy charge trapping patterns 134D and may contact the charge trapping patterns 134P and the dummy charge trapping patterns 134D. The second blocking dielectric pattern 162 may be made of a silicon oxide layer, a high dielectric layer, or a combination thereof. The metal oxide layer may be made of a high dielectric layer having a higher dielectric constant than the silicon oxide layer. For example, the high dielectric layer may be made of HfO 2 , Al 2 O 3 , or ZrO 2 It also includes, but is not limited to, the following:

[0028] The charge trapping pattern 134P and the tunneling dielectric film 140 are interposed between the plurality of first blocking dielectric patterns 132B and the channel film 150. The tunneling dielectric film 140 extends along the extension direction of the channel film 150 while passing between the charge trapping pattern 134P and the channel film 150 and between the dummy charge trapping pattern 134D and the channel film 150. The charge trapping pattern 134P is also made of a silicon oxide film. The horizontal widths of the charge trapping pattern 134P and the channel film 150 are also constant along their longitudinal directions. For example, the horizontal widths of the charge trapping pattern 134P and the channel film 150 are about 3 to 10 nm.

[0029] A width in a first horizontal direction (X direction) of each of the conductive lines CL and the insulating layers 110 is defined by a plurality of word line cut regions WLC. The conductive lines CL are repeatedly arranged at regular intervals separated from each other by the word line cut regions WLC.

[0030] In the substrate 102, a plurality of common source regions 160 extend along the second horizontal direction (Y direction). The plurality of common source regions 160 are also impurity regions doped with a high concentration of n-type impurities. A portion of the plurality of word line cut regions WLC is filled with a common source pattern CSP. The common source pattern CSP may constitute the common source line CSL illustrated in FIG. 1. The common source pattern CSP extends long in the second horizontal direction (Y direction) on the plurality of common source regions 160. In the word line cut region WLC, an insulating spacer 170 is formed to cover the sidewall of the common source pattern CSP. The insulating spacer 170 serves to electrically insulate the common source pattern CSP from the plurality of conductive lines CL. The common source pattern CSP and the insulating spacer 170 are covered with a capping insulating film 172. The common source pattern CSP may be composed of a metal such as tungsten, copper, or aluminum; a conductive metal nitride such as titanium nitride or tantalum nitride; a transition metal such as titanium or tantalum; or a combination thereof. The insulating spacer 170 and the capping insulating film 172 may each be made of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. A metal silicide film (not shown) is interposed between the common source region 160 and the common source pattern CSP to reduce contact resistance. For example, the metal silicide film may be made of cobalt silicide, tungsten silicide, nickel silicide, etc.

[0031] The conductive lines CL between two adjacent word line cut regions WLC constitute the ground selection line GSL, the word lines WL (WL1, WL2, ..., WLn-1, WLn), and the string selection line SSL described with reference to FIG. 1. The number of the conductive lines CL stacked on the substrate 102 along the Z direction may be selected in various ways as needed. For example, the conductive line CL closest to the substrate 102 among the conductive lines CL constitutes the ground selection line GSL. The two conductive lines CL farthest from the substrate 102 among the conductive lines CL constitute the string selection lines SSL. The string selection lines SSL may include portions separated by the string selection line cut regions SSLC. The string selection line cut regions SSLC are filled with an insulating film 184. The insulating film 184 may also be composed of an oxide film, a nitride film, an air gap, or a combination thereof. The term "air gap" as used herein means a space containing atmosphere or other gases present during the manufacturing process.

[0032] The plurality of conductive lines CL may include a metal, such as tungsten, nickel, cobalt, tantalum, a metal silicide, such as tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide, doped polysilicon, or a combination thereof.

[0033] In the memory cell array MCA, a plurality of bit lines BL extend in a first horizontal direction (X direction) on a plurality of channel structures CHS1. A plurality of bit line contact pads 182 are interposed between the plurality of channel structures CHS1 and the plurality of bit lines BL. A drain region 158 of each of the plurality of channel structures CHS1 is connected to a corresponding one of the plurality of bit lines BL through the bit line contact pad 182. The plurality of bit line contact pads 182 are insulated from each other by an insulating film 180. The insulating film 180 may be an oxide film, a nitride film, or a combination thereof.

[0034] 3A and 3B, the charge trapping patterns 134P are disposed in the channel hole CHH, and therefore the integrated circuit device 100A is advantageously employed for implementing an integrated circuit device highly scaled in the horizontal and vertical directions, as compared with the case where the charge trapping patterns 134P are disposed outside the channel hole CHH. In addition, the charge trapping patterns 134P are separated from each other in the vertical direction (Z direction) within one channel hole CHH via the dummy charge trapping pattern 134D and the second blocking dielectric pattern 162. Therefore, even when the interval between adjacent cells in the vertical direction in a vertical memory device is relatively narrow, a structure can be provided that can suppress cell interference due to charge diffusion between adjacent cells and improve reliability.

[0035] 4A is a schematic cross-sectional view of an integrated circuit device 100B according to another embodiment of the present invention, illustrating an enlarged cross-sectional configuration of a portion corresponding to the dotted line region marked BX1 in FIG.

[0036] Referring to FIG. 4A, the integrated circuit device 100B has almost the same configuration as the integrated circuit device 100A illustrated in FIG. 3A and FIG. 3B. However, in the integrated circuit device 100B, each of the first blocking dielectric patterns 132B is integrally connected to the second blocking dielectric pattern 162. The first blocking dielectric pattern 132B is referred to as a "first pattern part", and the second blocking dielectric pattern 162 is referred to as a "second pattern part". In FIG. 4A, the first blocking dielectric pattern 132B and the second blocking dielectric pattern 162 are separated by an imaginary line represented by a dotted line (DL), but in reality, the first blocking dielectric pattern 132B and the second blocking dielectric pattern 162 may be connected to each other without a visible interface between them. In the integrated circuit device 100B, the first blocking dielectric patterns 132B and the second blocking dielectric patterns 162 are also made of the same material. In one example, the first and second blocking dielectric patterns 132B and 162 are each made of a silicon oxide layer. In another example, the first and second blocking dielectric patterns 132B and 162 are each made of a high-k layer of the same material. The high-k layer may be HfO. 2 , Al 2 O 3 , or ZrO 2 It also includes, but is not limited to, the following:

[0037] 4B is a schematic cross-sectional view of an integrated circuit device 100C according to another embodiment of the present invention, illustrating an enlarged cross-sectional configuration of a portion corresponding to the dotted line region marked BX1 in FIG.

[0038] Referring to FIG. 4B, the integrated circuit device 100C has substantially the same configuration as the integrated circuit device 100A illustrated in FIG. 3A and FIG. 3B. However, the integrated circuit device 100C includes a second blocking dielectric pattern 164. The second blocking dielectric pattern 164 has substantially the same configuration as the second blocking dielectric pattern 162 illustrated in FIG. 3A and FIG. 3B. However, the third portion 162C of the second blocking dielectric pattern 164 includes an air gap AG1. The cross-sectional shape of the air gap AG1 is not limited to that illustrated in FIG. 4B. The air gap AG1 has various widths and heights. By including the air gap AG1 in the third portion 162C of the second blocking dielectric pattern 164, the dielectric constant between each of the plurality of charge trapping patterns 134P can be further reduced, and the effect of suppressing cell interference caused by charge diffusion between adjacent cells in the vertical memory device can be further improved. In the integrated circuit device 100C illustrated in Figure 4B, there is no visible interface between the first blocking dielectric pattern 132B and the second blocking dielectric pattern 164, similar to the interface between the first blocking dielectric pattern 132B and the second blocking dielectric pattern 162 described with reference to Figure 4A. In that case, the first blocking dielectric patterns 132B and the second blocking dielectric patterns 164 may also be composed of the same material.

[0039] 5 is a schematic cross-sectional view of an integrated circuit device 100D according to another embodiment of the present invention, illustrating an enlarged cross-sectional configuration of a portion corresponding to the dotted line region marked BX1 in FIG.

[0040] 5, an integrated circuit device 100D has substantially the same configuration as the integrated circuit device 100A illustrated in FIGS. 3A and 3B. However, the integrated circuit device 100D further includes a plurality of third blocking dielectric patterns 166. The plurality of third blocking dielectric patterns 166 are respectively interposed between the conductive lines CL and the second blocking dielectric patterns 162. The plurality of third blocking dielectric patterns 166 are each made of a silicon oxide layer, a high dielectric layer, or a combination thereof. The high dielectric layer may be HfO2 , Al 2 O 3 , or ZrO 2 In one example, the second blocking dielectric patterns 162 are made of a silicon oxide film, and the third blocking dielectric patterns 166 are made of a high dielectric film. In another example, the second blocking dielectric patterns 162 are made of a high dielectric film, and the third blocking dielectric patterns 166 are made of a silicon oxide film.

[0041] In the integrated circuit element 100D, the vertical length W1C of the charge trapping pattern 134P is less than or equal to the vertical length Lg1C of the conductive line CL and is also greater than or equal to half the length Lg1C of the conductive line CL.

[0042] 5 illustrates an example in which the integrated circuit element 100D further includes a third blocking dielectric pattern 166 in the same configuration as the integrated circuit element 100A illustrated in FIG. 3A and FIG. 3B, but the technical idea of ​​the present invention is not limited thereto. For example, the integrated circuit element 100D may further include a third blocking dielectric pattern 166 illustrated in FIG. 5 in the same configuration as the integrated circuit element 100C described with reference to FIG. 4B. Also, in the integrated circuit element 100D illustrated in FIG. 5, there is no interface between the first blocking dielectric pattern 132B and the second blocking dielectric pattern 162, as in the description of FIG. 4A. In this case, the first blocking dielectric patterns 132B and the second blocking dielectric patterns 162 may be made of the same material.

[0043] Fig. 6A is a schematic cross-sectional view of an integrated circuit device according to still another embodiment of the present invention, and Fig. 6B is an enlarged cross-sectional view of a dotted line area indicated as BX2 in Fig. 6A. Fig. 6A illustrates a cross-sectional configuration of a portion corresponding to the cross section of line X1-X1' in Fig. 2.

[0044] 6A and 6B, an integrated circuit element 200A has substantially the same configuration as the integrated circuit element 100A illustrated in Figures 3A and 3B, except that the integrated circuit element 200A includes a plurality of channel structures CHS2.

[0045] The channel structures CHS2 have substantially the same configuration as the channel structures CHS1 described with reference to Figures 3A and 3B, except that the channel structures CHS2 include a plurality of charge trapping patterns 234P and a plurality of dummy charge trapping patterns 234D.

[0046] The charge trapping patterns 234P are spaced apart from one another and are interposed between the conductive lines CL and the channel film 150 in the channel hole CHH. The dummy charge trapping patterns 234D are interposed between the insulating films 110 and the channel film 150 at positions spaced apart from the charge trapping patterns 234P. The dummy charge trapping patterns 234D are spaced apart from one another and one charge trapping pattern 234P is interposed between each of the dummy charge trapping patterns 234D. The charge trapping patterns 234P and the dummy charge trapping patterns 234D extend along a straight line in the channel hole CHH that extends in a direction away from the substrate 102 and are alternately arranged along the straight line.

[0047] The charge trapping patterns 234P and the dummy charge trapping patterns 234D may have different widths in the horizontal direction. The sidewalls of the charge trapping patterns 234P facing the channel film 150 and the sidewalls of the dummy charge trapping patterns 234D facing the channel film 150 extend in a straight line. The minimum separation distance between the charge trapping patterns 234P and the channel film 150 in the horizontal direction is substantially the same as the minimum separation distance between the dummy charge trapping patterns 234D and the channel film 150. The charge trapping patterns 234P and the dummy charge trapping patterns 234D are also made of a silicon nitride film.

[0048] The length W2 of the charge trapping pattern 234P in the vertical direction is equal to or less than the length Lg2 of the conductive line CL and is equal to or more than half the length Lg2 of the conductive line CL. The charge trapping pattern 234P does not include a portion of the conductive line CL facing a corner closest to the insulating film 110. Therefore, it is possible to minimize adverse effects on the charge trapping pattern 234P caused by the electric field concentrated at the corner of the conductive line CL.

[0049] A plurality of first blocking dielectric patterns 232B are disposed between the plurality of conductive lines CL and the channel structure CHS2. The plurality of first blocking dielectric patterns 232B are disposed between the plurality of insulating films 110, one by one. A portion of each of the plurality of first blocking dielectric patterns 232B vertically overlaps the plurality of insulating films 110. Each of the plurality of first blocking dielectric patterns 232B is interposed between the conductive line CL and the charge trapping pattern 234P. A portion of each of the plurality of first blocking dielectric patterns 232B may have a configuration that protrudes further toward the channel film 150 than a sidewall of the plurality of insulating films 110 that faces the channel film 150. A sidewall of the plurality of first blocking dielectric patterns 232B that faces the channel film 150 may be closer to the channel film 150 than a sidewall of the plurality of insulating films 110 that faces the channel film 150. The plurality of first blocking dielectric patterns 232B may also be composed of a silicon oxide film. The horizontal width of the plurality of first blocking dielectric patterns 232B is also about 3 to 10 nm, for example, about 3 to 5 nm.

[0050] A second blocking dielectric pattern 262 surrounding a portion of the first blocking dielectric pattern 232B and a portion of the conductive line CL is formed between each of the insulating layers 110. The second blocking dielectric pattern 262 may include a first portion 262A interposed between the conductive line CL and the insulating layer 110, a second portion 262B interposed between the first blocking dielectric pattern 232B and the insulating layer 110, a third portion 262C interposed between the charge trapping pattern 234P and the dummy charge trapping pattern 234D, and a fourth portion 262D interposed between the conductive line CL and the first blocking dielectric pattern 232B. The first portion 262A, the second portion 262B, the third portion 262C, and the fourth portion 262D of the second blocking dielectric pattern 262 are connected together. The third portion 262C of the second blocking dielectric pattern 262 fills the spacing between the charge trapping patterns 234P and the dummy charge trapping patterns 234D. The second portion 262B of the second blocking dielectric pattern 262 may include a portion vertically overlapping with the first blocking dielectric pattern 232B.

[0051] The charge trapping patterns 234P and the tunneling dielectric layer 140 are interposed between the plurality of first blocking dielectric patterns 232B and the channel layer 150.

[0052] In an exemplary embodiment, the integrated circuit element 200A may further include a plurality of third blocking dielectric patterns 166, similar to the description of FIG. 5. The plurality of third blocking dielectric patterns 166 are interposed between the conductive lines CL and the second blocking dielectric patterns 262, respectively.

[0053] 6A and 6B, there is no visible interface between the first blocking dielectric pattern 232B and the second blocking dielectric pattern 262, similar to the description of the interface between the first blocking dielectric pattern 132B and the second blocking dielectric pattern 162 with reference to FIG. 4A. In that case, the plurality of first blocking dielectric patterns 232B and the plurality of second blocking dielectric patterns 262 may be made of the same material.

[0054] 7 is a schematic cross-sectional view of an integrated circuit device 200B according to another embodiment of the present invention, illustrating an enlarged cross-sectional configuration of a portion corresponding to the dotted line region marked BX2 in FIG.

[0055] Referring to FIG. 7, the integrated circuit device 200B has substantially the same configuration as the integrated circuit device 200A described with reference to FIG. 6A and FIG. 6B. However, the integrated circuit device 200B includes a second blocking dielectric pattern 264. The second blocking dielectric pattern 264 has substantially the same configuration as the second blocking dielectric pattern 262 illustrated in FIG. 6A and FIG. 6B. However, the third portion 262C of the second blocking dielectric pattern 264 includes an air gap AG2. The cross-sectional shape of the air gap AG2 is not limited to that illustrated in FIG. 7. The air gap AG2 has various widths and heights. By including the air gap AG2 in the third portion 262C of the second blocking dielectric pattern 264, the dielectric constant between each of the plurality of charge trapping patterns 234P can be further reduced, and the effect of suppressing cell interference caused by charge diffusion between adjacent cells in a vertical memory device can be further improved.

[0056] In the integrated circuit element 200B illustrated in Figure 7, there is no visible interface between the first blocking dielectric pattern 232B and the second blocking dielectric pattern 264, similar to the interface between the first blocking dielectric pattern 132B and the second blocking dielectric pattern 162 described with reference to Figure 4A. In that case, the first blocking dielectric patterns 232B and the second blocking dielectric patterns 264 may also be composed of the same material.

[0057] Fig. 8A is a schematic cross-sectional view of an integrated circuit device 300A according to another embodiment of the present invention, and Fig. 8B is an enlarged cross-sectional view of a dotted line area indicated as BX3 in Fig. 8A. Fig. 8A illustrates a cross-sectional configuration of a portion corresponding to the cross section of line X1-X1' in Fig. 2.

[0058] 8A and 8B, an integrated circuit element 300A has substantially the same configuration as the integrated circuit element 200A illustrated in Figures 6A and 6B, except that the integrated circuit element 300A includes a plurality of channel structures CHS3.

[0059] The channel structures CHS3 have substantially the same configuration as the channel structures CHS2 described with reference to Figures 6A and 6B, except that the channel structures CHS3 include a plurality of charge trapping patterns 334P and a plurality of dummy charge trapping patterns 334D.

[0060] The charge trapping patterns 334P are interposed between the conductive line CL and the channel film 150 in the channel hole CHH while being spaced apart from each other. The dummy charge trapping patterns 334D are interposed between the insulating films 110 and the channel film 150 at positions spaced apart from the charge trapping patterns 334P. The dummy charge trapping patterns 334D are spaced apart from each other. One charge trapping pattern 334P is interposed between each of the dummy charge trapping patterns 334D. The charge trapping patterns 334P extend along a first straight line extending in a direction away from the substrate 102 in the channel hole CHH, and the dummy charge trapping patterns 334D extend along a second straight line extending in a direction away from the substrate 102 in the channel hole CHH, and the first straight line and the second straight line do not meet each other in the channel hole CHH. The multiple charge trapping patterns 334P and the multiple dummy charge trapping patterns 334D are alternately arranged one by one in the direction away from the substrate 102 within the channel hole CHH.

[0061] The charge trapping patterns 334P and the dummy charge trapping patterns 334D have the same width in the horizontal direction. The sidewall of the charge trapping patterns 334P facing the channel film 150 may be closer to the channel film 150 than the sidewall of the dummy charge trapping patterns 334D facing the channel film 150. Therefore, the minimum separation distance between the charge trapping patterns 334P and the channel film 150 in the horizontal direction is smaller than the minimum separation distance between the dummy charge trapping patterns 334D and the channel film 150. The charge trapping patterns 334P and the dummy charge trapping patterns 334D are also made of a silicon nitride film.

[0062] The length W3 of the charge trapping pattern 334P in the vertical direction is equal to or less than the length Lg3 of the conductive line CL and is equal to or more than half the length Lg3 of the conductive line CL. The charge trapping pattern 334P does not include a portion of the conductive line CL facing a corner closest to the insulating film 110. Therefore, it is possible to minimize adverse effects on the charge trapping pattern 334P caused by the electric field concentrated at the corner of the conductive line CL.

[0063] A second blocking dielectric pattern 362 surrounding a portion of the first blocking dielectric pattern 232B and a portion of the conductive line CL is formed between each of the insulating layers 110. The second blocking dielectric pattern 362 may include a first portion 362A interposed between the conductive line CL and the insulating layer 110, a second portion 362B interposed between the first blocking dielectric pattern 232B and the insulating layer 110, a third portion 362C interposed between the charge trapping pattern 334P and the dummy charge trapping pattern 334D, and a fourth portion 362D interposed between the conductive line CL and the first blocking dielectric pattern 232B. The first portion 362A, the second portion 362B, the third portion 362C, and the fourth portion 362D of the second blocking dielectric pattern 362 are connected together. The third portion 362C of the second blocking dielectric pattern 362 may fill spaces between the plurality of charge trapping patterns 334P and the plurality of dummy charge trapping patterns 334D.

[0064] A plurality of charge trapping patterns 334P and a tunneling dielectric layer 340 are interposed between the plurality of first blocking dielectric patterns 232B and the channel layer 150. The tunneling dielectric layer 340 has a variable width along a direction away from the substrate 102 in the channel hole CHH. In the horizontal direction, the width of a portion of the tunneling dielectric layer 340 interposed between the charge trapping pattern 334P and the channel layer 150 is smaller than the width of a portion of the tunneling dielectric layer 340 interposed between the dummy charge trapping pattern 334D and the channel layer 150. A sidewall of the tunneling dielectric layer 340 facing the channel layer 150 extends flat along the longitudinal direction of the channel hole CHH. A concavo-convex shape is formed along the longitudinal direction of the channel hole CHH on a sidewall of the tunneling dielectric layer 340 facing the plurality of charge trapping patterns 334P and the plurality of dummy charge trapping patterns 334D. The tunneling dielectric film 340 may also be made of silicon oxide.

[0065] In an exemplary embodiment, the integrated circuit element 300A may further include a plurality of third blocking dielectric patterns 166, similar to the description of FIG. 5. The plurality of third blocking dielectric patterns 166 are interposed between the conductive lines CL and the second blocking dielectric patterns 262, respectively.

[0066] 8A and 8B, there is no visible interface between the first blocking dielectric pattern 232B and the second blocking dielectric pattern 362, as described with reference to Fig. 4A for the interface between the first blocking dielectric pattern 132B and the second blocking dielectric pattern 162. In that case, the plurality of first blocking dielectric patterns 232B and the plurality of second blocking dielectric patterns 362 may be made of the same material.

[0067] 9 is a schematic cross-sectional view of an integrated circuit device 300B according to another embodiment of the present invention, illustrating an enlarged cross-sectional configuration of a portion corresponding to the dotted line region marked BX3 in FIG.

[0068] Referring to FIG. 9, the integrated circuit device 300B has substantially the same configuration as the integrated circuit device 300A described with reference to FIG. 8A and FIG. 8B. However, the integrated circuit device 300B includes a second blocking dielectric pattern 364. The second blocking dielectric pattern 364 has substantially the same configuration as the second blocking dielectric pattern 362 illustrated in FIG. 8A and FIG. 8B. However, the third portion 362C of the second blocking dielectric pattern 364 includes an air gap AG3. The cross-sectional shape of the air gap AG3 is not limited to that illustrated in FIG. 9. The air gap AG3 has various widths and heights. By including the air gap AG3 in the third portion 362C of the second blocking dielectric pattern 364, the dielectric constant between each of the plurality of charge trapping patterns 334P can be further reduced, and the effect of suppressing cell interference caused by charge diffusion between adjacent cells in the vertical memory device can be further improved.

[0069] In the integrated circuit element 300B illustrated in Fig. 9, there is no visible interface between the first blocking dielectric pattern 232B and the second blocking dielectric pattern 364, as described for the interface between the first blocking dielectric pattern 132B and the second blocking dielectric pattern 162 with reference to Fig. 4A. In that case, the plurality of first blocking dielectric patterns 232B and the plurality of second blocking dielectric patterns 364 may also be made of the same material.

[0070] 10A is a schematic cross-sectional view of an integrated circuit device 400A according to another embodiment of the present invention, which illustrates an enlarged cross-sectional configuration of a portion corresponding to a partial region of FIG. 3A.

[0071] 10A, an integrated circuit device 400A has an equivalent circuit of the memory cell array MCA of the integrated circuit device 100A illustrated in FIG. 1, and has almost the same configuration as the integrated circuit device 100A illustrated in FIG. 3A and FIG. 3B. In particular, the portion constituting the plurality of word lines WL (WL1, WL2, ..., WLn-1, WLn) of FIG. 1 has the configuration illustrated in FIG. 3A and FIG. 3B. However, in the integrated circuit device 400A, the portion constituting at least one of the ground selection line GSL and the string selection line SSL of FIG. 1 may include a conductive line CL4 instead of the conductive line CL illustrated in FIG. 3A and FIG. 3B. The vertical thickness of the conductive line CL4 is thicker than the vertical thickness of the conductive line CL illustrated in FIG. 3A and FIG. 3B. For example, but not limited to, the vertical thickness of the conductive line CL4 is at least twice the vertical thickness of the conductive lines CL (see Figures 3A and 3B) that constitute the multiple word lines WL (WL1, WL2, ..., WLn-1, WLn) in the integrated circuit element 400A.

[0072] The integrated circuit element 400A may include a channel structure CHS4 penetrating the conductive line CL4. The channel structure CHS4 may include a channel film 450 extending vertically from within the channel hole CHH, and a buried insulating film 456 filling the internal space of the channel film 450. A first blocking dielectric pattern 432B is disposed between the conductive line CL4 and the channel structure CHS4. The first blocking dielectric pattern 432B is disposed between two adjacent insulating films 110, and at least a portion of the first blocking dielectric pattern 432B vertically overlaps with the insulating film 110. The first blocking dielectric pattern 432B has a concave sidewall 432BS toward the channel film 450. The horizontal width of the first blocking dielectric pattern 432B is about 3 to 10 nm, for example, about 3 to 5 nm.

[0073] The charge trapping pattern 434P and the tunneling dielectric film 440 are interposed between the first blocking dielectric pattern 432B and the channel film 450. The tunneling dielectric film 440 extends along the extension direction of the channel film 450 while passing between the charge trapping pattern 434P and the channel film 150 and between the dummy charge trapping pattern 134D and the channel film 150. The charge trapping pattern 434P is also made of a silicon oxide film. The horizontal widths of the charge trapping pattern 434P, the tunneling dielectric film 440, and the channel film 450 are also constant along their longitudinal directions. In the vertical direction, the length W4 of the charge trapping pattern 434P is equal to or less than the length Lg4 of the conductive line CL4 and is equal to or more than half the length Lg1 of the conductive lines CL4. The charge trapping pattern 434P does not include a portion of the conductive line CL4 facing the corner closest to the insulating film 110. Therefore, the adverse effect of the electric field concentrated at the corner of the conductive line CL4 on the charge trapping pattern 434P can be minimized.

[0074] The charge trapping pattern 434P may include a convex sidewall 434PS facing the concave sidewall 432BS of the first blocking dielectric pattern 432B. The convex sidewall 434PS of the charge trapping pattern 434P may contact the concave sidewall 432BS of the first blocking dielectric pattern 432B. The tunneling dielectric film 440 has a convex sidewall 440S facing the concave sidewall 432BS of the first blocking dielectric pattern 432B. The channel film 450 has a convex sidewall 450S facing the concave sidewall 432BS of the first blocking dielectric pattern 432B. The buried insulating film 456 has a convex sidewall 456S facing the concave sidewall 432BS of the first blocking dielectric pattern 432B.

[0075] The conductive line CL4 is surrounded by a second blocking dielectric pattern 462. The second blocking dielectric pattern 462 may include a first portion 462A interposed between the conductive line CL4 and the insulating film 110, a second portion 462B interposed between the first blocking dielectric pattern 432B and the insulating film 110, a third portion 462C interposed between the charge trapping pattern 434P and the dummy charge trapping pattern 134D, and a fourth portion 462D interposed between the conductive line CL4 and the first blocking dielectric pattern 432B. The first portion 462A, the second portion 462B, the third portion 462C, and the fourth portion 462D of the second blocking dielectric pattern 462 are connected together. The third portion 462C of the second blocking dielectric pattern 462 fills a space between the charge trapping pattern 434P and the dummy charge trapping pattern 134D. Further detailed configurations of the first blocking dielectric pattern 432B, the charge trapping pattern 434P, the tunneling dielectric film 440, the channel film 450, the buried insulating film 456, the second blocking dielectric pattern 462, and the conductive line CL4 are similar to those described for the first blocking dielectric pattern 132B, the charge trapping pattern 134P, the tunneling dielectric film 140, the channel film 150, the buried insulating film 156, the second blocking dielectric pattern 162, and the conductive line CL with reference to Figures 3A and 3B.

[0076] In the integrated circuit element 400A illustrated in Figure 10A, there is no visible interface between the first blocking dielectric pattern 432B and the second blocking dielectric pattern 462, similar to the interface between the first blocking dielectric pattern 132B and the second blocking dielectric pattern 162 described with reference to Figure 4A. In that case, the first blocking dielectric patterns 432B and the second blocking dielectric patterns 462 may also be composed of the same material.

[0077] FIG. 10B is a schematic cross-sectional view of an integrated circuit device 400B according to yet another embodiment of the concepts of the present invention.

[0078] Referring to FIG. 10B, the integrated circuit element 400B has substantially the same configuration as the integrated circuit element 400A described with reference to FIG. 10A. However, the integrated circuit element 400B includes a second blocking dielectric pattern 464. The second blocking dielectric pattern 464 has substantially the same configuration as the second blocking dielectric pattern 462 illustrated in FIG. 10A. However, the third portion 462C of the second blocking dielectric pattern 464 includes an air gap AG4. The cross-sectional shape of the air gap AG4 is not limited to that illustrated in FIG. 10A. The air gap AG4 has various widths and heights. By including the air gap AG4 in the third portion 462C of the second blocking dielectric pattern 464, the dielectric constant between each of the plurality of charge trapping patterns 434P can be further reduced, and the effect of suppressing cell interference caused by charge diffusion between adjacent cells in the vertical memory device can be further improved.

[0079] In the integrated circuit element 400B illustrated in Figure 10B, there is no visible interface between the first blocking dielectric pattern 432B and the second blocking dielectric pattern 464, similar to the interface between the first blocking dielectric pattern 132B and the second blocking dielectric pattern 162 described with reference to Figure 4A. In that case, the first blocking dielectric patterns 432B and the second blocking dielectric patterns 464 may also be composed of the same material.

[0080] FIG. 11A is a plan layout diagram of a main area of ​​an integrated circuit device 500 according to yet another embodiment of the concept of the present invention.

[0081] 11A, an integrated circuit device 500 may include a memory cell array region 512, a first peripheral circuit region 514, a second peripheral circuit region 516, and a bonding pad region 518. The memory cell array region 512 may include a plurality of memory cell arrays MCA having the configuration described with reference to FIG. 1. The first peripheral circuit region 514 and the second peripheral circuit region 516 may include a control unit for controlling data input or output from the memory cell array region 512. In the first peripheral circuit region 514 and the second peripheral circuit region 516, peripheral circuits for driving vertical memory cells included in the memory cell array region 512 are arranged.

[0082] The first peripheral circuit region 514 may be arranged to vertically overlap the memory cell array region 512, thereby reducing the planar size of a chip including the integrated circuit device 500. In some embodiments, the peripheral circuits arranged in the first peripheral circuit region 514 may also be circuits that process data input / output to / from the memory cell array region 512 at high speed. For example, the peripheral circuits arranged in the first peripheral circuit region 514 may also be a page buffer, a latch circuit, a cache circuit, a column decoder, a sense amplifier, or a data in / out circuit.

[0083] The second peripheral circuit region 516 is disposed on one side of the memory cell array region 512 in a region that does not overlap with the memory cell array region 512 and the first peripheral circuit region 514. The peripheral circuit formed in the second peripheral circuit region 516 may be, for example, a row decoder. In some embodiments, unlike the example of FIG. 11A, at least a portion of the second peripheral circuit region 516 may be disposed below the memory cell array region 512.

[0084] The bonding pad region 518 is formed on the other side of the memory cell array region 512. The bonding pad region 518 is also a region where wiring connected from each word line of the vertical memory cells of the memory cell array region 512 is formed.

[0085] Figures 11B and 11C are schematic perspective and cross-sectional views of a portion of the integrated circuit element 500 illustrated in Figure 11A. In Figures 11B and 11C, the same reference symbols as in Figures 1 to 3B indicate the same members, and detailed descriptions thereof will be omitted here.

[0086] 11B and 11C, an integrated circuit device 500 includes a first peripheral circuit region 514 formed in a first level on a substrate 502, and a memory cell array region 512 formed in a second level on the substrate 502 that is higher than the first level. As used herein, the term "level" refers to a height along a vertical direction (Z direction in FIGS. 11B and 11C) from the substrate 502. On the substrate 502, the first level is closer to the substrate 502 than the second level.

[0087] The substrate 502 has a main surface 502M extending in the X-direction and the Y-direction. Further details of the substrate 502 are substantially the same as those of the substrate 102 based on FIG. 3A and FIG. 3B. In the substrate 502, a peripheral active region PAC is defined by an element isolation film 504. A plurality of transistors TR5 constituting a first peripheral circuit region 514 are formed on the peripheral active region PAC of the substrate 502. Each of the plurality of transistors TR5 may include a peripheral gate PG and a peripheral source / drain region PSD formed in the peripheral active region PAC on both sides of the peripheral gate PG. In some embodiments, unit elements such as resistors and capacitors are further disposed in the first peripheral circuit region 514. A peripheral interlayer insulating film 508 is formed on the plurality of transistors TR5. The peripheral interlayer insulating film 508 may include silicon oxide, SiON, SiOCN, or the like.

[0088] The first peripheral circuit region 514 may include a plurality of peripheral circuit wiring layers MTL5 and a plurality of peripheral circuit contacts MC5. Some of the peripheral circuit wiring layers MTL5 are configured to be electrically connected to a plurality of transistors TR5. The peripheral circuit contacts MC5 are configured to connect some peripheral circuit wiring layers MTL5 selected from the plurality of peripheral circuit wiring layers MTL5 to each other. The peripheral circuit wiring layers MTL5 and the peripheral circuit contacts MC5 are covered with a peripheral interlayer insulating film 508.

[0089] The peripheral circuit wiring layers MTL5 and the peripheral circuit contacts MC5 may each be made of a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, the peripheral circuit wiring layers MTL5 and the peripheral circuit contacts MC5 may each include a conductive material such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, or nickel silicide. In FIG. 11C, the peripheral circuit wiring layers MTL5 are illustrated as having a three-layer wiring structure along the vertical direction (Z direction), but the technical idea of ​​the present invention is not limited to that illustrated in FIG. 11C. For example, the peripheral circuit wiring layers MTL5 may have a two-layer or four-layer or more multilayer wiring structure.

[0090] A semiconductor layer 520 covering the peripheral interlayer insulating film 508 is formed on the first peripheral circuit region 514. The semiconductor layer 520 is also composed of Si, Ge, or a combination thereof. The semiconductor layer 520 is also composed of a doped semiconductor or an undoped semiconductor. The semiconductor layer 520 has a single crystal structure, an amorphous structure, or a polycrystalline structure. A plurality of common source regions 572 are formed in the semiconductor layer 520. A more detailed configuration of the plurality of common source regions 572 is almost the same as that described for the common source region 160 with reference to FIG. 3. The plurality of common source regions 572 are formed by doping impurities in the semiconductor layer 520.

[0091] A memory cell array region 512 is formed on the semiconductor layer 520. The memory cell array region 512 has substantially the same configuration as that described for the memory cell array region MCA of the integrated circuit element 100A with reference to Figures 3A and 3B. In particular, in the memory cell array region 512, a portion corresponding to the word lines WL (WL1, WL2, ..., WLn-1, WLn) in Figure 1 has a configuration as exemplified in Figures 3A and 3B. However, in the integrated circuit element 500, a portion corresponding to the ground selection line GSL and the common source line CSL in Figure 1 has a configuration as described with reference to Figure 10A.

[0092] More specifically, in the integrated circuit device 500, a portion corresponding to the word lines WL (WL1, WL2, ..., WLn-1, WLn) of FIG. 1 is composed of the conductive lines CL illustrated in FIG. 3A and FIG. 3B, and a portion corresponding to the ground selection line GSL and the common source line CSL of FIG. 1 is also composed of the conductive line CL4 illustrated in FIG. 10A. The integrated circuit device 500 may include a plurality of conductive lines CL and a plurality of conductive lines CL4, and a channel structure CHS5 penetrating them. A portion of the channel structure CHS5 penetrating the plurality of conductive lines CL has a configuration as described for the channel structure CHS1 with reference to FIG. 3A and FIG. 3B. A portion of the channel structure CHS5 penetrating the plurality of conductive lines CL4 has a configuration as described for the channel structure CHS4 with reference to FIG. 10A.

[0093] Next, a method for manufacturing an integrated circuit device according to an embodiment of the present invention will be described in detail.

[0094] 12A to 12M are cross-sectional views showing a process sequence to explain a method for manufacturing an integrated circuit device according to an embodiment of the present invention. In this example, an exemplary method for manufacturing the integrated circuit device 100A described with reference to FIGS. 3A and 3B is explained. In FIGS. 12A to 12M, an enlarged cross-sectional configuration of a portion corresponding to the dotted line region indicated as Q1 in FIG. 3A is illustrated in a process sequence.

[0095] 12A, an active region AC is defined in a substrate 102, and a plurality of insulating films 110 and a plurality of mold films ML are laminated one on top of the substrate 102. Of the plurality of insulating films 110, a lowest layer insulating film 110L in contact with the substrate 102 has a thickness D1 that is thinner than the other insulating films 110. The plurality of insulating films 110 are made of silicon oxide films, and the plurality of mold films ML are also made of silicon nitride films.

[0096] The mold films ML each serve to provide a space for forming a ground selection line GSL, a plurality of word lines WL, and a plurality of string selection lines SSL in a subsequent process. Of the mold films ML, the first mold film ML from the substrate 102 provides a space for forming the ground selection line GSL. Of the insulating films 110, the insulating film 110 in contact with an upper surface of the first mold film ML has a thickness D2 that is thicker than the other insulating films 110. The insulating films 110 and the mold films ML are each formed by a chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or atomic layer deposition (ALD) process.

[0097] Referring to FIG. 12B, after forming an insulating pattern 114 on the top insulating film 110 among the multiple insulating films 110, the multiple insulating films 110 and the multiple mold films ML are anisotropically etched using the insulating pattern 114 as an etching mask to form a channel hole CHH exposing the substrate 102.

[0098] The horizontal width of the channel hole CHH becomes narrower closer to the substrate 102. The insulating pattern 114 may also be made of a single layer or multiple layers made of an oxide film, a nitride film, or a combination thereof.

[0099] 12C, a selective epitaxial growth process is performed from the bottom of the channel hole CHH to form a semiconductor pattern 120 that partially fills the channel hole CHH. The semiconductor pattern 120 may also be composed of a doped semiconductor layer, for example, a doped Si layer or a doped Ge layer.

[0100] A portion of each of the mold films ML is selectively trimmed from the sidewalls of the mold films ML exposed through the channel holes CHH to form a plurality of mold indents MLA connected to the channel holes CHH between the respective insulating films 110. The horizontal width WH1 of each of the mold indents MLA is about 3 to 10 nm.

[0101] In order to trim the plurality of mold films ML, an etching process is used to selectively etch the plurality of mold films ML among the plurality of mold films ML and the plurality of insulating films 110. For example, when the plurality of mold films ML are made of silicon nitride films and the plurality of insulating films 110 are made of silicon oxide films, an etching solution made of an ammonia-based etching solution, a phosphoric acid-based etching solution, a sulfuric acid-based etching solution, an acetic acid-based etching solution, or a combination thereof is used to selectively trim a portion of each of the plurality of mold films ML. The process of trimming the plurality of mold films ML is performed in a state where the semiconductor pattern 120 is covered with a protective film (not shown).

[0102] Referring to FIG. 12D, a sacrificial layer 130 and a preliminary blocking insulating layer 132 are sequentially formed on the resultant structure of FIG. 12C.

[0103] The sacrificial film 130 is formed to conformally cover the surfaces exposed in the channel hole CHH and the plurality of mold indentations MLA. The sacrificial film 130 is also made of the same material as the constituent material of the plurality of mold films ML, or a material having the same or similar etching characteristics as the constituent material of the sacrificial film 130. For example, the sacrificial film 130 is also made of a silicon nitride film. The sacrificial film 130 is formed to have a width of about 3 to 10 nm in the horizontal direction. The preliminary blocking insulating film 132 is formed to extend long in the longitudinal direction of the channel hole CHH within the channel hole CHH while filling a part of each of the plurality of mold indentations MLA on the sacrificial film 130. The preliminary blocking insulating film 132 is also made of a doped polysilicon film or an undoped polysilicon film. The preliminary blocking insulating film 132 is formed to a thickness sufficient to fill the plurality of mold indentations MLA on the sacrificial film 130. The sacrificial film 130 and the preliminary blocking insulating film 132 are formed using an ALD process, a CVD process, or a combination thereof.

[0104] 12E, a trimming process is performed on the preliminary blocking insulating film 132 so that only the portions of the preliminary blocking insulating film 132 that fill the mold indentations MLA remain in the resultant product of FIG. 12D. As a result, a plurality of preliminary blocking dielectric patterns 132P consisting of the remaining portions of the preliminary blocking insulating film 132 remain in the mold indentations MLA. The preliminary blocking dielectric patterns 132P do not protrude into the channel holes CHH, and only fill the internal spaces of the mold indentations MLA.

[0105] A wet etching process using an etchant is used to perform the trimming process of the preliminary blocking insulating film 132. The etchant may be, but is not limited to, a mixed solution containing nitric acid and hydrofluoric acid, a mixed solution containing ammonia water, hydrogen peroxide and water, or a mixed solution containing an alkyl ammonium hydroxide compound, hydrogen peroxide and water.

[0106] 12F, the preliminary blocking dielectric patterns 132P in the resultant structure of FIG. 12E are oxidized to form a first blocking dielectric pattern 132B made of an oxide layer. When the preliminary blocking dielectric patterns 132P are made of a polysilicon layer, the first blocking dielectric pattern 132B is also made of a silicon oxide layer.

[0107] A dry oxidation process or a wet oxidation process is used to oxidize the plurality of preliminary blocking dielectric patterns 132P. For example, when the plurality of preliminary blocking dielectric patterns 132P are dry-oxidized, a plasma oxidation process, O 2 , N 2 A gas flow process is used using gases consisting of O, NO, or combinations thereof.

[0108] 12G, a trimming process is performed to remove the portions of the sacrificial film 130 exposed inside the channel holes CHH and on the top surfaces of the insulating patterns 114 in the resultant structure of FIG. 12F, thereby exposing the sidewalls of the insulating films 110 inside the channel holes CHH and the top surfaces of the insulating patterns 114. For the trimming process of the sacrificial film 130, an etchant consisting of an ammonia-based etchant, a phosphoric acid-based etchant, a sulfuric acid-based etchant, an acetic acid-based etchant, or a combination thereof is used.

[0109] 12H, in the resultant structure of FIG. 12G, a charge trapping layer 134, a tunneling dielectric layer 140, a channel layer 150, and a buried insulating layer 156 are sequentially formed in the channel hole CHH to form a drain region 158 filling the upper portion of the inlet side of the channel hole CHH. As used herein, the term "charge trapping layer" is also referred to as a "charge storage layer", and the terms "charge trapping layer" and "charge storage layer" are used interchangeably.

[0110] In the channel hole CHH, the charge trapping film 134, the tunneling dielectric film 140, and the channel film 150 each have a cylindrical shape. In the process of forming the charge trapping film 134, the tunneling dielectric film 140, and the channel film 150, a portion of the upper surface of the semiconductor pattern 120 is removed to form a recessed surface 120R on the upper surface of the semiconductor pattern 120. The channel film 150 contacts the recessed surface 120R of the semiconductor pattern 120.

[0111] The deposition and etch-back processes can be performed multiple times to form the charge trapping film 134, the tunneling dielectric film 140, the channel film 150, and the buried insulating film 156. The deposition process is performed by CVD, LPCVD (low pressure CVD), or ALD. The charge trapping film 134 is made of a silicon nitride film. The tunneling dielectric film 140 is made of a silicon oxide film. The channel film 150 is made of doped polysilicon or undoped polysilicon. The buried insulating film 156 is made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The drain region 158 is made of doped polysilicon, a metal, a conductive metal nitride, or a combination thereof. The metal constituting the drain region 158 is made of tungsten, nickel, cobalt, or tantalum.

[0112] Referring to FIG. 12I, the insulating pattern 114, the plurality of insulating films 110, and the plurality of mold films ML are anisotropically etched to form a word line cut region WLC that penetrates the insulating pattern 114, the plurality of insulating films 110, and the plurality of mold films ML to expose the substrate 102, and then impurity ions are implanted into the substrate 102 through the word line cut region WLC to form a common source region 160.

[0113] 12J, the mold films ML are removed through the word line cut region WLC to form a plurality of conductive spaces LS1, and the sacrificial film 130 exposed through the conductive spaces LS1 is removed. Then, a portion of the charge trapping film 134 exposed by removing the sacrificial film 130 is removed to separate the charge trapping film 134 into a plurality of charge trapping patterns 134P and a plurality of dummy charge trapping patterns 134D. A separation space TSS is formed between each of the plurality of charge trapping patterns 134P and the plurality of dummy charge trapping patterns 134D.

[0114] When the multiple mold films ML, the sacrificial film 130, and the charge trapping film 134 are each made of a silicon nitride film, a phosphoric acid-based etching solution is used to form the conductive space LS1 and the separation space TSS.

[0115] Referring to FIG. 12K, a second blocking dielectric pattern 162 is formed on the resultant structure of FIG. 12J. The second blocking dielectric pattern 162 is formed to conformally cover the conductive space LS1 and the surface exposed through the word line cut region WLC while filling the separation space TSS. The second blocking dielectric pattern 162 may include a first portion 162A covering the insulating film 110, a second portion 162B interposed between the first blocking dielectric pattern 132B and the insulating film 110, a third portion 162C filling the separation space TSS between the charge trapping pattern 134P and the dummy charge trapping pattern 134D, and a fourth portion 162D covering the sidewall of the first blocking dielectric pattern 132B facing the conductive space LS1. The second blocking dielectric pattern 162 is formed using an ALD process, a CVD process, or a plasma oxidation process.

[0116] 12L, a plurality of conductive lines CL are formed in the plurality of conductive spaces LS1 by filling the spaces of the plurality of conductive spaces LS1 defined by the second blocking dielectric pattern 162 with a conductive layer through the plurality of word line cut regions WLC. The conductive layer is made of a metal, for example, W. In the conductive space LS1, the sidewalls, bottom surface, and top surface of the conductive lines CL are covered with the second blocking dielectric pattern 162.

[0117] Referring to FIG. 12M, an insulating spacer 170, a common source pattern CSP, and a capping insulating film 172 are formed in the word line cut region WLC.

[0118] In an exemplary embodiment, in order to form the insulating spacer 170 in the word line cut region WLC, an insulating film for the spacer is first formed to cover the inner wall of the word line cut region WLC, and then the insulating film for the spacer is etched back to leave the insulating spacer 170 on the inner sidewall of the word line cut region WLC so that the common source region 160 is exposed at the bottom surface of the word line cut region WLC.

[0119] To form the common source pattern CSP, a conductive layer may be formed inside and outside the word line cut region WLC so that the space defined by the insulating spacer 170 in the word line cut region WLC is filled with a conductive material, and then unnecessary portions of the conductive layer may be removed by CMP (chemical mechanical polishing) or etch-back.

[0120] To form the capping insulating film 172, an insulating film may be formed on the resultant structure on which the insulating spacer 170 and the common source pattern CSP are formed to fill the remaining space of the word line cut region WLC, and then a portion of the insulating film may be removed by a CMP or etch-back process to expose the upper surface of the insulating pattern 114 and the upper surface of the drain region 158.

[0121] Next, as illustrated in FIG. 3A, an insulating film 180 is formed to cover the insulating pattern 114, the drain region 158, and the capping insulating film 172, and a portion of the insulating film 180, a portion of the insulating pattern 114, a portion of the insulating film 110, and a portion of the upper two word lines WL among the plurality of word lines WL are removed to form a string selection line cut region SSLC (see FIG. 3A), and the string selection line cut region SSLC can be filled with an insulating film 184.

[0122] Next, a plurality of bit line contact holes 180H penetrating a portion of the insulating film 180 are formed, a conductive material is filled in the plurality of bit line contact holes 180H to form a plurality of bit line contact pads 182, and a plurality of bit lines BL connected to the plurality of bit line contact pads 182 are formed on the insulating film 180, thereby manufacturing the integrated circuit device 100A illustrated in FIG. 3A.

[0123] 12A to 12M are used to manufacture the integrated circuit device 100C illustrated in FIG. 4B. However, in the process described with reference to FIG. 12K, a second blocking dielectric pattern 164 including an air gap AG1 occupying a part of the separation space TSS (FIG. 12J) is formed instead of the second blocking dielectric pattern 162. In order to form the second blocking dielectric pattern 164 including the air gap AG1, the deposition process atmosphere for forming the second blocking dielectric pattern 164, for example, the deposition temperature, deposition pressure, etc., can be controlled.

[0124] To manufacture the integrated circuit device 100D illustrated in Fig. 5, the process described with reference to Fig. 12A to Fig. 12M is used. However, as described with reference to Fig. 12K, after forming the second blocking dielectric pattern 162 and before performing the process of forming the conductive lines CL described with reference to Fig. 12L, a process of forming a third blocking dielectric pattern 166 conformally covering the second blocking dielectric pattern 162 in the conductive spaces LS1 and the word line cut region WLC is further performed. Then, in the process of forming the conductive lines CL described with reference to Fig. 12L, a portion of the third blocking dielectric pattern 166 outside the conductive space LS1 is removed, and the third blocking dielectric pattern 166 and the conductive lines CL remain in the conductive spaces LS1.

[0125] 13A to 13I are cross-sectional views showing a process sequence to explain a method for manufacturing an integrated circuit device according to another embodiment of the present invention. In this embodiment, a method for manufacturing an integrated circuit device 200A shown in FIGS. 6A and 6B is explained. In FIGS. 13A to 13I, an enlarged cross-sectional configuration of a portion corresponding to the dotted line region Q2 in FIG. 6A is shown in a process sequence. In FIGS. 13A to 13I, the same reference numerals as those in FIGS. 12A to 12M indicate the same members, and detailed descriptions thereof will be omitted here.

[0126] 13A, the process described with reference to FIGS. 12A to 12D is performed to form a sacrificial film 130 conformally covering the surfaces exposed by the channel hole CHH and the mold indentations MLA, and a preliminary blocking insulating film 232 filling a portion of each of the mold indentations MLA on the sacrificial film 130, and then a trimming process of the preliminary blocking insulating film 232 is performed in the same manner as described in FIG. 12E. However, in this example, after the trimming process of the preliminary blocking insulating film 232 is performed, a plurality of preliminary blocking dielectric patterns 232P remain in the plurality of mold indentations MLA. Each of the plurality of preliminary blocking dielectric patterns 232P may include a portion filling the mold indentation MLA and a portion extending from the mold indentation MLA to the inside of the channel hole CHH.

[0127] 13B, the preliminary blocking dielectric patterns 232P in the resultant structure of FIG. 13A are oxidized in a manner similar to that described in FIG. 12F to form a first blocking dielectric pattern 232B made of an oxide layer. The first blocking dielectric pattern 232B is made of a silicon oxide layer.

[0128] 13C, in the same manner as described in FIG. 12G, a trimming process is performed to remove exposed portions of the sacrificial film 130 in the resultant structure of FIG. 13B, thereby exposing sidewalls of the insulating films 110 in the channel holes CHH and exposing the top surfaces of the insulating patterns 114. After the trimming process of the sacrificial film 130, the first blocking dielectric patterns 232B have a structure that protrudes further in the horizontal direction toward the central axis of the channel holes CHH than the sidewalls of the insulating films 110 exposed in the channel holes CHH.

[0129] Referring to FIG. 13D, a charge trapping layer 233 is formed in the channel hole CHH in the resultant structure of FIG. 13C. The charge trapping layer 233 is formed to be thicker than the horizontal width of the charge trapping layer 234 to be formed in a subsequent process. The sidewall profile of the charge trapping layer 233 toward the inside of the channel hole CHH is formed to extend substantially linearly in a direction away from the substrate 102. The charge trapping layer 233 is made of a silicon nitride layer. A CVD process is used to form the charge trapping layer 233. In the process of forming the charge trapping layer 233, in a portion relatively close to the first blocking dielectric pattern 232B, the sidewall profile of the charge trapping layer 233 toward the inside of the channel hole CHH has an unevenness corresponding to the cross-sectional contour of the first blocking dielectric pattern 232B during the deposition process for forming the charge trapping layer 233. In this state, the deposition process for forming the charge trapping film 233 is further progressed, and the horizontal thickness of the charge trapping film 233 increases, so that the sidewall profile of the charge trapping film 233 toward the inside of the channel hole CHH has a shape that extends substantially in a straight line in the direction away from the substrate 102.

[0130] 13E, the charge trapping film 233 in the resultant structure of FIG. 13D is etched back to form a charge trapping film 234 in the channel hole CHH. The sidewall profile of the charge trapping film 234 toward the inside of the channel hole CHH extends substantially linearly in a direction away from the substrate 102.

[0131] The charge trapping film 234 extends to have a variable width along the longitudinal direction (Z direction) of the channel hole CHH. The charge trapping film 234 may include a first charge trapping film portion 234A covering the first blocking dielectric pattern 232B with a first width 234T1 and a second charge trapping film portion 234B covering the insulating film 110 with a second width 234T2 larger than the first width 234T1. A more detailed configuration and a forming method of the charge trapping film 234 are substantially the same as those described for the charge trapping film 134 with reference to FIG. 12H.

[0132] Referring to FIG. 13F, in the result of FIG. 13E, a tunneling dielectric layer 140 covering the charge trapping layer 234, a channel layer 150, and a buried insulating layer 156 are sequentially formed in the channel hole CHH in the manner described with reference to FIG. 12H, thereby forming a drain region 158 filling the upper portion of the entrance side of the channel hole CHH.

[0133] Referring to FIG. 13G, in the result of FIG. 13F, a word line cut region WLC and a common source region 160 are formed in the manner described with reference to FIG. 12I. Then, in the manner described with reference to FIG. 12J, a plurality of mold layers ML are removed through the word line cut region WLC to form a plurality of conductive spaces LS2, and the sacrificial layer 130 exposed through the plurality of conductive spaces LS2 is removed, and a portion of the charge trap layer 234 exposed as a result is removed to separate the charge trap layer 234 into a plurality of charge trap patterns 234P and a plurality of dummy charge trap patterns 234D. The plurality of charge trap patterns 234P and the plurality of dummy charge trap patterns 234D are alternately arranged one by one along the longitudinal direction (Z direction) of the channel hole CHH. In the horizontal direction, the plurality of charge trap patterns 234P have a first width 234T1, and the plurality of dummy charge trap patterns 234D have a second width 234T2 larger than the first width 234T1. A separation space TSS2 is formed between each of the plurality of charge trapping patterns 234P and the plurality of dummy charge trapping patterns 234D.

[0134] Referring to FIG. 13H, in the resultant product of FIG. 13G, a second blocking dielectric pattern 262 is formed in a manner similar to that described for forming the second blocking dielectric pattern 162 with reference to FIG. 12K.

[0135] The second blocking dielectric pattern 262 is formed to conformally cover the conductive space LS2 and the surface exposed through the word line cut region WLC while filling the separation space TSS2. The second blocking dielectric pattern 262 may include a first portion 262A covering the insulating film 110, a second portion 262B interposed between the first blocking dielectric pattern 232B and the insulating film 110, a third portion 262C filling the separation space TSS2 between the charge trapping pattern 234P and the dummy charge trapping pattern 234D, and a fourth portion 262D covering a sidewall of the first blocking dielectric pattern 232B facing the conductive space LS2.

[0136] Referring to FIG. 13I, in the result of FIG. 13H, a plurality of conductive lines CL are formed in a plurality of conductive spaces LS2 in the manner described based on FIG. 12L, an insulating spacer 170, a common source pattern CSP, and a capping insulating film 172 are formed in the word line cut region WLC, and subsequent processes as described based on FIG. 12M are performed to manufacture the integrated circuit element 200A illustrated in FIG. 6A and FIG. 6B.

[0137] 7 is manufactured by using the process described with reference to FIGS. 13A to 13I. However, in the process described with reference to FIG. 13H, a second blocking dielectric pattern 264 including an air gap AG2 is formed instead of the second blocking dielectric pattern 262. The air gap AG2 occupies a part of the separation space TSS2 (see FIG. 13G). In order to form the second blocking dielectric pattern 264 including the air gap AG2, the deposition process atmosphere for forming the second blocking dielectric pattern 264, such as the deposition temperature, deposition pressure, etc., is controlled.

[0138] 14A to 14D are cross-sectional views showing a process sequence to explain a method for manufacturing an integrated circuit device according to another embodiment of the present invention. In this embodiment, a method for manufacturing an integrated circuit device 300A shown in FIGS. 8A and 8B is explained. In FIGS. 14A to 14D, an enlarged cross-sectional configuration of a portion corresponding to the dotted line region Q3 in FIG. 8A is shown in a process sequence. In FIGS. 14A to 14D, the same reference numerals as those in FIGS. 12A to 12M and 13A to 13I indicate the same members, and detailed descriptions thereof will be omitted here.

[0139] 14A, a process is performed in which a plurality of first blocking dielectric patterns 232B are formed having a structure protruding further in the horizontal direction toward the central axis of the channel hole CHH than the sidewalls of the plurality of insulating films 110 exposed in the channel hole CHH on the substrate 102, and the sidewalls of the plurality of insulating films 110 are exposed in the channel hole CHH, in the same manner as described in FIG. 13A to 13C. Then, a charge trapping film 334 is formed conformally covering the exposed surfaces of the plurality of first blocking dielectric patterns 232B and the sidewalls of the plurality of insulating films 110 in the channel hole CHH, in the same manner as described in FIG. 13D. Then, a tunneling dielectric film 340, a channel film 150, and a buried insulating film 156 are sequentially formed in the channel hole CHH to sequentially cover the charge trapping film 334, and a drain region 158 is formed to fill the upper part of the inlet side of the channel hole CHH.

[0140] The charge trapping film 334 is formed to have a constant horizontal width along the longitudinal direction (Y direction) of the channel hole CHH. The tunneling dielectric film 340 is formed to have a variable width along a direction away from the substrate 102 in the channel hole CHH. In the horizontal direction, a first width 340T1 of a portion of the tunneling dielectric film 340 interposed between the charge trapping film 334 and the channel film 150 is smaller than a second width 340T2 of a portion of the tunneling dielectric film 340 interposed between the charge trapping film 334 and the channel film 150.

[0141] 14B, in the result of FIG. 14A, a word line cut region WLC and a common source region 160 are formed in the same manner as described with reference to FIG. 13G, a plurality of mold layers ML are removed through the word line cut region WLC to form a plurality of conductive spaces LS3, the sacrificial layer 130 exposed through the plurality of conductive spaces LS3 is removed, and a portion of the charge trapping layer 334 exposed as a result is removed to separate the charge trapping layer 334 into a plurality of charge trapping patterns 334P and a plurality of dummy charge trapping patterns 334D. As a result, a separation space TSS2 is formed between each of the plurality of charge trapping patterns 234P and the plurality of dummy charge trapping patterns 234D.

[0142] Referring to FIG. 14C, in the resultant product of FIG. 14B, a second blocking dielectric pattern 362 is formed in a manner similar to that described for forming the second blocking dielectric pattern 162 with reference to FIG. 12K.

[0143] The second blocking dielectric pattern 362 is formed to conformally cover the conductive space LS3 and the surface exposed through the word line cut region WLC while filling the separation space TSS3. The second blocking dielectric pattern 362 may include a first portion 362A covering the insulating film 110, a second portion 362B interposed between the first blocking dielectric pattern 232B and the insulating film 110, a third portion 362C filling the separation space TSS3 between the charge trapping pattern 334P and the dummy charge trapping pattern 334D, and a fourth portion 362D covering a sidewall of the first blocking dielectric pattern 232B facing the conductive space LS3.

[0144] Referring to FIG. 14D, in the result of FIG. 14C, a plurality of conductive lines CL are formed in a plurality of conductive spaces LS3 in the manner described based on FIG. 12L, an insulating spacer 170, a common source pattern CSP, and a capping insulating film 172 are formed in the word line cut region WLC, and subsequent processes as described based on FIG. 12M are performed to manufacture the integrated circuit element 300A illustrated in FIG. 8A and FIG. 8B.

[0145] 9 is manufactured by using the process described with reference to FIGS. 14A and 14B. However, in the process described with reference to FIG. 14C, a second blocking dielectric pattern 364 including an air gap AG3 is formed instead of the second blocking dielectric pattern 362. The air gap AG3 occupies a part of the separation space TSS3 (see FIG. 14B). In order to form the second blocking dielectric pattern 364 including the air gap AG3, the deposition process atmosphere for forming the second blocking dielectric pattern 364, for example, the deposition temperature, deposition pressure, etc., can be controlled.

[0146] 15A and 15B are cross-sectional views showing a process sequence to explain a manufacturing method of an integrated circuit device according to another embodiment of the present invention. In this embodiment, another exemplary manufacturing method of the integrated circuit device 100A shown in FIGS. 3A and 3B is explained. In FIGS. 15A and 15B, an enlarged cross-sectional configuration of a portion corresponding to the dotted line region Q1 in FIG. 3 is shown in a process sequence. In FIGS. 15A and 15B, the same reference numerals as those in FIGS. 12A to 12M indicate the same members, and detailed descriptions thereof will be omitted here.

[0147] Referring to FIG. 15A, the process of forming the word line cut region WLC, the conductive spaces LS1, and the isolation spaces TSS is performed in the same manner as described with reference to FIG. 12A to FIG. 12I. However, in this embodiment, the process described with reference to FIG. 12F, that is, the process of oxidizing the preliminary blocking dielectric patterns 132P to form the first blocking dielectric pattern 132B, is omitted, and the process described with reference to FIG. 12G is performed on the resultant structure of FIG. 12E in which the preliminary blocking dielectric patterns 132P remain. Therefore, when the charge trapping film 134, the tunneling dielectric film 140, the channel film 150, and the buried insulating film 156 are formed in the same manner as described with reference to FIG. 12H, they are formed on the preliminary blocking dielectric patterns 132P. After the conductive spaces LS1 and the isolation spaces TSS are formed, the preliminary blocking dielectric patterns 132P are exposed through the conductive spaces LS1 as illustrated in FIG. 15A.

[0148] Referring to FIG. 15B, in the result of FIG. 15A, a plurality of preliminary blocking dielectric patterns 132P are oxidized in the same manner as described in FIG. 12F to form a first blocking dielectric pattern 132B made of an oxide film.

[0149] Thereafter, the steps described with reference to FIGS. 12K to 12M are performed to manufacture the integrated circuit element 100A illustrated in FIGS. 3A and 3B.

[0150] Figure 16 is a cross-sectional view showing a process sequence to explain a manufacturing method of an integrated circuit device according to another embodiment of the present invention. In this example, another exemplary manufacturing method of the integrated circuit device 200A shown in Figures 6A and 6B is explained. Figure 16 shows an enlarged cross-sectional configuration of a portion corresponding to the dotted line area marked Q2 in Figure 6A in a process sequence. In Figure 16, the same reference numerals as those in Figures 13A to 13I indicate the same members, and detailed descriptions thereof will be omitted here.

[0151] 16, the process of forming the word line cut region WLC, the conductive spaces LS2, and the separation spaces TSS2 is performed in the same manner as described with reference to FIGS. 13A to 13G. However, in this embodiment, the process described with reference to FIG. 13B, that is, the process of oxidizing the preliminary blocking dielectric patterns 232P to form the first blocking dielectric pattern 232B, is omitted, and the process described with reference to FIG. 13C is performed on the resultant structure of FIG. 13A in which the preliminary blocking dielectric patterns 232P remain. Therefore, when the charge trapping layer 233 is formed in the manner described with reference to FIG. 13D, the charge trapping layer 233 is formed on the preliminary blocking dielectric patterns 232P. After the conductive spaces LS2 and the separation spaces TSS2 are formed, the preliminary blocking dielectric patterns 232P are exposed through the conductive spaces LS2 as illustrated in FIG. 16.

[0152] 16, the preliminary blocking dielectric patterns 232P are oxidized in the same manner as described in FIG 13B to form a first blocking dielectric pattern 232B made of an oxide film. Then, the processes described in FIG 13H and FIG 13I are performed to manufacture the integrated circuit device 200A illustrated in FIG 6A and FIG 6B.

[0153] 17A to 17C are cross-sectional views showing a process sequence to explain a manufacturing method of an integrated circuit device according to another embodiment of the present invention. In this embodiment, another exemplary manufacturing method of the integrated circuit device 300A shown in FIGS. 8A and 8B is explained. FIGS. 17A to 17C show an enlarged cross-sectional configuration of a portion corresponding to the dotted line region Q3 in FIG. 8A, shown in a process sequence. In FIGS. 17A to 17C, the same reference numerals as those in FIGS. 12A to 12M, 13A to 13I, and 14A to 14D indicate the same members, and detailed descriptions thereof will be omitted here.

[0154] Referring to Fig. 17A, the process described with reference to Fig. 13A to Fig. 13D is performed. However, in this example, the oxidation process of the preliminary blocking dielectric pattern 232P described with reference to Fig. 13B is omitted, and the process described with reference to Fig. 13C is performed on the resultant product of Fig. 13A in which the preliminary blocking dielectric patterns 232P remain. Thereafter, while the preliminary blocking dielectric patterns 232P formed in the process of Fig. 13A remain on the substrate 102, a charge trapping layer 334 is formed on the preliminary blocking dielectric patterns 232P in the same manner as described for the process of forming the charge trapping layer 334 with reference to Fig. 14A, and a tunneling dielectric layer 340, a channel layer 150, and a buried insulating layer 156 are sequentially formed thereon.

[0155] 17B, ​​a process for forming a word line cut region WLC, a plurality of conductive spaces LS3, and a plurality of separation spaces TSS3 is performed on the result of FIG. 17A in the same manner as described with reference to FIG. 14B. After the plurality of conductive spaces LS3 and the plurality of separation spaces TSS3 are formed, a plurality of preliminary blocking dielectric patterns 232P are exposed through the plurality of conductive spaces LS3.

[0156] Referring to Fig. 17C, in the result of Fig. 17B, the preliminary blocking dielectric patterns 232P are oxidized in the same manner as described in Fig. 13B to form a first blocking dielectric pattern 232B, and then the process described in Fig. 14C and Fig. 14D is performed to manufacture the integrated circuit device 300A illustrated in Fig. 8A and Fig. 8B.

[0157] 18A and 18B are cross-sectional views showing a process sequence for explaining a method for manufacturing an integrated circuit device according to another embodiment of the present invention. In this example, an exemplary method for manufacturing an integrated circuit device 400A illustrated in FIG. 10A will be explained.

[0158] Referring to FIG. 18A, the process described with reference to FIG. 12A to FIG. 12E is performed. However, in this example, in the process described with reference to FIG. 12A, a relatively thick mold film ML4 is formed in a portion corresponding to an area where a string select line SSL (see FIG. 1) is formed. In an exemplary embodiment, the first thickness of the mold film ML4 is thicker than the second thickness of the mold film ML formed in a portion corresponding to an area where a plurality of word lines WL (see FIG. 1) are formed. For example, the first thickness is at least twice as thick as the second thickness, but is not limited thereto.

[0159] 12E, the preliminary blocking dielectric patterns 432P formed on the sidewall of the mold film ML4 facing the inside of the channel hole CHH are formed to have concave sidewalls facing the inside of the channel hole CHH. On the other hand, the preliminary blocking dielectric patterns 132P formed on the sidewall of the mold film ML also have flat sidewalls facing the inside of the channel hole CHH.

[0160] 18B, the process described with reference to Figures 12F to 12J or the process described with reference to Figures 15A and 15B is performed on the resultant structure of Figure 18A to oxidize the preliminary blocking dielectric patterns 432P and the preliminary blocking dielectric patterns 132P to form a resultant structure in which the first blocking dielectric patterns 432B and the first blocking dielectric patterns 132B are exposed through the conductive spaces LS1. Then, the same process as that described with reference to Figures 12K to 12M is performed to manufacture the integrated circuit device 400A illustrated in Figure 10A.

[0161] 10B, a process for forming a second blocking dielectric pattern 464 including an air gap AG4 is performed in place of the second blocking dielectric pattern 462 illustrated in FIG. 10A to form the second blocking dielectric pattern 164 including the air gap AG1. The deposition process atmosphere, for example, deposition temperature, deposition pressure, etc., for forming the second blocking dielectric pattern 464 is controlled to form the second blocking dielectric pattern 464 including the air gap AG4.

[0162] According to a method for manufacturing an integrated circuit device according to the technical concept of the present invention, even when the spacing between adjacent cells in a vertical memory device in the vertical direction within a channel hole is relatively narrow, it is possible to provide a structure that suppresses cell interference due to charge diffusion between adjacent cells and improves reliability. Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications and alterations can be made by those having ordinary skill in the art within the technical spirit and scope of the present invention.

Claims

1. a conductive pattern extending on a substrate in a horizontal direction parallel to a main surface of the substrate; an insulating film extending in the horizontal direction on the substrate in parallel with the conductive pattern; a channel film extending in a vertical direction perpendicular to a main surface of the substrate within a channel hole penetrating the conductive pattern and the insulating film; a charge storage pattern interposed between the conductive pattern and the channel film in the channel hole; a dummy charge storage pattern interposed between the insulating film and the channel film in the channel hole, the dummy charge storing pattern is spaced apart from the charge storing pattern in the vertical direction; 11. An integrated circuit device comprising: a first charge storage pattern and a second charge storage pattern, the first charge storage pattern and the second charge storage pattern extending along a straight line and having the same width in the horizontal direction.

2. a first blocking dielectric pattern interposed between the conductive pattern and the charge storage pattern; 2. The integrated circuit device of claim 1, further comprising a second blocking dielectric pattern having a first portion interposed between the conductive pattern and the insulating film, a second portion interposed between the first blocking dielectric pattern and the insulating film, and a third portion interposed between the charge storing pattern and the dummy charge storing pattern, the first portion, the second portion, and the third portion being integrally connected.

3. 3. The integrated circuit device of claim 2, wherein the third portion of the second blocking dielectric pattern comprises an air gap located between the charge storing pattern and the dummy charge storing pattern.

4. a blocking dielectric pattern spaced apart from the channel film with the charge storage pattern interposed therebetween, a sidewall of the charge storing pattern facing the conductive pattern is closer to the channel layer than a sidewall of the dummy charge storing pattern facing the insulating layer; 2. The integrated circuit device of claim 1, wherein the blocking dielectric pattern has a sidewall that protrudes further toward the channel layer than the insulating layer.

5. a blocking dielectric pattern spaced apart from the channel film with the charge storage pattern interposed therebetween, 2. The integrated circuit device of claim 1, wherein the blocking dielectric pattern has a concave sidewall adjacent to a sidewall of the charge storage pattern facing the conductive pattern.

6. a first blocking dielectric pattern interposed between the conductive pattern and the charge storage pattern; a second blocking dielectric pattern having a first portion interposed between the conductive pattern and the insulating layer, a second portion interposed between the first blocking dielectric pattern and the insulating layer, and a third portion interposed between the charge storing pattern and the dummy charge storing pattern; a third blocking dielectric pattern spaced apart from the first blocking dielectric pattern and the insulating layer via the second blocking dielectric pattern and surrounding a portion of the conductive pattern, the first blocking dielectric pattern is made of a silicon oxide layer; 2. The integrated circuit device of claim 1, wherein the second and third blocking dielectric patterns are each comprised of a silicon oxide layer, a high dielectric layer, or a combination thereof.

7. a blocking dielectric pattern including a first pattern portion contacting a sidewall of the charge storing pattern facing the conductive pattern, and a second pattern portion contacting the charge storing pattern and the dummy charge storing pattern in a space between the charge storing pattern and the dummy charge storing pattern and surrounding a portion of the conductive pattern, 2. The integrated circuit device of claim 1, wherein the first pattern portion and the second pattern portion in the blocking dielectric pattern are connected to each other without an interface therebetween.

8. a blocking dielectric pattern in contact with the charge storing pattern and the dummy charge storing pattern and surrounding a portion of the conductive pattern, The blocking dielectric pattern comprises: a first blocking dielectric pattern in contact with the charge storing pattern and spaced apart from the conductive pattern and the dummy charge storing pattern; 2. The integrated circuit device of claim 1, further comprising: a second blocking dielectric pattern including a portion contacting the charge storing pattern and the dummy charge storing pattern, and a portion interposed between the first blocking dielectric pattern and the conductive pattern.

9. 2. The integrated circuit device of claim 1, wherein the charge storing pattern and the dummy charge storing pattern extend in a straight line.

10. 2. The integrated circuit device of claim 1, wherein a width of the charge storage pattern and a width of the dummy charge storage pattern are the same in the horizontal direction, and a minimum separation distance between the charge storage pattern and the channel layer in the horizontal direction is shorter than a minimum separation distance between the dummy charge storage pattern and the channel layer.

11. A plurality of conductive patterns extending on a substrate in a horizontal direction parallel to a main surface of the substrate and overlapping each other along a vertical direction perpendicular to the main surface; a plurality of insulating films each interposed between the plurality of conductive patterns and extending in the horizontal direction; a channel film extending in the vertical direction within a channel hole penetrating the plurality of conductive patterns and the plurality of insulating films; a plurality of charge trapping patterns disposed between the plurality of conductive patterns and the channel film in the channel hole and spaced apart from each other; a plurality of dummy charge trap patterns interposed between the plurality of insulating films and the channel film at positions spaced apart from the plurality of charge trap patterns in the vertical direction and spaced apart from each other; a plurality of blocking dielectric patterns including a plurality of first pattern portions and a plurality of second pattern portions, the plurality of first pattern portions being disposed one by one between each of the plurality of insulating films and interposed between the plurality of conductive patterns and the plurality of charge trapping patterns, and the plurality of second pattern portions surrounding a portion of each of the plurality of conductive patterns and filling a separation space between each of the plurality of charge trapping patterns and the plurality of dummy charge trapping patterns, 2. An integrated circuit device comprising: a first region that is formed on a first side of said first conductive layer and a second region that is formed on said first conductive layer;

12. In each of the plurality of blocking dielectric patterns, the first pattern portion contacts one of the plurality of charge trapping patterns, and the second pattern portion contacts one of the plurality of charge trapping patterns and one of the plurality of dummy charge trapping patterns, 12. The integrated circuit device of claim 11, wherein a length of each of the plurality of charge trapping patterns in the vertical direction is equal to or less than a length of each of the plurality of conductive patterns and is equal to or more than half a length of each of the plurality of conductive patterns.

13. 12. The integrated circuit device of claim 11, wherein the second pattern portions include portions that fill separation spaces between the charge trapping patterns and the dummy charge trapping patterns, and the portions that fill the separation spaces include air gaps.

14. a lower conductive line and an upper conductive line extending horizontally and parallel to each other on the substrate; an insulating film interposed between the lower conductive line and the upper conductive line and extending in the horizontal direction; a channel film formed in a channel hole extending vertically through the lower conductive line, the upper conductive line, and the insulating film; a lower charge trapping pattern interposed between the lower conductive line and the channel layer in the channel hole; an upper charge trapping pattern interposed between the upper conductive line and the channel layer in the channel hole and spaced apart in the vertical direction from the lower charge trapping pattern; a dummy charge trap pattern interposed between the insulating film and the channel film and spaced apart from the lower charge trap pattern and the upper charge trap pattern in the vertical direction; a lower first blocking dielectric pattern interposed between the lower conductive line and the channel layer; an upper first blocking dielectric pattern interposed between the upper conductive line and the channel layer; a lower second blocking dielectric pattern interposed between the lower conductive line and the lower first blocking dielectric pattern, filling a lower separation space between the lower charge trapping pattern and the dummy charge trapping pattern; an upper second blocking dielectric pattern interposed between the upper conductive line and the upper first blocking dielectric pattern, filling an upper separation space between the upper charge trapping pattern and the dummy charge trapping pattern; an integrated circuit device, wherein said lower charge trapping pattern, said upper charge trapping pattern and said dummy charge trapping pattern extend along a straight line and have the same width in said horizontal direction;

15. a thickness of the lower conductive line and a thickness of the upper conductive line in the vertical direction are different from each other; 15. The integrated circuit device of claim 14, wherein a sidewall of the lower first blocking dielectric pattern facing the channel layer and a sidewall of the upper first blocking dielectric pattern facing the channel layer have different shapes.

16. a plurality of conductive lines extending on a substrate in a horizontal direction parallel to a major surface of the substrate and overlapping each other along a vertical direction perpendicular to the major surface; a plurality of insulating films each interposed between each of the plurality of conductive lines and extending in the horizontal direction; a channel film extending in the vertical direction within a channel hole penetrating the plurality of conductive lines and the plurality of insulating films; a plurality of charge trapping patterns spaced apart from one another and interposed between the plurality of conductive lines and the channel film in the channel hole; a plurality of dummy charge trap patterns interposed between the plurality of insulating films and the channel film at positions spaced apart from the plurality of charge trap patterns in the vertical direction and spaced apart from each other; a plurality of first blocking dielectric patterns disposed between the insulating layers and interposed between the conductive lines and the charge trapping patterns; a plurality of second blocking dielectric patterns each including a portion surrounding a portion of each of the first blocking dielectric patterns and a portion of each of the conductive lines and filling a space between each of the charge trapping patterns and each of the dummy charge trapping patterns; a tunneling dielectric layer interposed between the first blocking dielectric patterns and the channel layer, 2. An integrated circuit device comprising: a first region that is formed on a first side of said first conductive layer and a second region that is formed on said first conductive layer;

17. forming a structure in which a plurality of insulating films and a plurality of mold films are stacked one on top of another on a substrate; forming a channel hole through the structure; removing portions of the mold films through the channel holes to form a plurality of mold indentations connected to the channel holes; forming a sacrificial layer and a preliminary dielectric pattern filling the interior of each of the plurality of mold indentations; oxidizing the preliminary dielectric pattern to form a first blocking dielectric pattern; forming a charge storage layer in the channel hole; forming a tunneling dielectric layer on the charge storage layer within the channel hole; forming a channel layer on the tunneling dielectric layer in the channel hole; removing the mold films to form conductive spaces between the insulating films; removing the sacrificial layer through the conductive space and removing a portion of the charge storage layer to form a plurality of separation spaces separating the charge storage layer into a plurality of charge storage patterns and a plurality of dummy charge storage patterns; forming a second blocking dielectric pattern filling the isolation spaces and covering the inner walls of the conductive spaces; forming a conductive pattern on the second blocking dielectric pattern within the conductive space.

18. forming a structure in which a plurality of insulating films and a plurality of mold films are stacked one on top of another on a substrate; forming a channel hole through the structure; removing portions of the mold films through the channel holes to form a plurality of mold indentations connected to the channel holes; forming a first blocking dielectric pattern within each of the plurality of mold indentations; forming a charge trapping layer covering the first blocking dielectric pattern in the channel hole; removing the plurality of mold layers to form a conductive space exposing the first blocking dielectric pattern; removing a portion of the charge trapping layer through the conductive space to form a plurality of separation spaces separating the charge trapping layer into a plurality of charge trapping patterns and a plurality of dummy charge trapping patterns; forming a second blocking dielectric pattern filling the separation spaces and covering the first blocking dielectric pattern in the conductive spaces; forming a conductive line within said conductive space.

19. forming a structure in which a plurality of insulating films and a plurality of mold films are stacked one on top of another on a substrate; forming a channel hole through the structure; removing portions of the mold films through the channel holes to form a plurality of mold indentations connected to the channel holes; forming a sacrificial layer and a preliminary dielectric pattern filling the interior of each of the plurality of mold indentations; forming a charge trapping layer covering the preliminary dielectric pattern in the channel hole; removing the plurality of mold layers to form a conductive space exposing the preliminary dielectric pattern; removing a portion of the charge trapping layer through the conductive space to form a plurality of separation spaces separating the charge trapping layer into a plurality of charge trapping patterns and a plurality of dummy charge trapping patterns; oxidizing the preliminary dielectric pattern through the conductive space to form a first blocking dielectric pattern; forming a second blocking dielectric pattern filling the separation spaces and covering the first blocking dielectric pattern in the conductive spaces; forming a conductive line within said conductive space.

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