Semiconductor Device

Abstract

To provide a semiconductor element that can reduce the process failure.SOLUTION: A semiconductor element according to the present invention includes a substrate, a plurality of conductive patterns provided on the substrate and separated from each other in a perpendicular direction that is perpendicular to a surface of the substrate, insulating patterns held between the conductive patterns in the perpendicular direction, side wall insulating patterns each provided on a side wall of each conductive pattern and covering a side wall of the conductive pattern, upper pad patterns, an interlayer insulating film covering the conductive patterns, the insulating patterns, the side wall insulating patterns, and the upper pad patterns, and contact plugs penetrating the interlayer insulating film and in contact with the upper pad patterns. An edge part of the conductive pattern includes a stepped part formed so that an end of one conductive pattern does not overlap in the perpendicular direction with the conductive pattern disposed thereon. The upper pad patterns are provided on an upper surface of the stepped part of the conductive pattern and an upper surface of a part of the side wall insulating pattern.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a vertical memory device having reduced process defects. [Background technology]

[0002] In recent years, vertical memory elements have been developed in which memory cells are stacked vertically from the surface of a substrate. The upper surface of the edge of the stacked conductive patterns included in each memory cell is provided as a pad pattern having a staircase shape. A contact plug is formed on the pad pattern.

[0003] However, the formation of the contact plugs can cause defects such as not-open or punching failure. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Publication No. 2007-0047309 Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE PRESENTLY PREFERRED EMBODIMENTS The present invention has been made in consideration of the problems inherent in the conventional vertical memory devices, and an object of the present invention is to provide a semiconductor device capable of reducing process defects. [Means for solving the problem]

[0006] In order to achieve the above object, a semiconductor device according to the present invention includes a substrate, a plurality of conductive patterns disposed on the substrate so as to be spaced apart from each other in a vertical direction perpendicular to a surface of the substrate, an insulating pattern interposed between the conductive patterns in the vertical direction, a sidewall insulating pattern disposed on sidewalls of the conductive patterns and covering the sidewalls of the conductive patterns, an upper pad pattern, an interlayer insulating film covering the conductive patterns, the insulating pattern, the sidewall insulating pattern, and the upper pad pattern, and contact plugs passing through the interlayer insulating film and contacting the upper pad pattern, wherein edges of the conductive patterns include stepped portions formed such that an end of one conductive pattern does not overlap with each conductive pattern disposed thereover in the vertical direction, and the upper pad pattern is provided on upper surfaces of the stepped portions of the conductive patterns and on upper surfaces of parts of the sidewall insulating patterns, The insulating pattern in contact with the bottom surface of each of the conductive patterns has a length longer than the conductive pattern located on the insulating pattern, and the insulating pattern in contact with the bottom surface of each of the conductive patterns protrudes from a side wall of the conductive pattern located on the insulating pattern. It is characterized by:

[0007] In order to achieve the above object, a semiconductor device according to the present invention includes a substrate, a plurality of conductive patterns disposed on the substrate so as to be spaced apart from each other in a vertical direction perpendicular to a surface of the substrate, an insulating pattern interposed between the conductive patterns in the vertical direction, sidewall insulating patterns each provided on a sidewall of the conductive patterns to cover the sidewall of the conductive patterns, and each provided on the insulating pattern, an upper pad pattern including polysilicon, an interlayer insulating film covering the conductive patterns, the insulating pattern, the sidewall insulating pattern, and the upper pad pattern, a dielectric film structure, a channel, the conductive pattern includes polysilicon, and an edge of the conductive pattern includes a stepped portion formed such that an end of one conductive pattern does not vertically overlap with each conductive pattern disposed thereover; the upper pad pattern is provided on an upper surface of the stepped portion of the conductive pattern and an upper surface of a part of the sidewall insulating pattern, and an upper surface of the upper pad pattern is disposed lower than an upper surface of the sidewall insulating pattern formed one layer above the upper pad pattern. The insulating pattern in contact with the bottom surface of each of the conductive patterns has a length longer than the conductive pattern located on the insulating pattern, and the insulating pattern in contact with the bottom surface of each of the conductive patterns protrudes from a side wall of the conductive pattern located on the insulating pattern. It is characterized by:

[0008] In order to achieve the above object, a semiconductor device according to the present invention includes a substrate, a plurality of conductive patterns disposed on the substrate so as to be spaced apart from each other in a vertical direction perpendicular to a surface of the substrate, insulating patterns interposed between the conductive patterns in the vertical direction, sidewall insulating patterns provided on sidewalls of the conductive patterns and covering at least the sidewalls of the conductive patterns, an upper pad pattern including polysilicon, an interlayer insulating film covering the conductive patterns, the insulating pattern, the sidewall insulating pattern, and the upper pad pattern, and contact plugs penetrating the interlayer insulating film and contacting each of the upper pad patterns, The conductive patterns include polysilicon, and edges of the conductive patterns include step portions formed such that an end of one conductive pattern does not vertically overlap with each conductive pattern disposed thereover, the upper pad patterns are each provided on an upper surface of the step portions of the conductive patterns, a bottom surface of each of the contact plugs is located on an upper surface or within an upper layer structure including the upper pad pattern and a lower conductive pattern in contact with the upper pad pattern, and the vertical thickness of each of the upper pad patterns is smaller than the vertical thickness of a layer structure of one conductive pattern and one insulating pattern. The insulating pattern in contact with the bottom surface of each of the conductive patterns has a length longer than the conductive pattern located on the insulating pattern, and the insulating pattern in contact with the bottom surface of each of the conductive patterns protrudes from a side wall of the conductive pattern located on the insulating pattern. It is characterized by: Effect of the Invention

[0009] In the semiconductor device according to the present invention, since the upper pad pattern is provided on the conductive pattern of the step portion, not-open or punching failure of the contact plug can be reduced. [Brief description of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing a schematic configuration of a vertical semiconductor device according to an embodiment of the present invention. [Diagram 2] 1 is a schematic plan view of a vertical semiconductor device according to an embodiment of the present invention; [Diagram 3] 2 is a cross-sectional view illustrating a detailed portion of a pad structure in a vertical semiconductor device according to an embodiment of the present invention; [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Figure 7] 1A to 1C are plan views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention; [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are plan views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention; [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Figure 12] 1A to 1C are plan views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention; [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Figure 14] 1A to 1C are plan views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention; [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Figure 16] 1 is a cross-sectional view showing a schematic configuration of a vertical semiconductor device according to an embodiment of the present invention. [Figure 17] 1 is a schematic plan view of a vertical semiconductor device according to an embodiment of the present invention; [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Figure 19]1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Figure 20] 1A to 1C are plan views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention; [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Figure 22] 1A to 1C are plan views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention; [Diagram 23] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Figure 24] 1 is a cross-sectional view showing a schematic configuration of a vertical semiconductor device according to an embodiment of the present invention. [Diagram 25] 1 is a schematic plan view of a vertical semiconductor device according to an embodiment of the present invention; [Figure 26] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Figure 27] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Figure 28] 1A to 1C are plan views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention; [Figure 29] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. [Diagram 30] 1A to 1C are plan views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention; [Diagram 31] 1A to 1C are plan views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Next, specific examples of embodiments for carrying out a semiconductor device according to the present invention will be described with reference to the drawings.

[0012] Hereinafter, a direction substantially perpendicular to the upper surface of the substrate is defined as a vertical direction, and two mutually intersecting horizontal directions substantially parallel to the upper surface of the substrate are defined as a first direction and a second direction, respectively. In an embodiment, the first and second directions are perpendicular to each other.

[0013] FIG. 1 is a cross-sectional view showing a schematic configuration of a vertical semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic plan view of a vertical semiconductor device according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view showing details of a portion of a pad structure in a vertical semiconductor device according to an embodiment of the present invention.

[0014] 1 to 3, a substrate 100 is provided which is divided into a first region and a second region. The first region is a cell region where memory cells are arranged, and the second region is a wiring region where wiring is connected. In one embodiment, the second region may be on both sides in a first direction from an edge of the first region. 1 and 2, only the second region located on one side of the first region is shown. Also, although only a portion of the first region is shown, the width of the first region in the first direction is actually greater than the width of the second region in the first direction.

[0015] Substrate 100 comprises a semiconductor material such as, for example, silicon or germanium. A lower insulating film 101 is formed on a substrate 100 . A conductive pattern structure 106c is provided on the lower insulating layer 101.

[0016] The conductive pattern structure 106c may have a shape that extends from a first region to second regions on both sides of the first region. The conductive pattern structure 106c extends parallel to the surface of the substrate 100 in a first direction. A plurality of conductive pattern structures 106c are provided, and the conductive pattern structures 106c are spaced apart from each other in the second direction. Openings 134 are provided between the conductive pattern structures 106c. In one embodiment, the openings 134 may separate the cell blocks. In this case, the openings 134 are arranged in cell block units.

[0017] First, the conductive pattern structure 106c on the first region will be described. The conductive pattern structure 106c on the first region includes a conductive pattern 104b and an insulating pattern 102b, and has a structure in which the conductive pattern 104b and the insulating pattern 102b are repeatedly stacked alternately. That is, the conductive patterns 104b are stacked vertically from the top surface of the substrate 100 while being spaced apart from each other. The conductive pattern 104b has a line shape extending in the first direction.

[0018] The upper and lower surfaces of the conductive pattern 104b and the insulating pattern 102b are substantially flat. In one embodiment, the conductive pattern 104b has a first thickness (t1) in the vertical direction. Additionally, the insulating pattern 102b has a second thickness (t2) in the vertical direction that is smaller than the first thickness (t1). The conductive pattern 104b includes a ground selection line (GSL), a string selection line (SSL), and a word line between the ground selection line and the string selection line. The conductive pattern 104b may include polysilicon.

[0019] The conductive pattern structure 106c on the second region will now be described. The edges of the conductive pattern structures 106c in the second region have a stepped shape. The conductive pattern structure 106c in the second region includes an insulating pattern 102b, a conductive pattern 104b, an upper pad pattern 114, and a sidewall insulating pattern 110.

[0020] The insulating pattern 102b and the conductive pattern 104b of the conductive pattern structure 106c in the second region are extended from the insulating pattern 102b and the conductive pattern 104b in the first region. Therefore, the insulating pattern 102b and the conductive pattern 104b have the same layered structure as the insulating pattern 102b and the conductive pattern 104b in the first region. That is, the insulating patterns 102b are disposed between the conductive patterns 104b, and the conductive patterns 104b are disposed so as to be spaced apart from each other in the vertical direction by the insulating patterns 102b. The conductive pattern 104b may have a line shape extending in a first direction.

[0021] Furthermore, the edges of the insulating pattern 102b and the conductive pattern 104b in the second region have a stepped shape. The insulating pattern 102b in contact with the bottom surface of one of the conductive patterns 104b has a length in the first direction that is longer than that of the conductive pattern 104b. That is, the insulating pattern 102b in contact with the bottom surface of each conductive pattern 104b protrudes in the first direction further than the conductive pattern 104b located on the insulating pattern 102b.

[0022] In each conductive pattern 104b in the second region, a portion that is not overlapped by an upper conductive pattern 104b is referred to as a step portion. At least a portion of the stepped portion of each conductive pattern 104b provides a lower pad pattern 112. In this embodiment, the lower pad pattern 112 is a portion of each conductive pattern 104 b that is not overlapped by the upper conductive pattern 104 b and the sidewall insulating pattern 110 .

[0023] Sidewall insulating patterns 110 are provided on the sidewalls of the conductive patterns 104b, respectively. The sidewall insulating pattern 110 covers the sidewall of the conductive pattern 104b. Sidewall insulating patterns 110 are provided on the insulating patterns 102b, respectively. The sidewall insulating pattern 110 includes an insulating material having a high etch selectivity with respect to the conductive pattern 104b and the insulating pattern 102b. In one embodiment, the sidewall insulating pattern 110 may include a nitride series material, such as silicon nitride.

[0024] In one embodiment, the top surface of the sidewall insulating pattern 110 and the top surface of the lower pad pattern 112 are located on the same plane. In one embodiment, the bottom surface of the sidewall insulating pattern 110 is flush with or lower than the bottom surface of the lower pad pattern 112 .

[0025] The upper pad pattern 114 covers at least the entire upper surface of the lower pad pattern 112 . In one embodiment, the upper pad pattern 114 is provided on an upper surface of the lower pad pattern 112 and a portion of an upper surface of the sidewall insulating pattern 110 . Therefore, the end of the upper pad pattern 114 protrudes further in the first direction than the end of the lower pad pattern 112 thereunder. However, the upper pad pattern does not protrude in the first direction beyond an end of the sidewall insulating pattern therebelow. The upper pad pattern 114 may include silicon. In one embodiment, the upper pad pattern 114 comprises polysilicon. The upper pad pattern 114 may be formed by epitaxially growing silicon on the lower pad pattern 112 .

[0026] In one embodiment, the top surface of the upper pad pattern 114 is lower than the top surface of the sidewall insulating pattern 110 formed on the first layer. In one embodiment, the thickness of the upper pad pattern 114 is less than the thickness of the structure in which one conductive pattern 104b and one insulating pattern 102b are stacked. If the thickness of the upper pad pattern 114 is thicker than a structure in which one conductive pattern 104b and one insulating pattern 102b are stacked, an interlayer bridge defect may occur between the upper pad patterns 114 located above and below.

[0027] The stacked structure of one lower pad pattern 112 and one upper pad pattern 114 provides one pad structure 116 . A contact plug 142 is formed on the pad structure 116 . The vertical thickness of the pad structure 116 is greater than the first thickness (t1) of the conductive pattern 104b.

[0028] In one embodiment, an upper pad pattern 114 is formed on an upper surface of the uppermost conductive pattern 104b of the conductive pattern structure 106c. That is, the upper pad pattern 114 located at the top of the conductive pattern structure 106c is formed on the first and second regions. A first interlayer insulating film 118 is provided covering the conductive pattern structure 106c. The top surface of the first interlayer insulating film 118 is flat. The first interlayer insulating film 118 may include silicon oxide. A channel structure 130 is provided which penetrates the conductive pattern structure 106c on the first region and the first interlayer insulating film 118 and is electrically connected to the substrate 100.

[0029] In one embodiment, a semiconductor pattern 120 is further provided between the substrate 100 and the channel structure 130 . The semiconductor pattern 120 may include, for example, single crystal silicon or polysilicon. The channel structure 130 includes a dielectric film structure 122 , a channel 124 , a buried insulating pattern 126 , and an upper conductive pattern 128 . The channel 124 may have a hollow cylinder shape, or a cup shape.

[0030] The channel 124 may comprise polysilicon or single crystal silicon. The buried insulating pattern 126 fills the interior space of the channel 124 . The dielectric membrane structure 122 is shaped to overlie the outer walls of the channel 124 . The dielectric film structure 122 is sequentially stacked on the outer wall of the channel 124 and includes a tunnel insulating film, a charge storage film, and a blocking film. An upper conductive pattern 128 is provided on the buried insulating pattern 126 and is electrically connected to the channel 124 .

[0031] A second interlayer insulating layer 132 is provided on the first interlayer insulating layer 118 . The first and second interlayer dielectric layers 118 and 132 may include the same material and be provided as a single interlayer dielectric layer. In one embodiment, a second insulating pattern 136 is provided that fills the interior of the openings 134 between the conductive pattern structures 106c. In one embodiment, a common source line (not shown) is provided that passes through the second insulating pattern 136 inside the opening 134 and is connected to the substrate. The common source line is spaced apart from each conductive pattern 104b.

[0032] The contact plugs 142 penetrate the first and second interlayer insulating layers 118 and 132 and contact the pad structures 116, respectively. Therefore, the contact plugs 142 are electrically connected to the conductive patterns 104b, respectively. In one embodiment, the contact plug 142 may include a barrier metal pattern and a metal pattern. The contact plugs 142 each contact the upper pad pattern 114 .

[0033] The bottom surface of the contact plug 142 may be located on the upper surface or within the stacked structure of the upper pad pattern 114 and the lower pad pattern. That is, the bottom surface of the contact plug 142 may be located on or within the upper surface of the pad structure 116 . As an example, the bottom surface of the contact plug 142 that contacts the pad structure 116 located at the top of the staircase is located relatively lower within the pad structure 116, and the bottom surface of the contact plug 142 that contacts the pad structure 116 located at the bottom of the staircase is located relatively higher within the pad structure 116.

[0034] In this manner, the thickness of the portion where the bottom of the contact plug 142 is located increases, so that the process margin increases and defects of the contact plug 142 can be reduced. For example, punching defects in which the contact plug 142 does not contact (eg, is disconnected from) the pad structure 116 or the contact plug 142 extends into a conductive pattern below the target pad structure can be reduced.

[0035] A wiring line (not shown) electrically connected to an upper surface of the contact plug 142 is further provided on the second interlayer insulating film 132 . In one embodiment, the wiring line has a line shape extending in the second direction. In addition, a wiring line electrically connected to the channel structure 130 is further provided on the second interlayer insulating film 132 .

[0036] 4 to 15 are cross-sectional and plan views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. 4 to 6, 8, 9, 11, 13, and 15 are cross-sectional views, and FIGS. 7, 10, 12, and 14 are plan views.

[0037] Referring to FIG. 4, a lower insulating layer 101 is formed on a substrate 100 in the first and second regions, and a first conductive layer 104 and an insulating layer 102 are alternately and repeatedly stacked on the lower insulating layer 101 to form a stacked structure. In one embodiment, the lower insulating film 101 and the insulating film 102 are formed of an oxide-based material such as silicon oxide, silicon carbonate, or silicon oxyfluoride. In one embodiment, the first conductive film 104 is formed of polysilicon.

[0038] In one embodiment, the lower insulating film 101 in direct contact with the substrate 100 has a greater vertical thickness than the insulating film 102 located above it. In one embodiment, the insulating film 102 has a thickness less than the thickness of the first conductive film 104 . By reducing the thickness of the insulating film 102, the height of the stacked structure can be reduced.

[0039] Referring to FIG. 5, a portion of the insulating film 102 and the first conductive film 104 is stepwise etched to form a first preliminary conductive pattern structure 106a having a stepped edge. The first preliminary conductive pattern structure 106a is formed by repeatedly stacking preliminary conductive patterns 104a and preliminary insulating patterns 102a in an alternating manner. Since only a portion of the thickness of the lower insulating film 101 remains on the surface of the substrate 100 , the surface of the substrate 100 is covered. Therefore, the surface of the substrate 100 located on the side of the first preliminary conductive pattern structure 106a is not exposed.

[0040] In one embodiment, the edge of the first preliminary conductive pattern structure 106a has a step shape in the first direction. In some embodiments, although not shown, the edges of the first preliminary conductive pattern structure 106a may be formed to have a stepped shape in each of the first and second directions. An upper surface of the preliminary insulating pattern 102a is exposed at the stepped portion of the first preliminary conductive pattern structure 106a. In one embodiment, the preliminary insulating pattern 102a located at the step portion is thinner than the thickness of the insulating film 102 as deposited. In some embodiments, the preliminary insulating pattern 102a at the step portion may have the same thickness as the insulating film 102 as deposited.

[0041] 6 and 7, the preliminary conductive pattern 104a exposed on the sidewall of the first preliminary conductive pattern structure 106a is partially etched to form a conductive pattern 104b. In addition, an undercut portion 108 defined by the conductive pattern 104b and the preliminary insulating patterns 102a located above and below the conductive pattern 104b is formed by the etching process. The etching process includes an isotropic etching process. Also, in one embodiment, the isotropic etching process may include a wet etching process or an isotropic dry etching process.

[0042] In one embodiment, the width of the undercut portion 108 in the first direction may be 200 Å to 500 Å. Since the width of the undercut portion 108 in the first direction is increased, the length of the preliminary conductive pattern in the first direction must be increased. Therefore, the width of the first preliminary conductive pattern structure 106a in the first direction increases. On the other hand, if the width of the undercut portion 108 in the first direction is smaller than, for example, 200 Å, an interlayer bridge defect between pad patterns may occur in a subsequent process. More preferably, the width of the undercut portion 108 in the first direction may be 200 Å to 300 Å.

[0043] Referring to FIG. 8, a sidewall insulating pattern 110 is formed to fill the undercut portion 108 . Specifically, an insulating film is conformally formed on the surface of the first preliminary conductive pattern structure 106a while filling the undercut portion 108. Thereafter, the insulating film is anisotropically etched to form a sidewall insulating pattern 110. The sidewall insulating pattern 110 is formed using an insulating material having a high etch selectivity with respect to the conductive pattern 104b and the preliminary insulating pattern 102a. In one embodiment, the sidewall insulating pattern 110 is formed using a nitride series material such as silicon nitride.

[0044] 9 and 10, the preliminary insulating pattern 102a formed on the upper surface of the step portion of the first preliminary conductive pattern structure 106a is etched to form an insulating pattern 102b. By the etching process, the top surface of the conductive pattern 104b in the step portion and the top surface of the sidewall insulating pattern 110 are exposed. The etching process may include an anisotropic etching process. A sidewall insulating pattern 110 is formed on the sidewall of the conductive pattern 104b.

[0045] According to the above process, the sidewalls of the step portion of the first preliminary conductive pattern structure 106a correspond to the sidewalls of the sidewall insulating pattern 110 and the sidewalls of the insulating pattern 102b. Furthermore, the conductive pattern 104b and the top surface of the sidewall insulating pattern 110 are exposed at the stepped portion of the first preliminary conductive pattern structure 106a. The lower insulating film 101 in contact with the surface of the substrate 100 remains partially even after the etching process. Therefore, the surface of the substrate 100 is covered with the lower insulating film 101 .

[0046] In the first preliminary conductive pattern structure 106a, the conductive pattern 104b formed in the first region serves as a gate pattern, and the conductive pattern 104b formed in the second region is connected to the gate pattern. In addition, a portion of the conductive pattern 104b formed in the second region that is exposed at the step portion is provided as a lower pad pattern 112.

[0047] 11 and 12, a selective epitaxial growth process is performed on the lower pad pattern 112 to form an upper pad pattern 114. As shown in FIG. The upper pad pattern 114 is formed by growing silicon using the lower pad pattern 112 containing polysilicon as a seed. In one embodiment, the upper pad pattern 114 comprises polysilicon. By carrying out the above steps, a second preliminary conductive pattern structure 106b is formed.

[0048] By performing a selective epitaxial growth process, the upper pad pattern 114 grows vertically and laterally. Therefore, the upper pad pattern 114 is formed on the upper surface of the lower pad pattern 112 and also on the upper surface of a portion of the sidewall insulating pattern 110 . The top surface of the upper pad pattern 114 is lower than the top surface of the sidewall insulating pattern 110 formed on the first layer. If the top surface of the upper pad pattern 114 is higher than the top surface of the sidewall insulating pattern 110 formed on the layer above, the upper pad pattern 114 and the lower pad pattern 112 on the layer above may come into contact with each other, which is undesirable.

[0049] The stacked structure of the lower pad pattern 112 and the upper pad pattern 114 is provided as a pad structure 116 . Meanwhile, an upper pad pattern 114 is formed on the uppermost conductive pattern of the second preliminary conductive pattern structure 106b. For example, the second preliminary conductive pattern structure 106b formed in the first and second regions has a structure in which the conductive pattern 104b and the upper pad pattern 114 are stacked on the uppermost portion.

[0050] 13 and 14, a first interlayer insulating film 118 is formed to cover the second preliminary conductive pattern structure 106b. In one embodiment, the first interlayer insulating film 118 is formed of an oxide film such as silicon oxide, silicon carbonate, or silicon oxyfluoride, and is formed by performing a planarization process on the top surface of the deposited oxide film. The planarization process may include a chemical-mechanical polishing and / or an etch-back process.

[0051] Thereafter, a channel hole is formed through the second preliminary conductive pattern structure 106b in the first region and the first interlayer insulating film 118 to expose the surface of the substrate 100. As shown in FIG. A channel structure 130 is formed inside each of the channel holes. In an embodiment, a semiconductor pattern 120 may be further formed under the channel structure 130 in contact with the substrate 100 .

[0052] Specifically, a selective epitaxial growth process is performed on the substrate 100 exposed by the channel hole to form the semiconductor pattern 120 . A channel structure 130 including a dielectric film structure 122, a channel 124, a buried insulating pattern 126, and an upper conductive pattern 128 is formed on the semiconductor pattern 120. A second interlayer insulating film 132 is formed on the first interlayer insulating film 118 to cover the channel structure 130 . The second preliminary conductive pattern structure 106b and the first and second interlayer insulating films 118 and 132 are anisotropically etched to form an opening 134 extending in a first direction. In one embodiment, the openings 134 are formed to separate blocks of cells of a semiconductor device.

[0053] In one embodiment, a second insulating pattern 136 is formed to fill the interior of the opening 134 . In some embodiments, a common source line (not shown) is formed through the second insulating pattern 136 inside the opening 134 to connect with the substrate. The common source line is spaced apart from each conductive pattern 104b. Thus, the second preliminary conductive pattern structures 106b are separated from each other to form conductive pattern structures 106c on both sides of the opening 134. The conductive pattern structure 106c extends in a first direction.

[0054] The surface of the substrate 100 is exposed at the bottom of the opening 134 . The conductive pattern structure 106c in the first region includes an insulating pattern 102b and a conductive pattern 104b. The conductive pattern structure 106c in the second region includes an insulating pattern 102b, a conductive pattern 104b, an upper pad pattern 114, and a sidewall insulating pattern 110.

[0055] Referring to FIG. 15, the first and second interlayer insulating films 118 and 132 are etched to form the pad structures 116 and the contact holes 140 that respectively expose the pad structures 116. That is, the bottom of the contact hole 140 exposes the lower pad pattern 112 or the upper pad pattern 114 .

[0056] In one embodiment, the pad structures 116 have a stepped shape such that the vertical height of the top surface of each pad structure 116 differs from one another. Therefore, before the contact hole 140 is formed in the lowermost pad structure 116 in the etching process, the contact hole 140 is already formed in the uppermost pad structure 116 . Therefore, during the etching process, the overlying pad structure 116 may be over-etched. However, since the pad structure 116 has a shape in which the lower pad pattern 112 and the upper pad pattern 114 are stacked, the thickness increases, which can reduce defects in which the bottom of the contact hole 140 is punched below the bottom of the lower pad pattern 112 due to over-etching.

[0057] 1 and 2, a conductive material is formed inside the contact hole 140 to form a contact plug 142. As shown in FIG. Specifically, a barrier metal layer is formed on the surface of the contact hole 140, a metal layer is formed on the barrier metal layer, and then the barrier metal layer is planarized so that the top surface of the second interlayer insulating film 132 is exposed. Although not shown, a wiring line electrically connected to an upper surface of the contact plug 142 is formed on the second interlayer insulating film 132 . In addition, a wiring line electrically connected to the channel structure 130 is formed on the second interlayer insulating film 132 .

[0058] 16 and 17 are a cross-sectional view and a schematic plan view showing a schematic configuration of a vertical semiconductor device according to an embodiment of the present invention. The vertical semiconductor device is substantially the same as the vertical semiconductor device described with reference to FIGS. 1 to 3, except for the shape of the conductive pattern structure formed in the second region. Therefore, duplicated explanations will be omitted or explained briefly.

[0059] 16 and 17, the edge of the conductive pattern structure 107b in the second region has a step shape. The conductive pattern structure 107b in the second region includes an insulating pattern 102b, a conductive pattern 105a, an upper pad pattern 114a, and a sidewall insulating pattern 150a. In the conductive pattern structure 107b in the second region, the insulating pattern 102b and the conductive pattern 105a are extended from the insulating pattern 102b and the conductive pattern 105a in the first region.

[0060] Moreover, the insulating pattern 102b and the conductive pattern 105a in the second region have stepped edges. A portion of the stepped portion of each conductive pattern 105a is provided as a lower pad pattern 112a. In this embodiment, the lower pad pattern 112a is a portion of each conductive pattern 105a that is not overlapped by the upper conductive pattern 105a and the sidewall insulating pattern 150a.

[0061] The sidewall insulating pattern 150a is formed on the sidewall of the lower pad pattern 112a. The sidewall insulating pattern 150a includes an insulating material having a high etch selectivity with respect to the conductive pattern 105a. In one embodiment, the sidewall insulating pattern 150a is formed using a nitride-based material such as silicon nitride. In some embodiments, the sidewall insulating pattern 150a may also include silicon oxide. In some embodiments, the sidewall insulating pattern 150a may have a structure in which a silicon oxide layer and a silicon nitride layer are stacked.

[0062] The top surface of the sidewall insulating pattern 150a formed on the sidewall of each conductive pattern 105a is higher than the top surface of each conductive pattern 105a in the step portion. That is, the top surface of the sidewall insulating pattern 150a formed on the sidewall of each conductive pattern 105a protrudes from the top surface of each conductive pattern 105a in the stepped portion. In one embodiment, the width of the sidewall insulating pattern 150a in the first direction has a thickness smaller than half the width of the step portion of the conductive pattern 105a in the first direction. Furthermore, the width of the sidewall insulating pattern 150a in the first direction is greater than the first thickness of the insulating pattern 102b in the first region.

[0063] The upper pad pattern 114a covers at least the upper surface of the lower pad pattern 112a. The upper pad pattern 114a may include silicon. In one embodiment, the upper pad pattern 114a may include polysilicon. The upper pad pattern 114a may be formed by epitaxially growing silicon on the lower pad pattern 112a.

[0064] In one embodiment, the top surface of the upper pad pattern 114a is flush with or lower than the top surface of the sidewall insulating pattern 150a. In one embodiment, the thickness of the upper pad pattern 114a is less than the thickness of the stack of one conductive pattern 105a and one insulating pattern 102b. In one embodiment, a conductive pattern 105a and an upper pad pattern 114a are stacked on the top of the conductive pattern structure 107b. That is, the upper pad pattern 114a located at the top of the conductive pattern structure 107b is formed on the first and second regions.

[0065] A first interlayer insulating film 118 is provided covering the conductive pattern structure 107b. A channel structure 130 is provided which penetrates the conductive pattern structure 107b on the first region and the first interlayer insulating film 118 and is electrically connected to the substrate 100. A second interlayer insulating layer 132 is provided on the first interlayer insulating layer 118 . The contact plugs 142 penetrate the first and second interlayer insulating layers 118 and 132 and contact the pad structures 116a in which the lower pad pattern 112a and the upper pad pattern 114a are stacked.

[0066] 18 to 23 are cross-sectional and plan views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. 18, 19, 21 and 23 are cross-sectional views, and FIGS. 20 and 22 are plan views. Referring to FIG. 18, first, substantially the same steps as those described with reference to FIGS. 4 and 5 are carried out. Therefore, a first preliminary conductive pattern structure 106a is formed on the lower insulating layer. The first preliminary conductive pattern structure 106a is formed by repeatedly stacking the conductive patterns 105a and the preliminary insulating patterns 102a in an alternating manner.

[0067] A spacer insulating layer 150 is conformally formed on the first preliminary conductive pattern structure 106 a and the lower insulating layer 101 . The spacer insulating layer 150 is formed flat on at least a portion of the upper surface of the stepped portion of the first preliminary conductive pattern structure 106a. If the spacer insulating layer 150 is thick, the horizontal area on which an upper pad pattern is to be formed in a subsequent process is reduced. In one embodiment, the spacer insulating film 150 has a thickness less than half the width of the step portion of the first preliminary conductive pattern structure 106a in the first direction. On the other hand, if the spacer insulating layer 150 is thin, the height of the upper pad pattern in the subsequent process will be small. In one embodiment, the spacer insulating layer 150 is thicker than the vertical thickness of the preliminary insulating pattern 102a in the first region.

[0068] The spacer insulating layer 150 includes an insulating material having a high etching selectivity with respect to the conductive pattern 105a. In one embodiment, the spacer insulating layer 150 is formed using a nitride-based material such as silicon nitride. In some embodiments, the spacer dielectric 150 can also include silicon oxide. In some embodiments, the spacer insulating film 150 may be formed by stacking a silicon oxide film and a silicon nitride film.

[0069] 19 and 20, the spacer insulating layer 150 is anisotropically etched to form sidewall insulating patterns 150a on the sidewalls of the first preliminary conductive pattern structures 106a. The sidewall insulating pattern 150a protects the conductive pattern 105a and the preliminary insulating pattern 102a in the step portion of the first preliminary conductive pattern structure 106a.

[0070] Next, the preliminary insulating pattern 102a is anisotropically etched at the step portion of the first preliminary conductive pattern structure 106a adjacent to the sidewall insulating pattern 150a to form an insulating pattern 102b. Therefore, the conductive pattern 105a is exposed at a step portion adjacent to the sidewall insulating pattern 150a. The conductive pattern 105a exposed at the step portion is provided as a lower pad pattern 112a.

[0071] The top surface of the sidewall insulating pattern 150a formed on the sidewall of each conductive pattern 105a is higher than the top surface of each conductive pattern 105a in the step portion. That is, the top surface of the sidewall insulating pattern 150a formed on the sidewall of each conductive pattern 105a protrudes from the top surface of each conductive pattern 105a in the stepped portion. Therefore, a recess is formed on each conductive pattern 105a of the step portion by the sidewall insulating pattern 150a.

[0072] 21 and 22, a selective epitaxial growth process is performed on the lower pad pattern 112a to form an upper pad pattern 114a. The upper pad pattern 114a may be formed by growing silicon using the lower pad pattern 112a, which includes polysilicon, as a seed. In one embodiment, the upper pad pattern 114a may include polysilicon. By carrying out the above steps, a second preliminary conductive pattern structure 107a is formed.

[0073] In one embodiment, the upper pad pattern 114a is formed in a recess created by the sidewall insulating pattern 150a. For example, the top surface of the upper pad pattern 114a may be flush with the top surface of the sidewall insulating pattern 150a, or may be lower than the top surface of the sidewall insulating pattern 150a. If the top surface of the upper pad pattern 114a is formed higher than the top surface of the sidewall insulating pattern 150a, the upper pad patterns 114a formed in each layer may contact each other due to excessive growth of the upper pad pattern 114a.

[0074] Meanwhile, an upper pad pattern 114a is formed on the uppermost conductive pattern 105a of the first preliminary conductive pattern structure 106a. Therefore, the uppermost part of the second preliminary conductive pattern structure 107a has a structure in which the conductive pattern 105a and the upper pad pattern 114a are stacked.

[0075] Referring to FIG. 23, the same steps are carried out as those described with reference to FIGS. Thus, the conductive pattern structure 107b, the channel structure 130, the first interlayer insulating film 118, and the second interlayer insulating film 132 are formed. Also, an insulating pattern is formed in the opening and inside the opening.

[0076] 16 and 17, the first and second interlayer insulating layers 118 and 132 are etched to form contact holes exposing the pad structures 116a, respectively. That is, the bottom of the contact hole exposes the lower pad pattern 112a or the upper pad pattern 114a. A conductive material is formed inside the contact hole to form a contact plug 142 .

[0077] 24 and 25 are a cross-sectional view and a schematic plan view showing a schematic configuration of a vertical semiconductor device according to an embodiment of the present invention. The vertical semiconductor device is substantially the same as the vertical semiconductor device described with reference to FIGS. 1 to 3, except for the shape of the conductive pattern structure formed in the second region. Therefore, duplicated explanations will be omitted or explained briefly.

[0078] 24 and 25, the edge of the conductive pattern structure 107d in the second region has a step shape. The conductive pattern structure 107d in the second region includes an insulating pattern 103a, a conductive pattern 105a, an upper pad pattern 114b, and a spacer insulating layer 160.

[0079] In the conductive pattern structure 107d in the second region, the insulating pattern 103a and the conductive pattern 105a are extended from the insulating pattern 103a and the conductive pattern 105a in the first region. Moreover, the conductive pattern 105a in the second region has a stepped edge. A portion of the step portion of each conductive pattern 105a is provided as a lower pad pattern 112b.

[0080] The spacer insulating film 160 covers the surface of the structure in which the insulating pattern 103a and the conductive pattern 105a are stacked. The spacer insulating film 160 conformally covers the surface of the conductive pattern 105a in the step portion. The spacer insulating layer 160 includes an insulating material having a high etching selectivity with respect to the conductive pattern 105a. In one embodiment, the spacer insulating layer 160 may include a nitride-based material, such as silicon nitride. In some embodiments, the spacer dielectric 160 may include silicon oxide.

[0081] In one embodiment, the spacer insulating layer 160 has a thickness less than half the width of the step portion of the conductive pattern structure 107d in the first direction. In one embodiment, the spacer insulating layer 160 is thicker than the vertical thickness of the insulating pattern 103a in the first region. The spacer insulating film 160 includes a hole 162 (see FIG. 27) that exposes a part of the stepped portion of the conductive pattern 105a. In one embodiment, the hole 162 passes through the spacer insulating layer 160 and the insulating pattern 103a formed in the step portion. The portion of the conductive pattern 105a exposed at the bottom of the hole 162 serves as a lower pad pattern 112b.

[0082] An upper pad pattern 114b is provided inside the hole 162. The upper pad pattern 114b contacts the upper surface of the conductive pattern 105a. That is, an upper pad pattern 114b is provided on a lower pad pattern 112b. The upper pad pattern 114b may include silicon. In one embodiment, the upper pad pattern 114b may include polysilicon. The upper pad pattern 114b may be formed by epitaxially growing silicon on the lower pad pattern 112b.

[0083] In one embodiment, the top pad pattern 114b completely fills the inside of the hole 162 or fills only a portion of the hole 162. For example, the upper surface of the upper pad pattern 114 b is located on the same plane as the upper entrance of the hole 162 . As another example, the top surface of the upper pad pattern 114 b is located lower than the upper entrance of the hole 162 . In one embodiment, the thickness of the upper pad pattern 114b is less than the thickness of the stack of one conductive pattern 105a and one insulating pattern 103a.

[0084] The upper pad pattern 114b covers a part of the upper surface of the stepped portion of the conductive pattern 105a. The upper pad pattern 114b has an isolated pattern shape on the upper surface of the stepped portion of the conductive pattern 105a. In one embodiment, an upper pad pattern 114b having an isolated shape is also laminated on the uppermost conductive pattern 105a of the conductive pattern structure 107d.

[0085] A first interlayer insulating film 118 is provided covering the conductive pattern structure 107d. A channel structure 130 is provided which penetrates the conductive pattern structure 107d on the first region and the first interlayer insulating film 118 and is electrically connected to the substrate 100. A second interlayer insulating layer 132 is provided on the first interlayer insulating layer 118 . The contact plugs 142 penetrate the first and second interlayer insulating layers 118 and 132 and contact the pad structures 116b in which the lower pad pattern 112b and the upper pad pattern 114b are stacked.

[0086] 26 to 31 are cross-sectional and plan views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment of the present invention. 26, 27, and 29 are cross-sectional views, and FIGS. 28, 30, and 31 are plan views.

[0087] Referring to FIG. 26, first, substantially the same steps as those described with reference to FIGS. 4 and 5 are carried out. Therefore, a first preliminary conductive pattern structure 106 a is formed on the lower insulating layer of the substrate 100 . The first preliminary conductive pattern structure 106a is formed by repeatedly stacking the conductive patterns 105a and the preliminary insulating patterns 102a in an alternating manner. A spacer insulating layer 160 is conformally formed on the first preliminary conductive pattern structure 106 a and the lower insulating layer 101 . The spacer insulating layer 160 is formed flat on at least a portion of the upper surface of the stepped portion of the first preliminary conductive pattern structure 106a.

[0088] If the spacer insulating layer 160 is thick, the horizontal area on which an upper pad pattern is to be formed in a subsequent process is reduced. In one embodiment, the spacer insulating layer 160 has a thickness less than half the width of the step portion of the first preliminary conductive pattern structure 106a in the first direction. On the other hand, if the spacer insulating layer 160 is thin, the height of the upper pad pattern in the subsequent process is small. In one embodiment, the spacer insulating layer 160 is thicker than the vertical thickness of the preliminary insulating pattern 102a in the first region.

[0089] The spacer insulating layer 160 includes an insulating material having a high etching selectivity with respect to the conductive pattern 105a. In one embodiment, the spacer insulating layer 160 is formed using a nitride-based material such as silicon nitride. In some embodiments, the spacer dielectric 160 may also include silicon oxide.

[0090] 27 and 28, a hole 162 is formed by etching the spacer insulating layer 160 formed on the step portion of the first preliminary conductive pattern structure 106a and the preliminary insulating pattern 102a thereunder. The preliminary insulating pattern 102a is converted into an insulating pattern 103a. At the bottom of each hole 162, the upper surface of the conductive pattern 105a is exposed. The conductive pattern 105a exposed by the hole 162 serves as a lower pad pattern 112b.

[0091] 29 and 30, a selective epitaxial growth process is performed on the lower pad pattern 112b exposed at the stepped portion to form an upper pad pattern 114b. The upper pad pattern 114b may be formed by growing silicon using the lower pad pattern 112b, which includes polysilicon, as a seed. In one embodiment, the upper pad pattern 114b may include polysilicon. By carrying out the above steps, a second preliminary conductive pattern structure 107c is formed.

[0092] In one embodiment, the upper pad pattern 114b is formed inside the hole 162. As an example, the top pad pattern 114b may completely fill the hole 162 or may only partially fill the hole 162. The upper pad pattern 114b is formed in an isolated shape on a portion of the upper surface of the stepped portion of the conductive pattern 105a. Meanwhile, an upper pad pattern 114b having an isolated shape is formed on the uppermost conductive pattern 105a of the first preliminary conductive pattern structure 106a.

[0093] Referring to FIG. 31, the same steps are carried out as those described with reference to FIGS. Thus, the conductive pattern structure 107d, the channel structure 130, the first interlayer insulating film 118, and the second interlayer insulating film 132 are formed. In addition, the opening 134 and the second insulating pattern 136 are formed inside the opening 134 .

[0094] 24 and 25, the first and second interlayer insulating films 118 and 132 are etched to form contact holes exposing pad structures 116b in which the lower pad pattern 112b and the upper pad pattern 114b are stacked. That is, the bottom of the contact hole exposes the lower pad pattern 112b or the upper pad pattern 114b. A conductive material is formed inside the contact hole to form a contact plug 142 .

[0095] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Industrial Applicability]

[0096] The present invention is suitable for use in a variety of electronic products that use vertical semiconductor devices. [Explanation of symbols]

[0097] 100 Substrates 101 Lower insulating film 102 Insulating film 102a Spare insulation pattern 102b Insulation pattern 104 First conductive film 104a Spare conductive pattern 104b, 105a Conductive patterns 106a First preliminary conductive pattern structure 106b, 107a Second preliminary conductive pattern structure 106c, 107b Conductive pattern structure 108 Undercut area 110 Sidewall insulation pattern 112 Lower Pad Pattern 114 Upper Pad Pattern 116 Pad Structure 118 First interlayer insulating film 120 Semiconductor Pattern 122 Dielectric membrane structure 124 Channels 126 Buried insulation pattern 128 Upper conductive pattern 130 Channel Structures 132 Second interlayer insulating film 134 Opening 136 Second insulation pattern 140 Contact Hole 142 Contact plug

Claims

1. A substrate; A plurality of conductive patterns disposed on the substrate so as to be spaced apart from each other in a vertical direction perpendicular to a surface of the substrate; an insulating pattern interposed vertically between the conductive patterns; sidewall insulating patterns provided on sidewalls of the conductive patterns to cover the sidewalls of the conductive patterns; An upper pad pattern; an interlayer insulating film covering the conductive pattern, the insulating pattern, the sidewall insulating pattern, and the upper pad pattern; contact plugs passing through the interlayer insulating film and contacting the upper pad pattern, the edge of the conductive pattern includes a step portion formed so that an end of one conductive pattern does not vertically overlap with each conductive pattern disposed thereover; the upper pad pattern is formed on an upper surface of a stepped portion of the conductive pattern and an upper surface of a portion of the sidewall insulating pattern, an insulating pattern in contact with a bottom surface of each of the conductive patterns has a length longer than the conductive pattern located on the insulating pattern; 4. A semiconductor device comprising: a first insulating pattern that is in contact with a bottom surface of each of said conductive patterns; and a second insulating pattern that is in contact with a bottom surface of each of said conductive patterns.

2. 2. The semiconductor device of claim 1, wherein the conductive pattern and the upper pad pattern comprise polysilicon.

3. 3. The semiconductor device of claim 2, wherein the upper pad pattern comprises polysilicon formed by epitaxial growth from an upper surface of the conductive pattern.

4. 2. The semiconductor device of claim 1, wherein the sidewall insulating pattern comprises an insulating material having a high etch selectivity with respect to the conductive pattern and the insulating pattern.

5. 2. The semiconductor device of claim 1, wherein an upper surface of the sidewall insulating pattern and an upper surface of the step portion of the conductive pattern are located on the same plane.

6. 2. The semiconductor device of claim 1, wherein an end of the upper pad pattern protrudes further laterally than an end of the conductive pattern that contacts a bottom surface of the upper pad pattern.

7. 2. The semiconductor device of claim 1, wherein a bottom surface of the upper pad pattern contacts at least a portion of an upper surface of the sidewall insulating pattern.

8. 2. The semiconductor device of claim 1, wherein an upper surface of the upper pad pattern is located lower than an upper surface of the sidewall insulating pattern formed on a layer above the upper pad pattern.

9. 2. The semiconductor device of claim 1, wherein an upper surface of the sidewall insulating pattern is located higher than an upper surface of the conductive pattern at a stepped portion in contact with the sidewall insulating pattern.

10. The semiconductor device of claim 1 , wherein the upper pad pattern covers an entire upper surface of the step portion of the conductive pattern that is not covered by the insulating pattern.

11. 2. The semiconductor device of claim 1, wherein a bottom surface of the contact plug is located on or within an upper surface of a stacked structure including the upper pad pattern and a lower conductive pattern in contact with the upper pad pattern.

12. A substrate; A plurality of conductive patterns disposed on the substrate so as to be spaced apart from each other in a vertical direction perpendicular to a surface of the substrate; an insulating pattern interposed vertically between the conductive patterns; sidewall insulating patterns each formed on a sidewall of the conductive pattern to cover the sidewall of the conductive pattern and each formed on the insulating pattern; an upper pad pattern comprising polysilicon; an interlayer insulating film covering the conductive pattern, the insulating pattern, the sidewall insulating pattern, and the upper pad pattern; a channel structure connected to the substrate through the conductive pattern and the insulating pattern, the channel structure including a dielectric film structure, a channel, a buried insulating pattern, and an upper conductive pattern; contact plugs passing through the interlayer insulating film and contacting the upper pad pattern, the conductive pattern includes polysilicon; the edge of the conductive pattern includes a step portion formed so that an end of one conductive pattern does not vertically overlap with each conductive pattern disposed thereover; the upper pad pattern is formed on an upper surface of a stepped portion of the conductive pattern and an upper surface of a portion of the sidewall insulating pattern, an upper surface of the upper pad pattern is disposed lower than an upper surface of the sidewall insulating pattern formed on a layer above the upper pad pattern; an insulating pattern in contact with a bottom surface of each of the conductive patterns has a length longer than the conductive pattern located on the insulating pattern; 4. A semiconductor device comprising: a first insulating pattern that is in contact with a bottom surface of each of said conductive patterns; and a second insulating pattern that is in contact with a bottom surface of each of said conductive patterns.

13. The semiconductor device of claim 12 , wherein an upper surface of the sidewall insulating pattern and an upper surface of the step portion of the conductive pattern are located on the same plane.

14. A substrate; A plurality of conductive patterns disposed on the substrate so as to be spaced apart from each other in a vertical direction perpendicular to a surface of the substrate; an insulating pattern interposed vertically between the conductive patterns; sidewall insulating patterns provided on sidewalls of the conductive patterns to cover at least the sidewalls of the conductive patterns; an upper pad pattern comprising polysilicon; an interlayer insulating film covering the conductive pattern, the insulating pattern, the sidewall insulating pattern, and the upper pad pattern; contact plugs passing through the interlayer insulating film and contacting the upper pad pattern, the conductive pattern includes polysilicon; the edge of the conductive pattern includes a step portion formed so that an end of one conductive pattern does not vertically overlap with each conductive pattern disposed thereover; the upper pad patterns are provided on upper surfaces of the step portions of the conductive patterns, a bottom surface of each of the contact plugs is located on or within an upper surface of a stacked structure including the upper pad pattern and a lower conductive pattern in contact with the upper pad pattern; the vertical thickness of each of the upper pad patterns is smaller than the vertical thickness of a stack of one conductive pattern and one insulating pattern; an insulating pattern in contact with a bottom surface of each of the conductive patterns has a length longer than the conductive pattern located on the insulating pattern; 4. A semiconductor device comprising: a first insulating pattern that is in contact with a bottom surface of each of said conductive patterns; and a second insulating pattern that is in contact with a bottom surface of each of said conductive patterns.

15. The semiconductor device of claim 14 , wherein an upper surface of the sidewall insulating pattern and an upper surface of the conductive pattern in the stepped portion are located on the same plane.

16. 15. The semiconductor device of claim 14, wherein an end of the upper pad pattern protrudes further laterally than an end of a lower conductive pattern that contacts a bottom surface of the upper pad pattern.

17. 15. The semiconductor device of claim 14, wherein an upper surface of the sidewall insulating pattern is positioned higher than an upper surface of the conductive pattern at a stepped portion in contact with the sidewall insulating pattern.

18. The semiconductor device of claim 14 , wherein the upper pad pattern covers an entire upper surface of the step portion of the conductive pattern that is not covered by the insulating pattern.

19. The semiconductor device of claim 1, wherein the bottom surface of the sidewall insulating pattern is in contact with the insulating pattern.

20. The semiconductor element according to claim 1, wherein the sidewall insulating pattern is formed of silicon nitride, silicon oxide, or a structure in which a silicon oxide film and a silicon nitride film are stacked.

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