Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device that provides both high breakdown voltage and low on-resistance and a manufacturing method for the same.SOLUTION: A semiconductor substrate SB has a convex part CON protruding upwardly from a surface SU. An n-type drift area DF is arranged on the semiconductor substrate SB so as to be located between a gate electrode GE and an n+ drain area DR in a plan view and has an impurity concentration lower than that of the n+ drain area DR. A p-type resurf area RS is arranged on the convex part CON and constitutes a pn junction with the n-type drift area DF.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Conventionally, a configuration in which a superjunction structure is applied to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor is disclosed, for example, in the following Non-Patent Document 1. In the configuration of Non-Patent Document 1, a repeating structure of p-type pillar regions and n-type pillar regions is arranged on the surface of a semiconductor substrate between a source region and a drain region. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] R. Zhu et al., "A High Voltage Super-Junction NLDMOS Device Implemented in 0.13μm SOI Based Smart Power IC Technology", Proceedings of The 22nd International Symposium on Power Semiconductor Devices & ICs, Hiroshima Summary of the Invention [Problem to be solved by the invention]

[0004] In the configuration described in Non-Patent Document 1, the provision of the p-type pillar region reduces the effective channel width that functions as a MOS transistor, making it difficult to reduce the on-resistance.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] In a semiconductor device according to one embodiment, a semiconductor substrate has a protruding portion protruding upward from a surface thereof. A first region of a first conductivity type is disposed in the semiconductor substrate so as to be located between a gate electrode and a drain region in a plan view, and has a lower impurity concentration than the drain region. A second region of a second conductivity type is disposed in the protruding portion and forms a pn junction with the first region.

[0007] In a semiconductor device according to another embodiment, the semiconductor substrate has a first protrusion and a second protrusion protruding upward from the surface. The resurf region of the first transistor is disposed on the first protrusion so as to form a pn junction with the drift region. The second source region and the second drain region of the second transistor are disposed on the second protrusion so as to be at a different height from the first source region and the first drain region of the first transistor.

[0008] According to a method for manufacturing a semiconductor device according to one embodiment, a semiconductor substrate is formed having a protrusion protruding upward from a surface thereof, a first region of a first conductivity type disposed below the protrusion, and a second region of a second conductivity type disposed on the protrusion so as to form a pn junction with the first region. A gate electrode is formed on the surface of the semiconductor substrate. A source region and a drain region of the first conductivity type having a higher concentration of the first conductivity type impurity than the first region are formed in the semiconductor substrate so as to sandwich the first region. Effect of the Invention

[0009] According to the above-described embodiment, it is possible to realize a semiconductor device that achieves both a high breakdown voltage and a low on-resistance, and a method for manufacturing the same. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view showing a configuration of a semiconductor device according to an embodiment in a chip state; [Diagram 2] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment. [Diagram 3] FIG. 3 is an enlarged cross-sectional view showing a part of FIG. 2 in an enlarged manner. [Figure 4] 1 is a plan view illustrating a configuration of a semiconductor device according to an embodiment. [Diagram 5] 1 is a perspective view illustrating a configuration of a semiconductor device according to an embodiment. [Figure 6] FIG. 2 is a plan view showing the planar shape of a gate electrode. [Figure 7] 13A and 13B are plan views showing modified examples of the planar shape of a gate electrode. [Figure 8] 11 is a plan view showing a configuration in which a RESURF region is electrically connected to a gate electrode. FIG. [Figure 9] 2 is a cross-sectional view showing a first step in a first example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] 4 is a cross-sectional view showing a second step in the first example of the method for manufacturing the semiconductor device according to the embodiment. FIG. [Figure 11] 4 is a cross-sectional view showing a third step in the first example of the method for manufacturing the semiconductor device according to the embodiment. FIG. [Figure 12] 4 is a cross-sectional view showing a fourth step in the first example of the method for manufacturing a semiconductor device according to the embodiment. FIG. [Figure 13] 4 is a cross-sectional view showing a fifth step in the first example of the method for manufacturing a semiconductor device according to the embodiment. FIG. [Figure 14] 10 is a cross-sectional view showing a sixth step in the first example of the method for manufacturing a semiconductor device according to the embodiment. FIG. [Figure 15] 5 is a cross-sectional view showing a first step in a second example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] 6 is a cross-sectional view showing a second step in a second example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] 11 is a cross-sectional view showing a first step in a third example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 18] 11 is a cross-sectional view showing a second step in a third example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 19]11 is a cross-sectional view showing a third step in a third example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 20] 11 is a cross-sectional view showing a fourth step in the third example of the method for manufacturing a semiconductor device according to the embodiment. FIG. [Figure 21] 11 is a cross-sectional view showing a fifth step in a third example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 22] 11 is a cross-sectional view showing a sixth step in the third example of the method for manufacturing a semiconductor device according to the embodiment. FIG. [Figure 23] 11 is a cross-sectional view showing a first step in a fourth example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 24] 11 is a cross-sectional view showing a second step in a fourth example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Diagram 25] FIG. 2 is a diagram showing equipotential lines in a semiconductor device according to an embodiment; [Figure 26] FIG. 13 is a diagram showing an impact ionization rate distribution of a semiconductor device according to an embodiment. [Figure 27] FIG. 11 is a cross-sectional view showing a configuration of a comparative example. [Figure 28] 1 is a graph showing the relationship between off-state breakdown voltage BVdss and on-state resistance Rsp. [Figure 29] 1 is a cross-sectional view showing a configuration of an application example of a semiconductor device according to an embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and drawings, the same or corresponding components are denoted by the same reference numerals, and redundant descriptions will not be repeated. In the drawings, the configuration may be omitted or simplified for convenience of explanation. In addition, at least a part of the embodiment and each modified example may be combined with each other in any desired manner.

[0012] Note that the semiconductor device in the embodiment described below is not limited to a semiconductor chip, and may be a semiconductor wafer before being divided into semiconductor chips, or may be a semiconductor package in which the semiconductor chip is encapsulated with resin. Also, the plan view in this specification means a viewpoint seen from a direction orthogonal to the surface of the semiconductor substrate.

[0013] <Configuration of the semiconductor device in chip state> First, the configuration of the semiconductor device in chip state according to an embodiment will be described with reference to FIG. 1.

[0014] As shown in FIG. 1, the semiconductor device CHI of this embodiment is, for example, in a chip state and has a semiconductor substrate. On the surface of the semiconductor substrate, formation regions such as a driver circuit DRI, a pre-driver circuit PDR, an analog circuit ANA, a power supply circuit PC, a logic circuit LC, and an input / output circuit IOC are arranged.

[0015] For each of the driver circuit DRI and the power supply circuit PC, for example, an LDMOS transistor is arranged.

[0016] <Configuration of the LDMOS transistor> Next, the configuration of the LDMOS transistor used in the semiconductor device CHI of FIG. 1 will be described with reference to FIGS. 2 to 8.

[0017] In the following, an LDMOS transistor using a silicon oxide film as the gate insulating layer will be described, but the gate insulating layer is not limited to a silicon oxide film and may be another insulating film. That is, the transistor used in this embodiment is not limited to an LDMOS transistor, and may be an LDMIS (Laterally Diffused Metal Insulator Semiconductor) transistor.

[0018] 2, the semiconductor substrate SB has a surface SU and a protrusion CON. The protrusion CON protrudes upward from the surface SU. The protrusion CON has both side surfaces SS1 and SS2 and an upper surface US in a cross section. Each of the both side surfaces SS1 and SS2 is an inclined surface inclined with respect to the surface SU of the semiconductor substrate SB. The both side surfaces SS1 and SS2 form a tapered shape in which the lateral distance between the both side surfaces SS1 and SS2 decreases from bottom to top in the cross section.

[0019] The crystal plane of each of the two side surfaces SS1 and SS2 is a {111} plane. The crystal plane of each of the two side surfaces SS1 and SS2 is, for example, a (111) plane, but is not limited to this and may be any plane equivalent to the (111) plane.

[0020] Each of the side surfaces SS1 and SS2 is inclined at, for example, 54.7±2° (52.7° or more and 56.7° or less) with respect to the surface SU of the semiconductor substrate SB. If the crystal plane of the surface of the semiconductor substrate SB is, for example, a (100) plane and the crystal planes of the side surfaces SS1 and SS2 are, for example, a (111) plane, theoretically the angle between each of the side surfaces SS1 and SS2 and the surface SU is 54.7°. However, in reality, due to manufacturing errors and the like, the angle between each of the side surfaces SS1 and SS2 and the surface SU may vary within a range of ±2°.

[0021] The upper surface US is connected to the upper ends of both side surfaces SS1 and SS2. The upper surface US is a flat surface and is, for example, approximately parallel to the surface SU of the semiconductor substrate SB. This makes the cross-sectional shape of the protrusion CON a trapezoid.

[0022] The semiconductor substrate SB has p - The substrate region SBR is disposed. - An LDMOS transistor TR is disposed on a semiconductor substrate SB having a substrate region SBR.

[0023] The LDMOS transistor TR includes a p-type body region BD, an n-type drift region DF (first region), and + A source region SR and n +It has a drain region DR, a p-type RESURF region RS (second region), a gate insulating layer GI, and a gate electrode GE.

[0024] The p-type body region BD is disposed in the semiconductor substrate SB. - The p-type body region BD is in contact with the substrate region SBR. The p-type body region BD has a portion located on the surface SU of the semiconductor substrate SB. - It has a higher p-type impurity concentration than the substrate region SBR.

[0025] The n-type drift region DF is disposed in the semiconductor substrate SB. - The n-type drift region DF forms a pn junction with the substrate region SBR. The n-type drift region DF is located between the gate electrode GE and the drain region DR in a plan view. The n-type drift region DF has a first semiconductor region DF1 and a second semiconductor region DF2. The first semiconductor region DF1 is located below the protrusion CON. The second semiconductor region DF2 is disposed on the first semiconductor region DF1 and located within the protrusion CON.

[0026] The second semiconductor region DF2 extends upward from the upper end of the first semiconductor region DF1. The n-type impurity concentration of the first semiconductor region DF1 is equal to the n-type impurity concentration of the second semiconductor region DF2. The n-type impurity concentrations of each of the first semiconductor region DF1 and the second semiconductor region DF2 are, for example, 1×10 17 / cm 3 The boundary between the first semiconductor region DF1 and the second semiconductor region DF2 is, for example, an extension of the surface SU of the semiconductor substrate SB (indicated by the dashed line in the drawing).

[0027] The boundary between the first semiconductor region DF1 and the second semiconductor region DF2 may have a structural discontinuity or an oxide, or the first semiconductor region DF1 and the second semiconductor region DF2 may be integral with each other, making the boundary between the first semiconductor region DF1 and the second semiconductor region DF2 unrecognizable.

[0028] n +The source region SR is disposed in the semiconductor substrate SB and forms a pn junction with the p-type body region BD. + The source region SR is arranged in the surface SU of the semiconductor substrate SB.

[0029] n + The drain region DR is disposed in the semiconductor substrate SB and is in contact with the n-type drift region DF. + The drain region DR is disposed on the surface SU of the semiconductor substrate SB. The n-type drift region DF is + Source regions SR and n + They have a lower n-type impurity concentration than each of the drain regions DR.

[0030] n + Source region SR and n + Between the drain region DR, a p-type body region BD, - The substrate region SBR and the n-type drift region DF (first semiconductor region DF1) are sandwiched between the p-type body region BD and the p - The substrate region SBR and the n-type drift region DF (first semiconductor region DF1) are arranged in this order on the front surface SU of the semiconductor substrate SB. + Source region SR to n + They are aligned toward the drain region DR.

[0031] The p-type RESURF region RS is disposed in the protrusion CON and is located at the upper end of the protrusion CON. The p-type RESURF region RS is disposed on the second semiconductor region DF2 and forms a pn junction with the second semiconductor region DF2 of the n-type drift region DF. The pn junction between the p-type RESURF region RS and the second semiconductor region DF2 is located in the protrusion CON and is located above the front surface SU of the semiconductor substrate SB.

[0032] The p-type impurity concentration of the p-type RESURF region RS is equal to or higher than the n-type impurity concentration of the n-type drift region DF, and is, for example, 1×10 17 / cm 3 The p-type RESURF region RS is electrically connected to either the gate electrode GE or the ground potential.

[0033] The gate electrode GE is disposed on the surface SU of the semiconductor substrate SB. The gate electrode GE is connected to at least the p-type body region BD and the p-type body region BD via the gate insulating layer GI. - The gate electrode GE faces the substrate region SBR. The gate electrode GE is made of, for example, polycrystalline silicon doped with impurities.

[0034] The gate electrode GE rides on the protrusion CON with the gate insulating layer GI therebetween. The gate electrode GE covers the pn junction between the second semiconductor region DF2 and the p-type RESURF region RS on the side surface SS1 of the protrusion CON. This makes it possible to relax the electric field between the second semiconductor region DF2 and the p-type RESURF region RS. The gate electrode GE also extends up to the upper surface US of the protrusion CON. The upper surface of the gate electrode GE located on the upper surface US of the protrusion CON is approximately parallel to the surface SU of the semiconductor substrate SB. This makes it easy to connect a contact to the upper surface of the gate electrode GE located on the upper surface US of the protrusion CON.

[0035] The surface SU of the semiconductor substrate SB has n + The p-type body region BD is in contact with the source region SR. + The contact area CO is disposed. + The contact region CO has a higher p-type impurity concentration than the p-type body region BD.

[0036] An interlayer insulating layer IL is disposed on the surface SU of the semiconductor substrate SB so as to cover the gate electrode GE and the like. Contact holes CH1 and CH2 are provided in the interlayer insulating layer IL. The contact hole CH1 is disposed at a position n + The contact hole CH2 extends from the upper surface of the interlayer insulating layer IL to the drain region DR. A conductive layer CL1 is buried in the contact hole CH1. The contact hole CH2 extends from the upper surface of the interlayer insulating layer IL to the + Source regions SR and p + The contact holes CH2 reach the respective contact regions CO. A conductive layer CL2 is buried in the contact holes CH2.

[0037] On the interlayer insulating layer IL, wiring layers DIN and SIN are arranged. The wiring layers DIN and SIN are made of a metal including, for example, aluminum (Al). The wiring layers DIN and SIN may be made of a metal including, for example, copper (Cu). The wiring layer DIN is connected to n through a conductive layer CL1. + The wiring layer SIN is electrically connected to the drain region DR through the conductive layer CL2. + Source regions SR and p + It is electrically connected to each of the contact regions CO.

[0038] 3, the surface SU of the semiconductor substrate SB is located a distance T1 below the height position of the pn junction between the n-type drift region DF and the p-type RESURF region RS. The distance T1 is, for example, about 0.05 μm. Here, the height position of the pn junction between the n-type drift region DF and the p-type RESURF region RS is the height position at which the n-type impurity concentration of the n-type drift region DF and the p-type impurity concentration of the p-type RESURF region RS are the same.

[0039] A depletion layer extends vertically from the pn junction between the n-type drift region DF and the p-type RESURF region RS. When no voltage is applied to the n-type drift region DF and the p-type RESURF region RS, the depletion layer extends downward to a distance T2 of about 0.03 μm from the pn junction between the n-type drift region DF and the p-type RESURF region RS. Therefore, by setting the distance T1 to, for example, about 0.05 μm, the depletion layer extending downward from the pn junction between the n-type drift region DF and the p-type RESURF region RS does not extend to the first semiconductor region DF1. In other words, the depletion layer does not extend downward below the height position of the front surface SU of the semiconductor substrate SB.

[0040] 4, the semiconductor substrate SB has an active region and an STI (Shallow Trench Isolation) region. Impurity regions constituting the LDMOS transistor TR are arranged in the active region. The STI region is arranged to surround the active region in a plan view.

[0041] 5, in the STI region, an STI structure, which is an element isolation structure, is disposed on the surface SU of the semiconductor substrate SB. The STI structure has a trench TRE and an insulating layer BI. The trench TRE extends to a predetermined depth from the surface SU of the semiconductor substrate SB. The insulating layer BI fills the trench TRE.

[0042] As shown in FIG. 4, the protrusion CON has n + Drain region DR and n + The p-type RESURF regions RS arranged in the protruding portions CON are also arranged so as to surround the source regions SR and the p-type RESURF regions RS in a plan view. + Drain region DR and n + The source regions SR are disposed so as to surround the respective peripheries of the source regions SR.

[0043] Each of the protrusion CON and the p-type RESURF region RS has, for example, a ladder shape having a plurality of slits in plan view. + A drain region DR is disposed in the second slit adjacent to the first slit in plan view. + The source region SR is arranged in the slits. + Drain region DR and n + The source regions SR are arranged alternately.

[0044] In plan view, n + The drain region DR is disposed with a distance W between it and the p-type RESURF region RS. The distance W is a distance when projected in a plan view. The distance W is, for example, about 0.2 μm or more.

[0045] The gate electrode GE is electrically connected to the wiring layer GIN through a conductive layer VCL. The conductive layer VCL fills a via hole VH provided in the interlayer insulating layer IL (FIG. 2). The wiring layer GIN is a conductive layer formed separately from the same layer as the wiring layers DIN and SIN, and is made of a metal such as aluminum.

[0046] The p-type RESURF region RS arranged in the protruding portion CON is electrically connected to the wiring layer SIN through the contact conductive layer CL3. The contact conductive layer CL3 is embedded in a contact hole CH3 provided in the interlayer insulating layer IL (FIG. 2). The wiring layer SIN is electrically connected to the n-type RESURF region RS through the conductive layer CL2 as described above. + The p-type RESURF region RS is electrically connected to the source region SR. As a result, the p-type RESURF region RS is electrically connected to the n-type + It is electrically connected to the source region SR and is at the ground potential.

[0047] The contact conductive layer CL3 has a thickness of n + n for the source region SR + They are arranged in a second direction D2 perpendicular to a first direction D1 toward the drain region DR.

[0048] 5, the contact conductive layer CL3 is connected to the upper surface US of the protrusion CON, avoiding both side surfaces SS1 and SS2 of the protrusion CON. The conductive layer VCL is connected to the flat upper surface of the gate electrode GE, avoiding the portions of the gate electrode GE located directly above both side surfaces SS1 and SS2 of the protrusion CON. The conductive layer VCL is located on the outer periphery side of the protrusion CON in a plan view.

[0049] 6, the gate electrode GE has a ring shape in a plan view. The ring-shaped gate electrode GE has n + It completely surrounds the source region SR. + The gate electrode GE and other n + The source region SR and the gate electrode GE surrounding it are separated from each other.

[0050] 7, the gate electrode GE may have a ladder shape in a plan view. In this case, the gate electrode GE has n + A portion surrounding the entire periphery of the source region SR, and n+ A portion surrounding the entire periphery of the drain region DR is connected to each other to form a ladder shape. Therefore, in the plurality of ladder-shaped slits, n + the drain region DR and n + the source regions SR are alternately arranged.

[0051] In the above description, the case where the p-type resurf region RS is at the ground potential has been described. However, the p-type resurf region RS may be at the same potential as the gate electrode GE. In this case, as shown in FIG. 8, the contact conductive layer CL3 connected to the flat upper surface of the convex portion CON is connected to the wiring layer GIN. Thereby, the p-type resurf region RS is electrically connected to the gate electrode GE through the contact conductive layer CL3, the wiring layer GIN, and the conductive layer VCL.

[0052] In the above description, the configuration in which the lower end of the n-type drift region DF is in contact with the p - substrate region SBR has been described with reference to FIG. 2. However, a p-type resurf region in contact with the lower end of the n-type drift region DF may be added. The additional p-type resurf region is located between the p - substrate region SBR and the n-type drift region DF, and forms a pn junction with the n-type drift region DF by contacting the lower end of the n-type drift region DF. By adding a p-type resurf region in contact with the lower end of the n-type drift region DF, the resurf effect is more significantly exhibited.

[0053] <Manufacturing Method of LDMOS Transistor> Next, four manufacturing methods of the LDMOS transistor in the present embodiment will be described with reference to FIGS. 9 to 24.

[0054] (First Example of Manufacturing Method) As shown in FIG. 9, an n-type region DFA is formed in the p - substrate region SBR of the semiconductor substrate SB. Thereafter, an STI structure (not shown) is formed on the surface of the semiconductor substrate SB.

[0055] 10, a p-type epitaxial layer RS ​​is formed on the surface of a semiconductor substrate SB by epitaxial growth. In this epitaxial growth, a single-crystal p-type epitaxial layer RS ​​grows on the surface of the single-crystal silicon of the semiconductor substrate SB, and a polycrystalline p-type epitaxial layer RS ​​grows on the STI structure.

[0056] 11, a mask layer MK1 made of, for example, a silicon oxide film is formed on the p-type epitaxial layer RS. The mask layer MK1 is formed so as to be located at least in a region directly above the n-type region DFA. Using the mask layer MK1 as a mask, anisotropic wet etching is performed using, for example, a TMAH (tetramethylammonium hydroxide) aqueous solution. This etching selectively removes the surface of the semiconductor substrate SB to a position deeper than the pn junction between the p-type epitaxial layer RS ​​and the n-type region DFA.

[0057] This anisotropic wet etching is highly dependent on the crystal orientation. <100> The etching rate in the direction is fast, <111> The etching rate in the direction of the (111) plane is the slowest. Therefore, by performing anisotropic wet etching using a (100) silicon substrate, a protrusion CON having both side surfaces SS1 and SS2 of the (111) plane is formed. This forms a trapezoidal protrusion CON having both side surfaces SS1 and SS2 inclined with respect to the surface SU of the semiconductor substrate SB and an upper surface US connecting the upper ends of both side surfaces SS1 and SS2.

[0058] By the above etching, a p-type RESURF region RS made of a p-type epitaxial layer RS ​​is formed on the upper part of the protrusion CON. An n-type drift region DF made of an n-type region is formed on the lower part of the protrusion CON. The n-type drift region DF can be divided into a first semiconductor region DF1 located below the surface SU of the semiconductor substrate SB and a second semiconductor region DF2 located above the surface SU of the semiconductor substrate SB. After this, the mask layer MK1 is removed.

[0059] 12, a p-type body region BD is formed as a p-type well region in the semiconductor substrate SB. After that, a surface SU of the semiconductor substrate SB is oxidized. As a result, a gate insulating layer GI made of a silicon oxide film is formed so as to cover the surface SU of the semiconductor substrate SB and the surfaces of the protrusions CON.

[0060] 13, a polycrystalline silicon layer GE having an impurity introduced therein is formed on a gate insulating layer GI. The polycrystalline silicon layer GE is patterned by photolithography and etching techniques to form a gate electrode GE.

[0061] As shown in FIG. 14, an n-type impurity is ion-implanted into the surface SU of the semiconductor substrate SB to form an n + Source region SR and n + A drain region DR is formed on the surface SU of the semiconductor substrate SB. In addition, a p-type impurity is ion-implanted into the surface SU of the semiconductor substrate SB to form a p + A contact region CO is formed on the surface SU of the semiconductor substrate SB.

[0062] As shown in Fig. 2, an interlayer insulating layer IL is then formed to cover the surface of the semiconductor substrate SB. Contact holes CH1 and CH2 are formed in the interlayer insulating layer IL. Conductive layers CL1 and CL2 are then formed to fill the contact holes CH1 and CH2, respectively. Then, wiring layers DIN and SIN are formed on the interlayer insulating layer IL. This forms the LDMOS transistor TR of this embodiment.

[0063] (Second example of manufacturing method) The second example of the manufacturing method undergoes the same steps as the first example of the manufacturing method shown in Fig. 9. Thereafter, in the second example of the manufacturing method, a mask layer MK2 is formed on the surface of the semiconductor substrate SB as shown in Fig. 15. The mask layer MK2 has an opening OP, and a part of the surface of the semiconductor substrate SB is exposed from the opening OP.

[0064] 16, epitaxial growth is selectively performed on the surface of the semiconductor substrate SB exposed from the opening OP of the mask layer MK2. As a result, a protrusion CON is formed in the opening OP of the mask layer MK2. By adjusting the conditions of this epitaxial growth, a trapezoidal protrusion CON having both side surfaces SS1 and SS2 of the (111) plane is formed.

[0065] An n-type second semiconductor region DF2 is formed in the lower part of this protruding portion CON. As a result, an n-type drift region DF consisting of the first semiconductor region DF1 and the second semiconductor region DF2 is formed. Furthermore, a p-type RESURF region RS is formed in the upper part of the protruding portion CON. The p-type RESURF region RS is formed so as to form a p-n junction with the second semiconductor region DF2. The p-n junction between the p-type RESURF region RS and the second semiconductor region DF2 is located in the protruding portion CON. After this, the mask layer MK2 is removed.

[0066] Thereafter, the second example of the manufacturing method undergoes steps similar to those of the first example of the manufacturing method shown in Figures 12 to 14 and 2. In this way, the LDMOS transistor TR of this embodiment shown in Figure 2 is formed.

[0067] (Third example of manufacturing method) As shown in FIG. 17, in the third example of the manufacturing method, an n-type epitaxial layer NE and a p-type epitaxial layer PE are formed in sequence at the same time by epitaxial growth on the surface of a semiconductor substrate SB.

[0068] 18, a mask layer MK3 made of, for example, a silicon oxide film is formed on the p-type epitaxial layer PE. Using the mask layer MK3 as a mask, anisotropic wet etching is performed using, for example, a TMAH aqueous solution. By this etching, the surface of the semiconductor substrate SB is selectively removed to a position deeper than the pn junction between the p-type epitaxial layer PE and the n-type epitaxial layer NE.

[0069] This anisotropic wet etching is highly dependent on the crystal orientation. <100> The etching rate in the direction is fast, <111> The etching rate in the direction of the (111) plane is the slowest. Therefore, by performing anisotropic wet etching using a (100) silicon substrate, a protrusion CON having both side surfaces SS1 and SS2 of the (111) plane is formed. This forms a trapezoidal protrusion CON having both side surfaces SS1 and SS2 inclined with respect to the surface SU of the semiconductor substrate SB and an upper surface US connecting the upper ends of both side surfaces SS1 and SS2.

[0070] By the above etching, a p-type RESURF region RS made of the p-type epitaxial layer RS ​​is formed on the upper part of the protruding portion CON. An n-type second semiconductor region DF2 made of a part of the n-type epitaxial layer NE is formed on the lower part of the protruding portion CON. An n-type first semiconductor region DF1 made of a part of the n-type epitaxial layer NE is formed below the protruding portion CON. An n-type drift region DF is formed from the first semiconductor region DF1 and the second semiconductor region DF2. The pn junction between the p-type RESURF region RS and the second semiconductor region DF2 is located in the protruding portion CON. After this, the mask layer MK1 is removed.

[0071] As shown in FIG. 19, a p-type body region BD is formed in a semiconductor substrate SB. The p-type body region BD is - It is formed to have a p-type impurity concentration higher than the p-type impurity concentration in the substrate region SBR.

[0072] 20, the surface SU of the semiconductor substrate SB is oxidized. As a result, a gate insulating layer GI made of a silicon oxide film is formed so as to cover the surface SU of the semiconductor substrate SB and the surfaces of the protrusions CON.

[0073] Thereafter, a polycrystalline silicon layer GE having an impurity doped therein is formed on the gate insulating layer GI. The polycrystalline silicon layer GE is patterned by photolithography and etching techniques to form a gate electrode GE.

[0074] As shown in FIG. 21, an n-type impurity is ion-implanted into the surface SU of a semiconductor substrate SB to form an n + Source region SR and n + A drain region DR is formed on the surface SU of the semiconductor substrate SB. In addition, a p-type impurity is ion-implanted into the surface SU of the semiconductor substrate SB to form a p + A contact region CO is formed on the surface SU of the semiconductor substrate SB.

[0075] As shown in Fig. 22, an interlayer insulating layer IL is formed to cover the surface of a semiconductor substrate SB. Contact holes CH1 and CH2 are formed in the interlayer insulating layer IL. Conductive layers CL1 and CL2 are formed to fill the contact holes CH1 and CH2, respectively. Thereafter, wiring layers DIN and SIN are formed on the interlayer insulating layer IL. This forms the LDMOS transistor TR of this embodiment.

[0076] (Fourth Example of Manufacturing Method) 23, in the fourth example of the manufacturing method, for example, phosphorus (P) and boron (B) are each implanted into the surface SU of the semiconductor substrate SB by an ion implantation method. At this time, phosphorus is implanted into a position deeper from the surface SU of the semiconductor substrate SB than boron.

[0077] As shown in Fig. 24, after the ion implantation, annealing is performed to activate the implanted ions. This annealing diffuses and activates phosphorus and boron in the semiconductor substrate SB. As a result, a diffusion region NR of n-type impurities (e.g., phosphorus) and a diffusion region PR of p-type impurities (e.g., boron) are formed in the semiconductor substrate SB. The diffusion region NR is a p - The p-type ... - The diffusion region PR is formed on the substrate region SBR. The diffusion region PR is formed on the diffusion region NR in the surface SU of the semiconductor substrate SB so as to form a pn junction with the diffusion region NR.

[0078] Thereafter, the fourth example of the manufacturing method undergoes steps similar to those of the third example of the manufacturing method shown in FIGS. 18 to 22, thereby forming the LDMOS transistor TR of this embodiment shown in FIG.

[0079] <Effects> Next, the effects of this embodiment will be described.

[0080] The inventors of the present invention investigated the potential distribution when the breakdown voltage BVdss between the drain and source in the configuration shown in Fig. 2 was set to about 47 V by device simulation, and obtained the results shown in Fig. 25.

[0081] 25, it was found that in this embodiment, the depletion layer spreads over almost the entire area of ​​the p-type RESURF region RS and the n-type drift region DF. It was also found that the intervals between the equipotential lines in the depletion layer are almost the same, and the potential distribution in the depletion layer is almost uniform. As a result, it was found that in this embodiment, a high breakdown voltage can be efficiently achieved.

[0082] The present inventors also investigated the impact ionization rate distribution by device simulation in the configuration shown in Fig. 2. As a result, the results shown in Fig. 26 were obtained.

[0083] 26, it was found that in this embodiment, the impact ionization rate distribution is high not on the surface of the semiconductor substrate SB but near the pn junction between the p-type RESURF region RS and the n-type drift region DF. This has been found to be advantageous in terms of ensuring reliability in this embodiment.

[0084] The inventors also investigated the relationship between the breakdown voltage BVdss and the on-resistance Rsp for each of the configuration of this embodiment shown in Fig. 2 and the configuration of the comparative example shown in Fig. 27. As a result, the results shown in Fig. 28 were obtained.

[0085] 27, the semiconductor substrate SB has no protruding portion CON and no p-type RESURF region RS on the front surface SU. + The STI structure is disposed adjacent to the drain region DR. The STI structure has a trench TRE provided in the surface SU of the semiconductor substrate SB and an insulating layer BI filling the trench TRE. The gate electrode GE extends onto the STI structure via the gate insulating layer GI.

[0086] Other than the above, the configuration of the comparative example shown in FIG. 27 is substantially the same as the configuration of this embodiment shown in FIG. 2, so the same elements are given the same reference numerals and their description will not be repeated.

[0087] In Fig. 28, the data indicated by the open circles is the data of the comparative example shown in Fig. 27. Moreover, the data indicated by the filled diamonds is the data of this embodiment shown in Fig. 2.

[0088] From the results in Fig. 28, it can be seen that in the breakdown voltage BVdss range of 20V to 70V, the on-resistance Rsp is reduced in the configuration of this embodiment shown in Fig. 2 compared to the configuration of the comparative example shown in Fig. 27 when the breakdown voltage BVdss is the same. This shows that the trade-off between the breakdown voltage BVdss and the on-resistance Rsp is improved in this embodiment. It was also found that the effect of improving the trade-off between the breakdown voltage BVdss and the on-resistance Rsp in this embodiment is particularly noticeable in the breakdown voltage BVdss range of 20V to 60V.

[0089] As described above, according to the present embodiment shown in FIG. 2, it is possible to achieve both a high breakdown voltage and a low on-resistance. This is based on the fact that in this embodiment, as shown in FIG. 2, the p-type resurf region RS is arranged in the convex portion CON on the surface of the semiconductor substrate SB. In other words, since the p-type resurf region RS is arranged in the convex portion CON, the channel width of the LDMOS transistor TR is not lost due to the p-type resurf region RS, and the current path between the source and the drain is not obstructed. This realizes a low on-resistance in the LDMOS transistor TR. Furthermore, since the p-type resurf region RS is provided, the potential distribution in the depletion layer becomes almost uniform as shown in FIG. 25, and a high breakdown voltage is realized.

[0090] In addition, since the potential distribution in the depletion layer becomes almost uniform as shown in Fig. 25, a high breakdown voltage can be obtained even if the n-type impurity concentration in the drift region DF is increased. This allows the n-type impurity concentration in the drift region DF to be increased, thereby reducing the on-resistance.

[0091] According to this embodiment, as shown in FIG. 3, the drift region DF has the second semiconductor region DF2 arranged on the protruding portion CON. As a result, the surface SU of the semiconductor substrate SB is located a distance T1 below the height position of the pn junction between the n-type drift region DF and the p-type RESURF region RS. Therefore, when no voltage is applied to each of the n-type drift region DF and the p-type RESURF region RS, the depletion layer generated at the pn junction between the n-type drift region DF and the p-type RESURF region RS is prevented from extending below the height position of the surface SU of the semiconductor substrate SB. This prevents the depletion layer extending below the height position of the surface SU of the semiconductor substrate SB from becoming a barrier and making it difficult for the on-current to flow. This makes it possible to further improve the on-current (reduce the on-resistance).

[0092] 2, the first semiconductor region DF1 and the second semiconductor region DF2 constituting the n-type drift region DF have the same n-type impurity concentration. As a result, the second semiconductor region DF2 having the same impurity concentration as the first semiconductor region DF1 is located in the protruding portion CON. As a result, the depletion layer generated in the pn junction between the n-type drift region DF and the p-type RESURF region RS is prevented from extending below the height position of the surface SU of the semiconductor substrate SB, thereby improving the on-current (reducing the on-resistance).

[0093] According to this embodiment, the p-type RESURF region RS is electrically connected to either the gate electrode GE or the ground potential, as shown in Fig. 4 or 8. This makes it possible to obtain the RESURF effect by the p-type RESURF region RS.

[0094] 2, according to this embodiment, the p-type impurity concentration in the p-type RESURF region RS is equal to or higher than the n-type impurity concentration in the drift region DF, which makes it easy to ensure charge balance in the depletion layer.

[0095] According to this embodiment, the side surface of the protrusion CON is an inclined surface of the {111} plane, as shown in Fig. 2. This reduces the angle at which the gate electrode GE rides onto the protrusion CON, mitigating the electric field in this portion and achieving a high breakdown voltage.

[0096] According to this embodiment, the gate electrode GE rides up on the protruding portion CON as shown in Fig. 2. This reduces the electric field as described above, and enables a high breakdown voltage to be achieved.

[0097] According to this embodiment, as shown in FIG. + Drain region DR and n + The p-type resurf region RS is disposed so as to surround the source region SR individually, thereby making it possible to effectively obtain the resurf effect by the p-type resurf region RS.

[0098] The contact conductive layer CL3 connected to the p-type RESURF region RS is n + If the contact conductive layer CL3 is disposed in the vicinity of the drain region DR, the breakdown voltage BVdss may decrease. However, according to the present embodiment, as shown in FIG. + n for the source region SR + The contact conductive layer CL3 is disposed in a second direction D2 perpendicular to the first direction D1 toward the drain region DR. + Since it is disposed away from the drain region DR, a decrease in the breakdown voltage BVdss can be suppressed.

[0099] 5, according to this embodiment, the contact conductive layer CL3 connected to the p-type RESURF region RS is connected to the flat surface which is the upper surface US of the protrusion CON. This makes it easier to connect the contact conductive layer CL3 and the p-type RESURF region RS compared to the case where the contact conductive layer CL3 is connected to the inclined surfaces SS1 and SS2 of the protrusion CON.

[0100] According to this embodiment, as shown in FIG. + The drain region DR is disposed with a distance W between it and the p-type RESURF region RS, which makes it possible to suppress a decrease in breakdown voltage due to reach-through.

[0101] Moreover, according to this embodiment, the gate electrode GE has either a ring shape as shown in Fig. 6 or a ladder shape as shown in Fig. 7 in plan view. In this manner, the planar shape of the gate electrode GE can be appropriately selected.

[0102] <Modification> Next, an application example of the semiconductor device according to this embodiment will be described with reference to FIG.

[0103] 29, the LDMOS transistor TR of this embodiment is arranged on a semiconductor substrate SB together with, for example, a MOS transistor and a bipolar transistor. In the formation regions of the MOS transistor and the bipolar transistor, protrusions CONA and CONB are provided on the surface SU of the semiconductor substrate SB. P-type regions PE1 and PE2 are arranged in the protrusions CONA and CONB, respectively.

[0104] In the MOS transistor formation region, n + Source region SR1 and n + The drain region DR1 is arranged in the MOS transistor. + Source regions SR1 and n + The drain region DR1 is the n-type + Source regions SR and n + The drain region DR is disposed at a different height position, and the channel of the MOS transistor is formed at a different height position from the channel of the LDMOS transistor TR.

[0105] In the MOS transistor forming region, the gate electrode GE1 is disposed on the upper surface of the protruding portion CONA with a gate insulating layer GI1 interposed therebetween. + Source regions SR1 and n + It is disposed on a region sandwiched between the drain regions DR1.

[0106] In the bipolar transistor forming region, an n-type region WL1 is arranged in the semiconductor substrate SB. - The n-type region WL1 forms a pn junction with the substrate region SBR. The n-type region WL1 forms a pn junction with the p-type region PE2 in the protrusion CON.

[0107] In the bipolar transistor formation region, n + The collector region CR is disposed on the surface SU of the semiconductor substrate SB so as to be adjacent to the n-type region. +The collector region CR is the n + Source regions SR and n + It is disposed at the same height as the drain region DR.

[0108] On the other hand, n + Emitter region ER and p + Each of the base regions BR and PE2 is disposed on the upper surface of the protrusion portion CONB so as to form a pn junction with the p-type region PE2. + Emitter region ER and p + The base region BR is an n-type + Source regions SR and n + The drain region DR is disposed at a different height.

[0109] In this manner, the LDMOS transistor TR of this embodiment may be arranged together with a MOD transistor and a bipolar transistor, or may be arranged together with other elements.

[0110] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0111] ANA Analog circuit, BD p-type body region, BI Insulating layer, BR p + Base region, CH1, CH2 contact holes, CHI semiconductor device, CL1, CL2, VCL conductive layers, CL3 contact conductive layer, CO p + Contact area, CON, CONA, CONB, convex part, CR n + Collector region, DF n-type drift region, DF1 First semiconductor region, DF2 Second semiconductor region, DFA,WL1 n-type region, DIN,GIN,SIN Wiring layer, DR,DR1 n + Drain region, DRI driver circuit, ER n +Emitter region, GE, GE1 gate electrode, GI, GI1 gate insulating layer, IL interlayer insulating layer, IOC input / output circuit, LC logic circuit, MK1, MK2, MK3 mask layer, NE n-type epitaxial layer, NR, PR diffusion region, PC power supply circuit, PDR predriver circuit, PE p-type epitaxial layer, PE1, PE2 p-type region, RS p-type resurf region, SB semiconductor substrate, SBR p - Substrate area, SR,SR1 n + Source region, SS1,SS2 side view, SU surface, TR LDMOS transistor, TRE trench, US top view.

Claims

1. a semiconductor substrate having a surface and a protrusion protruding upward from the surface; a gate electrode disposed on the surface of the semiconductor substrate; a source region and a drain region of a first conductivity type disposed in the semiconductor substrate; a first region of a first conductivity type that is disposed on the semiconductor substrate so as to be located between the gate electrode and the drain region in a plan view and has an impurity concentration lower than that of the drain region; a second region of a second conductivity type that is disposed on the protruding portion and that forms a pn junction with the first region, The second region is electrically connected to either the gate electrode or a ground potential.

2. The first region is A first semiconductor region disposed below the protruding portion; a second semiconductor region disposed on the protruding portion so as to form a pn junction with the second region; The semiconductor device according to claim 1 ,

3. 3. The semiconductor device according to claim 2, wherein a concentration of the first conductive type impurity in said second semiconductor region is equal to a concentration of the first conductive type impurity in said first semiconductor region.

4. 2. The semiconductor device according to claim 1, wherein a concentration of the second conductivity type impurity in said second region is equal to or higher than a concentration of the first conductivity type impurity in said first region.

5. 2. The semiconductor device according to claim 1, wherein the side surface of said protrusion is formed of an inclined surface of a {111} plane.

6. The semiconductor device according to claim 1 , wherein said gate electrode extends over said protruding portion.

7. 2. The semiconductor device according to claim 1, wherein said protrusions are arranged so as to surround each of said drain region and said source region individually in a plan view.

8. a contact conductive layer connected to the second region; 8. The semiconductor device according to claim 7, wherein the contact conductive layer is arranged in a second direction perpendicular to a first direction toward the drain region with respect to the source region in a plan view.

9. the protrusion has two side surfaces which are inclined surfaces in cross section, and a flat upper surface which is connected to upper ends of the two side surfaces, The semiconductor device according to claim 8 , wherein the contact conductive layer is connected to the upper surface of the protrusion.

10. The semiconductor device according to claim 1 , wherein said drain region is arranged with a gap between said drain region and said second region in a plan view.

11. The semiconductor device according to claim 1 , wherein said gate electrode has either a ring shape or a ladder shape in a plan view.

12. a second transistor different from the first transistor having the source region, the drain region and the gate electrode; 2. The semiconductor device according to claim 1, wherein the source region and the drain region of said second transistor are disposed at a different height position from the source region and the drain region of said first transistor.

13. A semiconductor substrate having a surface and a protrusion protruding upward from the surface; a gate electrode disposed on the surface of the semiconductor substrate; a source region and a drain region of a first conductivity type disposed in the semiconductor substrate; a first region of a first conductivity type that is disposed on the semiconductor substrate so as to be located between the gate electrode and the drain region in a plan view and has an impurity concentration lower than that of the drain region; a second region of a second conductivity type that is disposed on the protruding portion and that forms a pn junction with the first region, The side surface of the protrusion is formed of an inclined surface of a {111} plane.

14. a semiconductor substrate having a surface and a first protrusion and a second protrusion protruding upward from the surface; a first transistor having a first source region, a first drain region and a drift region of a first conductivity type, and a resurf region of a second conductivity type; a second transistor having a second source region and a second drain region; the RESURF region is disposed in the first protrusion so as to form a pn junction with the drift region, the second source region and the second drain region are disposed on the second protruding portion so as to be at a different height position from the first source region and the first drain region.

15. forming a semiconductor substrate having a surface, a convex portion protruding upward from the surface, a first region of a first conductivity type disposed below the convex portion, and a second region of a second conductivity type disposed on the convex portion so as to form a pn junction with the first region; forming a gate electrode on the surface of the semiconductor substrate; forming a source region and a drain region of a first conductivity type in the semiconductor substrate, the source region and the drain region having a higher concentration of an impurity of the first conductivity type than the first region, so as to sandwich the first region; The second region is electrically connected to either the gate electrode or a ground potential.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the convex portion is formed by selectively etching away a surface of the semiconductor substrate.

17. 16. The method for manufacturing a semiconductor device according to claim 15, wherein the convex portion is formed by selectively epitaxially growing a surface of the semiconductor substrate.

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