Semiconductor Device

Abstract

To provide a semiconductor device that can easily achieve improvement of breakdown voltage and miniaturization and a manufacturing method for the same.SOLUTION: A semiconductor substrate SB has a surface SU and a convex part CON protruding upwardly from the surface SU. An n-type drift area DF has a part DF2 located inside the convex part CON. An n-drain area DR has an n-type impurity concentration higher than that of the n-type drift area DF. The n-type drift area DF is sandwiched between the n-drain area DR and a gate electrode GE. The n-drain area DR is arranged inside the convex part CON on the n-type drift area DF.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. Place Regarding. [Background technology]

[0002] Conventionally, a planar type LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor having a relatively low breakdown voltage has been disclosed in, for example, the following Non-Patent Document 1. In the configuration of Non-Patent Document 1, + Source region and n + Between the drain region and the p-type well region, - The drift region is sandwiched between the n-type and n-type MOS transistors. - It has a simple structure that is not formed in the drift region. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Lin Wei et al., "A Novel Contact Field Plate Application in Drain-Extended-MOSFET Transistors", Proceedings of The 29th International Symposium on Power Semiconductor Devices & ICs, Sapporo Summary of the Invention [Problem to be solved by the invention]

[0004] With the above LDMOS transistors, it is difficult to miniaturize them while maintaining the same breakdown voltage, and it is also difficult to increase the breakdown voltage while maintaining the same size.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to a semiconductor device according to one embodiment, a semiconductor substrate has a surface and a protruding portion protruding upward from the surface. A first region of a first conductivity type has a portion located inside the protruding portion. A drain region of the first conductivity type has an impurity concentration higher than that of the first region, sandwiches the first region between the drain region and the gate electrode in a plan view, and is located inside the protruding portion and on the first region.

[0007] In a semiconductor device according to another embodiment, the semiconductor substrate has a surface and a first protrusion and a second protrusion protruding upward from the surface. The first transistor has a first source region disposed on the surface and a first drain region disposed in the first protrusion. The second transistor has a second source region and a second drain region disposed in the second protrusion.

[0008] According to a method for manufacturing a semiconductor device according to one embodiment, a semiconductor substrate is formed having a surface, a convex portion protruding upward from the surface, and a first region of a first conductivity type disposed within the convex portion. A gate electrode is formed on the surface of the semiconductor substrate. A drain region of the first conductivity type is formed, the drain region having a higher impurity concentration than the first region, sandwiching the first region between the gate electrode in a plan view, and disposed within the convex portion and on the first region. Effect of the Invention

[0009] According to the above embodiment, a semiconductor device that can easily improve the breakdown voltage and be miniaturized can be provided. Place It becomes possible to realize this. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment in a chip state. [Diagram 2] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 3] 4 is a cross-sectional view showing a configuration of a modified example of the semiconductor device according to the first embodiment. FIG. [Figure 4] 2 is a cross-sectional view showing a first step of the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5] 5 is a cross-sectional view showing a second step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 5 is a cross-sectional view showing a third step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 7] FIG. 11 is a cross-sectional view showing a configuration of a comparative example. [Figure 8] 1 is a graph showing the relationship between breakdown voltage BVDS and on-resistance Rsp. [Figure 9] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment. [Figure 10] 10 is a cross-sectional view showing a first step of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 11] 10 is a cross-sectional view showing a second step of the method for manufacturing a semiconductor device according to the second embodiment. [Figure 12] 10 is a cross-sectional view showing a third step of the method for manufacturing the semiconductor device according to the second embodiment. FIG. [Figure 13] 10 is a cross-sectional view showing a fourth step of the method for manufacturing a semiconductor device according to the second embodiment. FIG. [Figure 14] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment. [Figure 15] 11 is a cross-sectional view showing a first step of a method for manufacturing a semiconductor device according to embodiment 3. FIG. [Figure 16] 11 is a cross-sectional view showing a second step of the method for manufacturing a semiconductor device according to the third embodiment. [Figure 17] 11 is a cross-sectional view showing a third step of the method for manufacturing a semiconductor device according to the third embodiment. FIG. [Figure 18] 1 is a cross-sectional view showing a configuration of an application example of the semiconductor device according to the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and drawings, the same components or corresponding components are denoted by the same reference numerals, and duplicate explanations will not be repeated. In the drawings, for convenience of explanation, the configuration may be omitted or simplified. Also, at least a part of each embodiment and each modification may be arbitrarily combined with each other.

[0012] Note that the semiconductor device in the embodiments described below is not limited to a semiconductor chip, and may be a semiconductor wafer before being divided into semiconductor chips, or a semiconductor package in which the semiconductor chip is encapsulated with resin. Also, the plan view in this specification means a viewpoint seen from a direction orthogonal to the surface of the semiconductor substrate.

[0013] (Embodiment 1) <Configuration of the semiconductor device in chip state> First, the configuration in chip state of the semiconductor device according to Embodiment 1 will be described with reference to FIG. 1.

[0014] As shown in FIG. 1, the semiconductor device CHI of the present embodiment is, for example, in a chip state and has a semiconductor substrate. On the surface of the semiconductor substrate, formation regions such as a driver circuit DRI, a pre-driver circuit PDR, an analog circuit ANA, a power supply circuit PC, a logic circuit LC, and an input / output circuit IOC are arranged.

[0015] For example, LDMOS transistors are arranged in each of the driver circuit DRI and the power supply circuit PC.

[0016] <Configuration of the LDMOS transistor> Next, the configuration of the LDMOS transistor used in the semiconductor device CHI of FIG. 1 will be described with reference to FIG. 2.

[0017] In the following, an LDMOS transistor using a silicon oxide film as a gate insulating layer will be described, but the gate insulating layer is not limited to a silicon oxide film and may be another insulating film. In other words, the transistor used in this embodiment is not limited to an LDMOS transistor, and may be an LDMIS (Laterally Diffused Metal Insulator Semiconductor) transistor.

[0018] As shown in Fig. 2, the semiconductor substrate SB has a surface SU, a protrusion CON, and a protrusion CN. Each of the protrusion CON and the protrusion CN protrudes upward from the surface SU. The protrusion CON has both side surfaces SS1 and SS2 and an upper surface US in a cross section. Each of the both side surfaces SS1 and SS2 is an inclined surface inclined with respect to the surface SU of the semiconductor substrate SB. The both side surfaces SS1 and SS2 form a tapered shape in which the lateral distance between the both side surfaces SS1 and SS2 decreases from bottom to top in the cross section.

[0019] The crystal plane of each of the two side surfaces SS1 and SS2 is a {111} plane. The crystal plane of each of the two side surfaces SS1 and SS2 is, for example, a (111) plane, but is not limited to this and may be any plane equivalent to the (111) plane. The crystal plane of the surface SU of the semiconductor substrate SB is, for example, a (100) plane, but is not limited to this and may be any plane equivalent to the (100) plane.

[0020] Each of the side surfaces SS1 and SS2 is inclined at, for example, 54.7±2° (52.7° or more and 56.7° or less) with respect to the surface SU of the semiconductor substrate SB. If the crystal plane of the surface of the semiconductor substrate SB is, for example, a (100) plane and the crystal planes of the side surfaces SS1 and SS2 are, for example, a (111) plane, theoretically the angle between each of the side surfaces SS1 and SS2 and the surface SU is 54.7°. However, in reality, due to manufacturing errors and the like, the angle between each of the side surfaces SS1 and SS2 and the surface SU may vary within a range of ±2°.

[0021] The upper surface US is connected to the upper ends of both side surfaces SS1 and SS2. The upper surface US is a flat surface and is, for example, approximately parallel to the surface SU of the semiconductor substrate SB. This makes the cross-sectional shape of the protrusion CON a trapezoid.

[0022] The protrusion CN has the same cross-sectional shape as the protrusion CON. Therefore, the side surface SS3 of the protrusion CN is an inclined surface inclined with respect to the surface SU of the semiconductor substrate SB. The crystal plane of the side surface SS3 of the protrusion CN is a {111} plane.

[0023] An STI (Shallow Trench Isolation) structure, which is an element isolation structure, is arranged in the semiconductor substrate SB so as to surround the active region in a plan view. The STI structure has a trench TRE and an insulating layer BI. The trench TRE extends to a predetermined depth from the surface of the semiconductor substrate SB. The insulating layer BI fills the trench TRE. Impurity regions constituting the LDMOS transistor TR are arranged in the active region surrounded by the STI structure.

[0024] The LDMOS transistor TR includes a p-type body region BD, an n-type drift region DF (first region), and + A source region SR and n + It has a drain region DR, a gate insulating layer GI, and a gate electrode GE.

[0025] The semiconductor substrate SB has p - The substrate region SBR (second region) is disposed in the semiconductor substrate SB. The p-type body region BD is disposed in the semiconductor substrate SB. - The p-type body region BD is in contact with the substrate region SBR. The p-type body region BD has a portion located on the surface SU of the semiconductor substrate SB. - It has a higher p-type impurity concentration than the substrate region SBR.

[0026] The n-type drift region DF is disposed in the semiconductor substrate SB. -The n-type drift region DF forms a pn junction with the substrate region SBR. The n-type drift region DF is located between the gate electrode GE and the n-type drain region DR in a plan view. The n-type drift region DF has a first semiconductor region DF1 and a second semiconductor region DF2. The first semiconductor region DF1 is located below the protrusion CON. The second semiconductor region DF2 is disposed on the first semiconductor region DF1 and located within the protrusion CON.

[0027] The second semiconductor region DF2 extends upward from the upper end of the first semiconductor region DF1. The n-type impurity concentration of the first semiconductor region DF1 is equal to the n-type impurity concentration of the second semiconductor region DF2. The n-type impurity concentrations of each of the first semiconductor region DF1 and the second semiconductor region DF2 are, for example, 1×10 17 / cm 3 The boundary between the first semiconductor region DF1 and the second semiconductor region DF2 is, for example, an extension of the surface SU of the semiconductor substrate SB (indicated by the dashed line in the drawing).

[0028] The boundary between the first semiconductor region DF1 and the second semiconductor region DF2 may have a structural discontinuity or an oxide, or the first semiconductor region DF1 and the second semiconductor region DF2 may be integral with each other, making the boundary between the first semiconductor region DF1 and the second semiconductor region DF2 unrecognizable.

[0029] n + The source region SR is disposed in the semiconductor substrate SB on the surface SU of the semiconductor substrate SB. + The source region SR forms a pn junction with the p-type body region BD.

[0030] n + The drain region DR is disposed in the protrusion CON at the upper end of the protrusion CON. + The drain region DR is in contact with the upper end of the n-type drift region DF. + Source regions SR and n + They have a lower n-type impurity concentration than each of the drain regions DR.

[0031] n + Source region SR and n + Between the drain region DR, a p-type body region BD, - The substrate region SBR and the n-type drift region DF are sandwiched between the p-type body region BD and the p - The substrate region SBR and the n-type drift region DF are arranged in this order on the surface SU of the semiconductor substrate SB. + Source region SR to n + They are aligned toward the drain region DR.

[0032] Each of the side surfaces SS1 and SS2 of the protrusion CON is provided with a second semiconductor region DF2 of the n-type drift region DF and + The drain region DR is located in the n-type drift region DF. Specifically, the second semiconductor region DF2 of the n-type drift region DF is located in the lower part of each of the side surfaces SS1 and SS2 of the protrusion CON. Also, the n + The drain region DR is disposed on each of the side surfaces SS1 and SS2 of the protrusion CON. + A junction with the drain region DR is located there.

[0033] The gate electrode GE is disposed on the surface SU of the semiconductor substrate SB. The gate electrode GE is connected to at least the p-type body region BD and the p-type body region BD via the gate insulating layer GI. - The gate electrode GE faces the substrate region SBR. The gate electrode GE also faces the first semiconductor region DF1 with the gate insulating layer GI therebetween. The gate electrode GE is made of, for example, polycrystalline silicon doped with impurities.

[0034] p + The contact region CO is disposed in the semiconductor substrate SB, and + The source region SR and the p-type body region BD are in contact with each other. + The contact region CO has a higher p-type impurity concentration than the p-type body region BD.

[0035] p + The contact region CO is +Area CO1 and 2p + The first p + The region CO1 is located below the convex portion CN. + The area CO2 is the 1st p + It is disposed on the region CO1 and located within the convex portion CN.

[0036] 2nd p. + The area CO2 is the 1st p + It extends upward from the upper end of the region CO1. + The p-type impurity concentration of the region CO1 is the second p + The p-type impurity concentration is equal to that of the region CO2. + Area CO1 and 2p + The boundary with the region CO2 is, for example, an extension of the surface SU of the semiconductor substrate SB (indicated by the dashed line in the drawing).

[0037] 1st p. + Area CO1 and 2p + At the boundary between the first region CO2, there may be a structural discontinuity or oxide. + Area CO1 and 2p + The region CO2 is integral with the first p + Area CO1 and 2p + In some cases, the boundary between the two regions CO2 may not be discernible.

[0038] p - The substrate region SBR penetrates the first semiconductor region DF1 and the second semiconductor region DF2 in the region directly below the protrusion CON. + The drain region DR is reached. - The substrate region SBR forms pn junctions with the side portions of the first semiconductor region DF1 and the second semiconductor region DF2 in the region directly below the protrusion CON. - The substrate region SBR is also disposed inside the protruding portion CON, and forms a pn junction with the second semiconductor region DF2 inside the protruding portion CON. - The substrate region SBR forms a pn junction with the first semiconductor region DF1 and the second semiconductor region DF2, thereby making it possible to obtain a RESURF effect.

[0039] As shown in FIG. 3, each of the side surfaces SS1, SS2, and SS3 may rise perpendicular to the surface SU of the semiconductor substrate SB. In this case, the cross-sectional shape of each of the convex portions CON and CN is, for example, rectangular or square.

[0040] The crystal plane of each of the side surfaces SS1, SS2, and SS3 of the convex portions CON and CN is the {111} plane. The crystal plane of each of the both side surfaces SS1 and SS2 is, for example, the (111) plane, but is not limited thereto, and any plane equivalent to the (111) plane may be used. Further, the crystal plane of the surface SU of the semiconductor substrate SB is, for example, the (110) plane, but is not limited thereto, and any plane equivalent to the (110) plane may be used.

[0041] Each of the side surfaces SS1, SS2, and SS3 rises at an angle of, for example, 90.0 ± 2° (88.0° or more and 92.0° or less) with respect to the surface SU of the semiconductor substrate SB. When the crystal plane of the surface of the semiconductor substrate SB is, for example, the (110) plane and the crystal planes of the side surfaces SS1, SS2, and SS3 are, for example, the (111) planes, theoretically, the angle formed by each of the side surfaces SS1, SS2, and SS3 and the surface SU is 90.0°. However, actually, due to manufacturing errors or the like, the angle formed by each of the both side surfaces SS1 and SS2 and the surface SU may vary within a range of ±2°.

[0042] In addition, the configurations other than the above of the modification example shown in FIG. 3 are substantially the same as the configuration shown in FIG. 2. Therefore, the same elements are denoted by the same reference numerals, and the description thereof will not be repeated.

[0043] <Method for manufacturing LDMOS transistor> Next, the method for manufacturing the LDMOS transistor according to the present embodiment shown in FIG. 2 will be described with reference to FIGS. 4 to 6.

[0044] As shown in FIG. 4, p -An STI structure is formed on the surface of a semiconductor substrate SB having a substrate region SBR. Specifically, a trench TRE is formed on the surface of the semiconductor substrate SB by photolithography and etching. An insulating layer BI made of, for example, a silicon oxide film is formed on the surface of the semiconductor substrate SB so as to fill the trench TRE. Thereafter, the insulating layer BI is removed by CMP (Chemical Mechanical Polishing) until the surface of the semiconductor substrate SB is exposed. As a result, the insulating layer BI remains in the trench TRE, and the STI structure is formed.

[0045] 5, an n-type well region DF and a p-type well region BD are formed in a semiconductor substrate SB. The n-type well region DF becomes an n-type drift region DF, and the p-type well region BD becomes a p-type body region BD. The n-type drift region DF has a p - The p-type body region BD is formed to form a pn junction with the substrate region SBR. - It is formed so as to be in contact with the substrate region SBR.

[0046] 6, a mask layer MK1 made of, for example, a silicon oxide film is formed on the surface of the semiconductor substrate SB. Using the mask layer MK1 as a mask, anisotropic wet etching is performed using, for example, a TMAH (tetramethylammonium hydroxide) aqueous solution. By this etching, the surface of the semiconductor substrate SB exposed from the mask layer MK1 is selectively removed to a predetermined depth.

[0047] This anisotropic wet etching is highly dependent on the crystal orientation. <100> The etching rate in the direction is fast, <111> The etching rate in the direction is the slowest. Therefore, by performing anisotropic wet etching using a (100) silicon substrate, a protrusion CON having both side surfaces SS1 and SS2 of the (111) plane is formed. This forms a trapezoidal protrusion CON having both side surfaces SS1 and SS2 inclined with respect to the surface SU of the semiconductor substrate SB and an upper surface US connecting the upper ends of both side surfaces SS1 and SS2. The above anisotropic wet etching also forms a protrusion CN having a side surface SS3 of the (111) plane.

[0048] By the above etching, the first semiconductor region DF1 located below the protrusion CON and the second semiconductor region DF2 located inside the protrusion CON can be distinguished with reference to the surface SU of the semiconductor substrate SB. That is, the n-type drift region DF can be distinguished into the first semiconductor region DF1 located below the surface SU of the semiconductor substrate SB and the second semiconductor region DF2 located above the surface SU of the semiconductor substrate SB. After this, the mask layer MK1 is removed.

[0049] 2, the surface SU of the semiconductor substrate SB is oxidized. As a result, a gate insulating layer GI made of a silicon oxide film is formed so as to cover the surface SU of the semiconductor substrate SB and the surfaces of the protruding portions CON and CN.

[0050] A polycrystalline silicon layer GE having an impurity doped therein is formed on the gate insulating layer GI. The polycrystalline silicon layer GE is patterned by photolithography and etching techniques to form a gate electrode GE.

[0051] After this, n-type impurities are ion-implanted into the semiconductor substrate SB, + Source region SR and n + A drain region DR is formed. + The source region SR is formed on the surface SU of the semiconductor substrate SB. +The source region SR is formed to form a pn junction with the p-type body region BD. + The drain region DR is formed on the upper surface US of the protrusion CON. + The drain region DR is formed by the second semiconductor region DF2 and p - The substrate regions SBR are formed so as to be in contact with the upper ends of the substrate regions SBR.

[0052] In addition, p-type impurities are ion-implanted into the semiconductor substrate SB, + A contact region CO is formed in the semiconductor substrate SB. + The contact area CO has n + It is formed so as to be in contact with the source region SR and in contact with the p-type body region BD at its lower part. + The contact region CO is a first p + The region CO1 and the second p located inside the convex portion CN + It can be distinguished from the region CO2. + The contact region CO is a first p + The region CO1 and the second p + It can be distinguished from the region CO2.

[0053] In this manner, the LDMOS transistor TR of this embodiment is formed.

[0054] The structure shown in Fig. 3 can be obtained by anisotropically wet etching the surface of the semiconductor substrate SB having, for example, a (110) surface in Fig. 6 using a mask layer MK1 as a mask and a TMAH aqueous solution. The other manufacturing steps are the same as those described above, and therefore will not be described repeatedly.

[0055] <Effects> Next, the effects of this embodiment will be described.

[0056] The present inventors investigated the relationship between the breakdown voltage BVDS and the on-resistance Rsp for each of the configuration of this embodiment shown in Figures 2 and 3 and the configuration of the comparative example shown in Figure 7. As a result, the results shown in Figure 8 were obtained.

[0057] In the comparative example shown in FIG. 7, the convex portions CON and CN are not provided on the front surface SU of the semiconductor substrate SB. + The drain region DR is disposed on the surface SU of the semiconductor substrate SB. Since the configuration of the comparative example shown in Fig. 7 other than the above is almost the same as the configuration of the present embodiment shown in Fig. 2, the same elements are denoted by the same reference characters and description thereof will not be repeated.

[0058] In Fig. 8, data indicated by open circles is data for the comparative example shown in Fig. 7. Data indicated by filled circles is data for this embodiment shown in Fig. 2. Data indicated by filled triangles is data for this embodiment shown in Fig. 3.

[0059] From the results in FIG. 8, it can be seen that in the comparatively low range of breakdown voltage BVDS of 23 V to 28 V, the on-resistance Rsp is reduced in the configuration of this embodiment shown in FIG. 2 compared to the comparative example configuration shown in FIG. 7 when the breakdown voltage BVDS is the same.

[0060] Furthermore, in the comparatively low range of breakdown voltage BVDS of 23 V to 28 V, the configuration of this embodiment shown in FIG. 3 shows a further reduction in on-resistance Rsp when the breakdown voltage BVDS is the same, compared to the configuration of this embodiment shown in FIG.

[0061] It can also be seen that in the configuration of this embodiment shown in Fig. 2, when the on-resistance Rsp is the same, the breakdown voltage BVDS is improved compared to the configuration of the comparative example shown in Fig. 7. It can also be seen that in the configuration of this embodiment shown in Fig. 3, when the on-resistance Rsp is the same, the breakdown voltage BVDS is further improved compared to the configuration of this embodiment shown in Fig. 2.

[0062] As described above, according to the present embodiment shown in Fig. 2 and Fig. 3, a higher breakdown voltage can be obtained with the same size of the LDMOS transistor as compared to the comparative example shown in Fig. 7. This is because, in this embodiment, as shown in Fig. 2 and Fig. 3, + This is believed to be due to the fact that the drain region DR is disposed on the upper surface US of the protrusion CON. + By disposing the drain region DR, the side surfaces SS1 and SS2 of the protrusion CON are inclined or erected, so that n + Source region SR and n + It is considered that the breakdown voltage is improved because the length of the current path between the drain region DR can be increased.

[0063] Furthermore, according to this embodiment shown in FIGS. 2 and 3, if the withstand voltage is the same as that of the comparative example shown in FIG. 7, the cell size of the LDMOS transistor TR can be reduced.

[0064] As described above, the LDMOS transistor TR of this embodiment shown in FIGS. 2 and 3 can more easily achieve improved breakdown voltage and be made smaller in size than the comparative example shown in FIG.

[0065] 3, a higher breakdown voltage can be obtained if the size of the LDMOS transistor is the same as that of the present embodiment shown in FIG 2. This is considered to be due to the fact that in this embodiment, the side surfaces SS1 and SS2 of the protrusion CON are perpendicular to the surface SU of the semiconductor substrate SB, as shown in FIG 3. In other words, because the side surfaces SS1 and SS2 of the protrusion CON are perpendicular to the surface SU, the n + Source region SR and n + It is considered that the breakdown voltage is improved because the length of the current path between the drain region DR can be increased.

[0066] Furthermore, according to this embodiment shown in FIG. 3, if the withstand voltage is the same as that of the embodiment shown in FIG. 2, the cell size of the LDMOS transistor TR can be reduced.

[0067] As described above, the LDMOS transistor TR of the present embodiment shown in FIG. 3 is easier to improve the breakdown voltage and miniaturize than the present embodiment shown in FIG. 2.

[0068] Also, according to the present embodiment, as shown in FIGS. 2 and 3, p - The substrate region SBR is adjacent to each of the first semiconductor region DF1 and the second semiconductor region DF2. As a result, the RESURF effect can be obtained in the first semiconductor region DF1 and the second semiconductor region DF2.

[0069] Also, according to the present embodiment, as shown in FIGS. 2 and 3, p - The substrate region SBR has a portion disposed within the convex portion CON. As a result, p - The substrate region SBR can form a pn junction with the side portion of the second semiconductor region DF2 disposed within the convex portion CON. Therefore, the RESURF effect can also be obtained in the second semiconductor region DF2 within the convex portion CON.

[0070] Also, according to the present embodiment, as shown in FIGS. 2 and 3, p - The substrate region SBR is electrically connected to the ground potential. As a result, p - The RESURF effect by the substrate region SBR can be obtained.

[0071] Also, according to the present embodiment, as shown in FIGS. 2 and 3, the side surfaces SS1 and SS2 of the convex portion CON are composed of inclined surfaces of the {111} plane. As a result, an inclined surface or a vertical surface can be easily formed by anisotropic wet etching using a TMAH aqueous solution.

[0072] (Embodiment 2) <Configuration of LDMOS Transistor> Next, the configuration of the LDMOS transistor as the semiconductor device according to Embodiment 2 will be described with reference to FIG. 9.

[0073] As shown in FIG. 9, the LDMOS transistor TR of the present embodiment has a p within the convex portion CON as compared with the configuration of Embodiment 1 shown in FIG. 2. -It is different in that the substrate region SBR is not arranged.

[0074] In the convex portion CON, an n-type second semiconductor region DF2 and an n + drain region DR are arranged. The n-type second semiconductor region DF2 is arranged over the entire lower portion of the convex portion CON. Also, an n + drain region DR is arranged over the entire upper portion of the convex portion CON. p - The substrate region SBR forms a pn junction with the lower end of the second semiconductor region DF2. p - The pn junction formed by the substrate region SBR and the second semiconductor region DF2 extends along the extension line of the surface SU of the semiconductor substrate SB.

[0075] In addition, since the configuration of this embodiment other than the above is substantially the same as the configuration of Embodiment 1, the same reference numerals are given to the same elements, and the description thereof will not be repeated.

[0076] <Manufacturing method of LDMOS transistor> Next, a method for manufacturing an LDMOS transistor as a semiconductor device according to this embodiment will be described with reference to FIGS. 10 to 14.

[0077] As shown in FIG. 10, according to the manufacturing method of this embodiment, first, p - An n-type diffusion region DF1 is selectively formed on the surface of the semiconductor substrate SB having the substrate region SBR. The n-type diffusion region DF1 is formed so as to form a pn junction with the substrate region SBR at the side and lower portions. The n-type diffusion region DF1 becomes the first semiconductor region DF1 of the n-type drift region DF. -

[0078] As shown in FIG. 11, an n-type epitaxial layer NR is formed on the surface of the semiconductor substrate SB by epitaxial growth. Then, an STI structure is formed on the surface of the semiconductor substrate SB. Specifically, a trench TRE is formed on the surface of the semiconductor substrate SB by photolithography and etching. An insulating layer BI made of, for example, a silicon oxide film is formed on the surface of the semiconductor substrate SB so as to fill the trench TRE. Then, the insulating layer BI is removed by CMP until the surface of the semiconductor substrate SB is exposed. As a result, the insulating layer BI remains in the trench TRE, and the STI structure is formed.

[0079] As shown in Fig. 12, a mask layer MK2 made of, for example, a silicon oxide film is formed on the surface of the semiconductor substrate SB. Using the mask layer MK2 as a mask, anisotropic wet etching is performed using, for example, a TMAH aqueous solution. This etching is performed by removing at least p - This is continued until the substrate region SBR is exposed. As a result, the n-type epitaxial layer NR exposed from the mask layer MK2 is selectively removed.

[0080] This anisotropic wet etching is highly dependent on the crystal orientation. <100> The etching rate in the direction is fast, <111> The etching rate in the direction is the slowest. Therefore, by performing anisotropic wet etching using a (100) silicon substrate, a protrusion CON having both side surfaces SS1 and SS2 of the (111) plane is formed. This forms a trapezoidal protrusion CON having both side surfaces SS1 and SS2 inclined with respect to the surface SU of the semiconductor substrate SB and an upper surface US connecting the upper ends of both side surfaces SS1 and SS2. The above anisotropic wet etching also forms a protrusion CN having a side surface SS3 of the (111) plane.

[0081] By the above etching, the first semiconductor region DF1 located below the convex portion CON and the second semiconductor region DF2 located inside the convex portion CON can be distinguished with reference to the surface SU of the semiconductor substrate SB. That is, the n-type drift region DF can be distinguished into a first semiconductor region DF1 located below the surface SU of the semiconductor substrate SB and a second semiconductor region DF2 located above the surface SU of the semiconductor substrate SB. Thereafter, the mask layer MK2 is removed.

[0082] As shown in FIG. 13, a p-type diffusion region BD is selectively formed on the surface of the semiconductor substrate SB. The p-type diffusion region BD becomes a p-type body region. When forming the p-type diffusion region BD, p-type impurities are selectively ion-implanted into the semiconductor substrate SB. At this time, the p-type impurities are also implanted into the convex portion CN. Therefore, a p-type diffusion region is also formed in the region of the convex portion CN where the STI structure is not formed.

[0083] Thereafter, the manufacturing method of this embodiment goes through the same steps as the manufacturing method of Embodiment 1. Thereby, the LDMOS transistor TR of this embodiment shown in FIG. 9 is formed.

[0084] (Embodiment 3) <Configuration of LDMOS Transistor> Next, the configuration of the LDMOS transistor as a semiconductor device according to Embodiment 3 will be described with reference to FIG. 14.

[0085] As shown in FIG. 14, the LDMOS transistor TR of this embodiment is different in that a p-type resurf region RS is added as compared with the configuration of Embodiment 1 shown in FIG. 2.

[0086] The p-type resurf region RS has a p-type impurity concentration higher than the p-type impurity concentration of the p - substrate region SBR. The p-type resurf region RS forms a pn junction with each side portion of the first semiconductor region DF1 and the second semiconductor region DF2 in the region directly below the convex portion CON.

[0087] The p-type RESURF region RS extends up to a position above the height position of the surface SU of the semiconductor substrate SB. That is, the p-type RESURF region RS has a portion located below the convex portion CON and a portion located inside the convex portion CON.

[0088] The p-type RESURF region RS is + disposed in the region directly below the drain region DR and is + disposed away from the drain region DR. Between the p-type RESURF region RS and the + drain region DR, a - region PR is disposed. The - region PR is disposed inside the convex portion CON.

[0089] The - region PR has the same p-type impurity concentration as the p-type impurity concentration of the p-type substrate region SBR. Also, the - region PR has a p-type impurity concentration lower than the p-type impurity concentration of the p-type RESURF region RS. The upper end of the - region PR forms a pn junction with the - drain region DR. The lower end of the + region PR is connected to the p-type RESURF region RS. - Note that the configuration of this embodiment other than the above is substantially the same as the configuration of Embodiment 1 shown in FIG. 2. Therefore, the same elements are denoted by the same reference numerals, and the description thereof will not be repeated.

[0090] Next, a method for manufacturing an LDMOS transistor as the semiconductor device according to this embodiment will be described with reference to FIGS. 15 to 17.

[0091] <Method for manufacturing an LDMOS transistor> Next, a method for manufacturing an LDMOS transistor as the semiconductor device according to this embodiment will be described with reference to FIGS. 15 to 17.

[0092] The manufacturing method of this embodiment first goes through steps similar to those of the first embodiment shown in FIG. 4. Then, as shown in FIG. 15, an n-type well region DF is selectively formed in the semiconductor substrate SB. Then, a p-type RESURF region RS is formed in the semiconductor substrate SB. The p-type RESURF region RS is formed so as to contact the side of the n-type well region DF. The p-type RESURF region RS is also formed at a position a predetermined depth away from the surface SU of the semiconductor substrate SB. Therefore, there is a p-type RESURF region RS between the p-type RESURF region RS and the surface SU of the semiconductor substrate SB. - The region PR is located. - The region PR was originally p - It is part of the substrate region SBR. - The region PR is p - It has the same p-type impurity concentration as the p-type impurity concentration of the substrate region SBR.

[0093] 16, a mask layer MK3 made of, for example, a silicon oxide film is formed on the surface of the semiconductor substrate SB. Using the mask layer MK3 as a mask, anisotropic wet etching is performed using, for example, a TMAH aqueous solution. By this etching, the surface of the semiconductor substrate SB exposed from the mask layer MK3 is selectively removed.

[0094] This anisotropic wet etching is highly dependent on the crystal orientation. <100> The etching rate in the direction is fast, <111> The etching rate in the direction is the slowest. Therefore, by performing anisotropic wet etching using a (100) silicon substrate, a protrusion CON having both side surfaces SS1 and SS2 of the (111) plane is formed. This forms a trapezoidal protrusion CON having both side surfaces SS1 and SS2 inclined with respect to the surface SU of the semiconductor substrate SB and an upper surface US connecting the upper ends of both side surfaces SS1 and SS2. The above anisotropic wet etching also forms a protrusion CN having a side surface SS3 of the (111) plane.

[0095] By the above etching, the first semiconductor region DF1 located below the protrusion CON and the second semiconductor region DF2 located inside the protrusion CON can be distinguished with reference to the surface SU of the semiconductor substrate SB. That is, the n-type drift region DF can be distinguished into the first semiconductor region DF1 located below the surface SU of the semiconductor substrate SB and the second semiconductor region DF2 located above the surface SU of the semiconductor substrate SB. After this, the mask layer MK3 is removed.

[0096] As shown in Fig. 17, a p-type diffusion region BD is selectively formed in a surface SU of a semiconductor substrate SB. The p-type diffusion region BD becomes a p-type body region. When forming the p-type diffusion region BD, p-type impurities are selectively ion-implanted into the semiconductor substrate SB. At this time, the p-type impurities are also implanted into the protrusion CN. As a result, a p-type diffusion region is also formed in a region of the protrusion CN where the STI structure is not formed.

[0097] Thereafter, the manufacturing method of this embodiment goes through the same steps as those of the manufacturing method of embodiment 1. In this way, the LDMOS transistor TR of this embodiment shown in FIG.

[0098] <Effects> According to this embodiment, as shown in FIG. - The p-type resurf region RS, which has a higher p-type impurity concentration than the substrate region SBR, forms pn junctions with the side portions of the first semiconductor region DF1 and the second semiconductor region DF2, thereby making it possible to obtain a more significant resurf effect.

[0099] In addition, because the p-type RESURF region RS provides a more pronounced RESURF effect, a high breakdown voltage can be obtained even if the n-type impurity concentration in the n-type drift region DF is increased, which allows the n-type impurity concentration in the n-type drift region DF to be increased, thereby reducing the on-resistance.

[0100] The p-type RESURF region RS is + It is separated from the drain region DR. This allows +It is possible to avoid connection between the drain region DR and the p-type RESURF region RS.

[0101] <Application Examples> Next, an application example of the semiconductor device according to this embodiment will be described with reference to FIG.

[0102] As shown in FIG. 18, the LDMOS transistor TR of this embodiment is disposed on a semiconductor substrate SB together with, for example, a MOS transistor. In the formation region of the MOS transistor, a protruding portion CONA is provided on the surface SU of the semiconductor substrate SB. The MOS transistor TR1 is disposed on the protruding portion CONA. The MOS transistor TR1 has an n + A source region SR1 and n + It has a drain region DR1, a gate insulating layer GI1, and a gate electrode GE1.

[0103] In the MOS transistor forming region, a p-type region PE1 is arranged in the protruding portion CONA. + Source region SR1 and n + The drain region DR1 is disposed. + Source regions SR1 and n + Each of the drain regions DR1 forms a pn junction with the p-type region PE1.

[0104] The gate electrode GE1 is disposed on the upper surface of the protruding portion CONA with a gate insulating layer GI1 interposed therebetween. + Source regions SR1 and n + It is disposed on a region sandwiched between the drain regions DR1.

[0105] The height of the protrusion CONA from the surface SU of the semiconductor substrate SB is the same as the height of the protrusion CON from the surface SU of the semiconductor substrate SB. + Source regions SR1 and n + The upper end of each of the drain regions DR1 is connected to the n +The gate electrode GE1 of the MOS transistor TR1 is located at the same height as the upper end of the drain region DR. The gate electrode GE1 of the MOS transistor TR1 is located at a higher position than the gate electrode GE of the LDMOS transistor TR.

[0106] In this manner, the LDMOS transistor TR of this embodiment may be arranged together with a MOD transistor or together with other elements.

[0107] In addition, in FIG. 2, FIG. 3, FIG. 9, and FIG. 14, the lower end of the n-type drift region DF is p - Although the configuration in which the p-type resurf region is in contact with the substrate region SBR has been described, a p-type resurf region in contact with the lower end of the n-type drift region DF may be added. - The additional p-type RESURF region has a p-type impurity concentration higher than the p-type impurity concentration of the substrate region SBR. - The p-type RESURF region is located between the substrate region SBR and the n-type drift region DF, and contacts the lower end of the n-type drift region DF to form a pn junction with the n-type drift region DF. By adding the p-type RESURF region contacting the lower end of the n-type drift region DF, the RESURF effect is more pronounced.

[0108] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0109] ANA: Analog circuit, BD: p-type body region, BI: Insulating layer, CHI: Semiconductor device, CN, CON, CONA: Convex portion, CO: Contact region, CO1: First p + area, CO2 2nd p + area, PR p -region, DF n-type drift region, DF1 first semiconductor region, DF2 second semiconductor region, DR,DR1 drain region, DRI driver circuit, GE,GE1 gate electrode, GI,GI1 gate insulating layer, IOC input / output circuit, LC logic circuit, MK1,MK2,MK3 mask layer, NR n-type epitaxial layer, PC power supply circuit, PDR predriver circuit, PE1 p-type region, RS p-type resurf region, SB semiconductor substrate, SBR substrate region, SR,SR1 source region, SS1,SS2,SS3 side, SU surface, TR,TR1 transistor, TRE trench, US top surface.

Claims

1. a semiconductor substrate having a surface and a protrusion protruding upward from the surface; a gate electrode disposed on the surface of the semiconductor substrate; a first region of a first conductivity type having a portion located inside the protrusion; a drain region of a first conductivity type having a higher impurity concentration than the first region, sandwiching the first region between itself and the gate electrode in a plan view, and disposed within the protrusion and on the first region; The side surface of the protrusion is formed of an inclined surface of a {111} plane.

2. the first region has a first semiconductor region disposed below the protruding portion and a second semiconductor region disposed within the protruding portion, 2. The semiconductor device according to claim 1, wherein a concentration of the first conductive type impurity in said second semiconductor region is equal to a concentration of the first conductive type impurity in said first semiconductor region.

3. 3. The semiconductor device according to claim 2, further comprising a second region of a second conductivity type adjacent to each of said first semiconductor region and said second semiconductor region.

4. The semiconductor device according to claim 3 , wherein the second region has a portion disposed within the protruding portion.

5. 4. The semiconductor device according to claim 3, wherein said second region is electrically connected to a ground potential.

6. the second region includes a substrate region and a high concentration region having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the substrate region; 4. The semiconductor device according to claim 3, wherein said substrate region is adjacent to a bottom end of said first region, and said high concentration region is adjacent to a side portion of said first region.

7. The semiconductor device according to claim 6 , wherein said high concentration region is separated from said drain region.

8. a second transistor different from the first transistor having the drain region and the gate electrode; 2. The semiconductor device according to claim 1, wherein upper ends of the source region and the drain region of said second transistor are located at the same height as an upper end of said drain region of said first transistor.

9. A semiconductor substrate having a surface and a protrusion protruding upward from the surface; a gate electrode disposed on the surface of the semiconductor substrate; a first region of a first conductivity type having a portion located inside the protrusion; a drain region of a first conductivity type having a higher impurity concentration than the first region, sandwiching the first region between itself and the gate electrode in a plan view, and disposed within the protrusion and on the first region; the first region has a first semiconductor region disposed below the protruding portion and a second semiconductor region disposed within the protruding portion, a concentration of the first conductivity type impurity in the second semiconductor region is equal to a concentration of the first conductivity type impurity in the first semiconductor region; The semiconductor device further comprises a second region of a second conductivity type adjacent to each of the first semiconductor region and the second semiconductor region.

10. The semiconductor device described in Claim 9, wherein the second region has a portion located within the convex portion.

11. The semiconductor device of claim 9, wherein the second region is electrically connected to a ground potential.

12. A semiconductor device as described in claim 9, wherein the side of the convex portion is inclined with respect to the surface of the semiconductor substrate.

13. A semiconductor device as described in claim 9, wherein the side of the convex portion rises perpendicular to the surface of the semiconductor substrate.

14. The semiconductor device according to claim 9, wherein the side surface of the convex portion is composed of an inclined surface of a {111} plane.

15. The second region has a substrate region and a high concentration region having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the substrate region, 10. The semiconductor device according to claim 9, wherein the substrate region is adjacent to a bottom end of the first region, and the high concentration region is adjacent to a side of the first region.

16. The semiconductor device of claim 15, wherein the high concentration region is separated from the drain region.

17. The semiconductor device according to claim 1, further comprising a second transistor different from the first transistor having the drain region and the gate electrode, 10. The semiconductor device according to claim 9, wherein upper ends of the source region and the drain region of said second transistor are arranged at the same height as an upper end of said drain region of said first transistor.

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