Semiconductor Device

Abstract

To provide a semiconductor device that is suitable for miniaturization, and alternatively to provide a highly reliable semiconductor device.SOLUTION: A semiconductor device includes a transistor and a capacitive element. The transistor includes a semiconductor layer, the semiconductor layer is positioned over the capacitive element, and the capacitive element includes a first electrode that is electrically connected to the transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. The present invention relates to a method, manufacture, or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, or any of these devices. The present invention relates to a driving method thereof or a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Devices, storage devices, imaging devices, electro-optical devices, power generation devices (thin-film solar cells, organic thin-film solar cells etc.), and electronic devices may include semiconductor devices. [Background technology]

[0003] The technology of constructing transistors using semiconductor materials is attracting attention. Electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices) Silicon-based semiconductor materials are widely used as semiconductor materials that can be used in transistors. are widely known, but oxide semiconductors are attracting attention as another material.

[0004] For example, zinc oxide or In-Ga-Zn oxide semiconductor is used as the oxide semiconductor. Techniques for fabricating a transistor using this method have been disclosed (see Patent Documents 1 and 2).

[0005] In recent years, miniaturized transistors have become more common as electronic devices become more powerful, smaller, and lighter. 2. Description of the Related Art There is an increasing demand for integrated circuits in which semiconductor elements such as transistors are densely integrated. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device that is suitable for miniaturization. An object of the present invention is to provide a semiconductor device with a reduced circuit area.

[0008] Another object of the present invention is to provide a semiconductor device with high reliability. Another object of the present invention is to provide a memory device having good electrical characteristics. Another object of the present invention is to provide a semiconductor device having a novel structure. One of the objectives of the project is to provide a place where

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device including a capacitor and a first transistor. The semiconductor device has a first semiconductor layer, the first semiconductor layer being located above a capacitance element, and the capacitance element is a first The semiconductor device has a first electrode electrically connected to a transistor. In the above, the capacitance element is made up of m layers (m is a natural number of 3 or more) of conductive layers and n layers (n is a natural number). The first insulating film is sandwiched between the first conductive layer and the second conductive layer, and the second insulating film is The first conductive layer is sandwiched between the second conductive layer and the third conductive layer, and the first conductive layer is electrically connected to the third conductive layer. It is preferable.

[0011] Another embodiment of the present invention is a semiconductor device including a capacitor, a first transistor, and a second transistor. The first transistor has a first semiconductor layer, and the capacitance element has n layers (n is a natural number). ) insulating film and k layers (k is a natural number of 2 or more) of conductive layers, It is sandwiched between at least two conductive layers, and the first transistor is connected to the second transistor. The first semiconductor layer is located above the capacitor element, and the second semiconductor layer is located above the capacitor element. an insulating film (n is a natural number) is located between the first transistor and the second transistor, The capacitance element has a first electrode connected to either the source or the drain of the first transistor. The semiconductor device has the following features.

[0012] In the above structure, the n-layer insulating film is formed of at least one of hydrogen, water, and oxygen. In the above structure, the insulating film of the n-layer preferably has a function of blocking Silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide , gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, It is preferable that the material contains at least one of hafnium oxynitride.

[0013] In the above structure, the capacitor and the first transistor preferably overlap each other.

[0014] In the above structure, the first transistor has a first opening provided in the first semiconductor layer. It is preferable that the first electrode contacts the first opening.

[0015] In the above structure, the first transistor has a first conductive layer and a second conductive layer. The first conductive layer and the second conductive layer are in contact with the first semiconductor layer, and the first transistor is The first semiconductor layer and the first conductive layer are provided with an opening, and the first electrode is It is preferable that the conductive layer and the opening provided in the first conductive layer are in contact with each other. Effect of the Invention

[0016] According to one embodiment of the present invention, a semiconductor device suitable for miniaturization can be provided. It is possible to provide a semiconductor device with a reduced path area.

[0017] In addition, a highly reliable semiconductor device can be provided. In addition, a semiconductor device having a memory element with good retention characteristics can be provided. It is also possible to provide a semiconductor device with a novel configuration.

[0018] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other effects from the descriptions in the claims, etc. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 illustrates an example of a semiconductor device according to one embodiment of the present invention. [Diagram 2] FIG. 1 illustrates an example of a semiconductor device according to one embodiment of the present invention. [Diagram 3] FIG. 1 illustrates an example of a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 1 illustrates an example of a semiconductor device according to one embodiment of the present invention. [Diagram 5] 1A and 1B are a circuit diagram and a top view of a transistor according to one embodiment of the present invention. [Figure 6] FIG. 1 illustrates an example of a semiconductor device according to one embodiment of the present invention. [Figure 7] FIG. 1 illustrates an example of a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] FIG. 1 illustrates an example of a semiconductor device according to one embodiment of the present invention. [Figure 17] FIG. 1 illustrates an example of a semiconductor device according to one embodiment of the present invention. [Figure 18] 1A and 1B are a diagram illustrating a band structure of a part of a transistor according to one embodiment of the present invention and a diagram illustrating a current path during conduction. [Figure 19]Cross-sectional TEM image and local Fourier transform image of an oxide semiconductor. [Figure 20] 1A and 1B are diagrams showing a nanobeam electron diffraction pattern of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus. [Figure 21] An example of structural analysis using transmission electron diffraction measurements, and a planar TEM image. [Figure 22] FIG. [Figure 23] 3 shows an example of the configuration of an RF tag according to the embodiment. [Figure 24] 3 shows an example of the configuration of a CPU according to the embodiment. [Diagram 25] 1 is a circuit diagram of a memory element according to an embodiment. [Figure 26] 1A and 1B are a top view and a circuit diagram of a display device according to an embodiment. [Figure 27] 1 is an electronic device according to an embodiment. [Figure 28] 1 shows an example of how an RF tag is used according to an embodiment. [Figure 29] FIG. 1 is a circuit diagram illustrating an example of a semiconductor device according to one embodiment of the present invention. [Diagram 30] FIG. 1 illustrates an example of a semiconductor device according to one embodiment of the present invention. [Diagram 31] 1A and 1B are diagrams showing a semiconductor device. [Diagram 32] FIG. 1 is a top view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Diagram 33] FIG. 1 illustrates an example of a semiconductor device according to one embodiment of the present invention. [Diagram 34] FIG. 1 illustrates an example of a semiconductor device according to one embodiment of the present invention. [Diagram 35] FIG. 1 illustrates an example of a semiconductor device according to one embodiment of the present invention. [Diagram 36] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 37] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 38] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 39] Electron diffraction pattern of CAAC-OS. [Diagram 40] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Diagram 41] Schematic diagram explaining the film formation model of CAAC-OS and nc-OS. [Diagram 42] A diagram explaining InGaZnO4 crystals and pellets. [Diagram 43] Schematic diagram explaining a film formation model of CAAC-OS. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the present invention can be realized by the following embodiments. The present disclosure should not be construed as being limited to the contents of the preceding paragraph.

[0021] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and the repeated explanations are omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be used.

[0022] In each figure described in this specification, the size, layer thickness, or area of ​​each component is indicated by the following formula: The figures may be exaggerated for clarity and are not necessarily limited to scale. stomach.

[0023] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The numbers are added for the purpose of convenience and are not intended to be limiting.

[0024] Even if a material is described as a "semiconductor," it may be considered an "insulator" if, for example, its electrical conductivity is sufficiently low. In addition, the boundary between "semiconductors" and "insulators" is unclear and cannot be clearly defined. In some cases, the distinction cannot be made precisely. Therefore, the term "semiconductor" as used herein means "insulator" Similarly, the term "insulator" used in this specification can be interpreted as "semiconductor." In some cases, this can be rephrased as "body."

[0025] In addition, even if a material is written as a "semiconductor," if the material has a sufficiently high electrical conductivity, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear and not strictly defined. In some cases, the distinction may not be clear. Therefore, the term "semiconductor" as used herein means "conductor" or "electroconductor". Similarly, the term "conductor" used in this specification can be interpreted as "semiconductor In some cases, this can be rephrased as "body."

[0026] A transistor is a type of semiconductor device that controls the amplification of current or voltage and the conduction or non-conduction of electricity. In this specification, the transistor can realize a switching operation that controls the , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT: Thin Film Transistor ).

[0027] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° to 100°. Therefore, it includes the case where the angle is between 85° and 95°. refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0028] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0029] (Embodiment 1) [Example of laminated structure] An example of a stacked structure that can be applied to a semiconductor device of one embodiment of the present invention will be described below with reference to FIG. This will be explained using:

[0030] The stacked structure illustrated in FIG. 1A includes a transistor 100 and a capacitor 150. The transistor 100 is located above the capacitance element 150. The capacitance element 150 is a transistor. It is electrically connected to resistor 100.

[0031] The semiconductor layer 101 of the transistor 100 includes a low resistance region 171a and a low resistance region The low resistance region 171a and the low resistance region 171b may be connected to the source region. It is preferable that the low resistance region 171a and the low resistance region 171b function as a drain region. The resistive region 171b may be doped with impurities. The resistance of 101 can be reduced. The impurities to be added are, for example, argon and boron. , carbon, magnesium, aluminum, silicon, phosphorus, calcium, scandium, titanium Tin, vanadium, chromium, manganese, iron, cobalt, nickel, gallium, germanium Aluminum, arsenic, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum One or more selected from the group consisting of tungsten, cerium, neodymium, hafnium, tantalum, and tungsten The low resistance region 171a and the low resistance region 171b are preferably doped with, for example, The above-mentioned impurity element is added to the semiconductor layer 101 at 5×10 19 atoms / cm 3 Above, I prefer 1×10 20 atoms / cm 3 More preferably, 2×10 20 atoms / cm 3 More preferably, 5×10 20 atoms / cm 3 This is an area that includes the above.

[0032] The stacked structure illustrated in FIG. 1A may include a transistor 130. It is preferable to have a barrier film 111 between the transistor 100 and the transistor 130 . The capacitor element 150 has a conductive layer 151 and a conductive layer 152. The barrier film 111 is It has a structure sandwiched between conductive layers 152 .

[0033] Here, FIG. 1(B) shows a cross section taken along dashed line AB shown in FIG. 1(A). The cross section at the dashed line AB is, for example, the cross section shown in FIG. 1(A) that passes through the dashed line AB. In addition, in FIG. 1(B), some reference numerals are omitted. However, for the parts shown using the same hatching as in FIG. 1(A), please refer to FIG. 1(A), for example. stomach.

[0034] The transistor 130 is made of a first semiconductor material. 00 includes a second semiconductor material. The first semiconductor material and the second semiconductor material are They may be the same material, but are preferably different semiconductor materials.

[0035] Semiconductors that can be used as the first or second semiconductor material include , for example, semiconductor materials such as silicon, germanium, gallium, and arsenic; Compound semiconductor materials containing nium, gallium, arsenic, aluminum, etc., and organic semiconductor materials or an oxide semiconductor material.

[0036] Here, single crystal silicon is used as the first semiconductor material and oxide is used as the second semiconductor material. The case where a semiconductor is used will be described.

[0037] The transistor 100 includes a semiconductor layer 101 formed of a second semiconductor material, a gate insulating film 1 02, a gate electrode 103, a plug 121 and a plug 122. The plug 12 and the insulating film 113 are formed to cover the transistor 100. The insulating film 113, the insulating film 112, and the semiconductor layer 101 are in contact with an opening formed therein, and the insulating film 113 is in contact with the opening formed in the semiconductor layer 101. That is, the plug 121 is connected to the insulating film 113 and the insulating film 112. The insulating layer 104 is formed so as to penetrate the semiconductor layer 101 .

[0038] The barrier film 111 has a function of suppressing the diffusion of water and hydrogen from a lower layer to an upper layer. It is preferable that the barrier film 111 has low oxygen permeability. The barrier film 111 is provided between an electrode or wiring provided above it and an electrode or It may have an opening or a plug for electrically connecting to wiring. For example, In this way, the plug 121 and the conductive layer 151 are electrically connected to each other. The term "suppressing hydrogen diffusion" refers to, for example, silicon oxide, which is generally used as an insulating film. Compared to other materials, it is difficult for water and hydrogen to diffuse or has low permeability. Low permeability means that the permeability of oxygen is lower than that of silicon oxide, which is generally used as an insulating film. This indicates low permeability.

[0039] Like the barrier film 111, the insulating film 112 is preferably made of a material that is difficult for water and hydrogen to diffuse into. In particular, it is preferable to use a material that is difficult for oxygen to permeate for the insulating film 112. The insulating film 112 may have a stacked structure of two or more layers. In that case, for example, The film 112 has a two-layer laminate structure, and the lower layer is, for example, silicon oxide, silicon oxynitride, or silicon oxynitride. Silicon nitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide The upper layer may be made of aluminum nitride or aluminum nitride. It is preferable to use a material in which hydrogen is difficult to diffuse. The insulating film 114 is a semiconductor film formed through the gate insulating film 102 as an insulating film from which oxygen is released by heating. Oxygen may also be supplied from above the conductor layer 101 .

[0040] By covering the semiconductor layer 101 with the insulating film 112 containing a material that is difficult for oxygen to permeate, the semiconductor layer It is possible to suppress the release of oxygen from 101 to above the insulating film 112. Furthermore, oxygen desorbed from the insulating film 114 can be confined below the insulating film 112. Therefore, the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased.

[0041] In addition, the insulating film 112, which is difficult for water and hydrogen to permeate, prevents the oxide semiconductor from being exposed to the outside. The inclusion of impurities such as water and hydrogen can be suppressed, and fluctuations in the electrical characteristics of the transistor 100 can be prevented. This suppresses the generation of the dielectric constant, thereby achieving a highly reliable transistor.

[0042] In addition, below the insulating film 112, there is a layer in which oxygen is desorbed by heating, similar to the insulating film 114. An insulating film is provided, and oxygen is supplied from the upper side of the semiconductor layer 101 through the gate insulating film 102. This may also be configured.

[0043] In addition, the capacitor 150 is preferably formed so as to overlap with the transistor 100. By increasing the overlapping area between the capacitor 150 and the transistor 100, The area of ​​the device can be reduced.

[0044] The semiconductor device shown in FIG. 1 has an insulating film 114 between a transistor 100 and a capacitor element 150. The insulating film 114 preferably contains an oxide. Preferably, the oxide material is a material that separates the oxide from the stoichiometric composition. It is preferable to use an oxide that contains a large amount of oxygen. In the case where the insulating film 114 is used, oxygen released from the insulating film 114 is supplied to the oxide semiconductor. As a result, the electrical characteristics of the second transistor can be improved. Fluctuations can be suppressed and reliability can be improved.

[0045] Here, hydrogen, water, etc. should be reduced as much as possible below the barrier film 111. It is preferable to suppress the desorption of gas. Hydrogen and water are absorbed in the oxide semiconductor. This may cause a change in the electrical characteristics of the lower layer through the barrier film 111. The diffusion of hydrogen and water from the barrier layer to the upper layer can be suppressed by the barrier film 111. Hydrogen and water may diffuse to the upper layer through openings or plugs provided in the film 111. do.

[0046] In order to reduce hydrogen and water contained in each layer located below the barrier film 111, In order to suppress the desorption of gas, the barrier film 111 is formed before the barrier film 111 is formed or the barrier film 111 is introduced thereto. Immediately after forming an opening for forming a conductive layer, etc., the water contained in the layer below the barrier film 111 is removed. It is preferable to carry out a heat treatment to remove oxygen and water or to suppress desorption of gas. The heat resistance of conductive films constituting a semiconductor device and the electrical characteristics of transistors do not deteriorate. The higher the temperature of the heat treatment, the more preferable it is. The temperature is preferably 490°C or higher, more preferably 530°C or higher, but is preferably 650°C or higher. It may be carried out for 1 hour or more under an inert gas atmosphere or a reduced pressure atmosphere, preferably It is preferable to carry out the heat treatment for 5 hours or more, more preferably 10 hours or more. The thickness can be determined by taking into consideration the heat resistance of the wiring or electrode material located below 11. For example, if the material has low heat resistance, the temperature should be 550°C or less, 600°C or less, or 6 The temperature may be 50°C or less, or 800°C or less. It is sufficient to carry out the treatment at least once, but it is more preferable to carry out the treatment multiple times.

[0047] The insulating film provided below the barrier film 111 is analyzed by thermal desorption spectroscopy (TDS analysis). The amount of hydrogen molecules desorbed at a substrate surface temperature of 400°C, as measured by the At 0° C., the amount of hydrogen molecules released is preferably 130% or less, more preferably 110% or less. Alternatively, TDS analysis showed that the amount of desorbed hydrogen molecules at a substrate surface temperature of 450°C was 350 It is preferable that the amount of desorption is 130% or less, and preferably 110% or less, of the amount of desorption at .degree.

[0048] In addition, it is preferable that the water and hydrogen contained in the barrier film 111 itself be reduced. For example, the barrier film 111 may be a TDS-type film. The hydrogen molecule (M / z=2) was analyzed by the deposition in the substrate surface temperature range of 20°C to 600°C. The amount of desorption is 2×10 15 pieces / cm 2 Less than 1 x 10 15 pieces / cm 2 Less than, More than Preferably 5 x 10 14 pieces / cm 2 It is preferable to use a material for the barrier film 111 that has a resistance of less than 1000 MPa. Alternatively, TDS analysis shows that the water vapor deposition rate is 100% in the range of 20℃ to 600℃. The amount of desorption of the molecule (M / z=18) is 1×10 16 pieces / cm 2 Less than 5 x 10 1 5 pieces / cm 2 less than 2×10 12 pieces / cm 2 Barrier film material that is less than 1 It is preferable to use 11.

[0049] In addition, when single crystal silicon is used for the semiconductor layer of the transistor 130, the heat treatment The process is to terminate the dangling bonds of silicon with hydrogen. The hydrogenation process can also be used to remove the impurities from the transistor 13. Water contained in the gate insulating film of 0 or other insulating films formed below the barrier film 111 Some of the elements are detached and diffuse into the semiconductor layer of the first transistor, forming dangling By terminating the bonds, the reliability of the first transistor can be improved.

[0050] Materials that can be used for the barrier film 111 include aluminum oxide, hafnium oxide, and the like. Titanium, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), steel titanate The so-called h-type ferrites, such as (SrTiO3) or (Ba,Sr)TiO3 (BST) Insulating films containing igh-k materials can be used as single layers or laminated layers. The coating may be made of, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, etc. Silicon, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide, gas oxide Lithium may be added to the insulating film. Alternatively, these insulating films may be nitrided to form oxynitride films. Silicon oxide, silicon oxynitride or silicon nitride is laminated on the insulating film. In particular, aluminum oxide is preferred because it has excellent barrier properties against water and hydrogen. stomach.

[0051] The barrier film 111 is made of a layer of a material that is difficult for water and hydrogen to permeate, and also of a layer containing other insulating materials. For example, a layer containing silicon oxide or silicon oxynitride, a metal Layers containing oxides may be laminated.

[0052] Moreover, it is preferable that the barrier film 111 is made of a material that is difficult for oxygen to permeate. The material has excellent barrier properties against oxygen as well as hydrogen and water. By using this, oxygen released when the insulating film 114 is heated is concentrated in a layer below the barrier film 111. As a result, the diffusion of the ions from the insulating film 114 to the This can increase the amount of oxygen that can be supplied to the semiconductor layer of the transistor 100.

[0053] In this way, the concentration of hydrogen and water contained in each layer located below the barrier film 111 is reduced. The barrier film 111 is formed on the surface of the substrate 110 so as to reduce the amount of hydrogen and water emitted, or to suppress the amount of desorbed gas. This prevents hydrogen and water from diffusing into the transistor 100. The hydrogen and water contents in each layer constituting the transistor 100 are extremely low. For example, the insulating film 114, the semiconductor layer 101 of the transistor 100, is the hydrogen concentration in the gate insulating film 102 of 5×10 18 cm -3 Less than 1x, preferably 10 18 cm -3 less than 3×10 17 cm -3 To reduce to less than can be done.

[0054] With the above configuration, both the first transistor and the second transistor have high It is therefore possible to achieve both high reliability and high reliability, thereby achieving a highly reliable semiconductor device.

[0055] The conductive layer 152 may be disposed so as to overlap the channel region of the transistor 100. Examples of this case are shown in Fig. 34(A) and Fig. 34(B). Fig. 34(B) shows the same as Fig. 3 4(A) is a cross section taken along dashed line AB. For example, the gate electrode may have the following function: By supplying a constant potential, the threshold voltage of the transistor 100 can be controlled. Yes, it is possible.

[0056] In addition, an example of a stacked structure that can be applied to a semiconductor device of one embodiment of the present invention is shown in FIG. 3, as shown in FIGS. 4(A) and (B). As shown in FIG. 2, the capacitive element 150 is made up of three or more conductive layers. The conductive layer 151, the conductive layer 153a, and the conductive layer 153b may be formed by laminating them. The capacitor element 150 is electrically connected via the plug 121, the plug 126, and the plug 127. Although not shown, the conductive layer 152, the conductive layer 154a and the conductive The electrode layer 154 c is electrically connected to the capacitor 150 and forms the other electrode of the capacitor 150 .

[0057] As shown in FIG. 3, a conductive layer may be formed on both sides of the plug 126 and the plug 127. The conductive layer 151, the conductive layer 153a, and the conductive layer 153b are connected to the plug 121 and the plug 126. and electrically connected via a plug 127 to form one electrode of the capacitor element 150. Although not shown, the conductive layer 152, the conductive layer 152b, the conductive layer 154a, and the conductive layer 154 b, the conductive layer 154c and the conductive layer 154d are electrically connected to each other, It forms a pole.

[0058] As shown in FIG. 4A, the transistor 100 has a conductive layer in contact with the semiconductor layer 101. 4(A) and the conductive layer 104a and the conductive layer 104b may be included. The cross section is taken along the dashed line AB. The conductive layer 104a and the conductive layer 104b are connected to the source electrode. The transistor 100 has a conductive layer 105 which functions as a drain electrode. The conductive layer 105 may function as a second gate of the transistor 100. A voltage lower or higher than that of the source electrode is applied to the conductive layer 105, The threshold voltage may be shifted in a positive or negative direction. By shifting the threshold voltage of the transistor in the positive direction, the transistor In some cases, the transistor is in a non-conducting state (off state), resulting in a normally-off state. The voltage applied to the conductive layer 105 may be variable or fixed. When the voltage applied to 105 is made variable, a circuit for controlling the voltage is connected to the conductive layer 105. Good too.

[0059] The conductive layer 105 may be connected to the gate electrode 103 .

[0060] [Configuration example] FIG. 5A is an example of a circuit diagram of a semiconductor device of one embodiment of the present invention. The semiconductor device includes a transistor 100, a transistor 130, a capacitor element 150, and wiring. BL, a wiring WL, and a wiring CL.

[0061] One of the source and the drain of the transistor 130 is electrically connected to the wiring BL. The first side is electrically connected to the wiring SL, and the gate is the source or drain of the transistor 100. One electrode of the transistor 100 is electrically connected to one electrode of the capacitor 150. The other of the source and drain is electrically connected to the wiring BL, and the gate is electrically connected to the wiring WL. The other electrode of the capacitor 150 is electrically connected to the wiring CL. The second gate of the transistor 100 is electrically connected to the gate of the transistor 130. The transistor 100 has a source or drain, and the capacitor 150 has a drain. The node between the poles is called node FN.

[0062] The semiconductor device illustrated in FIG. 5A is arranged when the transistor 100 is in a conductive state (on state). A potential corresponding to the potential of the line BL is applied to the node FN. Also, when the transistor 100 is turned off, When the transistor is in the off state, the potential of the node FN is maintained. The semiconductor device shown in FIG. 1A functions as a memory cell of a memory device. The liquid crystal element and organic EL (Electroluminescence) In the case where a display element such as a pixel element is included, the semiconductor device of FIG. It can also be used to

[0063] The conductive or non-conductive state of the transistor 100 is selected by applying a signal to the wiring WL or the wiring BG. It can be controlled by the potential applied to the wiring WL or the wiring BG. The threshold voltage of the transistor 100 can be controlled by the above. In addition, by using a transistor with a small off-state current, the node F Therefore, the potential of N can be maintained for a long period of time. Since the frequency of switching can be reduced, a semiconductor device with low power consumption can be realized. Note that a transistor including an oxide semiconductor is an example of a transistor with low off-state current. Sta. is mentioned.

[0064] A constant potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to the wiring CL. At this time, the apparent threshold voltage of the transistor 100 is The apparent threshold voltage fluctuates, causing the transistor 130 to turn on or off. By utilizing the change in the non-conducting state, the potential information held at the node FN is converted into data. The data can be read out by

[0065] The potential held at node FN is 3.15×10 8 seconds) In order to hold the capacitance, the off-state current per 1 fF and the channel width of the transistor per 1 μm are The current value is 4.3yA (1yA is 10 -24 A) is preferably less than At this time, it is preferable that the allowable fluctuation in the potential of the node FN is within 0.5 V. Alternatively, the off-state current is preferably less than 1.5 yA at 95° C. In the semiconductor device according to the present invention, the hydrogen concentration in the layer below the barrier film is sufficiently reduced. As a result, the transistor using an oxide semiconductor as the upper layer has such an extremely low onset voltage. A floating current can be realized.

[0066] In addition, by increasing the capacitance, the potential can be held at the node FN for a longer period of time. That is, the retention time can be extended.

[0067] By arranging the semiconductor device shown in FIG. 5A in a matrix, a memory device (memory cell It is possible to configure a

[0068] 6A and 6B show cross-sectional configurations of a semiconductor device capable of realizing the circuit shown in FIG. 6B is a cross-sectional view taken along dashed line AB shown in FIG.

[0069] The semiconductor device shown in FIGS. 6A and 6B includes a transistor 130 and a transistor 100. The transistor 100 is provided above the transistor 130. Between the transistor 130 and the transistor 100, at least one barrier film is provided. In addition, the semiconductor device may have a plurality of barrier films. 1 and 2 show an example in which the semiconductor device has barrier films 111a to 111e. 5B shows a top view of the transistor 100. The cross section taken along the dashed line XX′ shown in FIG. is shown as the transistor 100 in FIG. 6A. Also, the dashed line Y-Y′ shown in FIG. A cross section of this is shown as transistor 100 in FIG.

[0070] [First transistor] The transistor 130 is provided on a semiconductor substrate 131 and is made up of a part of the semiconductor substrate 131. A semiconductor layer 132, a gate insulating film 134, a gate electrode 135, and a source region or drain The low resistance layer 133a and the low resistance layer 133b function as an in-region. The illustrated semiconductor device may include a transistor 160. The semiconductor substrate 131 is provided with a capacitor 130 .

[0071] The transistor 130 may be either a p-channel type or an n-channel type, depending on the circuit configuration and An appropriate transistor may be used depending on the driving method.

[0072] The region in which the channel of the semiconductor layer 132 is formed and the region in the vicinity thereof, the source region or the drain region In the low resistance layer 133a and the low resistance layer 133b which become the drain region, a silicon-based semiconductor Preferably, the semiconductor includes a semiconductor such as silicon, and more preferably, the semiconductor includes single crystal silicon. e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), It may be formed of a material having a crystal structure such as GaAlAs (gallium aluminum arsenide). A structure using strained silicon for the crystal may be used. Alternatively, GaAs and AlGaAs, etc. By using the above, the transistor 130 is a HEMT (High Electron Mob It may also be called a capacitance transistor.

[0073] Transistor 130 also includes region 176, which is a lightly doped drain (LDD) region. a and region 176b.

[0074] The low resistance layer 133a and the low resistance layer 133b are made of a semiconductor material applied to the semiconductor layer 132. In addition, elements that impart n-type conductivity, such as phosphorus, or p-type conductivity, such as boron, are added. Contains elements that

[0075] The gate electrode 135 is made of an element that provides n-type conductivity, such as phosphorus, or a p-type element, such as boron. Semiconductor materials such as silicon that contain elements that impart electrical conductivity of the type, metal materials, alloy materials, For the material, conductive materials such as metal oxide materials can be used. In particular, It is preferable to use a high melting point material such as tungsten or molybdenum, which has a high melting point. It is preferable to use a ten.

[0076] Here, the transistors 130 and 160 are replaced with transistors as shown in FIG. A transistor 190 and a transistor 191 may be used. The cross section shown in FIG. 16B is a cross-sectional view of the transistor 190 and the transistor 191. The semiconductor layer 132 (part of the semiconductor substrate) in which the channel is formed has a convex shape, and the side and A gate insulating film 134 and a gate electrode 135 are provided along the upper surface of the semiconductor substrate 130. The transistors 190 and 191 utilize the protruding portions of the semiconductor substrate. Therefore, it is also called a FIN type transistor. In this embodiment, a part of the semiconductor substrate may have an insulating film that functions as a mask. The case where a convex portion is formed by processing the SOI substrate has been shown, but the semiconductor layer having a convex shape is may be formed.

[0077] The transistor 130 is covered with an insulating film 136, an insulating film 137, and an insulating film 138 in this order. The electrodes are provided in a layered structure.

[0078] The insulating film 136 is formed by insulating the low resistance layer 133a and the low resistance layer 133b during the manufacturing process of the semiconductor device. It functions as a protective film when activating the conductive element added to b. 6 may not be provided if not necessary.

[0079] When the semiconductor layer 132 is made of a silicon-based semiconductor material, the insulating film 137 is an insulating material containing hydrogen. The insulating film 137 containing hydrogen is provided over the transistor 130, and By performing heat treatment, dangling bonds in the semiconductor layer 132 are broken down by hydrogen in the insulating film 137. is terminated, and the reliability of the transistor 130 can be improved.

[0080] The insulating film 138 is used to smooth out steps caused by the transistor 130 and other elements disposed below it. The upper surface of the insulating film 138 is formed of a layer that functions as a planarizing layer to improve the planarization of the upper surface. For this purpose, the CMP (Chemical Mechanical Polishing) method is used. The surface may be planarized by a planarization process performed in advance.

[0081] In addition, the insulating film 136, the insulating film 137, and the insulating film 138 are provided with the low resistance layer 133a and the low resistance layer 1 33b, etc., and a plug 140 electrically connected to the gate electrode 135 of the transistor 130. A plug 139 or the like for electrical connection may be embedded.

[0082] [Capacitive element] A barrier film 111 is provided between the transistor 130 and the transistor 100. The barrier film may be a single layer, or may be a multi-layer as shown in FIG. 6. In the example of the semiconductor device shown in FIG. 1, five barrier films, ie, barrier film 111a to barrier film 111e, are provided. When the barrier film is used as the insulating film of a capacitance element, the capacitance can be increased by making the film thickness thin. On the other hand, there is a risk that the barrier properties may decrease when the film is made thinner. Therefore, by stacking multiple thin barrier films, the capacity can be increased and the barrier properties can be improved. This can improve the characteristics of the transistor 100 and the transistor 130. can.

[0083] A conductive layer 151, a conductive layer 152, a conductive layer 153a, and a conductive layer 153 are formed on either side of the barrier film. b and conductive layers 154a to 154e are provided to form a capacitor 150. The plug 121, the plug 126 and the plug 127 are electrically connected. 26 is provided in an opening provided in the barrier film 111b, the insulating film 115b and the barrier film 111c. The conductive layer 151, the conductive layer 153a, and the conductive layer 153b are connected to the plug 127. The plug 126 is electrically connected to the conductive layer 104a of the transistor 100 via the plug 121. The conductive layer 151 is formed so as to be embedded in an opening provided in the insulating film 115a. Similarly, the conductive layers 154a and 154b are connected to the insulating film 115b, and the conductive layer 153a is connected to the insulating film 115b. The insulating film 115c is connected to the conductive layer 154c and the conductive layer 154d is connected to the insulating film 115d. The insulating film 115e is formed with the insulating film 53b so as to be embedded in the openings. .

[0084] 7 shows a cross section taken along dashed line CD in FIG. The conductive layer 154b and the conductive layer 154d are electrically connected to the plug 128. The plug 128 is electrically connected to the plug 129 through the plug 129a to the plug 129d. 28 is connected to wiring 142 via plug 141 .

[0085] An insulating film 114 is provided to cover the barrier film 111, the conductive layer 152, the conductive layer 154e, etc. is.

[0086] The top surface of the insulating film 114 is preferably planarized by the above-mentioned planarization treatment.

[0087] The insulating film 114 is preferably formed using an oxide material from which oxygen is partly released by heating. .

[0088] As an oxide material that releases oxygen by heating, It is preferable to use an oxide containing more oxygen than the stoichiometric composition. When an oxide film containing oxygen is heated, some of the oxygen is released. The oxide film containing more oxygen than the The oxygen in terms of oxygen atoms was analyzed by Esorption Spectroscopy. The amount of desorption is 1.0×10 18 atoms / cm 3 More than 3.0×10 20 at oms / cm3 The oxide film is as above. Note that the surface temperature of the film during the TDS analysis was The temperature is preferably in the range of 100°C to 700°C, or 100°C to 500°C. stomach.

[0089] For example, such a material may include silicon oxide or silicon oxynitride. Alternatively, a metal oxide can be used. Aluminum, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide Uranium, yttrium oxide nitride, hafnium oxide, hafnium oxide nitride, etc. can be used. In this specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen in its composition. Silicon oxide nitride refers to a material that contains more nitrogen than oxygen. Indicates the material with the highest content.

[0090] [Second Transistor] On the insulating film 114, a semiconductor layer 101 of the transistor 100 is provided.

[0091] The transistor 100 includes a semiconductor layer 101 in contact with the upper surface of an insulating film 114 and a conductive layer 104. a and the conductive layer 104b, and a gate insulating film 102 on the semiconductor layer 101, and a gate insulating film 10 The transistor 1 has a gate electrode 103 overlapping with the semiconductor layer 101 via the gate electrode 103. An insulating film 112, an insulating film 113, and an insulating film 116 are provided to cover the first insulating film 110. The transistor 100 may have a conductive layer 105 that functions as a second gate electrode. .

[0092] The semiconductor layer 101 may be formed as a single layer. 00, a stacked structure of semiconductor layers 101a, 101b, and 101c The transistor 100 shown in FIG. A semiconductor layer 101b in contact with the upper surface of the semiconductor layer 101a and a semiconductor layer 101b in contact with the upper surface of the semiconductor layer 101b The conductive layer 104a and the conductive layer 104b are separated in a region overlapping with the semiconductor layer 101b. A semiconductor layer 101c is provided on the upper surface of the conductor layer 101b. A gate insulating film is provided on the semiconductor layer 101c. 102, and the semiconductor layer 101b overlapping with the gate insulating film 102 and the semiconductor layer 101c therebetween. The transistor 100 shown in FIG. The conductive layer 105 functions as an electrode. The conductive layer 105 forms a part of the capacitor 150. The semiconductor layer 101a may be formed simultaneously with the insulating film 114 and the conductive layer 152 that is formed of the insulating film 114. The semiconductor layer 101c is disposed between the semiconductor layer 101b and the gate electrode 101c. The conductive layer 104a and the conductive layer 104b are provided between the gate insulating film 102. , in contact with the upper surface of the semiconductor layer 101b and in contact with the lower surface of the semiconductor layer 101c.

[0093] In addition, insulating films 112, 113, and 116 are provided to cover the transistor 100. It is provided.

[0094] As shown in FIG. 6A, the side surface of the semiconductor layer 101b is covered with the conductive layer 104a and the conductive layer 104b. In addition, the electric field of the gate electrode 103 electrically connects the semiconductor layer 101b to the gate electrode 104b. (The electric field of a conductor can electrically surround a semiconductor.) This structure is called the surrounded channel (s-channel) structure. As a result, a channel may be formed in the entirety (bulk) of the semiconductor layer 101b. The s-channel structure allows a large current to flow between the source and drain of a transistor. This makes it possible to increase the current (on-state current) when the transistor is conductive.

[0095] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device having the transistor The device can be a highly integrated, high density semiconductor device. For example, The transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. More preferably, the transistor has a channel width of 20 nm or less. or less than 40 nm, more preferably less than 30 nm, and even more preferably less than 20 nm. It has a range.

[0096] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part through which current flows when the transistor is on). The source (source region or source electrode) in the region where the channel is formed This refers to the distance between the transistor and the drain (the drain region or the drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is any one of the values, maximum value, minimum value, and The value is the average value.

[0097] The channel width is the width of the semiconductor (or transistor) when it is in the on state. In the region where the gate electrode overlaps with the gate electrode (where the current flows) or in the region where the channel is formed, This refers to the length of the part where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is any one of the values, maximum value, minimum value, and maximum value in the region where the channel is formed. The value is the average value.

[0098] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The channel width becomes larger than the apparent width shown in the figure, and the effect becomes non-negligible. For example, in a transistor with a fine and three-dimensional structure, The percentage of the channel region formed on the side of the semiconductor compared to the percentage of the channel region formed on the inside of the semiconductor. In that case, the apparent channel width shown in the top view may be In this case, the effective channel width where the channel is actually formed is larger than the actual channel width.

[0099] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width unless the exact channel conditions are known. .

[0100] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent thickness is the length of the part where the source and drain face each other in the region where the The channel width is defined as the "surrounded channel width (SCW)". In this specification, when it is simply referred to as the channel width, In some cases, this refers to the enclosed channel width or apparent channel width. In the detailed description, when the term "channel width" is used simply, it may refer to the effective channel width. In addition, channel length, channel width, effective channel width, apparent channel width, enclosure The channel width, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. , values ​​can be determined.

[0101] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0102] At least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) ) is a surface or side of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). The surface is provided on at least a portion (or all) of the face, upper face, and / or lower face.

[0103] Alternatively, at least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) may be The surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a), In contact with at least a portion (or all) of the side, top, and / or bottom surfaces; or At least a portion (or the entirety) of the conductive layer 104a (and / or the conductive layer 104b) At least a portion of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a) ( or all of the above.

[0104] Alternatively, at least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) may be The surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a), Electrically connected to at least a part (or the whole) of the side, top, and / or bottom surfaces Alternatively, at least a portion (or At least one of the semiconductor layers, such as semiconductor layer 101b (and / or semiconductor layer 101a), Also, a part (or the whole) of the wiring conductor 11 is electrically connected to the wiring conductor 11 .

[0105] Alternatively, at least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) may be The surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a), Located adjacent to at least a portion (or all) of the side, top, and / or bottom surfaces. Alternatively, at least a portion (or At least one of the semiconductor layers, such as semiconductor layer 101b (and / or semiconductor layer 101a), Some (or all) of the above are located in close proximity to each other.

[0106] Alternatively, at least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) may be The surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a), It is disposed laterally on at least a portion (or all) of the side, top, and / or bottom surfaces. Alternatively, at least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) ) is at least one of the semiconductor layers such as the semiconductor layer 101b (and / or the semiconductor layer 101a). It is located on part (or all) of the side.

[0107] Alternatively, at least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) may be The surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a), The side, top, and / or bottom surface are at least partially (or entirely) arranged diagonally above the Alternatively, at least a portion (or At least one of the semiconductor layers, such as semiconductor layer 101b (and / or semiconductor layer 101a), In both cases, part (or all) of the sensor is located diagonally above the sensor.

[0108] Alternatively, at least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) may be The surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a), It is disposed on at least a portion (or all) of the side, top, and / or bottom surfaces. Alternatively, at least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) ) is at least one of the semiconductor layers such as the semiconductor layer 101b (and / or the semiconductor layer 101a). It is located on the upper side of part (or all) of the

[0109] The semiconductor layer 101 is made of a semiconductor such as a silicon-based semiconductor in a region where a channel is formed. In particular, the semiconductor layer 101 may include a material having a band gap larger than that of silicon. It is preferable that the semiconductor layer 101 contains an oxide semiconductor. A semiconductor material with a wider band gap and lower carrier density than silicon is called The use of such a compound is preferable because it can reduce the current in the off state of the transistor.

[0110] By using such materials for the semiconductor layer, the fluctuation of electrical characteristics is suppressed, and reliability is improved. High-performance transistors can be realized.

[0111] Regarding preferred forms of oxide semiconductors applicable to the semiconductor layer and methods for forming the same, This will be explained in detail in a later embodiment.

[0112] Note that in the case of being substantially intrinsic in this specification and the like, the carrier density of the oxide semiconductor layer is , 1×10 17 / cm 3 Less than 1×10 15 / cm 3 Less than or equal to 1 × 10 13 / cm 3 Less than 8×10 11 / cm 3 less than 1×10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 End By making the oxide semiconductor layer highly purified and intrinsic, a stable transistor can be formed. Electrical properties can be imparted.

[0113] For example, the semiconductor layer 101b may be made of a material having a composition of In:Ga:Zn=1:1:1 or 3:1:2. When using an In-Ga-Zn oxide with an atomic ratio, the semiconductor layer 101a or the semiconductor layer 10 1c can be, for example, an In-Ga-Zn oxide with an atomic ratio such as In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, 1:6: 4, 1:6:8, 1:6:10, or 1:9:6. Note that the atomic ratios of the semiconductor layer 101b, the semiconductor layer 101a, and the semiconductor layer 101c each include a variation of plus or minus 20% of the above atomic ratio as an error. Also, the semiconductor layer 101a and the semiconductor layer 101c may use materials with the same composition or materials with different compositions. When using an In-M-Zn oxide for the semiconductor layer 101b, the target used to form the semiconductor film that becomes the semiconductor layer 101 b, when the atomic ratio of the metal elements contained in the target is In:M:Zn = x1:y1:z1, the value of x1 / y1 is 1 /

[0114] 3 or more and 6 or less, preferably 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less. It is preferable to use an oxide with such an atomic ratio. Note that by setting z1 / y1 to 6 or less, the CAAC-OS film described later is more likely to be formed. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:1:1, 3:1:2, etc. When using an In-M-Zn oxide for the semiconductor layer 101a and the semiconductor layer 101c, the target used to form the semiconductor films that become the semiconductor layer 101a and the semiconductor layer 101c is such that when the atomic ratio of the metal elements contained in the target is In:M:Zn = x2:y2:z 2, x2 / y2 < x1 / y1, and the value of z2 / y2 is 1 / 3 or more and 6 or less, When using an In-M-Zn oxide for the semiconductor layer 101a and the semiconductor layer 101c, the target used to form the semiconductor films that become the semiconductor layer 101a and the semiconductor layer 101c

[0115] When using an In-M-Zn oxide for the semiconductor layer 101a and the semiconductor layer 101c, the target used to form the semiconductor films that become the semiconductor layer 101a and the semiconductor layer 101c is such that when the atomic ratio of the metal elements contained in the target is In:M:Zn = x2:y2:z 2, x2 / y2 < x1 / y1, and the value of z2 / y2 is 1 / 3 or more and 6 or less, ​It is preferable to use an oxide having an atomic ratio of 1 to 6. By setting the value of the target to 6 or less, the CAAC-OS film described later can be easily formed. Representative examples of atomic ratios of metal elements are In:M:Zn=1:3:4, 1:3:6, 1: For example, 3:8.

[0116] When forming an oxide semiconductor film by sputtering, the atomic ratio of the target may deviate from the target atomic ratio. In particular, zinc has a higher atomic ratio in the film than the atomic ratio in the target. The ratio of the number of atoms of zinc contained in the target may become smaller. It may be between 0 atomic% and 90 atomic%.

[0117] One of the conductive layers 104a and 104b functions as a source electrode and the other functions as a drain electrode. It functions as an insulating electrode.

[0118] The plug 121 is formed by the conductive layer 104a, the semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 1 01c, an electric field is generated between the conductive layer 151 and the insulating film 114 and the barrier film 111 through an opening formed therein. The conductive layer 104a is electrically connected to the conductive layer 151 via the plug 121. Connect to.

[0119] The conductive layer 104a and the conductive layer 104b are made of aluminum, titanium, chromium, nickel, copper, or the like. , yttrium, zirconium, molybdenum, silver, tantalum, or tungsten. Metals or alloys mainly made of metals are used in a single layer or multilayer structure. For example, Single layer structure of aluminum film containing silicon, and two-layer structure of aluminum film laminated on titanium film A two-layer structure in which an aluminum film is laminated on a tungsten film, a copper-magnesium-aluminum A two-layer structure in which a copper film is laminated on a titanium alloy film, a two-layer structure in which a copper film is laminated on a titanium film, A two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or titanium nitride film and the titanium A titanium nitride film is laminated with an aluminum film or a copper film, and a titanium nitride film is laminated with an aluminum film or a copper film. A three-layer structure in which a titanium film or titanium nitride film is formed, a molybdenum film or molybdenum nitride film and Then, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film. There is also a three-layer structure in which a molybdenum film or a molybdenum nitride film is formed on top of the above. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0120] The gate insulating film 102 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide, nitride Silicon or the like may be used, and the layer may be a laminate or a single layer.

[0121] The gate insulating film 102 is made of hafnium silicate (HfSiO x ), nitrogen is added Added hafnium silicate (HfSi x O y N z ), hafnium aluminium doped with nitrogen Luminate (HfAl x O y N z ), using high-k materials such as yttrium oxide Good too.

[0122] The gate insulating film 102 may be made of aluminum oxide, magnesium oxide, or silicon oxide. Silicon oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, silicon oxide oxides such as lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide Insulating film, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride The insulating film can be formed using a nitride insulating film such as those mentioned above, or a film made of a mixture of the above materials.

[0123] The gate insulating film 102 is made of an oxide having a stoichiometric composition similar to the insulating film 114. It is preferable to use an oxide insulating film containing more oxygen than silicon.

[0124] In addition, when a specific material is used for the gate insulating film, electrons are captured in the gate insulating film under specific conditions. For example, silicon oxide and hafnium oxide can be used to increase the threshold voltage. For example, hafnium oxide, aluminum oxide, and oxide are mixed in the gate insulating film. By using a material with many electron capture levels, such as tantalum, and by using a material that can withstand higher temperatures (the operating temperature of semiconductor devices), Or higher than the storage temperature, or 125°C to 450°C, typically 1 At a temperature of 50°C or higher and 300°C or lower, the potential of the gate electrode is set to the potential of the source electrode or drain electrode. By maintaining the higher temperature for at least one second, typically at least one minute, the gate voltage is released from the semiconductor layer. Electrons move toward the pole, some of which are captured by the electron capture level.

[0125] In this way, a transistor that has captured the necessary number of electrons at the electron capture level has a threshold voltage The amount of electrons captured is controlled by controlling the voltage of the gate electrode. This allows the threshold voltage to be controlled. The treatment for adding the conductive layer may be performed during the manufacturing process of a transistor.

[0126] For example, forming wiring metal that connects to the source electrode or drain electrode of a transistor After, or after the completion of the pre-process (wafer processing), or after the wafer dicing process It is advisable to carry out the inspection at any stage before shipment from the factory, after packaging, etc. It is preferred that the subsequent exposure to temperatures above 125° C. is not to be allowed for more than 1 hour.

[0127] The gate electrode 103 is made of, for example, aluminum, chromium, copper, tantalum, titanium, or molybdenum. a metal selected from the group consisting of tungsten, tungsten, or an alloy containing the above-mentioned metals, or It can be formed by using an alloy of metals. In addition, impurity elements such as phosphorus may be used. Semiconductors such as polycrystalline silicon doped with silicon, and silicides such as nickel silicide The gate electrode 103 may have a single-layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a silicon layer on an aluminum film, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film, titanium nitride Two-layer structure with tungsten film laminated on the film, tantalum nitride film or tungsten nitride film A two-layer structure with a tungsten film laminated on top of the titanium film and an aluminum film on top of the titanium film. There are three-layer structures, such as a titanium film on top of the laminated aluminum. Choose from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film made of one or more of the above metals or a nitride film may be used.

[0128] The gate electrode 103 is made of indium tin oxide or indium containing tungsten oxide. Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide, etc. A light-transmitting conductive material such as doped indium tin oxide can also be used. Alternatively, the light-transmitting conductive material and the metal may be laminated together.

[0129] In addition, an In-Ga-Zn-based oxynitride semiconductor is formed between the gate electrode 103 and the gate insulating film 102. Conductor film, In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based Oxynitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (I These films may have a thermal conductivity of 5 eV or more, preferably 5.5 eV or more. Since the work function of the oxide semiconductor is higher than the electron affinity of the oxide semiconductor, The threshold voltage of the transistor using the FET can be shifted to the positive side, For example, an In-Ga-Zn oxynitride semiconductor can be used. In the case of using a semiconductor film, the nitrogen concentration is at least higher than that of the semiconductor layer 101, specifically, 7 atomic % or more. The above In-Ga-Zn-based oxynitride semiconductor film is used.

[0130] The insulating film 112, like the barrier film 111, may be made of a material that is difficult for water and hydrogen to diffuse into. In particular, it is preferable to use a material that is difficult for oxygen to permeate for the insulating film 112. It is.

[0131] By covering the semiconductor layer 101 with the insulating film 112 containing a material that is difficult for oxygen to permeate, the semiconductor layer It is possible to suppress the release of oxygen from 101 to above the insulating film 112. Furthermore, oxygen desorbed from the insulating film 114 can be confined below the insulating film 112. Therefore, the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased.

[0132] In addition, the insulating film 112, which is difficult for water and hydrogen to permeate, prevents the oxide semiconductor from being exposed to the outside. The inclusion of impurities such as water and hydrogen can be suppressed, and fluctuations in the electrical characteristics of the transistor 100 can be prevented. This suppresses the generation of the dielectric constant, thereby achieving a highly reliable transistor.

[0133] In addition, below the insulating film 112, there is a layer in which oxygen is desorbed by heating, similar to the insulating film 114. An insulating film is provided, and oxygen is supplied from the upper side of the semiconductor layer 101 through the gate insulating film 102. This may also be configured.

[0134] As shown in FIG. 6B, in a cross section in the channel width direction of the transistor, The electrode 103 is provided on the upper surface and the side surface of the semiconductor layer 101b, The channel is formed not only near the top surface of 01b but also near the side surface, and the effective channel width is In particular, the semiconductor layer 10 The width of 1b is extremely small (for example, 50 nm or less, preferably 30 nm or less, more preferably In the case where the thickness of the semiconductor layer 101b is 20 nm or less, the region in which the channel is formed extends to the inside of the semiconductor layer 101b. Since the size of the gate electrode spreads, its contribution to the on-current increases as the gate electrode becomes finer.

[0135] 17A and 17B illustrate an example of a transistor 100 included in a semiconductor device. The transistor 100 shown in FIG. 17(A) and (B) is the same as the transistor 100 shown in FIG. In comparison, the semiconductor layer 101c is provided in contact with the lower surfaces of the conductive layers 104a and 104b. The main difference is that the dashed line A in FIG. 17(A) is used. -B is a cross section.

[0136] With this configuration, the semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 10 Each film that makes up 1c is deposited continuously without being exposed to the air. Therefore, the occurrence of defects at each interface can be reduced.

[0137] The transistor 100 may have a structure shown in FIG. After forming the semiconductor layer 101a and the semiconductor layer 101b, the semiconductor layer 101c is formed. The side surfaces of the semiconductor layer 101a and the semiconductor layer 101b are covered with the semiconductor layer 101c. Alternatively, the transistor 100 may have a structure shown in FIG. 35(A) is that the gate electrode 103, the conductive layer 104a, and the gate The electrode 103 and the conductive layer 104b are overlapped in this structure, whereas in FIG. 35B, the conductive layer 104a and the conductive layer 104b do not overlap with each other. No.

[0138] 6(A), 6(B) and 17(A), 17(B), the semiconductor layer 101b is in contact with the semiconductor layer 101b. The configuration in which the conductor layer 101a and the semiconductor layer 101c are provided has been described. Alternatively, one or both of the semiconductor layers 101c may be omitted.

[0139] In the configuration shown in FIG. 6B, the ends of the gate insulating film 102 and the semiconductor layer 101c are roughly The gate electrode 103 is processed so as to be positioned inside the gate insulating film. As an example of a transistor 100 shown in FIG. 17(C), The insulating film 102, the semiconductor layer 101c, and the gate electrode 103 are processed so that their ends are approximately aligned. Alternatively, as in the example of a transistor 100 shown in FIG. The insulating film 102, the semiconductor layer 101c, and the gate electrode are heated so that their ends do not coincide with each other. It may be possible to carry out construction work.

[0140] The above is a description of transistor 100.

[0141] The insulating film 116 covering the transistor 100 serves as a planarizing layer that covers the uneven shape of the underlying layer. The insulating film 113 also functions as a protective film when the insulating film 116 is formed. The insulating film 113 does not have to be provided if it is not necessary.

[0142] The insulating film 112, the insulating film 113, and the insulating film 116 are provided with a conductive layer 104b. Plugs 123, 122, etc. are embedded in the holes.

[0143] On the upper portion of the insulating film 116, wiring 124 and the like that are electrically connected to the plug 123 are provided. There are.

[0144] Here, the wiring 124 shown in FIG. 6A corresponds to the wiring BL shown in FIG. The wiring 166 shown in (B) corresponds to the wiring BG, and the wiring 142 shown in FIG. 7 corresponds to the wiring CL. Although not shown, the wiring connected to the gate electrode 103 in FIG. The low resistance layer 133b of the transistor 130 corresponds to the wiring SL. the gate electrode 135 of the capacitor 130, and the plug 121 which functions as the first electrode of the capacitor element 150. 5A, and the node including the conductive layer 104a of the transistor 100 is a node F Equivalent to N.

[0145] In FIG. 6, the insulating film 137 provided on the insulating film 136 containing hydrogen is a burr It is preferable to provide an insulating film 137 containing the same material as the film 111. With such a configuration, water and hydrogen remaining in the insulating film 136 containing hydrogen are diffused upward. In this case, the insulating film 137 is formed before and after the insulating film 137 is formed. After forming the barrier film 137 and before forming the barrier film 111, water and hydrogen are removed. The heat treatment for this purpose may be carried out two or more times in total.

[0146] The wirings such as the wiring 124, the wiring 142, the wiring 166, etc. may be made of a metal material, an alloy material, or In particular, materials having both heat resistance and electrical conductivity, such as metal oxide materials, can be used. It is preferable to use a high melting point material such as tungsten or molybdenum, which has a high melting point. It is preferable to use stainless steel.

[0147] In addition, the conductive layer 125, the conductive layer 151, the conductive layer 152, the conductive layer 153a, and the conductive layer 153b , conductive layers such as the conductive layers 154a to 154e, plugs 121 to 123, Plug 126 to plug 128, plug 129a to plug 129d, plug 139 to plug The lug 141, the plug 164, the plug 165, and other plugs are made of metal materials, alloy materials, etc. In particular, materials having heat resistance and electrical conductivity, such as metal oxide materials, can be used. It is preferable to use a high melting point material such as tungsten or molybdenum, which has both excellent thermal conductivity and excellent thermal conductivity. It is preferable to use tungsten. In addition, materials such as titanium nitride and titanium can be used in combination with other materials. For example, titanium nitride or titanium can be used to improve the In addition, the adhesiveness of the conductive layer 125, the conductive layer 151, the conductive layer 152, Conductive layers such as the conductive layer 153a, the conductive layer 153b, and the conductive layers 154a to 154e, and the like, Lugs 121 to 123, plugs 126 to 128, plugs 129a to 12 9d, plugs 139 to 141, plug 164, plug 165, etc. It is preferable that they are embedded in the velum and that the upper surface of each is flattened.

[0148] Here, the plug 121 is a semiconductor layer 101, a conductive layer 104a, and a First, the semiconductor layer 101 and the conductive layer 10 of the transistor 100 are in contact with each other. 4a, which is connected to the source region or drain region of the transistor 100. In addition, the conductive layer 151 functions as a wiring. The plug 121 penetrates the transistor 100 and functions as a wiring that connects to the electrodes. By reaching the conductive layer 151, which is one electrode of the element 150, An electrode of the capacitance element 150 is connected to the source region or the drain region of the transistor 100. It can also serve as wiring.

[0149] Similarly, the plug 122 is connected to the semiconductor layer 101, the conductive layer 104b and the First, the semiconductor layer 101 and the conductive layer 10 of the transistor 100 are in contact with each other. 4b, which is connected to the source or drain region of the transistor 100. In addition, the conductive layer 125 functions as a wiring. The plug 122 functions as a wiring connecting to the source region or the drain region of the transistor. By penetrating the transistor 100 and reaching the conductive layer 125, The wiring connected to the source region or drain region of the transistor 130 and the source region or drain region of the transistor 100 are connected to the The insulating film 14 can also serve as a wiring connected to the source electrode or the drain electrode.

[0150] Next, an example of how the circuit area can be reduced by using the plugs 121 and 122 will be described with reference to FIG. The configuration shown in FIG. 31 does not use the plug 121 and the plug 122. For the barrier film 211a, see the description of the barrier film 111. The insulating film 115a is described with reference to the insulating film 115a. The contact 221 with the semiconductor layer 50 is formed outside the semiconductor layer 101b. Similarly, the conductive layer 104b and the source region of the transistor 130 Alternatively, the contact 222 with the conductive layer connected to the drain region is formed to be lower than the semiconductor layer 101b. Since it is formed on the outside, it causes an increase in the element area.

[0151] In the configuration example shown in FIG. 30A, one side of the capacitor 150 is connected through the transistor 100. A plug 121 is connected to the electrode of the transistor 100 and passes through the transistor 100 to the electrode of the transistor 130. A plug 12 connected to the conductive layer 251a electrically connected to the source electrode or drain region 2 is used. The barrier films 211a to 211f are the same as those in the barrier film 111. For the insulating films 215a to 215f, see the description of the insulating film 115a. For the conductive layer 251, refer to the description of the conductive layer 151. Please refer to the description of 5. Note that FIG. 30(B) is a diagram in which two configurations shown in FIG. 30(A) are arranged side by side. In addition, FIG. 30 shows an example in which the conductive layer 104a and the conductive layer 104b are not provided. However, it may be provided.

[0152] In FIG. 31, a contact 221 between the conductive layer 104a and the capacitance element 150, and a plug Since two contacts are provided, 321 and contact 223 of conductive layer 104a, On the other hand, in FIG. 30, the roles of the two contacts can be fulfilled by plug 121. Similarly, in FIG. 31, a contact 222 between the conductive layer 104b and the conductive layer 251a, Two contacts are provided: a plug 322 and a contact 224 to the conductive layer 104b. In FIG. 30, the role of the two contacts is taken on by a plug 122. In this way, by using the plug 121 and the plug 122, the structure shown in FIG. In the fabrication, the capacitance element 150 can be fabricated with a width approximately equal to that of the transistor 100. The child's footprint can be reduced.

[0153] Next, in the cross-sectional view shown in FIG. 30, a top view of the layers 281 to 287 is shown in FIG. In addition, in the cross-sectional view shown in FIG. 31, a top view of the layers 291 to 295 is shown in FIG. Each top view shows the minimum constituent unit of a memory cell. It can be seen that this can reduce the area to about half that of FIG.

[0154] Also, as shown in the cross section of the semiconductor device in FIG. 33, an insulating film 261 is provided for planarization. The plugs 121 and 122 may be formed from the above.

[0155] The semiconductor device of one embodiment of the present invention includes a transistor 130 and a first transistor 130. Since the transistor 100 is located above the transistor 100, the transistors 100 and 100 are stacked. The area occupied by the element can be reduced. This reduces the area occupied by the elements. A semiconductor device having favorable characteristics can be provided. When used in a semiconductor device having a memory, etc., it increases the memory capacity even with a small circuit area, It is possible to provide a semiconductor device having a memory with good retention characteristics. The barrier film 111 provided between the stator 130 and the transistor 100 Impurities such as water and hydrogen present in the lower layer can be prevented from diffusing into the transistor 100. Furthermore, a wiring having a part functioning as a first electrode and a part functioning as a second electrode are sandwiched between the barrier film 111. A wiring functioning as a second electrode is provided to form the capacitor 150. The capacitance element 150 can be easily manufactured without adding a separate process for manufacturing the capacitance element 150. This can be done.

[0156] The above is a description of the configuration example.

[0157] [Example of manufacturing method] An example of a method for manufacturing the semiconductor device shown in the above configuration example will be described below with reference to FIGS. The following description will be given using a cross-sectional view of the same.

[0158] First, a semiconductor substrate 131 is prepared. The semiconductor substrate 131 is, for example, a single crystal silicon. Silicon substrates (including p-type semiconductor substrates and n-type semiconductor substrates), silicon carbide and gallium nitride A compound semiconductor substrate made of aluminum can be used as the semiconductor substrate 131. In the following, single crystal silicon is used as the semiconductor substrate 131. This section explains what happens if

[0159] Next, an element isolation layer (not shown) is formed on the semiconductor substrate 131. The element isolation layer is formed by LOC. OS (Local Oxidation of Silicon) method or STI (Sh If the trench isolation method or mesa isolation method is used, good.

[0160] When forming p-type transistors and n-type transistors on the same substrate, the semiconductor substrate 1 For example, an n-type well or a p-type well may be formed in a portion of the n-type semiconductor substrate 13. 1 is doped with impurity elements such as boron that give it p-type conductivity to form a p-well, An n-type transistor and a p-type transistor may be formed on the substrate.

[0161] Next, an insulating film that will become the gate insulating film 134 is formed on the semiconductor substrate 131. For example, The surface of the semiconductor substrate 131 is oxidized to form a silicon oxide film. After the silicon oxide film is formed, a nitriding process is performed to nitride the surface of the silicon oxide film. In this way, a stacked structure of a silicon oxide film and a silicon oxynitride film may be formed. Alternatively, silicon oxide, silicon oxynitride, or high-dielectric-constant materials (also called high-k materials) Tantalum oxide, hafnium oxide, hafnium silicate oxide, zirconium oxide, Metal oxides such as aluminum oxide, titanium oxide, or rare earth oxides such as lanthanum oxide Objects etc. may also be used.

[0162] The insulating film is formed by sputtering, CVD (Chemical Vapor Deposition) sition) method (thermal CVD method, MOCVD (Metal Organic CVD) method , PECVD (Plasma Enhanced CVD) method, etc.), MBE (Mo lecular beam epitaxy) method, ALD (Atomic Layer Deposition) method, or PLD (Pulsed Laser Deposit) method Alternatively, the film may be formed by a film formation method such as a (ion) method.

[0163] Next, a conductive film that will become the gate electrode 135 is formed. Metals selected from the group consisting of tin, titanium, molybdenum, chromium, niobium, etc., or It is preferable to use an alloy material or a compound material whose main component is a metal. The polycrystalline silicon to which the impurity is added can be used. A laminated structure of metal films may be used. Examples of metal nitrides include tungsten nitride and molybdenum nitride. By providing a metal nitride film, the density of the metal film can be improved. This can improve adhesion and prevent peeling.

[0164] Conductive films are formed by sputtering, deposition, CVD (thermal CVD, MOCVD, PEC It is possible to form a film by a method such as VD method. It also reduces damage caused by plasma. For this purpose, a thermal CVD method, an MOCVD method or an ALD method is preferable.

[0165] Next, a resist mask is formed on the conductive film by using a lithography method or the like. The unnecessary parts of the film are removed. Then, the resist mask is removed to reveal the gate electrode. 135 can be formed.

[0166] Here, a method for processing a film to be processed will be described. When processing a film to be processed finely, Various microfabrication techniques can be used. For example, A method of slimming the resist mask may be used. A dummy pattern was formed by a raffin method or the like, and a sidewall was formed on the dummy pattern. After that, the dummy pattern is removed, and the remaining sidewall is used as a resist mask. The film to be processed may be etched. In addition, the etching of the film to be processed may be performed using a method for etching a film having a high aspect ratio. In order to achieve this, it is preferable to use anisotropic dry etching. Alternatively, a hard mask made of a metal film may be used.

[0167] The light used to form the resist mask is, for example, i-line (wavelength 365 nm) or g-line (wavelength 43 6 nm), H-line (wavelength 405 nm), or a mixture of these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used. Also, the exposure may be performed by immersion lithography. Light (EUV: Extreme Ultra-violet) or X-rays may also be used. Instead of light for exposure, electron beams can be used. Extreme ultraviolet light, X-rays, or The use of an electron beam is preferable because it enables extremely fine processing. When exposure is performed by scanning a beam such as a photomask, no photomask is required.

[0168] In addition, before forming the resist film that will become the resist mask, the film to be processed and the resist film are closely An organic resin film having a function of improving adhesion may be formed. The organic resin film may be, for example, By using a pin coating method or the like, the step of the lower layer is covered and the surface is flattened. This makes it possible to reduce the variation in thickness of the resist mask provided on the organic resin film. In particular, when fine processing is performed, the organic resin film is required to have a high resistance to the light used for exposure. It is preferable to use a material that functions as an anti-reflection film. As the resin film, for example, BARC (Bottom Anti-Reflection The organic resin film is removed at the same time as the resist mask is removed. Alternatively, it may be removed after removing the resist mask.

[0169] After the gate electrode 135 is formed, a sidewall is formed to cover the side surface of the gate electrode 135. The sidewall may be formed by depositing an insulating film thicker than the gate electrode 135, and then Anisotropic etching is performed to leave the insulating film only on the side of the gate electrode 135. It can be formed by:

[0170] FIG. 8(A) shows an example in which the gate insulating film is not etched when the sidewall is formed. 1, the insulating film that will become the gate insulating film 134 is also etched at the same time when the sidewall is formed. In this case, the gate insulating film 13 is formed on the lower part of the gate electrode 135 and the sidewall. 4 is formed.

[0171] Next, the gate electrode 135 (and sidewalls) of the semiconductor substrate 131 are provided. In the area where there is no n-type conductivity, such as phosphorus, or p-type conductivity, such as boron, is added. The element to be added is added. The schematic cross-sectional view at this stage corresponds to FIG. 8(A).

[0172] Next, after forming the insulating film 136, the above-mentioned element for imparting conductivity is activated. A first heat treatment is carried out.

[0173] The insulating film 136 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or silicon oxide. Silicon, Aluminum Oxide, Aluminum Oxynitride, Aluminum Oxide Nitride, Aluminum Nitride The insulating film 136 is formed by a sputtering method. , CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method Alternatively, the insulating film can be formed by using a PLD method or the like. In particular, the insulating film can be formed by using a CVD method, preferably Alternatively, it is preferable to form the film by a plasma CVD method, since the coating property can be improved. In order to reduce damage caused by plasma, it is necessary to use thermal CVD, MOCVD or A The LD method is preferred.

[0174] The first heat treatment is performed under an inert gas atmosphere such as a rare gas or nitrogen gas, or under a reduced pressure atmosphere. The heating can be performed at a temperature of, for example, 400° C. or higher but below the strain point of the substrate.

[0175] At this stage, the transistor 130 is formed. In a similar manner, transistor 160 may be formed.

[0176] Subsequently, an insulating film 137 and an insulating film 138 are formed.

[0177] The insulating film 137 may be made of a material that can be used for the insulating film 136, or a nitrogen-containing material that contains oxygen and hydrogen. By using silicon oxynitride (SiNOH), the amount of hydrogen released by heating can be increased. In addition, the insulating film 138 can be formed of the same material as the insulating film 136. In addition, TEOS (Tetra-Ethyl-Ortho-Silicate) or Silicon oxide with good step coverage formed by reacting silane with oxygen or nitrous oxide. It is preferable to use the element.

[0178] The insulating film 137 and the insulating film 138 are formed by, for example, a sputtering method, a CVD method (thermal CVD method, (including MOCVD, PECVD, etc.), MBE, ALD, or PLD methods, etc. In particular, the insulating film can be formed by a CVD method, preferably a plasma CVD method. Therefore, it is preferable to form a film by using plasma, since the covering property can be improved. To reduce damage, the thermal CVD method, the MOCVD method, or the ALD method is preferable.

[0179] Next, the upper surface of the insulating film 138 is planarized by a CMP method or the like. In this case, it is not necessary to perform planarization by the CMP method or the like. The planarization film can be formed by, for example, atmospheric pressure CVD or coating. Examples of films that can be formed using the VD method include BPSG (Boron Phosphor In addition, it can be formed by coating method. An example of the film that can be used is HSQ (hydrogen silsesquioxane).

[0180] Then, the dangling bonds in the semiconductor layer 132 are desorbed from the insulating film 137 by hydrogen. The second heat treatment is then performed to terminate the layers. By desorbing the water and hydrogen contained in the fuel, the water and hydrogen contents can be reduced.

[0181] The second heat treatment can be carried out under the conditions exemplified in the description of the laminated structure above. For example, The conditions described for the heat treatment in 1 can be used.

[0182] Next, the low resistance layer 133a and the low resistance layer 133b are formed on the insulating film 136, the insulating film 137, and the insulating film 138. An opening is formed that reaches the layer 133b and the gate electrode 135 (see FIG. 8(B)). Thereafter, a conductive film 181 that will become the plug 139 or the like is formed so as to fill the opening (see FIG. 8(C)). After that, the conductive film 181 is subjected to a planarization process so that the upper surface of the insulating film 138 is exposed. As a result, plugs 139 and 140 are formed (see FIG. 8(D)). The formation of 81 can be performed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, PEC It can be formed by using a method such as MBE, ALD, or PLD. do.

[0183] Next, the insulating film 115e is formed on the insulating film 138, and an opening is formed. A conductive film is formed so as to fill the gap, and a flat layer is formed on the conductive film so as to expose the upper surface of the insulating film 115e. By carrying out a flattening process, the conductive layer 144 and the conductive layer 153b are formed (FIG. 8(E) 6, the conductive layer 153b functions as an electrode of the capacitor.

[0184] Next, a barrier film 111e is formed, and then an insulating film 115d is formed (see FIG. 9(A)). Next, an opening is formed in the insulating film 115d. Then, a conductive layer is formed so as to fill the opening. A conductive film is formed, and a planarization process is performed on the conductive film so that the upper surface of the insulating film 115e is exposed. As a result, the conductive layers 154d and 154e are formed (see FIG. 9B). In the example shown in FIG. 1, the conductive layer 154d and the conductive layer 154e function as electrodes of a capacitor element. After that, a barrier film 111d is formed (see FIG. 9(C)).

[0185] Next, an opening is formed in the barrier film 111d, the insulating film 115d, and the barrier film 111e. Thereafter, a conductive film that becomes the plug 127 or the like is formed so as to fill the opening, and the barrier film 111 The conductive film is planarized so that the upper surface of the plug 127 and the Then, plugs 145 and the like are formed (see FIG. 9(D)).

[0186] Next, the insulating film 115c is formed (see FIG. 10(A)). An opening is then formed in the insulating film 115c. The conductive film is planarized so that the conductive surface is exposed. The conductive layer 153a and the like are formed (see FIG. 10B). It functions as such.

[0187] Next, the conductive layer 154a, the conductive layer 154b, the plug 126 and the plug 147 are formed as shown in FIG. After the barrier film 111a is formed by the same method as that shown in FIG. After forming an opening in the region in contact with the conductive layer 143 of a, a conductive film is formed. A resist mask is then formed, and unnecessary portions of the conductive film are removed by etching. By removing the mask, the conductive layer 152, the conductive layer 154e, and the second gate electrode are left. In this way, a conductive layer 105 functioning as the conductive layer can be formed (see FIG. 10C).

[0188] Here, in FIG. 9(D), the barrier film 111d has been subjected to a planarization process. As shown in FIG. 10, the barrier film 111d may be used as an insulating film for the capacitance element. Alternatively, the steps of FIG. 9(D) to FIG. 10(C) may be replaced with, for example, the steps of FIG. 13(A) to 14(B) may be substituted. After removing the barrier film 111d once, For example, a film may be formed on the surface of the substrate by a CMP method or the like. When chemical treatment is performed, damage may sometimes occur to the surface of the film. If so, remove the damaged film or surface area of ​​the film as described below. Then, the insulating film used for the capacitance element is formed again, thereby further improving the capacitance characteristics. This can be done.

[0189] FIG. 13A shows the barrier film 111d and the plug 12 as described in FIG. 9D. 13B shows the state in which the conductive film 7 is planarized. Then, the barrier film 111d is removed by etching or the like. Then, the barrier film 111f is formed. Next, a resist mask is formed and etching is performed to remove the barrier film 111f. Among them, an opening is provided in the barrier film 111f on the plugs such as the plug 127 and the plug 145. After that, the resist mask is removed (see FIG. 13(C)).

[0190] Next, an insulating film 115c is formed. After that, a resist mask is formed and etching is performed. Then, a conductive layer is formed in the insulating film 115c so as to fill the opening. Then, a layer 146, a conductive layer 153a, and the like are formed (see FIG. 14A).

[0191] Next, a barrier film 111c is formed, and then an insulating film 115b is formed. The layer 154c, the conductive layer 154d, the barrier film 111f, the plug 127 and the plug 145 are formed. The conductive layer 154a, the conductive layer 154b, the barrier film 111g, and the The plug 126 and the plug 147 are formed.

[0192] Next, the insulating film 115a is formed. Then, the conductive layer 146 and the conductive layer 153a are formed. The conductive layer 125 and the conductive layer 151 are formed by using the same method as that described above. After that, an opening is provided in the barrier film 111a, and then a conductive film is formed. A conductive layer 105, a conductive layer 152, and a conductive layer 154e are formed using a resist mask or the like. (See FIG. 14(B)). The above is the process of FIG. 9(D) to FIG. 10(C) in FIG. This is an explanation of the case where the steps are replaced with those in FIG.

[0193] The insulating films 115a to 115e are formed of the same material and by the same method as the insulating film 136. It can be formed.

[0194] The barrier films 111a to 111g are formed by, for example, a sputtering method or a CVD method (thermal C (including VD, MOCVD, PECVD, etc.), MBE, ALD, PLD, etc. In particular, the insulating film can be formed by a CVD method, preferably a plasma C method. The VD method is preferable because it can improve the coating property. To reduce damage caused by ions, thermal CVD, MOCVD, or ALD methods are preferred. The materials that can be used for the barrier films 111a to 111g are Please refer to the description in the above.

[0195] After the insulating film 115e is formed, third heat treatment is preferably performed. By removing the water and hydrogen contained in each layer, the water and hydrogen content is reduced. Immediately before forming the barrier film 111e, a third heat treatment is performed to form the barrier film 11 After thoroughly removing hydrogen and water contained in the layer below 1e, a barrier film 111e is formed. By doing so, water or hydrogen will be diffused again below the barrier film 111e in a later process. The above-mentioned problems can be suppressed.

[0196] The third heat treatment can be carried out under the conditions exemplified in the description of the laminated structure above. For example, The conditions for the heat treatment described in the first embodiment can be used. After the film 115d is formed, a similar heat treatment may be performed after the formation of each insulating film. .

[0197] At this stage, the capacitor element 150 is formed. The capacitor element 150 has a first electrode and a second electrode. The conductive layer 152 and the conductive layers 154a to 154e functioning as a second electrode The conductive layer 151, the conductive layer 153a, and the conductive layer 153b function as a The insulating film 111 is constituted by barrier films 111a to 111e.

[0198] Next, the insulating film 114 is formed. The insulating film 114 is formed by, for example, a sputtering method or a CVD method. (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD or PL In particular, the insulating film can be formed by a CVD method, preferably a Plasma It is preferable to form the film by the Zuma CVD method, since it is possible to improve the covering property. To reduce damage caused by plasma, thermal CVD, MOCVD or ALD are preferred. I wish.

[0199] In order to make the insulating film 114 contain excess oxygen, for example, the insulating film 11 is heated in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 114 after the film formation to make it contain excess oxygen. Alternatively, a region having either of these may be formed, or both approaches may be combined.

[0200] For example, oxygen (at least oxygen radicals, oxygen atoms, oxygen ions, etc.) may be added to the insulating film 114 after the film formation. A region containing excess oxygen is formed by introducing oxygen into the film. These include ion implantation, ion doping, plasma immersion ion implantation, and plasma Plasma treatment or the like can be used.

[0201] In the oxygen introduction process, a gas containing oxygen can be used. Examples of the gas containing oxygen include: Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, and the like can be used. In the oxygen introduction process, a rare gas may be added to the oxygen-containing gas. For example, a mixture of carbon dioxide, hydrogen and argon may be used. stomach.

[0202] After forming the insulating film 114, the insulating film 114 is polished by a CMP method or the like to improve the flatness of the upper surface. A flattening process may also be performed.

[0203] Next, a semiconductor film that will become the semiconductor layer 101a and a semiconductor film that will become the semiconductor layer 101b are formed in this order. It is preferable that the semiconductor film is continuously formed without being exposed to the air. The semiconductor that will become the semiconductor layer 101a and the semiconductor that will become the semiconductor layer 101b are formed by sputtering. The film may be formed by a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0204] The semiconductors to be the semiconductor layer 101a and the semiconductor layer 101b are as follows: When forming an In-Ga-Zn oxide layer by MOCVD, trimer gas is used as the source gas. Examples of suitable materials include trimethylindium, trimethylgallium, and dimethylzinc. The combination of raw material gases is not limited to the above, and triethylindium may be used instead of trimethylindium. Also, triethylgallium may be used in place of trimethylgallium. Also, diethyl zinc or the like may be used in place of dimethyl zinc.

[0205] After the semiconductor film is formed, a fourth heat treatment is preferably performed. At a temperature of 650°C or less, preferably 300°C to 500°C, in an inert gas atmosphere, and in an oxidizing atmosphere. The heat treatment may be carried out in an atmosphere containing 10 ppm or more of reactive gas or under reduced pressure. The atmosphere is an inert gas atmosphere, and then an oxidizing gas is introduced to replenish the oxygen that has been removed. The heat treatment may be performed in an atmosphere containing 10 ppm or more of fluorine. Alternatively, the semiconductor film may be processed to form island-shaped semiconductor layers 101a and 101b, and then By the heat treatment, oxygen is supplied from the insulating film 114 or the oxide film to the semiconductor film. In this way, oxygen vacancies in the semiconductor film can be reduced.

[0206] After that, a resist mask is formed and unnecessary parts are removed by etching. By removing the resist mask, the island-shaped semiconductor layer 101a and the island-shaped semiconductor layer 101b are formed. A laminated structure of the above can be formed (see FIG. 11(A)). During etching, a part of the insulating film 114 is etched, and the semiconductor layer 101a and the semiconductor layer 101 The insulating film 114 in the area not covered by b may become thin. It is preferable to form the insulating film 114 thick in advance so that it is not lost by the etching. stomach.

[0207] Thereafter, the conductive film 104 is formed (see FIG. 11(B)). For example, sputtering method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.) The insulating layer can be formed by using the MBE method, the ALD method, the PLD method, or the like. When the insulating film is formed by a CVD method, preferably a plasma CVD method, the coating property is improved. In order to reduce damage caused by plasma, the thermal CVD method and M The OCVD method or the ALD method is preferred.

[0208] Next, a resist mask is formed, and unnecessary portions of the conductive film 104 are removed by etching. Then, the resist mask is removed, and the conductive layer 104a and the conductive layer 104b are formed. Here, when the conductive film is etched, a part of the semiconductor layer 101b and the upper part of the insulating film 114 are etched. The conductive layer 104a and the conductive layer 104b are etched to thin the portions that do not overlap with each other. Therefore, the thickness of the semiconductor film or the like that becomes the semiconductor layer 101b is determined by the etching depth. It is preferable to form the insulating layer 11 thick in advance in consideration of the above.

[0209] Next, a gate insulating film 102 and a semiconductor layer 101c are formed, a resist mask is formed, and an etching process is performed. Then, the resist mask is removed. A conductive film is formed (see FIG. 12(A)). After that, a resist mask is formed and etching is performed. The conductive film is processed by etching, and then the resist mask is removed to form the gate electrode 103. The semiconductor layer 101c is formed by sputtering, CVD, MBE or P The film may be formed by using the LD method, the ALD method, or the like.

[0210] As a semiconductor for the semiconductor layer 101c, an In-Ga-Zn oxide layer was grown by MOCVD. When forming a film by this method, trimethylindium, trimethylgallium and and dimethyl zinc. The combination of the source gases is not limited to the above. Triethylindium or the like may be used in place of trimethylindium. Triethylgallium may be used instead of ethylgallium. Alternatively, diethyl zinc may be used.

[0211] At this stage, transistor 100 is formed.

[0212] Next, the insulating film 112 is formed. The insulating film 112 is formed by, for example, a sputtering method or a CVD method. (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD or PL In particular, the insulating film can be formed by a CVD method, preferably a Plasma It is preferable to form the film by the Zuma CVD method, since it is possible to improve the covering property. To reduce damage caused by plasma, thermal CVD, MOCVD or ALD are preferred. I wish.

[0213] After the insulating film 112 is formed, a fifth heat treatment is preferably performed. Oxygen is supplied to the semiconductor layer 101 from the film 114, etc., to reduce oxygen vacancies in the semiconductor layer 101. At this time, the oxygen desorbed from the insulating film 114 can be reduced by the and the insulating film 112, and is blocked by the lower layer than the barrier film 111 and the insulating film 114. Since the oxygen does not diffuse to the upper layer, the oxygen can be effectively trapped. The amount of oxygen that can be supplied to the conductor layer 101 can be increased, and oxygen deficiency in the semiconductor layer 101 can be reduced. The loss can be effectively reduced.

[0214] The insulating film 112 may have a stacked structure of two or more layers. In that case, for example, 112 is a two-layer laminate structure, and the lower layer is, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. Silicon, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride The upper layer may be made of aluminum, aluminum nitride, or the like. It is preferable to use a material in which hydrogen is difficult to diffuse. The semiconductor device is formed by interposing a gate insulating film 102 as an insulating film from which oxygen is released by heating, similar to the insulating film 14. Oxygen may also be supplied from the upper side of the electrolyte layer 101 .

[0215] Next, an insulating film 113 is formed. The insulating film 113 is made of, for example, silicon oxide or silicon oxynitride. Silicon, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, Aluminum nitride oxide, aluminum nitride, or the like may be used, and the layer may be a laminate or a single layer. The insulating film 113 is formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, P It can be formed by using methods such as ECVD, MBE, ALD, or PLD. In particular, when the film is formed by the CVD method, preferably the plasma CVD method, good coating properties can be obtained. In order to reduce damage caused by plasma, The thermal CVD method, the MOCVD method or the ALD method is preferred.

[0216] Next, as shown in FIG. 12B, the insulating film 113, the insulating film 112, and the gate insulating film 10 are 2, conductive layer 104a, conductive layer 104b, semiconductor layer 101b, semiconductor layer 101a and insulating layer An opening is provided in the film 114. Next, a conductive film is formed so as to fill the opening, and then a resist is formed. The unnecessary portion is removed using a resist mask, and the resist mask is removed to form the plug 121 and the plug Here, the plug 121 is formed by insulating film 113, insulating film 112, gate insulating film 113, and gate insulating film 114. An insulating film 102, a semiconductor layer 101c, a conductive layer 104a, a semiconductor layer 101b, and a semiconductor layer 101a. , which is formed so as to penetrate the insulating film 114 and the barrier film 111a and is connected to the conductive layer 151. Here, the plug 121 and the conductive layer 104a are in contact with each other at the side of the plug 121. Similarly, the plug 122 is connected to the insulating film 113, the insulating film 112, the gate insulating film 102, and the semiconductor Conductor layer 101c, conductive layer 104b, semiconductor layer 101b, semiconductor layer 101a, insulating film 114 and a conductive layer 104b formed to penetrate the barrier film 111a and connect to the conductive layer 125. is connected by contacting the side of plug 122.

[0217] Next, the insulating film 116 is formed. The insulating film 116 is made of, for example, silicon oxide or silicon oxynitride. Silicon, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, Aluminum nitride oxide, aluminum nitride, or the like may be used, and the layer may be a laminate or a single layer. The insulating film 116 is formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, P It can be formed by using methods such as ECVD, MBE, ALD, or PLD. In addition, when an organic insulating material such as an organic resin is used as the insulating film 116, Alternatively, the insulating film 116 may be formed by applying a coating method. It is preferable to perform planarization treatment on the upper surface. The materials and forming methods shown in 8 may also be used.

[0218] Next, in the same manner as above, the insulating film 116 is provided with a plug 122 reaching the plug 122. Form 3rd class.

[0219] Next, a conductive film is formed on the insulating film 116. After that, a resist is formed by the same method as above. A mask is formed, and unnecessary portions of the conductive film are removed by etching. By removing the pits, wiring 124 and the like can be formed (see FIG. 12(B)). .

[0220] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0221] When the semiconductor layer 101a and the semiconductor layer 101b are formed, the conductive film 104 is formed. Then, a resist mask is formed, the conductive film 104 is etched, and then the semiconductor layer 101a The semiconductor layer that will become the semiconductor layer 101b and the semiconductor layer that will become the semiconductor layer 101b are formed by etching. 5(A) may be used. After that, the conductive film 104 is processed again to form a conductive layer 104a and 12 and 13, a transistor 100 is formed. can have a structure as shown in FIG.

[0222] In addition, a transistor 100 having a structure different from that of the transistor 100 shown in FIG. As an example of a manufacturing method, a manufacturing method of the transistor 100 shown in FIG. will be explained.

[0223] First, a semiconductor film that will become the semiconductor layer 101 is formed on the insulating film 114, and then a resist mask or the like is applied. Then, etching is performed to form the semiconductor layer 101. Next, the gate insulating film 102 and Then, a resist mask or the like is formed, and a conductive film that becomes the gate electrode 103 is formed. Etching is carried out to form the gate electrode 103 and the gate insulating film 102.

[0224] Next, the low resistance region 171a and the low resistance region 171b are formed. The semiconductor layer has low resistance. The carrier density can be increased by, for example, doping impurities. For example, ion implantation is a method for increasing the carrier density. The element can be added by using a gas injection. Examples of elements that can be used include argon, Boron, carbon, magnesium, aluminum, silicon, phosphorus, calcium, scandium Titanium, vanadium, chromium, manganese, iron, cobalt, nickel, gallium, Manium, arsenic, yttrium, zirconium, niobium, molybdenum, indium, tin , lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. It is preferred to add one or more of them.

[0225] In such low-resistance regions, it is possible to trap unwanted hydrogen, for example. By trapping unnecessary hydrogen in the low resistance layer, the hydrogen concentration in the channel region can be reduced. As a result, good transistor characteristics can be obtained.

[0226] Next, the insulating film 112 and the insulating film 113 are formed. By the above steps, the transistor 1 shown in FIG. 00 can be created.

[0227] (Embodiment 2) In this embodiment, a semiconductor device that can be suitably used for the transistor 100 described in Embodiment 1 will be described. The oxide semiconductor will be described.

[0228] Here, as shown in FIG. 6 as an example, a semiconductor layer 101a is an oxide semiconductor, a semiconductor In this example, a semiconductor layer 101b and a semiconductor layer 101c are stacked. The oxide semiconductor that can be used for the semiconductor layer 101 may be a single layer. A structure that does not have either or both of the conductor layer 101b and the semiconductor layer 101c. You may do so.

[0229] The semiconductor layer 101b is, for example, an oxide semiconductor containing indium. For example, when b contains indium, the carrier mobility (electron mobility) increases. The semiconductor layer 101b preferably contains an element M. The element M is preferably aluminum, Gallium, yttrium, or tin. Other elements that can be used for M include The following elements are considered to be important: boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium nium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten However, there are cases where the element M may be a combination of multiple of the above elements. The element M is, for example, an element that has a high bond energy with oxygen. The bond energy of M is higher than that of indium. Alternatively, the element M may be, for example, oxide. It is an element that has the function of increasing the energy gap of a semiconductor. It is preferable that 01b contains zinc. When an oxide semiconductor contains zinc, it tends to be easily crystallized. There is a match.

[0230] However, the semiconductor layer 101b is not limited to an oxide semiconductor containing indium. Layer 101b is made of an indium-containing material, such as zinc tin oxide or gallium tin oxide. First, oxide semiconductors containing zinc, oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. It doesn't matter.

[0231] The semiconductor layer 101b is made of, for example, an oxide having a large energy gap. The energy gap of 101b is, for example, 2.5 eV or more and 4.2 eV or less, preferably The energy is preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0232] For example, the semiconductor layer 101a and the semiconductor layer 101c are made of the same material as the semiconductor layer 101b. The semiconductor layer 1 is an oxide semiconductor composed of one or more elements other than silicon. The semiconductor layers 101a and 101b are made of one or more elements other than oxygen. Since the semiconductor layer 101c is formed, the interface between the semiconductor layer 101a and the semiconductor layer 101b and In addition, an interface state is unlikely to be formed at the interface between the semiconductor layer 101b and the semiconductor layer 101c. .

[0233] The semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 101c are made of at least indium. When the semiconductor layer 101a is an In-M-Zn oxide, In and When the sum of In and M is 100 atomic %, In is preferably less than 50 atomic %. , M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is In addition, when the semiconductor layer 101b is an In-M-Zn oxide, When the sum of In and M is 100 atomic %, In is preferably 25 atomic %. ic% or more, M is less than 75 atomic %, and more preferably In is 34 atomic % In the above, M is less than 66 atomic %. In addition, the semiconductor layer 101c is an In-M-Zn oxide. In the case of a compound, when the sum of In and M is 100 atomic %, preferably In is 5 0 atomic %, M is 50 atomic % or more, and more preferably In is 25 atomic % or more. % or less, and M is 75 atomic % or more. The same type of oxide as that of the base layer 101a may be used.

[0234] The semiconductor layer 101b has a larger electron affinity than the semiconductor layers 101a and 101c. For example, the semiconductor layer 101b is made of a semiconductor layer 101a and a semiconductor The electron affinity of the layer 101c is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV More preferably, the oxide is 0.15 eV or more and 0.4 eV or less. The electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0235] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the semiconductor layer 101c contains indium gallium oxide. The Ga atom ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more. More preferably, it is set to 90% or more.

[0236] At this time, when an electric field is applied to the gate electrode, the semiconductor layer 101a, the semiconductor layer 101b, A channel is formed in the semiconductor layer 101b, which has a large electron affinity, of the conductor layer 101c.

[0237] Here, the band structure is shown in FIG. 18(A). In FIG. 18(A), uum level), the energy of the conduction band minimum of each layer (Ec), and This indicates the energy at the top of the valence band (denoted as Ev).

[0238] Here, between the semiconductor layer 101a and the semiconductor layer 101b, there is a semiconductor In some cases, the semiconductor layer 101b and the semiconductor layer 101b may have a mixed region. Between the semiconductor layer 101b and the semiconductor layer 101c, there may be a mixed region of the semiconductor layer 101b and the semiconductor layer 101c. The interfacial state density is low in the mixed region. The stack of the semiconductor layer 101c and the semiconductor layer 101b has a continuous energy distribution near the interface between the stack of the semiconductor layer 101c and the semiconductor layer 101b. (also called a continuous junction).

[0239] In FIG. 18A, the semiconductor layer 101a and the second semiconductor layer 101c have the same Ec. However, they may be different. For example, the semiconductor layer 101a The Ec of the semiconductor layer 101c may have a higher energy than that of the semiconductor layer 101b.

[0240] At this time, the electrons are not in the semiconductor layer 101a and the semiconductor layer 101c but in the semiconductor layer As described above, the electrons move mainly through the semiconductor layer 101b (see FIG. 18(B)). 1a and the interface state density at the interface between the semiconductor layer 101b and the semiconductor layer 101a. By lowering the interface state density at the interface with 101c, The movement of electrons is not hindered much, which makes it possible to increase the on-state current of the transistor. .

[0241] When the transistor has an s-channel structure, the entire semiconductor layer 101b Therefore, the thicker the semiconductor layer 101b, the larger the channel region. That is, the thicker the semiconductor layer 101b is, the higher the on-current of the transistor can be. For example, it is possible to set the thickness to 20 nm or more, preferably 40 nm or more, and more preferably 60 nm or more. More preferably, the semiconductor layer 101b may have a region having a thickness of 100 nm or more. However, since this may reduce the productivity of semiconductor devices, A semiconductor having a region preferably having a thickness of 200 nm or less, more preferably 150 nm or less. This may be called layer 101b.

[0242] In order to increase the on-current of the transistor, the thickness of the semiconductor layer 101c is small. For example, it is preferably less than 10 nm, more preferably 5 nm or less, and even more preferably 3 nm. The semiconductor layer 101c may have the following regions: The semiconductor layer 101b on which the hole is formed is doped with elements other than oxygen (hydrogen, The semiconductor layer 10 has a blocking function to prevent foreign matter (e.g., silicon) from entering the semiconductor layer 10. It is preferable that 1c has a certain thickness. For example, 0.3 nm or more, preferably The semiconductor layer 101c has a region having a thickness of 1 nm or more, and more preferably 2 nm or more. In addition, the semiconductor layer 101c can prevent outward diffusion of oxygen released from the insulating film 102, etc. In order to suppress this, it is preferable that the material has an oxygen blocking property.

[0243] In order to increase reliability, the semiconductor layer 101a is thick and the semiconductor layer 101c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 4 The semiconductor layer 101a has a thickness of 0 nm or more, and more preferably has a thickness of 60 nm or more. By increasing the thickness of the semiconductor layer 101a, the adjacent insulator and the semiconductor layer 101 It is possible to increase the distance from the interface with a to the semiconductor layer 101b in which the channel is formed. However, since the productivity of the semiconductor device may decrease, it is preferable to use a thickness of 200 nm or less. The semiconductor layer 1 has a region having a thickness of 120 nm or less, and more preferably a region having a thickness of 80 nm or less. Just use 01a.

[0244] When a large amount of hydrogen is contained in the oxide semiconductor film, the hydrogen is bonded to the oxide semiconductor. Some of the elements become donors and generate electrons, which are carriers. This causes a transistor Therefore, the threshold voltage of the oxide semiconductor film is shifted in the negative direction. After that, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film. It is preferable to remove the impurities to obtain a high purity so that the impurities are not included as much as possible.

[0245] Note that the oxide semiconductor film is dehydrated (dehydrogenated) to At the same time, oxygen may also decrease. A process of adding oxygen to an oxide to compensate for the increased oxygen deficiency caused by the oxidation process. In this specification and the like, when oxygen is supplied to an oxide semiconductor film, Alternatively, oxygen contained in the oxide semiconductor film may be stoichiometrically added. When the amount is more than the composition, it is sometimes referred to as excessive oxygen treatment.

[0246] In this manner, the oxide semiconductor film is dehydrated by dehydration treatment (dehydrogenation treatment). By removing oxygen and filling the oxygen vacancies with oxygen addition treatment, the i-type (intrinsic) or The oxide semiconductor film can be an oxide semiconductor film that is nearly i-type and is substantially i-type (intrinsic). Note that the term "substantially intrinsic" means that the number of carriers derived from donors in the oxide semiconductor film is extremely small. (close to zero), carrier density is 1×10 17 / cm 3 Below, 1×10 16 / cm 3 below , 1×10 15 / cm 3 Below, 1×10 14 / cm 3 Below, 1×10 13 / cm 3 Below , particularly preferably 8×10 11 / cm 3 less than 1×10 11 / cm 3 Not yet More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all. This means that...

[0247] In addition, a transistor including an i-type or substantially i-type oxide semiconductor film can be For example, a transistor using an oxide semiconductor film can be The drain current when the capacitor is off is 1×10 at room temperature (approximately 25°C). -18 Below A, Preferably 1 x 10 -21 A or less, more preferably 1×10-24 A or below, or 85 1×10 at °C -15 A or less, preferably 1×10 -18 A or less, more preferably 1x 10 -21 A or less. Note that the off state of a transistor is an n-channel In the case of a transistor of this type, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. In general, if the gate voltage is 1V, 2V, or 3V less than the threshold voltage, , the transistor is turned off.

[0248] The structure of the oxide semiconductor film will be described below.

[0249] Oxide semiconductor films are classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Alternatively, oxide semiconductors can be divided into crystalline oxide semiconductors and amorphous oxide semiconductors, for example. The non-single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor (Crystalline Oxide Semiconductor) film, polycrystalline oxide Semiconductor films, microcrystalline oxide semiconductor films, amorphous oxide semiconductor films, and the like. As for the semiconductors, single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, microcrystalline Oxide semiconductors.

[0250] First, we will explain the CAAC-OS membrane. These are called oxide semiconductors with axially aligned nanocrystals. It is also possible.

[0251] The CAAC-OS film is an oxide film having multiple crystal parts (also called pellets) aligned along the c-axis. It is one of the semiconductor films.

[0252] The CAAC-OS film was observed under a transmission electron microscope (TEM). Bright-field images and diffraction patterns of CAAC-OS were obtained using a 3D CT microscope. When observing the composite analytical image (also called a high-resolution TEM image), multiple pellets are identified. On the other hand, in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (gray Therefore, it is not possible to clearly confirm the boundary between the CAAC-O It can be said that the S film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0253] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When the metal atoms are observed, it can be confirmed that they are arranged in layers in the crystal part. Each layer of the CAAC-OS film is formed on a surface on which the film is to be formed (also called a surface on which the film is to be formed) or on a concave surface on the top surface. The shape reflects a convexity, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0254] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0255] FIG. 19(a) is a cross-sectional TEM image of the CAAC-OS film. This is a cross-sectional TEM image of 19(a) enlarged, with the atomic arrangement emphasized for ease of understanding. The tone is displayed.

[0256] Figure 19(c) shows the area surrounded by a circle (diameter approximately 4 mm) between AO and A' in Figure 19(a). From Fig. 19(c), it is clear that the c-axis orientation is In addition, the c-axis orientation is different between the A-O and O-A' sections, so the different graphs are formed. The c-axis angles between the AOs are 14.3° and 16. 6°, 26.4°, and so on. Similarly, OA Between these, the c-axis angle gradually changes to -18.3°, -17.6°, and -15.9°. It is clear that things are changing.

[0257] In addition, when electron diffraction is performed on the CAAC-OS film, spots (bright points) indicating orientation are observed. For example, a thickness of 1 nm to 30 nm is observed on the top surface of the CAAC-OS film. When electron diffraction using an electron beam (also called nanobeam electron diffraction) is performed, spots are observed. (See FIG. 20(A)).

[0258] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that...

[0259] Most of the crystals in the CAAC-OS film are cubic with a side length of less than 100 nm. The size is small enough to fit inside the body. Therefore, the crystal part in the CAAC-OS film has a side length of 10 This includes sizes that fit within a cube of less than 3 nm, 5 nm, or 5 nm. However, multiple crystals in the CAAC-OS film are connected to form a single large crystal domain. For example, in a planar TEM image, 2 More than 5μm 2 More than or equal to 1000μm 2 In some cases, crystal regions having more than this amount may be observed.

[0260] X-ray diffraction (XRD) of CAAC-OS film When the structure was analyzed using the device, for example, CAAC-OS with InGaZnO4 crystals was In the out-of-plane analysis of the film, the diffraction angle (2θ) peaked at around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that it is oriented in a roughly vertical direction.

[0261] On the other hand, in-p X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the lane method, a peak may appear at 2θ around 56°. is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to Even when φ is fixed at around 56° and scanned, no clear peak appears.

[0262] From the above, it is considered that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is in a plane parallel to the ab plane of the crystal.

[0263] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization process such as a heat treatment. As described above, the c-axis of the crystal is aligned to the surface on which the CAAC-OS film is to be formed. For example, in the CAAC-OS film, When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the face or top surface normal vector.

[0264] In addition, the distribution of the c-axis oriented crystal parts in the CAAC-OS film may not be uniform. For example, the crystals in the CAAC-OS film grow from the top surface of the CAAC-OS film. Therefore, when the crystal is formed, the region near the top surface has more c-axis oriented crystals than the region near the surface on which the crystal is formed. The proportion of the impurity part may be increased. The region where the ZnO was added was altered, and regions with different proportions of c-axis oriented crystals were formed. This may also occur.

[0265] In addition, the out-of-plane crystal structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have the 2θ value of about 31°. It is preferable that the spectrum shows a peak at 2θ of about 36° and does not show a peak at 2θ of about 36°.

[0266] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is preferably made of silicon or a transition metal element other than the main component of the oxide semiconductor film. The elements that bond to oxygen stronger than the metal elements that form the oxide semiconductor film, such as Zn, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Since the diameter (or molecular radius) of the ions is large, when the ions are contained inside the oxide semiconductor film, the oxide semiconductor film The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement of the oxide semiconductor film, which leads to deterioration of the crystallinity. Pure materials may act as carrier traps or carrier generation sources.

[0267] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in semiconductor films act as carrier traps and trap hydrogen. This can become a carrier generation source.

[0268] The low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. Since the film has a small carrier generation source, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics (noise) in which the threshold voltage is negative. It is also called "marine". It is rare for it to become "high purity genuine" or "substantially high purity". The intrinsic oxide semiconductor film has few carrier traps. Transistors using the film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time is long and the charge may behave as if it were a fixed charge. In addition, a transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. There may be cases where this occurs.

[0269] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. Gender variation is small.

[0270] Figure 36(A) shows a high-resolution T The TEM image is shown. For high-resolution TEM imaging, spherical aberration correction is used. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. The observation was performed using, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. This can be done by, etc.

[0271] FIG. 36(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 36(A). From FIG. 36(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is the same as that of the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed). The surface on which the CAAC-OS is formed or the top surface of the CAAC-OS reflects the unevenness of the surface on which the CAAC-OS is formed or the top surface of the CAAC-OS.

[0272] As shown in Figure 36(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 36(B) and Figure 36(C). Therefore, the size of each pellet is about 1 nm to 3 nm, and the size of each pellet is about 1 nm to 3 nm. It can be seen that the size of the gap caused by the inclination of the The zeolites can also be referred to as nanocrystals (nc).

[0273] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 36(D)). The inclination between the pellets observed in FIG. 36(C) The location where the crack occurs corresponds to an area 5161 shown in FIG.

[0274] FIG. 37(A) shows the Cs Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in FIG. 37(A). The enlarged Cs-corrected high-resolution TEM images are shown in Fig. 37(B), Fig. 37(C) and Fig. 37(D), respectively. 37(D). From Fig. 37(B), Fig. 37(C) and Fig. 37(D), the pellet is It can be seen that the metal atoms are arranged in triangular, tetragonal or hexagonal shapes. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0275] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When the structure is analyzed using the out-of-plane method, the result is as shown in Figure 38(A). A peak may appear at a diffraction angle (2θ) of about 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0276] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0277] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In It is assigned to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. 38(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ shift is When scanning was performed, the peaks attributable to the crystal plane equivalent to the (110) plane were as shown in FIG. Therefore, from the structural analysis using XRD, CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0278] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe with a diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 39(A) is obtained. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, even with electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately aligned on the surface to be formed or the upper surface. On the other hand, the same sample was probed perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm is incident is shown in FIG. (B) shows a ring-shaped diffraction pattern. Therefore, by electron diffraction, It is seen that the a-axis and b-axis of the pellets contained in the CAAC-OS have no orientation. In addition, the first ring in FIG. 39(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and other factors. The second ring in Figure 39(B) This is thought to be due to the (110) plane, etc.

[0279] Next, the polycrystalline oxide semiconductor film will be described.

[0280] In the polycrystalline oxide semiconductor film, crystal grains can be confirmed in the TEM image. The crystal grains contained in the crystalline oxide semiconductor film are, for example, 2 nm to 3 nm in a TEM image. 00 nm or less, 3 nm to 100 nm or 5 nm to 50 nm. In addition, in the case of a polycrystalline oxide semiconductor film, crystal grain boundaries cannot be confirmed in the TEM images. There may be cases where this occurs.

[0281] The polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientation between the plurality of crystal grains is In addition, the positions of the crystals in the polycrystalline oxide semiconductor film may differ from each other. When structural analysis was performed, for example, the ou of a polycrystalline oxide semiconductor film having InGaZnO4 crystals was In the t-of-plane analysis, there was a peak at 2θ near 31° and a peak at 2θ near 36°. or other peaks may appear.

[0282] A polycrystalline oxide semiconductor film has high crystallinity and therefore may have high electron mobility. Therefore, a transistor using a polycrystalline oxide semiconductor film has high field-effect mobility. However, in the polycrystalline oxide semiconductor film, impurities may be segregated at crystal grain boundaries. The grain boundaries of the polycrystalline oxide semiconductor film become defect states. Since the oxide semiconductor film may become a carrier trap or a carrier generation source, The transistors using the CAAC-OS film showed a small change in electrical characteristics compared to the transistors using the CAAC-OS film. may result in a transistor with low reliability.

[0283] Next, a microcrystalline oxide semiconductor film will be described.

[0284] In the TEM image of the microcrystalline oxide semiconductor film, crystal parts can be clearly seen. The crystal parts contained in the microcrystalline oxide semiconductor film may have a size of 1 nm or more and 100 nm or more. In particular, the size of the particles is between 1 nm and 10 nm. Nanocrystals (nc) are microcrystals with a diameter of 1 to 3 nm or less. The oxide semiconductor film having nc-OS (nanocrystalline O The nc-OS film is called a T In EM images, the grain boundaries may not be clearly visible. It is possible that the origin of the pellets in CAAC-OS is the same. The crystalline part of nc-OS is sometimes called a pellet.

[0285] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, when X-rays with a diameter larger than the crystal part (pellet) are irradiated onto the nc-OS film, When structural analysis is performed using the XRD device used, the out-of-plane method In the case of the nc-OS film, no peak indicating a crystal plane was detected. Electron diffraction using an electron beam with a large probe diameter (e.g., 50 nm or more) (selected area electron diffraction) ) results in a halo-like diffraction pattern. For the OS film, an electron beam with a probe diameter close to or smaller than the pellet size is used. When nanobeam electron diffraction was performed on the nc-OS film, spots were observed. When performing electron beam diffraction, a circular (ring-shaped) area of ​​high brightness is observed. In addition, multiple spots may be observed within a ring-shaped area (Figure 20). See (B). ).

[0286] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0287] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, the crystal orientation is not regular between different crystal parts. The OS film has a higher density of defect states than the CAAC-OS film.

[0288] Therefore, the nc-OS film may have a higher carrier density than the CAAC-OS film. An oxide semiconductor film having a high carrier density may have high electron mobility. In some cases, a transistor using an nc-OS film has high field-effect mobility. The nc-OS film has a higher defect density than the CAAC-OS film, which leads to carrier transport. Therefore, the transistor using the nc-OS film is Compared to transistors using OS films, the electrical characteristics fluctuate greatly and the reliability is low. However, the nc-OS film can be formed even if it contains a relatively large amount of impurities. Therefore, it is easier to form than the CAAC-OS film, and is preferably used depending on the application. Therefore, a semiconductor having a transistor using an nc-OS film can be The devices may be capable of being manufactured productively.

[0289] Next, the amorphous oxide semiconductor film will be described.

[0290] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state like quartz.

[0291] In the amorphous oxide semiconductor film, no crystal parts can be confirmed in a TEM image.

[0292] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of- In the plane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a semiconductor film, a halo pattern is observed. When nanobeam electron diffraction is performed on a semiconductor film, no spots are observed, and a halo pattern is observed. is observed.

[0293] The amorphous oxide semiconductor film is an oxide semiconductor film containing impurities such as hydrogen at a high concentration. In addition, the amorphous oxide semiconductor film has a high density of defect states.

[0294] An oxide semiconductor film having a high impurity concentration and a high density of defect states has carrier traps and The oxide semiconductor film is the most common source of CO2 generation.

[0295] Therefore, the amorphous oxide semiconductor film has a higher carrier density than the nc-OS film. Therefore, a transistor using an amorphous oxide semiconductor film may have a normally Therefore, it is difficult to obtain normally-on electrical characteristics from transistors that require normally-on electrical characteristics. The amorphous oxide semiconductor film may be preferably used as a photoresist. Therefore, the number of carrier traps may increase due to the high temperature. The transistors using the CAAC-OS film and the nc-OS film had the following characteristics: This results in a transistor with large fluctuations in electrical characteristics and low reliability.

[0296] Note that the oxide semiconductor film has a structure that exhibits physical properties intermediate between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may be used, particularly in the case of an amorphous like oxide film. Amorphous-like Oxide Semiconductor (a-like OS) The conductive film is called an iconductor film.

[0297] In the a-like OS film, voids are observed in the high-resolution TEM image. In addition, crystals may not be clearly visible in high-resolution TEM images. The a-like OS film has regions where crystals are visible and regions where no crystals are visible. Crystallization occurs when a small amount of electrons is irradiated, which is the level observed in TEM observations, and the growth of the crystals can be seen. On the other hand, in the case of a good quality nc-OS film, the amount of TEM observation is small. Almost no crystallization due to electron irradiation was observed.

[0298] The size of the crystals in the a-like OS film and the nc-OS film was measured using a high-resolution This can be done using TEM images. For example, InGaZnO4 crystals have a layered structure. InGaZnO4, there are two Ga-Zn-O layers between the In-O layers. The device has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned along the c-axis. It has a layered structure. Therefore, the spacing between adjacent layers is (009) The lattice spacing (also called the d value) of m. Therefore, focusing on the lattice fringes in the high-resolution TEM image, In the area where the spacing is 0.28 nm or more and 0.30 nm or less, each lattice fringe is In It corresponds to the ab plane of the GaZnO4 crystal.

[0299] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0300] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Sample B) and CAAC-OS (sample C) are prepared. The sample in is also an In-Ga-Zn oxide.

[0301] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0302] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0303] Figure 40 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystal part of eOS becomes larger according to the cumulative dose of electron irradiation. As shown by (1) in Figure 40, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2×10 in size, but the cumulative irradiation dose was 4.2×10 8 e - / nm 2On the other hand, in the nc-OS, the size of the nanoparticles grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in Fig. 40, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are about 1.4 nm and 2.1 nm, respectively. I realize something.

[0304] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. In other words, a-like OS is not seen in nc-OS and CAAC-OS. It can be seen that compared with S, it has a less stable structure.

[0305] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0306] In addition, the density of an oxide semiconductor film may differ depending on the structure. If the composition of the conductive film is known, the density can be determined by comparing it with the density of a single crystal with the same composition. For example, the density of a single crystal is The density of the -like OS film is 78.6% or more and less than 92.3%. The density of the nc-OS film and the CAAC-OS film is 92.3% or more of the density of the crystals. Note that an oxide semiconductor film having a density of less than 78% of the density of a single crystal is Therefore, the film formation itself is difficult.

[0307] The above will be explained using a specific example. For example, In the oxide semiconductor film that satisfies the [atomic ratio], single crystal InGaZnO with a rhombohedral crystal structure The density of 4 is 6.357g / cm 3 Therefore, for example, In:Ga:Zn=1:1: In the oxide semiconductor film that satisfies the atomic ratio of 1, the density of the a-like OS film is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1 In the oxide semiconductor film that satisfies the atomic ratio of 1:1, the density and CAAC of the nc-OS film -OS film density is 5.9g / cm 3 More than 6.3g / cm 3 It will be less than.

[0308] In some cases, single crystals of the same composition do not exist. In such cases, crystals of different compositions may be used in any ratio. By combining single crystals of the desired composition, the density corresponding to the single crystal of the desired composition can be calculated. The density of a single crystal of a desired composition varies with the ratio of the single crystals of different compositions combined. However, the density should be calculated using as few types of single crystals as possible. It is preferable to calculate the above in combination.

[0309] Next, a single crystal oxide semiconductor film will be described.

[0310] A single-crystal oxide semiconductor film has a low impurity concentration and a low density of defect states (few oxygen vacancies). ) an oxide semiconductor film. Therefore, the carrier density can be reduced. A transistor using a crystalline oxide semiconductor film rarely has normally-on electrical characteristics. In addition, since the single crystal oxide semiconductor film has a low impurity concentration and a low density of defect states, Therefore, in the case of a transistor using a single crystal oxide semiconductor film, the number of carrier traps may be reduced. The transistor has small fluctuations in electrical characteristics and is highly reliable.

[0311] Note that the oxide semiconductor film has a high density when the number of defects is small. High crystallinity increases density. In addition, the oxide semiconductor film has a low concentration of impurities such as hydrogen. The density of the single crystal oxide semiconductor film is higher than that of the CAAC-OS film. The CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. The conductor film has a higher density than the microcrystalline oxide semiconductor film. The density is higher than that of an crystalline oxide semiconductor film.

[0312] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a C The AAC-OS film may be a laminate film having two or more kinds of AAC-OS films.

[0313] <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0314] FIG. 41A shows how a CAAC-OS film is formed by a sputtering method. FIG.

[0315] The target 5130 is attached to a backing plate. A plurality of magnets are disposed at positions facing the target 5130. The magnetic field is generated by the magnet. The magnetic field of the magnet is used to increase the deposition speed. The sputtering method is called magnetron sputtering.

[0316] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d ( The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the deposition chamber is set to 0.02m or more and 0.5m or less. Most of the deposition gas (e.g., oxygen) is The chamber is filled with a gas mixture containing 5% or more by volume of nitrogen, argon, or oxygen. The pressure is controlled to be 0.1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a certain voltage to the target 5130, discharge begins and plasma is generated. It is noted that a high-density plasma region is formed near the target 5130 by the magnetic field. In the high density plasma region, the deposition gas is ionized, and ions 5101 are generated. The ions 5101 are, for example, positive oxygen ions (O + ) and argon cations (A r + ) etc.

[0317] Here, the target 5130 has a polycrystalline structure having a plurality of crystal grains, and any of the grains The crystal grains include cleavage planes. FIG. 42(A) shows an example of a cleavage plane included in a target 5130. The crystal structure of InGaZnO4 is shown in Fig. 42(A). This is the structure of an InGaZnO4 crystal. In the Ga-Zn-O layer, the oxygen atoms in each layer are arranged close to each other. It can be seen that the oxygen atom has a negative charge, and the two adjacent G Repulsion occurs between the a-Zn-O layers. As a result, the InGaZnO4 crystals are close to each other. The cleavage plane is between the two Ga-Zn-O layers.

[0318] Ions 5101 generated in the high-density plasma region are applied to the target 5130 side by the electric field. The cleavage plane is accelerated and eventually collides with the target 5130. At this time, flat or pellet-like particles are generated from the cleavage plane. Pellet 5100a and pellet 5100b, which are pellet-shaped sputtered particles, are peeled off and struck. The pellets 5100a and 5100b are the same as the pellets 5101. The impact of a collision can cause distortion of the structure.

[0319] The pellet 5100a is a flat or pellet-shaped pellet having a triangular, for example equilateral, plane. The pellet 5100b has a hexagonal, for example, regular hexagonal, planar surface. The sputtered particles are in the form of a plate or pellet. Pellet 5100b and other flat or pellet-shaped sputter particles are collectively referred to as pellet 5 The planar shape of the pellet 5100 is not limited to a triangle or a hexagon. For example, a triangle (e.g., an equilateral triangle) may have a shape that is made up of multiple triangles. In some cases, the shape may be two squares (for example, a diamond).

[0320] The thickness of the pellet 5100 is determined according to the type of deposition gas. The reason for this will be described later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferred over thick cubes. The thickness of the 5100 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably The pellet 5100 is (1) in FIG. For example, the target 51 having In-Ga-Zn oxide corresponds to the initial nucleus described in . When ions 5101 are bombarded onto the surface of the semiconductor substrate 30, the Ga-Zn-O layer, A pellet 5100 having three layers, an In-O layer and a Ga-Zn-O layer, is exfoliated. (C) shows the structure of the exfoliated pellet 5100 observed from a direction parallel to the c-axis. The plate 5100 is a nanotube having two Ga-Zn-O layers (panels) and an In-O layer (tool). It can also be called a no-size sandwich structure.

[0321] The pellet 5100 may become negatively or positively charged on its sides as it passes through the plasma. The pellet 5100 may, for example, be negatively charged due to the oxygen atoms located on its sides. The sides of the particles have the same polarity, causing repulsion between the charges, forming a flat or pellet-like shape. It is possible to maintain the shape of the In-Ga-Zn In the case of oxides, the oxygen atoms bonded to the indium atoms may be negatively charged. Or, an oxygen atom bonded to an indium atom, a gallium atom, or a zinc atom is negatively charged. In addition, when the pellet 5100 passes through the plasma, it may be possible that the pellet 5100 may be oxidized by the impurities in the plasma. When it grows by combining with other atoms such as tungsten, gallium, zinc, and oxygen, The difference in size between (2) and (1) in Figure 40 above corresponds to the growth in the plasma. Here, when the substrate 5120 is at room temperature, the pellets on the substrate 5120 Since the growth of 5100 is difficult to occur, it becomes nc-OS (see Figure 41(B)). Since the film can be formed in a short time, it is possible to form a film of nc-OS even on a large-area substrate (5120). In order to grow the pellet 5100 in plasma, the sputtering method is used. It is effective to increase the film formation power in the pellet 51. The structure of 00 can be stabilized.

[0322] As shown in FIG. 41(A) and FIG. 41(B), for example, a pellet 5100 is It flies like a kite through the air and flutters up to the top of the substrate 5120. Pellet 51 Since the 00 is electrically charged, it approaches an area where other pellets 5100 are already deposited. Here, on the upper surface of the substrate 5120, a repulsive force is generated in a direction parallel to the upper surface of the substrate 5120. In addition, the substrate 5120 and the target 51 Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is disposed on the upper surface of the substrate 5120 in a magnetic The force (Lorentz force) is exerted by the action of the electric field and the electric current. This is explained by Fleming's This can be understood using the left-hand rule.

[0323] The pellet 5100 has a large mass compared to a single atom. In order to move the object, it is important to apply some kind of force from the outside. It is possible that the force is generated by the action of a magnetic field and a current. In order to provide sufficient force to move the top surface of the substrate 5120, The magnetic field parallel to the upper surface of the plate 5120 is 10 G or more, preferably 20 G or more, and more preferably It is preferable to provide an area where the resistance is 30 G or more, and more preferably 50 G or more. On the upper surface of the substrate 5120, a magnetic field parallel to the upper surface of the substrate 5120 is applied to the upper surface of the substrate 5120. At least 1.5 times, preferably at least 2 times, more preferably at least 3 times the magnetic field perpendicular to the surface More preferably, a region in which the difference is 5 times or more is provided.

[0324] At this time, the magnet and the substrate 5120 move or rotate relatively to each other. Thus, the orientation of the horizontal magnetic field on the top surface of the substrate 5120 continues to change. On the upper surface of 5120, the pellet 5100 is subjected to forces from various directions and is moved in various directions. Can be moved.

[0325] Also, when the substrate 5120 is heated as shown in FIG. The resistance due to friction between the substrate 5120 and the substrate 5120 is small. The pellet 5100 glides over the upper surface of the substrate 5120. The movement occurs with the flat surface facing the substrate 5120. When the pellet 5100 reaches the side of the pellet, the sides of the pellet 5100 are joined together. The oxygen atom on the side of 0 is removed. The removed oxygen atom causes the acid in CAAC-OS to be Since the electron vacancies may be filled, the CAAC-OS has a low defect level density. The temperature of the upper surface of 5120 is, for example, 100°C or more and less than 500°C, 150°C or more and less than 450°C. 170° C. or more and less than 400° C. Therefore, Even in this case, it is possible to form a CAAC-OS film.

[0326] In addition, the pellet 5100 is heated on the substrate 5120, whereby the atoms are rearranged, The structural distortion caused by the collision of the ions 5101 is relieved. The pellet 51 with the distortion relieved is shown in FIG. 00 is almost a single crystal. Pellet 5100 is almost a single crystal, Even if the pellets 5100 are heated after being bonded to each other, the pellets 5100 themselves do not expand or contract. Therefore, the gaps between the pellets 5100 widen, causing the grains to It does not form defects such as boundaries or crevasse formation.

[0327] In addition, the CAAC-OS is not made of a single crystal oxide semiconductor. The aggregates of Pellet 5100 (nano crystals) are arranged like piles of bricks or blocks. In addition, there are no grain boundaries between the pellets 5100. The CAAC-OS was deformed, such as shrinking, due to heating during film formation, heating after film formation, or bending. Even in cases where the material is not fully deformed, it is possible to relieve local stress or release strain. This structure is suitable for use in flexible semiconductor devices. The resulting arrangement resembles randomly stacked nanocrystals.

[0328] When the target 5130 is sputtered by ions 5101, not only the pellet 5100 but also However, zinc oxide may peel off. Zinc oxide is lighter than pellet 5100, so Therefore, it will reach the upper surface of the substrate 5120 first. A zinc oxide layer 5102 having a thickness of 0.5 nm to 2 nm is formed. A schematic cross-sectional view is shown in Figure 43.

[0329] As shown in FIG. 43(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are piled up. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, it slides on pellet 5105b. In another aspect of 5a, a plurality of particles 5103 detached from the target along with zinc oxide. However, due to heating from the substrate 5120, it is crystallized to form a region 5105a1. The particles 5103 may include oxygen, zinc, indium, and gallium, among others.

[0330] As shown in FIG. 43(B), the region 5105a1 is integrated with the pellet 5105a. The pellet 5105c is formed by cutting the pellet 5105a2. It is arranged so as to be in contact with another side surface of 105b.

[0331] Next, as shown in FIG. 43(C), a pellet 5105d is further formed on the pellet 5105a2. and pellet 5105b, and then pellet 5105a2 and pellet 51 It slides on the pellet 5105b. It also slides towards the other side of the pellet 5105c. The pellet 5105 e slides on the zinc oxide layer 5102 .

[0332] As shown in FIG. 43(D), the pellet 5105d has a side surface similar to that of the pellet 510. The pellet 5105e is arranged so that its side surface is in contact with the pellet 5105a. Also, the other side of the pellet 5105d is arranged so as to contact the other side of the pellet 5105c. In the process, a plurality of particles 5103 peeled off from the target 5130 together with zinc oxide are deposited on the substrate. Heat from 5120 causes crystallization, forming region 5105d1.

[0333] As described above, the piled up pellets are arranged so that they come into contact with each other, and the pellets are formed on the side surfaces. As a result of this growth, a CAAC-OS is formed on the substrate 5120. The pellets of C-OS are larger than those of nc-OS. The difference in size between (1) and (2) corresponds to the growth that occurred after deposition.

[0334] In addition, the gaps between the pellets become extremely small, so that one large pellet is formed. One large pellet may have a single crystal structure. For example, The thickness is 10 nm or more and 200 nm or less, or 15 nm or more and 100 nm or less, as viewed from the top surface; or In some cases, the thickness may be between 20 nm and 50 nm. In some cases, the channel formation region of a nitride semiconductor fits into a single large pellet. In other words, the region having a single crystal structure can be used as a channel forming region. As the size of the gate increases, the region having a single crystal structure becomes the channel formation region of the transistor, In some cases, they can be used as source and drain regions.

[0335] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. By doing so, it may be possible to improve the frequency characteristics of the transistor.

[0336] Based on the above model, it is considered that the pellet 5100 accumulates on the substrate 5120. It is possible to form a CAAC-OS film even if the surface on which the film is to be formed does not have a crystalline structure. This indicates that the growth mechanism is different from epitaxial growth. C-OS does not require laser crystallization and can form a uniform film even on large glass substrates. For example, if the structure of the upper surface (formation surface) of the substrate 5120 is an amorphous structure (e.g., non-crystalline structure), It is possible to form a CAAC-OS film even on a substrate made of amorphous silicon oxide.

[0337] In addition, the CAAC-OS can be used even if the upper surface of the substrate 5120 on which the formation is to be performed is uneven. For example, the pellets 5100 are arranged along the shape of the upper surface of the substrate 5120. If the surface is atomically flat, the pellet 5100 will face down on a flat surface that is parallel to the ab plane. If the pellet 5100 has a uniform thickness, it is flat and has a uniform thickness. A layer with high crystallinity is formed. Then, the layer is stacked n levels (n is a natural number). By this, CAAC-OS can be obtained.

[0338] On the other hand, even if the upper surface of the substrate 5120 has unevenness, the CAAC-OS can be easily formed by the pellet 510. The structure is made up of n layers (n is a natural number) of layers with 0s arranged along the unevenness. Since the surface of the CAAC-OS is uneven, gaps may easily occur between the pellets. However, even in this case, intermolecular forces act between the pellets 5100, and unevenness may occur. The pellets are arranged so that the gaps between them are as small as possible. It is possible to obtain a CAAC-OS having high crystallinity.

[0339] Since the CAAC-OS film is formed by such a model, the sputtered particles have a thin film thickness. It is preferable that the sputtered particles are in the form of pellets. However, the surface facing the substrate 5120 may not be uniform, and the thickness and crystal orientation may not be uniform. be.

[0340] The film formation model shown above shows that a highly crystalline film can be formed even on a substrate surface with an amorphous structure. It is possible to obtain a CAAC-OS having the formula:

[0341] When an oxide semiconductor film has multiple structures, the structures can be resolved by using nanobeam electron diffraction. In some cases, analysis may be possible.

[0342] FIG. 20C shows an electron gun chamber 610, an optical system 612 below the electron gun chamber 610, and an optical system 613 below the electron gun chamber 610. 12, a sample chamber 614, an optical system 616, and a viewfinder 616. An observation room 620, a camera 618 installed in the observation room 620, and a film below the observation room 620. The transmission electron diffraction measurement apparatus has a chamber 622. The camera 618 is located inside the observation chamber 620. The film chamber 622 does not necessarily have to be provided.

[0343] FIG. 20(D) shows the internal structure of the transmission electron diffraction measurement device shown in FIG. 20(C). In the transmission electron diffraction measurement device, electrons emitted from an electron gun installed in the electron gun chamber 610 are The electrons are irradiated via an optical system 612 onto a substance 628 placed in a sample chamber 614. The electrons passing through 28 are guided to a fluorescent screen 63 installed inside an observation chamber 620 via an optical system 616. 2. On the fluorescent screen 632, a pattern appears according to the intensity of the incident electrons. A transmission electron diffraction pattern can be measured.

[0344] The camera 618 is installed facing the fluorescent screen 632 and captures the pattern that appears on the fluorescent screen 632. The center of the lens of the camera 618 and the center of the fluorescent screen 632 can be used to capture the image. The angle between the straight line passing through the center and the upper surface of the fluorescent screen 632 is, for example, 15° to 80°. , 30° to 75° or 45° to 70°. The smaller the angle, the Transmission electron diffraction patterns taken with MERA 618 are highly distorted. If the angle is known, it is possible to correct distortions in the obtained transmission electron diffraction pattern. There are cases where the camera 618 may be installed in the film chamber 622. For example, The camera 618 is installed in the film chamber 622 so as to face the direction of incidence of the electrons 624. In this case, a transmission electron diffraction pattern with little distortion is captured from the rear surface of the fluorescent screen 632. It is possible.

[0345] In the sample chamber 614, a holder for fixing a substance 628 which is a sample is installed. The holder is constructed to be transparent to electrons passing through the material 628. For example, the holder may have a function of moving the substance 628 in the X-axis, Y-axis, Z-axis, etc. The movement function may be, for example, 1 nm to 10 nm, 5 nm to 50 nm, or 10 nm or more. In ranges such as 100nm or less, 50nm to 500nm, 100nm to 1μm, etc. The ranges are determined by the structure of the material 628. Just set it as:

[0346] Next, the transmission electron diffraction pattern of the material is measured using the above-mentioned transmission electron diffraction measurement device. This article explains how to do this.

[0347] For example, as shown in FIG. 20(D), the irradiation position of the electron 624, which is a nanobeam, in the material By changing the position (scanning), it is possible to observe how the structure of a material changes. In this case, if the substance 628 is a CAAC-OS film, as shown in FIG. If the material 628 is an nc-OS film, the diffraction pattern shown in FIG. A diffraction pattern like that shown in B) is observed.

[0348] By the way, even if the material 628 is a CAAC-OS film, it is partially an nc-OS film. Therefore, the quality of the CAAC-OS film can be evaluated. is the ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (CA For example, a good quality CAAC-OS film can be expressed as If so, the CAAC ratio is 50% or more, preferably 80% or more, and more preferably 90% or more. % or more, and more preferably 95% or more. The percentage of the area where CAAC is observed is denoted as the non-CAAC rate.

[0349] As an example, the film is formed immediately after (denoted as-sputtered) or in an atmosphere containing oxygen. The top surface of each sample with CAAC-OS film after the heat treatment at 450 °C in air was scanned. Transmission electron diffraction patterns were obtained while scanning the sample at a speed of 5 nm / s for 60 s. The diffraction pattern was observed while scanning, and the observed diffraction pattern was captured as still images every 0.5 seconds. The CAAC rate was calculated by converting the electron beam into the A nano-beam electron beam of 1.5 m was used. The same measurements were performed on six samples. The AC conversion rate was calculated using the average value for six samples.

[0350] The CAAC ratio in each sample is shown in FIG. The AAC ratio was 75.7% (non-CAAC ratio was 24.3%). The CAAC content of the treated CAAC-OS membrane was 85.3% (non-CAAC content was 14.7%). It can be seen that the CAAC conversion rate is higher after heat treatment at 450°C than immediately after film formation. That is, the non-CAAC ratio is reduced by heat treatment at a high temperature (e.g., 400°C or higher). In addition, the CAAC content is increased when the temperature is heated below 500°C. It can be seen that a CAAC-OS membrane with a high CAAC content can be obtained even with

[0351] Here, most of the diffraction patterns different from those of the CAAC-OS film are similar to those of the nc-OS film. The pattern was a folded pattern. In addition, the amorphous oxide semiconductor film was not observed in the measurement area. Therefore, the heat treatment could not produce a region with a structure similar to that of the nc-OS film. However, it is suggested that the structure of the neighboring domains influences the rearrangement of the CAAC domain. .

[0352] 21(B) and 21(C) show the CAAC- 21(B) and 21(C) are planar TEM images of the OS film. It can be seen that the CAAC-OS film after the 50°C heat treatment has a more homogeneous film quality. It can be seen that the film quality of the CAAC-OS film is improved by the heat treatment at a low temperature.

[0353] Using this measurement method, it is possible to analyze the structure of oxide semiconductor films with multiple structures. This may be the case.

[0354] The CAAC-OS film can be formed, for example, by the following method.

[0355] The CAAC-OS film can be formed, for example, by sputtering a polycrystalline oxide semiconductor target. The film is formed by sputtering using the RF sputtering method, D The oxide semiconductor film can be formed by a C sputtering method, an AC sputtering method, or the like. In order to improve the uniformity of the distribution, film composition distribution, or crystallinity distribution, It is more preferable to use DC sputtering or AC sputtering.

[0356] By increasing the substrate temperature during film formation, migration of sputtered particles after reaching the substrate is suppressed. Specifically, the substrate temperature is set to 100° C. or higher and 740° C. or lower, preferably 200° C. or lower. The film is formed at a temperature of 500°C or less. By increasing the substrate temperature during film formation, the sputtering particles When the sputtered particles reach the substrate, they migrate onto the substrate, causing the particles to flatten. At this time, the sputtering particles are positively charged, so the The ring particles repel each other while adhering to the substrate, so the sputtering particles are biased and non-uniform. Therefore, a CAAC-OS film having a uniform thickness can be formed without overlapping.

[0357] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0358] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. Expressed as volume percent.

[0359] Alternatively, the CAAC-OS film is formed by the following method.

[0360] First, a first oxide semiconductor film is formed to a thickness of 1 nm or more and less than 10 nm. The semiconductor film is formed by sputtering. Specifically, the substrate temperature is set to 100°C or higher. The temperature is set to 500° C. or less, preferably 150° C. to 450° C., and the oxygen ratio in the deposition gas is set to 30 % by volume or more, preferably 100% by volume.

[0361] Next, heat treatment is performed to convert the first oxide semiconductor film into a first CAAC-OS film having high crystallinity. The temperature of the heat treatment is 350°C or higher and 740°C or lower, preferably 450°C or higher and 650°C or lower. The heat treatment time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Alternatively, heat treatment is performed in an inert atmosphere, and then heat treatment is performed in an oxidizing atmosphere. By the heat treatment in the atmosphere, the impurity concentration of the first oxide semiconductor film can be reduced in a short time. On the other hand, oxygen vacancies are generated in the first oxide semiconductor film by heat treatment in an inert atmosphere. In this case, the oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere. Heat treatment can be performed at 1000 Pa or less, 100 Pa or less, 10 Pa or less, or The step of removing the oxide semiconductor film from the first oxide semiconductor film may be performed under a reduced pressure of 1 Pa or less. can be reduced in an even shorter time.

[0362] The first oxide semiconductor film has a thickness of 1 nm or more and less than 10 nm. Compared with a thickness of 0 nm or more, it can be easily crystallized by heat treatment.

[0363] Next, a second oxide semiconductor film having the same composition as the first oxide semiconductor film is formed to a thickness of 10 nm or more. The second oxide semiconductor film is formed to a thickness of 0 nm or less by a sputtering method. Specifically, the substrate temperature is set to 100° C. or higher and 500° C. or lower, preferably 150° C. or higher and 450° C. or lower. The oxygen ratio in the deposition gas is set to 30% by volume or more, preferably 100% by volume. To film.

[0364] Next, heat treatment is performed to grow a second oxide semiconductor film from the first CAAC-OS film through solid phase epitaxial growth. The second CAAC-OS film is formed with high crystallinity by the heat treatment at a temperature of 350 The temperature is from 450°C to 650°C, preferably from 450°C to 650°C. The heating time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Preferably, the heat treatment is performed in an inert atmosphere. After that, a heat treatment is performed in an oxidizing atmosphere. The impurity concentration of the nitride semiconductor film can be reduced in a short time. Oxygen vacancies may be generated in the second oxide semiconductor film by the heat treatment. The oxygen vacancies can be reduced by heat treatment in a reactive atmosphere. The pressure may be reduced to 000 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration in the second oxide semiconductor film can be reduced in a shorter time. Cut.

[0365] In this manner, a CAAC-OS film having a total thickness of 10 nm or more is formed. can be done.

[0366] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0367] (Embodiment 3) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention will be described with reference to FIG. This will be described with reference to the following.

[0368] [Circuit configuration example] In the configuration shown in the first embodiment, the transistors, wiring, and electrode connection configuration are changed. By using the semiconductor device according to one embodiment of the present invention, various circuits can be configured. An example of a circuit configuration that can be realized by using the device will be described.

[0369] [CMOS Circuits] The circuit diagram shown in FIG. 22A includes a p-channel transistor 2200 and an n-channel The transistors 2100 are connected in series and the gates of the transistors are connected together. The figure shows the configuration of an OS circuit. Note that in the figure, the transistors to which the second semiconductor material is applied are is indicated with the symbol "OS."

[0370] [Analog Switch] The circuit diagram shown in FIG. 22B shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called analog switch.

[0371] [Example of storage device] By using a transistor according to one embodiment of the present invention, the contents of the memory can be read even when power is not supplied. An example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written is shown in Figure 2. Shown in 2.

[0372] The semiconductor device shown in FIG. 22C includes a transistor 3200 using a first semiconductor material and The semiconductor device includes a transistor 3300 using a second semiconductor material and a capacitor 3400 . Note that the transistor 3300 is any of the transistors described in the above embodiments. It is possible.

[0373] In this embodiment, the transistor 3300 is a transistor having a semiconductor layer including an oxide semiconductor. The transistor 3300 has an off-state current Since the capacitance is small, it is possible to retain memory contents for a long period of time by using this. In other words, no refresh operation is required, or the frequency of refresh operations is extremely low. Since it is possible to provide a semiconductor memory device with a smaller number of elements, it is possible to sufficiently reduce power consumption. can.

[0374] In FIG. 22C, a first wiring 3001 is connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode of the transistor 3300 or The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the The other of the source electrode and the drain electrode of the transistor 3300 is a capacitor 3400. The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. and is electrically connected to

[0375] In the semiconductor device shown in FIG. 22C, the potential of the gate electrode of the transistor 3200 is held. By taking advantage of this feature, it is possible to write, store, and read information as follows: be.

[0376] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitance element 3400. That is, the gate electrode of the transistor 3200 is Then, a certain charge is applied (write). Here, two different potential levels are applied. Either a low-level charge or a high-level charge is applied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By setting the transistor 3300 in the off state, the The charge applied to the gate electrode is retained (retention).

[0377] Since the off-state current of the transistor 3300 is extremely small, the gate The charge on the electrodes is maintained for a long period of time.

[0378] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor Depending on the amount of charge held in the gate electrode of the transistor 3200, the second wiring 3002 has different potentials. In general, if the transistor 3200 is an n-channel type, then the transistor 320 The apparent threshold voltage V when a high-level charge is applied to the gate electrode of th_ H The figure shows the state when a low-level charge is applied to the gate electrode of the transistor 3200. Threshold V th_L The apparent threshold voltage is The potential of the fifth wiring 3005 required to turn on the transistor 3200 is Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L Between By setting the potential V0 at the gate electrode of the transistor 3200, the charge applied to the gate electrode of the transistor 3200 can be determined. For example, if a high level charge is applied during writing, The potential of the fifth wiring 3005 is V0 (>V th_H ), then transistor 3200 is When a low-level charge is applied, the fifth wiring 3005 is in the "ON state". The potential is V0( <V th_L ), transistor 3200 remains in the "off state" Therefore, the stored data can be read by determining the potential of the second wiring 3002. It can be seen.

[0379] When memory cells are arranged in an array, it is possible to read only the information in a desired memory cell. In this way, if the information is not read out, the state of the gate electrode The potential at which transistor 3200 is in the "off state" regardless ofth_ H A smaller potential may be applied to the fifth wiring 3005. The potential at which transistor 3200 remains "on," that is, V th_L Yo A potential larger than the potential at the fifth wiring 3005 may be applied to the fifth wiring 3005 .

[0380] The semiconductor device shown in FIG. 22D differs from the semiconductor device shown in FIG. 2 mainly in that the transistor 3200 is not provided. In this case, the same operations as above are performed to write and hold information. It is possible to create

[0381] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in a floating state and the capacitor element 3400 are electrically connected to each other. As a result, the potential of the third wiring 3003 is The amount of change in the potential of the third wiring 3003 is the potential of one of the electrodes of the capacitor 3400. (or the charge stored in the capacitor 3400).

[0382] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, The capacitance component of the third wiring 3003 is denoted by CB, and the capacitance of the third wiring 3003 before the charge is redistributed is denoted by If the potential of the third wiring 3003 after the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of one of the electrodes of the element 3400 has two states, V1 and V0 (V1>V0), The potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (=( It can be seen that this is higher than (CB×VB0+C×V0) / (CB+C)).

[0383] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. This can be done.

[0384] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cells. A transistor in which a second semiconductor material is applied is used as the transistor 3300. The transistor may be laminated on the driver circuit.

[0385] In the semiconductor device described in this embodiment, an off-state current is generated by using an oxide semiconductor in a channel formation region. By using transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is unnecessary. Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, it is possible to operate the device without power supply (although it is preferable that the potential is fixed). Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0386] In addition, the semiconductor device described in this embodiment does not require a high voltage to write data. There is no problem with element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. In other words, the problem of deterioration of the gate insulating film does not occur at all. In a physical device, there is no limit to the number of times data can be rewritten, which is a problem with conventional non-volatile memory. This will dramatically improve reliability. Furthermore, the on and off states of transistors will determine the information Since the data is written in a single bit, high speed operation can be easily achieved.

[0387] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0388] (Embodiment 4) In this embodiment, an example of a semiconductor device including a transistor according to one embodiment of the present invention will be described. FIG. 29 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. Here is one example.

[0389] The semiconductor device shown in FIG. 29 includes a capacitor 660a, a capacitor 660b, and a transistor 661a, transistor 661b, transistor 662a, and transistor 662b , an inverter 663a, an inverter 663b, a wiring BL, a wiring BLB, and a wiring W L, wiring CL, and wiring GL.

[0390] In the semiconductor device shown in FIG. 29, an inverter 663a and an inverter 663b are connected in a ring. The output of the inverter 663b is connected to the memory cell 663c, forming a flip-flop. The node from which the output signal is output is designated as node VN1, and the output signal of inverter 663a is output. The node VN2 is the node where the memory cells are arranged in a matrix. A memory device (memory cell array) can be configured.

[0391] One of the source and drain of the transistor 662a is electrically connected to the wiring BL. The other drain is electrically connected to a node VN1, and the gate is electrically connected to a wiring WL. One of the source and drain of the transistor 662b is electrically connected to the node VN2. The other of the source and drain is electrically connected to the wiring BLB, and the gate is electrically connected to the wiring WL. To be continued.

[0392] One of the source and drain of the transistor 661a is electrically connected to the node VN1. The other of the source and drain is electrically connected to one electrode of the capacitor 660a, and the gate is connected to a wiring GL. Here, the other of the source and drain of the transistor 661a is A node between one electrode of the capacitor 660a and the transistor 660 is referred to as a node NVN1. One of the source and drain of 661b is electrically connected to the node VN2. The other electrode of the capacitor 660b is electrically connected to one electrode of the capacitor 660b, and the gate of the capacitor 660b is electrically connected to the wiring GL. Here, the other of the source and drain of the transistor 661b and the capacitance element 660 The node between one electrode of b and is called node NVN2.

[0393] The other electrode of the capacitor 660a is electrically connected to the wiring CL. One electrode is electrically connected to the wiring CL.

[0394] The conductive state or non-conductive state of the transistor 662a and the transistor 662b is selected as follows: The potential can be controlled by applying a potential to the wiring WL. The selection of the conductive state or non-conductive state of the transistor 661b is controlled by the potential applied to the wiring GL. It is possible.

[0395] The writing, holding and reading of the memory cell shown in FIG. 29 will be described below.

[0396] When writing, first, a voltage corresponding to data 0 or data 1 is applied to the wiring BL and wiring BLB. Apply a voltage.

[0397] For example, if you want to write data 1, set the line BL to a high-level power supply potential (VDD), The wiring BLB is set to the ground potential. Next, the transistor 662a and the transistor 6 A potential (VH) equal to or higher than the potential obtained by adding VDD to the threshold voltage of 62b is applied.

[0398] Next, the potential of the wiring WL is set to the threshold voltage of the transistor 662a and the transistor 662b. By setting it to less than 1, the data 1 written to the flip-flop will be held.

[0399] When reading, the wiring BL and the wiring BLB are set to VDD in advance. Next, the wiring WL By applying VH to the BL line, the BL line remains at VDD, but the BLB line is turned on by the transistor. The line BL is discharged through the inverter 662a and the inverter 663a to the ground potential. The potential difference between the line BLB and the line BLB is amplified by a sense amplifier (not shown). Data 1 can be read.

[0400] If you want to write data 0, set the line BL to ground potential and the line BLB to VDD. Then, VH is applied to the wiring WL. a, the flip-flop is written by making the transistor 662b lower than the threshold voltage. When reading, the data 0 is held by setting the wiring BL and wiring BLB to VD D, and by applying VH to the wiring WL, the wiring BLB remains at VDD, but The line BL is discharged through the transistor 662b and the inverter 663b to the ground potential. The potential difference between the wiring BL and the wiring BLB is amplified by a sense amplifier and maintained. The stored data, 0, can be read out.

[0401] Therefore, the semiconductor device shown in FIG. 29 is a so-called SRAM (Static Random Access Memory). SRAM functions as a high-speed access memory (HSRAM). Since data is retained by the EEPROM, no refresh operation is required. Power consumption can be reduced. In addition, since no capacitance element is used in the flip-flop, Therefore, it is suitable for applications requiring high speed operation.

[0402] In addition, in the semiconductor device shown in FIG. 29, Data can be written to the node NVN1. Similarly, the transistor 661b It is possible to write data from node VN2 to node NVN2 via The received data sets the transistor 661a or the transistor 661b in a non-conductive state. For example, even if the supply of the power supply potential is stopped, the nodes VN1 and In some cases, the data of node VN1 and node VN2 can be preserved.

[0403] Unlike conventional SRAMs, in which data is lost immediately when the power supply voltage is stopped, The semiconductor device shown in FIG. 1 can retain data even after the supply of power supply potential is stopped. By appropriately turning on or off the power supply potential, a semiconductor device with low power consumption can be realized. For example, by using the semiconductor device shown in FIG. 29 for the memory area of ​​the CPU, It is also possible to reduce the power consumption of the PU.

[0404] The period during which data is held at the nodes NVN1 and NVN2 is determined by the transistor It can be seen that the change occurs depending on the off-current of the transistor 661a and the transistor 661b. Therefore, in order to extend the data retention period, the transistor 661a and the transistor A transistor with low off-state current may be used for 661b. The capacitance of capacitor 660a and capacitor 660b should be increased.

[0405] For example, the transistor 100 and the capacitor 150 described in Embodiment 1 may be If the capacitor 661a and the capacitor 660a are used as the Similarly, the transistor 100 and the capacitor 150 When the transistor 661b and the capacitor 660b are used, a long Therefore, the data can be held for a long period of time. For transistor 661b, see the description of transistor 100. In addition, the capacitance elements 660a and 660b are the same as those of the capacitance element 150. Please refer to the description in the section on the above.

[0406] As described in the above embodiment, the transistor 100 is provided with the plug 121 and the plug By using the delay 122, the occupancy of the elements including the transistor 100 and the capacitance element 150 can be reduced. The area can be reduced. b, the capacitance element 660a and the capacitance element 660b are the transistors described in the above embodiment. The capacitor 100 and the capacitor element 150 can be used. Therefore, the semiconductor device shown in FIG. It can be fabricated without significantly increasing the area occupied by the SRAM compared to conventional SRAM. The transistor 662a, the transistor 662b, and the inverter 663a may include The transistors included in the inverter 663b and the transistors included in the inverter 663c are For details, see the description of the transistor 130.

[0407] As described above, the semiconductor device according to one embodiment of the present invention has high performance relative to the area it occupies. It is also clear that the semiconductor device has high productivity.

[0408] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0409] (Embodiment 5) In this embodiment, a R The F tag will be explained with reference to FIG.

[0410] The RF tag in this embodiment has a memory circuit inside and stores necessary information in the memory circuit. The information is stored in the memory, and information is exchanged with the outside world using a non-contact means, for example, wireless communication. Due to these characteristics, RF tags can identify items by reading their individual information. It can be used for individual authentication systems. Extremely high reliability is required. Here, the RF tag is, for example, an ID given to an item. It may be an RFID tag that recognizes the identifying information to be revealed.

[0411] The structure of an RF tag will be described with reference to Fig. 23. Fig. 23 shows an example of the structure of an RF tag. FIG.

[0412] As shown in FIG. 23, an RF tag 800 includes a communicator 801 (such as an interrogator or a reader / writer). An antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 804, and a 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor having the rectifying effect included in the demodulation circuit 807 is sufficiently suppressed. A material capable of suppressing the electric field, such as an oxide semiconductor, may be used. This suppresses the deterioration of the rectification effect caused by the reverse current and prevents the output of the demodulation circuit from becoming saturated. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linear. The data transmission format is a pair of coils arranged facing each other and communication is carried out by mutual induction. The electromagnetic coupling method uses electromagnetic fields to communicate, the electromagnetic induction method uses radio waves to communicate, The RF tag 800 shown in this embodiment is compatible with any of these three methods. It can also be used in formulas.

[0413] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 805 is a filter for adjusting an input AC signal generated by receiving a radio signal through the antenna 804. For example, the current is rectified by half-wave double voltage rectification, and the rectified signal is averaged by a capacitive element provided in the latter stage. The rectifier circuit 805 is a circuit for smoothing the input potential. A limiter circuit may be provided on the output side or on the input side. When the internally generated voltage is large, power above a certain level is not input to the downstream circuit. This is a circuit for controlling the above.

[0414] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0415] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0416] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds input information, such as a row decoder, a column decoder, a memory area, etc. The ROM 811 stores a unique number (ID) and outputs the information according to the processing. This is a circuit for doing so.

[0417] It should be noted that the above-mentioned circuits can be appropriately selected or omitted as necessary.

[0418] Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when the power supply is cut off. Furthermore, the memory circuit according to one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required for writing is significantly smaller than that of conventional non-volatile memory, It is also possible to eliminate the difference in maximum communication distance when reading and writing data. In this way, it is possible to suppress malfunctions or erroneous writing caused by a power shortage when writing data. This can be done.

[0419] The memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to each RF tag that is produced, only good products that are shipped will be assigned a unique number. This means that the unique numbers of products will be discontinuous after shipment. This makes it easier to manage customers' accounts after products are shipped.

[0420] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0421] (Embodiment 6) In this embodiment, at least the transistors described in the embodiment can be used. Next, a CPU including the storage device described in the above embodiment will be described.

[0422] FIG. 24 shows a CPU using the transistors described in the above embodiments at least in part. FIG. 2 is a block diagram showing an example of a configuration.

[0423] The CPU shown in FIG. 24 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. tic logic unit, ALU controller 1192, instruction action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI Substrates, glass substrates, etc. are used. ROM 1199 and ROM interface 1189 Of course, the CPU shown in FIG. 24 can be simplified in its configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 24 is regarded as one core, and the core is divided into multiple The CPU may also be configured to include a processor core and each core may operate in parallel. The number of bits that can be handled by a computing circuit or a data bus is, for example, 8 bits, 16 bits, 32 bits, 6 It can be 4 bits, etc.

[0424] The instructions input to the CPU via the bus interface 1198 are The signal is input to the input decoder 1193, decoded, and then passed to the ALU controller 1192, the input The interrupt controller 1194, the register controller 1197, the timing controller It is entered into RA 1195.

[0425] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to control the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it. It generates an address and reads or writes register 1196 depending on the CPU state. .

[0426] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. It is supplied to the various circuits listed above.

[0427] In the CPU shown in FIG. 24, a memory cell is provided in the register 1196. The transistors shown in the above embodiments can be used as memory cells of the memory cell 1196. Cut.

[0428] In the CPU shown in FIG. 24, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or the capacity Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. When data retention in the capacitive element is selected, rewriting data to the capacitive element The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0429] FIG. 25 is a circuit diagram of an example of a memory element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 in which memory data is not volatile, a switch 1203, a switch 1204, and a logic The circuit includes an element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as necessary. The transistor 1209 is an oxide semiconductor. It is preferable that the transistor has a channel formed in the semiconductor layer.

[0430] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory element 1200 is stopped, the transistor 12 The gate of 09 is supplied with ground potential (0V) or a potential that turns off transistor 1209. For example, the gate of the transistor 1209 is connected to the load such as a resistor. It is configured to be grounded.

[0431] The switch 1203 is a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 1214 of the switch 1203 is used. The terminal corresponds to one of the source and drain of the transistor 1213, and the first terminal of the switch 1203. The terminal 2 corresponds to the other of the source and drain of the transistor 1213, and the terminal 2 corresponds to the other of the source and drain of the switch 1203. The first terminal and the second terminal are connected to each other by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the terminals of the transistor 1213 (i.e., the on or off state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of a transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the The switch 1204 is connected to the gate of the transistor 1214. A control signal RD is input to the first terminal and the second terminal to establish or break continuity (i.e., The on or off state of transistor 1214 is selected.

[0432] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The other of the two is electrically connected to the gate of the transistor 1210. One of the source and drain of the transistor 1210 is connected to a low power supply voltage The other is electrically connected to a wiring (e.g., a GND line) that can supply a switch voltage. The first terminal of the transistor 1203 (one of the source and drain of the transistor 1213) is electrically connected to the The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the other terminal of the switch 1204 (the source and drain of the transistor 1214) The second terminal of the switch 1204 (the first terminal of the transistor 1214) is electrically connected to the The other of the source and drain is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) a first terminal of the switch 1204 (one of the source and drain of the transistor 1214) one of a pair of electrodes of a capacitor 1207, and an input terminal of a logic element 1206. , are electrically connected. Here, the connection point is designated as node M1. The other electrode of the pair may be configured to have a constant potential input thereto. For example, It can be configured so that the power supply potential (GND, etc.) or high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a power supply that can supply a low power potential. The pair of electrodes of the capacitor 1208 are electrically connected to a wiring (for example, a GND line). The other terminal may be configured to receive a constant potential. For example, a low power supply potential (GND A power supply potential (VDD, etc.) or a high power supply potential (VDD, etc.) can be input to the capacitance element 12. The other of the pair of electrodes of 08 is a wiring that can supply a low power supply potential (for example, GN D line).

[0433] The capacitors 1207 and 1208 are parasitic capacitances of transistors and wirings, etc. It is also possible to omit it by making active use of the above.

[0434] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal R, which is different from the control signal WE. D selects the conductive or non-conductive state between the first and second terminals, and When the first terminal and the second terminal of the switch are in a conductive state, the first terminal of the other switch and There is no electrical continuity between the second terminals.

[0435] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 25, the signal output from the circuit 1201 corresponds to the In the example shown, the other of the source and drain of the switch 1203 is connected to the source of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value of the inverted signal is inverted by the logic element 1206 and is output via the circuit 1220. The signal is then input to the circuit 1201.

[0436] In FIG. 25, the second terminal of the switch 1203 (the source of the transistor 1213) The signal output from the drain (the other drain) is passed through the logic element 1206 and the circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the circuit 1201. The signal output from the other terminal of the transistor 1213 (the other of the source and drain of the transistor 1213) is It may be input to the circuit 1201 without being inverted. For example, If there is a node that holds a signal whose logical value is the inverted value of the signal input from the input terminal, In this case, the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) can be input to the node.

[0437] In addition, in FIG. 25, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 11 made of a semiconductor other than an oxide semiconductor. 90. For example, a silicon layer or The memory element may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the element 1200 are transistors whose channels are formed in oxide semiconductor layers. Alternatively, the memory element 1200 may include a transistor 1209 or In addition, a transistor in which a channel is formed in an oxide semiconductor layer may be included. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be formed by

[0438] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0439] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0440] In addition, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer varies depending on the crystallinity. The off-state current is significantly lower than that of a transistor having a channel formed in silicon. Therefore, by using the transistor as the transistor 1209, Even when the power supply voltage is not supplied to the capacitor 1200, the signal held in the capacitor 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain the stored contents ( It is possible to retain the data.

[0441] In addition, by providing the switches 1203 and 1204, the precharge Since the memory element is characterized by performing the following operations, after the power supply voltage is resumed, the circuit 1201 This can shorten the time it takes to restore the original data.

[0442] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is restarted. After the signal is released, the signal held by the capacitive element 1208 is transferred to the transistor 1210 in the state (on or off state) and can be read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0443] Such a memory element 1200 may be a register or a cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, or multiple logic circuits, the power can be stopped for a short period of time, reducing power consumption. can be suppressed.

[0444] In the present embodiment, the memory element 1200 is used as a CPU. The 1200 is equipped with a DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device) and other LSIs, It can also be applied to RF (Radio Frequency) tags.

[0445] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0446] (Embodiment 7) In this embodiment, a structure example of a display panel according to one embodiment of the present invention will be described.

[0447] [Configuration example] FIG. 26A is a top view of a display panel according to one embodiment of the present invention, and FIG. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention. FIG. 26C is a circuit diagram illustrating a display panel according to one embodiment of the present invention. A circuit for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel FIG.

[0448] The transistors disposed in the pixel portion can be formed according to the above-described embodiment. In addition, since the transistor can be easily made into an n-channel type, the n-channel A part of the driver circuit can be composed of a transistor of the same type as the transistor of the pixel part. In this manner, the transistor shown in the above embodiment is formed in the pixel portion and the driver circuit. By using the above-mentioned capacitor, a highly reliable display device can be provided.

[0449] An example of a block diagram of an active matrix display device is shown in FIG. On the substrate 700, a pixel section 701, a first scanning line driving circuit 702, a second scanning line driving circuit 703, and a The pixel portion 701 includes a signal line driver circuit 703 and a signal line driver circuit 704. A first scanning line driving circuit 702 and a second scanning line driving circuit 704 are arranged to extend from the first scanning line driving circuit 702 and a second scanning line driving circuit 704. The second scanning line driving circuit 703 is extended from the second scanning line driving circuit 703. In each region, pixels each having a display element are arranged in a matrix. The substrate 700 of the device is a flexible printed circuit (FPC) or the like. It is connected to a timing control circuit (also called a controller or control IC) via a connection part. do.

[0450] In FIG. 26A, a first scanning line driver circuit 702, a second scanning line driver circuit 703, a signal The line driver circuit 704 is formed on the same substrate 700 as the pixel section 701. The number of components such as the drive circuits to be provided is reduced, which contributes to cost reduction. 700 If a driving circuit is provided externally, it becomes necessary to extend the wiring, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced. This can improve reliability or yield.

[0451] [Liquid crystal panel] An example of the circuit configuration of a pixel is shown in FIG. 26(B). Here, a VA type liquid crystal display panel 4 shows a pixel circuit that can be applied to the pixel of

[0452] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels of the multi-domain design to be The signals applied to the electrode layers can be controlled independently.

[0453] A gate wiring 712 of a transistor 716 and a gate wiring 713 of a transistor 717 The data lines are separated so that different gate signals can be applied. The source electrode layer or drain electrode layer 714 functioning as a transistor 716 is Transistors 716 and 717 are used in common in the above embodiment. In this case, the transistor 100 described in the above embodiment can be appropriately used. Therefore, it is possible to provide a high quality liquid crystal display panel.

[0454] A first pixel electrode layer electrically connected to the transistor 716 and a second pixel electrode layer electrically connected to the transistor 717 The shape of the second pixel electrode layer that is electrically connected to the first pixel electrode layer will be described. The shape of the pixel electrode layer is separated by slits. The first pixel electrode layer spreads in a V shape. The second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

[0455] The gate electrode of the transistor 716 is connected to the gate wiring 712, and the transistor 717 The gate electrode of the gate electrode 712 is connected to the gate wiring 713. 3, different gate signals are applied to transistors 716 and 717. By varying the thickness, the alignment of the liquid crystal can be controlled.

[0456] In addition, the capacitance wiring 710, the gate insulating film functioning as a dielectric, and the first pixel electrode layer Alternatively, a storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0457] The multi-domain structure has a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. can be.

[0458] Note that the pixel circuit shown in FIG. 26(B) is not limited to this. A switch, a resistor, a capacitor, a transistor, a sensor, or a logic circuit may be newly added to the pixel shown in FIG. etc. may be added.

[0459] [Organic EL Panel] Another example of the circuit configuration of a pixel is shown in FIG. 1 shows the pixel structure of a display panel.

[0460] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of a pair of electrodes. and holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The electrons and holes recombine to form an excited state in the light-emitting organic compound, When the excited state returns to the ground state, light is emitted. The optical element is called a current-excited light-emitting element.

[0461] FIG. 26C is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. can be used for the channel formation region of an n-channel transistor. The pixel circuit can apply digital time gray scale driving.

[0462] Regarding the configuration of an applicable pixel circuit and the operation of a pixel when digital time gray scale driving is applied, I will explain it below.

[0463] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light emitting The switching transistor 721 has a gate element 724 and a capacitor element 723. The first electrode (one of the source and drain electrode layers) is connected to the scan line 726. The second electrode (the other of the source electrode layer and the drain electrode layer) is connected to a signal line 725. It is connected to the gate electrode layer of the driving transistor 722. The gate electrode layer is connected to a power supply line 727 through a capacitor element 723, and the first electrode is connected to the power supply line 727, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light emitting element 724 corresponds to a common electrode 728. It is electrically connected to a common potential line formed thereon.

[0464] The switching transistor 721 and the driving transistor 722 are the same as those in the above embodiment. In this case, the transistor 100 described later can be appropriately used. It is possible to provide a functional EL display panel.

[0465] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727. For example, D, 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage of the light emitting element 72. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage in 24 refers to the voltage required to achieve the desired brightness, and should be at least 100%. Includes threshold voltage.

[0466] The capacitance element 723 is substituted for the gate capacitance of the driving transistor 722. The gate capacitance of the driving transistor 722 can be omitted. A capacitance may be formed between the gate electrode layer and the gate electrode layer.

[0467] Next, a signal input to the driving transistor 722 will be described. In the case of the above method, the driving transistor 722 is in two states, that is, fully on or off. A video signal that satisfies the above requirement is input to the driving transistor 722. In order to operate the actuator 722 in a linear region, a voltage higher than the voltage of the power supply line 727 is applied to the drive A gate electrode layer of the transistor 722 is connected to a signal line 725. A voltage equal to or greater than the threshold voltage Vth of the driving transistor 722 is applied.

[0468] When analog gradation driving is performed, the gate electrode layer of the driving transistor 722 is connected to the light emitting element 7 A voltage equal to or greater than the sum of the forward voltage of the transistor 724 and the threshold voltage Vth of the driving transistor 722 is applied. In addition, a video signal is input so that the driving transistor 722 operates in the saturation region. This causes a current to flow through the light emitting element 724. In addition, the driving transistor 722 is operated in a saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is passed to the light emitting element 724. Moreover, analog gray scale driving can be performed.

[0469] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. The pixel circuit shown in 6(C) is provided with a switch, a resistor, a capacitor, a sensor, a transistor or a logic A logic circuit or the like may be added.

[0470] When the transistors illustrated in the above embodiments are applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. The potential of the first gate electrode is controlled by a control circuit or the like. The second gate electrode is supplied with a potential lower than that applied to the source electrode by a wiring (not shown). Any of the above-mentioned potentials may be input.

[0471] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0472] (Embodiment 8) The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, Image playback device equipped with a DVD: Digital Versatile Disk c) a device having a display capable of reproducing a recording medium and displaying the image. In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used As such, mobile phones, portable game consoles, portable data terminals, e-book terminals, video cameras cameras, digital still cameras, goggle-type displays (head-mounted displays) Play), navigation systems, audio playback devices (car audio, digital audio copiers, fax machines, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. show.

[0473] FIG. 27A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 27(A) has two display units 903 and However, the number of display units that the portable game machine has is not limited to this. stomach.

[0474] FIG. 27B shows a portable data terminal, which includes a first housing 911, a second housing 912, and a first display unit. The first display unit 913, the second display unit 914, the connection unit 915, the operation keys 916, etc. 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The first display unit 913 and the second display unit 914 may be switched according to the angle between the first display unit 913 and the second display unit 914. At least one of the first display unit 912 and the second display unit 914 is provided with a function as a position input device. The function of the position input device may be achieved by touching the display device. The position input function can be added by providing a panel. It can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel section of the display device. This can be done.

[0475] FIG. 27C shows a notebook personal computer, which includes a housing 921, a display unit 922, It has a keyboard 923, a pointing device 924, and the like.

[0476] FIG. 27(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 933. 33 etc.

[0477] FIG. 27E shows a video camera, which includes a first housing 941, a second housing 942, and a display unit 943. The operation key 944, the lens 945, the connection part 946, etc. The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. 42.

[0478] FIG. 27(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, Light 954 etc.

[0479] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0480] (Embodiment 9) In this embodiment, a usage example of an RF tag according to one embodiment of the present invention will be described with reference to FIG. RF tags are used in a wide range of applications, including bills, coins, securities, and unregistered securities. Bonds, certificates (driver's licenses, resident's certificates, etc., see Figure 28(A)), packaging containers (wrapping paper bottles, etc., see Fig. 28(C), recording media (DVDs, video tapes, etc., see Fig. 28(B) (See Figure 28(D)), vehicles (bicycles, etc., see Figure 28(D)), personal belongings (bags, glasses, etc.), food, Plants, animals, the human body, clothing, daily necessities, medical products including medicines and pharmaceuticals, or electronic devices ( Liquid crystal display devices, EL display devices, television sets, or mobile phones) or other articles, It can be used by attaching it to tags (see Figure 28(E) and Figure 28(F)) to each item. can.

[0481] The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface of a device. It is fixed to the object. For example, in a book, it is embedded in the paper and the packaging is made of organic resin. If the RF terminal is used, it is embedded in the organic resin and fixed to each article. The 4000 is small, thin, and lightweight, so even after it is attached to an object, it does not lose its functionality. In addition, the design of banknotes, coins, securities, bearer bonds, or certificates is not affected. By providing an RF tag 4000 according to one embodiment of the present invention to a document or the like, an authentication function is provided. This authentication function can be used to prevent counterfeiting. The present invention can be applied to vessels, recording media, personal belongings, food, clothing, household goods, electronic devices, etc. By attaching an RF tag according to one embodiment, the efficiency of a system such as an inspection system can be improved. In addition, even in the case of vehicles, the RF tag according to one embodiment of the present invention can be attached. This can improve security against theft and the like.

[0482] As described above, the RF tag according to one aspect of the present invention can be used for each of the applications described in this embodiment. This reduces the power consumption during operation, including writing and reading information, and therefore the maximum communication distance It is also possible to store information for a very long time even when the power is cut off. Since the data can be stored for a long period of time, it can be used for applications where the frequency of writing and reading is low. can.

[0483] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Explanation of symbols]

[0484] 624 electronic 628 Substance 100 transistors 101 Semiconductor layer 101a Semiconductor layer 101b Semiconductor layer 101c Semiconductor layer 102 Gate insulating film 103 Gate electrode 104a conductive layer 104b Conductive layer 105 Conductive layer 111 Barrier membrane 111a Barrier film 111b Barrier film 111c Barrier film 111d Barrier film 111e Barrier film 111f Barrier film 111g Barrier membrane 112 Insulating film 113 Insulating film 114 Insulating film 115a Insulating film 115b Insulating film 115c Insulating film 115d Insulating film 115e Insulating film 116 Insulating film 121 Plug 122 Plug 123 Plug 124 Wiring 125 Conductive Layer 126 Plug 127 Plug 128 Plug 129a Plug 129b plug 129c plug 129d Plug 130 Transistor 131 Semiconductor Substrate 132 Semiconductor layer 133a Low resistance layer 133b Low resistance layer 134 Gate insulating film 135 Gate electrode 136 Insulating Film 137 Insulating Film 138 Insulating Film 139 Plug 140 Plug 141 Plug 142 Wiring 143 Conductive Layer 144 Conductive Layer 145 Plug 146 Conductive Layer 147 Plug 150 Capacitive element 151 Conductive layer 152 Conductive layer 152b Conductive layer 153a conductive layer 153b Conductive layer 154a conductive layer 154b Conductive layer 154c conductive layer 154d conductive layer 154e conductive layer 160 Transistors 164 Plug 165 Plug 166 Wiring 176a area 176b area 171a Low resistance region 171b Low resistance region 181 Conductive Film 190 Transistors 191 Transistor 211a Barrier film 211b Barrier film 211c Barrier membrane 211d Barrier film 211e Barrier film 211f Barrier film 215a Insulating film 215b Insulating film 215c Insulating film 215d Insulating film 215e Insulating film 215f Insulating film 251 Conductive Layer 251a Conductive layer 251b Conductive layer 251c conductive layer 251d conductive layer 251e conductive layer 261 Insulating Film 281 layers 282 layers 283 layers 284 layers 285 layers 286 layers 287 layers 288 layers 289 layers 290 layers 291 layers 292 layers 293 layers 294 layers 295 layers 321 Plug 322 Plug 610 Electron Gun Room 612 Optical system 614 Sample Room 616 Optical system 618 Camera 620 Observation Room 622 Film Room 632 Fluorescent Screen 660a Capacitive element 660b Capacitive element 661a Transistor 661b Transistor 662a Transistor 662b Transistor 663a Inverter 663b Inverter 700 Substrates 701 Pixel section 702 Scanning line driver circuit 703 Scanning line driver circuit 704 Signal line driver circuit 710 Capacitance wiring 712 Gate wiring 713 Gate wiring 714 Drain electrode layer 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 pixels 721 Switching Transistors 722 Driving Transistor 723 Capacitive element 724 Light emitting element 725 Signal Line 726 scan lines 727 Power line 728 Common electrode 800 RF Tags 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2100 Transistor 2200 Transistor 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistors 3300 Transistors 3400 Capacitive element 4000 RF tags 5100 pellets 5100a Pellet 5100b Pellets 5101 AEON 5102 Zinc oxide layer 5103 particles 5105a Pellet 5105a1 area 5105a2 Pellet 5105b Pellet 5105c Pellet 5105d Pellet 5105d1 area 5105e Pellet 5120 PCB 5130 Target 5161 area

Claims

1. A first transistor; A second transistor; and A capacitive element; A first conductive layer; and a second conductive layer; the first conductive layer is located on a gate electrode of the first transistor; a first terminal and a second terminal of the capacitance element are located on a gate electrode of the first transistor; a first terminal and a second terminal of the capacitance element are located under a channel formation region of the second transistor; a source electrode or a drain electrode of the second transistor is always electrically connected to a first terminal or a second terminal of the capacitance element; the second conductive layer penetrates a semiconductor in which the second transistor is formed, and is constantly in electrical contact with the first conductive layer.

2. A first transistor; A second transistor; and A capacitive element; A first conductive layer; and A second conductive layer; and wiring, the first conductive layer is located on a gate electrode of the first transistor; a first terminal and a second terminal of the capacitance element are located on a gate electrode of the first transistor; a first terminal and a second terminal of the capacitance element are located under a channel formation region of the second transistor; a source electrode or a drain electrode of the second transistor is always electrically connected to a first terminal or a second terminal of the capacitance element; the wiring is located above a channel formation region of the second transistor; the second conductive layer penetrates a semiconductor in which the second transistor is formed and is always electrically connected to the first conductive layer; The wiring is always electrically connected to the second conductive layer.

3. In claim 1 or 2, A semiconductor device, wherein a channel formation region of the first transistor has single crystal silicon.

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