Solid-state imaging device

Abstract

To provide a semiconductor device that is able to suppress a manufacturing process from becoming complicated, and a solid-state imaging sensor in which the semiconductor device is built into an amplifying transistor.SOLUTION: A semiconductor device includes: a low-concentration N-type region; a first high-concentration N-type region and a second high-concentration N-type region that are stacked with the low-concentration N-type region interposed therebetween, and that have a higher concentration of impurity than the low-concentration N-type region; a gate electrode that surrounds the low-concentration N-type region as viewed from a stacking direction which is a direction in which the low-concentration N-type region, the first high-concentration N-type region, and the second high-concentration N-type region are stacked; a first insulating film placed between the gate electrode and the low-concentration N-type region; and a second insulating film placed between the gate electrode and the first high-concentration N-type region. The first high-concentration N-type region is connected to one of a source electrode and a drain electrode, and the second high-concentration N-type region is connected to the other of the source electrode and the drain electrode.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The technology according to the present disclosure (the present technology) relates to, for example, a semiconductor device used in an imaging device, and a solid-state imaging element in which the semiconductor device is incorporated in an amplifying transistor. [Background technology]

[0002] As an example of a semiconductor device, there is a device having a Gate All Around structure (hereinafter, referred to as a "GAA structure") in which a gate electrode is formed so as to surround a channel, as in the technology disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-233073 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, as with the technique disclosed in Patent Document 1, a semiconductor device having a GAA structure requires a complicated manufacturing process, which increases the number of steps, resulting in an increase in costs.

[0005] In view of the above problems, an object of the present technology is to provide a semiconductor device capable of suppressing the complication of the manufacturing process, and a solid-state imaging element in which the semiconductor device is incorporated in an amplifying transistor. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment of the present technology includes a low-concentration N-type region, a first high-concentration N-type region, a second high-concentration N-type region, a gate electrode, a first insulating film, and a second insulating film. The first high-concentration N-type region and the second high-concentration N-type region are stacked with the low-concentration N-type region sandwiched therebetween, and are regions having a higher impurity concentration than the low-concentration N-type region. The first high-concentration N-type region is connected to one of the source electrode and the drain electrode, and the second high-concentration N-type region is connected to the other of the source electrode and the drain electrode. The gate electrode surrounds the low-concentration N-type region as viewed from a stacking direction in which the low-concentration N-type region, the first high-concentration N-type region, and the second high-concentration N-type region are stacked. The first insulating film is disposed between the gate electrode and the low-concentration N-type region. The second insulating film is disposed between the gate electrode and the first high-concentration N-type region.

[0007] A solid-state imaging device according to an aspect of the present technology includes a pixel circuit including an amplifier transistor, and the above-described semiconductor device is incorporated in the amplifier transistor. [Brief description of the drawings]

[0008] [Figure 1] 1 is a perspective view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line II-II of FIG. [Diagram 3] 4A to 4C are cross-sectional views showing the operation of the semiconductor device. [Figure 4] 4 is a cross-sectional view showing a bottom region forming step in the manufacturing process of the semiconductor device according to the first embodiment. FIG. [Diagram 5] 3 is a cross-sectional view showing an element isolation forming step in the manufacturing process of the semiconductor device according to the first embodiment. FIG. [Figure 6] 5 is a cross-sectional view showing a facing region forming step in the manufacturing process of the semiconductor device according to the first embodiment. FIG. [Figure 7] 3 is a cross-sectional view showing an oxide film deposition step in the manufacturing process of the semiconductor device according to the first embodiment. FIG. [Figure 8] 3 is a cross-sectional view showing a polysilicon deposition step in the manufacturing process of the semiconductor device according to the first embodiment. FIG. [Figure 9] 5 is a cross-sectional view showing a mask removing step in the manufacturing process of the semiconductor device according to the first embodiment. FIG. [Figure 10] 3A to 3C are cross-sectional views showing a low-concentration N-type region forming step and a second high-concentration N-type region forming step in the manufacturing process of the semiconductor device according to the first embodiment. [Figure 11] 11 is a perspective view showing a configuration of a semiconductor device according to a second embodiment. FIG. [Figure 12] 12 is a cross-sectional view taken along line XII-XII in FIG. 11. [Figure 13] 10 is a cross-sectional view showing a first oxide film deposition step in the manufacturing process of the semiconductor device according to the second embodiment. FIG. [Figure 14] 10A to 10C are cross-sectional views showing a first oxide film etching step in the manufacturing process of the semiconductor device according to the second embodiment. [Figure 15] 10A to 10C are cross-sectional views showing a first oxide film etching step in the manufacturing process of the semiconductor device according to the second embodiment. [Figure 16] 11A to 11C are cross-sectional views showing a first mask removing step in the manufacturing process of the semiconductor device according to the second embodiment. [Figure 17] 10 is a cross-sectional view showing a second oxide film depositing step in the manufacturing process of the semiconductor device according to the second embodiment. FIG. [Figure 18] 11 is a cross-sectional view showing a polysilicon deposition step in the manufacturing process of the semiconductor device according to the second embodiment. FIG. [Figure 19] 11 is a cross-sectional view showing a mask removing step in the manufacturing process of the semiconductor device according to the second embodiment. FIG. [Figure 20] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment. [Figure 21] 11A to 11C are cross-sectional views showing a first oxide film depositing step in the manufacturing process of the semiconductor device according to the third embodiment. [Figure 22] 11A to 11C are cross-sectional views showing a first oxide film etching step in the manufacturing process of the semiconductor device according to the third embodiment. [Diagram 23]11A to 11C are cross-sectional views showing a first oxide film etching step in the manufacturing process of the semiconductor device according to the third embodiment. [Figure 24] 11A to 11C are cross-sectional views showing a first mask removing step in the manufacturing process of the semiconductor device according to the third embodiment. [Diagram 25] 11A to 11C are cross-sectional views showing a second oxide film depositing step in the manufacturing process of the semiconductor device according to the third embodiment. [Figure 26] 11A to 11C are cross-sectional views showing a polysilicon deposition step in the manufacturing process of the semiconductor device according to the third embodiment. [Figure 27] 11 is a cross-sectional view showing a mask removing step in the manufacturing process of the semiconductor device according to the third embodiment. FIG. [Figure 28] FIG. 13 is a perspective view showing the configuration of a semiconductor device according to a fourth embodiment. [Figure 29] 29 is a cross-sectional view taken along line XXIX-XXIX of FIG. 28. [Diagram 30] FIG. 13 is a perspective view showing a configuration of a semiconductor device according to a modified example of the fourth embodiment. [Diagram 31] This is a cross-sectional view taken along line XXXI-XXXI in Figure 30. [Diagram 32] FIG. 13 is a perspective view showing the configuration of a semiconductor device according to a fifth embodiment. [Diagram 33] This is a cross-sectional view taken along line XXXIII-XXXIII in Figure 32. [Diagram 34] 13 is a perspective view showing the configuration of a semiconductor device according to a sixth embodiment. FIG. [Diagram 35] FIG. 13 is a perspective view showing the configuration of a semiconductor device according to a seventh embodiment. [Diagram 36] FIG. 13 is a cross-sectional view showing the configuration of a solid-state imaging element according to an eighth embodiment. [Figure 37] FIG. 13 is a cross-sectional view showing the configuration of a solid-state imaging element according to an eighth embodiment. [Figure 38] FIG. 2 is a diagram illustrating an example of a sensor pixel and a readout circuit. [Figure 39] 1 is a diagram illustrating an example of a connection mode between a plurality of readout circuits and a plurality of vertical signal lines. [Diagram 40]This is a cross-sectional view taken along line XXXX-XXXX in Figure 37. [Diagram 41] 13A to 13C are cross-sectional views showing a manufacturing process for a solid-state imaging device according to an eighth embodiment. [Diagram 42] 13A to 13C are cross-sectional views showing a manufacturing process for a solid-state imaging device according to an eighth embodiment. [Diagram 43] 13A to 13C are cross-sectional views showing a manufacturing process for a solid-state imaging device according to an eighth embodiment. [Diagram 44] 13A to 13C are cross-sectional views showing a manufacturing process for a solid-state imaging device according to an eighth embodiment. [Diagram 45] 13A to 13C are cross-sectional views showing a manufacturing process for a solid-state imaging device according to an eighth embodiment. [Diagram 46] 13A to 13C are cross-sectional views showing a manufacturing process for a solid-state imaging device according to an eighth embodiment. [Figure 47] 13A to 13C are cross-sectional views showing a manufacturing process for a solid-state imaging device according to an eighth embodiment. [Figure 48] 13A to 13C are cross-sectional views showing a manufacturing process for a solid-state imaging device according to an eighth embodiment. [Figure 49] 13A to 13C are cross-sectional views showing a manufacturing process for a solid-state imaging device according to an eighth embodiment. [Figure 50] 13A to 13C are cross-sectional views showing a manufacturing process for a solid-state imaging device according to an eighth embodiment. [Figure 51] 13A to 13C are cross-sectional views showing a manufacturing process for a solid-state imaging device according to an eighth embodiment. [Figure 52] 13A to 13C are cross-sectional views showing a manufacturing process for a solid-state imaging device according to an eighth embodiment. [Figure 53] 13A to 13C are cross-sectional views showing a manufacturing process for a solid-state imaging device according to an eighth embodiment. [Figure 54] This is a cross-sectional view taken along line XXXXXIV-XXXXXIV in Figure 53. [Figure 55] This is a cross-sectional view of line XXXXXV-XXXXXV in Figure 54. [Figure 56] FIG. 13 is a cross-sectional view showing the configuration of a solid-state imaging element according to a ninth embodiment. [Figure 57] FIG. 21 is a cross-sectional view showing the configuration of a solid-state imaging element according to a tenth embodiment. [Figure 58] FIG. 21 is a cross-sectional view showing the configuration of a solid-state imaging element according to an eleventh embodiment. [Figure 59] FIG. 23 is a cross-sectional view showing the configuration of a solid-state imaging element according to a twelfth embodiment. [Figure 60] FIG. 23 is a cross-sectional view showing the configuration of a solid-state imaging element according to a thirteenth embodiment. [Figure 61] 21A to 21C are cross-sectional views showing a manufacturing process for a solid-state imaging element according to a thirteenth embodiment. [Figure 62] FIG. 23 is a block diagram illustrating an example of the functional configuration of an imaging device according to a fourteenth embodiment. [Figure 63] 63 is a plan view showing a schematic configuration of the imaging device shown in FIG. 62. [Figure 64] 64 is a schematic diagram showing a cross-sectional configuration taken along line III-III' shown in FIG. 63. [Figure 65] FIG. 63 is an equivalent circuit diagram of the pixel sharing unit shown in FIG. 62. [Figure 66] 10 is a diagram illustrating an example of a connection mode between a plurality of pixel sharing units and a plurality of vertical signal lines. [Figure 67] FIG. 65 is a schematic cross-sectional view showing an example of a specific configuration of the imaging device shown in FIG. 64. [Figure 68A] 68 is a schematic diagram illustrating an example of a planar configuration of a main part of the first substrate shown in FIG. 67. [Figure 68B] 68B is a schematic diagram showing the planar configuration of a pad portion together with a main portion of the first substrate shown in FIG. 68A. [Figure 69] 68 is a schematic diagram illustrating an example of a planar configuration of the second substrate (semiconductor layer) shown in FIG. 67. FIG. [Figure 70] 68 is a schematic diagram showing an example of a planar configuration of a pixel circuit and a main part of a first substrate, together with the first wiring layer shown in FIG. 67. [Figure 71] 68 is a schematic diagram illustrating an example of a planar configuration of the first wiring layer and the second wiring layer illustrated in FIG. 67. [Figure 72] 68 is a schematic diagram illustrating an example of a planar configuration of the second wiring layer and the third wiring layer shown in FIG. 67. [Figure 73]68 is a schematic diagram illustrating an example of a planar configuration of the third wiring layer and the fourth wiring layer shown in FIG. 67. [Figure 74] FIG. 65 is a schematic diagram for explaining the path of an input signal to the imaging device shown in FIG. 64. [Figure 75] FIG. 65 is a schematic diagram for explaining a signal path of a pixel signal in the imaging device shown in FIG. 64. [Figure 76] 70 is a schematic diagram showing a modified example of the planar configuration of the second substrate (semiconductor layer) shown in FIG. 69. FIG. [Figure 77] 77 is a schematic diagram showing the planar configuration of the pixel circuit shown in FIG. 76 as well as the first wiring layer and the main part of the first substrate. [Figure 78] 78 is a schematic diagram showing an example of a planar configuration of a second wiring layer together with the first wiring layer shown in FIG. 77. [Figure 79] 79 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. 78. [Figure 80] 79A is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 79. [Figure 81] FIG. 68B is a schematic diagram illustrating a modified example of the planar configuration of the first substrate shown in FIG. 68A. [Figure 82] 82 is a schematic diagram showing an example of a planar configuration of a second substrate (semiconductor layer) laminated on the first substrate shown in FIG. 81. FIG. [Figure 83] FIG. 83 is a schematic diagram showing an example of a planar configuration of a first wiring layer together with the pixel circuit shown in FIG. 82. [Figure 84] 84 is a schematic diagram showing an example of a planar configuration of a second wiring layer together with the first wiring layer shown in FIG. 83. [Figure 85] 85 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. 84. [Figure 86] 86 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 85. [Figure 87] 82 is a schematic diagram illustrating another example of the planar configuration of the first substrate shown in FIG. 81. FIG. [Figure 88]88 is a schematic diagram illustrating an example of a planar configuration of a second substrate (semiconductor layer) that is laminated on the first substrate illustrated in FIG. 87. FIG. [Figure 89] FIG. 89 is a schematic diagram showing an example of a planar configuration of a first wiring layer together with the pixel circuit shown in FIG. 88. [Figure 90] 89. FIG. 90 is a schematic diagram showing an example of a planar configuration of the second wiring layer together with the first wiring layer shown in FIG. 89. [Figure 91] 91 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. 90. [Figure 92] 92 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 91. [Figure 93] 65 is a schematic cross-sectional view illustrating another example of the imaging device shown in FIG. 64. [Figure 94] FIG. 94 is a schematic diagram for explaining the path of an input signal to the imaging device shown in FIG. 93. [Figure 95] FIG. 94 is a schematic diagram for explaining a signal path of a pixel signal in the imaging device shown in FIG. 93. [Figure 96] 68 is a schematic cross-sectional view illustrating another example of the imaging device shown in FIG. 67. [Figure 97] FIG. 67 is a diagram illustrating another example of the equivalent circuit shown in FIG. 65. [Figure 98] FIG. 68B is a schematic plan view illustrating another example of the pixel separating portion shown in FIG. 68A etc. [Figure 99] FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging system including an imaging device according to the above embodiment and its modified example. [Figure 100] A diagram showing an example of an imaging procedure of the imaging system shown in Figure 99. [Figure 101] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 102] 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. [Figure 103] 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 104] 2 is a block diagram showing an example of a functional configuration of a camera head and a CCU. FIG. [Figure 105] 1 is a circuit diagram showing an example of a solid-state imaging device as an application example of the present technology. [Fig. 106] 1 is a cross-sectional view showing an example of a solid-state imaging element as an application example of the present technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present technology will be described with reference to the drawings. In the description of the drawings, the same or similar parts are given the same or similar symbols, and duplicate descriptions are omitted. Each drawing is schematic and may differ from the actual one. The embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present technology, and the technical idea of ​​the present technology is not limited to the devices and methods exemplified in the following embodiments. The technical idea of ​​the present technology can be modified in various ways within the technical scope described in the claims.

[0010] (First embodiment) <Overall configuration of semiconductor device> The semiconductor device according to the first embodiment is incorporated in, for example, an amplifying transistor provided in a pixel circuit of a solid-state imaging device.

[0011] As shown in Figures 1 and 2, the semiconductor device has a low-concentration N-type region LN, a first high-concentration N-type region 2, a second high-concentration N-type region 3, a gate electrode 4, a first insulating film 5a, a second insulating film 5b, and a third insulating film 5c.

[0012] The low-concentration N-type region LN has an impurity concentration of 10 keV / 1E 18 (pcs / cm 2 In the first embodiment, the low-concentration N-type region LN is formed using a material having an impurity concentration of 100 keV / 1E 13 (pcs / cm 2 ) phosphorus will be described. The low-concentration N-type region LN has a rectangular parallelepiped shape.

[0013] Of the rectangular parallelepiped formed by the low-concentration n-type region LN, two faces that are not adjacent to each other each form a plane when viewed from the stacking direction shown in Fig. 2. The stacking direction will be described later. Therefore, the shape of the low-concentration N-type region LN is rectangular when viewed from the stacking direction.

[0014] The first high concentration N-type region 2 is made of a material having a higher impurity concentration than the low concentration N-type region LN. For example, the first high concentration N-type region 2 is made of a material having an impurity concentration of 10 keV / 1E 19 (pcs / cm 2 In the first embodiment, the first high concentration N-type region 2 is formed using a material having an impurity concentration of 500 keV / 1E or more. 14 (pcs / cm 2 ) phosphorus and impurity concentration of 100keV / 1E 14 (pcs / cm 2 ) phosphorus will be described. The first high-concentration N-type region 2 is formed to include a facing region 2a and a bottom region 2b.

[0015] The facing region 2a is a region facing the low-concentration N-type region LN with the gate electrode 4 interposed therebetween. In the first embodiment, as an example, the facing region 2a is 14 (pcs / cm 2 ) phosphorus will be described. The bottom region 2b is a region including a portion in contact with one of two non-adjacent surfaces (the lower surface in FIG. 2) of the low-concentration N-type region LN and a portion facing the gate electrode 4 in the stacking direction. In the first embodiment, as an example, the bottom region 2b is 14 (pcs / cm 2 ) phosphorus will be described.

[0016] The first high-concentration N-type region 2 is connected to one of the source electrode and the drain electrode. In the first embodiment, as shown in the figure, a case will be described in which the opposing region 2a of the first high-concentration N-type region 2 is connected to the drain electrode ("Drain" in FIG. 2).

[0017] The second high concentration N-type region 3 is made of a material having a higher impurity concentration than the low concentration N-type region LN. For example, the second high concentration N-type region 3 is made of a material having an impurity concentration of 10 keV / 1E 19 (pcs / cm 2 In the first embodiment, the second high-concentration N-type region 3 is formed using a material having an impurity concentration of 10 keV / 1E 14 (pcs / cm 2 ) phosphorus will be described. The second high-concentration n-type region 3 is in contact with the other of the two non-adjacent surfaces of the lightly doped n-type region LN (the upper surface in FIG. 2).

[0018] As described above, the first high-concentration N-type region 2 and the second high-concentration N-type region 3 are stacked with the low-concentration N-type region LN sandwiched therebetween, and are regions with a higher impurity concentration than the low-concentration N-type region LN. Therefore, the stacking direction is the direction in which the lightly doped N-type region LN, the first heavily doped N-type region 2, and the second heavily doped N-type region 3 are stacked.

[0019] The second high-concentration N-type region 3 is connected to the other of the source electrode and the drain electrode. In the first embodiment, as shown in the figure, a case will be described in which the second high-concentration N-type region 3 is connected to the source electrode ("Source" in FIG. 2). The surface of the second heavily doped n-type region 3 connected to the source electrode and the surface of the opposing region 2a connected to the drain electrode are at the same height (height of the silicon surface) when viewed from a direction perpendicular to the stacking direction. Therefore, the surface of the first heavily doped N-type region 2 connected to the source electrode or drain electrode and the surface of the second heavily doped N-type region 3 connected to the source electrode or drain electrode are at the same height when viewed in a direction perpendicular to the stacking direction.

[0020] The gate electrode 4 surrounds the low-concentration N-type region LN when viewed from the stacking direction (the up-down direction in FIG. 2). In addition, the gate electrode 4 has a portion that does not face the low-concentration N-type region LN. That is, the low-concentration N-type region LN has a portion that does not face the gate electrode 4.

[0021] The gate electrode 4 is made of, for example, at least one of polycrystalline silicon (Poly-Si), titanium nitride (TiN), copper (Cu), aluminum (Al), and tungsten (W). In the first embodiment, a case in which polycrystalline silicon is used as the material of the gate electrode 4 will be described. The gate electrode 4 has a rectangular shape when viewed from the stacking direction.

[0022] The first insulating film 5a is disposed between the gate electrode and the low-concentration N-type region LN. The material of the first insulating film 5a is, for example, at least one of silicon oxide (SiO), silicon nitride (SiN), and hafnium oxide (HfO).

[0023] The second insulating film 5b is disposed between the gate electrode and the first high-concentration N-type region 2. The second insulating film 5b is made of, for example, at least one of silicon oxide, silicon nitride, and hafnium oxide.

[0024] The third insulating film 5c is disposed between the facing region 2a and the gate electrode. The third insulating film 5c is made of, for example, at least one of silicon oxide, silicon nitride, and hafnium oxide.

[0025] In the first embodiment, a case will be described in which silicon oxide is used as the material of the first insulating film 5a, the second insulating film 5b, and the third insulating film 5c.

[0026] The semiconductor device of the first embodiment has a distribution of a layer with a high impurity concentration (first high-concentration N-type region 2), a layer with a low impurity concentration (low-concentration N-type region LN), and a layer with a high impurity concentration (second high-concentration N-type region 3) in the vertical direction in a region below the silicon surface. In addition, the semiconductor device of the first embodiment has a GAA structure in which the low-concentration N-type region LN is surrounded by a gate insulating film (first insulating film 5a, second insulating film 5b, and third insulating film 5c) and a gate electrode 4. As a result, current flows vertically (in the stacking direction) from the source electrode to which the second high-concentration N-type region 3 is connected, through the channel (channel region) formed in the low-concentration N-type region LN, to the first high-concentration N-type region 2 (bottom region 2b) connected to the drain electrode. As shown in Fig. 3, the gate electrode 4 adjusts the width of the depletion layer DL from around the channel depending on the gate potential, and expands the depletion layer DL when the gate potential is reduced. When the entire channel is depleted, no current flows from the source electrode to the drain electrode (in off operation). On the other hand, when the gate potential is increased and the depletion layer DL is narrowed, a current flows from the source electrode to the drain electrode (in on operation). Note that in Fig. 3, the interface traps of the gate insulating film are indicated with the symbol TP.

[0027] <Semiconductor device manufacturing process> A manufacturing process for manufacturing the semiconductor device of the first embodiment will be described with reference to FIGS. 1 to 3 and with reference to FIGS. The manufacturing process of the semiconductor device includes a bottom region forming step, an element isolation forming step, a facing region forming step, an oxide film depositing step, and a polysilicon depositing step, as well as a mask removing step, a low concentration N-type region forming step, a second high concentration N-type region forming step, a heat treatment step, and a contact forming step.

[0028] In the bottom region forming step, as shown in FIG. 4, an ion implantation method is used to implant impurities into the bottom region of the silicon substrate 10 at a concentration of 500 keV / 1E. 14 (pcs / cm 2 ) phosphorus is implanted to form bottom region 2b.

[0029] The element isolation forming step is a step subsequent to the bottom region forming step. 5, in the element isolation forming step, a hard mask 12 made of a nitride film or the like is patterned by photolithography in regions other than the regions in which the gate electrode 4, the first insulating film 5a, the second insulating film 5b, and the third insulating film 5c will be formed later. Furthermore, in the element isolation forming step, the silicon substrate 10 is etched by plasma etching to a depth of about 500 nm in the regions in which the gate electrode 4, the first insulating film 5a, the second insulating film 5b, and the third insulating film 5c will be formed later.

[0030] The facing region forming step is a step subsequent to the element isolation forming step. 6, in the facing region forming step, a first resist mask 14a is formed by photolithography on the portion of the silicon substrate 10 that has been carved in the element isolation forming step and on the portion surrounded by the portion carved in the element isolation forming step as viewed from the stacking direction. Furthermore, in the facing region forming step, an ion implantation method is used to implant impurities at a concentration of 100 keV / 1E into the silicon substrate 10 in the region where the first resist mask 14a is not formed. 14 (pcs / cm 2 ) is implanted to form the facing region 2a.

[0031] The oxide film depositing step is a step subsequent to the facing region forming step. 7, in the oxide film depositing step, the first resist mask 14a formed in the facing region forming step is removed. Then, an oxide film 16, which will later become the first insulating film 5a, the second insulating film 5b, and the third insulating film 5c, is deposited on the silicon substrate 10, the bottom region 2b, and the hard mask 12 by a thermal oxidation method to a thickness of, for example, about 7 [nm].

[0032] The polysilicon deposition step is a step that follows the oxide film deposition step. In the polysilicon deposition step, as shown in FIG. 8, polysilicon 18 is deposited by a CVD (Chemical Vapor Deposition) method on the surface on which the oxide film 16 has been deposited in the oxide film deposition step.

[0033] The mask removal step is a step that follows the polysilicon deposition step. 9, in the mask removal step, the polysilicon 18 deposited in the polysilicon deposition step is planarized by a CMP (Chemical Mechanical Polishing) method. Furthermore, in the mask removal step, the hard mask 12 patterned in the element isolation formation step is removed by wet etching to form the gate electrode 4, the first insulating film 5a, the second insulating film 5b, and the third insulating film 5c.

[0034] The low concentration N-type region forming step is a step subsequent to the mask removing step. 10, in the low-concentration N-type region forming step, a second resist mask 14b is formed by photolithography on the opposing region 2a, the gate electrode 4, the first insulating film 5a, and the third insulating film 5c. Furthermore, in the low-concentration N-type region forming step, an ion implantation method is used to implant an impurity having a concentration of 100 keV / 1E into the silicon substrate 10 in the region where the second resist mask 14b is not formed. 13 (pcs / cm 2 ) phosphorus is implanted to form a low concentration N-type region LN.

[0035] The second high concentration N-type region forming step is a step subsequent to the low concentration N-type region forming step. In the second high-concentration N-type region formation step, as shown in FIG. 10, the surface of the low-concentration N-type region LN opposite to the surface in contact with the bottom region 2b (the upper surface in FIG. 10) is implanted with an impurity concentration of 100 keV / 1E by using an ion implantation method. 14 (pcs / cm 2 ) is implanted. Thereby, in the second high concentration N-type region forming step, second high concentration N-type region 3 is formed.

[0036] The heat treatment step and the contact formation step are steps subsequent to the second high concentration N-type region formation step. In the heat treatment step, the impurities are activated by performing heat treatment. The contact formation process involves a process similar to that used to form a known CMOS, thereby connecting the first heavily doped N-type region 2 to one of the source electrode and the drain electrode, and connecting the second heavily doped N-type region 3 to the other of the source electrode and the drain electrode.

[0037] The configuration of the first embodiment has compatibility with the known manufacturing process for forming conventional CMOS, and therefore it is possible to provide a semiconductor device that can suppress the complication of the manufacturing process.

[0038] Furthermore, in the configuration of the first embodiment, the channel formed in the low-concentration N-type region LN is surrounded by the gate electrode 4, so that the channel is not affected by interface traps in the gate insulating film. This makes it possible to suppress noise caused by interface traps.

[0039] (Modification of the first embodiment) In the first embodiment, polycrystalline silicon is used as the material of the gate electrode 4, but the present invention is not limited thereto, and titanium nitride and aluminum may be used as the material of the gate electrode 4. In this case, a suitable combination of the gate electrode 4 and the gate insulating film is one in which the materials of the first insulating film 5a, the second insulating film 5b, and the third insulating film 5c are made of silicon oxide as a main component and hafnium oxide as an additive.

[0040] Second embodiment The semiconductor device according to the second embodiment also has the cross-sectional structure shown in Fig. 1, and has the same structure as the semiconductor device according to the first embodiment. However, the semiconductor device according to the second embodiment differs from the first embodiment in that the thickness T2 of the second insulating film 5b and the thickness T3 of the third insulating film 5c are thicker than the thickness T1 of the first insulating film 5a, as shown in Figs.

[0041] <Semiconductor device manufacturing process> 11 and 12, a manufacturing process for manufacturing the semiconductor device of the second embodiment will be described using FIGS. 13 to 19. FIG.

[0042] The manufacturing process of the semiconductor device includes a bottom region forming step, an isolation forming step, a facing region forming step, a first oxide film depositing step, a first oxide film etching step, a first mask removing step, and a second oxide film depositing step. In addition, the manufacturing process of the semiconductor device includes a polysilicon depositing step, a second mask removing step, a low concentration N-type region forming step, a second high concentration N-type region forming step, a heat treatment step, and a contact forming step. The bottom region forming process, the element isolation forming process, the opposing region forming process, the low concentration N-type region forming process, the second high concentration N-type region forming process, the heat treatment process, and the contact forming process are similar to those in the first embodiment described above, and therefore will not be described.

[0043] The first oxide film deposition step is a step subsequent to the facing region formation step. In the first oxide film deposition step, as shown in FIG. 13, a first oxide film 16a, which will later become the second insulating film 5b and the third insulating film 5c, is deposited on the silicon substrate 10, the bottom region 2b, and the hard mask 12 by a thermal oxidation method to a thickness of, for example, about 14 nm.

[0044] The first oxide film etching step is a step subsequent to the first oxide film deposition step. In the first oxide film etching step, as shown in FIG. 14, a third resist mask 14c is formed by photolithography on the portion of the silicon substrate 10 that was dug in the element isolation formation step and on the outer periphery side of the portion that was dug in the element isolation formation step. Furthermore, in the first oxide film etching step, as shown in FIG. 15, the portion of the first oxide film 16a that is not covered by the third resist mask 14c is removed by wet etching.

[0045] The first mask removing step is a step subsequent to the first oxide film etching step. In the first mask removal step, as shown in FIG. 16, the third resist mask 14c is removed.

[0046] The second oxide film deposition step is a step subsequent to the first mask removal step. In the second oxide film deposition process, as shown in FIG. 17, a second oxide film 16b, which will later become the first insulating film 5a, is deposited on the silicon substrate 10, the bottom region 2b, and the hard mask 12 by a thermal oxidation method to a thickness of, for example, about 7 nm.

[0047] The polysilicon deposition step is a step that follows the second oxide film deposition step. In the polysilicon depositing step, as shown in FIG. 18, polysilicon 18 is deposited by CVD on the surface on which the second oxide film 16b has been deposited in the second oxide film depositing step.

[0048] The mask removal step is a step that follows the polysilicon deposition step. In the mask removal step, the polysilicon 18 deposited in the polysilicon deposition step is planarized by a CMP method, as shown in Fig. 19. Furthermore, in the mask removal step, the hard mask 12 patterned in the element isolation formation step is removed by wet etching, thereby forming the gate electrode 4, the first insulating film 5a, the second insulating film 5b, and the third insulating film 5c.

[0049] In the configuration of the second embodiment, by making the film thickness of the second insulating film 5b and the third insulating film 5c different from the film thickness of the first insulating film 5a, it is possible to reduce the first parasitic capacitance CPa and the second parasitic capacitance CPb. The first parasitic capacitance CPa is a parasitic capacitance formed between the facing region 2a and the gate electrode 4. The second parasitic capacitance CPb is a parasitic capacitance formed between the bottom region 2b and the gate electrode 4. This makes it possible to reduce the capacitance between the drain electrode and the gate electrode 4.

[0050] Third embodiment The semiconductor device according to the third embodiment also has the cross-sectional structure shown in Fig. 1, and has the same structure as the semiconductor device according to the first embodiment. However, the semiconductor device according to the third embodiment differs from the first embodiment in that the thickness T3 of the third insulating film 5c is thicker than the thickness T1 of the first insulating film 5a and the thickness T2 of the second insulating film 5b, as shown in Fig. 20.

[0051] <Semiconductor device manufacturing process> A manufacturing process for manufacturing the semiconductor device of the third embodiment will be described with reference to FIG. 20 and with reference to FIGS.

[0052] The manufacturing process in the third embodiment includes a bottom region forming step, an element isolation forming step, a facing region forming step, a first oxide film depositing step, a first oxide film etching step, a first mask removing step, and a second oxide film depositing step. In addition, the manufacturing process of the semiconductor device includes a polysilicon depositing step, a second mask removing step, a low concentration N-type region forming step, a second high concentration N-type region forming step, a heat treatment step, and a contact forming step. The bottom region forming process, the element isolation forming process, the opposing region forming process, the low concentration N-type region forming process, the second high concentration N-type region forming process, the heat treatment process, and the contact forming process are similar to those in the first embodiment described above, and therefore will not be described.

[0053] The first oxide film deposition step is a step subsequent to the facing region formation step. In the first oxide film deposition step, as shown in FIG. 21, a third oxide film 16c, which will later become the third insulating film 5c, is deposited on the silicon substrate 10, the bottom region 2b, and the hard mask 12 by a thermal oxidation method to a thickness of, for example, about 14 nm.

[0054] The first oxide film etching step is a step subsequent to the first oxide film deposition step. In the first oxide film etching process, as shown in FIG. 22, a fourth resist mask 14d is formed by photolithography on the third oxide film 16c deposited in the first oxide film deposition process, excluding the region that will later become the low-concentration N-type region LN and the region that will later become the first insulating film 5a. Furthermore, in the first oxide film etching step, as shown in FIG. 23, the portion of the third oxide film 16c that is not covered by the fourth resist mask 14d is removed by wet etching.

[0055] The first mask removing step is a step subsequent to the first oxide film etching step. In the first mask removal step, as shown in FIG. 24, the fourth resist mask 14d is removed.

[0056] The second oxide film deposition step is a step subsequent to the first mask removal step. In the second oxide film deposition process, as shown in FIG. 25, a fourth oxide film 16d, which will later become the first insulating film 5a and the second insulating film 5b, is deposited on the silicon substrate 10, the bottom region 2b, and the hard mask 12 by a thermal oxidation method to a thickness of, for example, about 7 nm.

[0057] The polysilicon deposition step is a step that follows the second oxide film deposition step. In the polysilicon depositing step, as shown in FIG. 26, polysilicon 18 is deposited by CVD on the surface on which the second oxide film 16b has been deposited in the second oxide film depositing step.

[0058] The mask removal step is a step that follows the polysilicon deposition step. 27, in the mask removal step, the polysilicon 18 deposited in the polysilicon deposition step is planarized by a CMP method. Furthermore, in the mask removal step, the hard mask 12 patterned in the element isolation formation step is removed by wet etching to form the gate electrode 4, the first insulating film 5a, the second insulating film 5b, and the third insulating film 5c.

[0059] (Fourth embodiment) 28 and 29, the semiconductor device according to the fourth embodiment differs from the first embodiment in that it has a plurality (two) of low-concentration N-type regions LNa,1b and a plurality (two) of second high-concentration N-type regions 3a,3b. In the following description, the description of the parts common to the first embodiment will be omitted.

[0060] The two lightly doped N-type regions LNa,1b are arranged with a gap between them. The two second high-concentration N-type regions 3a and 3b are in contact with the surfaces of the two low-concentration N-type regions LNa and 1b opposite to the surface in contact with the bottom region 2b. In the figure, the second high-concentration N-type region 3a is in contact with the low-concentration N-type region LNa, and the second high-concentration N-type region 3b is in contact with the low-concentration N-type region LNb. Therefore, in one first high-concentration N-type region 2, a plurality of second high-concentration N-type regions (second high-concentration N-type regions 3a, 3b) and a plurality of low-concentration N-type regions (low-concentration N-type regions LNa, 1b) are stacked.

[0061] In the configuration of the fourth embodiment, by increasing the number of source electrodes, it is possible to increase the area efficiency and increase the current compared to the configuration of the first embodiment, and it becomes possible to adjust the size of the transistor.

[0062] (Modification of the fourth embodiment) In the fourth embodiment, the structure has two low-concentration N-type regions LNa,1b and two second high-concentration N-type regions 3a,3b, but the present invention is not limited to this. That is, for example, as shown in Figures 30 and 31, the structure may have four low-concentration N-type regions LNa to 1d and four second high-concentration N-type regions 3a to 3d. With this configuration, it is possible to increase the area efficiency and the current, as compared to the configuration of the fourth embodiment, and it is possible to adjust the size of the transistors.

[0063] Fifth embodiment 32 and 33, the semiconductor device according to the fifth embodiment differs from the first embodiment in that the surface where the first high-concentration N-type region 2 is connected to the drain electrode and the surface where the second high-concentration N-type region 3 is connected to the source electrode are at different heights. In addition, the two surfaces are at different heights when viewed from a direction perpendicular to the stacking direction. In the following description, a description of the parts common to the first embodiment will be omitted.

[0064] The first high concentration N-type region 2 is formed to include only the bottom region 2b. A portion of the bottom region 2b that does not face the low-concentration N-type region LN, the gate electrode 4, the first insulating film 5a, the second insulating film 5b, and the third insulating film 5c in the stacking direction is connected to the drain electrode. The configuration of the fifth embodiment makes it possible to improve the degree of freedom in designing a semiconductor device.

[0065] Sixth embodiment 34, the semiconductor device according to the sixth embodiment differs from the first embodiment in that the gate electrode 4 has a portion facing the low-concentration N-type region LN and a portion not facing the low-concentration N-type region LN when viewed from the stacking direction, and in that the semiconductor device has a fourth insulating film 5d. In the following description, the description of the parts common to the first embodiment will be omitted.

[0066] The gate electrode 4 faces three of the four faces adjacent to the two faces in contact with the first high concentration N-type region 2 and the second high concentration N-type region 3 of the lightly doped N-type region LN.

[0067] The fourth insulating film 5d is in contact with the low-concentration N-type region LN, the first high-concentration N-type region 2, the second high-concentration N-type region 3, the gate electrode 4, the first insulating film 5a, the second insulating film 5b, and the third insulating film 5c in a direction perpendicular to the stacking direction. The fourth insulating film 5d is made of, for example, at least one of silicon oxide, silicon nitride, and hafnium oxide. In the sixth embodiment, a case will be described in which silicon oxide is used as the material of the fourth insulating film 5d.

[0068] In the configuration of the sixth embodiment, the gate potential is controlled from three directions with respect to the channel formed in the low-concentration N-type region LN. Note that the gate potential may be controlled from one or two directions with respect to the channel. Moreover, with the configuration of the sixth embodiment, it is possible to improve the degree of freedom in designing the semiconductor device.

[0069] Seventh embodiment

[0070] As shown in FIG. 35, the semiconductor device of the seventh embodiment differs from the first embodiment in that the shape of the low-concentration N-type region LN is circular when viewed from the stacking direction, and the shape of the gate electrode 4 is also circular when viewed from the stacking direction. Therefore, the shape of the second high-concentration n-type region 3 is also circular when viewed from the stacking direction. In the configuration of the seventh embodiment, the shape of the channel formed in the low-concentration N-type region LN has no sharp corners, so there are no points inside the channel where the electric field is concentrated and the distribution of the electric field is uniform, enabling uniform transistor operation.

[0071] Eighth embodiment The semiconductor device according to the eighth embodiment has a solid-state image sensor SCC, as shown in Fig. 36. In the following description, the description of parts common to the first embodiment may be omitted. The solid-state image sensor SCC includes a first semiconductor layer 260, an interlayer insulating layer 270, a second semiconductor layer 280, an N-type polysilicon pad 290a, and a shared contact 290b.

[0072] The first semiconductor layer 260 is a semiconductor layer in which the pixel circuits 210 are disposed. The pixel circuit 210 includes a photodiode 110, a transfer transistor TR, and a floating diffusion 130. The photodiode 110 photoelectrically converts incident light, and generates and accumulates electric charges according to the amount of light resulting from the photoelectric conversion. One end (anode electrode) of the photodiode 110 (photoelectric conversion element) is grounded, and the other end (cathode electrode) of the photodiode 110 is connected to the source electrode of the transfer transistor TR.

[0073] The transfer transistor TR is disposed between the photodiode 110 and the floating diffusion 130. The drain electrode of the transfer transistor TR is connected to the drain electrode of the reset transistor 140 and the gate electrode of the amplification transistor 150. Moreover, the transfer transistor TR turns on or off the transfer of charges from the photodiode 110 to the floating diffusion 130 in accordance with a drive signal TGR supplied to its gate electrode from a timing control unit (not shown). As shown in FIG. 37, a transfer-side interlayer wiring 310 that penetrates the interlayer insulating layer 270 and the second semiconductor layer 280 is connected to the transfer transistor TR.

[0074] The floating diffusion 130 accumulates the charge transferred from the photodiode 110 via the transfer transistor TR and converts it into a voltage. That is, the signal charge accumulated in the photodiode 110 is transferred to the floating diffusion 130. The floating diffusion 130 is formed at a point (connection point) where the drain electrode of the transfer transistor TR, the source electrode of a reset transistor 140 (described later), and the gate electrode of an amplifier transistor 150 (described later) are connected.

[0075] The interlayer insulating layer 270 is a layer laminated on the first semiconductor layer 260 , and provides insulation between the first semiconductor layer 260 and the second semiconductor layer 280 . The second semiconductor layer 280 is a layer laminated on the interlayer insulating layer 270, and is a semiconductor layer in which the amplification transistor 150 including the semiconductor device SD and the reset transistor 140 are disposed.

[0076] The amplifying transistor 150 is a common-source transistor in which the gate electrode is connected to the floating diffusion 130 and the source electrode is grounded. The N-type polysilicon pad 290a connects the four floating diffusions 130 included in each of the four pixel circuits 210. Note that, in Fig. 36, only two of the four floating diffusions 130 and photodiodes 110 are illustrated. The shared contact 290 b connects the N-type polysilicon pad 290 a and the amplifying transistor 150 .

[0077] The first semiconductor layer 260 also has a plurality of sensor pixels SP that perform photoelectric conversion. The plurality of sensor pixels SP are arranged in a matrix inside a pixel region in the first semiconductor layer 260. In the eighth embodiment, as shown in FIG. 38, a case will be described in which four sensor pixels SP share one readout circuit RC. Here, "shared" refers to the outputs of the four sensor pixels SP being input to a common readout circuit RC.

[0078] Each sensor pixel SP has components in common with each other. In Fig. 38, in order to distinguish the components of each sensor pixel SP from each other, identification numbers (1, 2, 3, 4) are added to the end of the reference numerals of the components of each sensor pixel SP. In the following, when it is necessary to distinguish the components of each sensor pixel SP from each other, the identification numbers are added to the end of the reference numerals of the components of each sensor pixel SP, but when it is not necessary to distinguish the components of each sensor pixel SP from each other, the identification numbers added to the end of the reference numerals indicating the components of each sensor pixel SP are omitted.

[0079] Each sensor pixel SP includes, for example, a photodiode 110, a transfer transistor TR, and a floating diffusion 130. The floating diffusions 130 of the sensor pixels SP sharing one readout circuit RC are electrically connected to each other and to an input terminal of the common readout circuit RC. The readout circuit RC includes, for example, a reset transistor 140, an amplification transistor 150, and a selection transistor 160. The selection transistor 160 may be omitted as necessary. The source of the selection transistor 160 (the output terminal of the readout circuit RC) is electrically connected to a vertical signal line 170. The gate of the selection transistor 160 is electrically connected to a pixel drive line (not shown). The source of the amplification transistor 150 (the output terminal of the readout circuit RC) is electrically connected to the vertical signal line 170. An FD transfer transistor FDG is provided between the source of the reset transistor 140 and the gate of the amplification transistor 150. The gate of the amplification transistor 150 is electrically connected to the source of the FD transfer transistor FDG.

[0080] The FD transfer transistor FDG is used when switching the conversion efficiency. In general, the pixel signal is small when shooting in a dark place. Based on Q=CV, when performing charge-voltage conversion, if the capacitance (FD capacitance C) of the floating diffusion 130 is large, V when converted to a voltage by the amplification transistor 150 becomes small. On the other hand, in a bright place, the pixel signal becomes large, so if the FD capacitance C is not large, the floating diffusion 130 cannot receive the charge of the photodiode 110. Furthermore, the FD capacitance C needs to be large so that V when converted to a voltage by the amplification transistor 150 does not become too large (in other words, so that it becomes small). In consideration of this, when the FD transfer transistor FDG is turned on, the gate capacitance of the FD transfer transistor FDG increases, so that the entire FD capacitance C becomes large. On the other hand, when the FD transfer transistor FDG is turned off, the entire FD capacitance C becomes small. In this way, by switching the FD transfer transistor FDG on and off, the FD capacitance C can be made variable and the conversion efficiency can be switched.

[0081] FIG. 39 shows an example of a connection between a plurality of readout circuits RC and a plurality of vertical signal lines 170. When a plurality of readout circuits RC are arranged side by side in the extension direction of the vertical signal lines 170 (for example, the column direction), a plurality of vertical signal lines 170 may be assigned to each readout circuit RC. For example, as shown in FIG. 39, when four readout circuits RC are arranged side by side in the extension direction of the vertical signal lines 170 (for example, the column direction), a plurality of vertical signal lines 170 may be assigned to each readout circuit RC. In FIG. 39, in order to distinguish each vertical signal line 170, an identification number (1, 2, 3, 4) is added to the end of the reference numeral of each vertical signal line 170.

[0082] 1 and 2, 37 and 40, the semiconductor device SD has a low-concentration N-type region LN, a first high-concentration N-type region 2, a second high-concentration N-type region 3, a gate electrode 4, a shielding electrode 320, a first insulating film 5a, a second insulating film 5b, and a fifth insulating film 5e. Note that the first high-concentration N-type region 2, the second high-concentration N-type region 3, and the second insulating film 5b are omitted from illustration in FIG. 37. The low-concentration N-type region LN has an impurity concentration of, for example, 10 keV / 1E 18 (pcs / cm 2 ) or less. The low-concentration N-type region LN has a rectangular parallelepiped shape.

[0083] The low-concentration N-type region LN is a rectangle having two sides parallel to the stacking direction and two sides perpendicular to the stacking direction when viewed from the stacking direction, which is the direction in which the low-concentration N-type region LN, the first high-concentration N-type region 2, and the second high-concentration N-type region 3 are stacked. The first high-concentration N-type region 2 is formed using a material having a higher impurity concentration than the low-concentration N-type region LN. The first high-concentration N-type region 2 is connected to one of the source electrode and the drain electrode.

[0084] The second high-concentration N-type region 3 is formed using a material having a higher impurity concentration than the low-concentration N-type region LN. The second high-concentration N-type region 3 is connected to the other of the source electrode and the drain electrode. The first high concentration N-type region 2 and the second high concentration N-type region 3 are laminated in a direction perpendicular to the direction in which the first semiconductor layer 260 and the second semiconductor layer 280 are laminated, with the low concentration N-type region LN sandwiched therebetween. In Fig. 40, the direction perpendicular to the direction in which the first semiconductor layer 260 and the second semiconductor layer 280 are laminated is indicated as the "perpendicular direction". The spacer layer 420 shown in Fig. 40 will be described later.

[0085] The gate electrode 4 faces at least a part of the low-concentration N-type region LN. Specifically, the gate electrode 4 faces at least a part of the low-concentration N-type region LN when viewed from the stacking direction and the perpendicular direction. Moreover, the gate electrode 4 is connected to the floating diffusion 130 and electrically connected to the first semiconductor layer 260 by a gate-side interlayer wiring 330 that penetrates the interlayer insulating layer 270 and the second semiconductor layer 280. The gate-side interlayer wiring 330 is a wiring that electrically connects the gate electrode 4 and the first semiconductor layer 260. Furthermore, the gate electrode 4 is formed in an L-shape having two orthogonal sides when viewed from the stacking direction. One of the two sides of the gate electrode 4 faces the side CNb farther from the first semiconductor layer 260 out of the two sides (CNa, CNb) parallel to the stacking direction of the low-concentration N-type region LN when viewed from the stacking direction. The other of the two sides of the gate electrode 4 faces the side CNc closer to the gate-side interlayer wiring 330 out of the two sides (CNc, CNd) perpendicular to the stacking direction of the low-concentration N-type region LN when viewed from the stacking direction.

[0086] The shielding electrode 320 faces at least a part of the low-concentration N-type region LN different from the part facing the gate electrode 4. Specifically, the shielding electrode 320 faces at least a part of the low-concentration N-type region LN when viewed from the stacking direction and the perpendicular direction. The shielding electrode 320 faces at least a part of the low-concentration N-type region LN different from the part facing the gate electrode 4. Moreover, the shielding electrode 320 is electrically connected to a portion (for example, a semiconductor layer not shown in the figure that is stacked above the second semiconductor layer 280) different from the first semiconductor layer 260 and the second semiconductor layer 280, for example, by using the shielding-side wiring 340. Note that the shielding-side wiring 340 is wiring that electrically connects the shielding electrode 320 to a semiconductor layer different from the first semiconductor layer 260 and the second semiconductor layer 280. In the eighth embodiment, a configuration in which a fixed potential such as a GND potential is set to the shielding electrode 320 by connecting the shielding side wiring 340 to the shielding electrode 320 will be described. Furthermore, the shielding electrode 320 is formed in an L-shape having two orthogonal sides when viewed from the stacking direction. One of the two sides of the shielding electrode 320 faces the side CNa, which is closer to the first semiconductor layer 260, of the two sides parallel to the stacking direction of the low-concentration N-type region LN when viewed from the stacking direction. The other of the two sides of the shielding electrode 320 faces the side CNd, which is closer to the transfer-side interlayer wiring 310, of the two sides perpendicular to the stacking direction of the low-concentration N-type region LN when viewed from the stacking direction. As a result, the gate electrode 4 and the shielding electrode 320 face the four sides (CNa to CNd) of the low-concentration N-type region LN when viewed from the stacking direction in which the low-concentration N-type region LN, the first high-concentration N-type region 2, and the second high-concentration N-type region 3 are stacked.

[0087] The first insulating film 5a is disposed between the gate electrode 4 and the low-concentration N-type region LN. The second insulating film 5b is disposed between the gate electrode 4 and the first high-concentration N-type region 2. The fifth insulating film 5e is disposed between the shielding electrode 320 and the low-concentration N-type region LN. The fifth insulating film 5e is made of, for example, at least one of silicon oxide, silicon nitride, and hafnium oxide.

[0088] <Manufacturing process of solid-state imaging devices> A manufacturing process for manufacturing the solid-state imaging device SCC of the eighth embodiment will be described using FIGS. 41 to 55 while referring to FIGS. 36 to 40. In the manufacturing process of the solid-state imaging device SCC, first, as shown in Fig. 41, a first interlayer insulating film 270a and a second interlayer insulating film 270b for forming the interlayer insulating layer 270 are formed on a first semiconductor substrate 260a (formed using, for example, Si) for forming the first semiconductor layer 260. The first interlayer insulating film 270a is formed of, for example, an oxide film. The second interlayer insulating film 270b is formed of, for example, an oxide film or a nitride film. 42, a fifth basic insulating film 410 for forming a fifth insulating film 5e is formed on a channel semiconductor substrate 400 (formed using, for example, Si) for forming a low-concentration N-type region LN. The fifth basic insulating film 410 is formed using, for example, an oxide film.

[0089] 43, a shielding electrode material layer 320a for forming the shielding electrode 320 is formed on the entire surface of the fifth basic insulating film 410 opposite to the surface facing the channel semiconductor substrate 400. The shielding electrode material layer 320a is formed using, for example, polycrystalline silicon. 44, a third interlayer insulating film 270c is formed on the entire surface of the shielding electrode material layer 320a opposite to the surface facing the fifth basic insulating film 410, to form the interlayer insulating layer 270 by bonding the second interlayer insulating film 270b to the entire surface. The third interlayer insulating film 270c is formed of, for example, an oxide film.

[0090] Then, as shown in FIG. 45, the stack of the channel semiconductor substrate 400, the fifth basic insulating film 410, the shielding electrode material layer 320a, and the third interlayer insulating film 270c is reversed in the stacking direction, and further, as shown in FIG. 46, the third interlayer insulating film 270c and the second interlayer insulating film 270b are bonded together. Next, as shown in FIG. 47, the channel semiconductor substrate 400 is polished to a thickness for forming the low-concentration N-type region LN, and then, as shown in FIG. 48, the channel semiconductor substrate 400 and the fifth basic insulating film 410 are etched while leaving a region corresponding to the low-concentration N-type region LN.

[0091] Furthermore, as shown in FIG. 49, the shielding electrode material layer 320a is etched, leaving a portion that forms one of the two sides of the shielding electrode 320. 50, a second-layer material insulating film 280a for forming the second semiconductor layer 280 is formed on the entire surface of the third interlayer insulating film 270c opposite to the surface facing the second interlayer insulating film 270b, so as to entirely bury the channel semiconductor substrate 400, the fifth basic insulating film 410, and the shielding electrode material layer 320a. The second-layer material insulating film 280a is formed of, for example, an oxide film.

[0092] Thereafter, as shown in FIG. 51, portions of the second-layer material insulating film 280a where the gate electrode 4 and the shielding electrode 320 are to be formed that face two sides (CNc, CNd) perpendicular to the stacking direction of the low-concentration N-type region LN are engraved. Next, as shown in FIG. 52, the first insulating film 5a and the fifth lateral insulating film 411, which is a portion of the fifth insulating film 5e that, together with the fifth base insulating film 410, forms the fifth insulating film 5e, are deposited.

[0093] 53, a gate side electrode material 4a is deposited on a portion where the gate electrode 4 is to be formed. A shielding side electrode material 320b is deposited on a portion where the other of the two sides of the shielding electrode 320 is to be formed. 54, a spacer layer 420 is formed on each of two surfaces continuous with the surface facing the low-concentration N-type region LN on one of the two sides of the gate electrode 4. Furthermore, a first high-concentration N-type region 2 and a second high-concentration N-type region 3 are formed by, for example, using an ion implantation method in a portion facing the low-concentration N-type region LN in the stacking direction. 55, a third layer material insulating film 280b for forming the second semiconductor layer 280 together with the second layer material insulating film 280a is formed so as to bury the gate electrode 4 and the spacer layer 420. The third layer material insulating film 280b is formed of, for example, an oxide film. Furthermore, contact holes communicating with the gate electrode 4 and the shielding electrode 320 are formed, and a gate-side interlayer wiring 330 and a shielding-side wiring 340 are formed using a conductor (for example, tungsten).

[0094] In the configuration of the eighth embodiment, the electrodes (gate electrode 4, shielding electrode 320) facing the low-concentration N-type region LN are divided into two, and a fixed potential is set to the shielding electrode 320, making it possible to shield the electric field from the adjacent structures of different potentials (transfer-side interlayer wiring 310, gate-side interlayer wiring 330). This makes it possible to suppress a decrease in threshold voltage that occurs when the same bias is applied to the low-concentration N-type region LN from all directions. Furthermore, in the configuration of the eighth embodiment, by setting the shielding electrode 320 to a potential different from that of the gate electrode 4 (a potential different from the GND potential), for example, it becomes possible to arbitrarily control the threshold voltage. The decrease in the threshold voltage occurs due to the following factors. If the low-concentration N-type region LN and the opposing electrode are an integrated structure that is not divided, the opposing electrodes function as their respective back gates, and the bias amount required to cancel and invert the space charge in the channel (low-concentration N-type region LN) decreases, resulting in a significant decrease in the threshold voltage, making it difficult to control the threshold voltage within an appropriate range.

[0095] (Modification of the eighth embodiment) In the eighth embodiment, for example, as shown in FIG. 37, a gap is provided between the gate electrode 4 and the gate side interlayer wiring 330. However, this is not limited to this, and the gate electrode 4 and the gate side interlayer wiring 330 may be in contact with each other.

[0096] Ninth embodiment 56, the solid-state imaging element according to the ninth embodiment differs from the eighth embodiment in the configurations of the gate electrode 4 and the shielding electrode 320. In the following description, the description of the parts common to the eighth embodiment may be omitted. The gate electrode 4 is formed in a C-shape having two parallel sides and one side perpendicular to the two parallel sides when viewed from the stacking direction. The two parallel sides of the gate electrode 4 face two sides (CNa, CNb) parallel to the stacking direction of the low-concentration N-type region LN when viewed from the stacking direction. The side perpendicular to the two parallel sides of the gate electrode 4 faces one side CNc closer to the gate-side interlayer wiring 330 out of two sides (CNc, CNd) perpendicular to the stacking direction of the low-concentration N-type region LN when viewed from the stacking direction.

[0097] The shielding electrode 320 is formed with only one straight side when viewed from the stacking direction. The one side of the shielding electrode 320 faces the side CNd that is closer to the transfer-side interlayer wiring 310 out of two sides (CNc, CNd) that are perpendicular to the stacking direction of the low-concentration N-type region LN when viewed from the stacking direction. As a result, the gate electrode 4 and the shielding electrode 320 face the four sides (CNa to CNd) of the low-concentration N-type region LN when viewed from the stacking direction in which the low-concentration N-type region LN, the first high-concentration N-type region 2, and the second high-concentration N-type region 3 are stacked.

[0098] In the configuration of the ninth embodiment, the electrodes (gate electrode 4, shielding electrode 320) facing the low-concentration N-type region LN are divided into two, and a fixed potential is set to the shielding electrode 320, making it possible to shield the electric field from the adjacent structures of different potentials (transfer-side interlayer wiring 310, gate-side interlayer wiring 330). This makes it possible to suppress a decrease in threshold voltage that occurs when the same bias is applied to the low-concentration N-type region LN from all directions. Furthermore, in the configuration of the ninth embodiment, by setting the shielding electrode 320 to a potential different from that of the gate electrode 4 (a potential different from the GND potential), it becomes possible to arbitrarily control the threshold voltage.

[0099] Tenth embodiment 57, the solid-state imaging element according to the tenth embodiment differs from the eighth embodiment in the configurations of the gate electrode 4 and the shielding electrode 320. In the following description, the description of the parts common to the eighth embodiment may be omitted. The gate electrode 4 is formed in an L-shape having two orthogonal sides when viewed from the stacking direction. One of the two sides of the gate electrode 4 faces the side CNa that is closer to the first semiconductor layer 260 among the two sides (CNa, CNb) parallel to the stacking direction of the low-concentration N-type region LN when viewed from the stacking direction. The other of the two sides of the gate electrode 4 faces the side CNc that is closer to the gate-side interlayer wiring 330 among the two sides (CNc, CNd) perpendicular to the stacking direction of the low-concentration N-type region LN when viewed from the stacking direction.

[0100] The shielding electrode 320 is formed with only one straight side when viewed from the stacking direction. The one side of the shielding electrode 320 faces the side CNd that is closer to the transfer-side interlayer wiring 310 out of two sides (CNc, CNd) that are perpendicular to the stacking direction of the low-concentration N-type region LN when viewed from the stacking direction. As a result, the gate electrode 4 and the shielding electrode 320 face three sides (CNa, CNc, CNd) of the low-concentration N-type region LN when viewed from the stacking direction in which the low-concentration N-type region LN, the first high-concentration N-type region 2, and the second high-concentration N-type region 3 are stacked.

[0101] In the configuration of the tenth embodiment, the electrodes (gate electrode 4, shielding electrode 320) facing the low-concentration N-type region LN are divided into two, and a fixed potential is set to the shielding electrode 320, making it possible to shield the electric field from the adjacent structures of different potentials (transfer-side interlayer wiring 310, gate-side interlayer wiring 330). This makes it possible to suppress a decrease in threshold voltage that occurs when the same bias is applied to the low-concentration N-type region LN from all directions. Furthermore, in the configuration of the tenth embodiment, by setting the shielding electrode 320 to a potential different from that of the gate electrode 4 (a potential different from the GND potential), for example, it becomes possible to arbitrarily control the threshold voltage.

[0102] Eleventh embodiment 58, the solid-state imaging element according to the eleventh embodiment differs from the eighth embodiment in the configurations of the gate electrode 4 and the shielding electrode 320. In the following description, the description of the parts common to the eighth embodiment may be omitted. The gate electrode 4 is formed with only one straight side as viewed from the stacking direction. The one side of the gate electrode 4 faces the side CNc closer to the gate-side interlayer interconnect 330 out of two sides (CNc, CNd) perpendicular to the stacking direction of the low-concentration N-type region LN as viewed from the stacking direction.

[0103] The shielding electrode 320 is formed in an L-shape having two orthogonal sides when viewed from the stacking direction. One of the two sides of the shielding electrode 320 faces the side CNa that is closer to the first semiconductor layer 260, out of the two sides (CNa, CNb) parallel to the stacking direction of the low-concentration N-type region LN when viewed from the stacking direction. The other of the two sides of the shielding electrode 320 faces the side CNd that is closer to the transfer-side interlayer wiring 310, out of the two sides (CNc, CNd) perpendicular to the stacking direction of the low-concentration N-type region LN. As a result, the gate electrode 4 and the shielding electrode 320 face three sides (CNa, CNc, CNd) of the low-concentration N-type region LN when viewed from the stacking direction in which the low-concentration N-type region LN, the first high-concentration N-type region 2, and the second high-concentration N-type region 3 are stacked.

[0104] In the configuration of the eleventh embodiment, the electrodes (gate electrode 4, shielding electrode 320) facing the low-concentration N-type region LN are divided into two, and a fixed potential is set to the shielding electrode 320, making it possible to shield the electric field from the adjacent structures of different potentials (transfer-side interlayer wiring 310, gate-side interlayer wiring 330). This makes it possible to suppress a decrease in threshold voltage that occurs when the same bias is applied to the low-concentration N-type region LN from all directions. Furthermore, in the configuration of the eleventh embodiment, by setting the shielding electrode 320 to a potential different from that of the gate electrode 4 (a potential different from the GND potential), it becomes possible to arbitrarily control the threshold voltage.

[0105] Twelfth embodiment As shown in Fig. 59, the solid-state imaging element according to the twelfth embodiment differs from the eighth embodiment in the configurations of the gate electrode 4, the shielding electrode 320, and the fifth insulating film 5e. In the following description, the description of the parts common to the eighth embodiment may be omitted. In the solid-state imaging device SCC according to the twelfth embodiment, the gate electrode 4 and the shielding electrode 320 are integrated together. The integrated gate electrode 4 and the shielding electrode 320 are formed in a rectangular cylindrical shape when viewed from the stacking direction, and surround the low-concentration N-type region LN.

[0106] The gate electrode 4 has two parallel sides when viewed from the stacking direction. The two parallel sides of the gate electrode 4 face two sides (CNa, CNb) of the low-concentration N-type region LN that are parallel to the stacking direction when viewed from the stacking direction. The shielding electrode 320 has two parallel sides when viewed from the stacking direction. The two parallel sides of the shielding electrode 320 face two sides (CNc, CNd) of the low-concentration n-type region LN that are perpendicular to the stacking direction when viewed from the stacking direction. The fifth insulating film 5e is thicker than the first insulating film 5a. In the twelfth embodiment, a configuration in which the fifth insulating film 5e is twice or more as thick as the first insulating film 5a will be described as an example.

[0107] In the configuration of the twelfth embodiment, by making the fifth insulating film 5e thicker than the first insulating film 5a, even if the length of the shielding electrode 320 varies, the channel length of the low-concentration N-type region LN is defined by the structural dimension along the orthogonal direction to the gate electrode 4. For this reason, it is possible to suppress the variation in the characteristics of the amplifying transistor 150 caused by the variation in the length of the shielding electrode 320. Moreover, in the configuration of the twelfth embodiment, it is possible to shield the electric field from the adjacent structures of different potentials (the transfer-side interlayer wiring 310 and the gate-side interlayer wiring 330) by the shielding electrode 320. This makes it possible to suppress a decrease in the threshold voltage caused by applying the same bias to the low-concentration N-type region LN from all directions.

[0108] Thirteenth embodiment 60, the solid-state imaging element according to the thirteenth embodiment differs from the eighth embodiment in the configurations of the gate electrode 4, the first high-concentration N-type region 2, and the second high-concentration N-type region 3. In the following description, the description of the parts common to the eighth embodiment may be omitted.

[0109] The gate electrode 4 has a low concentration region facing portion 4L and a high concentration region facing portion 4H. The low-concentration region facing portion 4L is a portion facing the low-concentration N-type region LN. The distance between the low-concentration region facing portion 4L and the low-concentration N-type region LN is uniform. The high-concentration region facing portion 4H is a portion facing the first high-concentration N-type region 2 and the second high-concentration N-type region 3. Further, a gate-side inclined portion 500a is formed in the high-concentration region facing portion 4H. The gate side inclined portion 500a is formed in such a shape that the surface of the gate electrode 4 facing the first high concentration N-type region 2 and the second high concentration N-type region 3 becomes more distant from the first high concentration N-type region 2 and the second high concentration N-type region 3 as it moves away from the center of the gate electrode 4.

[0110] In the first high-concentration N-type region 2, a first high-concentration side inclined portion 500b is formed in a portion facing the gate electrode 4. The first high-concentration side inclined portion 500b is formed in a shape such that the surface of the first high-concentration side inclined portion 500b facing the gate electrode 4 becomes more distant from the gate electrode 4 as it becomes farther away from the low-concentration n-type region LN. In the second high-concentration N-type region 3, a second high-concentration side inclined portion 500c is formed in a portion facing the gate electrode 4. The second high-concentration side inclined portion 500c is formed in a shape such that the surface of the second high-concentration side inclined portion 500c facing the gate electrode 4 becomes more distant from the gate electrode 4 as it becomes farther from the low-concentration n-type region LN.

[0111] As a result, in the solid-state imaging element of the 13th embodiment, the distance over which the high-concentration region opposing portion 4H faces the first high-concentration N-type region 2 and the second high-concentration N-type region 3 is longer than the distance over which the low-concentration region opposing portion 4L faces the low-concentration N-type region LN.

[0112] <Manufacturing process of solid-state imaging devices> A manufacturing process for manufacturing the solid-state imaging device SCC of the thirteenth embodiment will be described with reference to FIG. 60 and FIG. In the manufacturing process of the solid-state imaging device SCC, as shown in Fig. 61, a protective film 500d is formed on the low-concentration N-type region LN, the first high-concentration N-type region 2, and the second high-concentration N-type region 3. Thereafter, a gate side inclined portion 500a is formed on a portion of the gate electrode 4 facing the first high-concentration N-type region 2 and the second high-concentration N-type region 3, for example, by using isotropic etching. Furthermore, a first high-concentration side inclined portion 500b is formed on a portion of the first high-concentration N-type region 2 facing the gate electrode 4. In addition, a second high-concentration side inclined portion 500c is formed on a portion of the second high-concentration N-type region 3 facing the gate electrode 4. Thereafter, for example, a layer for burying the lightly doped N-type region LN and the first and second heavily doped N-type regions 2 and 3 is formed using silicon oxide.

[0113] In the configuration of the thirteenth embodiment, the parasitic capacitance of the gate electrode 4 can be reduced by removing, by etching, a part of the gate electrode 4 overlapping with the first high concentration N-type region 2 and the second high concentration N-type region 3 connected to the source electrode and the drain electrode. This makes it possible to suppress a decrease in efficiency when converting an optical signal into an electric signal by the pixel circuit 210. In addition, the closer the distance between the first high-concentration N-type region 2 and the second high-concentration N-type region 3 and the gate electrode 4, the greater the parasitic capacitance between the first high-concentration N-type region 2 and the second high-concentration N-type region 3 and the gate electrode 4. This reduces the efficiency of conversion from an optical signal to an electric signal by the pixel circuit 210.

[0114] (Modification of the thirteenth embodiment) In the thirteenth embodiment, the solid-state imaging element is configured such that the distance between the gate electrode 4 and the first high-concentration N-type region 2 and the second high-concentration N-type region 3 is longer than the distance between the gate electrode 4 and the low-concentration N-type region LN, but the present invention is not limited to this. That is, the distance between the gate electrode 4 and at least one of the first high-concentration N-type region 2 and the second high-concentration N-type region 3 and the gate electrode 4 may be longer than the distance between the gate electrode 4 and the low-concentration N-type region LN.

[0115] Fourteenth embodiment The fourteenth embodiment will be described in detail below with reference to the drawings. The description will be made in the following order. 1. Embodiment (imaging device having a stacked structure of three substrates) 2. Modification 1 (Planar Configuration Example 1) 3. Modification 2 (Planar Configuration Example 2) 4. Modification 3 (Planar Configuration Example 3) 5. Modification 4 (Example in which a contact portion between substrates is provided in the center of the pixel array portion) 6. Modification 5 (Example with Planar Type Transfer Transistor) 7. Modification 6 (Example in which one pixel is connected to one pixel circuit) 8. Modification 7 (Example of the configuration of the pixel separation unit) 9. Application Examples (Imaging Systems) 10. Application Examples

[0116] <1. Preferred embodiment> [Functional configuration of imaging device 1] FIG. 62 is a block diagram showing an example of a functional configuration of an imaging device (imaging device 1) according to an embodiment of the present disclosure.

[0117] The imaging device 1 in FIG. 62 includes, for example, an input section 510A, a row driver section 520, a timing control section 530, a pixel array section 540, a column signal processing section 550, an image signal processing section 560, and an output section 510B.

[0118] In the pixel array section 540, pixels 541 are repeatedly arranged in an array. More specifically, a pixel sharing unit 539 including a plurality of pixels is a repeating unit, and this is repeatedly arranged in an array having a row direction and a column direction. In this specification, for convenience, the row direction may be called the H direction, and the column direction perpendicular to the row direction may be called the V direction. In the example of FIG. 62, one pixel sharing unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). Each of the pixels 541A, 541B, 541C, and 541D has a photodiode PD (illustrated in FIG. 67, etc., which will be described later). The pixel sharing unit 539 is a unit that shares one pixel circuit (pixel circuit 210 in FIG. 64, which will be described later). In other words, one pixel circuit (pixel circuit 210, which will be described later) is included for every four pixels (pixels 541A, 541B, 541C, and 541D). By operating this pixel circuit in a time-division manner, pixel signals of the pixels 541A, 541B, 541C, and 541D are sequentially read out. The pixels 541A, 541B, 541C, and 541D are arranged in, for example, 2 rows and 2 columns. In the pixel array section 540, a plurality of row driving signal lines 542 and a plurality of vertical signal lines (column readout lines) 543 are provided in addition to the pixels 541A, 541B, 541C, and 541D. The row driving signal line 542 drives the pixels 541 included in each of a plurality of pixel sharing units 539 arranged in a row direction in the pixel array section 540. The row driving signal line 542 drives each pixel arranged in a row direction among the pixel sharing units 539. As will be described in detail later with reference to FIG. 65, the pixel sharing unit 539 is provided with a plurality of transistors. In order to drive each of these transistors, a plurality of row driving signal lines 542 are connected to one pixel sharing unit 539. The pixel sharing unit 539 is connected to the vertical signal line (column readout line) 543. Pixel signals are read out via the vertical signal line (column readout line) 543 from each of the pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539.

[0119] The row driving unit 520 includes, for example, a row address control unit that determines the position of the row for driving the pixels, in other words, a row decoder unit, and a row driving circuit unit that generates signals for driving the pixels 541A, 541B, 541C, and 541D.

[0120] The column signal processing unit 550 includes, for example, a load circuit unit that is connected to the vertical signal line 543 and forms a source follower circuit together with the pixels 541A, 541B, 541C, and 541D (pixel sharing units 539). The column signal processing unit 550 may include an amplifier circuit unit that amplifies a signal read out from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing unit 550 may include a noise processing unit. In the noise processing unit, for example, a system noise level is removed from the signal read out from the pixel sharing unit 539 as a result of photoelectric conversion.

[0121] The column signal processing unit 550 has, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, the signal read from the pixel sharing unit 539 or the analog signal that has been subjected to the noise processing is converted into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. In the comparator unit, the analog signal to be converted is compared with a reference signal to be compared therewith. In the counter unit, the time until the comparison result in the comparator unit is inverted is measured. The column signal processing unit 550 may include a horizontal scanning circuit unit that controls scanning of the readout column.

[0122] The timing control section 530 supplies signals for controlling timing to the row driving section 520 and the column signal processing section 550 based on a reference clock signal and a timing control signal input to the device.

[0123] The image signal processing unit 560 is a circuit that performs various signal processing on data obtained as a result of photoelectric conversion, in other words, data obtained as a result of the imaging operation in the imaging device 1. The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may also include a processor unit.

[0124] One example of signal processing executed by the image signal processing unit 560 is a tone curve correction process that imparts more gradation to the AD converted imaging data when the data is of a dark subject, and reduces the gradation when the data is of a bright subject. In this case, it is desirable to store in advance in the data storage unit of the image signal processing unit 560 characteristic data of the tone curve based on which the gradation of the imaging data is to be corrected.

[0125] The input section 510A is for inputting, for example, the above-mentioned reference clock signal, timing control signal, characteristic data, and the like from outside the device to the imaging device 1. The timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal. The characteristic data is, for example, for storage in a data holding section of the image signal processing section 560. The input section 510A includes, for example, an input terminal 511, an input circuit section 512, an input amplitude changing section 513, an input data conversion circuit section 514, and a power supply section (not shown).

[0126] The input terminal 511 is an external terminal for inputting data. The input circuit unit 512 is for taking in the signal input to the input terminal 511 into the inside of the imaging device 1. The input amplitude change unit 513 changes the amplitude of the signal taken in by the input circuit unit 512 to an amplitude that is easily used inside the imaging device 1. The input data conversion circuit unit 514 changes the arrangement of the data string of the input data. The input data conversion circuit unit 514 is composed of, for example, a serial-parallel conversion circuit. In this serial-parallel conversion circuit, a serial signal received as input data is converted into a parallel signal. Note that, in the input unit 510A, the input amplitude change unit 513 and the input data conversion circuit unit 514 may be omitted. The power supply unit supplies power set to various voltages required inside the imaging device 1 based on a power source supplied from the outside to the imaging device 1.

[0127] When the imaging device 1 is connected to an external memory device, the input unit 510A may be provided with a memory interface circuit that receives data from the external memory device. The external memory device may be, for example, a flash memory, an SRAM, or a DRAM.

[0128] The output unit 510B outputs image data to the outside of the device. This image data is, for example, image data captured by the imaging device 1 and image data signal-processed by the image signal processing unit 560. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude change unit 516, an output circuit unit 517, and an output terminal 518.

[0129] The output data conversion circuit unit 515 is configured, for example, by a parallel-serial conversion circuit, and the output data conversion circuit unit 515 converts the parallel signal used inside the imaging device 1 into a serial signal. The output amplitude change unit 516 changes the amplitude of the signal used inside the imaging device 1. The signal with the changed amplitude can be easily used by an external device connected to the outside of the imaging device 1. The output circuit unit 517 is a circuit that outputs data from inside the imaging device 1 to the outside of the device, and the output circuit unit 517 drives a wiring outside the imaging device 1 connected to an output terminal 518. The output terminal 518 outputs data from the imaging device 1 to the outside of the device. In the output unit 510B, the output data conversion circuit unit 515 and the output amplitude change unit 516 may be omitted.

[0130] When the imaging device 1 is connected to an external memory device, the output unit 510B may be provided with a memory interface circuit that outputs data to the external memory device. The external memory device may be, for example, a flash memory, an SRAM, or a DRAM.

[0131] [Schematic configuration of imaging device 1] FIG. 63 and FIG. 64 show an example of a schematic configuration of the imaging device 1. The imaging device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). FIG. 63 shows a schematic planar configuration of each of the first substrate 100, the second substrate 200, and the third substrate 300, and FIG. 64 shows a schematic cross-sectional configuration of the first substrate 100, the second substrate 200, and the third substrate 300 stacked on top of each other. FIG. 64 corresponds to the cross-sectional configuration along line III-III' shown in FIG. 63. The imaging device 1 is a three-dimensional imaging device formed by bonding three substrates (the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the interlayer insulating film around it is called the wiring layer (100T, 200T, 300T) provided on each substrate (the first substrate 100, the second substrate 200, and the third substrate 300) for convenience. The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order, and the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor layer 300S are arranged in this order along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. The arrow shown in FIG. 64 indicates the incident direction of the light L to the imaging device 1. In this specification, for convenience, in the following cross-sectional views, the light incident side of the imaging device 1 may be referred to as "bottom", "lower side", or "downward", and the side opposite the light incident side may be referred to as "upper side", "upper side", or "upper". Also, in this specification, for convenience, with respect to a substrate having a semiconductor layer and a wiring layer, the wiring layer side may be referred to as the front side, and the semiconductor layer side may be referred to as the back side. Note that the description in the specification is not limited to the above names. The imaging device 1 is, for example, a back-illuminated imaging device in which light is incident from the back side of the first substrate 100 having a photodiode.

[0132] The pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are both configured using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C, and 541D that the pixel sharing unit 539 has. Each of these pixels 541 has a photodiode (a photodiode PD described later) and a transfer transistor (a transfer transistor TR described later). The second substrate 200 is provided with a pixel circuit (a pixel circuit 210 described later) that the pixel sharing unit 539 has. The pixel circuit reads out pixel signals transferred from the photodiodes of the pixels 541A, 541B, 541C, and 541D via the transfer transistors, or resets the photodiodes. In addition to such pixel circuits, the second substrate 200 has a plurality of row driving signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 further has a power supply line 544 extending in the row direction. The third substrate 300 has, for example, an input section 510A, a row driver 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B. The row driver 520 is provided, for example, in a region where a part of the row driver 520 overlaps with the pixel array section 540 in the stacking direction (hereinafter, simply referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, the row driver 520 is provided in a region where the row driver 520 overlaps with the vicinity of an end of the pixel array section 540 in the H direction in the stacking direction (FIG. 63). The column signal processing section 550 is provided, for example, in a region where a part of the row driver 520 overlaps with the pixel array section 540 in the stacking direction. More specifically, the column signal processing section 550 is provided in a region overlapping the vicinity of an end portion in the V direction of the pixel array section 540 in the stacking direction (FIG. 63). Although not shown, the input section 510A and the output section 510B may be disposed in a portion other than the third substrate 300, for example, on the second substrate 200. Alternatively, the input section 510A and the output section 510B may be provided on the back surface (light incident surface) side of the first substrate 100.The pixel circuits provided on the second substrate 200 may also be called pixel transistor circuits, pixel transistor groups, pixel transistors, pixel readout circuits, or readout circuits. In this specification, the term pixel circuits is used.

[0133] The first substrate 100 and the second substrate 200 are electrically connected by, for example, through electrodes (through electrodes 120E, 121E in FIG. 67 described later). The second substrate 200 and the third substrate 300 are electrically connected by, for example, contact portions 201, 202, 301, 302. The second substrate 200 is provided with contact portions 201, 202, and the third substrate 300 is provided with contact portions 301, 302. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R in which a plurality of contact portions 201 are provided, and a contact region 202R in which a plurality of contact portions 202 are provided. The third substrate 300 has a contact region 301R in which a plurality of contact parts 301 are provided, and a contact region 302R in which a plurality of contact parts 302 are provided. The contact regions 201R, 301R are provided between the pixel array section 540 and the row driver section 520 in the stacking direction (FIG. 64). In other words, the contact regions 201R, 301R are provided, for example, in a region where the row driver section 520 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap in the stacking direction, or in a region nearby the region. The contact regions 201R, 301R are disposed, for example, at the end in the H direction of such a region (FIG. 63). In the third substrate 300, for example, the contact region 301R is provided at a position that overlaps with a part of the row driver section 520, specifically, the end in the H direction of the row driver section 520 (FIGS. 63 and 64). The contact sections 201 and 301 connect, for example, the row driving section 520 provided on the third substrate 300 and the row driving signal line 542 provided on the second substrate 200. The contact sections 201 and 301 may connect, for example, the input section 510A provided on the third substrate 300 to a power supply line 544 and a reference potential line (a reference potential line VSS described later). The contact regions 202R and 302R are provided between the pixel array section 540 and the column signal processing section 550 in the stacking direction (FIG. 64).In other words, the contact regions 202R and 302R are provided in, for example, a region where the column signal processing section 550 (the third substrate 300) and the pixel array section 540 (the second substrate 200) overlap in the stacking direction, or in a region adjacent thereto. The contact regions 202R and 302R are arranged, for example, at the end in the V direction of such a region (FIG. 63). In the third substrate 300, for example, the contact region 301R is provided at a position overlapping a part of the column signal processing section 550, specifically, an end in the V direction of the column signal processing section 550 (FIGS. 63 and 64). The contact sections 202 and 302 are for connecting, for example, pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion in the photodiodes) output from each of the multiple pixel sharing units 539 of the pixel array section 540 to the column signal processing section 550 provided on the third substrate 300. The pixel signals are sent from the second substrate 200 to the third substrate 300.

[0134] FIG. 64 is an example of a cross-sectional view of the imaging device 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the imaging device 1 has an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300. Specifically, the contact portions 201, 202, 301, and 302 are formed with electrodes formed of a conductive material. The conductive material is formed of a metal material such as copper (Cu), aluminum (Al), and gold (Au). The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate and the third substrate by directly joining wirings formed as electrodes, for example, to each other, thereby enabling input and / or output of signals between the second substrate 200 and the third substrate 300.

[0135] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided at a desired location. For example, as described as the contact regions 201R, 202R, 301R, and 302R in FIG. 64, the electrical connection portion may be provided in a region that overlaps with the pixel array section 540 in the stacking direction. The electrical connection portion may also be provided in a region that does not overlap with the pixel array section 540 in the stacking direction. Specifically, the electrical connection portion may be provided in a region that overlaps with a peripheral portion disposed outside the pixel array section 540 in the stacking direction.

[0136] The first substrate 100 and the second substrate 200 are provided with, for example, connection holes H1 and H2. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200 (FIG. 64). The connection holes H1 and H2 are provided outside the pixel array section 540 (or a portion overlapping the pixel array section 540) (FIG. 63). For example, the connection hole H1 is disposed outside the pixel array section 540 in the H direction, and the connection hole H2 is disposed outside the pixel array section 540 in the V direction. For example, the connection hole H1 reaches the input section 510A provided on the third substrate 300, and the connection hole H2 reaches the output section 510B provided on the third substrate 300. The connection holes H1 and H2 may be hollow or may contain a conductive material at least in part. For example, there is a configuration in which a bonding wire is connected to an electrode formed as the input section 510A and / or the output section 510B. Alternatively, there is a configuration in which an electrode formed as the input section 510A and / or the output section 510B is connected to a conductive material provided in the connection holes H1, H2. The conductive material provided in the connection holes H1, H2 may be embedded in a part or all of the connection holes H1, H2, or the conductive material may be formed on the side walls of the connection holes H1, H2.

[0137] 64 shows a structure in which the input section 510A and the output section 510B are provided on the third substrate 300, but the present invention is not limited to this. For example, the input section 510A and / or the output section 510B can be provided on the second substrate 200 by sending a signal of the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T. Similarly, the input section 510A and / or the output section 510B can be provided on the first substrate 100 by sending a signal of the second substrate 200 to the first substrate 1000 via the wiring layers 100T and 200T.

[0138] FIG. 65 is an equivalent circuit diagram showing an example of the configuration of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 (four pixels 541, 541A, 541B, 541C, and 541D, are shown in FIG. 65), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 5433 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors, specifically, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FD. As described above, the pixel sharing unit 539 is configured to sequentially output pixel signals of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543 by operating one pixel circuit 210 in a time-division manner. A state in which one pixel circuit 210 is connected to multiple pixels 541 and the pixel signals of the multiple pixels 541 are output in a time-division manner by the single pixel circuit 210 is said to be "multiple pixels 541 sharing one pixel circuit 210."

[0139] The pixels 541A, 541B, 541C, and 541D have components in common with each other. Hereinafter, in order to distinguish the components of the pixels 541A, 541B, 541C, and 541D from each other, the identification number 1 is added to the end of the reference numeral of the component of the pixel 541A, the identification number 2 is added to the end of the reference numeral of the component of the pixel 541B, the identification number 3 is added to the end of the reference numeral of the component of the pixel 541C, and the identification number 4 is added to the end of the reference numeral of the component of the pixel 541D. When it is not necessary to distinguish the components of the pixels 541A, 541B, 541C, and 541D from each other, the identification numbers at the end of the reference numerals of the components of the pixels 541A, 541B, 541C, and 541D are omitted.

[0140] The pixels 541A, 541B, 541C, and 541D each have, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. In the photodiodes PD (PD1, PD2, PD3, and PD4), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (for example, ground). The photodiode PD photoelectrically converts incident light and generates a charge according to the amount of light received. The transfer transistors TR (transfer transistors TR1, TR2, TR3, and TR4) are, for example, n-type CMOS (Complementary Metal Oxide Semiconductor) transistors. In the transfer transistor TR, the drain is electrically connected to the floating diffusion FD, and the gate is electrically connected to a drive signal line. This drive signal line is a part of a plurality of row drive signal lines 542 (see FIG. 62) connected to one pixel sharing unit 539. The transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusions FD1, FD2, FD3, FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding means that temporarily holds the charge transferred from the photodiode PD, and is also a charge-voltage conversion means that generates a voltage according to the amount of charge.

[0141] The four floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) included in one pixel shared unit 539 are electrically connected to each other and to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel shared unit 539. The drain of the reset transistor RST is connected to a power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. This drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel shared unit 539. The gate of the amplification transistor AMP is connected to the floating diffusion FD, the drain of the amplification transistor AMP is connected to the power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to a vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539 .

[0142] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. The gate (transfer gate TG) of the transfer transistor TR includes, for example, a so-called vertical electrode, and is provided extending from the surface of the semiconductor layer (semiconductor layer 100S in FIG. 67 described later) to a depth reaching the PD, as shown in FIG. 67 described later. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates, as the pixel signal, a signal of a voltage according to the level of the charge held in the floating diffusion FD. The amplification transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. In the column signal processing unit 550, the amplification transistor AMP configures a source follower together with a load circuit unit (see FIG. 62) connected to the vertical signal line 543. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type CMOS transistors.

[0143] The FD conversion gain switching transistor FDG is used to change the gain of the charge-voltage conversion in the floating diffusion FD. In general, the pixel signal is small when shooting in a dark place. Based on Q=CV, when performing charge-voltage conversion, if the capacitance (FD capacitance C) of the floating diffusion FD is large, V when converted to voltage by the amplification transistor AMP will be small. On the other hand, in a bright place, the pixel signal becomes large, so if the FD capacitance C is not large, the floating diffusion FD cannot receive the charge of the photodiode PD. Furthermore, the FD capacitance C needs to be large so that V when converted to voltage by the amplification transistor AMP does not become too large (in other words, so that it becomes small). In consideration of this, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, so the overall FD capacitance C becomes large. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C becomes small. In this way, by switching the FD conversion gain switching transistor FDG on and off, the FD capacitance C can be made variable and the conversion efficiency can be switched. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0144] It is also possible to configure the pixel circuit 210 without providing the FD conversion gain switching transistor FDG. In this case, for example, the pixel circuit 210 is composed of three transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 has at least one pixel transistor, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.

[0145] The selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542 (see FIG. 62). The source of the amplification transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Although not shown in the figure, the number of pixels 541 sharing one pixel circuit 210 may be other than four. For example, two or eight pixels 541 may share one pixel circuit 210.

[0146] FIG. 66 shows an example of a connection between a plurality of pixel sharing units 539 and a vertical signal line 543. For example, four pixel sharing units 539 arranged in a column direction are divided into four groups, and a vertical signal line 543 is connected to each of the four groups. For the sake of simplicity, FIG. 66 shows an example in which each of the four groups has one pixel sharing unit 539, but each of the four groups may include a plurality of pixel sharing units 539. In this way, in the imaging device 1, a plurality of pixel sharing units 539 arranged in a column direction may be divided into groups including one or more pixel sharing units 539. For example, a vertical signal line 543 and a column signal processing circuit 550 are connected to each of the groups, so that pixel signals can be read out simultaneously from each group. Alternatively, in the imaging device 1, one vertical signal line 543 may be connected to a plurality of pixel sharing units 539 arranged in a column direction. In this case, pixel signals are read out sequentially in a time-division manner from the plurality of pixel sharing units 539 connected to one vertical signal line 543.

[0147] [Specific configuration of imaging device 1] FIG. 67 shows an example of a cross-sectional configuration perpendicular to the main surfaces of the first substrate 100, the second substrate 100, and the third substrate 300 of the imaging device 1. FIG. 67 is a schematic representation for making it easier to understand the positional relationship of the components, and may differ from the actual cross section. In the imaging device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. The imaging device 1 further has a light receiving lens 401 on the back side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may be provided between the light receiving lens 401 and the first substrate 100. The light receiving lens 401 is provided, for example, for each of the pixels 541A, 541B, 541C, and 541D. The imaging device 1 is, for example, a back-illuminated imaging device. The imaging device 1 has a pixel array section 540 arranged in the center and a peripheral section 540B arranged outside the pixel array section 540.

[0148] The first substrate 100 has, in order from the light receiving lens 401 side, an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T. The semiconductor layer 100S is made of, for example, a silicon substrate. The semiconductor layer 100S has, for example, a p-well layer 115 in a part of the surface (the surface on the wiring layer 100T side) and in the vicinity thereof, and has an n-type semiconductor region 114 in the other region (region deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 form a pn junction type photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0149] Fig. 68A shows an example of the planar configuration of the first substrate 100. Fig. 68A mainly shows the planar configuration of the pixel separation portion 117, the photodiode PD, the floating diffusion FD, the VSS contact region 118, and the transfer transistor TR of the first substrate 100. The configuration of the first substrate 100 will be described using Fig. 68A together with Fig. 67.

[0150] A floating diffusion FD and a VSS contact region 118 are provided near the surface of the semiconductor layer 100S. The floating diffusion FD is composed of an n-type semiconductor region provided in the p-well layer 115. The floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) of the pixels 541A, 541B, 541C, and 541D are provided close to each other in the center of the pixel sharing unit 539 (FIG. 68A), for example. Although details will be described later, the four floating diffusions (floating diffusions FD1, FD2, FD3, FD4) included in this pixel sharing unit 539 are electrically connected to each other via electrical connection means (pad section 120 described later) in the first substrate 100 (more specifically, in the wiring layer 100T). Furthermore, the floating diffusion FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via an electrical means (a through electrode 120E described below). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG by this electrical means.

[0151] The VSS contact region 118 is a region electrically connected to the reference potential line VSS, and is arranged apart from the floating diffusion FD. For example, in the pixels 541A, 541B, 541C, and 541D, the floating diffusion FD is arranged at one end of each pixel in the V direction, and the VSS contact region 118 is arranged at the other end (FIG. 68A). The VSS contact region 118 is, for example, composed of a p-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. This allows a reference potential to be supplied to the semiconductor layer 100S.

[0152] The first substrate 100 is provided with a transfer transistor TR together with a photodiode PD, a floating diffusion FD, and a VSS contact region 118. The photodiode PD, the floating diffusion FD, the VSS contact region 118, and the transfer transistor TR are provided in each of the pixels 541A, 541B, 541C, and 541D. The transfer transistor TR is provided on the front surface side (the side opposite to the light incident surface side, the second substrate 200 side) of the semiconductor layer 100S. The transfer transistor TR has a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the front surface of the semiconductor layer 100S and a vertical portion TGa provided in the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end is provided in the n-type semiconductor region 114. By configuring the transfer transistor TR with such a vertical transistor, transfer failure of pixel signals is less likely to occur, and the readout efficiency of pixel signals can be improved.

[0153] The horizontal part TGb of the transfer gate TG extends from a position facing the vertical part TGa toward, for example, the center of the pixel sharing unit 539 in the H direction (FIG. 68A). This allows the H direction position of the through electrode (through electrode TGV described below) that reaches the transfer gate TG to be closer to the H direction positions of the through electrodes (through electrodes 120E, 121E described below) connected to the floating diffusion FD and the VSS contact region 118. For example, the multiple pixel sharing units 539 provided on the first substrate 100 have the same configuration (FIG. 68A).

[0154] The semiconductor layer 100S is provided with a pixel separator 117 that separates the pixels 541A, 541B, 541C, and 541D from one another. The pixel separator 117 is formed extending in a normal direction of the semiconductor layer 100S (a direction perpendicular to the surface of the semiconductor layer 100S). The pixel separator 117 is provided to separate the pixels 541A, 541B, 541C, and 541D from one another, and has, for example, a lattice-like planar shape (FIGS. 68A and 68B). The pixel separator 117 electrically and optically separates the pixels 541A, 541B, 541C, and 541D from one another. The pixel separator 117 includes, for example, a light-shielding film 117A and an insulating film 117B. The light-shielding film 117A is made of, for example, tungsten (W) or the like. The insulating film 117B is provided between the light shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B is made of, for example, silicon oxide (SiO). The pixel separator 117 has, for example, a full trench isolation (FTI) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separator 117 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, it may have a deep trench isolation (DTI) structure that does not penetrate the semiconductor layer 100S. The pixel separator 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial region of the semiconductor layer 100S.

[0155] The semiconductor layer 100S is provided with, for example, a first pinning region 113 and a second pinning region 116. The first pinning region 113 is provided near the back surface of the semiconductor layer 100S, and is disposed between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on a side surface of the pixel separating section 117, specifically, between the pixel separating section 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 are formed of, for example, a p-type semiconductor region.

[0156] A fixed charge film 112 having a negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111. A first pinning region 113 of the hole accumulation layer is formed at the interface on the light-receiving surface (rear surface) side of the semiconductor layer 100S due to an electric field induced by the fixed charge film 112. This suppresses the generation of dark current due to the interface state on the light-receiving surface side of the semiconductor layer 100S. The fixed charge film 112 is formed, for example, of an insulating film having a negative fixed charge. Examples of materials for the insulating film having a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0157] A light-shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. This light-shielding film 117A may be provided continuously with the light-shielding film 117A constituting the pixel separating section 117. The light-shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided, for example, at a position facing the pixel separating section 117 in the semiconductor layer 100S. The insulating film 111 is provided so as to cover this light-shielding film 117A. The insulating film 111 is made of, for example, silicon oxide.

[0158] The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 has an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124 in this order from the semiconductor layer 100S side. The horizontal portion TGb of the transfer gate TG is provided in this wiring layer 100T, for example. The interlayer insulating film 119 is provided over the entire surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 is made of, for example, a silicon oxide film. The configuration of the wiring layer 100T is not limited to the above, and may be any configuration having wiring and an insulating film.

[0159] FIG. 68B shows the configuration of the pad sections 120 and 121 together with the planar configuration shown in FIG. 68A. The pad sections 120 and 121 are provided in selective regions on the interlayer insulating film 119. The pad section 120 is for connecting the floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D to each other. The pad section 120 is disposed, for example, in the center of the pixel sharing unit 539 in plan view for each pixel sharing unit 539 (FIG. 68B). This pad section 120 is disposed so as to straddle the pixel separating section 117, and is disposed so as to overlap at least a portion of each of the floating diffusions FD1, FD2, FD3, and FD4 (FIGS. 67 and 68B). Specifically, the pad section 120 is formed in a region that overlaps at least a portion of each of the plurality of floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) that share the pixel circuit 210 and at least a portion of the pixel separation section 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, PD4) that share the pixel circuit 210 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection via 120C for electrically connecting the pad section 120 and the floating diffusions FD1, FD2, FD3, FD4. The connection via 120C is provided in each of the pixels 541A, 541B, 541C, 541D. For example, a portion of the pad section 120 is embedded in the connection via 120C, so that the pad section 120 and the floating diffusions FD1, FD2, FD3, FD4 are electrically connected.

[0160] The pad portion 121 is for connecting the multiple VSS contact regions 118 to each other. For example, the VSS contact regions 118 provided in the pixels 541C and 541D of one pixel sharing unit 539 adjacent to each other in the V direction and the VSS contact regions 118 provided in the pixels 541A and 541B of the other pixel sharing unit 539 are electrically connected by the pad portion 121. The pad portion 121 is provided, for example, so as to straddle the pixel separation portion 117, and is arranged so as to overlap at least a part of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps at least a part of each of the multiple VSS contact regions 118 and at least a part of the pixel separation portion 117 formed between the multiple VSS contact regions 118 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection via 121C for electrically connecting the pad portion 121 and the VSS contact region 118. The connection via 121C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, a part of the pad portion 121 is embedded in the connection via 121C, thereby electrically connecting the pad portion 121 and the VSS contact region 118. For example, the pad portion 120 and the pad portion 121 of each of the multiple pixel sharing units 539 aligned in the V direction are disposed at approximately the same position in the H direction ( FIG. 68B ).

[0161] By providing the pad section 120, it is possible to reduce the wiring for connecting each floating diffusion FD to the pixel circuit 210 (for example, the gate electrode of the amplification transistor AMP) in the entire chip. Similarly, by providing the pad section 121, it is possible to reduce the wiring for supplying a potential to each VSS contact region 118 in the entire chip. This makes it possible to reduce the area of ​​the entire chip, suppress electrical interference between wiring in miniaturized pixels, and / or reduce costs by reducing the number of components.

[0162] The pads 120 and 121 can be provided at desired positions on the first substrate 100 and the second substrate 200. Specifically, the pads 120 and 121 can be provided on either the wiring layer 100T or the insulating region 212 of the semiconductor layer 200S. When provided on the wiring layer 100T, the pads 120 and 121 may be directly in contact with the semiconductor layer 100S. Specifically, the pads 120 and 121 may be directly connected to at least a part of each of the floating diffusion FD and / or the VSS contact region 118. Alternatively, the pads 120 and 121 may be provided at desired positions in the insulating region 2112 of the wiring layer 100T and the semiconductor layer 200S by providing connection vias 120C and 121C from each of the floating diffusion FD and / or the VSS contact region 118 connected to the pads 120 and 121.

[0163] In particular, when the pad portions 120, 121 are provided in the wiring layer 100T, it is possible to reduce the number of wirings connected to the floating diffusion FD and / or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 200S. This makes it possible to reduce the area of ​​the insulating region 212 for forming the through wiring for connecting the floating diffusion FD to the pixel circuit 210, among the second substrate 200 for forming the pixel circuit 210. Therefore, it is possible to secure a large area for the second substrate 200 for forming the pixel circuit 210. By securing the area for the pixel circuit 210, it is possible to form a large pixel transistor, which can contribute to improving image quality by reducing noise, etc.

[0164] In particular, when an FTI structure is used for the pixel separation section 117, it is preferable to provide a floating diffusion FD and / or a VSS contact region 118 in each pixel 541, and therefore, by using the configuration of the pad sections 120, 121, the wiring connecting the first substrate 100 and the second substrate 200 can be significantly reduced.

[0165] 68B, for example, the pad section 120 to which the floating diffusions FD are connected and the pad section 121 to which the VSS contact regions 118 are connected are alternately arranged in a straight line in the V direction. The pad sections 120 and 121 are formed at positions surrounded by the photodiodes PD, the transfer gates TG, and the floating diffusions FD. This allows elements other than the floating diffusions FD and the VSS contact regions 118 to be freely arranged on the first substrate 100 on which the elements are formed, and the layout of the entire chip can be made more efficient. In addition, symmetry in the layout of the elements formed in each pixel sharing unit 539 is ensured, and the variation in the characteristics of each pixel 541 can be suppressed.

[0166] The pad parts 120 and 121 are made of, for example, polysilicon (Poly Si), more specifically, doped polysilicon to which impurities are added. The pad parts 120 and 121 are preferably made of a conductive material with high heat resistance, such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride (TiN). This makes it possible to form the pixel circuit 210 after bonding the semiconductor layer 200S of the second substrate 200 to the first substrate 100. The reason for this will be explained below. In the following explanation, the method of forming the pixel circuit 210 after bonding the semiconductor layer 200S of the first substrate 100 to the semiconductor layer 200S of the second substrate 200 is called the first manufacturing method.

[0167] Here, it is also conceivable to form the pixel circuits 210 on the second substrate 200 and then bond it to the first substrate 100 (hereinafter referred to as the second manufacturing method). In this second manufacturing method, electrodes for electrical connection are formed in advance on the surface of the first substrate 100 (surface of the wiring layer 100T) and the surface of the second substrate 200 (surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are bonded together, the electrodes for electrical connection formed on the surfaces of the first substrate 100 and the second substrate 200 come into contact with each other at the same time. As a result, an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by configuring the imaging device 1 using the second manufacturing method, it is possible to manufacture the imaging device using an appropriate process according to the configuration of each of the first substrate 100 and the second substrate 200, for example, and it is possible to manufacture a high-quality, high-performance imaging device.

[0168] In such a second manufacturing method, when the first substrate 100 and the second substrate 200 are bonded together, an alignment error may occur due to a manufacturing device for bonding. In addition, the first substrate 100 and the second substrate 200 have a diameter of, for example, several tens of centimeters, and when the first substrate 100 and the second substrate 200 are bonded together, the substrates may expand and contract in microscopic regions of the first substrate 100 and the second substrate 200. This expansion and contraction of the substrates is caused by a slight difference in the timing at which the substrates contact each other. Due to such expansion and contraction of the first substrate 100 and the second substrate 200, an error may occur in the position of the electrodes for electrical connection formed on the surface of the first substrate 100 and the surface of the second substrate 200. In the second manufacturing method, it is preferable to take measures so that the electrodes of the first substrate 100 and the second substrate 200 contact each other even if such an error occurs. Specifically, at least one, and preferably both, of the electrodes of the first substrate 100 and the second substrate 200 are made large in consideration of the above-mentioned error. Therefore, when the second manufacturing method is used, for example, the size (size in the substrate planar direction) of the electrode formed on the surface of the first substrate 100 or the second substrate 200 becomes larger than the size of the internal electrode extending in the thickness direction from the inside of the first substrate 100 or the second substrate 200 to the surface.

[0169] On the other hand, by forming the pad parts 120, 121 from a heat-resistant conductive material, it becomes possible to use the first manufacturing method. In the first manufacturing method, after forming the first substrate 100 including the photodiode PD and the transfer transistor TR, the first substrate 100 and the second substrate 200 (semiconductor layer 2000S) are bonded together. At this time, the second substrate 200 is in a state in which the patterns of the active elements and wiring layers constituting the pixel circuits 210 have not yet been formed. Since the second substrate 200 is in a state before the patterns are formed, even if an error occurs in the bonding position when the first substrate 100 and the second substrate 200 are bonded together, this bonding error does not cause an error in the alignment between the pattern of the first substrate 100 and the pattern of the second substrate 200. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are bonded together. When forming a pattern on the second substrate, for example, an exposure device for pattern formation performs pattern formation while using the pattern formed on the first substrate as a target for alignment. For the above reasons, errors in the bonding positions of the first substrate 100 and the second substrate 200 do not pose a problem in manufacturing the imaging device 1 in the first manufacturing method. For the same reason, errors caused by expansion and contraction of the substrates in the second manufacturing method do not pose a problem in manufacturing the imaging device 1 in the first manufacturing method.

[0170] In the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together in this manner, active elements are formed on the second substrate 200. After that, the through electrodes 120E, 121E and the through electrodes TGV (FIG. 67) are formed. In forming the through electrodes 120E, 121E, and TGV, for example, a pattern of the through electrodes is formed from above the second substrate 200 using reduced projection exposure by an exposure device. Since reduced projection exposure is used, even if an error occurs in the alignment between the second substrate 200 and the exposure device, the magnitude of the error is only a fraction (the reciprocal of the reduced projection magnification) of the error in the second substrate 200 in the second manufacturing method. Therefore, by configuring the imaging device 1 using the first manufacturing method, it becomes easier to align the elements formed on the first substrate 100 and the second substrate 200, and a high-quality, high-performance imaging device can be manufactured.

[0171] The imaging device 1 manufactured using such a first manufacturing method has different characteristics from the imaging device manufactured using the second manufacturing method. Specifically, in the imaging device 1 manufactured using the first manufacturing method, for example, the through electrodes 120E, 121E, and TGV have a substantially constant thickness (size in the substrate plane direction) from the second substrate 200 to the first substrate 100. Alternatively, when the through electrodes 120E, 121E, and TGV have a tapered shape, they have a tapered shape with a constant inclination. The imaging device 1 having such through electrodes 120E, 121E, and TGV makes it easy to miniaturize the pixels 541.

[0172] Here, when the imaging device 1 is manufactured by the first manufacturing method, since the active elements are formed on the second substrate 200 after bonding the first substrate 100 and the second substrate 200 (semiconductor layer 200S), the first substrate 100 is also affected by the heat treatment required for forming the active elements. For this reason, as described above, it is preferable to use a conductive material with high heat resistance for the pad parts 120, 121 provided on the first substrate 100. For example, it is preferable to use a material with a higher melting point (i.e., higher heat resistance) for the pad parts 120, 121 than at least a part of the wiring material included in the wiring layer 200T of the second substrate 200. For example, a conductive material with high heat resistance such as doped polysilicon, tungsten, titanium, or titanium nitride is used for the pad parts 120, 121. This makes it possible to manufacture the imaging device 1 by using the first manufacturing method described above.

[0173] The passivation film 122 is provided over the entire surface of the semiconductor layer 100S so as to cover the pad portions 120 and 121 (FIG. 67). The passivation film 122 is made of, for example, a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 with the passivation film 122 therebetween. This interlayer insulating film 123 is provided over the entire surface of the semiconductor layer 100S. The interlayer insulating film 123 is made of, for example, a silicon oxide (SiO) film. The bonding film 124 is provided on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. This bonding film 124 is provided over the entire main surface of the first substrate 100. The bonding film 124 is made of, for example, a silicon nitride film.

[0174] The light receiving lens 401 faces, for example, the semiconductor layer 100S with the fixed charge film 112 and the insulating film 111 therebetween (FIG. 67). The light receiving lens 401 is provided, for example, at a position facing the photodiode PD of each of the pixels 541A, 541B, 541C, and 541D.

[0175] The second substrate 200 has a semiconductor layer 200S and a wiring layer 200T in this order from the first substrate 100 side. The semiconductor layer 200S is made of a silicon substrate. A well region 211 is provided in the semiconductor layer 200S across the thickness direction. The well region 211 is, for example, a p-type semiconductor region. The second substrate 200 is provided with a pixel circuit 210 arranged for each pixel sharing unit 539. The pixel circuit 210 is provided, for example, on the front surface side (the wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 such that the back surface side (the semiconductor layer 200S side) of the second substrate 200 faces the front surface side (the wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is bonded to the first substrate 100 face-to-back.

[0176] 69 to 73 show an example of the planar configuration of the second substrate 200. FIG. 69 shows the configuration of the pixel circuit 210 provided near the surface of the semiconductor layer 200S. FIG. 70 shows the configuration of the wiring layer 200T (specifically, the first wiring layer W1 described later), the semiconductor layer 200S connected to the wiring layer 200T, and each part of the first substrate 100. FIG. 71 to FIG. 73 show an example of the planar configuration of the wiring layer 200T. Hereinafter, the configuration of the second substrate 200 will be described with reference to FIG. 67 and FIG. 69 to FIG. 73. In FIG. 69 and FIG. 70, the outline of the photodiode PD (the boundary between the pixel isolation section 117 and the photodiode PD) is shown by a dashed line, and the boundary between the semiconductor layer 200S and the element isolation region 213 or the insulating region 214 in the portion overlapping the gate electrode of each transistor constituting the pixel circuit 210 is shown by a dotted line. In the portion overlapping the gate electrode of the amplifying transistor AMP, a boundary between the semiconductor layer 200S and the element isolation region 213 and a boundary between the element isolation region 213 and the insulating region 212 are provided on one side in the channel width direction.

[0177] The second substrate 200 is provided with an insulating region 212 that divides the semiconductor layer 200S and an element isolation region 213 provided in a part of the semiconductor layer 200S in the thickness direction (FIG. 67). For example, in the insulating region 212 provided between two pixel circuits 210 adjacent to each other in the H direction, the through electrodes 120E, 121E and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) of two pixel sharing units 539 connected to the two pixel circuits 210 are arranged (FIG. 70).

[0178] The insulating region 212 has approximately the same thickness as the semiconductor layer 200S (FIG. 67). The semiconductor layer 200S is divided by this insulating region 212. The through electrodes 120E, 121E and the through electrodes TGV are arranged in this insulating region 212. The insulating region 212 is made of, for example, silicon oxide.

[0179] The through electrodes 120E, 121E are provided penetrating the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E, 121E are connected to the wirings (first wiring W1, second wiring W2, third wiring W3, and fourth wiring W4 described later) of the wiring layer 200T. The through electrodes 120E, 121E are provided penetrating the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and the lower ends are connected to the pad parts 120, 121 (FIG. 67). The through electrodes 120E are for electrically connecting the pad part 120 and the pixel circuit 210. That is, the floating diffusion FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 by the through electrodes 120E. The through electrode 121E is for electrically connecting the pad portion 121 and the reference potential line VSS of the wiring layer 200T. That is, the through electrode 121E electrically connects the VSS contact region 118 of the first substrate 100 to the reference potential line VSS of the second substrate 200.

[0180] The through electrode TGV is provided to penetrate the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring layer 200T. This through electrode TGV is provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and its lower end is connected to the transfer gate TG (FIG. 67). Such a through electrode TGV is for electrically connecting the transfer gate TG (transfer gates TG1, TG2, TG3, TG4) of each of the pixels 541A, 541B, 541C, 541D to the wiring of the wiring layer 200T (a part of the row driving signal line 542, specifically, the wirings TRG1, TRG2, TRG3, TRG4 in FIG. 72 described later). That is, the transfer gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 by the through electrode TGV, so that a drive signal is sent to each of the transfer transistors TR (transfer transistors TR1, TR2, TR3, TR4).

[0181] The insulating region 212 is a region for providing the through electrodes 120E, 121E and the through electrodes TGV for electrically connecting the first substrate 100 and the second substrate 200 insulated from the semiconductor layer 200S. For example, the through electrodes 120E, 121E and the through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) connected to the two pixel circuits 210 (shared units 539) adjacent to each other in the H direction are provided in the insulating region 212 provided between the two pixel circuits 210 (shared units 539). The insulating region 212 is provided, for example, extending in the V direction (FIGS. 69 and 70). Here, the position of the through electrodes TGV in the H direction is arranged closer to the position of the through electrodes 120E, 121E in the H direction than the position of the vertical part TGa by devising the arrangement of the horizontal part TGb of the transfer gate TG (FIGS. 68A and 70). For example, the through electrode TGV is disposed at approximately the same position as the through electrodes 120E, 120E in the H direction. This allows the through electrodes 120E, 121E and the through electrode TGV to be provided together in the insulating region 212 extending in the V direction. As another arrangement example, it is possible to provide the horizontal part TGb only in the region overlapping the vertical part TGa. In this case, the through electrode TGV is formed approximately directly above the vertical part TGa, and the through electrode TGV is disposed, for example, in the approximately center of each pixel 541 in the H direction and the V direction. At this time, the position of the through electrode TGV in the H direction and the position of the through electrodes 120E, 121E in the H direction are largely shifted. For example, an insulating region 212 is provided around the through electrodes TGV and the through electrodes 120E, 121E to electrically insulate them from the adjacent semiconductor layer 200S. When the position of the through electrode TGV in the H direction is significantly separated from the positions of the through electrodes 120E, 121E in the H direction, it is necessary to provide an insulating region 212 independently around each of the through electrodes 120E, 121E, and TGV. This results in the semiconductor layer 200S being divided into small pieces. In contrast, a layout in which the through electrodes 120E, 121E and the through electrode TGV are collectively disposed in the insulating region 212 extending in the V direction can increase the size of the semiconductor layer 200S in the H direction. This makes it possible to secure a large area for the semiconductor element formation region in the semiconductor layer 200S.This makes it possible, for example, to increase the size of the amplification transistor AMP and suppress noise.

[0182] As described with reference to FIG. 65, the pixel sharing unit 539 has a structure in which the floating diffusions FD provided in the respective pixels 541 are electrically connected to each other, and the pixels 541 share one pixel circuit 210. The floating diffusions FD are electrically connected to each other by a pad section 120 provided on the first substrate 100 (FIGS. 67 and 68B). The electrical connection section (pad section 120) provided on the first substrate 100 and the pixel circuit 210 provided on the second substrate 200 are electrically connected to each other via one through electrode 120E. As another structural example, it is also possible to provide the electrical connection section between the floating diffusions FD on the second substrate 200. In this case, the pixel sharing unit 539 is provided with four through electrodes connected to the floating diffusions FD1, FD2, FD3, and FD4, respectively. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S increases, and the insulating region 212 that insulates the periphery of these through electrodes becomes larger. In comparison, the structure in which the pad portion 120 is provided in the first substrate 100 (FIGS. 67 and 68B) can reduce the number of through electrodes and make the insulating region 212 smaller. Therefore, a large area can be secured for the semiconductor element formation region in the semiconductor layer 200S. This makes it possible, for example, to increase the size of the amplification transistor AMP and suppress noise.

[0183] The element isolation region 213 is provided on the surface side of the semiconductor layer 200S. The element isolation region 213 has an STI (Shallow Trench Isolation) structure. In the element isolation region 213, the semiconductor layer 200S is dug in the thickness direction (perpendicular to the main surface of the second substrate 200), and an insulating film is embedded in the dug portion. The insulating film is made of, for example, silicon oxide. The element isolation region 213 isolates a plurality of transistors constituting the pixel circuit 210 according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element isolation region 213 (deep in the semiconductor layer 200S).

[0184] Here, with reference to Figures 68A, 68B, and 69, the difference between the outer shape (outer shape in the substrate planar direction) of the pixel sharing unit 539 on the first substrate 100 and the outer shape of the pixel sharing unit 539 on the second substrate 200 will be described.

[0185] In the imaging device 1, a pixel sharing unit 539 is provided across both the first substrate 100 and the second substrate 200. For example, the outer shape of the pixel sharing unit 539 provided on the first substrate 100 and the outer shape of the pixel sharing unit 539 provided on the second substrate 200 are different from each other.

[0186] 68A and 68B, the outlines of the pixels 541A, 541B, 541C, and 541D are indicated by dashed lines, and the outline shape of the pixel sharing unit 539 is indicated by a thick line. For example, the pixel sharing unit 539 of the first substrate 100 is configured with two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction, and two pixels 541 (pixels 541C and 541D) arranged adjacent to each other in the V direction. That is, the pixel sharing unit 539 of the first substrate 100 is configured with four pixels 541 arranged in two rows and two columns adjacent to each other, and the pixel sharing unit 539 of the first substrate 100 has a substantially square outline shape. In the pixel array section 540, such pixel sharing units 539 are arranged adjacent to each other at a two pixel pitch in the H direction (a pitch equivalent to two pixels 541) and at a two pixel pitch in the V direction (a pitch equivalent to two pixels 541).

[0187] In Fig. 69 and Fig. 70, the outlines of the pixels 541A, 541B, 541C, and 541D are indicated by dashed lines, and the outline shape of the pixel sharing unit 539 is indicated by a thick line. For example, the outline shape of the pixel sharing unit 539 of the second substrate 200 is smaller than that of the pixel sharing unit 539 of the first substrate 100 in the H direction, and is larger than that of the pixel sharing unit 539 of the first substrate 100 in the V direction. For example, the pixel sharing unit 539 of the second substrate 200 is formed with a size (area) equivalent to one pixel in the H direction, and is formed with a size equivalent to four pixels in the V direction. That is, the pixel sharing unit 539 of the second substrate 200 is formed with a size equivalent to adjacent pixels arranged in one row x four columns, and the pixel sharing unit 539 of the second substrate 200 has a substantially rectangular outline shape.

[0188] For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged in this order in the V direction (FIG. 69). By providing the outer shape of each pixel circuit 210 in a substantially rectangular shape as described above, it is possible to arrange four transistors (the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG) in one direction (the V direction in FIG. 69). This allows the drain of the amplification transistor AMP and the drain of the reset transistor RST to be shared in one diffusion region (the diffusion region connected to the power supply line VDD). For example, it is also possible to provide the formation region of each pixel circuit 210 in a substantially square shape (see FIG. 82 described later). In this case, two transistors are arranged along one direction, and it becomes difficult to share the drain of the amplification transistor AMP and the drain of the reset transistor RST in one diffusion region. Therefore, by providing the formation region of the pixel circuit 210 in a substantially rectangular shape, it becomes easier to arrange the four transistors close to each other, and the formation region of the pixel circuit 210 can be made smaller. That is, the pixel can be miniaturized. Furthermore, when it is not necessary to reduce the formation area of ​​the pixel circuit 210, it is possible to increase the formation area of ​​the amplification transistor AMP and suppress noise.

[0189] For example, in addition to the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is provided near the surface of the semiconductor layer 200S. The VSS contact region 218 is, for example, configured of a p-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via the wiring of the wiring layer 200T and the through electrode 121E. This VSS contact region 218 is provided, for example, at a position adjacent to the source of the FD conversion gain switching transistor FDG with the element isolation region 213 therebetween (FIG. 69).

[0190] Next, with reference to Fig. 68B and Fig. 69, the positional relationship between the pixel sharing unit 539 provided on the first substrate 100 and the pixel sharing unit 539 provided on the second substrate 200 will be described. For example, one of the two pixel sharing units 539 arranged in the V direction of the first substrate 100 (for example, the upper side of the paper surface in Fig. 68B) is connected to one of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (for example, the left side of the paper surface in Fig. 69). For example, the other of the two pixel sharing units 539 arranged in the V direction of the first substrate 100 (for example, the lower side of the paper surface in Fig. 68B) is connected to the other of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (for example, the right side of the paper surface in Fig. 69).

[0191] For example, of two pixel sharing units 539 arranged in the H direction of the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel sharing unit 539 is substantially equal to a layout obtained by inverting the internal layout of the other pixel sharing unit 539 in the V direction and H direction. The effects obtained by this layout will be described below.

[0192] In two pixel sharing units 539 aligned in the V direction of the first substrate 100, each pad section 120 is disposed at the center of the outer shape of the pixel sharing unit 539, that is, the center of the pixel sharing unit 539 in the V direction and the H direction ( FIG. 68B ). On the other hand, since the pixel sharing unit 539 of the second substrate 200 has an outer shape that is substantially rectangular and elongated in the V direction as described above, for example, the amplification transistor AMP connected to the pad section 120 is disposed at a position shifted upward from the center of the pixel sharing unit 539 in the V direction on the paper. For example, when the internal layouts of two pixel sharing units 539 aligned in the H direction of the second substrate 200 are the same, the distance between the amplification transistor AMP of one pixel sharing unit 539 and the pad section 120 (for example, the pad section 120 of the pixel sharing unit 539 on the upper side of the paper in FIG. 68) becomes relatively short. However, the distance between the amplification transistor AMP of the other pixel sharing unit 539 and the pad section 120 (for example, the pad section 120 of the pixel sharing unit 539 on the lower side of the paper surface of FIG. 68) becomes longer. Therefore, the area of ​​the wiring required to connect this amplification transistor AMP and the pad section 120 becomes larger, and there is a concern that the wiring layout of the pixel sharing unit 539 becomes complicated. This may affect the miniaturization of the imaging device 1.

[0193] In contrast, by inverting the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 at least in the V direction, the distance between the amplifier transistors AMP and the pad section 120 of both of these two pixel sharing units 539 can be shortened. Therefore, compared with a configuration in which the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are the same, it is easier to miniaturize the imaging device 1. Note that the planar layout of each of the multiple pixel sharing units 539 of the second substrate 200 is symmetrical within the range shown in FIG. 69, but becomes asymmetrical when the layout of the first wiring layer W1 shown in FIG. 70 described later is included.

[0194] In addition, it is preferable that the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are also inverted with respect to each other in the H direction. The reason for this will be described below. As shown in FIG. 70, the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are connected to the pad portions 120, 121 of the first substrate 100. For example, the pad portions 120, 121 are disposed in the center portions in the H direction of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (between the two pixel sharing units 539 arranged in the H direction). Therefore, by inverting the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 with respect to each other in the H direction, the distance between each of the multiple pixel sharing units 539 of the second substrate 200 and the pad portions 120, 121 can be reduced. That is, it becomes easier to miniaturize the imaging device 1.

[0195] In addition, the position of the outline of the pixel sharing unit 539 of the second substrate 200 does not have to be aligned with the position of any of the outlines of the pixel sharing unit 539 of the first substrate 100. For example, of the two pixel sharing units 539 arranged in the H direction of the second substrate 200, in one pixel sharing unit 539 (for example, the left side of the paper in FIG. 70), the outline of one side in the V direction (for example, the upper side of the paper in FIG. 70) is disposed outside the outline of one side in the V direction of the corresponding pixel sharing unit 539 of the first substrate 100 (for example, the upper side of the paper in FIG. 68B). In addition, of the two pixel sharing units 539 arranged in the H direction of the second substrate 200, in the other pixel sharing unit 539 (for example, the right side of the paper in FIG. 70), the outline of the other side in the V direction (for example, the lower side of the paper in FIG. 70) is disposed outside the outline of the other side in the V direction of the corresponding pixel sharing unit 539 of the first substrate 100 (for example, the lower side of the paper in FIG. 68B). In this way, by disposing the pixel sharing unit 539 of the second substrate 200 and the pixel sharing unit 539 of the first substrate 100 relative to each other, it is possible to shorten the distance between the amplification transistor AMP and the pad section 120. Therefore, it becomes easier to miniaturize the imaging device 1.

[0196] Furthermore, the positions of the outlines of the multiple pixel sharing units 539 on the second substrate 200 do not need to be aligned with each other. For example, two pixel sharing units 539 aligned in the H direction of the second substrate 200 are arranged with the positions of the outlines in the V direction shifted from each other. This makes it possible to shorten the distance between the amplification transistor AMP and the pad section 120. This makes it easier to miniaturize the imaging device 1.

[0197] With reference to FIG. 68B and FIG. 70, the repeated arrangement of the pixel sharing units 539 in the pixel array section 540 will be described. The pixel sharing unit 539 of the first substrate 100 has a size equivalent to two pixels 541 in the H direction and a size equivalent to two pixels 541 in the V direction (FIG. 68B). For example, in the pixel array section 540 of the first substrate 100, the pixel sharing units 539 having a size equivalent to four pixels 541 are repeatedly arranged adjacent to each other at a two pixel pitch (a pitch equivalent to two pixels 541) in the H direction and at a two pixel pitch (a pitch equivalent to two pixels 541) in the V direction. Alternatively, the pixel array section 540 of the first substrate 100 may be provided with a pair of pixel sharing units 539 in which two pixel sharing units 539 are arranged adjacent to each other in the V direction. In the pixel array section 540 of the first substrate 100, for example, a pair of pixel sharing units 539 are repeatedly arranged adjacent to each other at a two pixel pitch (a pitch equivalent to two pixels 541) in the H direction and a four pixel pitch (a pitch equivalent to four pixels 541) in the V direction. The pixel sharing unit 539 of the second substrate 200 has a size of one pixel 541 in the H direction and a size of four pixels 541 in the V direction ( FIG. 70 ). For example, the pixel array section 540 of the second substrate 200 is provided with a pair of pixel sharing units 539 including two pixel sharing units 539 each having a size equivalent to four pixels 541. The pixel sharing units 539 are arranged adjacent to each other in the H direction and offset from each other in the V direction. In the pixel array section 540 of the second substrate 200, for example, a pair of pixel sharing units 539 are repeatedly arranged adjacent to each other with no gaps at a two pixel pitch (a pitch equivalent to two pixels 541) in the H direction and at a four pixel pitch (a pitch equivalent to four pixels 541) in the V direction. By repeatedly arranging the pixel sharing units 539 in this way, it is possible to arrange the pixel sharing units 539 without any gaps. This makes it easier to miniaturize the imaging device 1.

[0198] It is preferable that the amplification transistor AMP has a three-dimensional structure, such as a Fin type (FIG. 67). This increases the effective gate width, making it possible to suppress noise. The selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG have, for example, a planar structure. The amplification transistor AMP may have a planar structure. Alternatively, the selection transistor SEL, the reset transistor RST, or the FD conversion gain switching transistor FDG may have a three-dimensional structure.

[0199] The wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221 is in contact with, for example, the surface of the semiconductor layer 200S, and covers the entire surface of the semiconductor layer 200S. This passivation film 221 covers the gate electrodes of the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is provided between the passivation film 221 and the third substrate 300. This interlayer insulating film 222 separates the plurality of wirings (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4). The interlayer insulating film 222 is made of, for example, silicon oxide.

[0200] In the wiring layer 200T, for example, from the semiconductor layer 200S side, a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact parts 201, 202 are provided in this order, and these are insulated from each other by an interlayer insulating film 222. In the interlayer insulating film 222, a plurality of connection parts are provided to connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to the layers below them. The connection parts are parts in which a conductive material is embedded in connection holes provided in the interlayer insulating film 222. For example, in the interlayer insulating film 222, a connection part 218V is provided to connect the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S. For example, the hole diameter of such a connection part that connects elements of the second substrate 200 to each other is different from the hole diameters of the through electrodes 120E, 121E and the through electrodes TGV. Specifically, the diameter of the connection hole connecting the elements of the second substrate 200 is preferably smaller than the diameter of the through electrodes 120E, 121E and the through electrode TGV. The reason for this will be described below. The depth of the connection part (connection part 218V, etc.) provided in the wiring layer 200T is smaller than the depth of the through electrodes 120E, 121E and the through electrode TGV. Therefore, the connection part can be filled with a conductive material more easily than the through electrodes 120E, 121E and the through electrode TGV. By making the diameter of the connection part smaller than the diameter of the through electrodes 120E, 121E and the through electrode TGV, it becomes easier to miniaturize the imaging device 1.

[0201] For example, the first wiring layer W1 connects the through electrode 120E to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG (specifically, a connection hole reaching the source of the FD conversion gain switching transistor FDG). The first wiring layer W1 connects, for example, the through electrode 121E to the connection portion 218V, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S to the VSS contact region 118 of the semiconductor layer 100S.

[0202] Next, the planar configuration of the wiring layer 200T will be described with reference to Fig. 71 to Fig. 73. Fig. 71 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2. Fig. 72 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3. Fig. 73 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4.

[0203] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL extending in the H direction (row direction) (FIG. 72). These wirings correspond to the row driving signal lines 542 described with reference to FIG. 65. The wirings TRG1, TRG2, TRG3, and TRG4 are for sending driving signals to the transfer gates TG1, TG2, TG3, and TG4, respectively. The wirings TRG1, TRG2, TRG3, and TRG4 are connected to the transfer gates TG1, TG2, TG3, and TG4 via the second wiring layer W2, the first wiring layer W1, and the through-electrode 120E, respectively. The wiring SELL is for sending a driving signal to the gate of the selection transistor SEL, the wiring RSTL is for sending a driving signal to the gate of the reset transistor RST, and the wiring FDGL is for sending a driving signal to the gate of the FD conversion gain switching transistor FDG, respectively. The wirings SELL, RSTL, and FDGL are each connected to the gates of the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG via the second wiring layer W2, the first wiring layer W1, and a connection portion.

[0204] For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 extending in the V direction (column direction) (FIG. 73). The power supply line VDD is connected to the drain of the amplification transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection part. The reference potential line VSS is connected to the VSS contact region 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection part 218V. The reference potential line VSS is also connected to the VSS contact region 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad part 121. The vertical signal line 543 is connected to the source (Vout) of the selection transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection part.

[0205] The contact parts 201 and 202 may be provided at positions overlapping the pixel array part 540 in a plan view (for example, FIG. 64), or may be provided in the outer peripheral part 540B of the pixel array part 540 (for example, FIG. 67). The contact parts 201 and 202 are provided on the surface of the second substrate 200 (surface on the wiring layer 200T side). The contact parts 201 and 202 are made of metal such as Cu (copper) and Al (aluminum). The contact parts 201 and 202 are exposed on the surface of the wiring layer 200T (surface on the third substrate 300 side). The contact parts 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for bonding the second substrate 200 and the third substrate 300 together.

[0206] Fig. 67 shows an example in which a peripheral circuit is provided in the peripheral portion 540B of the second substrate 200. This peripheral circuit may include a part of the row driving section 520 or a part of the column signal processing section 550. Also, as shown in Fig. 64, the peripheral circuit may not be arranged in the peripheral portion 540B of the second substrate 200, and the connection holes H1 and H2 may be arranged in the vicinity of the pixel array section 540.

[0207] The third substrate 300 has, for example, a wiring layer 300T and a semiconductor layer 300S in this order from the second substrate 200 side. For example, the surface of the semiconductor layer 300S is provided on the second substrate 200 side. The semiconductor layer 300S is made of a silicon substrate. A circuit is provided on the surface side of the semiconductor layer 300S. Specifically, for example, at least a part of the input unit 510A, the row driver 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B is provided on the surface side of the semiconductor layer 300S. The wiring layer 300T provided between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and contact units 301 and 302. The contact parts 301 and 302 are exposed on the surface (surface on the second substrate 200 side) of the wiring layer 300T, and the contact part 301 is in contact with the contact part 201 of the second substrate 200, and the contact part 302 is in contact with the contact part 202 of the second substrate 200. The contact parts 301 and 302 are electrically connected to circuits (for example, at least one of the input part 510A, the row driving part 520, the timing control part 530, the column signal processing part 550, the image signal processing part 560, and the output part 510B) formed in the semiconductor layer 300S. The contact parts 301 and 302 are made of metals such as Cu (copper) and aluminum (Al). For example, the external terminal TA is connected to the input part 510A via the connection hole part H1, and the external terminal TB is connected to the output part 510B via the connection hole part H2.

[0208] Here, the features of the imaging device 1 will be described.

[0209] In general, an imaging device mainly consists of a photodiode and a pixel circuit. Increasing the area of ​​the photodiode increases the charge generated as a result of photoelectric conversion, thereby improving the signal-to-noise ratio (S / N ratio) of the pixel signal, and enabling the imaging device to output better image data (image information). On the other hand, increasing the size of the transistors (especially the size of the amplifying transistors) included in the pixel circuit reduces the noise generated in the pixel circuit, thereby improving the S / N ratio of the imaging signal, and enabling the imaging device to output better image data (image information).

[0210] However, in an imaging device in which a photodiode and a pixel circuit are provided on the same semiconductor substrate, if the area of ​​the photodiode is increased within the limited area of ​​the semiconductor substrate, the size of the transistor in the pixel circuit may be reduced, and if the size of the transistor in the pixel circuit is increased, the area of ​​the photodiode may be reduced.

[0211] To solve these problems, for example, the imaging device 1 of the present embodiment uses a structure in which a plurality of pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged so as to overlap the photodiode PD. This makes it possible to maximize the area of ​​the photodiode PD and to maximize the size of the transistor provided in the pixel circuit 210 within the limited area of ​​the semiconductor substrate. This improves the S / N ratio of the pixel signal, and enables the imaging device 1 to output better image data (image information).

[0212] When realizing a structure in which a plurality of pixels 541 share one pixel circuit 210 and this is arranged to overlap the photodiode PD, a plurality of wirings connected to one pixel circuit 210 extend from the floating diffusion FD of each of the plurality of pixels 541. In order to secure a large area of ​​the semiconductor substrate 200 in which the pixel circuit 210 is formed, for example, a connection wiring can be formed that connects the plurality of extending wirings to each other and combines them into one. Similarly, for the plurality of wirings extending from the VSS contact region 118, a connection wiring can be formed that connects the plurality of extending wirings to each other and combines them into one.

[0213] For example, if a connection wiring that interconnects the multiple wirings extending from the floating diffusion FD of each of the multiple pixels 541 is formed in the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable that the area for forming the transistors included in the pixel circuit 210 will be reduced. Similarly, if a connection wiring that interconnects the multiple wirings extending from the VSS contact region 118 of each of the multiple pixels 541 and combines them into one is formed in the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable that the area for forming the transistors included in the pixel circuit 210 will be reduced.

[0214] In order to solve these problems, for example, the imaging device 1 of this embodiment can have a structure in which a plurality of pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged superimposed on a photodiode PD, and the first substrate 100 can be provided with a connection wiring that interconnects and combines the floating diffusions FD of the plurality of pixels 541, and a connection wiring that interconnects and combines the VSS contact regions 118 provided in each of the plurality of pixels 541.

[0215] Here, when the above-mentioned second manufacturing method is used as a manufacturing method for providing the first substrate 100 with the connection wiring for connecting the floating diffusions FD of the plurality of pixels 541 to one another and the connection wiring for connecting the VSS contact regions 118 of the plurality of pixels 541 to one another, for example, the first substrate 100 and the second substrate 200 can be manufactured using an appropriate process according to the configuration of each substrate, and a high-quality, high-performance imaging device can be manufactured. In addition, the connection wiring of the first substrate 100 and the second substrate 200 can be formed by a simple process. Specifically, when the above-mentioned second manufacturing method is used, an electrode connected to the floating diffusion FD and an electrode connected to the VSS contact region 118 are provided on the surface of the first substrate 100 and the surface of the second substrate 200, which are the bonding interface between the first substrate 100 and the second substrate 200. Furthermore, it is preferable to make the electrodes formed on the surfaces of the two substrates large so that the electrodes can contact each other even if a positional deviation occurs between the electrodes provided on the surfaces of the two substrates when the first substrate 100 and the second substrate 200 are bonded together. In this case, it may become difficult to arrange the electrodes within the limited area of ​​each pixel of the imaging device 1.

[0216] In order to solve the problem of needing a large electrode at the bonding interface between the first substrate 100 and the second substrate 200, for example, the imaging device 1 of this embodiment can use the first manufacturing method described above as a manufacturing method in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged so as to overlap the photodiode PD. This makes it easy to align the elements formed on the first substrate 100 and the second substrate 200, respectively, and allows the manufacturing of a high-quality, high-performance imaging device. Furthermore, it is possible to have a unique structure that is generated by using this manufacturing method. That is, the structure has a semiconductor layer 100S and wiring layer 100T of the first substrate 100 and a semiconductor layer 200S and wiring layer 200T of the second substrate 200 stacked in this order, in other words, a structure in which the first substrate 100 and the second substrate 200 are stacked face-to-back, and has through electrodes 120E, 121E that pass from the surface side of the semiconductor layer 200S of the second substrate 200, through the semiconductor layer 200S and the wiring layer 100T of the first substrate 100, and reach the surface of the semiconductor layer 100S of the first substrate 100.

[0217] In a structure in which a first substrate 100 is provided with connection wiring that interconnects and combines the floating diffusions FD of the multiple pixels 541 into one, and connection wiring that interconnects and combines the VSS contact regions 118 of the multiple pixels 541 into one, if this structure is stacked on a second substrate 200 using the first manufacturing method to form a pixel circuit 210 on the second substrate 200, there is a possibility that the influence of the heating process required when forming the active elements provided in the pixel circuit 210 will extend to the connection wiring formed on the first substrate 100.

[0218] Therefore, in order to solve the problem that the connection wiring is affected by the heat treatment when forming the active element, in the imaging device 1 of the present embodiment, it is desirable to use a conductive material with high heat resistance for the connection wiring that connects the floating diffusions FD of the respective pixels 541 to each other and combines them into one, and for the connection wiring that connects the VSS contact regions 118 of the respective pixels 541 to each other and combines them into one. Specifically, the conductive material with high heat resistance can be a material with a higher melting point than at least a part of the wiring material included in the wiring layer 200T of the second substrate 200.

[0219] In this manner, for example, the imaging device 1 of the present embodiment has: (1) a structure in which the first substrate 100 and the second substrate 200 are stacked face-to-back (specifically, a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked in this order); (2) a structure in which through-electrodes 120E, 121E are provided from the front surface side of the semiconductor layer 200S of the second substrate 200, penetrating the semiconductor layer 200S and the wiring layer 100T of the first substrate 100, and reaching the front surface of the semiconductor layer 100S of the first substrate 100; and (3) a structure in which the floating diffusions FD provided in each of the plurality of pixels 541 are provided. By providing a structure in which the first substrate 100 and the second substrate 200 have a connection wiring that interconnects the floating diffusions FD of the respective pixels 541 and combines them into one, and a connection wiring that interconnects the VSS contact regions 118 of the respective pixels 541 and combines them into one, and a structure in which the connection wiring is formed from a conductive material with high heat resistance, it is possible to provide the first substrate 100 with the connection wiring that interconnects the floating diffusions FD of the respective pixels 541 and combines them into one, and the connection wiring that connects the VSS contact regions 118 of the respective pixels 541 and combines them into one, without providing a large electrode at the interface between the first substrate 100 and the second substrate 200.

[0220] [Operation of imaging device 1] Next, the operation of the imaging device 1 will be described with reference to Figs. 74 and 75. Figs. 74 and 75 are diagrams in which arrows representing the paths of each signal have been added to Fig. 64. Fig. 74 shows the paths of the input signal input from the outside to the imaging device 1, the power supply potential, and the reference potential with arrows. Fig. 75 shows the signal paths of the pixel signals output from the imaging device 1 to the outside with arrows. For example, an input signal (e.g., a pixel clock and a synchronization signal) input to the imaging device 1 via the input section 510A is transmitted to the row driver 520 of the third substrate 300, and a row drive signal is generated in the row driver 520. This row drive signal is sent to the second substrate 200 via the contact sections 301 and 201. Furthermore, this row drive signal reaches each of the pixel shared units 539 of the pixel array section 540 via a row drive signal line 542 in the wiring layer 200T. Among the row driving signals that reach the pixel sharing unit 539 of the second substrate 200, the driving signals other than the transfer gate TG are input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. The driving signal of the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV, and the pixels 541A, 541B, 541C, and 541D are driven (FIG. 74). In addition, the power supply potential and the reference potential supplied to the input section 510A (input terminal 511) of the third substrate 300 from the outside of the imaging device 1 are sent to the second substrate 200 via the contact sections 301 and 201, and are supplied to the pixel circuits 210 of each pixel sharing unit 539 via the wiring in the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121E. Meanwhile, pixel signals photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are sent to the pixel circuit 210 of the second substrate 200 for each pixel sharing unit 539 via the through-electrode 120E. A pixel signal based on this pixel signal is sent from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact units 202 and 302. This pixel signal is processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, and then output to the outside via the output unit 510B.

[0221] [effect] In this embodiment, the pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539) and the pixel circuit 210 are provided on different substrates (first substrate 100 and second substrate 200). This allows the areas of the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 to be enlarged compared to when the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 are formed on the same substrate. As a result, it is possible to increase the amount of pixel signals obtained by photoelectric conversion and reduce the transistor noise of the pixel circuit 210. This improves the signal-to-noise ratio of the pixel signals, and the imaging device 1 can output better pixel data (image information). In addition, it is possible to miniaturize the imaging device 1 (in other words, reduce the pixel size and make the imaging device 1 smaller). The imaging device 1 can increase the number of pixels per unit area by reducing the pixel size, and output a high-quality image.

[0222] In addition, in the imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other by the through electrodes 120E, 121E provided in the insulating region 212. For example, a method of connecting the first substrate 100 and the second substrate 200 by bonding pad electrodes to each other, or a method of connecting by through wiring (for example, TSV (Thorough Si Via)) that penetrates a semiconductor layer can be considered. Compared to such methods, by providing the through electrodes 120E, 121E in the insulating region 212, the area required for connecting the first substrate 100 and the second substrate 200 can be reduced. This reduces the pixel size, and the imaging device 1 can be made more compact. In addition, the resolution can be increased by further miniaturizing the area per pixel. When it is not necessary to reduce the chip size, the formation area of ​​the pixels 541A, 541B, 541C, 541D and the pixel circuit 210 can be expanded. As a result, it is possible to increase the amount of pixel signals obtained by photoelectric conversion and reduce noise in the transistors provided in the pixel circuits 210. This improves the signal-to-noise ratio of the pixel signals, enabling the imaging device 1 to output better pixel data (image information).

[0223] Furthermore, in the imaging device 1, the pixel circuit 210, the column signal processing section 550, and the image signal processing section 560 are provided on different substrates (the second substrate 200 and the third substrate 300). This allows the area of ​​the pixel circuit 210 and the areas of the column signal processing section 550 and the image signal processing section 560 to be enlarged compared to a case in which the pixel circuit 210, the column signal processing section 550, and the image signal processing section 560 are formed on the same substrate. This allows noise generated in the column signal processing section 550 to be reduced, and allows the image signal processing section 560 to be equipped with a more advanced image processing circuit. This improves the signal-to-noise ratio of the pixel signal, and enables the imaging device 1 to output better pixel data (image information).

[0224] In the imaging device 1, the pixel array section 540 is provided on the first substrate 100 and the second substrate 200, and the column signal processing section 550 and the image signal processing section 560 are provided on the third substrate 300. The contact sections 201, 202, 301, and 302 that connect the second substrate 200 and the third substrate 300 are formed above the pixel array section 540. Therefore, the contact sections 201, 202, 301, and 302 can be freely laid out without being interfered with in the layout by various wirings provided in the pixel array. This makes it possible to use the contact sections 201, 202, 301, and 302 for electrical connection between the second substrate 200 and the third substrate 300. By using the contact sections 201, 202, 301, and 302, for example, the column signal processing section 550 and the image signal processing section 560 have a high degree of freedom in layout. This makes it possible to reduce noise generated in the column signal processing unit 550 and to incorporate a more advanced image processing circuit in the image signal processing unit 560. Therefore, the signal-to-noise ratio of the pixel signals is improved, and the imaging device 1 can output better pixel data (image information).

[0225] Furthermore, in the imaging device 1, the pixel separator 117 penetrates the semiconductor layer 100S. This makes it possible to suppress color mixing between the pixels 541A, 541B, 541C, and 541D even if the distance between adjacent pixels (pixels 541A, 541B, 541C, and 541D) is reduced due to miniaturization of the area per pixel. This improves the signal-to-noise ratio of the pixel signal, enabling the imaging device 1 to output better pixel data (image information).

[0226] Furthermore, in the imaging device 1, a pixel circuit 210 is provided for each pixel sharing unit 539. This allows the formation area of ​​the transistors (amplification transistor AMP, reset transistor RST, selection transistor SEL, FD conversion gain switching transistor FDG) that constitute the pixel circuit 210 to be larger than when a pixel circuit 210 is provided for each of the pixels 541A, 541B, 541C, and 541D. For example, by increasing the formation area of ​​the amplification transistor AMP, it is possible to suppress noise. This improves the signal-to-noise ratio of the pixel signal, and enables the imaging device 1 to output better pixel data (image information).

[0227] Furthermore, in the imaging device 1, the pad section 120 that electrically connects the floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) of the four pixels (pixels 541A, 541B, 541C, 541D) is provided on the first substrate 100. This makes it possible to reduce the number of through electrodes (through electrodes 120E) that connect the first substrate 100 and the second substrate 200, compared to the case where such a pad section 120 is provided on the second substrate 200. Therefore, it is possible to reduce the insulating region 212 and ensure a sufficient size of the formation region (semiconductor layer 200S) of the transistors that constitute the pixel circuit 210. This makes it possible to reduce noise of the transistors provided in the pixel circuit 210, improve the signal-to-noise ratio of the pixel signal, and enable the imaging device 1 to output better pixel data (image information).

[0228] Modifications of the imaging device 1 according to the above embodiment will be described below. In the following modifications, components common to the above embodiment will be denoted by the same reference numerals.

[0229] <2. Variation 1> 76 to 80 show a modified example of the planar configuration of the imaging device 1 according to the above embodiment. FIG. 76 shows a schematic planar configuration of the semiconductor layer 200S of the second substrate 200 near the surface, and corresponds to FIG. 69 described in the above embodiment. FIG. 77 shows a schematic configuration of the first wiring layer W1 and the semiconductor layer 200S and each part of the first substrate 100 connected to the first wiring layer W1, and corresponds to FIG. 70 described in the above embodiment. FIG. 78 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, and corresponds to FIG. 71 described in the above embodiment. FIG. 79 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, and corresponds to FIG. 72 described in the above embodiment. FIG. 80 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to FIG. 73 described in the above embodiment.

[0230] In this modification, as shown in Fig. 77, of two pixel sharing units 539 arranged in the H direction of the second substrate 200, the internal layout of one pixel sharing unit 539 (e.g., the right side of the paper) is configured to be inverted only in the H direction from the internal layout of the other pixel sharing unit 539 (e.g., the left side of the paper). Also, the deviation in the V direction between the outline of one pixel sharing unit 539 and the outline of the other pixel sharing unit 539 is larger than the deviation (Fig. 70) described in the above embodiment. In this way, by increasing the deviation in the V direction, it is possible to reduce the distance between the amplification transistor AMP of the other pixel sharing unit 539 and the pad section 120 connected thereto (the pad section 120 of the other (lower side of the paper) of the two pixel sharing units 539 arranged in the V direction shown in Fig. 68). With such a layout, in the first modification of the imaging device 1 shown in FIGS. 76 to 80, the area of ​​the two pixel sharing units 539 arranged in the H direction can be made the same as that of the pixel sharing unit 539 of the second substrate 200 described in the above embodiment without inverting the planar layouts of the two pixel sharing units 539 arranged in the H direction in the V direction. The planar layout of the pixel sharing unit 539 of the first substrate 100 is the same as the planar layout (FIGS. 68A and 68B) described in the above embodiment. Therefore, the imaging device 1 of this modification can obtain the same effect as the imaging device 1 described in the above embodiment. The arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangement described in the above embodiment and this modification.

[0231] <3. Variation 2> 81 to 86 show a modified example of the planar configuration of the imaging device 1 according to the above embodiment. FIG. 81 shows a schematic planar configuration of the first substrate 100, and corresponds to FIG. 68A described in the above embodiment. FIG. 82 shows a schematic planar configuration of the semiconductor layer 200S of the second substrate 200 near the surface, and corresponds to FIG. 69 described in the above embodiment. FIG. 83 shows a schematic configuration of the first wiring layer W1 and the semiconductor layer 200S and each part of the first substrate 100 connected to the first wiring layer W1, and corresponds to FIG. 70 described in the above embodiment. FIG. 84 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, and corresponds to FIG. 71 described in the above embodiment. FIG. 85 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, and corresponds to FIG. 72 described in the above embodiment. FIG. 86 shows an example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to FIG. 73 described in the above embodiment.

[0232] In this modification, the outer shape of each pixel circuit 210 has a substantially square planar shape (FIG. 82, etc.). In this respect, the planar configuration of the imaging device 1 of this modification differs from the planar configuration of the imaging device 1 described in the above embodiment.

[0233] For example, the pixel sharing unit 539 of the first substrate 100 is formed over a pixel region of 2 rows x 2 columns as described in the above embodiment, and has a substantially square planar shape ( FIG. 81 ). For example, in each pixel sharing unit 539, the horizontal portions TGb of the transfer gates TG1 and TG3 of the pixels 541A and 541C of one pixel column extend in a direction from a position where the transfer gates TG1 and TG3 overlap with the vertical portion TGa toward the center of the pixel sharing unit 539 in the H direction (more specifically, in a direction toward the outer edges of the pixels 541A and 541C and toward the center of the pixel sharing unit 539), and the horizontal portions TGb of the transfer gates TG2 and TG4 of the pixels 541B and 541D of the other pixel column extend in a direction from a position where the transfer gates TG2 and TG4 overlap with the vertical portion TGa toward the outside of the pixel sharing unit 539 in the H direction (more specifically, in a direction toward the outer edges of the pixels 541B and 541D and toward the outside of the pixel sharing unit 539). The pad portion 120 connected to the floating diffusion FD is provided in the center of the pixel sharing unit 539 (the center of the pixel sharing unit 539 in the H and V directions), and the pad portion 121 connected to the VSS contact region 118 is provided at the end of the pixel sharing unit 539 at least in the H direction (in the H and V directions in Figure 81).

[0234] As another arrangement example, it is possible to provide the horizontal parts TGb of the transfer gates TG1, TG2, TG3, and TG4 only in the region facing the vertical parts TGa. In this case, the semiconductor layer 200S is likely to be divided into small parts, as described in the above embodiment. Therefore, it is difficult to form the transistors of the pixel circuit 210 to be large. On the other hand, if the horizontal parts TGb of the transfer gates TG1, TG2, TG3, and TG4 are extended in the H direction from the position where they overlap with the vertical parts TGa as in the above modification, the width of the semiconductor layer 200S can be increased, as described in the above embodiment. Specifically, it is possible to arrange the positions in the H direction of the through electrodes TGV1 and TGV3 connected to the transfer gates TG1 and TG3 close to the position in the H direction of the through electrode 120E, and to arrange the positions in the H direction of the through electrodes TGV2 and TGV4 connected to the transfer gates TG2 and TG4 close to the position in the H direction of the through electrode 121E (FIG. 83). This allows the width (size in the H direction) of the semiconductor layer 200S extending in the V direction to be increased, as in the above embodiment. This allows the size of the transistors in the pixel circuit 210, particularly the size of the amplifying transistor AMP, to be increased. As a result, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0235] The pixel sharing unit 539 of the second substrate 200 has, for example, approximately the same size in the H direction and the V direction as the pixel sharing unit 539 of the first substrate 100, and is provided, for example, over an area corresponding to a pixel area of ​​approximately 2 rows x 2 columns. For example, in each pixel circuit 210, a selection transistor SEL and an amplification transistor AMP are arranged side by side in the V direction in one semiconductor layer 200S extending in the V direction, and an FD conversion gain switching transistor FDG and a reset transistor RST are arranged side by side in the V direction in one semiconductor layer 200S extending in the V direction. The one semiconductor layer 200S in which the selection transistor SEL and the amplification transistor AMP are provided and the one semiconductor layer 200S in which the FD conversion gain switching transistor FDG and the reset transistor RST are provided are arranged side by side in the H direction via an insulating region 212. This insulating region 212 extends in the V direction (FIG. 82).

[0236] Here, the outer shape of the pixel sharing unit 539 of the second substrate 200 will be described with reference to Fig. 82 and Fig. 83. For example, the pixel sharing unit 539 of the first substrate 100 shown in Fig. 81 is connected to an amplification transistor AMP and a selection transistor SEL provided on one side of the H direction of the pad section 120 (the left side of the paper in Fig. 83), and an FD conversion gain switching transistor FDG and a reset transistor RST provided on the other side of the H direction of the pad section 120 (the right side of the paper in Fig. 83). The outer shape of the pixel sharing unit 539 of the second substrate 200 including the amplification transistor AMP, the selection transistor SEL, the FD conversion gain switching transistor FDG, and the reset transistor RST is determined by the following four outer edges.

[0237] The first outer edge is the outer edge of one end in the V direction (the end on the upper side of the paper in FIG. 83) of the semiconductor layer 200S including the selection transistor SEL and the amplification transistor AMP. This first outer edge is provided between the amplification transistor AMP included in the pixel sharing unit 539 and the selection transistor SEL included in the pixel sharing unit 539 adjacent to the pixel sharing unit 539 on one side in the V direction (the upper side of the paper in FIG. 83). More specifically, the first outer edge is provided in the center in the V direction of the element isolation region 213 between the amplification transistor AMP and the selection transistor SEL. The second outer edge is the outer edge of the other end in the V direction (the end on the lower side of the paper in FIG. 83) of the semiconductor layer 200S including the selection transistor SEL and the amplification transistor AMP. This second outer edge is provided between the selection transistor SEL included in the pixel sharing unit 539 and the amplification transistor AMP included in the pixel sharing unit 539 adjacent to the pixel sharing unit 539 on the other side in the V direction (the lower side of the paper in FIG. 83). More specifically, the second outer edge is provided in the center in the V direction of the element isolation region 213 between the selection transistor SEL and the amplification transistor AMP. The third outer edge is the outer edge of the other end in the V direction (the end on the lower side of the paper in FIG. 83) of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. This third outer edge is provided between the FD conversion gain switching transistor FDG included in the pixel shared unit 539 and the reset transistor RST included in the pixel shared unit 539 adjacent to the other side in the V direction (the lower side of the paper in FIG. 83) of this pixel shared unit 539. More specifically, the third outer edge is provided in the center in the V direction of the element isolation region 213 between the FD conversion gain switching transistor FDG and the reset transistor RST. The fourth outer edge is the outer edge of one end in the V direction (the end on the upper side of the paper in FIG. 83) of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. This fourth outer edge is provided between the reset transistor RST included in the pixel sharing unit 539 and the FD conversion gain switching transistor FDG (not shown) included in the pixel sharing unit 539 adjacent to the pixel sharing unit 539 on one side of the V direction (the upper side of the paper in Figure 83).More specifically, the fourth outer edge is provided at the center in the V direction of the element isolation region 213 (not shown) between the reset transistor RST and the FD conversion gain switching transistor FDG.

[0238] In the outline of the pixel sharing unit 539 of the second substrate 200 including such first, second, third, and fourth outer edges, the third and fourth outer edges are arranged to be shifted to one side in the V direction with respect to the first and second outer edges (in other words, offset to one side in the V direction). By using such a layout, it is possible to arrange both the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG as close as possible to the pad section 120. Therefore, the area of ​​the wiring connecting them is reduced, and it becomes easier to miniaturize the imaging device 1. The VSS contact region 218 is provided between the semiconductor layer 200S including the selection transistor SEL and the amplification transistor AMP and the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. For example, the multiple pixel circuits 210 have the same arrangement.

[0239] The imaging device 1 having such a second substrate 200 can also obtain the same effects as those described in the above embodiment. The arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangements described in the above embodiment and this modified example.

[0240] <4. Variation 3> 87 to 92 show a modified example of the planar configuration of the imaging device 1 according to the above embodiment. FIG. 87 shows a schematic planar configuration of the first substrate 100, and corresponds to FIG. 68B described in the above embodiment. FIG. 88 shows a schematic planar configuration of the semiconductor layer 200S of the second substrate 200 near the surface, and corresponds to FIG. 69 described in the above embodiment. FIG. 89 shows a schematic configuration of the first wiring layer W1 and the semiconductor layer 200S and each part of the first substrate 100 connected to the first wiring layer W1, and corresponds to FIG. 70 described in the above embodiment. FIG. 90 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, and corresponds to FIG. 71 described in the above embodiment. FIG. 91 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, and corresponds to FIG. 72 described in the above embodiment. FIG. 92 shows an example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to FIG. 73 described in the above embodiment.

[0241] In this modification, the semiconductor layer 200S of the second substrate 200 extends in the H direction (FIG. 89). That is, this substantially corresponds to a configuration obtained by rotating the planar configuration of the imaging device 1 shown in FIG. 82 etc. by 90 degrees.

[0242] For example, the pixel sharing unit 539 of the first substrate 100 is formed over a pixel region of 2 rows x 2 columns as described in the above embodiment, and has a substantially square planar shape ( FIG. 87 ). For example, in each pixel sharing unit 539, the transfer gates TG1 and TG2 of the pixels 541A and 541B in one pixel row extend toward the center of the pixel sharing unit 539 in the V direction, and the transfer gates TG3 and TG4 of the pixels 541C and 541D in the other pixel row extend toward the outside of the pixel sharing unit 539 in the V direction. The pad section 120 connected to the floating diffusion FD is provided in the center of the pixel sharing unit 539, and the pad section 121 connected to the VSS contact region 118 is provided at an end of the pixel sharing unit 539 at least in the V direction (in the V direction and H direction in FIG. 87 ). At this time, the V-direction positions of the through electrodes TGV1 and TGV2 of the transfer gates TG1 and TG2 approach the V-direction position of the through electrode 120E, and the V-direction positions of the through electrodes TGV3 and TGV4 of the transfer gates TG3 and TG4 approach the V-direction position of the through electrode 121E (FIG. 89). Therefore, for the same reason as described in the above embodiment, the width (size in the V direction) of the semiconductor layer 200S extending in the H direction can be increased. This makes it possible to increase the size of the amplification transistor AMP and suppress noise.

[0243] In each pixel circuit 210, the selection transistor SEL and the amplification transistor AMP are arranged side by side in the H direction, and the reset transistor RST is arranged adjacent to the selection transistor SEL in the V direction with the insulating region 212 between them (FIG. 88). The FD conversion gain switching transistor FDG is arranged side by side with the reset transistor RST in the H direction. The VSS contact region 218 is provided in an island shape in the insulating region 212. For example, the third wiring layer W3 extends in the H direction (FIG. 91), and the fourth wiring layer W4 extends in the V direction (FIG. 92).

[0244] The imaging device 1 having such a second substrate 200 can also obtain the same effects as those described in the above embodiment. The arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangements described in the above embodiment and this modification. For example, the semiconductor layer 200S described in the above embodiment and modification 1 may extend in the H direction.

[0245] <5. Variation 4> Fig. 93 is a schematic diagram showing a modified example of the cross-sectional configuration of the imaging device 1 according to the above embodiment. Fig. 93 corresponds to Fig. 64 described in the above embodiment. In this modified example, the imaging device 1 has contact portions 203, 204, 303, and 304 at positions facing the center of the pixel array section 540, in addition to the contact portions 201, 202, 301, and 302. In this respect, the imaging device 1 of this modified example differs from the imaging device 1 described in the above embodiment.

[0246] The contact portions 203 and 204 are provided on the second substrate 200, and are exposed on the bonding surface with the third substrate 300. The contact portions 303 and 304 are provided on the third substrate 300, and are exposed on the bonding surface with the second substrate 200. The contact portion 203 contacts the contact portion 303, and the contact portion 204 contacts the contact portion 304. That is, in this imaging device 1, the second substrate 200 and the third substrate 300 are connected by the contact portions 203, 204, 303, and 304 in addition to the contact portions 201, 202, 301, and 302.

[0247] Next, the operation of the imaging device 1 will be described with reference to FIG. 94 and FIG. 95. In FIG. 94, the input signal inputted from the outside to the imaging device 1, and the paths of the power supply potential and the reference potential are indicated by arrows. In FIG. 95, the signal path of the pixel signal outputted from the imaging device 1 to the outside is indicated by arrows. For example, the input signal inputted to the imaging device 1 via the input section 510A is transmitted to the row driver 520 of the third substrate 300, and the row driver 520 generates a row drive signal. This row drive signal is sent to the second substrate 200 via the contact sections 303 and 203. Furthermore, this row drive signal reaches each pixel sharing unit 539 of the pixel array section 540 via the row drive signal line 542 in the wiring layer 200T. Among the row drive signals that reach the pixel sharing units 539 of the second substrate 200, the drive signals other than the transfer gate TG are inputted to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. A drive signal for the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV, and the pixels 541A, 541B, 541C, and 541D are driven. In addition, a power supply potential and a reference potential supplied to an input section 510A (input terminal 511) of the third substrate 300 from the outside of the imaging device 1 are sent to the second substrate 200 via contact sections 303 and 203, and are supplied to the pixel circuits 210 of the pixel sharing units 539 via wiring in the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121E. Meanwhile, pixel signals photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are sent to the pixel circuit 210 of the second substrate 200 for each pixel sharing unit 539. A pixel signal based on this pixel signal is sent from the pixel circuit 210 to the third substrate 300 via a vertical signal line 543 and contact units 204 and 304. This pixel signal is processed by a column signal processing unit 550 and an image signal processing unit 560 of the third substrate 300, and then output to the outside via an output unit 510B.

[0248] The imaging device 1 having such contact portions 203, 204, 303, and 304 can also provide the same effects as those described in the above embodiment. The positions and number of the contact portions can be changed depending on the design of the circuit of the third substrate 300 to which the wiring via the contact portions 303 and 304 is connected.

[0249] <6. Variation 5> Fig. 96 shows a modified cross-sectional configuration of the imaging device 1 according to the above embodiment. Fig. 96 corresponds to Fig. 67 described in the above embodiment. In this modification, a transfer transistor TR having a planar structure is provided on the first substrate 100. In this respect, the imaging device 1 of this modification differs from the imaging device 1 described in the above embodiment.

[0250] In the transfer transistor TR, the transfer gate TG is formed only by the horizontal portion TGb, In other words, the transfer gate TG does not have the vertical portion TGa and is provided opposite to the semiconductor layer 100S.

[0251] The imaging device 1 having such a planar-structured transfer transistor TR also provides the same effects as those described in the above embodiment. Furthermore, by providing the planar-type transfer gate TG on the first substrate 100, the photodiode PD can be formed closer to the surface of the semiconductor layer 100S than when a vertical-type transfer gate TG is provided on the first substrate 100, and this can be considered to increase the saturation signal amount (Qs). In addition, the method of forming the planar-type transfer gate TG on the first substrate 100 requires fewer manufacturing steps than the method of forming the vertical-type transfer gate TG on the first substrate 100, and it can be considered that the manufacturing steps are less likely to adversely affect the photodiode PD.

[0252] <7. Variation 6> Fig. 97 shows a modified example of the pixel circuit of the imaging device 1 according to the above embodiment. Fig. 97 corresponds to Fig. 65 described in the above embodiment. In this modified example, a pixel circuit 210 is provided for each pixel (pixel 541A). That is, the pixel circuit 210 is not shared by multiple pixels. In this respect, the imaging device 1 of this modified example differs from the imaging device 1 described in the above embodiment.

[0253] The imaging device 1 of this modification is the same as the imaging device 1 described in the above embodiment in that the pixel 541A and the pixel circuit 210 are provided on different substrates (the first substrate 100 and the second substrate 200). Therefore, the imaging device 1 according to this modification can also obtain the same effects as those described in the above embodiment.

[0254] <8. Variation 7> Fig. 98 shows a modified example of the planar configuration of pixel separation section 117 described in the above embodiment. Gaps may be provided in pixel separation section 117 surrounding each of pixels 541A, 541B, 541C, and 541D. That is, pixels 541A, 541B, 541C, and 541D do not have to be entirely surrounded by pixel separation section 117. For example, the gaps in pixel separation section 117 are provided in the vicinity of pad sections 120 and 121 (see Fig. 68B).

[0255] In the above embodiment, an example (see FIG. 67) has been described in which pixel separator 117 has an FTI structure penetrating semiconductor layer 100S, but pixel separator 117 may have a configuration other than the FTI structure. For example, pixel separator 117 does not have to be provided so as to completely penetrate semiconductor layer 100S, and may have a so-called DTI (Deep Trench Isolation) structure.

[0256] <9. Application Examples> FIG. 99 shows an example of a schematic configuration of an imaging system 7 including the imaging device 1 according to the above embodiment and its modified example.

[0257] The imaging system 7 is, for example, an electronic device such as an imaging device such as a digital still camera or a video camera, or a mobile terminal device such as a smartphone or a tablet terminal. The imaging system 7 includes, for example, the imaging device 1 according to the above embodiment and its modified example, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the imaging system 7, the imaging device 1 according to the above embodiment and its modified example, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 are connected to each other via a bus line 249.

[0258] The imaging device 1 according to the above embodiment and its modified examples outputs image data according to incident light. The DSP circuit 243 is a signal processing circuit that processes a signal (image data) output from the imaging device 1 according to the above embodiment and its modified examples. The frame memory 244 temporarily holds the image data processed by the DSP circuit 243 on a frame-by-frame basis. The display unit 245 is formed of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the imaging device 1 according to the above embodiment and its modified examples. The storage unit 246 records image data of a moving image or a still image captured by the imaging device 1 according to the above embodiment and its modified examples in a recording medium such as a semiconductor memory or a hard disk. The operation unit 247 issues operation commands for various functions of the imaging system 7 according to an operation by a user. The power supply unit 248 appropriately supplies various power sources that serve as operating power sources for the imaging device 1 according to the above embodiment and its modified examples, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, and the operation unit 247 to these supply targets.

[0259] Next, the imaging procedure in the imaging system 7 will be described.

[0260] 100 shows an example of a flowchart of an imaging operation in the imaging system 7. A user operates the operation unit 247 to instruct the start of imaging (step S101). Then, the operation unit 247 transmits an imaging command to the imaging device 1 (step S102). Upon receiving the imaging command, the imaging device 1 (specifically, the system control circuit 36) executes imaging in a predetermined imaging method (step S103).

[0261] The imaging device 1 outputs image data obtained by imaging to the DSP circuit 243. Here, the image data refers to data for all pixels of pixel signals generated based on charges temporarily stored in the floating diffusion FD. The DSP circuit 243 performs predetermined signal processing (e.g., noise reduction processing, etc.) based on the image data input from the imaging device 1 (step S104). The DSP circuit 243 stores the image data that has been subjected to the predetermined signal processing in the frame memory 244, and the frame memory 244 stores the image data in the storage unit 246 (step S105). In this manner, imaging is performed in the imaging system 7.

[0262] In this application example, the imaging device 1 according to the above-described embodiment and its modified example is applied to an imaging system 7. This allows the imaging device 1 to be made smaller or have higher definition, so that a small or high-definition imaging system 7 can be provided.

[0263] <10. Application Examples> [Application example 1] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0264] FIG. 101 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology of the present disclosure can be applied.

[0265] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 101, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0266] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0267] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0268] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0269] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0270] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0271] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0272] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0273] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0274] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 101, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0275] FIG. 102 is a diagram showing an example of the installation position of the imaging unit 12031.

[0276] In FIG. 102, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as an imaging unit 12031.

[0277] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0278] 102 shows an example of the imaging ranges of the imaging units 12101 to 12104. An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and an imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0279] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0280] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0281] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0282] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0283] An example of a mobile object control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, the imaging device 1 according to the above embodiment and its modified example can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, a high-definition captured image with little noise can be obtained, and therefore, high-precision control using the captured image can be performed in the mobile object control system.

[0284] [Application example 2] FIG. 103 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0285] 103 shows a state in which an operator (doctor) 11131 is performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0286] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may be configured as a so-called flexible scope having a flexible lens barrel.

[0287] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an observation target in the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0288] An optical system and an image sensor are provided inside the camera head 11102, and reflected light (observation light) from an observation target is collected on the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to an observation image. The image signal is transmitted to a camera control unit (CCU) 11201 as RAW data.

[0289] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.

[0290] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0291] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 11100 with irradiation light when photographing an operation site or the like.

[0292] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiated light, magnification, focal length, etc.) of the endoscope 11100.

[0293] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 sends gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing the field of view of the endoscope 11100 and securing the working space of the surgeon. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, image, or graph.

[0294] The light source device 11203 that supplies irradiation light to the endoscope 11100 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in a time-division manner by irradiating the observation object with laser light from each of the RGB laser light sources in a time-division manner and controlling the driving of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0295] The light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. The driving of the image sensor of the camera head 11102 may be controlled in synchronization with the timing of the change in the light intensity to obtain images in a time-division manner, and the images may be synthesized to generate an image with a high dynamic range that is free of so-called blackout and whiteout.

[0296] The light source device 11203 may be configured to supply light of a predetermined wavelength band corresponding to the special light observation. In the special light observation, for example, by utilizing the wavelength dependency of light absorption in body tissue, a narrow band light is irradiated compared to the irradiated light (i.e., white light) during normal observation, and a predetermined tissue such as blood vessels on the mucous membrane surface is photographed with high contrast, so-called narrow band imaging is performed. Alternatively, in the special light observation, a fluorescent observation may be performed in which an image is obtained by fluorescence generated by irradiating an excitation light. In the fluorescent observation, it is possible to irradiate an excitation light to a body tissue and observe the fluorescence from the body tissue (autofluorescence observation), or to locally inject a reagent such as indocyanine green (ICG) into the body tissue and irradiate the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0297] FIG. 104 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0298] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so as to be able to communicate with each other.

[0299] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

[0300] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be one (so-called single-plate type) or multiple (so-called multi-plate type). When the imaging unit 11402 is composed of a multi-plate type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining the image signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site. Note that when the imaging unit 11402 is composed of a multi-plate type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0301] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately behind the objective lens.

[0302] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be appropriately adjusted.

[0303] The communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0304] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201, and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing the image, and / or information specifying the magnification and focus of the captured image.

[0305] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by a user, or may be automatically set by the control unit 11413 of the CCU 11201 based on an acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0306] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404.

[0307] The communication unit 11411 is configured with a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0308] Furthermore, the communication unit 11411 transmits, to the camera head 11102, a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0309] The image processing unit 11412 performs various types of image processing on the image signal, which is RAW data sent from the camera head 11102 .

[0310] The control unit 11413 performs various controls related to imaging of the surgical site etc. by the endoscope 11100 and display of the captured image obtained by imaging the surgical site etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0311] Further, the control unit 11413 causes the display device 11202 to display the captured image showing the surgical site, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 can recognize surgical tools such as forceps, specific living body parts, bleeding, mist when the energy treatment tool 11112 is used, etc., by detecting the shape and color of the edge of an object included in the captured image. When the control unit 11413 causes the display device 11202 to display the captured image, it may use the recognition result to superimpose various types of surgery support information on the image of the surgical site. By superimposing and presenting the surgery support information to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0312] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0313] Here, in the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0314] An example of an endoscopic surgery system to which the technology according to the present disclosure can be applied has been described above. Of the configurations described above, the technology according to the present disclosure can be suitably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the imaging unit 11402, the imaging unit 11402 can be made smaller or have higher resolution, so that a small or high-resolution endoscope 11100 can be provided.

[0315] (Examples) The semiconductor device of the present technology is configured to be incorporated in an amplifying transistor 150 included in a pixel circuit (CMOS image sensor) combined with a photodiode 110 (photoelectric conversion element), for example, as shown in Fig. 105. The semiconductor device can be applied to a solid-state imaging element having the semiconductor device and the pixel circuit 210. The solid-state imaging element may be a so-called back-illuminated solid-state imaging device, or may be a front-illuminated solid-state imaging device. The pixel circuit 210 includes a transfer transistor TR, a floating diffusion 130, a reset transistor 140, an amplification transistor 150, a selection transistor 160, and a vertical signal line 170.

[0316] The transfer transistor TR is disposed between the photodiode 110 and the floating diffusion 130. The source electrode of the transfer transistor TR is connected to the other end (cathode electrode) of the photodiode 110, which performs photoelectric conversion on incident light and generates and accumulates electric charges according to the amount of light resulting from the photoelectric conversion. One end (anode electrode) of the photodiode 110 is grounded. The drain electrode of the transfer transistor TR is connected to the drain electrode of the reset transistor 140 and the gate electrode of the amplification transistor 150. Moreover, the transfer transistor TR turns on or off the transfer of charge from the photodiode 110 to the floating diffusion 130 in accordance with a drive signal supplied to its gate electrode from a timing control unit (not shown). Note that while the transfer transistor TR stops transferring signal charge to the floating diffusion 130, the charge photoelectrically converted by the photodiode 110 is accumulated in the photodiode 110.

[0317] The floating diffusion 130 is formed at a point (connection point) where the drain electrode of the transfer transistor TR, the source electrode of the reset transistor 140, and the gate electrode of the amplification transistor 150 are connected. Furthermore, the floating diffusion 130 accumulates the charge transferred from the photodiode 110 via the transfer transistor TR and converts it into a voltage. That is, the signal charge accumulated in the photodiode 110 is transferred to the floating diffusion 130.

[0318] The reset transistor 140 has a source electrode connected to the floating diffusion 130 and a drain electrode connected to a reset-side pixel power supply 180 . Furthermore, the reset transistor 140 turns on or off the discharge of the charge accumulated in the floating diffusion 130 in accordance with a drive signal supplied to the gate electrode from the timing control unit.

[0319] For example, when a high-level drive signal is supplied to the gate electrode of the reset transistor 140, the reset transistor 140 flows charge to the pixel power supply before transferring the signal charge from the photodiode 110 to the floating diffusion 130. This causes the charge accumulated in the floating diffusion 130 to be discharged (reset). The amount of charge discharged is an amount according to the drain voltage. The drain voltage is a reset voltage that resets the floating diffusion 130. On the other hand, when a low-level drive signal is supplied to the gate electrode of the reset transistor 140, the reset transistor 140 puts the floating diffusion 130 into an electrically floating state.

[0320] The amplification transistor 150 has a gate electrode connected to the floating diffusion 130 and a source electrode connected to an amplifier-side pixel power supply 190. A control voltage is input to the source electrode of the amplification transistor 150 from a circuit not shown in the figure. The drain electrode of the amplification transistor 150 is connected to the source electrode of the selection transistor 160. Moreover, the amplification transistor 150 reads out, as a reset level, the potential of the floating diffusion 130 reset by the reset transistor 140. Furthermore, the amplification transistor 150 amplifies a voltage according to the signal charge accumulated in the floating diffusion 130 to which the signal charge has been transferred by the transfer transistor TR. That is, the amplification transistor 150 reads out and amplifies the signal charge transferred to the floating diffusion 130 as an electrical signal. The voltage (voltage signal) amplified by the amplifying transistor 150 is output to a vertical signal line 170 via a selection transistor 160 .

[0321] The selection transistor 160 has, for example, a drain electrode connected to one end of the vertical signal line 170 and a source electrode connected to the drain electrode of the amplification transistor 150 . Furthermore, the selection transistor 160 turns on or off the output of a voltage signal from the amplification transistor 150 to the vertical signal line 170 in accordance with a drive signal SEL supplied to the gate electrode from the timing control section.

[0322] The vertical signal line 170 (vertical signal line) is a wiring that outputs an electrical signal amplified by the amplification transistor 150. One end of the vertical signal line 170 is connected to a drain electrode of the selection transistor 160. The other end of the vertical signal line 170 is connected to an A / D converter (not shown).

[0323] As shown in FIG. 106, the solid-state imaging device SCC has a configuration in which a first device layer 215, a first wiring layer 220, a second device layer 230, and a second wiring layer 240 are laminated.

[0324] The first device layer 215 forms a photoelectric conversion substrate including the photodiode 110, the transfer transistor TR, the reset transistor 140, and the floating diffusion . The first wiring layer 220 is laminated on one surface (the upper surface in FIG. 106) of the first device layer 215, and forms an interlayer insulating layer that provides insulation between the first device layer 215 and the second device layer 230. In addition, part of the interlayer wiring 250 that connects the photodiode 110 and the amplification transistor 150 is formed in the first wiring layer 220.

[0325] The second device layer 230 is laminated on one surface (the upper surface in FIG. 106) of the first wiring layer 220, and includes an amplifying transistor 150 in which a semiconductor device SD is incorporated. In addition, a part of an interlayer wiring 250 that connects the photodiode 110 and the amplifying transistor 150 is formed in the first wiring layer 220. The second wiring layer 240 is laminated on one surface (the upper surface in FIG. 106) of the second device layer 230, and a part of the interlayer wiring 250 that connects the photodiode 110 and the amplifying transistor 150 is formed therein.

[0326] The reset transistor 140 and the selection transistor 160 may be either a junctionless FET or a planar type FET.

[0327] The first wiring layer 220, the second device layer 230, and the second wiring layer 240 are each formed so that the thickness along the stacking direction is, for example, 0.5 [μm]. Therefore, the surface of the upper silicon layer formed by the second device layer 230 and the second wiring layer 240 is formed at a height of approximately 1 μm from the surface of the lower silicon substrate formed by the first device layer 215 and the first wiring layer 220.

[0328] Moreover, the low-concentration N-type region LN, the second high-concentration N-type region 3, the gate electrode 4, and the opposing region 2a are each formed so that the width viewed from the stacking direction is, for example, 0.2 [μm]. Furthermore, the second high concentration N-type region 3 is formed so as to have a thickness along the stacking direction of, for example, 0.1 [μm]. Also, the low concentration N-type region LN and the bottom region 2b are each formed so as to have a thickness along the stacking direction of, for example, 0.2 [μm].

[0329] That is, the semiconductor device SD having a vertical GAA structure in which the first high concentration N-type region 2 and the second high concentration N-type region 3 are stacked with the low concentration N-type region LN sandwiched therebetween is formed so that the size of each component is approximately 0.1 [μm] to 0.3 [μm]. In particular, the distance between the gate electrode 4 and the low-concentration N-type region LN (channel) extending in the vertical direction (stacking direction) from the source electrode to the drain electrode is set to about 0.05 μm.

[0330] The size of the semiconductor device SD is set to be smaller than the photodiode 110 in accordance with the size of the photodiode 110, and the detailed size is determined in accordance with the characteristics and ease of processing. It should be noted that the semiconductor device according to the present technology is not limited to a configuration in which the amplifier transistor 150 is incorporated, and may be a configuration in which the amplifier transistor 150 is incorporated in something other than the photodiode 110, for example.

[0331] (Other embodiments) As described above, the embodiment of the present technology has been described, but the description and drawings forming a part of this disclosure should not be understood as limiting the present technology. Various alternative embodiments, examples, and operating techniques will be apparent to those skilled in the art from this disclosure. In addition, the present technology naturally includes various embodiments not described here, such as configurations in which the configurations described in the above embodiments are arbitrarily applied, etc. Therefore, the technical scope of the present technology is determined only by the invention-specifying matters related to the scope of the claims appropriate from the above description.

[0332] Furthermore, the semiconductor device of the present disclosure does not need to include all of the components described in the above embodiments, and conversely, may include other components. The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0333] The present technology can be configured as follows. (1) A low concentration N-type region; a first high concentration N-type region and a second high concentration N-type region which are stacked with the low concentration N-type region therebetween and have a higher impurity concentration than the low concentration N-type region; a gate electrode surrounding the low-concentration N-type region when viewed from a stacking direction in which the low-concentration N-type region, the first high-concentration N-type region, and the second high-concentration N-type region are stacked; a first insulating film disposed between the gate electrode and the low concentration N-type region; a second insulating film disposed between the gate electrode and the first high concentration N-type region; the first high concentration N-type region is connected to one of a source electrode and a drain electrode; The second high concentration N-type region is connected to the other of the source electrode and the drain electrode. (2) A low concentration N-type region; a first high concentration N-type region and a second high concentration N-type region that are stacked with the low concentration N-type region therebetween and have a higher impurity concentration than the low concentration N-type region; a gate electrode having a portion facing the low-concentration N-type region and a portion not facing the low-concentration N-type region when viewed from a stacking direction in which the low-concentration N-type region, the first high-concentration N-type region, and the second high-concentration N-type region are stacked; a first insulating film disposed between the gate electrode and the low concentration N-type region; a second insulating film disposed between the gate electrode and the first high concentration N-type region; the first high concentration N-type region is connected to one of a source electrode and a drain electrode; The second high concentration N-type region is connected to the other of the source electrode and the drain electrode. (3) the first high concentration N-type region is formed including an opposing region which is an opposing region to the low concentration N-type region with the gate electrode therebetween, a third insulating film disposed between the facing region and the gate electrode; The semiconductor device according to (1) or (2), wherein the second insulating film and the third insulating film have a thickness greater than the thickness of the first insulating film. (4) the first high concentration N-type region is formed including an opposing region which is an opposing region to the low concentration N-type region with the gate electrode therebetween, a third insulating film disposed between the facing region and the gate electrode; The semiconductor device according to (1) or (2), wherein the third insulating film has a thickness larger than that of the first insulating film and that of the second insulating film. (5) The semiconductor device according to (3) or (4), wherein the third insulating film is made of at least one of silicon oxide, silicon nitride, and hafnium oxide. (6) The semiconductor device according to any one of (1) to (5) above, wherein at least one of silicon oxide, silicon nitride, and hafnium oxide is used as a material for the first insulating film and the second insulating film. (7) The semiconductor device according to any one of (1) to (6), wherein the gate electrode is made of at least one of polycrystalline silicon, titanium nitride, copper, aluminum, and tungsten. (8) a plurality of the second high concentration N-type regions and a plurality of the low concentration N-type regions; The semiconductor device according to any one of (1) to (7), wherein a plurality of the second high concentration N-type regions and a plurality of the low concentration N-type regions are stacked on one of the first high concentration N-type regions. (9) the low concentration N-type region has a rectangular shape when viewed from the stacking direction, The semiconductor device according to any one of (1) to (8), wherein the gate electrode has a rectangular shape when viewed from the stacking direction. (10) the low concentration N-type region has a circular shape when viewed from the stacking direction, The semiconductor device according to any one of (1) to (8), wherein the gate electrode has a circular shape when viewed from the stacking direction. (11) The semiconductor device according to any one of (1) to (10), wherein a surface of the first heavily doped N-type region connected to the source electrode or the drain electrode and a surface of the second heavily doped N-type region connected to the source electrode or the drain electrode are at the same height when viewed from a direction perpendicular to the stacking direction. (12) The semiconductor device according to any one of (1) to (10), wherein a surface of the first heavily doped N-type region connected to the source electrode or the drain electrode and a surface of the second heavily doped N-type region connected to the source electrode or the drain electrode are at different heights when viewed from a direction perpendicular to the stacking direction. (13) The semiconductor device according to any one of (1) to (12), wherein the low concentration N-type region has a portion that does not face the gate electrode. (14) The low-concentration N-type region has an impurity concentration of 10 keV / 1E 18 (pcs / cm 2 ) or less, The first high concentration N-type region and the second high concentration N-type region have an impurity concentration of 10 keV / 1E 19 (pcs / cm 2 14. The semiconductor device according to any one of (1) to (13) above. (15) A pixel circuit including an amplification transistor; A solid-state imaging device in which the semiconductor device according to any one of (1) to (14) above is incorporated in the amplifying transistor. (16) A pixel circuit including an amplification transistor; A solid-state imaging element in which the semiconductor device described in (2) is incorporated in the amplifying transistor. (17) a first semiconductor layer in which a pixel circuit is arranged, the pixel circuit including a photodiode, a transfer transistor connected to the photodiode, and a floating diffusion; an interlayer insulating layer laminated on the first semiconductor layer; a second semiconductor layer which is a semiconductor layer in which an amplifying transistor including a semiconductor device is arranged and which is laminated on the interlayer insulating layer; a transfer-side interlayer wiring penetrating the interlayer insulating layer and the second semiconductor layer is connected to the transfer transistor; The semiconductor device includes: A low concentration N-type region; a first high concentration N-type region and a second high concentration N-type region that are stacked in a direction perpendicular to a direction in which the first semiconductor layer and the second semiconductor layer are stacked with the lightly doped N-type region therebetween and have a higher impurity concentration than the lightly doped N-type region; a gate electrode facing at least a portion of the low concentration N-type region; a shielding electrode facing at least a part of the low concentration N-type region different from a part facing the gate electrode; a first insulating film disposed between the gate electrode and the low concentration N-type region; a second insulating film disposed between the gate electrode and the first high concentration N-type region; the first high concentration N-type region is connected to one of a source electrode and a drain electrode; the second high concentration N-type region is connected to the other of the source electrode and the drain electrode; the gate electrode is connected to the floating diffusion by a gate-side interlayer wiring penetrating the interlayer insulating layer and the second semiconductor layer, and is electrically connected to the first semiconductor layer; The shielding electrode is electrically connected to a portion different from the first semiconductor layer and the second semiconductor layer. (18) the low-concentration N-type region is a rectangle having two sides parallel to the stacking direction and two sides perpendicular to the stacking direction when viewed from the stacking direction, The solid-state imaging element according to (17), wherein the gate electrode and the shielding electrode face three or four sides of the low concentration N-type region when viewed from the stacking direction. (19) the gate electrode faces, as viewed from the stacking direction, one of the two parallel sides that is farther from the first semiconductor layer and one of the two perpendicular sides that is closer to the gate-side interlayer wiring; The solid-state imaging element described in (18) above, wherein the shielding electrode, when viewed from the stacking direction, faces one of the two parallel sides that is closer to the first semiconductor layer, and one of the two perpendicular sides that is closer to the transfer-side interlayer wiring. (20) the gate electrode faces one of the two parallel sides and the two orthogonal sides that is closer to the gate-side interlayer wiring when viewed from the stacking direction, The solid-state imaging element according to (19), wherein the shielding electrode faces one of the two orthogonal sides closer to the transfer-side interlayer wiring when viewed from the stacking direction. (twenty one) the gate electrode faces, as viewed from the stacking direction, one of the two parallel sides that is closer to the first semiconductor layer and one of the two perpendicular sides that is closer to the gate-side interlayer wiring; The solid-state imaging element according to (19), wherein the shielding electrode faces one of the two orthogonal sides closer to the transfer-side interlayer wiring when viewed from the stacking direction. (twenty two) the gate electrode faces one of the two orthogonal sides that is closer to the gate-side interlayer wiring when viewed from the stacking direction, The solid-state imaging element described in (19) above, wherein the shielding electrode, when viewed from the stacking direction, faces one of the two parallel sides that is closer to the first semiconductor layer, and one of the two perpendicular sides that is closer to the transfer-side interlayer wiring. (twenty three) the gate electrode faces the two parallel sides when viewed from the stacking direction, the shielding electrode faces the two perpendicular sides as viewed from the stacking direction, a fifth insulating film disposed between the shielding electrode and the lightly doped N-type region; The solid-state imaging device according to (19) above, wherein the fifth insulating film is thicker than the first insulating film. (twenty four) The gate electrode and the shielding electrode are integrated together, The solid-state imaging element according to (23) above, wherein the integrated gate electrode and shielding electrode surround the low concentration N-type region when viewed from the stacking direction. (twenty five) the gate electrode has a low-concentration region facing portion which is a portion facing the low-concentration N-type region, and a high-concentration region facing portion which is a portion facing at least one of the first high-concentration N-type region and the second high-concentration N-type region, A solid-state imaging element according to any one of (17) to (24), wherein the distance between the high concentration region opposing portion and at least one of the first high concentration N-type region and the second high concentration N-type region is longer than the distance between the low concentration region opposing portion and the low concentration N-type region. (26) Four of the pixel circuits are disposed in the first semiconductor layer, N-type polysilicon pads connecting the four floating diffusions included in the four pixel circuits, respectively; The solid-state imaging device according to any one of (17) to (25) above, further comprising a shared contact that connects the N-type polysilicon pad and the amplifying transistor. [Explanation of symbols]

[0334] 1...imaging device, 2...first high concentration N-type region, 2a...opposing region, 2b...bottom region, 3 (3a to 3d)...second high concentration N-type region, 4...gate electrode, 4a...gate side electrode material, 4L...low concentration region opposing portion, 4H...high concentration region opposing portion, 5a...first insulating film, 5b...second insulating film, 5c...third insulating film, 5d...fourth insulating film, 5e...fifth insulating film, 10...silicon substrate, 12...hard mask, 14a...first resist mask, 14b...second resist mask, 14c...third resist mask, 14d...fourth resist mask, 16...oxide film, 16a...third First oxide film, 16b...second oxide film, 16c...third oxide film, 16d...fourth oxide film, 18...polysilicon, 110...photodiode, 130...floating diffusion, 140...reset transistor, 150...amplification transistor, 160...selection transistor, 170...vertical signal line, 180...reset side pixel power supply, 190...amplification side pixel power supply, 210...pixel circuit, 215...first device layer, 220...first wiring layer, 230...second device layer, 240...second wiring layer, 250...interlayer wiring, 260...first semiconductor layer, 260 a...first semiconductor substrate, 270...interlayer insulating layer, 270a...first interlayer insulating film, 270b...second interlayer insulating film, 270c...third interlayer insulating film, 280...second semiconductor layer, 280a...second layer material insulating film, 280b...third layer material insulating film, 290a...N-type polysilicon pad, 290b...shared contact, 310...transfer side interlayer wiring, 320...shielding electrode, 320a...shielding electrode material layer, 320b...shielding side electrode material, 330...gate side interlayer wiring, 340...shielding side wiring, 400...channel semiconductor substrate, 410...fifth basic insulating film, 411...fifth lateral Insulating film, 420...spacer layer, 500a...gate side inclined portion, 500b...first high concentration side inclined portion, 500c...second high concentration side inclined portion, 500d...protective film, LN (LNa to LNd)...low concentration N-type region, DL...depletion layer, TP...interface trap, T1...film thickness of first insulating film 5a, T2...film thickness of second insulating film 5b, T3...film thickness of third insulating film 5c, CPa...first parasitic capacitance, CPb...second parasitic capacitance, SCC...solid-state imaging element, TR...transfer transistor, SD...semiconductor device, SP...sensor pixel, RC...readout circuit, FDG...FD transfer transistor

Claims

1. a first semiconductor layer in which a pixel circuit is arranged, the pixel circuit including a photodiode, a transfer transistor connected to the photodiode, and a floating diffusion; an interlayer insulating layer laminated on the first semiconductor layer; a second semiconductor layer which is a semiconductor layer in which an amplifying transistor including a semiconductor device is arranged and which is laminated on the interlayer insulating layer; a transfer-side interlayer wiring penetrating the interlayer insulating layer and the second semiconductor layer is connected to the transfer transistor; The semiconductor device includes: A lightly doped N-type region; a first high concentration N-type region and a second high concentration N-type region that are stacked in a direction perpendicular to a direction in which the first semiconductor layer and the second semiconductor layer are stacked with the lightly doped N-type region therebetween and have a higher impurity concentration than the lightly doped N-type region; a gate electrode facing at least a portion of the low concentration N-type region; a shielding electrode facing at least a portion of the low concentration N-type region different from a portion facing the gate electrode; a first insulating film disposed between the gate electrode and the low concentration N-type region; a second insulating film disposed between the gate electrode and the first high concentration N-type region; the first high concentration N-type region is connected to one of a source electrode and a drain electrode; the second high concentration N-type region is connected to the other of the source electrode and the drain electrode; the lightly doped N-type region is a rectangle having two sides parallel to the stacking direction and two sides perpendicular to the stacking direction when viewed from a stacking direction in which the lightly doped N-type region, the first heavily doped N-type region, and the second heavily doped N-type region are stacked, the gate electrode is connected to the floating diffusion by a gate-side interlayer wiring penetrating the interlayer insulating layer and the second semiconductor layer, and is electrically connected to the first semiconductor layer; the shielding electrode is electrically connected to a portion different from the first semiconductor layer and the second semiconductor layer; The gate electrode and the shielding electrode face three or four sides of the low concentration N-type region when viewed from the stacking direction.

2. the gate electrode faces, as viewed from the stacking direction, one of the two parallel sides that is farther from the first semiconductor layer and one of the two perpendicular sides that is closer to the gate-side interlayer wiring; The solid-state imaging element according to claim 1 , wherein the shielding electrode faces one of the two parallel sides that is closer to the first semiconductor layer, and one of the two perpendicular sides that is closer to the transfer side interlayer wiring, when viewed from the stacking direction.

3. the gate electrode faces one of the two parallel sides and the two orthogonal sides that is closer to the gate-side interlayer wiring when viewed from the stacking direction, 2. The solid-state imaging device according to claim 1, wherein the shielding electrode faces one of the two orthogonal sides closer to the transfer-side interlayer wiring when viewed from the stacking direction.

4. the gate electrode faces, when viewed from the stacking direction, one of the two parallel sides that is closer to the first semiconductor layer and one of the two perpendicular sides that is closer to the gate-side interlayer wiring; 2. The solid-state imaging device according to claim 1, wherein the shielding electrode faces one of the two orthogonal sides closer to the transfer-side interlayer wiring when viewed from the stacking direction.

5. the gate electrode faces one of the two orthogonal sides that is closer to the gate-side interlayer wiring when viewed from the stacking direction, The solid-state imaging element according to claim 1 , wherein the shielding electrode faces one of the two parallel sides that is closer to the first semiconductor layer, and one of the two perpendicular sides that is closer to the transfer side interlayer wiring, when viewed from the stacking direction.

6. the gate electrode faces the two parallel sides when viewed from the stacking direction, the shielding electrode faces the two perpendicular sides as viewed from the stacking direction, a fifth insulating film disposed between the shielding electrode and the lightly doped N-type region; 2. The solid-state imaging device according to claim 1, wherein the fifth insulating film is thicker than the first insulating film.

7. The gate electrode and the shielding electrode are integrated together, 7. The solid-state imaging device according to claim 6, wherein the integrated gate electrode and shield electrode surrounds the low-concentration N-type region when viewed from the stacking direction.

8. the gate electrode has a low-concentration region facing portion which is a portion facing the low-concentration N-type region, and a high-concentration region facing portion which is a portion facing at least one of the first high-concentration N-type region and the second high-concentration N-type region, 2. A solid-state imaging element as described in claim 1, wherein the distance between the high concentration region opposing portion and at least one of the first high concentration N-type region and the second high concentration N-type region is longer than the distance between the low concentration region opposing portion and the low concentration N-type region.

9. Four of the pixel circuits are disposed on the first semiconductor layer, an N-type polysilicon pad connecting the four floating diffusions included in each of the four pixel circuits; 2. The solid-state imaging device according to claim 1, further comprising a shared contact connecting said N-type polysilicon pad and said amplifying transistor.

Images