Light emitting diode based display pixels for display screens - Patents.com

Abstract

This specification relates to a display pixel (12 i,j For the display pixel, the pixel comprises a light emitting diode (LED), a driver circuit (40) for driving the light emitting diode, and first, second, third and fourth conductive pads (36). The light emitting diode is powered by a first voltage (Vcc) received between the first and second conductive pads. The driver circuit receives a first binary signal (Com i ) and a second binary signal (Data j ) to control the light emitting diode based on the first binary signal (Com i A second binary signal (Data) is received between the third conductive pad and the second conductive pad and alternates between a second voltage (Vdd) lower than the first voltage and a third voltage (Gnd) lower than the second voltage. j A power supply voltage (Vdd) is received between the fourth conductive pad and the second conductive pad and alternates between a second voltage (Vdd) and a third voltage (Gnd). The display pixel includes a circuit (60) for providing a power supply voltage (Vdd) to a drive circuit based on the first binary signal and the second binary signal.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to display pixels comprising light emitting diodes for display screens. [Background technology]

[0002] An image pixel corresponds to a unit element of an image displayed by a display screen. To display a color image, a display screen generally comprises at least three elements, also called display subpixels, for displaying each pixel of the image, each emitting light of a substantially single color (e.g., red, green, and blue). The superposition of the light emitted by the three display subpixels gives the observer a sense of color corresponding to the pixel of the displayed image. In this case, the ensemble formed by the three display subpixels used to display a pixel of the image is called a display pixel of the display screen. Each display subpixel may have a light source, in particular a light-emitting diode.

[0003] The display pixels may be distributed in an array, with each display pixel located at the intersection of a row (or line) and a column of the array. Typically, each row of display pixels is selected in succession, and the display pixels of the selected row are programmed to display a desired image pixel.

[0004] An active array is a screen driving configuration that can keep all pixel rows active for the entire duration of an image, as opposed to an array called passive, in which each row is only active for T=Tframe / N (where Tframe is the duration of the image and N is the number of rows on the screen). This allows for increased brightness of the display screen. Furthermore, lower voltage or current levels can be sent to the control lines of the array, allowing for a larger data flow to be displayed. Summary of the Invention [Problem to be solved by the invention]

[0005] In screens based on micrometer-sized light-emitting diodes formed on electronic circuits, the size of the light-emitting diode circuit is generally smaller than the size of the image pixel due to the high inherent brightness of the light-emitting diodes. Therefore, one solution used is to deposit these unit light-emitting diodes on a support (also called a panel) that also contains driving electronics. Another solution uses display pixels that include a light-emitting diode and a circuit for controlling the light-emitting diode. Such display pixels are called smart pixels. This simplifies the formation of the active array, in particular because most of the control electronics for the light-emitting diodes of the display pixel are embedded in the display pixel. An example of a smart pixel is described in the document WO 2018 / 185433.

[0006] In a smart pixel, the size of the smart pixel is determined by the number of conductive pads of the smart pixel used to electrically connect the smart pixel to the support, in particular the minimum size of these conductive pads and the minimum space provided between these conductive pads. In order to limit the number of conductive pads, it is known to supply one power supply voltage to the display pixels, with each display pixel generating one or more reduced power supply voltages internally, in particular for biasing components of the control electronics.

[0007] The static power consumption of a display pixel corresponds to the power consumed by the display pixel when it is not emitting light. Such power may consist of component leakage current or current required for the internal operation of the display pixel's control circuitry. In a smart pixel, the majority of the static power consumption is due to the generation of the power supply voltage within the smart pixel.

[0008] To avoid generating the power supply voltage within the smart pixel, it may be envisioned to provide an additional conductive pad for each smart pixel to supply a reduced power supply voltage to the smart pixel, however, this may increase the size of the smart pixel, which is undesirable.

[0009] There is a trend to increase the number of display pixels in display screens. Therefore, the static power consumption of the display pixels can become an important factor. In fact, for so-called 4K display screens with a resolution of 2,160 x 3,840 display pixels, the static power consumption of the display screen can exceed 150 W.

[0010] There is a need to reduce the static power consumption of display screens.

[0011] It is an object of embodiments to provide a display screen with light emitting diodes that overcomes all or some of the disadvantages of existing display screens with light emitting diodes.

[0012] Another object of an embodiment is to limit the number of interconnections between the display pixel and the display pixel support so that the display pixel has a size of less than 200 μm. [Means for solving the problem]

[0013] An embodiment provides a display pixel for a display screen, the display pixel comprising: at least one light emitting diode; a drive circuit for driving the light emitting diode; and a first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad, wherein the light emitting diode is powered by a first voltage received between the first conductive pad and the second conductive pad; the drive circuit configured to control the light emitting diode based on a first binary signal and a second binary signal, the first binary signal being received between the third conductive pad and the second conductive pad and alternating between a second voltage lower than the first voltage and a third voltage lower than the second voltage; and the second binary signal being received between the fourth conductive pad and the second conductive pad and alternating between the second voltage and the third voltage, the display pixel further comprising circuitry for providing a power supply voltage for powering the drive circuit based on the first binary signal and the second binary signal and equal to within 10% of the second voltage.

[0014] This advantageously allows a reduced power supply voltage to be generated within the display pixels while reducing the static power consumption of the display pixels, as the reduced power supply voltage is not generated from the first power supply voltage of the light emitting diode within each display pixel.

[0015] According to the embodiment, the circuit for supplying the power supply voltage includes a first switch connecting the third conductive pad and a node for supplying the power supply voltage, and a second switch connecting the fourth conductive pad and the node, so that the structure of the circuit for supplying the power supply voltage is simple.

[0016] According to an embodiment, the circuit for supplying the power supply voltage includes a first circuit for controlling the first switch configured to control the first switch to ON when the first binary signal is at the second voltage and to control the first switch to OFF when the first binary signal is at the third voltage, and a second circuit for controlling the second switch configured to control the second switch to OFF when the second binary signal is at the third voltage. Thus, as soon as the first binary signal becomes the second voltage, the power supply voltage for the drive circuit is preferentially obtained from the first binary signal.

[0017] According to an embodiment, the second circuit for controlling the second switch is configured to control the second switch to be on when the second binary signal is at the second voltage and the first binary signal is at the third voltage, and to control the second switch to be off when the first binary signal is at the second voltage. Thus, the power supply voltage of the drive circuit is obtained from the second binary signal only when the first binary signal is at the third voltage or the second voltage.

[0018] According to the embodiment, the first switch is a first MOS transistor and the second switch is a second MOS transistor, which makes it possible to easily form a circuit that supplies a power supply voltage integrally.

[0019] According to the embodiment, the gate of the first MOS transistor is connected to the third conductive pad, and the gate of the second MOS transistor is connected to the fourth conductive pad. Since the first MOS transistor and the second MOS transistor are directly controlled by the first binary signal and the second binary signal, the circuit for supplying the power supply voltage is simplified.

[0020] According to an embodiment, the circuit for providing the power supply voltage comprises a capacitor having a first plate connected to the node and a second plate coupled to the second conductive pad, thereby ensuring a substantially constant power supply voltage even when both the first binary signal and the second binary signal are at a third voltage.

[0021] According to an embodiment, the circuit for supplying a supply voltage does not comprise a capacitor having a plate connected to the node, so that the circuit for supplying a supply voltage has a particularly simple structure.

[0022] According to an embodiment, the driver circuit is configured to determine a digital signal from the value of the second binary signal received during each first pulse during which the first binary signal is at the second voltage, and to control the light-emitting diode based on the digital signal, the first binary signal being advantageously used to clock the driver circuit to obtain the value of the second binary signal.

[0023] According to an embodiment, the driver circuit is configured to determine a digital signal from the value of the second binary signal received during each first pulse during which the first binary signal is at the third voltage, and to control the light-emitting diode based on the digital signal. The first pulses during which the first binary signal is at the third voltage can clock the driver circuit to obtain the value of the second binary signal, thereby advantageously transmitting the first binary signal at the second voltage during the first pulses.

[0024] According to an embodiment, the driver circuit is configured to determine a digital signal from the value of the second binary signal received immediately after each first pulse during which the first binary signal is at the third voltage, and to control the light-emitting diode based on the digital signal, thereby enabling the second binary signal to be emitted at the second voltage during the first pulse.

[0025] According to the embodiment, the drive circuit is configured to control the light emitting diode by pulse width modulation based on the digital signal, thereby making it possible to control the light emitting diode at an optimum operating point.

[0026] According to an embodiment, the display pixel comprises only the first conductive pad, the second conductive pad, the third conductive pad and the fourth conductive pad, which is advantageous in reducing the number of conductive pads in a display pixel.

[0027] According to an embodiment, the drive circuit is configured to turn the light emitting diode on or off during a second pulse period when the first binary signal is at the second voltage or the third voltage, the first binary signal being advantageously used to clock the drive circuit to control the light emitting diode.

[0028] Embodiments further provide a display screen comprising an array of display pixels as previously defined, and further comprising circuitry for providing, for each said display pixel, the first voltage between the first conductive pad and the second conductive pad, sending the first binary signal between the third conductive pad and the second conductive pad, and sending the second binary signal to the fourth conductive pad.

[0029] Embodiments further provide a method for controlling a display screen comprising an array of display pixels as previously defined, comprising providing, for each said display pixel, the first voltage between the first conductive pad and the second conductive pad, sending the first binary signal between the third conductive pad and the second conductive pad, and sending the second binary signal to the fourth conductive pad, thus reducing the number of signals / voltages sent to each display pixel to control and power it.

[0030] According to an embodiment, the method includes, during operation, transmitting the first and second binary signals such that a ratio of an average duration that at least one of the first and second binary signals is at the second voltage to a sum of an average duration that the first and second binary signals are at the third voltage and an average duration that at least one of the first and second binary signals is at the second voltage is higher than 75%, thereby advantageously enabling a stable power supply voltage to be supplied within a display pixel.

[0031] According to an embodiment, the method comprises delivering the first and second binary signals such that during operation at least one of the first and second binary signals is at the second voltage at all times, thereby advantageously enabling a stable power supply voltage to be provided within a display pixel for each display pixel without the need for compression within the display pixel.

[0032] According to an embodiment, the method comprises sending, for each display pixel, first pulses during which the first binary signal is at the second voltage, and the drive circuit of the display pixel is configured to determine a digital signal based on the value of the second binary signal it receives during each first pulse during which the first binary signal is at the second voltage, and to control the light emitting diode based on the digital signal, the first binary signal being advantageously used to clock the drive circuit for controlling the light emitting diode.

[0033] According to an embodiment, the method comprises sending, for each display pixel, first pulses during which the first binary signal is at the third voltage, and the drive circuit of the display pixel is configured to determine a digital signal based on the value of the second binary signal it receives during each first pulse during which the first binary signal is at the third voltage, and to control the light-emitting diode based on the digital signal. The first pulses during which the binary signal is at the third voltage can clock the drive circuit to obtain the value of the second binary signal, thereby advantageously sending the first binary signal at the second voltage during the first pulses.

[0034] According to an embodiment, the method includes sending, for each display pixel, a first pulse during which the first binary signal is at the third voltage, and the drive circuit is configured to determine a digital signal based on the value of the second binary signal received immediately after each first pulse during which the first binary signal is at the third voltage, and to control the light-emitting diode based on the digital signal, thereby enabling the second binary signal to be sent at the second voltage during the first pulse. [Brief explanation of the drawings]

[0035] The foregoing and other features and advantages will be described in detail in the remainder of this disclosure of particular embodiments, given by way of non-limiting example with reference to the accompanying drawings, in which:

[0036] [Figure 1] FIG. 2 is a partial schematic diagram of an example display screen. [Figure 2] 1 is a highly schematic cross-sectional view of an example display pixel; [Figure 3] 3 is a bottom view showing the display pixel of FIG. 2. FIG. [Figure 4] 3 is a block diagram showing an example of a display pixel in FIG. 2. FIG. [Figure 5] 2 is a block diagram illustrating an embodiment according to the present invention of a display pixel of the display screen of FIG. 1; [Figure 6] 6 is a block diagram illustrating an embodiment of a circuit for providing reduced voltages for the display pixels of FIG. 5. [Figure 7] 6 is a block diagram illustrating another embodiment of a circuit for providing reduced voltages for the display pixels of FIG. 5. [Figure 8] 6 is a timing diagram illustrating example signals for the display pixel of FIG. 5 according to an embodiment of a method of operating the display screen. [Figure 9] 6 is a timing diagram illustrating example signals for the display pixel of FIG. 5 according to another embodiment of a method of operating the display screen. [Figure 10]6 is a timing diagram illustrating signals for the display pixel of FIG. 5 according to another embodiment of a method of operating the display screen. [Figure 11] 6 is an electrical circuit diagram illustrating an embodiment of a current source for the display pixel of FIG. 4 or FIG. 5; [Figure 12] 6 is an electrical circuit diagram illustrating another embodiment of a current source for the display pixel of FIG. 4 or FIG. 5. DETAILED DESCRIPTION OF THE INVENTION

[0037] In the various figures, like features are indicated by like reference numerals. In particular, structural and / or functional features common to various embodiments may have the same reference numerals and may have the same structural, dimensional, and material characteristics. For clarity, only those steps and elements useful for understanding the embodiments described herein are shown and described in detail.

[0038] In the following description, when reference is made to terms that qualify absolute positions such as "front," "back," "top," "bottom," "left," and "right," or terms that qualify relative positions such as "above," "below," "upper," and "lower," or terms that qualify directions such as "horizontal" and "vertical," the terms refer to the display screen in its drawing orientation or normal position of use, unless otherwise specified.

[0039] Unless otherwise indicated, when referring to two elements connected together, this refers to a direct connection without any intermediate elements other than conductors, and when referring to two elements linked together, this refers to the fact that the two elements may be connected or may be linked via one or more other elements.

[0040] Furthermore, a signal that alternates between a first constant state, e.g., a low state designated "0," and a second constant state, e.g., a high state designated "1," is referred to as a "binary signal." The high and low states of different binary signals of the same electronic circuit may be different. In fact, a binary signal may correspond to a voltage that may not be perfectly constant in either the high or low state.

[0041] Furthermore, in the following description, the source and drain of an insulated gate field effect transistor, or MOS transistor, are referred to as the "power terminals" of the insulated gate field effect transistor, or MOS transistor.

[0042] Furthermore, unless otherwise indicated, when referring to the voltage of a conductive pad, the difference between the potential of said conductive pad and a reference potential, for example ground, which is considered to be 0V, is taken into account.

[0043] Furthermore, as used herein, the terms "insulating" and "conducting" are considered to refer to "electrically insulating" and "electrically conducting," respectively.

[0044] The terms "about," "approximately," "substantially," and "to the extent," unless otherwise specified, refer to within 10%, preferably within 5%, of the relevant value.

[0045] 1 shows, partially and diagrammatically, a known example of a display screen 10. The display screen 10 comprises display pixels 12 arranged, for example, in M ​​rows and N columns. i,j where M is an integer ranging from 1 to 8,000, N is an integer ranging from 1 to 16,000, i is an integer ranging from 1 to M, and j is an integer ranging from 1 to N. For example, in FIG. 1, M and N are 6. Each display pixel 12 i,j Electrode 14 i is connected to a low reference potential source Gnd, e.g., ground, via the electrode 16 j 1. The electrode 14 is connected to a high reference potential source Vcc via i are shown aligned along a row in FIG. 1, and electrodes 16 jare shown aligned along a column in FIG. 1, although the reverse arrangement is possible. The power supply voltage of the display screen corresponds to a voltage between a high reference potential Vcc and a low reference potential Gnd, and is denoted as Vcc, like the high reference potential. The power supply voltage Vcc is determined depending on, among other things, the layout of the light-emitting diodes and the manufacturing technology of the light-emitting diodes. As an example, the power supply voltage Vcc may be about 4V to 5V.

[0046] For each row, 12 display pixels in the row i,j Row electrode 18 i For each column, the display pixels 12 in the column are connected to i,j is column electrode 20 j The display screen 10 is connected to the row electrodes 18. i The selection circuit 22 is coupled to each row electrode 18. i Select Timing Signal Com i The display screen 10 is adapted to emit column electrodes 20 j The data supply circuit 24 is coupled to each column electrode 20. j Data signal j The selection circuit 22 and the data supply circuit 24 are controlled by a circuit 26 which includes, for example, a processor.

[0047] FIG. 2 shows a display pixel 12 i,j 3 is a highly schematic cross-sectional view of a known example of a display pixel 12 i,j 1 is a bottom view showing each display pixel 12 i,jThe display pixel 30 includes a control circuit 30 covered by a display circuit 32. The display circuit 32 includes at least one light-emitting diode LED, preferably at least three light-emitting diodes LED. The display pixel has a bottom surface 34 and a top surface 35 opposite the bottom surface 34, which are preferably planar and parallel. The control circuit 30 further includes conductive pads 36 (not shown in FIG. 2 ) on the bottom surface 34. The control circuit 30 may correspond to an integrated circuit including electronic components, in particular insulated-gate field-effect transistors (also known as MOS transistors) or thin-film transistors (also known as TFTs). Preferably, the display circuit 32 includes only the light-emitting diodes LED and the conductive elements of these light-emitting diodes LED, while the control circuit 30 includes all the electronic components necessary to control the light-emitting diodes LED of the display circuit 32. Alternatively, the display circuit 32 may include other electronic components in addition to the light-emitting diodes LED. The light emitting diodes LED may be two-dimensional light emitting diodes, also called planar light emitting diodes, having a stack of planar layers, or three-dimensional light emitting diodes, each having a three-dimensional semiconductor element covered by an active area. In FIG. 2, the light emitting diodes LED are shown connected with a common anode. However, it may be desirable to arrange the light emitting diodes LED according to other configurations. For example, the light emitting diodes LED may be connected with a common cathode or may be connected independently of each other.

[0048] According to an embodiment, display pixel 12 i,j has three display sub-pixels emitting light at a first wavelength, a second wavelength, and a third wavelength. According to an embodiment, the first wavelength corresponds to blue light and is in the range of 430 nm to 490 nm. According to an embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to an embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm.

[0049] Each conductive pad 36 corresponds to an electrode 14 shown schematically in FIG. i , 16j , 18 i , 20 j The first conductive pad 36 is connected to a low reference potential source Gnd. The second conductive pad 36 is connected to a high reference potential source Vcc. The third conductive pad 36 is connected to a row electrode 18. i The select timing signal Com i The fourth conductive pad 36 receives the column electrode 20 j and the data signal Data j The size of the conductive pads 36 and their placement on the lower surface 34 are particularly important for the display pixels 12. i,j Design rules and display pixels 12 in a display screen 10 i,j This is determined by the assembly method.

[0050] FIG. 4 shows a display pixel 12 of the display screen 10. i,j 4 is a block diagram showing an example of a power supply voltage used to power the electronics of a block, shown above each block.

[0051] By way of example, display pixel 12 i,j has at least three light emitting diodes, one light emitting diode LED is shown in Figure 4. Each light emitting diode LED is connected in series to a controllable current source CS, which may comprise, for example, a MOS transistor. In this example, for each light emitting diode LED, the anode of the light emitting diode LED is connected to a conductive pad 36 that receives, for example, a high reference potential Vcc, the cathode of the light emitting diode LED is connected to, for example, a terminal of the controllable current source CS, and the other terminal of the controllable current source CS is connected to a conductive pad 36 that receives, for example, a low reference potential Gnd.

[0052] Display pixels: 12 i,jThe display pixel 12 further comprises a drive circuit 40 for driving the controllable current source CS. The drive circuit 40 may comprise, among other things, electronic components such as MOS transistors. It may be desirable to use a low supply voltage of less than 4 V, for example around 1 V or 1.8 V, to power the electronic components of the drive circuit 40, which low supply voltage corresponds to the voltage that may be applied across the power terminals of, for example, a MOS transistor. To this end, the display pixel 12 i,j The circuit 42 (Vdd generation) is used to provide, based on the supply voltage Vcc, a reduced supply voltage Vdd, which is used in particular to power the driver circuit 40. The circuit 42 includes, for example, a voltage divider.

[0053] According to an embodiment, each display pixel 12 i,j The selection timing signal Com is received at one of the conductive pads 36 of i is a binary signal that alternates between a low state "0" and a high state "1", where the low state corresponds to a low reference potential Gnd and the high state "1" corresponds to a low voltage substantially equal to the reduced power supply voltage Vdd. j is a binary signal that alternates between a low state "0" and a high state "1", where the low state corresponds to a low reference potential Gnd and the high state "1" corresponds to a low voltage substantially equal to the reduced power supply voltage Vdd.

[0054] The driver circuit 40 receives the data signal Data j The data signal Data j The drive circuit 40 has a circuit 46 (mode selection) that receives the signal Clk and the signal Data, and the circuit 46 receives the selection timing signal Com. iThe circuit 48 is coupled to the conductive pad 36 for receiving the signal Clk and the signal Data, and is configured to send the signal Clk and the signal Data to a storage circuit 48 (color data register) or to send a PWM signal to a circuit 50 (LED driver) for controlling a controllable current source CS associated with each light emitting diode LED. The storage circuit 48 is configured to store the color signals R, G, and B representing the image pixels to be displayed. The circuit 50 is adapted to control the controllable current sources CS coupled to the light emitting diodes LED with the signals I_red, I_green, and I_blue derived from the color signals R, G, and B and the signal PWM.

[0055] As described below, display pixel 12 i,j In order to limit the number of conductive pads 36 per j , and transmits both the clock signal and the color signals R, G, and B, which represent the desired light intensities of the emitted light at the first wavelength, the second wavelength, and the third wavelength, to each display pixel 12. i,j According to another embodiment, the clock signal Clk can be determined by the selection timing signal Com. i is obtained from

[0056] Display pixels: 12 i,j A significant portion of the static power consumption of the display screen 10 is due to the non-MOS transistor electronic components of the drive circuit 40, particularly the circuit 42 for supplying the reduced power supply voltage Vdd. i,j There is a trend to increase the number of pixels. Therefore, the static power consumption of the display pixels can become an important factor. In fact, for a so-called 4K display screen 10 having a resolution of 2,160 x 3,840 display pixels, the static power consumption of the display screen 10 can exceed 150 W.

[0057] Lower power supply voltage Vdd Display pixel 12 i,j To prevent this from occurring within the display pixel 12 i,j3, an additional conductive pad 36 is provided at each display pixel 12 to provide an additional high reference potential Vdd to the i,j However, a configuration in which the display pixel 12 i,j It may not be possible to add additional conductive pads 36 without increasing the lateral dimensions of the board, which may be undesirable.

[0058] According to an embodiment of the present invention, the reduced voltage Vdd is connected to the signal Com i and data signal Data j Therefore, the total number of conductive pads 36 remains unchanged. i,j This reduces the static power consumption of the display screen. i,j The lateral dimensions of the may not be changed.

[0059] FIG. 5 shows the display pixel 12 i,j 5 is a block diagram illustrating an embodiment of the display pixel 12 of FIG. i,j The circuit 42 for supplying the reduced power supply voltage Vdd is connected to the select timing signal Com i and data signal Data j 4 except that the display pixel 12 shown in FIG. 4 has been replaced with a circuit 60 for receiving Vdd and providing a reduced power supply voltage Vdd. i,j It has the same structure as that of

[0060] FIG. 6 shows the display pixel 12 of FIG. i,j 1 is a block diagram illustrating an embodiment of a circuit 60 for providing a reduced voltage Vdd for the MOSFETs 10 and 11. The circuit 60 is connected to a select and timing signal Com i a first switch T1 connecting the conductive pad 36 receiving the data signal Data j1. Circuit 60 includes a second switch T2 coupling a conductive pad 36 receiving a low reference signal Gnd to node Q. Circuit 60 includes a circuit 64 for providing a signal GT1 to control switch T1 and a circuit 66 for providing a signal GT2 to control switch T2. Circuit 60 includes a capacitor C having a first plate coupled, preferably connected, to node Q and a second plate coupled to conductive pad 36 receiving a low reference signal Gnd. Node Q corresponds to the output of circuit 60 for providing a reduced voltage Vdd.

[0061] Switch T1 selects the timing signal Com i is in state "1", i.e., at voltage Vdd, and the select timing signal Com i When the switch T1 is on, the capacitor C is charged with the voltage Vdd through the switch T1. i Turning switch T1 off when is in state "0" prevents switch T1 from discharging capacitor C. Switch T2 turns off the data signal Data j is in state "1", i.e., at voltage Vdd, and the data signal Data j is in the "0" state, which is equal to 0V, for example. When the switch T2 is on, the capacitor C is charged with the voltage Vdd through the switch T2. j Turning switch T2 off when is in state "0" prevents switch T2 from discharging capacitor C.

[0062] Each switch T1, T2 may correspond to a MOS transistor, for example an N-channel MOS transistor having its source coupled, preferably connected, to node Q. Thus, signal GT1 corresponds to a voltage for controlling the gate of transistor T1, and signal GT2 corresponds to a voltage for controlling the gate of transistor T2.

[0063] In the embodiment shown in FIG. 6, circuit 64 generates a signal Com i The circuit 64 includes a buffer circuit having an input for receiving the signal Com and an output for delivering the signal GT1. i The circuit 66 copies the data signal Data j The first input receives the selected timing signal Com i 1, and an output that delivers signal GT2. i When the select timing signal Com is in the "1" state, i.e., at voltage Vdd, the transistor T1 is on and the transistor T2 is off. Therefore, the capacitor C is charged with voltage Vdd through the switch T1. i is in a state "0" equal to 0V, for example, and the data signal Data j When the select timing signal Com is in state "1", i.e., at voltage Vdd, the transistor T1 is off and the transistor T2 is on. Therefore, the capacitor C is charged with voltage Vdd through the switch T2. i is in a state "0" equal to 0V, for example, and the data signal Data j is in state "0", for example equal to 0 V, transistor T1 is off and transistor T2 is off, and capacitor C does not discharge through transistor T1 and transistor T2.

[0064] Therefore, the selection timing signal Com i or data signal Data j As soon as either of these goes to state "1", the capacitor C is charged to the reduced voltage Vdd. This makes it possible to use a capacitor C with a reduced capacitance, for example in the range of 10 fF to 10 pF.

[0065] FIG. 7 shows the display pixel 12 of FIG. i,j7 is a block diagram illustrating another embodiment of a circuit 60 for providing a reduced voltage Vdd at a voltage Vdd of 1 V. The circuit 60 shown in FIG. 7 has all the elements of the circuit 60 shown in FIG. 6, except that a circuit 64 corresponds to a conductive track connecting the gate of transistor T1 to the drain of transistor T1 (thus, transistor T1 is configured with a diode), and a circuit 66 corresponds to a conductive track connecting the gate of transistor T2 to the drain of transistor T2 (thus, transistor T2 is configured with a diode). The embodiment of FIG. 7 advantageously has better response than the embodiment of FIG. 6.

[0066] According to another embodiment, the circuit 64 is not provided and the switch T1 is connected to the anode of the select timing signal Com i , preferably connected to the conductive pad 36 receiving the data signal Data , and corresponds to a diode with its cathode coupled, preferably connected, to the node Q. According to another embodiment, the circuit 66 is not provided and the switch T2 is j , and corresponds to a diode whose cathode is coupled, preferably connected, to node Q.

[0067] FIG. 8 illustrates an embodiment of a method for displaying an image on a display screen 10 using a display pixel 12 having the structure shown in FIG. i,j FIG. 1 is a timing diagram of signals received by

[0068] The potentials Vcc and Gnd are substantially constant. The image pixels of the new image to be displayed are displayed successively from the row with rank 1 to the row with rank M. The duration between two successive selections of the same row of the display screen 10 is called the frame duration T. The signal Com i The timing diagram of the signal Com1 and the signal Data1 will now be described in detail for the row of rank 1, with the understanding that the timing diagram of the signal Com1 is similar to the timing diagram of the signal Com2, albeit shifted over time. 1,jThe display of a new image pixel by (j ranges from 1 to N) includes a first stage P1 followed by a second stage P2. During the first stage P1, the data signal Data j But each display pixel 12 in the rank 1 row 1,j Only the data signal Data1 is shown in Figure 8. During the second phase P2, each display pixel 12 1,j The light-emitting diode j The control is based on the color signals R, G, and B, which are determined based on the above.

[0069] During the first phase P1, the selection and timing signal Com1 is set to the state "1". The long-term setting of the selection and timing signal Com1 to the state "1" causes each display pixel 12 in the row of rank 1 to 1,j The display pixels 12 in this row are detected by the circuit 46. 1,j During the first phase P1, the data signal Data j is column electrode 20 j Display pixel 12 1,j Each time, the circuit 44 outputs a data signal Data j The clock signal Clk and the data Data are determined based on the pulses of the data signal Data. j Each pulse of the signal Clk may have a first duration or a second duration longer than the first duration. The signal Clk has a rising edge corresponding to a rising edge of the data signal Data j The data Data may correspond to a series of pulses of the same duration that coincide with the rising edge of the pulse of the signal Data within a certain possible deviation. j When the pulse of signal Data has a first duration, it is in state "0" and jmay correspond to a binary signal that is in the "1" state when the pulse of signal Com1 has a second duration. Circuit 46, selected by signal Com1 in the "1" state, transmits data Data, which is stored in circuit 50, in the form of digital signals R, G, and B, whose bits are given by successive values ​​of signal Data, at periods of clock signal Clk. The end of the first period P1 of a row corresponds to the start of the first period P1 of the next row.

[0070] According to an embodiment, display pixel 12 1,j The light emitting diodes LED are controlled by pulse width modulation, i.e. PWM control. For this purpose, during the second phase P2, the selection and timing signal Com1 exhibits a repetitive series of pulses of state "1", which pulses are applied to each display pixel 12 of the row of rank 1 to clock the operation of the circuit 50 for controlling the light emitting diodes LED by pulse width modulation. 1,j The circuit 46 sends the signal Com1 to the circuit 50 (as a PWM signal). The number of successive pulses corresponds to the number of bits in the digital signal R, the digital signal G, and the digital signal B, respectively. For example, if the current source CS corresponds to a MOS transistor, this transistor is turned on or off in the period of the PWM pulse depending on the value "0" or "1" of each bit of the color signal R, the color signal G, or the color signal B, starting from the most significant bit, and remains on or off until the next pulse of the signal Com1. Since the duration between two successive pulses of the signal Com1 is divided by two each time, the total duration during which the light-emitting diode is on depends on the value of the color signal R, the color signal G, or the color signal B. The series of pulses of the signal Com1 is repeated until the next first stage P1 of the row of rank 1, one repetition of which is shown as an example in FIG. 8.

[0071] FIG. 9 illustrates another embodiment of a method for displaying an image on a display screen 10 using a display pixel 12 having the structure shown in FIG. i,j FIG. 1 is a timing diagram of signals received by

[0072] The signals Vcc, Gnd and Data in the embodiment shown in FIG.j The timing diagram of the signal Com in the embodiment shown in FIG. i (i is in the range of 1 to M) is the signal Com i , i.e., signal Com in the embodiment shown in FIG. i is in state "0", the signal Com i (i ranges from 1 to M) is in state “1” and the signal Com i is in the state "1", the signal Com i is in state "0". i,j is the signal Com i is in state "0" for a long time, and the pulse width modulation or PWM control detects the signal Com in state "0" during phase P2. i This is done by pulses of

[0073] Signal Com i is mostly in state "1" in the embodiment described in connection with Figure 9 compared to the embodiment described in connection with Figure 8. This allows capacitor C of circuit 60 to be recharged more frequently to provide the reduced voltage Vdd, thus further reducing the capacitance of capacitor C.

[0074] Generally, according to an embodiment, the signal Com i and signal Data j The average duration that at least one of the signals Com is at a reduced voltage Vdd. i and signal Data j The average duration of the signal Com at the low reference potential Gnd. i and the second signal Data j to the sum of the average durations during which at least one of the voltages Vdd is at the reduced voltage Vdd is greater than 75%, preferably greater than 85%, and more preferably greater than 95%.

[0075] According to another embodiment, the selection circuit 22, the data supply circuit 24 and the circuit 26 are i,j Every 12 display pixels i,j The select timing signal Com is received by the i and data signal Data j Therefore, in this embodiment, the capacitor C of the circuit 60 for supplying the reduced voltage Vdd does not need to be provided.

[0076] FIG. 10 illustrates another embodiment of a method for displaying an image on a display screen 10 using a display pixel 12 having the structure shown in FIG. i,j FIG. 1 is a timing diagram of signals received by

[0077] In FIG. 10, the timing diagrams of signals Com1, Com2, Com3 and Data1 for the rows of rank 1, rank 2 and rank 3 and the columns of rank 1 are shown. i 10. The timing diagram of signal Vcc and signal Gnd, as well as Com1, which are not shown in the embodiment shown in FIG. i The timing diagram of the data signal Data in the embodiment shown in FIG. j The timing diagram of is identical to that shown in Figure 8, except that each stage P1 has two successive stages P1.1 and P1.2. During stage P1.1, to select a row of rank i, the signal Com i (i is in the range of 1 to N) is in the state "0" for a long time, each data signal Data j (j ranges from 1 to N) is kept in state "1". During step P1.2 after step P1.1, the data signal Data j is column electrode 20 j is sent to the display pixel 12 of the row of rank i. i,j is obtained by

[0078] This embodiment is particularly suited to the case where the capacitor C of the circuit 60 for providing the reduced voltage Vdd is not provided. In fact, even if the capacitor C is not provided, the display pixel 12 i,j Always display pixels 12 i,j The signal received by Com i and data signal Data j Since at least one of the nodes Q and Q is in the state "1", the node Q always supplies the voltage Vdd.

[0079] In the above-described embodiment, the display pixel 12 1,j The light emitting diodes LEDs of the display pixels 12 are controlled by pulse width modulation. 1,j The control of the light emitting diode LED may be different from that by pulse width modulation. According to an embodiment, the control of the light emitting diode LED is a current level control.

[0080] FIG. 11 shows an embodiment of a current source CS, in which the current source CS is made up of N controllable basic current sources CS1 to CS N Here, N is an integer equal to or greater than 2. It is preferable that N is equal to the number of bits of the digital color signal R, the digital color signal G, or the digital color signal B. In this embodiment, the basic current source CS j (j ranges from 1 to N) are assembled in parallel between node A1 and node A2. As shown in FIG. 4 or 5, when the light emitting diodes LED are assembled with a common anode, node A1 is coupled, preferably connected, to the cathode of the light emitting diode LED corresponding to the target color, and node A2 is coupled, preferably connected, to a conductive pad 36 coupled to a low reference potential source Gnd. When the light emitting diodes LED are assembled with a common cathode, node A1 is coupled, preferably connected, to a conductive pad 36 coupled to a high reference potential source Vcc, and node A2 is coupled, preferably connected, to the anode of the light emitting diode LED corresponding to the target color.

[0081] Each basic current source CS j is generated by the circuit 50 as a control signal C j For example, the control signal C j is a binary signal corresponding to the bit of rank j of the digital color signal R, the digital color signal G, or the digital color signal B. j When is in a first state, e.g., a low state, the basic current source CS j is off, and the control signal C j When is in a second state, e.g., a high state, the current source CS j works.

[0082] Active current source CS j The greater the number of LEDs, the greater the intensity of the current ICS. According to an embodiment, the current source CS can provide a current ICS with an intensity of one of a number of constant levels, the level being determined depending on the number of conducting general light-emitting diodes. j The currents supplied by each basic current source CS may be the same or different. j is capable of supplying a current of intensity I×2j-1. Therefore, the current source CS is j The current I C S is adapted to supply a current I C S having an intensity which may take any value k×I depending on the input voltage, where k lies in the range 0 to 2M−1.

[0083] According to an embodiment, the control of the light emitting diode LED is an analog control.

[0084] 12 shows an embodiment of a current source CS, in which the current source includes a MOS transistor T assembled in series with a resistor Rs between nodes A1 and A2, where nodes A1 and A2 are defined as described above in connection with FIG. 11. The current source CS further includes a digital-to-analog converter DAC for receiving a digital color signal R, a digital color signal G, or a digital color signal B, and an operational amplifier, the operational amplifier having an inverting input (-) coupled, preferably connected, to the midpoint between the resistor Rs and the MOS transistor DAC, and a non-inverting input (+) for receiving an analog signal delivered by the digital-to-analog converter DAC. The transistor T is substantially turned on in response to the digital color signal R, the digital color signal G, or the digital color signal B delivered to the digital-to-analog converter DAC.

[0085] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations may be combined, and other variations will occur to those skilled in the art. In particular, PWM modulation is performed on the signal Com i To avoid this, use the display pixel 12 i,j The modulation may be generated within the control circuit 30. In other embodiments, PWM modulation may not be used, but linear driving of the light emitting diodes LEDs may be used. In other embodiments, other electro-optical components may be used, such as organic light emitting diodes.

[0086] Finally, the actual implementation of the described embodiments and variants is within the skill of a person skilled in the art based on the functional representations given above. In particular, with respect to the second embodiment shown in Figure 5, it may be advantageous to use an SOI (Silicon-on-Insulator) type structure to facilitate the management of negative voltages.

[0087] This patent application claims priority from French Patent Application No. 21 / 13487, which is incorporated herein by reference.

Claims

1. 1. A display pixel for a display screen, comprising: at least one light emitting diode; a driving circuit for driving the light emitting diode; and a first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad; the light emitting diode is powered by a first voltage received between the first conductive pad and the second conductive pad; the drive circuit is configured to control the light emitting diode based on a first binary signal and a second binary signal; the first binary signal is received between the third conductive pad and the second conductive pad and alternates between a second voltage lower than the first voltage and a third voltage lower than the second voltage; the second binary signal is received between the fourth conductive pad and the second conductive pad and alternates between the second voltage and the third voltage; the display pixel further comprising circuitry for supplying a power supply voltage for powering the drive circuitry, the power supply voltage being equal to within 10% of the second voltage based on the first binary signal and the second binary signal.

2. 2. The display pixel of claim 1, wherein the circuit for supplying the power supply voltage comprises a first switch connecting the third conductive pad and a node supplying the power supply voltage, and a second switch connecting the fourth conductive pad and the node.

3. 3. The display pixel of claim 2, wherein the circuit for supplying the power supply voltage comprises: a first circuit for controlling the first switch configured to control the first switch to on when the first binary signal is at the second voltage and to control the first switch to off when the first binary signal is at the third voltage; and a second circuit for controlling the second switch configured to control the second switch to off when the second binary signal is at the third voltage.

4. 4. The display pixel of claim 3, wherein a second circuit for controlling the second switch is configured to control the second switch to be on when the second binary signal is at the second voltage and the first binary signal is at the third voltage, and to control the second switch to be off when the first binary signal is at the second voltage.

5. The display pixel of any one of claims 2 to 4, wherein the first switch is a first MOS transistor and the second switch is a second MOS transistor.

6. 5. The display pixel of claim 1, wherein the drive circuit is configured to determine a digital signal from a value of the second binary signal received based on a first pulse of the first binary signal, and to control the light emitting diode based on the digital signal.

7. 7. The display pixel of claim 6, wherein the drive circuit is configured to determine a digital signal from a value of the second binary signal received during a respective first pulse while the first binary signal is at the second voltage, or during a respective first pulse while the first binary signal is at the third voltage, or immediately after the first binary signal changes from the third voltage to the second voltage of each first pulse, and to control the light emitting diode based on the digital signal.

8. The display pixel of claim 6 , wherein the drive circuit is configured to control the light emitting diode by pulse width modulation based on the digital signal.

9. 5. The display pixel according to claim 1, wherein no conductive pads are provided other than the first conductive pad, the second conductive pad, the third conductive pad and the fourth conductive pad.

10. 5. The display pixel of claim 1, wherein the drive circuit is configured to turn the light emitting diode on or off at a second pulse period during which the first binary signal is at the second voltage or the third voltage.

11. Comprising an array of display pixels according to any one of claims 1 to 4, the display screen further comprising circuitry for providing the first voltage between the first conductive pad and the second conductive pad, for transmitting the first binary signal between the third conductive pad and the second conductive pad, and for transmitting the second binary signal to the fourth conductive pad for each of the display pixels.

12. A method for controlling a display screen comprising an array of display pixels according to any one of claims 1 to 4, comprising the steps of: providing, for each of the display pixels, the first voltage between the first conductive pad and the second conductive pad, transmitting the first binary signal between the third conductive pad and the second conductive pad, and transmitting the second binary signal to the fourth conductive pad.

13. 13. The method of claim 12, further comprising transmitting the first and second binary signals such that during operation, a ratio of an average duration that at least one of the first and second binary signals is at the second voltage to a sum of an average duration that the first and second binary signals is at the third voltage and an average duration that at least one of the first and second binary signals is at the second voltage is higher than 75%.

14. 14. The method of claim 13, further comprising transmitting the first binary signal and the second binary signal such that during operation at least one of the first binary signal and the second binary signal is at the second voltage at all times.

15. sending a first pulse for each of the display pixels such that the first binary signal is at the second voltage or the third voltage; 13. The method of claim 12, wherein the drive circuitry of the display pixel is configured to determine a digital signal based on a value of the second binary signal it receives during a respective first pulse during which the first binary signal is at the second voltage or the third voltage, and to control the light emitting diode based on the digital signal.

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