Methods of forming microelectronic devices and related microelectronic devices and electronic systems

Abstract

The microelectronic device includes a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure includes a stack structure having tiers each including a conductive structure and an insulating structure, a staircase structure confined within the staircase region and having a step including edges of the tiers of the stack structure in a deck and an additional deck, and a semiconductor pillar structure confined within the memory array region and extending through the stack structure. The stack structure includes a deck including a group of tiers, an additional deck above the deck and including the additional group of tiers, and an inter-deck section between the deck and the additional deck including a dielectric structure confined within the memory array region and another group of tiers within a vertical boundary of the dielectric structure and confined within the staircase region.

Description

[Technical field]

[0001] [Priority claim] This application was filed on February 24, 2020. U.S. Patent Application Serial No. 16 / 799,254 For “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, AND ELECTRONIC SYSTEMS” This is a national phase application of international patent application PCT / US2021 / 017430, which was published in English as International Patent Publication WO2021 / 173346 A1 on September 2, 2021, and which designates Japan and claims the benefit of Article 8 of the Patent Cooperation Treaty (PCT). .

[0002] [Technical field] The disclosure in various embodiments relates generally to the field of microelectronic device design and manufacturing. More specifically, the disclosure relates to methods of forming microelectronic devices, as well as related microelectronic devices, memory devices, and electronic systems. [Background technology]

[0003] A continuing goal of the microelectronics industry is to increase the memory density (e.g., number of memory cells per memory die) of memory devices such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase the memory density of non-volatile memory devices is to utilize a vertical memory array (also referred to as a "three-dimensional (3D) memory array") architecture. A conventional vertical memory array includes vertical memory strings that extend through openings in one or more stack structures that include conductive structures and tiers of dielectric material. Each vertical memory string may include at least one select device coupled in series to a series combination of vertically stacked memory cells. Such a configuration allows for more switching devices (e.g., transistors) to be placed per unit of die area (i.e., length and width of consumed active surface) by building the arrays upwards (e.g., vertically) on the die, as compared to structures having a conventional planar (e.g., two-dimensional) array of transistors.

[0004] Vertical memory array architectures typically include electrical connections between conductive structures of a tier of stacked structures of memory devices and access lines (e.g., word lines) so that memory cells of the vertical memory array can be uniquely selected for write, read, or erase operations. One method of forming such electrical connections includes forming so-called "staircase" (or "stair-step") structures at the edges (e.g., horizontal edges) of the tiers of stacked structures of memory devices. The staircase structures include individual "steps" that define contact areas of the conductive structures, over which conductive contact structures are positioned to provide electrical access to the conductive structures.

[0005] As vertical memory array technology advances, improved memory density is provided by forming memory devices to exhibit multiple deck (e.g., dual deck) configurations. For example, in one conventional dual deck configuration, some vertical memory strings are disposed in an upper deck including a first stack structure, and additional vertical memory strings are disposed in a lower deck below the upper deck and including a second stack structure. The vertical memory strings of the upper deck may be electrically isolated (e.g., via an inter-deck dielectric structure) from the additional vertical memory strings of the lower deck, or the vertical memory strings of the upper deck may be electrically coupled (e.g., via a conductive interconnect structure extending through the inter-deck dielectric structure) to the additional vertical memory strings of the lower deck. Unfortunately, conventional methods of forming multiple deck (e.g., dual deck) configurations may result in relatively thick inter-deck dielectric structures vertically interposed between different decks, which may prevent efficient formation of staircase structures in the lower deck. Inter-deck dielectric structures may, for example, disrupt the vertically alternating sequence of first structures (e.g., insulating structures) and second structures (e.g., additional insulating structures, conductive structures) in different decks, thereby preventing simple and efficient transfer of one or more staircase structure configurations from a higher deck into a lower deck using conventional chopping processes. As a result, forming desired staircase structures in stack structures on different decks may require complex, inefficient, and expensive processes (e.g., separate staircase formation processes each including a series of masking and etching operations) for each of the different decks.

[0006] Thus, there remains a need for new methods of forming microelectronic devices (e.g., memory devices such as 3D NAND flash memory devices) that facilitate increased memory density while mitigating the problems of conventional methods of forming microelectronic devices, as well as new microelectronic devices and new electronic systems formed using such methods. Summary of the Invention

[0007] In some embodiments, the microelectronic device includes a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure includes a stack structure, a staircase structure, and a semiconductor pillar structure. The stack structure has tiers each including a conductive structure and an insulating structure vertically adjacent the conductive structure. The stack structure includes a deck including a group of tiers, an additional deck vertically above the deck including an additional group of tiers, and an inter-deck section vertically between the deck and the additional deck. The inter-deck section includes a dielectric structure horizontally confined in the memory array region and another group of tiers horizontally confined within the vertical boundary of the dielectric structure and within the staircase region. The staircase structure is horizontally confined in the staircase region and has a step including edges of the tiers of the stack structure in the deck and the additional deck. The semiconductor pillar structure is horizontally confined in the memory array region and extends vertically through the stack structure.

[0008] In an additional embodiment, a method of forming a microelectronic device includes forming a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure is formed to include a first preliminary stack structure including a vertically alternating sequence of first and second insulating structures arranged in tiers. A dielectric structure is formed in an upper portion of the first preliminary stack structure and is substantially confined within a horizontal boundary of the memory array region. A second preliminary stack structure is formed above the first preliminary stack structure and the dielectric structure. The second preliminary stack structure includes a vertically alternating sequence of additional first and additional second insulating structures arranged in additional tiers. A semiconductor pillar structure is formed to extend vertically through the second preliminary stack structure, the dielectric structure, and portions of the first preliminary stack structure in the memory array region. Staircase structures are formed within portions of the second preliminary stack structure and the first preliminary stack structure in the staircase region. Some of the staircase structures have steps that include horizontal ends of the tiers of the first preliminary stack structure. Others of the staircase structures have additional steps that include horizontal ends of additional tiers of the second preliminary stack structure. The second insulating structure and the additional second insulating structure are at least partially replaced with the conductive structure.

[0009] In yet an additional embodiment, the microelectronic device includes a microelectronic device structure including a stack structure, a staircase structure, and a semiconductor pillar structure. The stack structure has tiers each including a conductive structure and an insulating structure vertically adjacent the conductive structure. The stack structure includes a lower deck including some of the tiers, an upper deck above the lower deck including others of the tiers, and an inter-deck section between the lower deck and the upper deck. The inter-deck section includes an inter-deck dielectric structure and an additional tier horizontally between the inter-deck dielectric structures. The additional tiers each include an additional insulating structure and a further insulating structure vertically adjacent the additional insulating structure. The staircase structure has steps including edges of the tiers of the stack structure in the lower deck and the upper deck. The semiconductor pillar structure extends vertically through the stack structure.

[0010] In a further embodiment, a method of forming a microelectronic device includes forming a microelectronic device structure including a first preliminary stack structure including a vertically alternating sequence of first insulating structures and second insulating structures arranged in tiers. A vertically extending dielectric structure is formed in the first preliminary stack structure. The dielectric structures are horizontally spaced apart from one another in a first direction and extend horizontally substantially linearly in a second direction orthogonal to the first direction. A second preliminary stack structure is formed above the first preliminary stack structure and the dielectric structure. The second preliminary stack structure includes a vertically alternating sequence of additional first insulating structures and additional second insulating structures arranged in additional tiers. A semiconductor pillar structure is formed to extend vertically through a portion of the second preliminary stack structure and the first preliminary stack structure positioned horizontally between the dielectric structures. A staircase structure is formed in the second preliminary stack structure and the first preliminary stack structure. Some of the staircase structures having steps include edges of the tiers of the first preliminary stack structure. Others of the staircase structures have additional steps that include edges of additional tiers of the second preliminary stack structure. Additional second insulating structures of the second preliminary stack structure and second insulating structures of the first preliminary stack structure positioned outside the vertical boundaries of the dielectric structures are replaced with conductive structures.

[0011] In yet another embodiment, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device and including at least one microelectronic device structure having a memory array region and a staircase region. The at least one microelectronic device structure includes a stack structure, a staircase structure, and a semiconductor pillar structure. The stack structure has tiers each including a conductive structure and an insulating structure vertically adjacent the conductive structure. The stack structure includes a deck including some of the tiers, an additional deck vertically above the deck and including others of the tiers, and an inter-deck section vertically between the deck and the additional deck. The inter-deck section includes at least one dielectric structure that is within a horizontal boundary of the memory array region and does not substantially exist or extend completely across a horizontal region of the staircase region. The staircase structure is within the staircase region and has a step that includes an edge of a tier of the stack structure in the deck and the additional deck. The semiconductor pillar structure is within the memory array region and extends vertically through the stack structure. [Brief description of the drawings]

[0012] [Figure 1A] 1A-1D are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to disclosed embodiments. [Figure 1B] FIG. 1B is a simplified partial cross-sectional view taken along line AA depicted in FIG. 1A. [Figure 2A] 1A-1D are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to disclosed embodiments. [Figure 2B] FIG. 2B is a simplified partial cross-sectional view taken along line AA depicted in FIG. 2A. [Figure 3A] 1A-1D are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to disclosed embodiments. [Figure 3B] FIG. 3B is a simplified partial cross-sectional view taken along line AA depicted in FIG. 3A. [Figure 4A] 1A-1D are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to disclosed embodiments. [Figure 4B] FIG. 4B is a simplified partial cross-sectional view taken along line AA depicted in FIG. 4A. [Figure 5A] 1A-1D are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to disclosed embodiments. [Figure 5B] FIG. 5B is a simplified partial cross-sectional view taken along line AA depicted in FIG. 5A. [Figure 6A] 1A-1D are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to disclosed embodiments. [Figure 6B] FIG. 6B is a simplified partial cross-sectional view taken along line AA depicted in FIG. 6A. [Figure 7A] 1A-1D are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to disclosed embodiments. [Figure 7B] FIG. 7B is a simplified partial cross-sectional view taken along line AA depicted in FIG. 7A. [Figure 8A] 1A-1D are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to disclosed embodiments. [Figure 8B] FIG. 8B is a simplified partial cross-sectional view taken along line AA depicted in FIG. 8A. [Figure 9A] 1A-1D are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to disclosed embodiments. [Figure 9B] FIG. 9B is a simplified partial cross-sectional view taken along line AA depicted in FIG. 9A. [Figure 10A] 1A-1D are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to disclosed embodiments. [Figure 10B] FIG. 10B is a simplified partial cross-sectional view taken along line AA depicted in FIG. 10A. [Figure 11A] 10A-10C are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to an additional embodiment of the disclosure. [Figure 11B] FIG. 11B is a simplified partial cross-sectional view taken along line BB depicted in FIG. [Figure 12A] 10A-10C are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to an additional embodiment of the disclosure. [Figure 12B] FIG. 12B is a simplified partial cross-sectional view taken along line BB depicted in FIG. 12A. [Figure 13A] 10A-10C are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to an additional embodiment of the disclosure. [Figure 13B] FIG. 13B is a simplified partial cross-sectional view taken along line BB depicted in FIG. 13A. [Figure 14A] 10A-10C are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to an additional embodiment of the disclosure. [Figure 14B] FIG. 14B is a simplified partial cross-sectional view taken along line BB depicted in FIG. 14A. [Figure 15A] 10A-10C are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to an additional embodiment of the disclosure. [Figure 15B] FIG. 15B is a simplified partial cross-sectional view taken along line BB depicted in FIG. 15A. [Figure 16A] 10A-10C are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to an additional embodiment of the disclosure. [Figure 16B] FIG. 16B is a simplified partial cross-sectional view taken along line BB depicted in FIG. 16A. [Figure 17A] 10A-10C are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to an additional embodiment of the disclosure. [Figure 17B] FIG. 17B is a simplified partial cross-sectional view taken along line BB depicted in FIG. 17A. [Figure 18A] 10A-10C are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to an additional embodiment of the disclosure. [Figure 18B] FIG. 18B is a simplified partial cross-sectional view taken along line BB depicted in FIG. 18A. [Figure 19A] 10A-10C are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to an additional embodiment of the disclosure. [Figure 19B] FIG. 19B is a simplified partial cross-sectional view taken along line BB depicted in FIG. 19A. [Figure 20A] 10A-10C are simplified partial cross-sectional views illustrating a method of forming a microelectronic device according to an additional embodiment of the disclosure. [Figure 20B] FIG. 20B is a simplified partial cross-sectional view taken along line BB depicted in FIG. 20A. [Figure 21] FIG. 1 is a simplified partial cutaway perspective view of a microelectronic device according to an embodiment of the disclosure. [Figure 22] FIG. 1 is a schematic block diagram illustrating an electronic system according to an embodiment of the disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The following description provides specific details such as material compositions, shapes, and sizes to provide a complete description of the disclosed embodiments. However, one of ordinary skill in the art will understand that the disclosed embodiments may be practiced without these specific details. Indeed, the disclosed embodiments may be practiced in conjunction with conventional microelectronic device manufacturing techniques used in the industry. Additionally, the description provided below does not form a complete process flow for manufacturing a microelectronic device (e.g., a memory device such as a 3D NAND flash memory device). The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary to understand the disclosed embodiments are described in detail below. Additional actions to form a complete microelectronic device from the structure may be performed by conventional manufacturing techniques.

[0014] The drawings presented herein are for illustrative purposes only and are not meant to be actual views of any particular material, component, structure, device, or system. Variations from shapes depicted in the drawings are expected, for example, as a result of manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes or regions as described, including, for example, deviations in shapes resulting from manufacturing. For example, a region illustrated or described as a box shape may have rough and / or non-linear features, and a region illustrated or described as a circle may include some rough and / or linear features. Furthermore, sharp angles described may be rounded, and vice versa. Thus, the regions depicted in the figures are schematic in nature, and their shapes are not intended to describe the exact shape of the regions and do not limit the scope of the claims. The figures are not necessarily drawn to scale. Additionally, elements common between the figures may retain the same numerical designations.

[0015] As used herein, "memory device" means and includes, but is not limited to, a microelectronic device that exhibits memory functionality.

[0016] As used herein, the terms "vertical", "longitudinal", "horizontal" and "transverse" refer to the major plane of a structure, not necessarily defined by the Earth's gravitational field. A "horizontal" or "transverse" direction is a direction that is substantially parallel to the major plane of the structure, while a "vertical" or "longitudinal" direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of a structure is defined by the surface of the structure that has a relatively large area compared to other surfaces of the structure.

[0017] As used herein, features (e.g., regions, structures, devices) described as "adjacent" to one another refer to and include features of the disclosed entity (or entities) that are in closest (e.g., nearest) position to one another. Additional features (e.g., additional regions, additional structures, additional devices) that do not coincide with the disclosed entity (or entities) of the "adjacent" feature may be disposed between the "adjacent" features. In other words, "adjacent" features may be positioned directly adjacent to one another such that there are no intervening features between the "adjacent" features, or "adjacent" features may be positioned indirectly adjacent to one another such that at least one feature having an entity other than that associated with at least one "adjacent" feature is positioned between the "adjacent" features. Thus, features described as "vertically adjacent" to one another refer to and include features of the disclosed entity (or entities) that are in closest vertical (e.g., nearest) position to one another. Additionally, features described as "horizontally adjacent" to one another mean and include the features of the disclosed entity (or entities) that are in closest horizontal proximity (e.g., horizontally closest) to one another.

[0018] As used herein, the terms "comprising," "including," "having," and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional, unrecited elements or method steps, but also include "consisting of" and "consisting essentially of" and their grammatical equivalents. As used herein, the term "may" in reference to a material, structure, feature, or method act indicates that such terms are intended to be used in implementing the disclosed embodiments and are used in reference to the more restrictive term "is" to avoid any implication that other compatible materials, structures, features, and methods that can be used in combination therewith should or must be excluded.

[0019] As used herein, spatially relative terms such as "under", "lower", "bottom", "upper", "top", "top", "front", "rear", "left", and "right" may be used for ease of description to describe the relationship of an element or feature to another element or feature as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of the material in addition to the orientation depicted in the figures. For example, if the material in the figures were inverted, an element described as "under" or "under" or "below" or "at the bottom of" the other element or feature would then be oriented "above" or "on top" of the other element or feature. Thus, the term "under" can encompass both an orientation of above and below, depending on the context in which the term is used, as would be apparent to one of ordinary skill in the art. The materials may be otherwise oriented (eg, rotated 90 degrees, flipped, inverted) and the spatially relative descriptors used herein may be interpreted accordingly.

[0020] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0021] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] As used herein, the term "configured" refers to a size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device that facilitates the operation of one or more of the structures and devices in a predetermined manner.

[0023] As used herein, the term "substantially" with respect to a given parameter, characteristic, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition meets some degree of variation, such as within an acceptable tolerance. By way of example, depending on the particular parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be at least 90.0 percent met, at least 95.0 percent met, at least 99.0 percent met, at least 99.9% met, or even 100.0 percent met.

[0024] As used herein, "about" or "approximately" with respect to a numerical value for a particular parameter includes the numerical value, and the degree of variation from the numerical value that one of ordinary skill in the art would understand is within the acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value can include additional numerical values ​​within the range of 90.0 percent to 110.0 percent of the numerical value, such as within the range of 95.0 percent to 105.0 percent of the numerical value, within the range of 97.5 percent to 102.5 percent of the numerical value, within the range of 99.0 percent to 101.0 percent of the numerical value, within the range of 99.5 percent to 100.5 percent of the numerical value, or within the range of 99.9 percent to 100.1 percent of the numerical value.

[0025] Unless the context dictates otherwise, the materials described herein may be formed by any suitable process, including, but not limited to, spin coating, blanket coating, chemical vapor deposition ("CVD"), atomic layer deposition ("ALD"), plasma enhanced ALD, physical vapor deposition ("PVD") (including sputtering, evaporation, ionized PVD, and / or plasma enhanced CVD), or epitaxial growth. Depending on the particular material being formed, techniques for depositing or growing the material may be selected by one of skill in the art. Also, unless the context dictates otherwise, removal of the materials described herein may be accomplished by any suitable process, including, but not limited to, etching (e.g., dry etching, wet etching, steam etching), ion milling, abrasive planarization, or other known methods.

[0026] 1A-10B are simplified partial cross-sectional views illustrating an embodiment of a method for forming a microelectronic device (e.g., a memory device such as a 3D NAND flash memory device). FIGs. 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B are simplified partial cross-sectional views about line AA depicted in FIGs. 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A, respectively. Together with the description provided below, it will be readily apparent to one skilled in the art that the methods and structures described herein can be used in a variety of devices and electronic systems.

[0027] 1A, a microelectronic device structure 100 may be formed to include a base structure 102 and a first preliminary stack structure 104 on or above the base structure 102. The microelectronic device structure 100 includes a memory array region 112 and a staircase region 114 horizontally adjacent (e.g., in the X-direction) to the memory array region 112. As described in more detail below, the microelectronic device structure 100 further includes additional components (e.g., features, structures, devices) within the boundaries of its different horizontal regions (e.g., memory array region 112, staircase region 114). FIG. 1B is a simplified partial cross-sectional view of the microelectronic device structure 100 at the processing stage depicted in FIG. 1A about line AA shown in FIG. 1A.

[0028] The base structure 102 of the microelectronic device structure 100 may include a base material or construction on which additional materials and structures of the microelectronic device structure 100 are formed. In some embodiments, the base structure 102 is made of a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), an alloy (Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, The base structure 102 may include a conductive structure formed of at least one conductive material, such as one or more of a Co and Ni-based alloy, an Fe and Co-based alloy, a Co and Ni and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, steel, low carbon steel, stainless steel), a conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped germanium (Ge), conductively doped silicon germanium (SiGe)), and a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). The base structure 102 may be used, for example, as a source structure (e.g., a source plate) for a microelectronic device, as described in more detail below.

[0029] The first preliminary stack structure 104 of the microelectronic device structure 100 includes a vertically (e.g., Z-direction) alternating sequence of first insulating structures 106 and second insulating structures 108 arranged in tiers 110. Each of the tiers 110 of the first preliminary stack structure 104 can include at least one of the first insulating structures 106 vertically adjacent to at least one of the second insulating structures 108. The first preliminary stack structure 104 can include any desired amount of tiers 110. For example, the first preliminary stack structure 104 may include ten (10) or more tiers 110, twenty-five (25) or more tiers 110, fifty (50) or more tiers 110, one hundred (100) or more tiers, one hundred and fifty (150) or more tiers, or two hundred (200) or more tiers of the first insulating structure 106 and the second insulating structure 108.

[0030] The first insulating structure 106 of the tier 110 of the first preliminary stack structure 104 is made of at least one dielectric oxide material (e.g., silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium dioxide (TiO x ), zirconium oxide (ZrO x ), tantalum oxide (TaO x ), and magnesium oxide (MgO x )), at least one dielectric nitride material (e.g., silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )), and at least one dielectric carboxynitride material (e.g., silicon carboxynitride (SiO x C z N y))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) x , AlO x , HfO x , NbO x , TiO x , SiN y , SiO x N y , SiO x C z N y ) represents a material that includes an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). Because the formula represents relative atomic ratios and is not a strict chemical structure, the first insulating structure 106 may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, where the values ​​of "x", "y", and "z" (if present) may be integers or non-integer. As used herein, the term "non-stoichiometric compounds" means and includes chemical compounds that cannot be expressed in a clearly defined ratio of whole numbers and have an elemental composition that violates the law of definite proportionality. Each of the first insulating structures 106 may individually include a substantially uniform or substantially non-uniform distribution of at least one electrically insulating material. As used herein, the term "uniform distribution" means that the amount of material does not vary across different portions of the structure (e.g., different horizontal portions, different vertical portions). Conversely, as used herein, the term "non-uniform distribution" means that the amount of material varies across different portions of the structure. In some embodiments, each of the first insulating structures 106 exhibits a substantially uniform distribution of the electrically insulating material. In further embodiments, at least one of the first insulating structures 106 exhibits a substantially non-uniform distribution of at least one electrically insulating material. One or more of the first insulating structures 106 may be formed of or may include, for example, a stack (e.g., a laminate) of at least two different electrically insulating materials (e.g., at least two different dielectric materials). In some embodiments, each of the first insulating structures 106 may be formed of, or may include, a stack (e.g., a laminate) of at least two different electrically insulating materials (e.g., at least two different dielectric materials).x The first insulating structures 106 may be formed of or include a dielectric oxide material such as silicon dioxide (SiO2). Each of the first insulating structures 106 may be substantially planar and may each individually exhibit a desired thickness. Also, each of the first insulating structures 106 may be substantially identical to one another (e.g., may exhibit substantially the same material composition, material distribution, size, and shape), or at least one of the first insulating structures 106 may be different from at least one other of the first insulating structures 106 (e.g., may exhibit one or more of a different material composition, a different material distribution, a different size, and a different shape). In some embodiments, each of the first insulating structures 106 is substantially identical to each of the other first insulating structures 106.

[0031] The second insulating structure 108 of the tier 110 of the first preliminary stack structure 104 may be formed of or may include at least one additional electrically insulating material. The material compositions of the second insulating structure 108 and the first insulating structure 106 may be selected such that the first insulating structure 106 and the second insulating structure 108 may be selectively removed relative to one another. The second insulating structure 108 may be selectively etchable relative to the first insulating structure 106 during a common (e.g., collectively, mutual) exposure to a first etchant, and the first insulating structure 106 may be selectively etchable relative to the second insulating structure 108 during a common exposure to a second, different etchant. As used herein, a material is "selectively etchable" with respect to another material if the material exhibits an etch rate that is at least about five times (5x) faster than the etch rate of the other material, such as about ten times (10x) faster, about twenty times (20x) faster, or about forty times (40x) faster. The material composition of the second insulating structure 108 is different from the material composition of the first insulating structure 106. The second insulating structure 108 is made of at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x , TiO x, ZrO x , TaO x , and MgO x at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), and at least one dielectric carboxynitride material (e.g., SiO x C z N y In some embodiments, each of the second insulating structures 108 may include one or more of SiN y (e.g., Si3N4). Each of the second insulating structures 108 may individually include a substantially uniform distribution of at least one additional electrically insulating material or a substantially non-uniform distribution of at least one additional electrically insulating material. In some embodiments, each of the second insulating structures 108 of the first preliminary stack structure 104 exhibits a substantially uniform distribution of the additional electrically insulating material. In additional embodiments, at least one of the second insulating structures 108 of the first preliminary stack structure 104 exhibits a substantially non-uniform distribution of at least one additional electrically insulating material. The second insulating structures 108 may, for example, individually be formed of or include a stack (e.g., a laminate) of at least two different additional electrically insulating materials. The second insulating structures 108 may each be substantially planar and each individually exhibit a desired thickness.

[0032] 1A, the microelectronic device structure 100 may further include contact structures 116 in its memory array region 112. The contact structures 116 may function, for example, as source contact structures. The contact structures 116 may be configured (e.g., sized, shaped, material composition) and positioned to facilitate electrical connection between one or more features of the microelectronic device structure 100 (e.g., base structure 102) and one or more additional structures or devices (e.g., pillar structures, vertical strings of memory cells) formed on or above the one or more contact structures 116, as described in more detail below. The contact structures 116 may each be individually formed of or include at least one conductive material, such as a metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), an alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co and Ni and Fe-based alloy, Al-based alloy, Cu-based alloy, Mg-based alloy, Ti-based alloy, steel, low carbon steel, stainless steel), a conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped Ge, conductively doped SiGe), a conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide), or a combination thereof. In some embodiments, the contact structures 116 are formed of or include W. Each of the contact structures 116 may individually include a substantially uniform distribution of at least one conductive material or a non-uniform distribution of at least one conductive material. In some embodiments, each of the contact structures 116 exhibits a substantially uniform distribution of the conductive material. In additional embodiments, at least one of the contact structures 116 exhibits a non-uniform distribution of the at least one conductive material.

[0033] The base structure 102, the first preliminary stack structure 104 (including its first insulating structure 106 and tier 110 of second insulating structure 108), and the contact structure 116 are formed using conventional processes (e.g., conventional material deposition processes, conventional photolithographic patterning processes, conventional material removal processes) and conventional processing equipment that are not described in detail herein.

[0034] Referring now to FIG. 2A, a photoresist structure 118 may be formed on or above a portion of the first preliminary stack structure 104 within the horizontal boundaries of the staircase region 114 of the microelectronic device structure 100. As shown in FIG. 2A, the photoresist structure 118 may be formed to be substantially confined within the staircase region 114 such that the photoresist structure 118 does not extend substantially horizontally into the memory array region 112 of the microelectronic device structure 100. In other words, the photoresist structure 118 may be formed to be substantially (e.g., completely) absent from the memory array region 112 of the first preliminary stack structure 104. FIG. 2B is a simplified partial cross-sectional view of the microelectronic device structure 100 at the processing stage depicted in FIG. 2A about the line AA shown in FIG. 2A.

[0035] The photoresist structure 118 may function as a mask to protect portions of the first preliminary stack structure 104 (e.g., including the first insulating structure 106 and the tier 110 of the second insulating structure 108) that are vertically below and within its horizontal boundaries from removal during subsequent processing, as described in more detail below. The photoresist structure 118 may be formed of or include a photoresist material, such as a positive tone photoresist material or a negative tone photoresist material. Suitable photoresist materials (e.g., positive tone photoresist material, negative tone photoresist material) are known in the art and therefore will not be described in detail herein. The photoresist structure 118 may be compatible with, for example, 13.7 nm, 157 nm, 193 nm, 248 nm, or 365 nm wavelength systems, 193 nm wavelength immersion systems, and / or electron beam lithography systems.

[0036] The photoresist structures 118 may be formed using conventional processes (e.g., conventional deposition processes such as one or more of PVD, CVD, ALD, and spin-coating, conventional photolithography processes, conventional material removal processes), which are known in the art and therefore will not be described in detail herein.

[0037] 3A, the microelectronic device structure 100 may be subjected to a material removal process to selectively remove portions of the relatively vertically tall tier 110 (e.g., the top tier) of the first preliminary stack structure 104 in the memory array region 112 of the microelectronic device structure 100. As shown in FIG. 3A, the material removal process may form a recess 120 (e.g., trench, opening) that extends vertically partially into the first preliminary stack structure 104 in the memory array region 112 of the microelectronic device structure 100. The photoresist structure 118 (FIG. 2A) may be used as a mask during the material removal process to impede or prevent removal of additional portions of the relatively vertically tall tier 110 of the first preliminary stack structure 104 in the staircase region 114 of the microelectronic device structure 100. Thus, the recess 120 may be formed to be substantially confined within the memory array region 112 such that the recess 120 does not extend substantially horizontally into the staircase region 114 of the microelectronic device structure 100. Following formation of recess 120, the remainder (non-removed portions) of photoresist structure 118 (FIG. 2A), if any, may be removed. FIGURE 3B is a simplified partial cross-sectional view of microelectronic device structure 100 at the processing stage depicted in FIGURE 3A about line AA shown in FIGURE 3A.

[0038] The material removal process may be controlled to remove portions of a desired number of tiers 110 of the first preliminary stack structure 104 (e.g., portions not protected by the photoresist structures 118 (FIG. 2A)). As shown in FIG. 3A, in some embodiments, the material removal process removes portions of two (2) relatively vertically tall tiers (e.g., two (2) top tiers) of the first preliminary stack structure 104 including portions of their first insulating structures 106 and second insulating structures 108. In additional embodiments, the material removal process may remove portions of a different number of relatively vertically tall tiers 110 of the first preliminary stack structure 104. As a non-limiting example, the material removal process may be controlled to remove portions of a single (e.g., only one) relatively vertically tall tier (e.g., a top tier) of the first preliminary stack structure 104. As another non-limiting example, the material removal process may be controlled to remove a portion of more than the two (2) vertically highest tiers 110 of the first preliminary stack structure 104, such as a portion of the three (3) relatively vertically highest tiers 110 of the first preliminary stack structure 104 (e.g., the three (3) top tiers), a portion of the four (4) relatively vertically highest tiers of the first preliminary stack structure 104 (e.g., the four (4) top tiers), or five (5) or more relatively vertically highest tiers 110 of the first preliminary stack structure 104 (e.g., five top tiers).

[0039] The portions of the relatively vertically taller tier 110 of the first preliminary stack structure 104 in the memory array region 112 of the microelectronic device structure 100 may be removed using conventional material removal processes (e.g., conventional etching processes such as conventional anisotropic etching processes) not described in detail herein. For example, the portions of the top tier 110 of the first preliminary stack structure 104 in the memory array region 112 of the microelectronic device structure 100 may be removed using an etching cycle that includes removing exposed portions of the second insulating structure 108 of the top tier 110 using a first etching action (e.g., a first anisotropic etching action) and then removing exposed portions of the first insulating structure 106 of the top tier 110 using a second etching action (e.g., a second anisotropic etching action). Portions of the one or more additional tiers 110 of the first preliminary stack structure 104 within the memory array region 112 may then be removed using one or more additional etching cycles similar to the etching cycle to form recesses 120 to a desired vertical depth within the memory array region 112 of the microelectronic device structure 100.

[0040] Following formation of the vertically extending recesses 120 in the first preliminary stack structure 104, remnants, if any, of the photoresist structures 118 (FIG. 2A) may be selectively removed using one or more conventional material removal processes not described in detail herein. For example, the microelectronic device structure 100 may be exposed to a developer (e.g., positive tone developer, negative tone developer) formulated to selectively remove (e.g., develop) remnants of the photoresist structures 118 (FIG. 2A). Suitable developers are known in the art and therefore will not be described in detail herein.

[0041] Referring now to FIG. 4A, a dielectric fill material 122 may be formed on or above the exposed surfaces of the first preliminary stack structure 104 inside and outside the recess 120 (FIG. 3A). As shown in FIG. 4A, the dielectric fill material 122 may be formed to cover and substantially extend (e.g., extend substantially continuously) across the surfaces of the first preliminary stack structure 104 in the memory array region 112 and the staircase region 114 of the microelectronic device structure 100. The dielectric fill material 122 may cover and substantially extend across the surfaces of the first preliminary stack structure 104 at and outside the boundaries (e.g., horizontal boundaries, vertical boundaries) of the recess 120 (FIG. 3A), such as the surfaces at and within the boundaries of the staircase region 114 of the microelectronic device structure 100. The dielectric fill material 122 may be at least partially (e.g., substantially) conformal to a topography defined by the surfaces (e.g., horizontal surfaces, vertical surfaces) on which the dielectric fill material 122 is formed. FIG. 4B is a simplified partial cross-sectional view of the microelectronic device structure 100 at the processing stage depicted in FIG. 4A about line AA shown in FIG. 4A.

[0042] The dielectric fill material 122 may be formed of or may include at least one dielectric material. The material composition of the dielectric fill material 122 may be selected relative to the material composition of the second insulating structures 108 of the preliminary stack structure 100 such that the second insulating structures 108 and the dielectric fill material 122 may be selectively removed relative to one another. The second insulating structures 108 may be selectively etchable relative to the dielectric fill material 122 during a common (e.g., collectively, mutual) exposure to a first etchant, and the dielectric fill material 122 may be selectively etchable relative to the second insulating structures 108 during a common exposure to a second, different etchant. The material composition of the dielectric fill material 122 may be different from the material composition of the second insulating structures 108 and may include at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x, TiO x , ZrO x , TaO x , and MgO x at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), and at least one dielectric carboxynitride material (e.g., SiO x C z N y ). The material composition of the dielectric fill material 122 may be selected to be substantially the same as the material composition of one or more (e.g., each) of the first insulating structures 106 of the first preliminary stack structure 104, or may be selected to be different from the material composition of the first insulating structures 106 of the first preliminary stack structure 104. In some embodiments, the dielectric fill material 122 is a dielectric oxide material (e.g., SiO 2 , such as SiO 2 ). x ). The dielectric fill material 122 may include a substantially uniform distribution of dielectric material or a substantially non-uniform distribution of dielectric material. In some embodiments, the dielectric fill material 122 exhibits a substantially uniform distribution of dielectric material. In additional embodiments, the dielectric fill material 122 exhibits a substantially non-uniform distribution of dielectric material. The dielectric fill material 122 may be formed of or include a stack (e.g., a laminate) of at least two different dielectric materials, for example.

[0043] The dielectric fill material 122 may be formed (e.g., conformally formed) using a conventional process (e.g., a conventional conformal deposition process) not described in detail herein. By way of non-limiting example, the dielectric fill material 122 may be formed via one or more of a conventional CVD process (e.g., a conventional PECVD process) and a conventional ALD process. In some embodiments, the dielectric fill material 122 is formed on the exposed surface of the first preliminary stack structure 104 using a PECVD process.

[0044] Referring now to FIG. 5A, portions of the dielectric fill material 122 (FIG. 4A) outside the boundaries (e.g., horizontal boundaries, vertical boundaries) of the recess 120 (FIG. 3A) may be removed while retaining additional portions of the dielectric fill material 122 (FIG. 4A) inside the boundaries of the recess 120 (FIG. 3A) to form at least one inter-deck dielectric structure 124. As shown in FIG. 5A, the removal process may expose a top surface of the first preliminary stack structure 104 in the staircase region 114 of the microelectronic device structure 100. The top boundary (e.g., top surface) of the inter-deck dielectric structure 124 in the memory array region 112 of the microelectronic device structure 100 may be substantially coplanar with the top boundary (e.g., top surface) of the first preliminary stack structure 104 in the staircase region 114 of the microelectronic device structure 100. FIG. 5B is a simplified partial cross-sectional view of the microelectronic device structure 100 at the processing stage depicted in FIG. 5A about the line AA shown in FIG. 5A.

[0045] 5A , the inter-deck dielectric structure 124 may be substantially confined within the horizontal boundaries of the memory array region 112 of the microelectronic device structure 100. In other words, the inter-deck dielectric structure 124 is formed such that the inter-deck dielectric structure 124 does not extend substantially horizontally into the staircase region 114 of the microelectronic device structure 100. Confining the inter-deck dielectric structure 124 substantially within the horizontal boundaries of the memory array region 112 may alleviate previous issues and complications associated with forming staircase structures within the staircase region 114 of the microelectronic device structure 100, for example, as described in further detail below.

[0046] The portions of the dielectric fill material 122 (FIG. 4A) outside the boundaries (e.g., horizontal boundaries, vertical boundaries) of the recess 120 (FIG. 3A) may be removed from the inter-deck dielectric structure 124 using conventional processes (e.g., conventional planarization processes) not described in detail herein. For example, the portions of the dielectric fill material 122 (FIG. 4A) outside the boundaries of the recess 120 (FIG. 3A) may be removed using at least one chemical mechanical planarization (CMP) process to form the inter-deck dielectric structure 124.

[0047] 6A, an opening 126 (e.g., a via) may be formed in the memory array region 112 of the microelectronic device structure 100, and a plug structure 128 may be formed at an upper vertical boundary (e.g., in the Z direction) of the opening 126 to substantially fill (e.g., cover) the opening 126. Figure 6B is a simplified partial cross-sectional view of the microelectronic device structure 100 at the processing stage depicted in Figure 6A about line AA shown in Figure 6A.

[0048] 6B , the openings 126 may extend vertically (e.g., in the Z direction) through the inter-deck dielectric structure 124 and the portion of the first preliminary stack structure 104 vertically underlying the inter-deck dielectric structure 124 to the contact structures 116 in the memory array region 112 of the microelectronic device structure 100. Each of the openings 126 may be at least partially (e.g., substantially) horizontally (e.g., in the X direction and the Y direction) aligned with one of the contact structures 116 vertically underlying it. A lower vertical boundary of the openings 126 may be defined by a surface (e.g., a top surface) of the contact structure 116, and a horizontal boundary of the openings 126 may be defined by a surface (e.g., a side surface) of the first preliminary stack structure 104 (e.g., surfaces of the first insulating structure 106 and the second insulating structure 108 of that tier 110) and the inter-deck dielectric structure 124. The openings 126 may then be filled with material to form pillar structures in the memory array region 112 of the microelectronic device structure 100, as described in more detail below.

[0049] Each of the openings 126 may be individually formed to exhibit a desired geometric configuration (e.g., a desired shape and a desired dimension). In some embodiments, each of the openings 126 is individually formed to exhibit a columnar shape (e.g., a cylindrical shape, a rectangular column shape, an oval column shape, a pillar shape) and is sized and positioned to expose a single (e.g., only one) contact structure 116. For example, each of the openings 126 may individually exhibit a cylindrical shape having a substantially circular horizontal cross-sectional area sized and positioned to be at least partially (e.g., substantially) within a horizontal boundary of the contact structure 116 at least partially exposed thereby. In some embodiments, each of the openings 126 is substantially confined within a horizontal boundary of the contact structure 116 that defines a lower vertical boundary of the opening 126. In additional embodiments, one or more of the openings 126 extend horizontally (e.g., in the X-direction and / or Y-direction) beyond a horizontal boundary of the contact structure 116 that defines a portion of the lower vertical boundary of the opening 126.

[0050] A desired amount of openings 126 may be formed in the memory array region 112 of the microelectronic device structure 100. In some embodiments, the amount of openings 126 formed in the memory array region 112 is the same as the amount of contact structures 116 in the memory array region 112. In additional embodiments, the amount of openings 126 formed in the memory array region 112 is different from the amount of contact structures 116 in the memory array region 112. For example, the amount of openings 126 may be less than the amount of contact structures 116 such that less than all of the contact structures 116 are exposed by the openings 126.

[0051] The openings 126 may be formed using conventional processes (eg, conventional photolithographic patterning processes, conventional etching processes) and conventional processing equipment not described in detail herein.

[0052] With continued reference to FIG. 6B , the plug structures 128 may extend vertically (e.g., in the Z direction) into the inter-deck dielectric structure 124 and block the openings 126. The plug structures 128 may be configured and positioned to prevent the openings 126 from filling with material during additional processing operations to form additional preliminary stack structures above the first preliminary stack structure 104, as described in further detail below. Each of the plug structures 128 may be at least partially (e.g., substantially) horizontally (e.g., in the X direction and the Y direction) aligned with one of the openings 126 vertically below it. The lower vertical boundary of the plug structure 128 may be defined by the upper vertical boundary of the remaining unfilled portion of the opening 126 and the horizontally extending surface of the inter-deck dielectric structure 124 vertically above the bottommost vertical boundary of the inter-deck dielectric structure 124. The plug structures 128 may be confined within the vertical boundaries (e.g., upper vertical boundary, lower vertical boundary) of the inter-deck dielectric structure 124. For example, the plug structure 128 may not extend vertically into the portion of the first preliminary stack structure 104 that is vertically underlying the inter-deck dielectric structure 124. The horizontal boundaries of the plug structure 128 may be defined by the vertically extending surfaces (e.g., sides) of the inter-deck dielectric structure 124.

[0053] Each of the plug structures 128 may be individually formed to exhibit a desired geometric configuration (e.g., a desired shape and desired dimensions) that facilitates blocking (e.g., surrounding) at least one of the underlying openings 126. In some embodiments, each of the plug structures 128 is individually formed to exhibit a columnar shape (e.g., a cylindrical shape, a rectangular column shape, an oval column shape, a pillar shape) and is sized and positioned to block a single (e.g., only one) opening 126. For example, each of the plug structures 128 may individually exhibit a cylindrical shape having a substantially circular horizontal cross-sectional area sized and positioned to completely cover the horizontal cross-sectional area of ​​the opening 126 blocked thereby. Each of the plug structures 128 may extend beyond the horizontal boundaries of the opening 126 blocked thereby. In additional embodiments, one or more of the plug structures 128 may exhibit different shapes and / or different sizes, so long as one or more of the plug structures 128 occludes (e.g., within its horizontal boundaries) the opening 126 operably associated therewith.

[0054] The plug structures 128 may each be individually formed of and may include at least one material capable of bridging the upper portion of the opening 126 operatively associated therewith (e.g., blocked by) in the inter-deck dielectric structure 124 and protecting the lower portion of the opening 126 in the first preliminary stack structure 104 from beginning to be filled with material during additional processing operations to form a second preliminary stack structure above the first preliminary stack structure 104. The plug structure 128 may be made of, for example, at least one semiconductor material (e.g., a silicon material such as polysilicon), at least one conductive material (e.g., at least one metal such as one or more of W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, and Al, a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe and Ni-based alloy, a Co and Ni-based alloy, an Fe and Co-based alloy, a Co and Ni and Fe-based alloy, an Al-based alloy, a Cu-based alloy, an Mg-based alloy, a Ti-based alloy, steel, low carbon steel, and stainless steel). The plug structure 128 may include one or more of at least one alloy, such as one or more of stainless steels, at least one conductive metal-containing material, such as one or more of conductive metal nitrides, conductive metal silicides, conductive metal carbides, and conductive metal oxides, at least one conductively doped semiconductor material, such as one or more of conductively doped silicon, conductively doped germanium, and conductively doped silicon germanium, and at least one dielectric material, such as one or more of a dielectric oxide, a dielectric nitride, a dielectric oxynitride, and a dielectric carboxynitride. In some embodiments, the plug structure 128 is formed of or includes polysilicon. In additional embodiments, the plug structure 128 is formed of or includes tungsten (W). In further embodiments, the plug structure 128 is formed of or includes titanium nitride (TiN).

[0055] The plug structure 128 may be formed using conventional processes not described in detail herein (e.g., conventional material removal processes such as conventional etching processes and conventional planarization processes, conventional deposition processes such as conventional non-conformal deposition processes) and conventional processing equipment. As a non-limiting example, following the formation of the opening 126, the inter-deck dielectric structure 124 may be subjected to an etching process to expand (e.g., increase) a horizontal dimension of an upper portion of the opening 126 located vertically within the inter-deck dielectric structure 124, a plug material may be formed non-conformally inside and outside the horizontally expanded upper portion of the opening 126, vertically expanding into and not filling a portion of the opening 126 vertically below the inter-deck dielectric structure 124, bridging and closing the opening 126, and then the portion of the plug material above the upper vertical boundary of the inter-deck dielectric structure 124 may be removed (e.g., via a planarization process such as a CMP process) to form the plug structure 128.

[0056] 7A, a second preliminary stack structure 130 may be formed on or above the first preliminary stack structure 104, the inter-deck dielectric structure 124, and the plug structure 128, and then a pillar structure 138 may be formed to extend vertically through the second preliminary stack structure 130, the plug structure 128, the inter-deck dielectric structure 124, and the first preliminary stack structure 104 in the memory array region 112 of the microelectronic device structure 100. As shown in FIG. 7A, the second preliminary stack structure 130 may extend horizontally through the memory array region 112 and the staircase region 114 of the microelectronic device structure 100, and the pillar structure 138 may be horizontally confined within the memory array region 112 of the microelectronic device structure 100. FIG. 7B is a simplified partial cross-sectional view of the microelectronic device structure 100 at the processing stage depicted in FIG. 7A about the line AA shown in FIG. 7A.

[0057] The second preliminary stack structure 130 may be formed to include a vertically (e.g., Z-direction) alternating sequence of additional first insulating structures 132 and additional second insulating structures 134 arranged in additional tiers 136. Each of the additional tiers 136 of the second preliminary stack structure 130 may include at least one of the additional first insulating structures 132 vertically adjacent to at least one of the additional second insulating structures 134. The second preliminary stack structure 130 may include any desired amount of additional tiers 136. For example, the second preliminary stack structure 130 may include ten (10) or more additional tiers 136, twenty-five (25) or more additional tiers 136, fifty (50) or more additional tiers 136, one hundred (100) or more additional tiers 136, one fifty (150) or more additional tiers 136, or two hundred (200) or more additional tiers of the additional first insulating structures 132 and the additional second insulating structures 134. The amount of the additional tiers 136 of the second preliminary stack structure 130 may be equal to (e.g., the same as) the amount of the tiers 110 of the first preliminary stack structure 104, or the amount of the additional tiers 136 of the second preliminary stack structure 130 may be different from (e.g., less than, more than) the amount of the tiers 110 of the first preliminary stack structure 104.

[0058] The additional first insulating structures 132 of the second preliminary stack structure 130 may have an etch selectivity substantially similar to the etch selectivity of the first insulating structures 106 of the first preliminary stack structure 104. For example, the material composition of the additional first insulating structures 132 may be substantially the same as the material composition of the first insulating structures 106. The etch selectivity of the additional first insulating structures 132 may also be substantially similar to the etch selectivity of the inter-deck dielectric structure 124. For example, the material composition of the additional first insulating structures 132 may be substantially the same as the material composition of the inter-deck dielectric structure 124. In some embodiments, each of the additional first insulating structures 132 of the second preliminary stack structure 130 is made of SiO x It may be formed of or include a dielectric oxide material such as (e.g., SiO2).

[0059] The additional second insulating structure 134 of the second preliminary stack structure 130 may have an etch selectivity substantially similar to the etch selectivity of the second insulating structure 108 of the first preliminary stack structure 104. For example, the material composition of the additional second insulating structure 134 may be substantially the same as the material composition of the second insulating structure 108. The etch selectivity of the additional second insulating structure 134 may be different from the etch selectivity of the first insulating structure 106 of the first preliminary stack structure 104, the inter-deck dielectric structure 124, and the additional first insulating structure 132 of the second preliminary stack structure 130. The additional second insulating structure 134 and the second insulating structure 108 may be selectively etchable relative to the first insulating structure 106, the inter-deck dielectric structure 124, and the additional first insulating structure 132 during a common (e.g., collective, mutual) exposure to a first etchant, and the first insulating structure 106, the inter-deck dielectric structure 124, and the additional first insulating structure 132 may be selectively etchable relative to the additional second insulating structure 134 and the second insulating structure 108 during a common exposure to a second, different etchant. In some embodiments, each of the additional second insulating structures 134 of the second preliminary stack structure 130 is made of SiN y The insulating layer 100 may be formed of or include a dielectric nitride material such as (e.g., Si3N4).

[0060] The second preliminary stack structure 130, including its additional first insulating structure 132 and additional tier 136 of additional second insulating structure 134, may be formed using conventional processes (e.g., conventional material deposition processes) and conventional processing equipment not described in detail herein.

[0061] As shown in FIG. 7B, within the memory array region 112 of the microelectronic device structure 100, the pillar structures 138 may be formed to extend vertically from the top surface of the second preliminary stack structure 130 to the top surface of the contact structure 116. The pillar structures 138 may land at least partially (e.g., substantially) on and physically contact the contact structure 116. The pillar structures 138 may be formed to substantially fill the remainder of the openings 126 (FIGS. 6A and 6B) that extend vertically through the inter-deck dielectric structure 124 and the first preliminary stack structure 104, as well as additional openings formed to extend vertically through the second preliminary stack structure 130 and the plug structures 128 to connect to the openings 126 (FIGS. 6A and 6B). Stated another way, the pillar structures 138 can be formed to substantially fill a relatively large opening each individually formed from a combination of one of the openings 126 (FIGS. 6A and 6B) and an additional opening formed to extend vertically through the second preliminary stack structure 130 and the plug structure 128 to an unfilled portion of one of the openings 126 (FIGS. 6A and 6B).

[0062] The pillar structures 138 may each be individually formed of or include one or more materials that facilitate formation of vertical strings of memory cells in the memory array region 112 of the microelectronic device structure 100 following subsequent processing of the microelectronic device structure 100 (e.g., so-called "replacement gate" or "gate last" processing), as described in more detail below. As a non-limiting example, each of the pillar structures 138 may be individually formed to include a semiconductor structure (e.g., a semiconductor pillar) that is at least partially horizontally surrounded by at least one charge storage structure. The semiconductor structure may include, for example, a polysilicon structure (e.g., a polysilicon pillar) or a silicon germanium structure (e.g., a silicon germanium pillar). The charge storage structure may include, for example, a charge trapping structure (e.g., a charge trapping structure including an oxide-nitride-oxide ("ONO") material).

[0063] The pillar structures 138, including their semiconductor structures and charge storage structures, may be formed using conventional processes (e.g., conventional material deposition processes, conventional material removal processes) and conventional processing equipment not described in detail herein.

[0064] Referring now to FIG. 8A, an upper stadium structure 140 may be formed within a portion of the second preliminary stack structure 130 within the horizontal boundary of the staircase region 114 of the microelectronic device structure 100. The upper stadium structures 140 may each individually include opposing staircase structures 144 each having a step 146 defined by a horizontal edge of an additional tier 136 of the second preliminary stack structure 130. The boundaries (e.g., vertical boundaries, horizontal boundaries) of the trenches 142 (e.g., openings) formed to extend vertically in the second preliminary stack structure 130 are at least partially defined by the upper stadium structures 140. The trenches 142 may each individually be horizontally interposed between opposing staircase structures 144 of one of the upper stadium structures 140. FIG. 8B is a simplified partial cross-sectional view of the microelectronic device structure 100 at the processing stage depicted in FIG. 8A about the line AA shown in FIG. 8A.

[0065] As shown in FIG. 8A . A plurality (e.g., two or more) of the upper stadium structures 140 may be formed to be positioned at substantially the same height (e.g., vertical position) relative to one another within the second preliminary stack structure 130. In some embodiments, the vertical boundary (e.g., top vertical boundary, bottom vertical boundary) of at least one of the upper stadium structures 140 is substantially the same as the vertical boundary (e.g., top vertical boundary, bottom vertical boundary) of at least one other of the upper stadium structures. In additional embodiments, at least one of the upper stadium structures 140 is formed to be positioned at one or more heights (e.g., vertical positions) within the second preliminary stack structure 130 that are different from at least one other of the upper stadium structures 140. For example, at least one of the upper stadium structures 140 may be formed to exhibit at least one different vertical boundary (e.g., different top vertical boundary, different bottom vertical boundary) relative to at least one other of the upper stadium structures 140.

[0066] Any desired quantity and distribution (e.g., spacing and arrangement) of upper stadium structures 140 may be formed within the portion of the second preliminary stack structure 130 within the staircase region 114 of the microelectronic device structure 100. As shown in FIG. 8A, in some embodiments, two (2) of the upper stadium structures 140 are formed within the portion of the second preliminary stack structure 130 within the staircase region 114 of the microelectronic device structure 100. In additional embodiments, two (2) or more of the upper stadium structures 140 (e.g., three (3) or more, four (4) or more, five (5) or more, ten (10) or more, twenty-five (25) or more) are formed within the portion of the second preliminary stack structure 130 within the staircase region 114 of the microelectronic device structure 100. In such an embodiment, the upper stadium structures 140 may be substantially uniformly (e.g., equally, evenly) spaced such that each of the upper stadium structures 140 is separated from each other of the horizontally (e.g., in the X-direction) adjacent stadium structures 12 by substantially the same distance from one another, or the upper stadium structures 140 may be at least partially non-uniformly (e.g., unequal, unequal) spaced such that at least one of the upper stadium structures 140 is separated by different (e.g., unequal) distances from at least two other of the upper stadium structures 140 that are horizontally (e.g., in the X-direction) adjacent to the upper stadium structure 140.

[0067] As shown in FIG. 8A. Each opposing staircase structure 144 of the upper stadium structure 140 may individually include a forward staircase structure 144a and a rear staircase structure 144b that mirrors the forward staircase structure 144a. A phantom line extending from the top of the forward staircase structure 144a to the bottom of the forward staircase structure 144a may have a positive slope, and another phantom line extending from the top of the rear staircase structure 144b to the bottom of the rear staircase structure may have a negative slope. In additional embodiments, one or more (e.g., each) of the upper stadium structures 140 may be modified to include the forward staircase structure 144a but not the rear staircase structure 144b (e.g., the rear staircase structure 144b may not be present). In additional embodiments, one or more (e.g., each) of the upper stadium structures 140 may be modified to include the rear stair structure 144b but not the forward stair structure 144a (e.g., the forward stair structure 144a may not be present).

[0068] Each of the upper stadium structures 140 may be individually formed to include a desired amount of steps 146. Each of the upper stadium structures 140 may include substantially the same amount of steps 146 as each of the upper stadium structures 140, or at least one of the upper stadium structures 140 may include a different amount of steps 146 than at least one of the other upper stadium structures 140. In some embodiments, the steps 146 of each of the upper stadium structures 140 are arranged in order such that steps 146 that are horizontally adjacent to one another (e.g., in the X direction) correspond to additional tiers 136 of the second preliminary stack structure 130 that are vertically adjacent to one another (e.g., in the Z direction). In additional embodiments, one or more steps 146 of the upper stadium structures 140 are arranged in random order such that at least some steps 146 of the upper stadium structures 140 that are horizontally adjacent to one another (e.g., in the X direction) correspond to tiers 136 of the second preliminary stack structure 130 that are not vertically adjacent to one another (e.g., in the Z direction).

[0069] The upper stadium structure 140 may be formed within a portion of the second preliminary stack structure 130 within the staircase region 114 of the microelectronic device structure 100 using conventional processes (e.g., conventional photolithographic patterning processes, conventional material removal processes) and conventional processing equipment not described in detail herein.

[0070] 9A, the microelectronic device structure 100 may be subjected to one or more material removal processes (e.g., one or more chopping processes) to increase the depth (e.g., in the Z direction) of one or more upper stadium structures relative to one or more others of the upper stadium structures 140 and form at least one lower stadium structure 148. As shown in FIG. 9A, the lower stadium structure 148 may be formed to be positioned vertically within the first preliminary stack structure 104, while the upper stadium structure 140 may remain positioned vertically within the second preliminary stack structure 130. FIG. 9B is a simplified partial cross-sectional view of the microelectronic device structure 100 at the processing stage depicted in FIG. 9A about the line AA shown in FIG. 9A.

[0071] The lower stadium structures 148 may be substantially similar to the upper stadium structures 140 used to form the lower stadium structures 148, except that the lower stadium structures 148 are located at a relatively lower vertical position within the microelectronic device structure 100 (e.g., within the first preliminary stack structure 104 rather than the second preliminary stack structure 130). As shown in FIG. 9A, each of the lower stadium structures 148 may include opposing staircase structures 150 (e.g., a forward staircase structure 150a and a rear staircase structure 150b that mirrors the forward staircase structure 150a), each having a step 152 defined by a horizontal edge of a tier 110 of the first preliminary stack structure 110. The boundaries (e.g., vertical boundaries, horizontal boundaries) of one or more additional trenches 149 (e.g., additional openings) formed to extend vertically through the second preliminary stack structure 130 and into the first preliminary stack structure 104 may be defined in part by the lower stadium structures 148. The additional trenches 149 may each be individually horizontally interposed between opposing stair structures 150 of one of the lower stadium structures 148. Aside from being located at the horizontal ends of the tiers 110 of the first preliminary stack structure 104, the opposing stair structures 150 of the lower stadium structure 148 (including the configuration of their steps 152) may be formed substantially similarly to the opposing stair structures 144 of the upper stadium structure 140 utilized to form the lower stadium structure 148 (including the configuration of their steps 146).

[0072] 9A, the tiers 110 of the first preliminary stack structure 104 at the same vertical position (e.g., in the Z direction) as at least a portion of the interdeck dielectric structure 124 may be substantially free of the portions (e.g., steps 152) of the lower stadium structure 148 therein. For example, all of the steps 152 of the lower stadium structure 148 may be positioned vertically below the tiers 110 of the first preliminary stack structure 104 at the same vertical position (e.g., in the Z direction) as at least a portion of the interdeck dielectric structure 124. The tiers 110 of the first preliminary stack structure 104 at the same vertical position (e.g., in the Z direction) as at least a portion of the interdeck dielectric structure 124 may form inactive (e.g., dummy) regions of stack structures subsequently formed from the first preliminary stack structure 104 and the second preliminary stack structure 130, as described in more detail below. In additional embodiments, one or more of the tiers 110 of the first preliminary stack structure 104 that are at the same vertical position (e.g., in the Z direction) as at least a portion of the inter-deck dielectric structure 124 may include a portion of the lower stadium structure 148 therein (e.g., one or more steps 152).

[0073] The lower stadium structure 148 may be formed by disposing a masking material into at least one of the trenches 142 formed in the second preliminary stack structure 130, while leaving at least one of the trenches 142 formed in the second preliminary stack structure 130 free of (e.g., not filled with) the masking material. At least one of the trenches 142 may then be vertically extended into the first preliminary stack structure 104 using at least one material removal process (e.g., at least one chopping process) so as to terminate vertically below a lower vertical boundary of the inter-deck dielectric structure 124. Vertically extending at least one other of the trenches 142 may form an additional trench 149 and the lower stadium structure 148. The masking material may substantially protect portions of the second preliminary stack structure 130 and the first preliminary stack structure that are vertically below and within a horizontal boundary of at least one of the trenches 142 that was filled therewith from being removed during the material removal process.

[0074] 10A, an insulating material 154 may be formed in the trench 142 (FIG. 9A) and the additional trench 149 (FIG. 9A) to form the microelectronic device structure 100 by forming the second insulating structure 108 (FIG. 9A) of the first preliminary stack structure 104 (FIG. 9A) and the additional second insulating structure 134 (FIG. 9A) of the second preliminary stack structure (FIG. 9A) into a conductive structure. 156(FIG. 9A) to form a stack structure 160. The stack structure 160 includes a vertically (e.g., Z-direction) alternating sequence of conductive structures 156 and insulating structures 157 arranged in tiers 158. The insulating structures 157 may correspond to the remainders (e.g., remnants) of the first insulating structures 106 (FIG. 9A) of the first preliminary stack structure 104 (FIG. 9A) and the additional first insulating structures 132 (FIG. 9A) of the second preliminary stack structure 130 (FIG. 9A). Each of the tiers 158 of the stack structure 160 includes at least one of the conductive structures 156 vertically adjacent to at least one of the insulating structures 157. FIG. 10B is a simplified partial cross-sectional view of the microelectronic device structure 100 at the processing stage depicted in FIG. 10A about the line AA shown in FIG. 10A.

[0075] The insulating material 154 is at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x , TiO x , ZrO x , TaO x , and MgO x at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), as well as at least one dielectric carboxy-nitride material (e.g., SiO x CzN y Insulating material 154 may be formed from or may include at least one dielectric material, such as one or more of: xInsulating material 154 may be formed of or include a material such as SiO2. Insulating material 154 may be formed using conventional processes (e.g., conventional material deposition processes) and conventional processing equipment not described in detail herein.

[0076] The conductive structures 156 of the tiers 158 of the stack structure 160 may be formed of or include at least one conductive material, such as one or more of a metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), an alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co and Ni and Fe-based alloy, Al-based alloy, Cu-based alloy, Mg-based alloy, Ti-based alloy, steel, low carbon steel, stainless steel), a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide), a conductively doped semiconductor material (e.g., conductively doped Si, conductively doped Ge, conductively doped SiGe). In some embodiments, the conductive structures 156 are formed of or include tungsten (W).

[0077] 10B , to form the conductive structures 156 (and thus the stack structure 160 including the conductive structures 156 and the tiers of insulating structures 158), slots 168 (e.g., slits, trenches) may be formed to extend vertically through the second preliminary stack structure 130 ( FIGS. 9A and 9B ), the inter-deck dielectric structure 124, and the first preliminary stack structure 130 ( FIGS. 9A and 9B ) to form individual blocks 170. Thereafter, portions of the second insulating structures 108 ( FIGS. 9A and 9B ) of the first preliminary stack structure 104 ( FIGS. 9A and 9B ) and portions of the additional second insulating structures 134 ( FIGS. 9A and 9B ) of the second preliminary stack structure 130 ( FIGS. 9A and 9B ) may be selectively removed (e.g., selectively etched, excavated) through the slots 168 and replaced with conductive material to form the conductive structures 156. Some of the conductive structures 156 may function as access line structures (e.g., word line structures) for the microelectronic device structure 100, and others of the conductive structures 156 may function as select gate structures for the microelectronic device structure 100. Following formation of the conductive structures 156, the slots 168 may be filled with at least one dielectric fill material 172, and optionally, at least one dielectric liner material 174, as depicted in FIG.

[0078] The dielectric fill material 172 formed within and at least partially filling the slot 168 is made of at least one dielectric oxide material (e.g., one or more SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x , TiO x , ZrO x , TaO x , and MgO x ), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y), and at least one dielectric carboxynitride material (e.g., SiO x C z N y ), the dielectric fill material 172 may include a substantially uniform or substantially non-uniform distribution of the at least one dielectric material. In some embodiments, the dielectric fill material 172 exhibits a substantially uniform distribution of the dielectric material. In further embodiments, the dielectric fill material 172 exhibits a substantially non-uniform distribution of the at least one dielectric material. The dielectric fill material 172 may be formed of or include a stack (e.g., a laminate) of at least two different dielectric materials, for example. In some embodiments, the dielectric fill material 172 is formed of or includes SiO2. Also, when formed, a dielectric liner material 174 may be formed to interpose between the dielectric fill material 172 and the conductive structures 156 of the stack structure 160. The dielectric liner material may be, for example, a non-oxide dielectric material (e.g., SiN) used to retard or prevent oxidation of the conductive structures 156 during the formation of the dielectric fill material 172 (e.g., when the dielectric fill material 172 is formed to include a dielectric oxide material such as SiO2). y The dielectric materials may include nitride materials such as SiO 2 and / or SiO 2 .

[0079] 10A , following formation of the stack structure 160, the microelectronic device structure 100 may include a lower deck 162, an upper deck 164 vertically above the lower deck 162, and an inter-deck section 166 vertically interposed between the lower deck 162 and the upper deck 164. The lower deck 162 may include a tier 158 of the stack structure 160 vertically below the inter-deck dielectric structure 124. The upper deck 164 may include a tier 158 of the stack structure 160 vertically above the inter-deck dielectric structure 124. The inter-deck section 166 may include the inter-deck dielectric structure 124 and the tier 158 of the stack structure 160 horizontally adjacent and within the vertical boundary of the inter-deck dielectric structure 124. Within the inter-deck section 166, the tiers 158 of the stack structure 160 may be horizontally confined within the staircase region 114 of the microelectronic device structure 100, and the inter-deck dielectric structure 124 may be horizontally confined within the memory array region 112 of the microelectronic device structure 100. The tiers 158 of the stack structure 160 within the inter-deck section 166 may include so-called "dummy tiers" that do not facilitate electrical communication between two or more components (e.g., memory cells, string drivers) of a microelectronic device that includes the microelectronic device structure 100. Conversely, at least some of the tiers 158 of the stack structure 160 within the lower deck 162 and upper deck 164 of the microelectronic device structure 100 include so-called "active tiers" that facilitate electrical communication between two or more components (e.g., memory cells, string drivers) of a microelectronic device that includes the microelectronic device structure 100.Optionally, one or more of the tiers 158 of the stack structure 160 in the lower deck 162 that are vertically adjacent to (e.g., vertically adjacent to) the inter-deck section 166 may include a dummy tier, so long as one or more of the other tiers 158 of the stack structure 160 in the lower deck include an active tier, and / or one or more of the tiers 158 of the stack structure 160 in the upper deck 164 that are vertically adjacent to (e.g., vertically adjacent to) the inter-deck section 166 may include a dummy tier, so long as one or more of the other tiers 158 of the stack structure 160 in the upper deck 164 include an active tier.

[0080] Thus, according to an embodiment of the disclosure, a microelectronic device includes a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure includes a stack structure, a staircase structure, and a semiconductor pillar structure. The stack structure has tiers each including a conductive structure and an insulating structure vertically adjacent the conductive structure. The stack structure includes a deck including a group of tiers, an additional deck vertically above the deck including an additional group of tiers, and an inter-deck section vertically between the deck and the additional deck. The inter-deck section includes a dielectric structure horizontally confined in the memory array region and another group of tiers within the vertical boundary of the dielectric structure and horizontally confined in the staircase region. The staircase structure is horizontally confined in the staircase region and has a step including edges of the tiers of the stack structure in the deck and the additional deck. The semiconductor pillar structure is horizontally confined in the memory array region and extends vertically through the stack structure.

[0081] Further according to the disclosed embodiment, a method of forming a microelectronic device includes forming a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure is formed to include a first preliminary stack structure including a vertically alternating sequence of first insulating structures and second insulating structures arranged in tiers. The dielectric structure is formed in an upper portion of the first preliminary stack structure and is substantially confined within a horizontal boundary of the memory array region. A second preliminary stack structure is formed above the first preliminary stack structure and the dielectric structure. The second preliminary stack structure includes a vertically alternating sequence of additional first insulating structures and additional second insulating structures arranged in additional tiers. A semiconductor pillar structure is formed to extend vertically through the second preliminary stack structure, the dielectric structure, and a portion of the first preliminary stack structure in the memory array region. A staircase structure is formed in a portion of the second preliminary stack structure and the first preliminary stack structure in the staircase region. Some of the staircase structures have a step that includes a horizontal edge of a tier of the first preliminary stack structure. Others of the staircase structures have an additional step that includes a horizontal edge of an additional tier of the second preliminary stack structure. The second insulating structure and the additional second insulating structure are at least partially replaced with a conductive structure.

[0082] 11A-20B are simplified partial cross-sectional views illustrating an embodiment of another method for forming a microelectronic device (e.g., a memory device such as a 3D NAND flash memory device). 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, and 20B are partial cross-sectional views about line BB depicted in 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A, respectively. Throughout 11A-20B and the associated description below, features (e.g., structures, materials, regions) that are functionally similar to features of the microelectronic device structure 100 previously described with reference to 1A-20B are referred to using similar reference numerals incremented by 100. To avoid repetition, not all features shown in 11A-20B are described in detail herein. Rather, unless otherwise explained below, in Figures 11A-20B, features designated by reference numbers that are incremented by 100 from the reference number of a previously described feature (whether the previously described feature is first described before or after this paragraph) will be understood to be substantially similar to and formed in substantially the same manner as the previously described features.

[0083] 11A, the microelectronic device structure 200 may be formed to include a base structure 202, a contact structure 216 on or above the base structure 202, and a first preliminary stack structure 204 on or above the base structure 202 and the contact structure 216. The first preliminary stack structure 204 includes a vertically (e.g., Z-direction) alternating sequence of first insulating structures 206 and second insulating structures 208 arranged in tiers 210. As shown in FIG. 11A, the microelectronic device structure 200 includes a memory array region 212 and a staircase region 210 horizontally (e.g., X-direction) adjacent a first horizontal boundary of the memory array region 212. The base structure 202 and the first preliminary stack structure 204 extend horizontally through the memory array region 212 and the staircase region 210. The base structure 202, the contact structure 216, the first preliminary stack structure 204 (including its first insulating structure 206 and its tier 210 of second insulating structure 208), the memory array region 212 of the microelectronic device structure 200, and the staircase region 214 of the microelectronic device structure 200 may be formed substantially similarly to the base structure 102, the contact structure 116, the first preliminary stack structure 104 (including its first insulating structure 106 and its tier 110 of second insulating structure 108), the memory array region 112 of the microelectronic device structure 100, and the staircase region 114 of the microelectronic device structure 100, respectively, previously described with reference to FIG. 1A. FIG. 11B is a simplified partial cross-sectional view of the microelectronic device structure 200 at the processing stage depicted in FIG. 11A about the line BB shown in FIG. 11A.

[0084] 12A, a photoresist structure 218 may be formed on or above the first preliminary stack structure 204. The photoresist structure 218 may extend horizontally across the memory array region 212 of the microelectronic device structure 200 and portions within the staircase region 214 of the microelectronic device structure 200. FIG 12B is a simplified partial cross-sectional view of the microelectronic device structure 100 at the processing stage depicted in FIG 12A about line BB shown in FIG 12A.

[0085] 12B, the photoresist structure 218 may be formed to include openings 219 extending vertically therethrough. The openings 219 may each individually extend vertically to and expose a portion of the top surface of the first preliminary stack structure 204, and each individually extend horizontally in a substantially linear manner through the memory array region 212 of the microelectronic device structure 200 and the staircase region 210 of the microelectronic device structure 200. As shown in FIG. 12B, the openings 219 may be positioned horizontally (e.g., in the Y direction) outside of the horizontal boundary (e.g., in the Y direction) of the contact structure 216. The horizontal location of the openings 219 may correspond to the horizontal location of a slot formed through the first preliminary stack structure 204 (and a second preliminary stack structure formed above the first preliminary stack structure 204), as described in more detail below. The openings 219 can each be individually formed to have a width W1 (e.g., a horizontal dimension in the Y direction) that is greater than a predetermined width of a slot that will subsequently be formed in the first preliminary stack structure 204 at the horizontal position of the opening 219.

[0086] The photoresist structure 218 may function as a mask to protect portions of the first preliminary stack structure 204 (e.g., including the first insulating structure 206 and the tier 210 of the second insulating structure 208) that are vertically below it from removal during subsequent processing, as described in more detail below. The photoresist structure 218 may be formed of or include a photoresist material, such as a positive tone photoresist material or a negative tone photoresist material. Suitable photoresist materials (e.g., positive tone photoresist material, negative tone photoresist material) are known in the art and therefore will not be described in detail herein. The photoresist structure 118 may be compatible with, for example, 13.7 nm, 157 nm, 193 nm, 248 nm, or 365 nm wavelength systems, 193 nm wavelength immersion systems, and / or electron beam lithography systems. Additionally, the photoresist structure 218 including the opening 219 extending therethrough may be formed using conventional processes (e.g., conventional deposition processes such as one or more of PVD, CVD, ALD, and spin-coating, conventional photolithography processes, conventional material removal processes), which are known in the art and therefore will not be described in detail herein.

[0087] Referring now to FIG. 13A, the microelectronic device structure 200 may be subjected to a material removal process to selectively remove portions of the relatively vertically tall tier 210 (e.g., top tier) of the first preliminary stack structure 204 that are vertically below and within the horizontal boundary of the opening 219 (FIG. 12B) in the photoresist structure 218 (FIGS. 12A and 12B). FIG. 13B is a simplified partial cross-sectional view of the microelectronic device structure 200 at the processing stage depicted in FIG. 13A about the line BB shown in FIG. 13A. As shown in FIG. 13B, the material removal process may form a partially vertically extending recess 220 (e.g., trench, opening) in the first preliminary stack structure 104. The recess 220 may each individually extend horizontally in a substantially linear manner through the memory array region 212 of the microelectronic device structure 200 and the staircase region 214 of the microelectronic device structure 200. Each of the recesses 220 may have a substantially horizontal position (e.g., in the Y direction) and horizontal dimensions (e.g., width W1 in the Y direction, length in the X direction) individually as an opening 219 (FIG. 12B) in the photoresist structure 218 (FIGS. 12A and 12B) used to form the recesses 220. Following formation of the recesses 220, the remaining (e.g., unremoved) portions, if any, of the photoresist structure 218 (FIGS. 12A and 12B) may be removed.

[0088] The material removal process may be controlled to remove portions of a desired number of tiers 210 of the first preliminary stack structure 204 (e.g., portions not protected by the photoresist material of the photoresist structure 218 (FIGS. 12A and 12B)). As shown in FIG. 13B, in some embodiments, the material removal process removes portions of the two (2) relatively vertically highest tiers (e.g., the two (2) top tiers) of the first preliminary stack structure 204 including portions of its first insulating structure 206 and second insulating structure 208. In additional embodiments, the material removal process may remove portions of a different number of relatively vertically high tiers 210 of the first preliminary stack structure 204. As a non-limiting example, the material removal process may be controlled to remove portions of a single (e.g., only one) relatively vertically highest tier 210 (e.g., the top tier) of the first preliminary stack structure 204. As another non-limiting example, the material removal process may be controlled to remove a portion of more than two (2) relatively vertically highest tiers 210 of the first preliminary stack structure 204, such as a portion of three (3) relatively vertically highest tiers 210 (e.g., the three (3) top tiers) of the first preliminary stack structure 204, a portion of four (4) relatively vertically highest tiers 210 (e.g., the four (4) top tiers) of the first preliminary stack structure 204, or five (5) or more relatively vertically highest tiers 210 (e.g., the five (5) top tiers) of the first preliminary stack structure 204.

[0089] The portion of the relatively vertically taller tier 210 of the first preliminary stack structure 204 that is vertically below and within the horizontal boundary of the opening 219 (FIG. 12B) in the photoresist structure 218 (FIGS. 12A and 12B) may be removed using a conventional material removal process (e.g., a conventional etching process, such as a conventional anisotropic etching process) not described in detail herein. For example, the portion of the top tier 210 of the first preliminary stack structure 204 that is vertically below and within the horizontal boundary of the opening 219 (FIG. 12B) in the photoresist structure 218 (FIGS. 12A and 12B) may be removed using an etching cycle that includes removing the exposed portions of the second insulating structure 208 of the top tier 210 using a first etching action (e.g., a first anisotropic etching action) and then removing the exposed portions of the first insulating structure 206 of the top tier 210 using a second etching action (e.g., a second anisotropic etching action). Portions of one or more additional tiers 210 of the first preliminary stack structure 204 that are vertically below and within the horizontal boundary of the opening 219 (FIG. 12B) in the photoresist structure 218 (FIGS. 12A and 12B) may then be removed using one or more additional etching cycles similar to the etching cycle to form a recess 220 to a desired vertical depth in the first preliminary stack structure 204.

[0090] Referring now to Figure 14A, a dielectric fill material 222 may be formed on or above the exposed surfaces of the first preliminary stack structure 204 inside and outside the recess 220 (Figure 13B). Figure 14B is a simplified partial cross-sectional view of the microelectronic device structure 200 at the processing stage depicted in Figure 14A about line BB shown in Figure 14A. As shown in Figure 14, the dielectric fill material 222 may be formed to cover and substantially extend (e.g., extend substantially continuously) across the surfaces of the first preliminary stack structure 204 in the memory array region 212 of the microelectronic device structure 200 and in the staircase region 210 of the microelectronic device structure 200. 14B, the dielectric fill material 222 may substantially fill the vertically extending recess 220 (FIG. 13B) in the first preliminary stack structure 204 and may cover and extend substantially across the surfaces of the first preliminary stack structure 204 at and outside the boundaries (e.g., horizontal boundaries, vertical boundaries) of the recess 220 (FIG. 13B). The dielectric fill material 222 may be at least partially (e.g., substantially) conformal to the topography defined by the surfaces (e.g., horizontal surfaces, vertical surfaces) on which the dielectric fill material 222 is formed.

[0091] The material composition of the dielectric fill material 122 can be substantially similar to the material composition of the dielectric fill material 122 previously described with reference to Figures 13A and 13B. In some embodiments, the dielectric fill material 222 is a dielectric oxide material (e.g., SiO2, such as x ) and may be formed using conventional processes (e.g., conventional material deposition processes) and conventional processing equipment not described in detail herein.

[0092] 15A and 15B (a simplified partial cross-sectional view of the microelectronic device structure 200 at the processing stage depicted in FIG. 15A about line BB shown in FIG. 15A ), portions of the dielectric fill material 122 (FIGS. 14A and 14B ) outside the boundaries (e.g., horizontal boundaries, vertical boundaries) of the recess 220 (FIG. 13B ) may be removed while retaining additional portions of the dielectric fill material 122 (FIGS. 14A and 14B ) inside the boundaries of the recess 220 (FIG. 13B ) to form an inter-deck dielectric structure 224 (FIG. 15B ). The removal process may expose the memory array region 212 of the microelectronic device structure 200 and a top surface of the first preliminary stack structure 204 in the staircase region 214 of the microelectronic device structure 200. The top boundary (e.g., top surface) of the inter-deck dielectric structure 224 may be substantially coplanar with the top boundary (e.g., top surface) of the first preliminary stack structure 204.

[0093] Portions of dielectric fill material 122 (FIGS. 14A and 14B) outside the boundaries (e.g., horizontal boundaries, vertical boundaries) of recess 220 (FIG. 13B) may be removed to form inter-deck dielectric structure 224 using conventional processes (e.g., conventional planarization processes) not described in detail herein. For example, portions of dielectric fill material 222 (FIGS. 14A and 14B) outside the boundaries of recess 220 (FIG. 13B) may be removed using at least one CMP process to form inter-deck dielectric structure 224.

[0094] 16A, an opening 226 (e.g., a via) may be formed in the memory array region 212 of the microelectronic device structure 200, and a plug structure 228 may be formed at an upper vertical boundary (e.g., in the Z direction) of the opening 226 to substantially fill (e.g., cover) the opening 226. Figure 16B is a simplified partial cross-sectional view of the microelectronic device structure 200 at the processing stage depicted in Figure 16A about line BB shown in Figure 16A.

[0095] 16B, the openings 226 may extend vertically (e.g., in the Z direction) through portions of the first preliminary stack structure 204 in the memory array region 212 of the microelectronic device structure 200. The openings 226 may be positioned horizontally (e.g., in the Y direction) between portions of the inter-deck dielectric structures in the memory array region 212 of the microelectronic device structure 200. The openings 226 may each be at least partially (e.g., substantially) aligned horizontally (e.g., in the X and Y directions) with one of the contact structures 216 below them vertically. A lower vertical boundary of the openings 226 may be defined by a surface (e.g., a top surface) of the contact structure 216, and a horizontal boundary of the openings 226 may be defined by a surface (e.g., a side surface) of the first preliminary stack structure 204 (e.g., surfaces of the first insulating structure 206 and the second insulating structure 208 of that tier 210). The openings 226 may then be filled with material to form pillar structures in the memory array region 212 of the microelectronic device structure 200, as described in more detail below.

[0096] The geometry (e.g., shape, size) and quantity of the openings 226 may be substantially similar to the geometry and quantity of the openings 126 previously described with reference to Figures 6A and 6B, and the openings 226 may be formed using conventional processes (e.g., conventional photolithographic patterning processes, conventional etching processes) and conventional processing equipment not described in detail herein.

[0097] 16B , the plug structures 228 may extend vertically (e.g., in the Z direction) into the first preliminary stack structure 204 and block the openings 226. The plug structures 228 may be configured and positioned to protect the openings 226 from filling with material during additional processing operations to form additional preliminary stack structures above the first preliminary stack structure 204, as described in more detail below. Each of the plug structures 228 may be at least partially (e.g., substantially) aligned horizontally (e.g., in the X and Y directions) with one of the openings 226 vertically below it. The lower vertical boundary of the plug structures 228 may be defined by the upper vertical boundary of the remaining unfilled portion of the opening 126 and a horizontally extending surface of the first preliminary stack structure 204 vertically above the bottom vertical boundary of the inter-deck dielectric structure 224. 16B, in some embodiments, the lower vertical boundary of the plug structure 228 is substantially coplanar with the lower vertical boundary of the vertically topmost tier 210 of the first preliminary stack structure 204. In some embodiments, the lower vertical boundary of the plug structure 228 is vertically offset (e.g., vertically upward, vertically downward) from the lower vertical boundary of the vertically topmost tier 210 of the first preliminary stack structure 204. The horizontal boundary of the plug structure 228 may be defined by a vertically extending surface (e.g., side surface) of the first preliminary stack structure 204. The plug structure 228 may be positioned horizontally (e.g., in the Y direction) between portions of the inter-deck dielectric structure 224 in the memory array region 212 of the microelectronic device structure 200.

[0098] The geometry (e.g., shape, dimensions) and material composition of the plug structure 228 may be substantially similar to the geometry and material composition of the plug structure 128 described previously with reference to Figures 6A and 6B, respectively, and the plug structure 228 may be formed using conventional processes not described in detail herein (e.g., conventional material removal processes, such as conventional etching processes and conventional planarization processes, conventional deposition processes, such as conventional non-conformal deposition processes) and conventional processing equipment.

[0099] 17A, a second preliminary stack structure 230 may be formed on or above the first preliminary stack structure 204, the inter-deck dielectric structure 224, and the plug structure 228, and then a pillar structure 238 may be formed to extend vertically through the second preliminary stack structure 230, the plug structure 228, and the first preliminary stack structure 204 in the memory array region 212 of the microelectronic device structure 200. As shown in FIG. 17A, the second preliminary stack structure 230 may extend horizontally through the memory array region 212 and the staircase region 210 of the microelectronic device structure 200, and the pillar structure 238 may be horizontally confined within the memory array region 212 of the microelectronic device structure 200. FIG. 17B is a simplified partial cross-sectional view of the microelectronic device structure 100 at the processing stage depicted in FIG. 17A about line BB shown in FIG. 17A.

[0100] The second preliminary stack structure 230 may be formed to include a vertically (e.g., Z-direction) alternating sequence of additional first insulating structures 232 and additional second insulating structures 234 arranged in additional tiers 236. The second preliminary stack structure 230 (including additional tiers 236 of additional first insulating structures 232 and additional second insulating structures 234) may be substantially similar to the second preliminary stack structure 130 (including additional tiers 136 of additional first insulating structures 132 and additional second insulating structures 134) previously described with reference to Figures 7A and 7B. The second preliminary stack structure 230 may be formed using conventional processes (e.g., conventional material deposition processes) and conventional processing equipment not described in detail herein.

[0101] Within the memory array region 212 of the microelectronic device structure 200, pillar structures 238 may be formed extending vertically from a top surface of the second preliminary stack structure 230 to a top surface of the contact structure 216. The pillar structures 238 may be substantially similar to the pillar structures 138 previously described with reference to Figures 7A and 7B. Also, the pillar structures 238 may be formed using conventional processes (e.g., conventional material deposition processes, conventional material removal processes) and conventional processing equipment not described in detail herein.

[0102] 18A, an upper stadium structure 240 may be formed within a portion of the second preliminary stack structure 230 within the horizontal boundary of the staircase region 210 of the microelectronic device structure 200. The upper stadium structure 240 may each individually include opposing staircase structures 244 (e.g., a front staircase structure 244a and a rear staircase structure 244b that mirrors the front staircase structure 244a), each having a step 246 defined by a horizontal edge of an additional tier 236 of the second preliminary stack structure 230. The boundaries (e.g., vertical boundaries, horizontal boundaries) of trenches 242 (e.g., openings) formed to extend vertically in the second preliminary stack structure 230 may be at least partially defined by the upper stadium structure 240. The trenches 242 may each individually be horizontally interposed between opposing staircase structures 244 of one of the upper stadium structures 240. FIG. 18B is a simplified partial cross-sectional view of the microelectronic device structure 200 at the processing stage depicted in FIG. 18A about line BB shown in FIG. 18A.

[0103] The upper stadium structure 240 (including their opposing staircase structures 244 and steps 246) and trench 242 may be substantially similar to the upper stadium structure 140 (including their opposing staircase structures 144 and steps 146) and trench 142 previously described with reference to Figures 8A and 8B. The upper stadium structure 240 may be formed using conventional processes (e.g., conventional photolithographic patterning processes, conventional material removal processes) and conventional processing equipment not described in detail herein.

[0104] 19A, the microelectronic device structure 200 may be subjected to one or more material removal processes (e.g., one or more chopping processes) to increase the depth (e.g., in the Z direction) of one or more upper stadium structures relative to one or more others of the upper stadium structures 240 and form at least one lower stadium structure 248. As shown in FIG. 19A, the lower stadium structure 248 may be formed to be positioned vertically within the first preliminary stack structure 204, while the upper stadium structure 240 may remain positioned vertically within the second preliminary stack structure 230. FIG. 19B is a simplified partial cross-sectional view of the microelectronic device structure 200 at the processing stage depicted in FIG. 19A about line BB shown in FIG. 19A.

[0105] 19A, each of the lower stadium structures 248 may include opposing staircase structures 250 (e.g., a forward staircase structure 250a and a rear staircase structure 250b mirroring the forward staircase structure 250a) each having a step 252 defined by the horizontal edge of each of the tiers 210 of the first preliminary stack structure 204. The boundaries (e.g., vertical boundaries, horizontal boundaries) of one or more additional trenches 249 (e.g., additional openings) formed to extend vertically through the second preliminary stack structure 230 into the first preliminary stack structure 204 may be partially defined by the lower stadium structures 248. The additional trenches 249 may each be individually horizontally interposed between opposing staircase structures 250 of one of the lower stadium structures 248. Aside from being located at the horizontal end of the tier 210 of the first preliminary stack structure 204, the opposing staircase structures 250 of the lower stadium structure 248 (including the configuration of their steps 252) may be formed substantially similarly to the opposing staircase structures 244 of the upper stadium structure 240 utilized to form the lower stadium structure 242 (including the configuration of their steps 246).

[0106] As shown in FIG. 19A, an inter-deck dielectric structure 224The tiers 210 of the first preliminary stack structure 204 at the same vertical position (e.g., in the Z direction) as the portions of the lower stadium structure 248 may be substantially free of the portions (e.g., steps 152) of the lower stadium structure 248 therein. For example, all of the steps 252 of the lower stadium structure 248 may be positioned vertically below the tiers 210 of the first preliminary stack structure 204 at the same vertical position (e.g., in the Z direction) as the portions of the inter-deck dielectric structure 224. The tiers 210 of the first preliminary stack structure 204 at the same vertical position (e.g., in the Z direction) as the portions of the inter-deck dielectric structure 224 may form inactive (e.g., dummy) regions of the stack structures subsequently formed from the first preliminary stack structure 204 and the second preliminary stack structure 230, as described in more detail below. In additional embodiments, one or more of the tiers 210 of the first preliminary stack structure 204 that are at the same vertical position (e.g., in the Z direction) as a portion of the inter-deck dielectric structure 224 may include a portion of the lower stadium structure 248 therein (e.g., one or more steps 252).

[0107] The lower stadium structure 248 (including its opposing staircase structure 250 and step 252) and the additional trench 249 may be formed using a process substantially similar to that previously described with reference to Figures 9A and 9B for the formation of the lower stadium structure 148 (including its opposing staircase structure 150 and step 152) and the additional trench 149.

[0108] 20A, an insulating material 254 may be formed in the trench 242 (FIG. 19A) and the additional trench 249 (FIG. 19A) to form the microelectronic device structure 200 with some (e.g., less than all) of the second insulating structures 208 (FIG. 19A) of the first preliminary stack structure 204 (FIG. 19A) and the additional second insulating structures 234 (FIG. 19A) of the second preliminary stack structure 230 (FIG. 19A) as conductive structures. 25620A and 20B , and may be subjected to so-called "replacement gate" or "gate last" processing operations to at least partially replace the insulating material 254 and conductive structures 256 to form stack structure 260. Insulating material 254 and conductive structures 256 may be substantially similar to insulating material 154 and conductive structures 156, respectively, previously described with reference to Figures 10A and 10B. Figure 20B is a simplified partial cross-sectional view of microelectronic device structure 200 at the processing stage depicted in Figure 20A about line BB shown in Figure 20A.

[0109] 20B, stack structure 260 includes a vertically (e.g., in the Z direction) alternating sequence of conductive structures 256 and insulating structures 257 arranged in tiers 258 positioned vertically above and vertically below inter-deck dielectric structure 224, and also includes tiers 210 of first insulating structures 206 and second insulating structures 208 at vertical locations within the vertical boundaries of inter-deck dielectric structure 224. Insulating structures 257 may correspond to remnants (e.g., remainders) of first insulating structures 206 ( FIG. 9A ) of first preliminary stack structure 204 ( FIG. 9A ) and additional first insulating structures 232 ( FIG. 9A ) of second preliminary stack structure 230 ( FIG. 9A ) at vertical locations outside (e.g., beyond) the vertical boundaries of inter-deck dielectric structure 224. Each of the tiers 258 of the stack structure 260 includes at least one of the conductive structures 256 vertically adjacent to at least one of the insulating structures 257 .

[0110] 20B, to form the stack structure 260, slots 268 (e.g., slits, trenches) may be formed to extend vertically through the second preliminary stack structure 230 (FIGS. 19A and 19B), the inter-deck dielectric structure 224, and the first preliminary stack structure 204 (FIGS. 9A and 9B) to form individual blocks 270. Each of the slots 268 may be formed to have a width W2 (e.g., dimension in the Y direction) that is less than a width W1 of the inter-deck dielectric structure 224 through which the slot 268 extends vertically. Thereafter, portions of the additional second insulating structures 234 (FIGS. 19A and 19B) of the second preliminary stack structure 230 (FIGS. 9A and 9B) outside the vertical boundaries of the inter-deck dielectric structure 224 and portions of the second insulating structures 208 (FIGS. 9A and 9B) of the first preliminary stack structure 204 (FIGS. 19A and 19B) may be selectively removed (e.g., selectively etched, excavated) through the slots 268 and replaced with a conductive material to form the conductive structures 256. The remainder of the inter-deck dielectric structure 224 may substantially prevent portions of the second insulating structures 208 within the vertical boundaries of the inter-deck dielectric structure 224 from being removed through the slots 268 and replaced with a conductive material. Some of the conductive structures 256 may function as access line structures (e.g., word line structures) for the microelectronic device structure 200, and others of the conductive structures 256 may function as select gate structures for the microelectronic device structure 200. Following formation of the conductive structures 256, the slots 268 may be filled with at least one dielectric fill material 272, and optionally at least one dielectric liner material 274, as depicted in Figure 20B. The dielectric fill material 272 and the dielectric liner material 274 (if formed) may be substantially similar individually to the dielectric fill material 172 and the dielectric liner material 174 previously described with reference to Figure 10B.

[0111] 20A , following formation of the stack structure 260, the microelectronic device structure 200 may include a lower deck 262, an upper deck 264 vertically above the lower deck 262, and an inter-deck section 266 vertically interposed between the lower deck 262 and the upper deck. The lower deck 262 may include a tier 258 of the stack structure 260 (including their conductive structures 256 and insulating structures 257) vertically below the inter-deck dielectric structure 224. The upper deck 264 may include a tier 258 of the stack structure 260 (including their conductive structures 256 and insulating structures 257) vertically above the inter-deck dielectric structure 224. The inter-deck section 266 may include the inter-deck dielectric structure 224 and the tier 210 of the stack structure 260 (including their first insulating structures 206 and second insulating structures 208) horizontally adjacent to and within the vertical boundary of the inter-deck dielectric structure 224. The tiers 210 of the stack structure 260 in the inter-deck section 266 may include so-called "dummy tiers" that do not facilitate electrical communication between two or more components (e.g., memory cells, string drivers) of a microelectronic device that includes the microelectronic device structure 200. Conversely, at least some of the tiers 258 of the stack structure 260 in the lower deck 262 and upper deck 264 of the microelectronic device structure 200 include so-called "active tiers" that facilitate electrical communication between two or more components (e.g., memory cells, string drivers) of a microelectronic device that includes the microelectronic device structure 200. Optionally, one or more of the tiers 258 of the stack structure 260 in the lower deck 262 that are vertically adjacent (e.g., vertically adjacent) to the inter-deck section 266 may include a dummy tier, so long as one or more of the other of the tiers 258 of the stack structure 260 in the lower deck 262 includes an active tier, and / or one or more of the tiers 258 of the stack structure 260 in the upper deck 264 that are vertically adjacent (e.g., vertically adjacent) to the inter-deck section 266 may include a dummy tier, so long as one or more of the other of the tiers 258 of the stack structure 260 in the upper deck 264 includes an active tier.

[0112] Thus, according to the disclosed embodiments, a microelectronic device includes a microelectronic device structure including a stack structure, a staircase structure, and a semiconductor pillar structure. The stack structure has tiers each including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The stack structure includes a lower deck including some of the tiers, an upper deck above the deck and including others of the tiers, and an inter-deck section between the lower deck and the upper deck. The inter-deck section includes an inter-deck dielectric structure and an additional tier horizontally between the inter-deck dielectric structures. The additional tiers each include an additional insulating structure and a further insulating structure vertically adjacent to the additional insulating structure. The staircase structure has steps including edges of the tiers of the stack structure in the lower deck and the upper deck. The semiconductor pillar structures extend vertically through the stack structure.

[0113] Further according to the disclosed embodiment, a method of forming a microelectronic device includes forming a microelectronic device structure including a first preliminary stack structure including a vertically alternating sequence of first insulating structures and second insulating structures arranged in tiers. Dielectric structures are formed to extend vertically in the first preliminary stack structure. The dielectric structures are horizontally spaced apart from one another in a first direction and extend horizontally substantially linearly in a second direction orthogonal to the first direction. A second preliminary stack structure is formed above the first preliminary stack structure and the dielectric structures. The second preliminary stack structure includes a vertically alternating sequence of additional first insulating structures and additional second insulating structures arranged in additional tiers. A semiconductor pillar structure is formed to extend vertically through a portion of the second preliminary stack structure and the first preliminary stack structure positioned horizontally between the dielectric structures. Staircase structures are formed in the second preliminary stack structure and the first preliminary stack structure. Some of the staircase structures having steps include edges of the tiers of the first preliminary stack structure. Others of the staircase structures have additional steps that include edges of additional tiers of the second preliminary stack structure. Additional second insulating structures of the second preliminary stack structure and second insulating structures of the first preliminary stack structure positioned outside the vertical boundaries of the dielectric structures are replaced with conductive structures.

[0114] FIG. 21 illustrates a partial cutaway perspective view of a portion of a microelectronic device 300 (e.g., a memory device such as a 3D NAND flash memory device) including a microelectronic device structure 302. The microelectronic device structure 302 may be substantially similar to the microelectronic device structure 100 at the stage of processing previously described with reference to FIGS. 10A and 10B, or the microelectronic device structure 302 may be substantially similar to the microelectronic device structure 200 at the stage of processing previously described with reference to FIGS. 20A and 20B. In some embodiments, the microelectronic device structure 302 is formed through a process previously described with reference to FIGS. 1A-10B. In additional embodiments, the microelectronic device structure 302 is formed through a process previously described with reference to FIGS. 11A-20B. 21, the microelectronic device structure 302 may include a stack structure 304 including a vertically (e.g., in the Z direction) alternating sequence of conductive structures 306 and insulating structures 308 arranged in tiers 310, and a staircase structure 312 having a step 314 defined by an edge (e.g., a horizontal edge in the X direction) of the tier 310. In some embodiments, the stack structure 304, conductive structures 306, insulating structures 308, tiers 310, staircase structure 312, and step 314 are individually substantially similar to the stack structure 160, conductive structures 156, insulating structures 157, tiers 158, staircase structures 144 and 150, and steps 146 and 152 previously described with reference to FIGS. 10A and 10B. In such embodiments, the microelectronic device structure 302 further includes an inter-deck dielectric structure substantially similar to the inter-deck dielectric structure 124 previously described with reference to the microelectronic device structure 100 at the process stage depicted in FIGS. 10A and 10B. In an additional embodiment, stack structure 304, conductive structure 306, insulating structure 308, tier 310, staircase structure 312, and step 314 are substantially similar to stack structure 260, conductive structure 256, insulating structure 257, tier 258, staircase structures 244 and 250, and steps 246 and 252 previously described with reference to Figures 20A and 20B.In such an embodiment, the microelectronic device structure 302 further includes an inter-deck dielectric structure and additional tiers substantially similar to the inter-deck dielectric structure 224 and tier 210 (including their first insulating structure 206 and second insulating structure 208) previously described with reference to the microelectronic device structure 200 at the process stage depicted in Figures 20A and 20B. The microelectronic device 300 also includes additional features (e.g., structures, devices) operatively associated with the microelectronic device structure 302, as described in more detail below.

[0115] The microelectronic device 300 may further include a vertical string 319 of memory cells 320 coupled together in series, a data line 322 (e.g., a bit line), a source structure 324, an access line 326, a first select gate 328 (e.g., a top select gate, a drain select gate (SGD)), a select line 330, a second select gate 332 (e.g., a bottom select gate, a source select gate (SGS)), a contact structure 318, and an additional contact structure 334. The vertical string 319 of memory cells 320 extends vertically and orthogonally to the conductive lines and tiers (e.g., the data line 322, the source structure 324, the tier 310 of the stack structure 304, the access line 326, the first select gate 328, the select line 330, the second select gate 332). The contact structures 318 and additional contact structures 334 may electrically couple the components to each other (e.g., the select line 330 to the first select gate 328 and the access line 326 to the tier 310 of the stack structure 304 of the microelectronic device structure 302) as shown.

[0116] 21, the microelectronic device 300 may also include a control unit 336 (e.g., a control device) positioned vertically below the vertical strings 319 of memory cells 320, which may include one or more of string driver circuits, pass gates, circuits for selecting gates, circuits for selecting conductive lines (e.g., access lines 326, select lines 330, data lines 322, additional access lines, additional select lines, additional data lines), circuits for amplifying signals, and circuits for sensing signals. In some embodiments, the control unit 336 is positioned at least partially (e.g., substantially) within the horizontal boundaries (e.g., in the X- and Y-directions) of the horizontal area occupied by the vertical strings 319 of memory cells 320. The control unit 336 may be electrically coupled to, for example, the data lines 322, the source structures 324, the access lines 326, and the select lines 330. In some embodiments, the control unit 336 includes CMOS (complementary metal oxide semiconductor) circuitry. In such an embodiment, the control unit 336 may be characterized as having a "CMOS under array" ("CuA") configuration.

[0117] Microelectronic device structures (e.g., microelectronic device structure 100 previously described with reference to FIGS. 10A and 10B, microelectronic device structure 200 previously described with reference to FIGS. 20A and 20B) and microelectronic devices (e.g., microelectronic device 300 previously described with reference to FIG. 21) according to disclosed embodiments may be used in disclosed electronic system embodiments. For example, FIG. 22 is a block diagram of an exemplary electronic system 400 according to disclosed embodiments. Electronic system 400 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a mobile phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet such as an iPad® or SURFACE® tablet, an e-book, a navigation device, and the like. Electronic system 400 includes at least one memory device 402. Memory device 402 may include, for example, one or more embodiments of the microelectronic device structures and microelectronic devices previously described herein. The electronic system 400 may further include at least one electronic signal processor device 404 (often referred to as a "microprocessor"). The electronic signal processor device 404 may optionally include one or more embodiments of the microelectronic device structures and microelectronic devices previously described herein. Although the memory device 402 and the electronic signal processor device 404 are depicted in FIG. 22 as two (2) separate devices, in additional embodiments, a single (e.g., only one) memory / processor device having the functionality of the memory device 402 and the electronic signal processor device 404 is included in the electronic system 400. In such embodiments, the memory / processor device may include one or more of the microelectronic device structures and microelectronic devices previously described herein.The electronic system 400 may further include one or more input devices 406 for inputting information into the electronic system 400 by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, buttons, or a control panel. The electronic system 400 may further include one or more output devices 408 for outputting information (e.g., visual or audio output) to a user, such as, for example, one or more of a monitor, a display, a printer, an audio output jack, and a speaker. In some embodiments, the input devices 406 and the output devices 408 may include a single touch screen device that may be used both to input information into the electronic system 400 and to output visual information to a user. The input devices 406 and the output devices 408 may be in electrical communication with one or more of the memory device 402 and the electronic signal processor device 404.

[0118] Thus, according to an embodiment of the disclosure, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device and including at least one microelectronic device structure having a memory array region and a staircase region. The at least one microelectronic device structure includes a stack structure, a staircase structure, and a semiconductor pillar structure. The stack structure has tiers each including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The stack structure includes a deck including some of the tiers, an additional deck vertically above the deck and including others of the tiers, and an inter-deck section vertically between the deck and the additional deck. The inter-deck section includes at least one dielectric structure that is within a horizontal boundary of the memory array region and does not substantially exist or extend completely across a horizontal region of the staircase region. The staircase structure is within the staircase region and has a step that includes an edge of a tier of the stack structure in the deck and the additional deck. The semiconductor pillar structure is within the memory array region and extends vertically through the stack structure.

[0119] The disclosed methods, structures (e.g., microelectronic device structures 100, 200, 302), devices (e.g., microelectronic device 300), and systems (e.g., electronic system 400) advantageously facilitate one or more of improved performance, reliability, and durability, lower cost, improved component miniaturization, improved pattern quality, and increased packaging density compared to conventional structures, devices, and systems. The disclosed methods and structures may alleviate problems associated with forming and processing conventional microelectronic devices, including stack structures having stair structures on their edges. For example, the disclosed methods and structures may enable the efficient transfer of a staircase structure configuration formed in one or more relatively vertically taller preliminary stack structures (e.g., the second preliminary stack structure 130, 230) to one or more relatively vertically lower preliminary stack structures (e.g., the first preliminary stack structure 104, 204) using a simple chopping process, thereby avoiding complex, inefficient and costly processes (e.g., separate staircase formation processes each involving a series of masking and etching operations) traditionally associated with forming staircase structures in different decks of conventional microelectronic device structures.

[0120] Additional non-limiting exemplary embodiments of the disclosure are described below.

[0121] Embodiment 1: A microelectronic device structure having a memory array region and a staircase region, the microelectronic device structure comprising a stack structure having tiers each including a conductive structure and an insulating structure vertically adjacent the conductive structure, the stack structure including a deck including a group of tiers, an additional deck vertically above the deck and including an additional group of tiers, and an inter-deck section vertically between the deck and the additional deck, the inter-deck section including a dielectric structure horizontally confined in the memory array region and another group of tiers within a vertical boundary of the dielectric structure and horizontally confined in the staircase region; a staircase structure horizontally confined in the staircase region having a step including edges of the tiers of the stack structure in the deck and the additional deck; and a semiconductor pillar structure horizontally confined in the memory array region and extending vertically through the stack structure.

[0122] Embodiment 2: The microelectronic device of embodiment 1, further comprising a plug structure within the dielectric structure and horizontally surrounding the semiconductor pillar structure.

[0123] Embodiment 3: A microelectronic device described in any one of embodiments 1 and 2, wherein another group of tiers in the inter-deck section of the stack structure includes at least two of the tiers of the stack structure.

[0124] Embodiment 4: A microelectronic device according to any one of embodiments 1 to 3, wherein the dielectric structure of the stack structure and each insulating structure of the tiers comprises at least one dielectric oxide material.

[0125] Embodiment 5: A microelectronic device according to any one of embodiments 1 to 4, wherein the inter-deck section of the stack structure does not include any part of the staircase structure within its vertical boundaries.

[0126] Embodiment 6: A microelectronic device described in any one of embodiments 1 to 5, wherein the stair structure includes a first stadium structure located within a deck of the stack structure and including a first stair structure having a positive slope and a second stair structure facing the first stair structure and having a negative slope, and a second stadium structure located within an additional deck of the stack structure and including a third stair structure having a positive slope and a fourth stair structure facing the third stair structure and having a negative slope.

[0127] Embodiment 7: Forming a microelectronic device structure having a memory array region and a staircase region, the microelectronic device structure being formed to include a first preliminary stack structure including a vertically alternating sequence of first insulating structures and second insulating structures arranged in tiers; forming a dielectric structure within an upper portion of the first preliminary stack structure and substantially confined within a horizontal boundary of the memory array region; and forming a second preliminary stack structure above the first preliminary stack structure and the dielectric structure, the second preliminary stack structure including a vertically alternating sequence of additional first insulating structures and additional second insulating structures arranged in additional tiers. forming a semiconductor pillar structure extending vertically through portions of the second preliminary stack structure, the dielectric structure, and the first preliminary stack structure in the memory array region; forming staircase structures in the second preliminary stack structure and portions of the first preliminary stack structure in the staircase region, some of the staircase structures having steps that include horizontal ends of a tier of the first preliminary stack structure and others of the staircase structures having additional steps that include horizontal ends of additional tiers of additional second preliminary stack structures; and at least partially replacing the second insulating structure and the additional second insulating structure with a conductive structure.

[0128] Embodiment 8: The method of embodiment 7, wherein forming a dielectric structure within an upper portion of the first preliminary stack structure includes forming a photoresist structure above a portion of the first preliminary stack structure within the staircase region, selectively removing an upper portion of the first preliminary stack structure using the photoresist structure as a mask to form a recess within the first preliminary stack structure and substantially confined within a horizontal boundary of the memory array region, forming a dielectric fill material above an exposed surface of the first preliminary stack structure inside and outside the recess, and removing portions of the dielectric fill material outside the horizontal and vertical boundaries of the recess to form a dielectric structure.

[0129] Embodiment 9: The method of any one of embodiments 7 and 8, further comprising selecting the first insulating structure, the dielectric structure, and the additional first insulating structure of the second preliminary stack structure to each comprise a dielectric oxide material.

[0130] Embodiment 10: The method of any one of embodiments 7 to 9, wherein forming the semiconductor pillar structure includes forming an opening extending vertically through the dielectric structure and a lower portion of the first preliminary stack structure underlying the dielectric structure, covering the opening with a plug structure extending vertically partially into the opening, forming a second preliminary stack structure above the first preliminary stack structure, the dielectric structure, and the plug structure, forming an additional opening extending vertically through the second preliminary stack structure and the plug structure to the remainder of the opening to form a relatively larger opening, and filling the relatively larger opening with a semiconductor material.

[0131] Embodiment 11: A method as described in any one of embodiments 7 to 10, wherein forming a staircase structure within the second preliminary stack structure and a portion of the first preliminary stack structure within the staircase area includes forming a stadium structure within the second preliminary stack structure, the stadium structure including a first staircase structure having a positive slope and a second staircase structure facing the first staircase structure and having a negative slope, and forming an additional stadium structure within the first preliminary stack structure, the additional stadium structure including a third staircase structure having a positive slope and a fourth staircase structure facing the third staircase structure and having a negative slope.

[0132] Embodiment 12: The method of embodiment 11, wherein forming an additional stadium structure in the first preliminary stack structure includes subjecting the second preliminary stack structure to a chopping process to vertically expand an opening defined by another stadium structure formed in the second preliminary stack structure into the first preliminary stack structure and form the additional stadium structure.

[0133] Embodiment 13: The method according to any one of embodiments 7 to 12, wherein at least partially replacing the second insulating structure and the additional second insulating structure with a conductive structure includes at least partially replacing the second insulating structure and the additional second insulating structure with tungsten.

[0134] Embodiment 14: A microelectronic device comprising a stack structure having tiers each including a conductive structure and an insulating structure vertically adjacent the conductive structure, the stack structure including a lower deck including some of the tiers, an upper deck above the deck and including others of the tiers, and an inter-deck section between the lower deck and the upper deck, the inter-deck section including an inter-deck dielectric structure and additional tiers vertically between the inter-deck dielectric structures, the additional tiers each including an additional insulating structure and a further insulating structure vertically adjacent the additional insulating structure; a stair structure having steps including edges of the tiers of the stack structure in the lower deck and the upper deck; and a semiconductor pillar structure extending vertically through the stack structure.

[0135] Embodiment 15: A microelectronic device as described in embodiment 14, wherein the semiconductor pillar structure is positioned horizontally between inter-deck dielectric structures.

[0136] Embodiment 16: A microelectronic device described in any one of embodiments 14 and 15, wherein the semiconductor pillar structure extends vertically through a first group of tiers in the upper deck of the stack structure, additional tiers of the stack structure in the inter-deck section of the stack structure, and a second group of tiers in the lower deck of the stack structure.

[0137] Embodiment 17: A microelectronic device described in any one of embodiments 14 to 16, further comprising filled slots extending vertically through the tiers of the stack structure and the inter-deck dielectric structure, each filled with at least one dielectric material.

[0138] Embodiment 18: A microelectronic device described in any one of embodiments 14 to 17, wherein the inter-deck dielectric structure, the insulating structures of each of the tiers in the lower and upper decks of the stack structure, and the additional insulating structures of each of the additional tiers in the inter-deck section of the stack structure comprise at least one dielectric oxide material.

[0139] Embodiment 19: A microelectronic device described in any one of embodiments 14 to 18, wherein each further insulating structure of the additional tier in the inter-deck section of the stack structure comprises at least one dielectric nitride material.

[0140] Embodiment 20: A microelectronic device described in any one of embodiments 14 to 19, wherein the stair structure includes a stadium structure located in the upper deck of the stack structure and including a first stair structure having a positive slope and a second stair structure mirroring the first stair structure and having a negative slope, and an additional stadium structure located in the lower deck of the stack structure and including a third stair structure having a positive slope and a fourth stair structure mirroring the third stair structure and having a negative slope.

[0141] Embodiment 21: Forming a microelectronic device structure including a first preliminary stack structure including a vertically alternating sequence of first insulating structures and second insulating structures arranged in tiers; forming vertically extending dielectric structures in the first preliminary stack structure, the dielectric structures being horizontally spaced apart from one another in a first direction and extending horizontally substantially linearly in a second direction orthogonal to the first direction; forming a second preliminary stack structure above the first preliminary stack structure and the dielectric structures, the second preliminary stack structure including a vertically alternating sequence of additional first insulating structures and additional second insulating structures arranged in additional tiers; A method of forming a microelectronic device, comprising: forming a semiconductor pillar structure extending vertically through the tack structure and a portion of the first preliminary stack structure positioned horizontally therebetween of the dielectric structure; forming staircase structures in the second preliminary stack structure and the first preliminary stack structure, some of the staircase structures having steps that include edges of tiers of the first preliminary stack structure and others of the staircase structures having additional steps that include edges of additional tiers of the second stack structure; and replacing additional second insulating structures of the second preliminary stack structure and second insulating structures of the first preliminary stack structure positioned outside the vertical boundaries of the dielectric structure with conductive structures.

[0142] Embodiment 22: The method of embodiment 21, wherein forming a vertically extending dielectric structure in the first preliminary stack structure includes forming a photoresist structure above the first preliminary stack structure, the photoresist structure comprising a photoresist material having an opening extending vertically therethrough, selectively removing an upper portion of the first preliminary stack structure exposed by the opening in the photoresist material of the photoresist structure and within a horizontal boundary of the opening to form a recess in the first preliminary stack structure, forming a dielectric fill material above an exposed surface of the first preliminary stack structure inside and outside the recess, and removing a portion of the dielectric fill material outside the boundary of the recess to form a dielectric structure.

[0143] Embodiment 23: A method as described in any one of embodiments 21 and 22, further comprising selecting a first insulating structure of the first preliminary stack structure, a dielectric structure, and an additional first insulating structure of the second preliminary stack structure to each include a dielectric oxide material, and selecting a second insulating structure of the first preliminary stack structure and an additional second insulating structure of the second preliminary stack structure to each include a dielectric nitride material.

[0144] Embodiment 24: A method according to any one of embodiments 21 to 23, wherein forming the semiconductor pillar structure includes forming an opening extending vertically through a portion of a tier of a first preliminary stack structure positioned horizontally between the dielectric structures, covering the opening with a plug structure extending vertically partially into the opening, forming a second preliminary stack structure above the first preliminary stack structure, the dielectric structure, and the plug structure, forming an additional opening extending vertically through the second preliminary stack structure and the plug structure to the remainder of the opening to form a relatively larger opening, and filling the relatively larger opening with a semiconductor material.

[0145] Embodiment 25: A method according to any one of embodiments 21 to 24, wherein forming a staircase structure within the second preliminary stack structure and the first preliminary stack structure includes forming a first stadium structure within the second preliminary stack structure, the first stadium structure including a first staircase structure and a second staircase structure mirroring the first staircase structure, and forming a second stadium structure within the first preliminary stack structure, the second stadium structure including a third staircase structure and a fourth staircase structure mirroring the third staircase structure.

[0146] Embodiment 26: The method of embodiment 25, wherein forming a second stadium structure in the first preliminary stack structure includes vertically extending an opening defined by a third stadium structure formed in the second preliminary stack structure into the first preliminary stack structure to form the second stadium structure.

[0147] Embodiment 27: An electronic system including: an input device; an output device; a processor device operably coupled to the input device and the output device; a memory device operably coupled to the processor device and including at least one microelectronic device structure having a memory array region and a staircase region, the at least one microelectronic device structure being a stack structure having tiers each including a conductive structure and an insulating structure vertically adjacent the conductive structure, the stack structure including a deck including some of the tiers, an additional deck vertically above the deck and including others of the tiers, and an inter-deck section vertically between the deck and the additional deck, the inter-deck section including at least one dielectric structure within a horizontal boundary of the memory array region and substantially absent or not extending completely across a horizontal region of the staircase region; a staircase structure in the staircase region having a step including edges of the tiers of the stack structure in the deck and the additional deck; and a semiconductor pillar structure in the memory array region and extending vertically through the stack structure.

[0148] While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail herein. However, the disclosure is not limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the following appended claims and their legal equivalents.

Claims

1. 1. A microelectronic device comprising a microelectronic device structure having a memory array region and a staircase region, The microelectronic device structure comprises:

1. A stack structure having tiers, each tier including a conductive structure and an insulating structure vertically adjacent the conductive structure, the stack structure comprising: a lower deck including a first group of the tiers; an upper deck vertically above the lower deck and including a second group of the tiers; an inter-deck section vertically between the lower deck and the upper deck, the inter-deck section comprising: a dielectric structure confined horizontally within the memory array region and absent from horizontal areas of the staircase region; a third group of said tiers within a vertical boundary of said dielectric structure and horizontally confined within said staircase region; the inter-deck section including The stack structure, a staircase structure having steps horizontally confined within the staircase area and including edges of the tiers of the stack structure in the lower deck and the upper deck; a semiconductor pillar structure confined horizontally within the memory array area and extending vertically through the stack structure; 4. A microelectronic device comprising:

2. The microelectronic device of claim 1 further comprising a plug structure within said dielectric structure and laterally surrounding said semiconductor pillar structure.

3. The microelectronic device of claim 1 , wherein the third group of the tiers in the inter-deck section of the stack structure includes at least two of the tiers of the stack structure.

4. The microelectronic device of claim 1 , wherein the dielectric structure and the insulating structure of each of the tiers of the stack structure comprise at least one dielectric oxide material.

5. A microelectronic device according to any one of claims 1 to 3, wherein the inter-deck section of the stack structure does not include within its vertical boundaries any part of the stair structure.

6. The staircase structure includes: A first stadium structure within the lower deck of the stack structure, a first staircase structure having a positive slope; a second staircase structure facing the first staircase structure and having a negative slope; The first stadium structure including: a second stadium structure within the upper deck of the stack structure, a third stair structure having a positive slope; and a fourth staircase structure facing the third staircase structure and having a negative slope; the second stadium structure including: The microelectronic device according to any one of claims 1 to 3, comprising:

7. forming a microelectronic device structure having a memory array region and a staircase region, the microelectronic device structure being formed to include a first preliminary stack structure including a vertically alternating sequence of first insulating structures and second insulating structures arranged in tiers; forming a dielectric structure in an upper portion of the first preliminary stack structure, the dielectric structure being confined within a horizontal boundary of the memory array region and being absent from a horizontal region of the staircase region; forming a second preliminary stack structure above the first preliminary stack structure and the dielectric structure, the second preliminary stack structure including a vertically alternating sequence of additional first insulating structures and additional second insulating structures arranged in additional tiers; forming a semiconductor pillar structure extending vertically through the second preliminary stack structure, the dielectric structure, and portions of the first preliminary stack structure in the memory array area; forming staircase structures within the second preliminary stack structure and the portion of the first preliminary stack structure within the staircase region, some of the staircase structures having a step including a horizontal end of the tier of the first preliminary stack structure and others of the staircase structures having an additional step including a horizontal end of the additional tier of the additional second preliminary stack structure; at least partially replacing the second insulating structure and the additional second insulating structure with a conductive structure; A method for forming a microelectronic device comprising:

8. forming a dielectric structure in an upper portion of the first preliminary stack structure, forming a photoresist structure over a portion of the first preliminary stack structure in the staircase region; selectively removing the top portion of the first preliminary stack structure using the photoresist structure as a mask to form a recess in the first preliminary stack structure, the recess being substantially confined within the horizontal boundary of the memory array area; forming a dielectric fill material over an exposed surface of the first preliminary stack structure inside and outside the recess; removing portions of the dielectric fill material outside horizontal and vertical boundaries of the recess to form the dielectric structure; The method of claim 7, comprising:

9. 8. The method of claim 7, further comprising selecting the first insulating structure of the first preliminary stack structure, the dielectric structure, and the additional first insulating structure of the second preliminary stack structure to each comprise a dielectric oxide material.

10. Forming a semiconductor pillar structure includes: forming an opening extending vertically through the dielectric structure and a lower portion of the first preliminary stack structure underlying the dielectric structure; covering the opening with a plug structure extending vertically partially into the opening; forming the second preliminary stack structure over the first preliminary stack structure, the dielectric structure, and the plug structure; forming an additional opening extending vertically through the second preliminary stack structure and the plug structure to a remainder of the opening to form a relatively large opening; filling the relatively large opening with a semiconductor material; The method according to any one of claims 7 to 9, comprising:

11. forming a staircase structure within the portion of the second preliminary stack structure and the first preliminary stack structure within the staircase region, forming a first stadium structure within the second preliminary stack structure, the first stadium structure comprising: a first one of the staircase structures having a positive slope; and a second staircase structure of the staircase structures facing the first staircase structure of the staircase structures and having a negative slope; and forming a second stadium structure within the first preliminary stack structure, the second stadium structure comprising: a third one of the staircase structures having a positive slope; and a fourth staircase structure of the staircase structures facing the third staircase structure of the staircase structures and having a negative slope; and The method according to any one of claims 7 to 9, comprising:

12. 12. The method of claim 11, wherein forming the second stadium structure in the first preliminary stack structure includes vertically extending an opening formed in the second preliminary stack structure into the first preliminary stack structure.

13. 8. The method of claim 7, wherein at least partially replacing the second insulating structure and the additional second insulating structure with a conductive structure comprises at least partially replacing the second insulating structure and the additional second insulating structure with tungsten.

14. 1. A microelectronic device comprising a microelectronic device structure having a memory array region and a staircase region, The microelectronic device structure comprises: A stack structure comprising: a lower deck including a first group of tiers, each tier in the first group including a first conductive structure and a first insulating structure vertically adjacent the first conductive structure; an upper deck overlying the lower deck and including a second group of tiers, each tier in the second group including a second conductive structure and a second insulating structure vertically adjacent the second conductive structure; an inter-deck section between the lower deck and the upper deck, the inter-deck section comprising: an inter-deck dielectric structure that is horizontally confined within the memory array region and is absent from the horizontal areas of the staircase region; a third group of tiers horizontally between the inter-deck dielectric structures, each tier in the third group including a third insulating structure and a fourth insulating structure vertically adjacent the third insulating structure; the inter-deck section including The stack structure, a staircase structure having steps including edges of the tiers of the stack structure in the lower deck and the upper deck; a semiconductor pillar structure extending vertically through the stack structure; 4. A microelectronic device comprising:

15. The microelectronic device of claim 14 , wherein the semiconductor pillar structure is positioned horizontally between two adjacent inter-deck dielectric structures.

16. 16. The microelectronic device of claim 15, wherein the semiconductor pillar structure extends vertically through the second group of tiers in the upper deck of the stack structure, the third group of tiers in the inter-deck section of the stack structure, and the first group of tiers in the lower deck of the stack structure.

17. 17. The microelectronic device of claim 14, further comprising fill slots extending vertically through the tiers of the stack structure and the inter-deck dielectric structure, each of the fill slots being filled with at least one dielectric material.

18. 17. The microelectronic device of claim 14, wherein the inter-deck dielectric structure, the first insulating structure of the first group of tiers in the lower deck of the stack structure, the second insulating structure of the second group of tiers in the upper deck of the stack structure, and the third insulating structure of the third group of tiers in the inter-deck section of the stack structure comprise at least one dielectric oxide material.

19. 20. The microelectronic device of claim 18, wherein the fourth insulating structure of the third group of tiers in the inter-deck section of the stack structure comprises at least one dielectric nitride material.

20. The staircase structure includes: A first stadium structure within the upper deck of the stack structure, a first staircase structure having a positive slope; a second staircase structure mirroring the first staircase structure and having a negative slope; The first stadium structure including: a second stadium structure within the lower deck of the stack structure, a third stair structure having a positive slope; and a fourth staircase structure mirroring the third staircase structure and having a negative slope; the second stadium structure including: The microelectronic device according to any one of claims 14 to 16, comprising:

21. forming a microelectronic device structure including a first preliminary stack structure including a vertically alternating sequence of first insulating structures and second insulating structures arranged in tiers, the microelectronic device structure including a memory array region and a staircase region; forming a vertically extending dielectric structure in the first preliminary stack structure, the dielectric structure being horizontally confined within the memory array region and absent from horizontal regions of the staircase region; forming a second preliminary stack structure above the first preliminary stack structure and the dielectric structure, the second preliminary stack structure including a vertically alternating sequence of additional first insulating structures and additional second insulating structures arranged in additional tiers; forming a semiconductor pillar structure extending vertically through portions of the second preliminary stack structure and the first preliminary stack structure, the semiconductor pillar structure being positioned horizontally between two adjacent dielectric structures; forming staircase structures in the second preliminary stack structure and the first preliminary stack structure, some of the staircase structures having steps that include edges of the tiers of the first preliminary stack structure and others of the staircase structures having additional steps that include edges of the additional tiers of the second preliminary stack structure; replacing the additional second insulating structure of the second preliminary stack structure and the second insulating structure of the first preliminary stack structure positioned outside a vertical boundary of the dielectric structure with a conductive structure; A method for forming a microelectronic device comprising:

22. forming a vertically extending dielectric structure in the first preliminary stack structure comprises: forming a photoresist structure over the first preliminary stack structure, the photoresist structure including a photoresist material having an opening extending vertically therethrough; selectively removing an upper portion of the first preliminary stack structure exposed by and within a horizontal boundary of the opening in the photoresist material of the photoresist structure to form a recess in the first preliminary stack structure; forming a dielectric fill material over an exposed surface of the first preliminary stack structure inside and outside the recess; removing a portion of the dielectric fill material outside a boundary of the recess to form the dielectric structure; 22. The method of claim 21 , comprising:

23. selecting the first insulating structure of the first preliminary stack structure, the dielectric structure, and the additional first insulating structure of the second preliminary stack structure to each comprise a dielectric oxide material; selecting the second insulating structure of the first preliminary stack structure and the additional second insulating structure of the second preliminary stack structure to each comprise a dielectric nitride material; 22. The method of claim 21 further comprising:

24. Forming a semiconductor pillar structure includes: forming an opening extending vertically through a portion of the tier of the first preliminary stack structure, the opening being positioned horizontally between two adjacent dielectric structures; covering the opening with a plug structure extending vertically partially into the opening; forming the second preliminary stack structure over the first preliminary stack structure, the dielectric structure, and the plug structure; forming an additional opening extending vertically through the second preliminary stack structure and the plug structure to a remainder of the opening to form a relatively large opening; filling the relatively large opening with a semiconductor material; The method according to any one of claims 21 to 23, comprising:

25. Forming a staircase structure in the second preliminary stack structure and the first preliminary stack structure includes: forming a first stadium structure within the second preliminary stack structure, the first stadium structure comprising: A first staircase structure of the staircase structures; and a second staircase structure of the staircase structures that mirrors the first staircase structure of the staircase structures; and and forming a second stadium structure within the first preliminary stack structure, the second stadium structure comprising: A third staircase structure among the staircase structures; and a fourth one of the staircase structures that mirrors the third one of the staircase structures; and and The method according to any one of claims 21 to 23, comprising:

26. 26. The method of claim 25, wherein forming a second stadium structure in the first preliminary stack structure includes vertically extending an opening defined by a third stadium structure formed in the second preliminary stack structure into the first preliminary stack structure to form the second stadium structure.

27. An input device; An output device; a processor device operatively coupled to the input device and the output device; a memory device operatively coupled to the processor device and including at least one microelectronic device structure having a memory array region and a staircase region; An electronic system comprising: The at least one microelectronic device structure comprises:

1. A stack structure having tiers, each tier including a conductive structure and an insulating structure vertically adjacent the conductive structure, the stack structure comprising: a lower deck including some of the tiers; and an upper deck vertically above said lower deck and including others of said tiers; an inter-deck section vertically between the lower deck and the upper deck, the inter-deck section including at least one dielectric structure within a horizontal boundary of the memory array region and absent from a horizontal region of the staircase region; The stack structure, a staircase structure in the staircase region, the staircase structure having steps including edges of the tiers of the stack structure in the lower deck and the upper deck; a semiconductor pillar structure in the memory array area extending vertically through the stack structure; 2. An electronic system comprising:

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