Wrap-around contacts for top source / drain of vertical field-effect transistors

Abstract

The semiconductor structure and method for making the same includes: a first recessed region in the semiconductor structure defining a first opening having a first positive tapering profile that widens the first opening in a direction toward a top source / drain region of the semiconductor structure at a first tapering angle as at least a portion of the first positive tapering profile; and top source / drain contacts in the first opening, the top source / drain contacts surrounding a surface of the top source / drain region. The semiconductor structure further includes a protective liner located at an interface between a bottom portion of the top source / drain region, a top spacer adjacent to the top source / drain region, and a dielectric material between two consecutive top source / drain regions, the protective liner protecting the top source / drain region during contact patterning.

Description

[Technical field]

[0001] The present invention relates generally to the field of semiconductor devices, and more particularly to a method for forming source / drain contacts surrounding a top source / drain region of a vertical field effect transistor (VFET). [Background technology]

[0002] VFETs have been pursued as a potential device option for scaling complementary metal-oxide semiconductors (CMOS) to the 5 nanometer (nm) node and beyond. In contrast to planar CMOS devices, VFETs are oriented vertically with vertical fins or nanowires extending upward from a substrate. The fins or nanowires form the channel region of the transistor. Source and drain regions are placed in electrical contact with the top and bottom ends of the channel region, while a gate is disposed on one or more of the fin or nanowire sidewalls. Thus, in a VFET, the direction of current flow between the source and drain regions is perpendicular to the major surface of the substrate.

[0003] In current VFET integration schemes, top source / drain contact (CA) over-etch is performed to achieve the desired contact dimensions and ensure good contact landing. However, during this process, over-etching of the dielectric material between the epi regions can occur, causing CA to gate shorts. Summary of the Invention

[0004] According to an embodiment, a method of forming a semiconductor structure includes forming a first recessed region in the semiconductor structure, the first recessed region defining a first opening having a first positive tapering profile that widens the first opening in a direction toward a top source / drain region of the semiconductor structure at a first tapering angle as at least a portion of the first positive tapering profile, and forming top source / drain contacts in the first opening, the top source / drain contacts surrounding a surface of the top source / drain region.

[0005] According to another embodiment, a method of forming a semiconductor structure includes forming a top source / drain region in contact with an upper surface of a channel fin extending vertically from a bottom source / drain region located above a substrate, where a top spacer separates the top source / drain region from a high-k metal gate stack located around the channel fin, the channel fin and the top spacer in contact with an adjacent first interlayer dielectric layer located immediately above the bottom source / drain region; recessing the first interlayer dielectric layer to expose a top portion of the top source / drain region and a top portion of the top spacer adjacent the top source / drain region; selectively removing the exposed top portion of the top spacer to expose a bottom portion of the top source / drain region; and conformally depositing a protective liner over the top source / drain region in direct contact with the top source / drain region.

[0006] According to yet another embodiment, a semiconductor structure includes a first region including a first positive tapering profile, the first positive tapering profile including a first tapering angle diverging in a direction toward a top source / drain region of the semiconductor structure, and a top source / drain contact in the first region, the top source / drain contact surrounding a surface of the top source / drain region.

[0007] The following detailed description, given by way of example and not solely as a limitation of the invention, will be best understood in conjunction with the accompanying drawings. [Brief description of the drawings]

[0008] [Figure 1A] 1A-1D are cross-sectional views of a semiconductor structure at an intermediate step during a semiconductor manufacturing process, in accordance with an embodiment of the present invention. [Figure 1B] FIG. 2 is a side view of a semiconductor structure taken along the Y plane. [Figure 2A] 2 is a cross-sectional view of a semiconductor structure after forming top source / drain regions according to an embodiment of the present invention. [Figure 2B] FIG. 2 is a side view of a semiconductor structure taken along the Y plane. [Figure 3A] 2 is a cross-sectional view of a semiconductor structure after recessing a first interlevel dielectric layer according to an embodiment of the present invention. [Figure 3B] FIG. 2 is a side view of a semiconductor structure taken along the Y plane. [Figure 4A] 1A-1C are cross-sectional views of a semiconductor structure illustrating selective removal of exposed portions of a top spacer according to an embodiment of the present invention. [Figure 4B] FIG. 2 is a side view of a semiconductor structure taken along the Y plane. [Figure 5A] 1 is a cross-sectional view of a semiconductor structure after deposition of a protective liner in accordance with an embodiment of the present invention. [Figure 5B] FIG. 2 is a side view of a semiconductor structure taken along the Y plane. [Figure 6A] 1A-1C are cross-sectional views of a semiconductor structure illustrating deposition of a sacrificial material according to an embodiment of the present invention. [Figure 6B] FIG. 2 is a side view of a semiconductor structure taken along the Y plane. [Figure 7A] FIG. 2 is a cross-sectional view of a semiconductor structure after deposition of an organic planarization layer and contact patterning according to one embodiment of the present invention. [Figure 7B] FIG. 2 is a side view of a semiconductor structure taken along the Y plane. [Figure 8A] FIG. 2 is a cross-sectional view of a semiconductor structure after depositing a second interlevel dielectric layer and removing the organic planarization layer in accordance with an embodiment of the present invention. [Figure 8B] FIG. 2 is a side view of a semiconductor structure taken along the Y plane. [Figure 9A] 2 is a cross-sectional view of a semiconductor structure after removal of a sacrificial material according to an embodiment of the present invention. [Figure 9B] FIG. 2 is a side view of a semiconductor structure taken along the Y plane. [Figure 10A] 1 is a cross-sectional view of a semiconductor structure after middle-of-line contact metallization according to one embodiment of the present invention. [Figure 10B] FIG. 2 is a side view of a semiconductor structure taken along the Y plane. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The drawings are not necessarily to scale. The drawings are merely schematic representations and do not depict specific parameters of the invention. The drawings depict only typical embodiments of the invention. In the drawings, like numbers represent like elements.

[0010] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in a variety of forms. The invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the specification, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0011] For purposes of the following description, terms such as "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof, shall refer to the disclosed structures and methods as oriented in the illustrated figures. Terms such as "above," "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, is above a second element, such as a second structure, where an intervening element, such as an interface structure, may be between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the interface of the two elements.

[0012] In order not to obscure the description of the embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be integrated together for the purposes of description and illustration, and in some cases may not be described in detail. In other cases, some process steps or operations known in the art may not be described at all. It should be understood that the following description will rather focus on distinctive features or elements of various embodiments of the present invention.

[0013] Some non-planar transistor device architectures, such as the VFET, utilize semiconductor fins and side gates that may be contacted outside the active area, resulting in greater device density than lateral devices. In a VFET, current from source to drain flows in a direction perpendicular to the main surface of the substrate. For example, in a known VFET configuration, the main substrate surface is horizontal, and a vertical fin extends upward from the substrate surface. The fin forms the channel region of the transistor. Source / drain regions are placed in electrical contact with the top and bottom ends of the channel region (i.e., the top source / drain region and the bottom source / drain region), while a gate is disposed on one or more of the fin sidewalls. A contact patterning process is performed to form metal contacts to the top source / drain region (CA contact), the bottom source / drain region (CR contact), and the gate (CB contact).

[0014] In the current VFET integration scheme, CA over-etch is performed to achieve the desired contact dimensions and ensure good contact landing. However, during this process, over-etching of the dielectric material between the epi regions can occur, causing CA-gate shorts. The CA etch can easily punch through the dielectric material, especially when weak spots exist in the dielectric material. If CA over-etch is not performed, the contact size is too small. Possible solutions to reducing the CA contact size may include (1) increasing the size of the top epi region, or (2) increasing the CA contact to cover the surface of the top epi region, or both. Both (1) and (2) can cause device shorts.

[0015] Therefore, embodiments of the present invention provide a method and related structure for forming a VFET device having a top source / drain contact that surrounds a surface of the top source / drain region with a protective liner located at the interface between a bottom portion of the top source / drain region, a top spacer adjacent the top source / drain region, and a dielectric material between two consecutive top source / drain regions. By forming the protective liner, over-etching of the dielectric material located between adjacent top source / drain regions does not expose the top source / drain during contact patterning, thus preventing contact shorting and improving device reliability. An embodiment by which a VFET device having a wrap-around top contact and a protective liner can be formed is described in detail below by referring to the accompanying drawings of Figures 1A-10B.

[0016] 1A, there is shown a cross-sectional view of a semiconductor structure 100 in accordance with one embodiment of the present invention. In this embodiment, FIG. 1B is a side view of the semiconductor structure 100 taken along the Y-axis, specifically along the channel fin 112.

[0017] Known semiconductor fabrication operations have been used to form the semiconductor structure 100. At this step of the fabrication process, the semiconductor structure 100 includes a bottom S / D region 106 formed above a substrate 102, a channel fin 112 formed above the bottom S / D region 106, bottom spacers 118 formed at opposing ends of the channel fin 112, high-k metal gate stacks 120 disposed above the bottom spacers 118 at (adjacent) opposing ends of the channel fin 112, a first interlayer dielectric (ILD) layer 124, top spacers 126 above the high-k metal gate stacks 120 and on (adjacent) opposing ends of the channel fin 112, and shallow trench isolation regions (STI) 108 constructed and arranged as shown in the figure.

[0018] The various elements forming the semiconductor structure 100 extend along a first axis (e.g., the X-axis) to define a width dimension, and extend along a second axis (e.g., the Y-axis) perpendicular to the X-axis to define a height (or thickness) dimension. Although not specifically depicted in the cross-sectional views shown in Figures 1A-1B, the various elements forming the semiconductor structure 100 also extend along a third axis (e.g., the Z-axis) perpendicular to the first and second axes to define a depth dimension. In accordance with standard VFET architecture, the various elements of the semiconductor structure 100 (e.g., bottom spacer 118, high-k metal gate stack 120, etc.) extend all the way around the sidewalls of the channel fin 112 in the X, Y, and Z directions.

[0019] 1A-1B, the substrate 102 can be any suitable substrate material, such as, for example, single crystal Si, SiGe, SiC, III-V compound semiconductors, II-VI compound semiconductors, or semiconductor-on-insulator (SOI). In some embodiments, the substrate 102 includes a buried oxide layer (not shown). In some embodiments, the bottom S / D region 106 can be formed before the channel fin 112. In some embodiments, the bottom S / D region 106 is epitaxially grown after the formation of the channel fin 112, and the doping required to form the bottom S / D region 106 is done via in situ doping during the epitaxial growth process or via ion implantation after the bottom S / D region 106 is formed. The bottom S / D regions 106 may be formed by any suitable doping technique, including, but not limited to, ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, in situ epitaxy growth, or any suitable combination of these techniques.

[0020] The epitaxial material can be formed from gaseous or liquid precursors. The epitaxial material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. Epitaxial silicon, silicon germanium, germanium, or carbon doped silicon (Si:C), or combinations thereof, can be doped during deposition (in situ doped) by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (boron or gallium), depending on the type of transistor. The dopant concentration in the bottom S / D region 106 can be greater than 1×10 19 cm -3 From 2 × 10 21 cm -3 up to, or preferably 2 x 10 20 cm -3 and 2×10 21 cm -3 The range may be between .

[0021] The terms "epitaxially grown and / or deposited" and "epitaxially formed and / or grown" refer to the growth of one semiconductor material (a crystalline material) on a deposition surface of another semiconductor material (a crystalline material) where the grown semiconductor material (the crystalline overlayer) has substantially the same crystalline properties as the semiconductor material of the deposition surface (the seed material). In an epitaxial deposition process, chemical reactants provided by source gases are controlled and system parameters are set such that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around the surface, so that the deposited atoms self-orient in the crystalline arrangement of the atoms of the deposition surface. Thus, the epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which the epitaxially grown material is formed. For example, epitaxially grown semiconductor material deposited on a {100} oriented crystalline surface will inherit the {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective to formation on semiconductor surfaces and generally does not deposit material on exposed surfaces such as silicon dioxide or silicon nitride surfaces.

[0022] In some embodiments, the gas source for deposition of epitaxial semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon (Si) layer can be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Meanwhile, an epitaxial silicon-germanium alloy layer can be formed using a combination of such gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0023] As shown, the substrate 102 further includes an STI region 108. Shallow trench isolation regions, such as the STI region 108, are often used in semiconductor technology to isolate active areas within the substrate 102 and to prevent current leakage between adjacent components. The process of forming the STI region 108 is well known in the art and generally involves etching the substrate 102 to create a recess that is subsequently filled with an insulating material using any deposition method known in the art. In some embodiments, the STI region 108 can be composed of any low-k dielectric material, including, but not limited to, silicon nitride, silicon oxide, silicon oxynitride, and fluorine-doped silicate glass.

[0024] A bottom spacer 118 is formed from the doped S / D region 106 to a bottom portion of the adjacent channel fin 112. The bottom spacer 118 can include a dielectric material such as, for example, SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, SiOxNy, and combinations thereof. The dielectric material can be a low-k material having a dielectric constant of less than about 7, less than about 5, or even less than about 2.5. The bottom spacer 118 can be formed using a combination of known deposition and etching processes, such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical solution deposition, and etching processes including reactive ion etch (RIE), wet etch, or isotropic gas phase dry etch.

[0025] As shown in the figure, a high-k metal gate stack 120 is formed in direct contact with the channel fin 112. For ease of illustration, the high-k metal gate stack 120 is depicted as simply one layer. However, as known to those skilled in the art, the high-k metal gate stack 120 may include a gate dielectric and a gate conductor / metal (e.g., a work function metal (WFM)) disposed adjacent a portion of the channel fin 112 above the bottom spacer 118. In some embodiments, the high-k metal gate stack 120 is deposited by ALD.

[0026] The gate dielectric (not shown) can be formed from one or more gate dielectric films. The gate dielectric film can be, for example, a dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0. Non-limiting examples of suitable materials for the high-k dielectric film include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials having a dielectric constant greater than 7.0 include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zircon oxide, zircon silicon oxide, zircon silicon oxynitride, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The gate dielectric film may further include dopants such as, for example, lanthanum and aluminum. The gate dielectric film may be formed by a suitable deposition process, such as, for example, CVD, PECVD, ALD, PVD, chemical solution deposition, or other similar processes. The thickness of the gate dielectric film may vary depending on the deposition process and the composition and number of high-k dielectric materials used.

[0027] The gate conductor (not shown) in the high-k metal gate stack 120 can include doped polycrystalline or amorphous silicon, germanium, silicon-germanium, metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), conductive metal compound materials (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium-aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials. The conductive material can further include dopants that are incorporated during or after deposition. In some embodiments, the gate conductor can be a WFM deposited above the gate dielectric film by a suitable deposition process, such as CVD, PECVD, PVD, plating, thermal or e-beam evaporation, and sputtering. The type of WFM depends on the type of transistor and can vary between nFET and pFET devices. P-type WFMs include compositions such as titanium nitride (TiN), ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, or any combination thereof. N-type WFMs include compositions such as titanium carbide (TiC), titanium aluminum carbide (TiAlC), hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and titanium carbide), aluminides, or any combination thereof. The gate conductor can further include tungsten (W), titanium (Ti), aluminum (Al), cobalt (Co), or nickel (Ni) material above the WFM layer of the gate conductor. The gate conductor can be deposited by a suitable deposition process, such as CVD, PECVD, PVD, plating, thermal or electron beam evaporation, and sputtering.

[0028] In this embodiment, the high-k metal gate stack 120 is conformally deposited on the semiconductor structure 100. After deposition of the high-k metal gate stack 120, a patterning process is performed on the semiconductor structure 100 to etch away the unwanted high-k metal gate stack 120.

[0029] A first ILD layer 124 is formed to fill voids between gate structures and other existing devices in the semiconductor structure 100. The first ILD layer 124 can be formed, for example, by CVD of a dielectric material. Non-limiting examples of dielectric materials for forming the first ILD layer 124 can include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon-based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics, including porous organic dielectrics.

[0030] Typically, after deposition of the first ILD layer 124 , a chemical mechanical polishing (CMP) process is performed on the semiconductor structure 100 to expose the top surface of the channel fin 112 .

[0031] 1A-1B , in some embodiments, after removing the fin hard mask (not shown), the high-k metal gate stack 120 can be recessed below the top surface of the channel fin 112 as shown. A top spacer 126 can then be conformally deposited above and in direct contact with the high-k metal gate stack 120. In such embodiments, the top spacer 126 can be deposited using, for example, CVD, PECVD, radio frequency CVD (RFCVD), PVD, ALD, molecular layer deposition (MLD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), sputtering, and / or plating. Non-limiting examples of materials forming the top spacer 126 may include silicon nitride (SiN), silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), or silicon oxycarbonitride (SiOCN). Prior to deposition of the first ILD layer 124, any suitable etching technique (e.g., RIE) may be used to remove the top spacer 126 from the upper surface of the channel fin 112, as shown.

[0032] It should be noted that although the bottom spacer 118 and the top spacer 126 are depicted on adjacent opposing sides of the channel fin 112, the bottom spacer 118 and the top spacer 126 surround the entire surface of the channel fin 112. The bottom spacer 118 and the top spacer 126 can determine the location of a pn junction within the semiconductor structure 100.

[0033] 2A, there is shown a cross-sectional view of semiconductor structure 100 after forming top S / D regions 202, in accordance with one embodiment of the present invention. In this embodiment, FIG. 2B is a side view of semiconductor structure 100 taken along the Y-axis.

[0034] At this point in the fabrication process, the top S / D region 202 may be formed off of the exposed portion of the channel fin 112 following steps similar to those described above with respect to the bottom S / D region 106. As may be known to one skilled in the art, the diamond shape observed in the top S / D region 202 is a result of different growth rates during the epitaxial deposition process inherent to each crystallographic orientation plane of the material forming the top S / D region 202. In other embodiments, the top S / D region 202 may have a shape other than the diamond shape shown in FIG. 2A. It should be noted that although references to the top S / D region 202 and the channel fin 112 are made in the singular, more than one top S / D region 202 and more than one channel fin 112 may be present in the semiconductor structure 100 as shown in the figures.

[0035] 3A, there is shown a cross-sectional view of the semiconductor structure 100 after recessing the first ILD layer 124, in accordance with one embodiment of the present invention. In this embodiment, FIG. 3B is a side view of the semiconductor structure 100 taken along the Y-axis.

[0036] As shown, recessing the first ILD layer 124 exposes a top portion of the top S / D region 202 and a top portion of the top spacer 126 adjacent to the top S / D region 202. According to one embodiment, recessing the first ILD layer 124 is accomplished by performing a blanket atomic layer etch (ALE) on the dielectric material forming the first ILD layer 124. The ALE etch can provide high selectivity because the dose gas and ion energy can be tailored to minimize etching of the mask layer or underlying material.

[0037] It is noted that to ensure good contact landing in current VFET integration schemes, over-etching of the ILD (i.e., first ILD layer 124) located between the top epitaxial regions (i.e., top S / D regions 202) may occur during a typical RIE process, which facilitates CA-gate shorts. This is especially true in cases where weak spots may exist in the dielectric material. Thus, by using a blank ALE etch instead of traditional RIE, precise control of the etch depth can be achieved to avoid over-etching of the first ILD layer 124 and prevent CA-gate shorts. It is also noted that in some embodiments, a selective ILD etch process, such as a selective wet etch or a selective dry etch using BHF or DHF, can be used to recess the ILD relative to the surrounding material.

[0038] 4A, there is shown a cross-sectional view of semiconductor structure 100 illustrating selective removal of exposed portions of top spacers 126, in accordance with one embodiment of the present invention. In this embodiment, FIG. 4B is a side view of semiconductor structure 100 taken along the Y-axis.

[0039] After recessing the first ILD layer 124, portions of the top spacers 126 are exposed as seen in Figures 3A-3B. In this embodiment, the exposed portions of the top spacers 126 are selectively removed using any suitable etching technique. In an exemplary embodiment, a selective wet etch process, such as hot phosphoric acid, or a selective dry etch process may be used to remove the top spacers.

[0040] 5A, there is shown a cross-sectional view of semiconductor structure 100 after deposition of a (sacrificial) protective liner 502, in accordance with one embodiment of the present invention. In this embodiment, FIG. 5B is a side view of semiconductor structure 100 taken along the Y-axis.

[0041] According to an embodiment, the protective liner 502 comprises titanium (Ti), titanium oxide (TiOx), or titanium nitride (TiN), or a combination thereof. The protective liner 502 protects the top S / D regions 202 during a contact patterning process, as described in detail below. The protective liner 502 is conformally deposited on the semiconductor structure 100 above the top S / D regions 202, the first ILD layer 124, and the top spacer 126, and in direct contact with the top spacer 126, as shown. The protective liner 502 can be formed by any suitable deposition technique, such as, for example, ALD. According to an embodiment, the thickness of the protective liner 502 can vary from approximately 5 nm to approximately 20 nm.

[0042] 6A, there is shown a cross-sectional view of semiconductor structure 100 illustrating deposition of sacrificial material 610, in accordance with one embodiment of the present invention. In this embodiment, FIG. 6B is a side view of semiconductor structure 100 taken along the Y-axis.

[0043] A sacrificial material 610 is formed on the semiconductor structure 100 to define a contact placeholder. In one embodiment, the sacrificial material 610 comprises an amorphous silicon (a-Si) layer. In other embodiments, the sacrificial material 610 can comprise materials such as SiGe, TiOx, AlOx, room temperature oxide, etc. The sacrificial material 610 can be deposited using a standard deposition process such as PECVD. The thickness of the sacrificial material 610 can vary from approximately 20 nm to approximately 100 nm.

[0044] 7A, there is shown a cross-sectional view of semiconductor structure 100 illustrating deposition and contact patterning of an organic planarization layer (OPL) 720, in accordance with one embodiment of the present invention. In this embodiment, FIG. 7B is a side view of semiconductor structure 100 taken along the Y-axis.

[0045] The OPL 720 is formed directly on the sacrificial material 610. The OPL can be made of any organic planarization material that can effectively prevent damage to the underlying layers during the subsequent etching process. According to an embodiment, the OPL 720 allows for excellent depth control during the contact patterning process. The OPL 720 can include, but is not necessarily limited to, organic polymers containing C, H, and N. According to an embodiment, the OPL material can be free of silicon (Si). According to another embodiment, the OPL material can be free of Si and fluorine (F). As defined herein, a material is free of atomic elements when the level of the atomic element in the material is at or below trace levels detectable using analytical methods available in the art. Non-limiting examples of OPL materials forming the OPL 720 can include JSR HM8006, JSR HM8014, AZ UM10M2, Shin Etsu ODL102, or other similar commercially available materials. OPL720 can be deposited, for example, by spin coating followed by a planarization process such as CMP.

[0046] Continuing with reference to Figures 7A-7B, the lithography process is followed by an etching process performed on the semiconductor structure 100 to etch the OPL 720, the sacrificial material 610, the protective liner 502, and the top portion of the first ILD layer 124, as shown in the figures. In some embodiments, etching the OPL 720, the sacrificial material 610, the protective liner 502, and the first ILD layer 124 involves a two-step process. For example, an OPL RIE with trace point detection is performed to etch the OPL 720 down to the top portion of the protective liner 502. The process then continues with a time etch technique that allows recessing the protective liner 502 and the first ILD layer 124 to a depth of approximately 5 nm to approximately 30 nm into the first ILD layer 124. In other words, the etching of the protective liner 502 and first ILD layer 124 occurs until the protective layer 502 is no longer present anywhere on the wafer at the bottom of the first recess (or trench) 730, as shown in the figure. As can be seen, the first recess 730 formed in the semiconductor structure 100 includes tapered angles for subsequent formation of source / drain contacts and gate contacts, as described in more detail below.

[0047] It should be noted that by etching through the protective layer 502, the top S / D regions 202, and the first ILD layer 124, the top source / drain regions between adjacent devices or between top and bottom contacts within a device can be effectively isolated, thus avoiding contact shorts.

[0048] 8A, there is shown a cross-sectional view of semiconductor structure 100 illustrating deposition of second ILD layer 802 and removal of OPL 720 in accordance with one embodiment of the present invention. In this embodiment, FIG. 8B is a side view of semiconductor structure 100 taken along the Y-axis.

[0049] Exemplary techniques suitable for removing OPL720 may include, but are not limited to, oxygen plasma, nitrogen plasma, hydrogen plasma or other carbon strip or ashing processes that cause minimal or no damage to the underlying layers.

[0050] A second ILD layer 802 is deposited over the semiconductor structure 100 to substantially fill the first recess 730 (FIGS. 7A-7B). The second ILD layer 802 may be made of similar materials and formed in a similar manner as the first ILD layer 124. In some embodiments, a planarization process may be performed on the semiconductor structure 100 after deposition of the second ILD layer 802.

[0051] 9A, there is shown a cross-sectional view of the semiconductor structure 100 after removing the sacrificial material 610, in accordance with an embodiment of the present invention. In this embodiment, FIG. 9B is a side view of the semiconductor structure 100 taken along the Y-axis.

[0052] Standard etching techniques can be performed to remove the sacrificial material 610. For example, in one embodiment, the sacrificial material 610 can be removed by a hot ammonia wet etch. After removal of the sacrificial material 610, any exposed protective liner 502 can also be removed, for example, by a wet SC1. Removal of the sacrificial material 610 and exposed protective liner 502 from the semiconductor structure 100 creates a second recess 930 for forming top source / drain contacts, as described in more detail below.

[0053] 10A, there is shown a cross-sectional view of a semiconductor structure 100 after middle-of-line (MOL) contact metallization, in accordance with one embodiment of the present invention, in which FIG. 10B is a side view of the semiconductor structure 100 taken along the Y-axis.

[0054] As shown, the top source / drain contact 1012 (i.e., CA contact) extends all the way through to the top S / D region 202, while the bottom source / drain contact 1014 (i.e., CR contact) extends all the way through to the bottom S / D region 106. The process of forming metal contacts is standard and well known in the art. Typically, the process involves patterning the bottom S / D (CR) trench and the gate contact trench (CB), followed by filling the trenches (i.e., second recess 930 in FIGS. 9A-9B) formed in a dielectric layer, such as the second ILD layer 802 and / or the first ILD layer 124, with a conductive material or combination of conductive materials to form the top source / drain contact 1012, the bottom source / drain contact 1014, and the gate contact 1016. The conductive material filling the top source / drain contact 1012, bottom source / drain contact 1014, and gate contact 1016 comprises a conductive metal, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), cobalt (Co), ruthenium (Ru), copper (Cu), or any combination thereof. Note that in some embodiments, an adhesion metal liner (not shown) can be used before the conductive metal depth, such as TiN, TaN, etc. The conductive material can be deposited by a suitable deposition process, such as CVD, PECVD, PVD, plating, thermal or e-beam evaporation, or sputtering. A planarization process, such as CMP, is typically performed to remove all conductive material from the surface of the semiconductor structure 100.

[0055] As can be seen in FIG. 10B, according to one embodiment, the top S / D contact 1012 has a positive tapering profile (i.e., the top critical dimension (CD) is smaller than the bottom CD), while the bottom S / D contact 1014 and the gate contact 1016 have a negative tapering profile (top CD is larger than the bottom CD). As known to those skilled in the art, tapering includes a gradual thinning or narrowing towards one end. In the case of the top S / D contact 1012 having a positive tapering angle towards the top S / D region 202, the thinning occurs in the direction away from the (epitaxial) top S / D region 202, while the widening occurs in the direction towards the top S / D region 202. In the case of bottom S / D contact 1014 and gate contact 1016 with negative tapering angles, thinning occurs towards the (epitaxial) bottom S / D region 106 and the high-k metal gate stack 120, respectively. Different contact tapering profiles can help to avoid very small separations occurring at the same location (e.g., if all contacts are negatively tapered, the top CD is the largest, increasing the risk of contact shorting at the top S / D).

[0056] According to one embodiment, the top S / D contact 1012 is formed circumferentially around the top S / D region 202. In other words, the above steps allow the conductive material forming the top S / D contact 1012 to surround or encircle a large surface of the top S / D region 202 (including the sidewalls and bottom region of the S / D epi surface).

[0057] Note that a portion of the protective liner 502 remains in direct contact with the bottom portion of the top S / D region 202. Specifically, the protective liner 502 remains at the interface between the bottom portion of the top S / D region 202, the upper surface of the top spacer 126 adjacent the top S / D region 202, and the portion of the second ILD layer 802 located between two consecutive top S / D regions 202. As seen in FIG. 10B, the remaining portions of the protective liner 502 are disposed on opposing bottom sides (indicated by the annular regions) of the top S / D regions 202, and by performing this over-etching of the first ILD layer 124 between adjacent top S / D regions 202, the top S / D region 202 is not exposed, thus avoiding contact shorting and improving device reliability.

[0058] The description of various embodiments of the present invention has been presented for the purpose of illustration, but is not exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used in this specification has been selected to best explain the principles of the embodiments, practical applications or technical improvements to the technology found in the market, or to enable other skilled in the art to understand the embodiments disclosed herein.

[0059] In a preferred embodiment of the present invention, there is provided herein a method of forming a semiconductor structure, the method including forming a top source / drain region in contact with an upper surface of a channel fin extending vertically from a bottom source / drain region located above a substrate, wherein a top spacer separates the top source / drain region from a high-k metal gate stack located around the channel fin, the channel fin and the top spacer in contact with an adjacent first interlayer dielectric layer located immediately above the bottom source / drain region; recessing the first interlayer dielectric layer to expose a top portion of the top source / drain region and a top portion of the top spacer adjacent the top source / drain region; selectively removing the exposed top portion of the top spacer to expose a bottom portion of the top source / drain region; and conformally depositing a protective liner over the top source / drain region and in direct contact with the top source / drain region. Preferably, the method further comprises depositing a sacrificial material over the protective liner, depositing an organic planarization layer over the sacrificial material, and recessing a top portion of the organic planarization layer, the sacrificial material, the protective liner, and the first interlayer dielectric layer. A portion of the protective liner preferably remains at an interface between a bottom portion of the top source / drain region, a top spacer adjacent the top source / drain region, and a second dielectric material between two consecutive top source / drain regions. The recessing creates a first recess with a positive tapering angle widening in a direction toward the top source / drain region and a second recess with a negative tapering angle narrowing in a direction toward the high-k metal gate stack and in a direction toward the bottom source / drain region. The method preferably further comprises forming a top source / drain contact in the first recess with a positive tapering angle, the top source / drain contact surrounding a surface of the top source / drain region. The method preferably further includes forming a bottom source / drain contact in at least one of the second recesses that narrow in a direction toward the bottom source / drain region.The method preferably further includes forming a gate contact in at least one of the plurality of second recesses having a negative tapering angle narrowing in a direction toward the high-k metal gate stack. The protective liner preferably includes titanium nitride. Recessing the first interlevel dielectric layer is preferably performed using a highly selective blanket atomic layer etch.

Claims

1. forming a first recessed region in a semiconductor structure, the first recessed region defining the first opening having a first positive tapering profile that widens the first opening in a direction toward a top source / drain region of the semiconductor structure at a first tapering angle as at least a portion of the first positive tapering profile; forming a top source / drain contact in the first opening, the top source / drain contact surrounding a surface of the top source / drain region; Including, forming a protective liner in direct contact with the bottom portion of the top source / drain region at an interface between the bottom portion of the top source / drain region, a top spacer adjacent to the top source / drain region, and a second dielectric material between two successive top source / drain regions; Further comprising: A method for forming a semiconductor structure.

2. forming a second recessed region including a second opening having a first negative tapering profile, the first negative tapering profile including a second tapering angle that narrows in a direction toward a bottom source / drain region of the semiconductor structure; forming a bottom source / drain contact in the second recessed region; The method of claim 1 further comprising:

3. forming a third recessed region including a third opening having a second negative tapering profile, the second negative tapering profile including a third tapering angle that narrows in a direction toward the high-k metal gate stack; forming a gate contact in the third recessed region; and The method of claim 1 further comprising:

4. forming the protective liner in direct contact with the bottom portion of the top source / drain region; recessing the first interlevel dielectric layer to expose a top portion of the top source / drain region and a top portion of the top spacer adjacent the top source / drain region; selectively removing the exposed top portion of the top spacer; conformally depositing the protective liner over and in direct contact with the top source / drain regions; The method of claim 1 further comprising:

5. 5. The method of claim 4, wherein recessing the first interlevel dielectric layer is performed using a highly selective blanket atomic layer etch.

6. depositing a sacrificial material above the protective liner; depositing an organic planarization layer over the sacrificial material; recessing a top portion of the organic planarization layer, the sacrificial material, the protective liner, and a first interlayer dielectric layer, the recessing creating a plurality of recesses having different tapering profiles for contact formation; The method of claim 1 further comprising:

7. The method of claim 1 , wherein the protective liner comprises titanium nitride.

8. 1. A semiconductor structure comprising: a first region having a first positive tapering profile, the first positive tapering profile including a first tapering angle diverging in a direction toward a top source / drain region of the semiconductor structure; a top source / drain contact in the first region, the top source / drain contact surrounding a surface of the top source / drain region; Equipped with a protective liner in direct contact with the bottom portion of the top source / drain region at an interface between the bottom portion of the top source / drain region, a top spacer adjacent the top source / drain region, and a second dielectric material located between two successive top source / drain regions. Further comprising: Semiconductor structure.

9. a second region having a first negative tapering profile, the first negative tapering profile including a second tapering angle that narrows in a direction toward a bottom source / drain region of the semiconductor structure; a bottom source / drain contact in the second region; and 10. The semiconductor structure of claim 8 further comprising:

10. a third region having a second negative tapering profile, the second negative tapering profile including a third tapering angle that narrows in a direction toward the high-k metal gate stack; a gate contact in the third region; and 10. The semiconductor structure of claim 8 further comprising:

11. 9. The semiconductor structure of claim 8 wherein said protective liner comprises titanium nitride.

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