Semiconductor device and electronic device

Abstract

To provide a semiconductor device that can hold data for a long time.SOLUTION: A semiconductor device includes a storage circuit including a first transistor, and a voltage holding circuit including a second transistor and a capacitor. The first transistor includes a gate and a back gate. The capacitor includes a first electrode, a second electrode, and a ferroelectric layer. The ferroelectric layer is provided between the first electrode and the second electrode. One of the first electrode or the second electrode is electrically connected to a gate of the second transistor. The other of the first electrode or the second electrode is electrically connected to a wire that applies voltage to inversely polarize the ferroelectric layer. The other of the source or the drain of the second transistor is electrically connected to a the back gate of the first transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an object, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manufacture, or a composition of matter. Another aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, or a driving method or manufacturing method thereof. In particular, one aspect of the present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor.

[0002] In this specification and the like, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. Display devices, electro-optical devices, semiconductor circuits, and electronic devices may include semiconductor devices. [Background technology]

[0003] Technology for constructing transistors using semiconductor materials has been attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor materials that can be used for transistors, but oxide semiconductors have also attracted attention as other materials.

[0004] Patent Document 1 discloses an example in which a transistor having an oxide semiconductor in a channel formation region (hereinafter referred to as an "oxide semiconductor transistor") is used in a dynamic random access memory (DRAM). Since an oxide semiconductor transistor has a very small leakage current (off current) in an off state, it is possible to manufacture a DRAM with a long refresh period and low power consumption.

[0005] Moreover, Patent Document 2 discloses a nonvolatile memory using an oxide semiconductor transistor. Unlike flash memories, these nonvolatile memories have no limit to the number of times they can be rewritten, can easily achieve high-speed operation, and consume little power.

[0006] Furthermore, Patent Document 2 discloses an example in which a second gate is provided in an oxide semiconductor transistor to control the threshold voltage of the transistor and reduce the off-state current of the transistor.

[0007] Moreover, Patent Documents 2 and 3 disclose examples of the configuration of a circuit for driving the above-mentioned second gate. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2013-168631 A [Patent Document 2] JP 2012-069932 A [Patent Document 3] JP 2012-146965 A Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to provide a storage device capable of retaining data for a long period of time.An object of one embodiment of the present invention is to provide a storage device capable of reducing power consumption.An object of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long period of time.An object of one embodiment of the present invention is to provide a semiconductor device capable of reducing power consumption.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0010] The description of multiple problems does not preclude the existence of each problem. Note that one embodiment of the present invention does not need to solve all of these problems. In addition, problems other than those listed will become apparent from the description of the specification, drawings, claims, etc., and these problems may also be problems of one embodiment of the present invention. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a memory circuit having a first transistor and a voltage holding circuit having a second transistor and a capacitor, the first transistor having a gate and a back gate, the capacitor having a first electrode, a second electrode, and a ferroelectric layer, the ferroelectric layer being provided between the first electrode and the second electrode, one of the first electrode or the second electrode being electrically connected to a gate of the second transistor, the other of the first electrode or the second electrode being electrically connected to a terminal that applies a voltage that inverts the polarization of the ferroelectric layer, and one of the source or drain of the second transistor being electrically connected to the back gate of the first transistor.

[0012] One embodiment of the present invention is preferably a semiconductor device including a memory circuit having a first transistor, a voltage holding circuit having a second transistor and a capacitor, and a negative voltage generation circuit, in which the first transistor has a gate and a back gate, the capacitor has a first electrode, a second electrode, and a ferroelectric layer, the ferroelectric layer being provided between the first electrode and the second electrode, one of the first electrode or the second electrode being electrically connected to a gate of the second transistor, the other of the first electrode or the second electrode being electrically connected to a terminal that applies a voltage that inverts the polarization of the ferroelectric layer, one of the source or drain of the second transistor being electrically connected to the back gate of the first transistor, and the other of the source or drain of the second transistor being electrically connected to the negative voltage generation circuit.

[0013] In one embodiment of the present invention, the first transistor and the second transistor are preferably transistors having an oxide semiconductor in a channel.

[0014] In one embodiment of the present invention, the ferroelectric layer preferably has hafnium oxide and / or zirconium oxide.

[0015] One embodiment of the present invention is an electronic device including the above-described semiconductor device.

[0016] Other aspects of the present invention are described in the following "Description of Embodiments of the Invention" and "Drawings." Effect of the Invention

[0017] According to one embodiment of the present invention, it is possible to provide a storage device capable of retaining data for a long period of time. According to one embodiment of the present invention, it is possible to provide a storage device capable of reducing power consumption. According to one embodiment of the present invention, it is possible to provide a semiconductor device capable of retaining data for a long period of time. According to one embodiment of the present invention, it is possible to provide a semiconductor device capable of reducing power consumption. According to one embodiment of the present invention, it is possible to provide a novel semiconductor device.

[0018] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0019] [Figure 1] 1A and 1B are circuit diagrams illustrating an example of a circuit according to one embodiment of the present invention. [Diagram 2] FIG. 2 is a circuit diagram illustrating an example of a circuit according to one embodiment of the present invention. [Diagram 3] Fig. 3A is a diagram showing a configuration example of a memory cell, and Fig. 3B is a diagram showing a configuration example of a memory device. [Figure 4] Fig. 4A is a diagram showing a configuration example of a memory cell, and Fig. 4B is a diagram showing a configuration example of a memory device. [Diagram 5] FIG. 5 is a diagram illustrating an example of a register configuration. [Figure 6] 6A to 6C are diagrams illustrating configuration examples of transistors. [Figure 7]FIG. 7 is a diagram illustrating an example of the configuration of a CPU. [Figure 8] FIG. 8 is a diagram illustrating an example of an electronic device. [Figure 9] Fig. 9(A) is a diagram for explaining a cross-sectional structure of a sample according to an embodiment, Fig. 9(B) is a diagram showing an input voltage waveform, and Fig. 9(C) is a diagram showing a measurement result of the sample according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0021] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be used.

[0022] In addition, in each figure described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0023] (Embodiment 1) In this embodiment, a circuit configuration of a semiconductor device which is one embodiment of the present invention will be described.

[0024] A circuit 100 shown in Fig. 1 shows a circuit configuration of a semiconductor device for driving the second gate of a transistor ME. The semiconductor device shown in Fig. 1 has an input terminal VBG, an input terminal VLS, a memory cell array MCA, a circuit 100 electrically connected to the memory cell array MCA, a negative voltage generating circuit NBG, and a circuit CP. The memory cell array MCA has a plurality of memory cells MC, and each memory cell MC has a transistor M0 having a first and second gate. The transistor M0 can be, for example, a write transistor in the memory cell MC (or a write / read transistor depending on the configuration of the memory cell MC).

[0025] The circuit 100 includes a transistor M1, a capacitor C1, and a capacitor FEC.

[0026] The second gate of the transistor M0 has a function of controlling the threshold voltage (Vth) of the transistor M0. For example, when the transistor M0 is an n-channel transistor, applying a potential lower than the source potential to the second gate of the transistor M0 can shift the Vth of the transistor M0 in the positive direction and reduce the off-current at Vgs=0V (the transistor can be normally off). On the other hand, applying a potential higher than the source potential to the second gate of the transistor M0 can shift the Vth of the transistor M0 in the negative direction and allow an on-current to flow at Vgs=0V (the transistor can be normally on).

[0027] The first gate of the transistor M0 and the second gate of the transistor M0 have an overlapping region with the semiconductor layer therebetween.

[0028] A first gate of the transistor M1 is electrically connected to a first terminal (also referred to as an electrode) of the capacitor FEC. One of a source and a drain of the transistor M1 is electrically connected to an input terminal VBG. The other of the source and the drain of the transistor M1 is electrically connected to a wiring BGL. The input terminal VBG is electrically connected to a negative voltage generating circuit NBG.

[0029] The wiring BGL is electrically connected to the second gates of the multiple transistors M0.

[0030] A first terminal of the capacitor C1 is electrically connected to the other of the source and drain of the transistor M1 and the wiring BGL. A second terminal of the capacitor C1 is electrically connected to the wiring GNL. A constant potential is applied to the wiring GNL. The constant potential may be a ground potential.

[0031] An input terminal VLS is electrically connected to a second terminal (also referred to as an electrode) of the capacitive element FEC. The input terminal VLS is also electrically connected to a circuit CP.

[0032] The transistor M1 is preferably a transistor with a small off-state current. For example, the off-state current of the transistor M1 is preferably 10 -18 A / μm or less, more preferably 10 -21 A / μm or less, more preferably 10 -24 An oxide semiconductor transistor is an example of a transistor with low off-state current.

[0033] In this specification, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and source (Vgs) is lower than Vth for an n-channel transistor, and a state in which Vgs is higher than Vth for a p-channel transistor. For example, the off-state current of an n-channel transistor may refer to the drain current when Vgs is lower than Vth. The off-state current of a transistor may depend on Vgs. Therefore, if the off-state current of a transistor is 10 -21 A or less means that the off-state current of the transistor is 10 -21 It may also mean that there exists a value of Vgs where the off-state current is equal to or less than A. The off-state current of a transistor may refer to the off-state at a specified Vgs, at a Vgs within a specified range, or at a Vgs where a sufficiently reduced off-state current is obtained, etc.

[0034] In this specification, the off-current of a transistor having a channel width (W) may be expressed as a current value flowing per channel width. Alternatively, it may be expressed as a current value flowing per a predetermined channel width (e.g., 1 μm). In the latter case, the unit of the off-current may be expressed in units having the dimension of current / length (e.g., A / μm).

[0035] The off-state current of a transistor may depend on temperature. In this specification, unless otherwise specified, the off-state current may refer to the off-state current at room temperature, 60° C., 85° C., 95° C., or 125° C. Alternatively, the off-state current may refer to the off-state current at a temperature at which the reliability of a semiconductor device or the like including the transistor is guaranteed, or at a temperature at which a semiconductor device or the like including the transistor is used (for example, any one of temperatures from 5° C. to 35° C.).

[0036] The off-current of a transistor may depend on the voltage (Vds) between the drain and the source. In this specification, unless otherwise specified, the off-current may refer to the off-current at an absolute value of Vds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V. Alternatively, the off-current may refer to the Vds at which the reliability of a semiconductor device or the like including the transistor is guaranteed, or the off-current at Vds used in a semiconductor device or the like including the transistor.

[0037] 1A illustrates not only the first gate but also the second gate of the transistor M1, and although the electrical connection destination of the second gate is not specified, the electrical connection destination of the second gate can be determined at the design stage. For example, in a transistor having a second gate, the first gate and the second gate may be electrically connected to each other in order to increase the on-current of the transistor. For example, in a transistor having a second gate, a wiring electrically connected to an external circuit or the like may be provided to change the threshold voltage of the transistor or reduce the off-current of the transistor, and a fixed potential or a variable potential may be applied to the second gate of the transistor by the external circuit or the like.

[0038] The capacitive element FEC is a capacitive element having a material that can have ferroelectricity as a dielectric between two electrodes. In this specification, a capacitor using a material that can have ferroelectricity as a dielectric is called a ferroelectric capacitor.

[0039] Materials that can have ferroelectric properties include hafnium oxide, zirconium oxide, and HfZrO. X (X is a real number greater than 0), materials in which element J (here, element J is silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to hafnium oxide, yttria-stabilized zirconia (YSZ), PbTiO X, barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium tantalate bismuthate (SBT), bismuth ferrite (BFO), barium titanate, etc. Also, as the material, a piezoelectric ceramic having a perovskite structure may be used. Also, as the material, for example, a plurality of materials selected from the materials listed above, or a laminate structure consisting of a plurality of materials selected from the materials listed above, may be used. Incidentally, since the crystal structure (characteristics) of hafnium oxide may change not only depending on the film formation conditions, but also depending on the film configuration above and below, or the process, in this specification, etc., a ferroelectric is not only referred to as a material that exhibits ferroelectricity, but is referred to as a material that can have ferroelectricity or that is made to have ferroelectricity.

[0040] Among them, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferable as a material capable of having ferroelectricity because it can have ferroelectricity even when processed into a thin film of several nm. By forming a ferroelectric layer that can be thinned, it is possible to form a semiconductor device combined with a miniaturized transistor.

[0041] A material that can have ferroelectricity is an insulator, and has the property that polarization occurs inside when an electric field is applied from the outside, and the polarization remains even when the electric field is made zero, so that it can be applied as a non-volatile memory element. Therefore, by using the material as a dielectric sandwiched between a pair of electrodes of a capacitance, the capacitance can be made into a "capacitor that can have ferroelectricity" or a "ferroelectric capacitor". In addition, in this specification, etc., the material that can have ferroelectricity may be said to be between the first terminal and the second terminal of the capacitor. Note that a memory circuit using a capacitor that can have ferroelectricity may be called FeRAM (Ferroelectric Random Access Memory), ferroelectric memory, etc.

[0042] The circuit CP has a function as a voltage generating circuit. For example, the voltage generated by the circuit CP can be a low-level potential, a negative voltage, etc. The voltage generated by the circuit CP is input to a terminal VSL of the circuit 100.

[0043] Here, when a voltage generated by the circuit CP, for example, a low-level potential, is input to the terminal VSL, the low-level potential is applied to the second terminal of the capacitance element FEC. At this time, the potential of the first gate of the transistor M1 drops due to the capacitive coupling of the capacitance element FEC. Also, when the potential difference between the first terminal and the second terminal of the capacitance element FEC reaches a specific potential difference, polarization occurs in the dielectric of the capacitance element FEC, which may have ferroelectricity. By causing polarization in the dielectric of the capacitance element FEC, which may have ferroelectricity, the potential applied to the first gate of the transistor M1 can be held by the capacitance element FEC even if the supply of the low-level potential from the circuit CP to the terminal VSL is stopped.

[0044] The negative voltage generating circuit NBG has a function of generating a negative voltage. The negative voltage generating circuit NBG generates a negative voltage and supplies the negative voltage to the input terminal VBG of the circuit 100.

[0045] Note that the semiconductor device of one embodiment of the present invention is not limited to the circuit configuration in Fig. 1A. The semiconductor device of one embodiment of the present invention may have a configuration in which the circuit configuration in Fig. 1A is changed depending on the situation. For example, the semiconductor device of one embodiment of the present invention may have a configuration in which the capacitor C1 is not provided in the circuit 100 as shown in Fig. 1B.

[0046] 1A, the memory cell MC electrically connected to the wiring BGL is a memory cell MC located in one row of the memory cell array MCA, but one embodiment of the present invention is not limited to this. For example, as shown in FIG. 2, the wiring BGL may be extended to divide the memory cell array MCA into a plurality of rows, and the wiring BGL may be electrically connected to the second gate of each of the transistors M0 of the memory cells MC arranged in a matrix. With this configuration, it is not necessary to provide a circuit 100 for each row, and therefore the circuit area of ​​the semiconductor device can be reduced.

[0047] Next, an operation example of the semiconductor device in FIG.

[0048] In the initial state, the negative voltage generating circuit NBG does not supply a negative voltage to the input terminal VBG. Also, for example, at this time, the negative voltage generating circuit NBG may supply a ground potential to the input terminal VBG.

[0049] In addition, a low-level potential (which may be a negative voltage) is supplied from the circuit CP to the input terminal VLS. L As a result, polarization occurs in the dielectric of the capacitance element FEC, which may have ferroelectricity, and an electric field is generated in the direction from the second terminal to the first terminal of the capacitance element FEC. Furthermore, the first gate of the transistor M1 drops from its original potential due to the capacitive coupling of the capacitance FEC. The dropped potential of the first gate of the transistor M1 is referred to as V G Let us assume that.

[0050] The potential of the first gate of the transistor M1 is V G After this, the supply of the low-level potential from the circuit CP to the input terminal VLS may be stopped.

[0051] Here, a negative voltage is supplied from the negative voltage generating circuit NBG to the input terminal VBG. BG Here, in the transistor M1, V G -V BGWhen is greater than the threshold voltage of transistor M1, transistor M1 is turned on and the negative voltage V BG is supplied to the wiring BGL. Note that the transistor M1 is V G -V BG is smaller than the threshold voltage of transistor M1 and is a negative voltage even in the range where it operates in the subthreshold region. BG can be supplied to the wiring BGL.

[0052] As a result of the above, a negative voltage V BG In addition, the voltage of the wiring BGL is a negative voltage V BG After reaching V, the circuit CP supplies V to the input terminal VLS. L potential (V LL As a result, the potential V of the first gate of the transistor M1 is increased by the capacitive coupling of the capacitor FEC. G At this time, the V LL Even if the supply of the negative voltage V BG can be held in

[0053] Negative voltage V on wire BGL BG By retaining the data written in the memory cell MC, the threshold voltage of the transistor M0 can be lowered. Since the transistor M0 functions as a write transistor for the memory cell MC, the off-leak current of the transistor M0 can be reduced by lowering the threshold voltage of the transistor M0. This allows the data written in the memory cell MC to be retained for a long time.

[0054] The structure described in this embodiment mode can be appropriately combined with structures described in other embodiment modes or examples.

[0055] (Embodiment 2) In this embodiment mode, an application example of a semiconductor device including the circuit 100 described in Embodiment 1 will be described.

[0056] <Non-volatile memory> FIG. 3A shows a circuit configuration of a memory cell MC having a function as a memory element.

[0057] A memory cell MC in FIG. 3A includes a transistor M0 having a first gate and a second gate, a transistor 112, a capacitor 114, a node FN, a wiring BL, a wiring SL, a wiring WL, a wiring RL, and a wiring BGL.

[0058] In the memory cell MC in Figure 3(A), a first gate of the transistor M0 is electrically connected to the wiring WL, a second gate of the transistor M0 is electrically connected to the wiring BGL, one of the source and drain of the transistor M0 is electrically connected to the wiring BL, and the other of the source and drain of the transistor M0 is electrically connected to a node FN.

[0059] In the memory cell MC in Figure 3(A), the gate of the transistor 112 is electrically connected to a node FN, one of the source and the drain of the transistor 112 is electrically connected to a wiring BL, and the other of the source and the drain of the transistor 112 is electrically connected to a wiring SL.

[0060] In the memory cell MC in FIG. 3A, a first terminal of the capacitor 114 is electrically connected to the wiring RL, and a second terminal of the capacitor 114 is electrically connected to a node FN.

[0061] The transistor M0 is preferably a transistor with a small off-state current. For example, the off-state current of the transistor M0 is preferably 10 -18 A / μm or less, more preferably 10 -21 A / μm or less, more preferably 10 -24 An oxide semiconductor transistor is an example of a transistor with low off-state current.

[0062] It is preferable to use a transistor with small variation in threshold voltage as the transistor 112. Here, a transistor with small variation in threshold voltage refers to a transistor that can be formed with an allowable difference in threshold voltage of 100 mV or less when the transistors are manufactured in the same process. Specifically, a transistor whose channel is formed of single crystal silicon can be used.

[0063] The memory cell MC can write, retain, and read information by utilizing the feature that the node FN can retain an electric charge, as described below.

[0064] Writing and holding of data will now be described. First, a potential is applied to the wiring WL so that the transistor M0 is turned on. As a result, the potential of the wiring BL is applied to the node FN. That is, a predetermined charge is applied to the node FN (writing). Here, it is assumed that one of two charges that provide different potential levels (hereinafter referred to as a low level and a high level) is applied. After that, the transistor M0 is turned off, whereby the charge applied to the node FN is held (retained).

[0065] Since the off-state current of the transistor M0 is extremely small, the charge on the gate of the transistor M0 is held for a long time.

[0066] Next, the information reading will be described. When an appropriate potential (read potential) is applied to the wiring RL while a predetermined potential (constant potential) is applied to the wiring SL, the potential of the wiring BL varies according to the amount of charge held in the gate of the transistor 112. Generally, when the transistor 112 is a p-channel type, the apparent threshold value Vth_H when a High level is applied to the node FN is lower than the apparent threshold value Vth_L when a Low level is applied to the node FN. Here, the apparent threshold voltage means the potential of the wiring RL required to turn on the transistor 112. Therefore, by setting the potential of the wiring RL to a potential V0 between Vth_H and Vth_L, the charge applied to the gate of the transistor 112 can be discriminated. For example, in writing, when a Low level is applied, if the potential of the node FN becomes V0 (<Vth_L), the transistor 112 turns on. When a High level is applied, even if the potential of the node FN becomes V0 (>Vth_H), the transistor 112 remains off. Therefore, the held information can be read by discriminating the potential of the wiring BL.

[0067] In the above description, the transistor 112 is treated as a p-channel type transistor, but it is not limited to this, and the transistor 112 may be an n-channel type transistor.

[0068] FIG. 3(B) shows the circuit configuration of the memory device 120 having the memory cells MC arranged in a matrix and the circuit 100 shown in the first embodiment. The memory device 120 has a function as a non-volatile memory.

[0069] The memory device 120 has memory cells MC arranged in an m×n matrix. Here, m and n represent natural numbers of 2 or more. The memory cells MC arranged in the m-th row are electrically connected to the wiring WL[m] and the wiring RL[m], and the memory cells MC arranged in the n-th column are electrically connected to the wiring BL[n] and the wiring SL.

[0070] The second gate of the transistor M0 included in each memory cell MC is electrically connected to the circuit 100 through the wiring BGL. That is, the circuit 100 has a function of supplying a signal that controls the second gate of the transistor M0 included in all memory cells.

[0071] By controlling the second gate of the transistor M0, the circuit 100 allows the transistor M0 to have an appropriate Vth and prevents the transistor M0 from being normally on. As a result, the off-current of the transistor M0 can be reduced and the charge written to the node FN can be held.

[0072] By configuring the storage device 120 as described above, it is possible to provide a storage device that is capable of retaining data for a long period of time even when the power is turned off.

[0073] DRAM FIG. 4A shows a circuit configuration of a memory cell MC having a function as a memory element.

[0074] A memory cell MC in FIG. 4A includes a transistor M0 having a first gate and a second gate, a capacitor 131, a wiring BL, a wiring WL, a wiring CL, and a wiring BGL.

[0075] 4A, a first gate of the transistor M0 is electrically connected to a wiring WL, a second gate of the transistor M0 is electrically connected to a wiring BGL, one of a source and a drain of the transistor M0 is electrically connected to a wiring BL, and the other of the source and drain of the transistor M0 is electrically connected to a first terminal of the capacitor 131. In addition, a second terminal of the capacitor 131 is electrically connected to a wiring CL.

[0076] The transistor M0 is preferably a transistor with a small off-state current. For example, the off-state current of the transistor M0 is preferably 10 -18 A / μm or less, more preferably 10 -21A / μm or less, more preferably 10 -24 An oxide semiconductor transistor is an example of a transistor with low off-state current.

[0077] The wiring WL has a function of supplying a signal that controls the on / off state of the transistor M0, and the wiring BL has a function of writing charge to the capacitor 131 through the transistor M0. After writing charge to the capacitor 131, the transistor M0 is turned off, so that the charge written to the capacitor 131 can be held.

[0078] Since the charge written to the capacitor 131 flows out through the transistor M0, it is necessary to periodically rewrite (refresh) the charge written to the capacitor 131; however, since the off-state current of the transistor M0 is extremely low and the amount of charge flowing out of the capacitor 131 is small, the frequency of refreshing is also low.

[0079] 4B illustrates a circuit configuration of a memory device 140 including the memory cells MC illustrated in FIG. 2A, which are arranged in a matrix, and the circuit 100 illustrated in Embodiment 1. The memory device 140 functions as a DRAM.

[0080] The memory device 140 has memory cells MC arranged in a matrix of m rows and n columns. The memory cell MC arranged in the mth row is electrically connected to a wiring WL[m], and the memory cell MC arranged in the nth column is electrically connected to a wiring BL[n]. The wiring CL is electrically connected to a terminal VC that applies a constant low potential.

[0081] The second gate of the transistor M0 included in each memory cell MC is electrically connected to the circuit 100 through the wiring BGL. That is, the circuit 100 has a function of supplying a signal that controls the second gate of the transistor M0 included in all memory cells.

[0082] The circuit 100 controls the second gate of the transistor M0, which allows the transistor M0 to have an appropriate Vth and prevents the transistor M0 from being normally on. As a result, the off-current of the transistor M0 can be reduced, and the charge written to the capacitance element 131 can be held.

[0083] By configuring the memory device 140 as described above, it is possible to provide a memory device that requires less frequent refreshing and can operate with low power consumption.

[0084] Register FIG. 5 shows an example of the configuration of a 1-bit register circuit 150. As shown in FIG.

[0085] The register circuit 150 includes a transistor M0 having a first gate and a second gate, a capacitor 154, a node N5, and a flip-flop circuit 153.

[0086] The flip-flop circuit 153 has an inverter 151 and an inverter 152. The inverter 151 is connected in parallel to the inverter 152 in the opposite direction.

[0087] The second gate of transistor M0 is electrically connected to circuit 100, the first gate of transistor M0 is electrically connected to the input terminal Sig1, one of the source and drain of transistor M0 is electrically connected to the input terminal Sig2, and the other of the source and drain of transistor M0 is electrically connected to node N5.

[0088] A first terminal of the capacitor 154 is electrically connected to the node N5, and a constant low potential is applied to a second terminal of the capacitor 154. The low potential may be a ground potential. The node N5 is electrically connected to the flip-flop circuit 153.

[0089] The transistor M0 is preferably a transistor with a small off-state current. For example, the off-state current of the transistor M0 is preferably 10 -18 A / μm or less, more preferably 10 -21 A / μm or less, more preferably 10 -24 An oxide semiconductor transistor is an example of a transistor with low off-state current.

[0090] The register circuit 150 stores and outputs data in response to input signals from the input terminals Sig1 and Sig2. For example, when a high-level voltage is supplied to the input terminals Sig1 and Sig2, the transistor M0 is turned on and a high-level voltage is input to the node N5. As a result, a low-level voltage inverted by the inverter 151 is output from the output terminal OUT of the register circuit 150, and at the same time, low-level voltage data is stored in the flip-flop circuit 153. On the other hand, when a low-level voltage is input from the input terminal Sig2, a high-level voltage is similarly output from the output terminal OUT and the high-level voltage data is stored in the flip-flop circuit 153.

[0091] The capacitor 154 has a function of holding the voltage of the node N5.

[0092] By turning off the transistor M0 after writing a potential from the input terminal Sig2 to the node N5, the register circuit 150 can hold the potential of the node N5 even when the supply of the power supply voltage is stopped. This is because the off-current of the transistor M0 is extremely small. In other words, by using the register circuit 150, it is possible to provide a memory device that can hold data even when the supply of the power supply voltage is stopped.

[0093] The circuit 100 also has a function of supplying a signal to control the second gate of the transistor M0. By the circuit 100 controlling the second gate of the transistor M0, the transistor M0 can have an appropriate Vth, and the normally-on state can be prevented. As a result, the off-current of the transistor M0 can be reduced, and the charge written to the node N5 can be held.

[0094] In this embodiment, a simple configuration using two inverter circuits is shown as an example of the flip-flop circuit 153, but the present invention is not limited to this, and a configuration using a clocked inverter capable of clock operation or a configuration combining a NAND circuit and an inverter can be used as appropriate. For example, known flip-flop circuits such as RS type, JK type, D type, and T type can be used as appropriate.

[0095] The structure described in this embodiment mode can be appropriately combined with structures described in other embodiment modes or examples.

[0096] (Embodiment 3) In this embodiment, a structural example of a transistor that can be applied to the semiconductor device described in the above embodiment will be described.

[0097] Fig. 6A is a top view of a transistor 500 which can be used in the semiconductor device described in the above embodiment. Fig. 6B is a cross-sectional view taken along the dashed line L1-L2 in Fig. 6A and is a cross-sectional view of the transistor 500 in the channel length direction. Fig. 6C is a cross-sectional view taken along the dashed line W1-W2 in Fig. 6A and is a cross-sectional view of the transistor 500 in the channel width direction. The transistor 500 can be used as an OS transistor included in the semiconductor device described in the above embodiment, such as the transistor M0.

[0098] 6A to 6C, the transistor 500 can be provided in an insulator 512. The transistor 500 includes a conductor 503 disposed so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 disposed over the insulator 516 and the conductor 503, an insulator 522 disposed over the insulator 520, an insulator 524 disposed over the insulator 522, an oxide 530a disposed over the insulator 524, an oxide 530b disposed over the oxide 530a, conductors 542a and 542b disposed apart from each other on the oxide 530b, an insulator 580 disposed over the conductor 542a and the conductor 542b and having an opening formed therebetween to overlap the conductor 542a and the conductor 542b, an insulator 545 disposed on a bottom surface and a side surface of the opening, and a conductor 560 disposed on a surface on which the insulator 545 is formed.

[0099] 6(A) to 6(C), an insulator 544 is preferably disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. As shown in FIGS. 6(A) to 6(C), the conductor 560 preferably includes a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. As shown in FIGS. 6(A) to 6(C), an insulator 574 is preferably disposed over the insulator 580, the conductor 560, and the insulator 545.

[0100] In this specification and the like, oxide 530a and oxide 530b may be collectively referred to as oxide 530.

[0101] Note that, in the transistor 500, a two-layer structure of the oxide 530a and the oxide 530b is illustrated in the region where a channel is formed and in the vicinity thereof, but the present invention is not limited to this structure. For example, a single layer of the oxide 530b or a stacked structure of three or more layers may be used.

[0102] Although the conductor 560 in the transistor 500 has a two-layer structure, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 illustrated in Figures 6(A) to 6(C) is an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, or the like.

[0103] Here, the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment, so that the area occupied by the transistor 500 can be reduced. This allows the semiconductor device to be miniaturized and highly integrated.

[0104] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. As a result, the switching speed of the transistor 500 can be improved, and high frequency characteristics can be achieved.

[0105] The conductor 560 may function as a first gate (also referred to as a gate or a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a back gate or a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be increased and the off-current can be reduced. Therefore, the drain current when the potential applied to the conductor 560 is 0 V can be reduced by applying a negative potential to the conductor 503 compared to the case where a negative potential is not applied.

[0106] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this manner, when a potential is applied to the conductor 560 and the conductor 503, an electric field generated from the conductor 560 and an electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered.

[0107] In this specification and the like, a transistor configuration in which a channel formation region is electrically surrounded by the electric field of a pair of gate electrodes (a first gate electrode and a second gate electrode) is called a surrounded channel (S-channel) configuration. The S-channel configuration disclosed in this specification and the like is different from a fin type configuration and a planar type configuration. By adopting the S-channel configuration, it is possible to obtain a transistor that is more resistant to the short channel effect, in other words, in which the short channel effect is less likely to occur.

[0108] In addition, the conductor 503 has a conductor 503a formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and a conductor 503b formed further inside. Note that, although the transistor 500 has a structure in which the conductor 503a and the conductor 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0109] Here, the conductor 503a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, copper atoms, etc. (the impurities are less likely to permeate through). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate through). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities or the oxygen.

[0110] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and the conductivity from decreasing.

[0111] In addition, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b is made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that, although the conductor 503 is illustrated in this embodiment as a stack of the conductors 503a and 503b, the conductor 503 may have a single layer structure.

[0112] The insulators 520, 522, and 524 function as a second gate insulating film.

[0113] Here, it is preferable that the insulator 524 in contact with the oxide 530 is an insulator containing more oxygen than the oxygen that satisfies the stoichiometric composition. The oxygen is easily released from the film by heating. In this specification and the like, oxygen released by heating is sometimes referred to as "excess oxygen." In other words, it is preferable that the insulator 524 has a region containing excess oxygen (also referred to as an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen deficiencies (V O In addition, when hydrogen enters an oxygen vacancy in the oxide 530, the defect (hereinafter, V OH.) may function as a donor and generate electrons as carriers. Some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. O In order to obtain an oxide semiconductor in which H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also referred to as "oxygenation treatment"). O When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0114] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating as an insulator having an excess oxygen region. An oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms is 1.0×10 18 atoms / cm 3 More than 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 or more than 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or higher and 700° C. or lower, or 100° C. or higher and 400° C. or lower.

[0115] In addition, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By carrying out such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the bond of VoH, in other words, "V O The reaction "H → Vo + H" occurs, and dehydrogenation can be achieved. Some of the hydrogen generated at this time combines with oxygen to form H 2 As O, hydrogen may be removed from the oxide 530 or from an insulator near the oxide 530. Also, some of the hydrogen may be gettered to the conductor 542a and the conductor 542b.

[0116] Moreover, the microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma, or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator in the vicinity of the oxide 530. The microwave treatment may be performed under a pressure of 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. For example, oxygen and argon are used as gases to be introduced into the apparatus for performing the microwave treatment, and the oxygen flow ratio (O 2 / (O 2 +Ar)) is set to 50% or less, preferably 10% or more and 30% or less.

[0117] In addition, in a manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed at a temperature of, for example, 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. In this way, oxygen is supplied to the oxide 530 to reduce oxygen deficiencies (VO ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in succession to a heat treatment in a nitrogen gas or inert gas atmosphere.

[0118] In addition, by performing an oxygen addition process on the oxide 530, the oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "Vo+O→null" can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530 to convert the hydrogen into H 2 O. This causes the hydrogen remaining in the oxide 530 to recombine with the oxygen vacancies and form V. O The formation of H can be suppressed.

[0119] Furthermore, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).

[0120] The insulator 522 preferably has a function of suppressing diffusion of oxygen or impurities, so that oxygen contained in the oxide 530 does not diffuse toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0121] The insulator 522 may be, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba,Sr)TiO 3It is preferable to use an insulator containing a so-called high-k material such as (BST) in a single layer or a multilayer structure. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0122] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials having a function of suppressing the diffusion of impurities and oxygen (the oxygen is unlikely to permeate through them). As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses release of oxygen from the oxide 530 or the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0123] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0124] In addition, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In addition, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable laminated structure with a high dielectric constant.

[0125] 6A to 6C, the second gate insulating film has a three-layer stack structure including the insulators 520, 522, and 524. However, the second gate insulating film may have a single-layer structure, a two-layer structure, or a four-layer structure or more. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0126] In the transistor 500, a metal oxide functioning as an oxide semiconductor is used for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like) may be used for the oxide 530.

[0127] The metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide functioning as an oxide semiconductor will be described in detail in another embodiment.

[0128] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. In this manner, by using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0129] The oxide 530 has the oxide 530a below the oxide 530b, and thus can suppress the diffusion of impurities from components formed below the oxide 530a to the oxide 530b.

[0130] The oxide 530 preferably has a laminated structure of a plurality of oxide layers having different atomic ratios of metal atoms. Specifically, the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530b. In addition, the atomic ratio of element M to In in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 530b. In addition, the atomic ratio of In to element M in the metal oxide used for the oxide 530b is preferably larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a.

[0131] In addition, it is preferable that the energy of the conduction band minimum of the oxide 530a is higher than that of the oxide 530b, or, in other words, it is preferable that the electron affinity of the oxide 530a is smaller than that of the oxide 530b.

[0132] Here, at the junction between the oxide 530a and the oxide 530b, the energy level of the conduction band minimum changes gradually. In other words, it can be said that the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0133] Specifically, the oxide 530a and the oxide 530b have a common element other than oxygen (as a main component), so that a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a may be an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0134] At this time, the main carrier path is the oxide 530b. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0135] Conductors 542a and 542b functioning as a source electrode and a drain electrode are provided on the oxide 530b. As the conductors 542a and 542b, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, and are therefore preferable.Furthermore, metal nitride films such as tantalum nitride are preferable because they have barrier properties against hydrogen or oxygen.

[0136] 6B, the conductor 542a and the conductor 542b have a single-layer structure, but may have a stacked structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. A titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0137] In addition, there are three-layer structures in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0138] 6B, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in a region between the regions 543a and 543b.

[0139] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0140] The insulator 544 is provided to cover the conductor 542a and the conductor 542b and suppresses oxidation of the conductor 542a and the conductor 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0141] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. In addition, the insulator 544 can also be made of silicon nitride oxide, silicon nitride, or the like.

[0142] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize in a heat treatment in a later process. Note that when the conductor 542a and the conductor 542b are made of a material having oxidation resistance or a material whose conductivity does not decrease significantly even when oxygen is absorbed, the insulator 544 is not an essential component. It may be designed appropriately depending on the desired transistor characteristics.

[0143] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b. The insulator 580 can also prevent the conductor 542a and the conductor 542b from being oxidized by excess oxygen contained in the insulator 580.

[0144] The insulator 545 functions as a first gate insulating film. Like the insulator 524 described above, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0145] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0146] By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to a channel formation region of the oxide 530b. Similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably 1 nm or more and 20 nm or less. The microwave treatment described above may be performed before and / or after the formation of the insulator 545.

[0147] Furthermore, in order to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 545 to the conductor 560 can be suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to the excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 can be used.

[0148] The insulator 545 may have a layered structure, similar to the second gate insulating film. As transistors are miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by making the insulator that functions as the gate insulating film have a layered structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a layered structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0149] The conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 6B and 6C, but may have a single-layer structure or a stacked structure of three or more layers.

[0150] The conductor 560a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N 2 O, NO, NO 2 It is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as copper atoms, etc., etc. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). When the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 560b from being oxidized by the oxygen contained in the insulator 545 and the conductivity from decreasing. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used. In addition, an oxide semiconductor that can be applied to the oxide 530 can be used as the conductor 560a. In that case, the conductor 560b can be formed by a sputtering method to reduce the electrical resistance value of the conductor 560a and make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0151] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material.

[0152] The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or a resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having voids are preferable because they allow for easy formation of an excess oxygen region in a later step.

[0153] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0154] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b. As a result, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0155] In miniaturizing a semiconductor device, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased for that purpose, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580, so that even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0156] The insulator 574 is preferably provided in contact with a top surface of the insulator 580, a top surface of the conductor 560, and a top surface of the insulator 545. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0157] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0158] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as a barrier film against impurities such as hydrogen as well as an oxygen source.

[0159] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524 and the like, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0160] The conductor 540a and the conductor 540b are arranged in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductor 540a and the conductor 540b are provided facing each other with the conductor 560 interposed therebetween.

[0161] The structure described in this embodiment mode can be appropriately combined with structures described in other embodiment modes or examples.

[0162] (Embodiment 4) In this embodiment, a CPU which can use the transistor described in Embodiment 1 and includes the memory device described in Embodiment 2 will be described.

[0163] FIG. 7 is a block diagram showing a configuration of an example of a CPU that uses the transistors described in the above embodiments at least in part.

[0164] The CPU shown in FIG. 7 has an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198 (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F) on a substrate 1190. The substrate 1190 is a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 7 is merely an example in which the configuration is simplified, and an actual CPU has a wide variety of configurations depending on its application. For example, a configuration including the CPU or arithmetic circuit shown in FIG. 7 may be one core, and a configuration including a plurality of such cores may be configured so that each core operates in parallel. Furthermore, the number of bits that the CPU can handle in its internal arithmetic circuit or data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, and the like.

[0165] An instruction input to the CPU via the bus interface 1198 is input to an instruction decoder 1193 , decoded, and then input to an ALU controller 1192 , an interrupt controller 1194 , a register controller 1197 , and a timing controller 1195 .

[0166] The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes interrupt requests from external input / output devices or peripheral circuits based on their priority or mask state while the CPU is executing a program. The register controller 1197 generates an address for the register 1196, and reads or writes to the register 1196 depending on the state of the CPU.

[0167] Furthermore, the timing controller 1195 generates signals that control the timing of the operations of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0168] 7, a memory cell is provided in a register 1196. As the memory cell of the register 1196, the transistor described in Embodiment 1 or the memory device described in Embodiment 2 can be used.

[0169] 7, the register controller 1197 selects the holding operation in the register 1196 according to an instruction from the ALU 1191. That is, it selects whether the data is to be held by a flip-flop or by a capacitive element in the memory cell of the register 1196. When holding data by a flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. When holding data in a capacitive element is selected, data is rewritten to the capacitive element, and the supply of the power supply voltage to the memory cell in the register 1196 can be stopped.

[0170] The structure described in this embodiment mode can be appropriately combined with structures described in other embodiment modes or examples.

[0171] (Embodiment 5) In this embodiment, application examples of a semiconductor device according to one embodiment of the present invention will be described.

[0172] The semiconductor device according to one embodiment of the present invention can be applied to, for example, memory devices of various electronic devices (for example, information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording and playback devices, navigation systems, game consoles, and the like). The semiconductor device can also be used in image sensors, the Internet of Things (IoT), healthcare, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.

[0173] [Extension device for PC] The semiconductor device described in the above embodiment can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0174] Fig. 8(A) shows, as an example of such an expansion device, an expansion device 6100 that is portable and equipped with a chip capable of storing information and that is externally attached to a PC. The expansion device 6100 can store information using the chip by connecting to a PC, for example, via a Universal Serial Bus (USB) or the like. Note that, although Fig. 8(A) shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.

[0175] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with a circuit for driving the semiconductor device or the like described in the above embodiments. For example, an electronic component 4700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0176] [SD card] The semiconductor device described in the above embodiment can be applied to an SD card which can be attached to electronic devices such as an information terminal or a digital camera.

[0177] FIG. 8(B) is a schematic diagram of the appearance of an SD card, and FIG. 8(C) is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a board 5113. The connector 5112 functions as an interface for connecting to an external device. The board 5113 is housed in the housing 5111. The board 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, the board 5113 is provided with an electronic component 4700 and a controller chip 5115. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to the above description, and may be changed as appropriate depending on the situation. For example, a write circuit, a row driver, a read circuit, and the like provided in the electronic component may be incorporated in the controller chip 5115 instead of the electronic component 4700.

[0178] The capacity of the SD card 5110 can be increased by providing the electronic component 4700 also on the back side of the substrate 5113. A wireless chip having a wireless communication function may be provided on the substrate 5113. This enables wireless communication between an external device and the SD card 5110, and allows data to be read and written to the electronic component 4700.

[0179] [SSD] The semiconductor device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

[0180] FIG. 8(D) is a schematic diagram of the appearance of the SSD, and FIG. 8(E) is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a board 5153. The connector 5152 functions as an interface for connecting to an external device. The board 5153 is housed in the housing 5151. The board 5153 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, the board 5153 is provided with an electronic component 4700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing the electronic component 4700 on the back side of the board 5153 as well. A work memory is built into the memory chip 5155. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 is built with a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0181] The structure described in this embodiment mode can be appropriately combined with structures described in other embodiment modes or examples. EXAMPLES

[0182] A film of an insulator exhibiting ferroelectricity was formed, and the change in spontaneous polarization was measured. Figure 9(A) shows a schematic diagram of the cross-sectional structure of sample 800 used in the measurement.

[0183] <Data structure> The sample 800 was formed by using single crystal silicon as the substrate 801. Specifically, a thermal oxide film having a thickness of 100 nm was formed as the insulator 802 on the substrate 801, tungsten (W) having a thickness of 30 nm was formed as the conductor 803a on the insulator 802, and titanium nitride (TiNx) having a thickness of 10 nm was formed as the conductor 803b on the conductor 803a. In addition, hafnium zirconium oxide (HfZrOx) having a thickness of 10 nm was formed as the insulator 804 covering the conductor 803 (the conductor 803a and the conductor 803b).

[0184] Furthermore, titanium nitride (TiNx) was formed to a thickness of 10 nm as conductor 805a in a portion of the region on insulator 804 overlapping with conductor 803, and tungsten (W) was formed to a thickness of 20 nm as conductor 805b on conductor 805a. Silicon oxynitride (SiON) was formed as insulator 806 covering insulator 804 and conductor 805 (conductor 805a and conductor 805b).

[0185] In addition, an electrode 807 electrically connected to the conductor 805 and an electrode 808 electrically connected to the conductor 803 are formed over the insulator 806 .

[0186] <Measurement> A triangular wave with an amplitude of 3 V and a frequency of 100 Hz was applied between the electrode 807 and the conductor 803, and the change in the spontaneous polarization of the insulator 804 was measured. The input voltage waveform is shown in FIG.

[0187] The measurement results are shown in Fig. 9(C). The horizontal axis of Fig. 9(C) indicates the voltage applied between electrode 807 and conductor 803, and the vertical axis indicates the polarization amount of insulator 804. Fig. 9(C) shows that when the polarization amount is positive, positive charges are biased toward one electrode (one of conductor 803 or conductor 805) and negative charges are biased toward the other electrode (the other of conductor 803 or conductor 805). Also, when the polarization amount is negative, it shows that negative charges are biased toward one electrode and positive charges are biased toward the other electrode.

[0188] When the applied voltage is increased after voltage VPI1 is applied between electrode 807 and conductor 803, the amount of polarization increases according to curve 851. On the other hand, when the applied voltage is decreased after voltage VPI2 is applied, the amount of polarization decreases according to curve 852. In other words, it can be seen that when voltage VPI1 or voltage VPI2 is applied to insulator 804, polarization inversion occurs in insulator 804, resulting in hysteresis characteristics.

[0189] From FIG. 9C, it is found that the insulator 804 has hysteresis characteristics and functions as a ferroelectric.

[0190] (Additional Notes Regarding the Description of the Present Specification, etc.) The above embodiment and each configuration in the embodiment will be described below with additional notes.

[0191] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments or examples to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0192] In addition, the content (or a part of the content) described in one embodiment can be applied to, combined with, or replaced by another content (or a part of the content) described in that embodiment, and / or the content (or a part of the content) described in one or more other embodiments.

[0193] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0194] In addition, a figure (or a part of it) described in one embodiment can be combined with another part of that figure, with another figure (or a part of it) described in that embodiment, and / or with a figure (or a part of it) described in one or more other embodiments to form even more figures.

[0195] In addition, in the present specification and the like, in the block diagrams, the components are classified by function and shown as mutually independent blocks. However, in actual circuits and the like, it is difficult to separate the components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and may be rephrased appropriately according to the situation.

[0196] In addition, in the drawings, the size, layer thickness, or region are shown at an arbitrary size for convenience of explanation. Therefore, they are not necessarily limited to the scale. Note that the drawings are shown diagrammatically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0197] In addition, the positional relationship of components shown in the drawings is relative. Therefore, when describing components with reference to the drawings, terms such as "above" and "below" that indicate the positional relationship may be used for convenience. The positional relationship of components is not limited to the contents described in this specification, and can be rephrased appropriately depending on the situation.

[0198] In this specification and the like, when describing the connection relationship of a transistor, the term "one of the source or drain" (or first electrode or first terminal) is used, and the other of the source and drain is used as "the other of the source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. The source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, etc. depending on the situation.

[0199] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" and "wirings" are formed as a single unit.

[0200] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0201] In addition, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage is a potential difference from a reference potential, and if the reference potential is a ground voltage (earth voltage), for example, voltage can be interchanged with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may be changed depending on the reference potential.

[0202] In addition, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0203] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, vacuum, etc.). In addition, the "direction of current" in wiring, etc. is the direction in which positively charged carriers move, and is described as a positive current. In other words, the direction in which negatively charged carriers move is the opposite direction to the direction of current, and is expressed as a negative current. Therefore, in this specification, etc., unless otherwise specified regarding the positive and negative (or current direction) of the current, the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A" etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0204] In this specification, A and B are connected means that A and B are electrically connected. Here, A and B are electrically connected means a connection in which an electrical signal between A and B can be transmitted when an object (an element such as a switch, a transistor element, or a diode, or a circuit including the element and wiring) exists between A and B. Note that when A and B are electrically connected, this includes a case in which A and B are directly connected. Here, A and B are directly connected means a connection in which an electrical signal between A and B can be transmitted through wiring (or electrodes) between A and B without passing through the object. In other words, a direct connection means a connection that can be regarded as the same circuit diagram when expressed as an equivalent circuit.

[0205] In this specification, a switch refers to a device that has a function of controlling whether a current flows or not by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0206] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between the source and drain in a region where a channel is formed.

[0207] In this specification, the channel width refers to, for example, the length of the region where a semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap, or the length of the portion where a source and a drain face each other in a region in which a channel is formed.

[0208] In this specification and the like, the terms "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". [Explanation of symbols]

[0209] C1 Capacitive element L1-L2 part M0 Transistor M1 Transistor N5 Node Sig1 input terminal Sig2 input terminal V0 potential W1-W2 part 3V amplitude 100 circuits 112 Transistor 114 Capacitive element 120 Storage device 131 Capacitive element 140 Storage device 150 Resistor Circuit 151 Inverter 152 Inverter 153 Flip-flop circuit 154 Capacitive element 500 transistors 503 Conductors 503a Conductors 503b Conductor 512 Insulators 514 Insulators 516 Insulators 520 Insulator 522 Insulators 524 Insulators 530 Oxide 530a Oxide 530b Oxide 540a Conductor 540b Conductor 542a Conductor 542b Conductor 543a area 543b area 544 Insulator 545 Insulator 560 Conductors 560a Conductor 560b Conductor 574 Insulators 580 Insulator 581 Insulators 800 samples 801 Substrate 802 Insulator 803 Conductors 803a Conductor 803b Conductor 804 Insulator 805 Conductors 805a Conductor 805b Conductor 806 Insulators 807 Electrode 808 Electrode 851 Curve 852 curve 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 4700 Electronic Components 5110 SD card 5111 Case 5112 Connector 5113 Substrate 5115 Controller Chip 5150 SSD 5151 Case 5152 Connector 5153 Circuit Board 5155 memory chip 5156 controller chip 6100 Expansion Device 6101 Case 6102 Cap 6103 USB Connector 6104 Substrate 6106 Controller Chip

Claims

1. a memory circuit having a first transistor; a voltage holding circuit having a second transistor and a capacitance element; A negative voltage generating circuit having a function of generating a negative voltage, the first transistor has a gate and a back gate; the capacitance element includes a first electrode, a second electrode, and a ferroelectric layer; the ferroelectric layer is provided between the first electrode and the second electrode, one of the first electrode and the second electrode is electrically connected to a gate of the second transistor; the other of the first electrode and the second electrode is electrically connected to a terminal for applying a first negative voltage that inverts the polarization of the ferroelectric layer; one of a source and a drain of the second transistor is electrically connected to a back gate of the first transistor; the other of the source and the drain of the second transistor is electrically connected to the negative voltage generating circuit, supplying the first negative voltage to the terminal to invert the polarization of the ferroelectric layer, and then supplying a second negative voltage to the other of the source or drain of the second transistor to turn the second transistor on; a second negative voltage supplying portion that supplies a second negative voltage to a back gate of the first transistor via the second transistor, and then the second transistor is turned off, thereby holding the second negative voltage in the back gate of the first transistor.

2. 2 . The semiconductor device according to claim 1 , wherein the first transistor and the second transistor are transistors having an oxide semiconductor in a channel.

3. 3. The semiconductor device according to claim 1, wherein the ferroelectric layer comprises hafnium oxide and / or zirconium oxide.

4. 4. An electronic device comprising the semiconductor device according to claim 1.

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