Three-dimensional (3D) memory devices and methods

Abstract

[0006] Embodiments of a 3D memory device and methods of forming the same are disclosed. In one example, the 3D memory device includes a memory stack including alternating stacked conductive layers and stacked dielectric layers, a semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and into the semiconductor layer, and an insulating structure extending vertically through the memory stack and including a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods for manufacturing the same. [Background technology]

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as memory cell feature sizes approach lower limits, planar processes and manufacturing techniques become difficult and expensive. As a result, the memory density of planar memory cells approaches an upper limit.

[0003] 3D memory structures can address the density limitations of planar memory cells and include peripheral devices that control signals to and from the memory array. Summary of the Invention

[0004] SUMMARY OF THE DISCLOSURE Disclosed herein are embodiments of 3D memory devices and methods for forming the same. [Means for solving the problem]

[0005] In one example, a 3D memory device includes a memory stack including alternating stacked conductive layers and stacked dielectric layers, a semiconductor layer, a number of channel structures each extending vertically through the memory stack and into the semiconductor layer, and an insulating structure extending vertically through the memory stack and including a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.

[0006] In another example, a 3D memory device includes a memory stack including alternating stacked conductive layers and stacked dielectric layers, a semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and into the semiconductor layer, and an insulating structure extending vertically through the memory stack and including a dielectric layer, each channel structure including a memory film and a semiconductor channel doped with at least one of hydrogen or an isotope of hydrogen.

[0007] In yet another example, a method for forming a 3D memory device is disclosed. A channel structure is formed that extends vertically through a memory stack in a semiconductor layer on a substrate. The memory stack includes alternating stacked conductive layers and stacked dielectric layers. An insulating structure is formed in an opening that extends vertically through the memory stack and includes a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen. [Brief description of the drawings]

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the disclosure and, together with the description, further serve to enable those skilled in the art to make and use the disclosure. [Figure 1A] 1 illustrates a cross-sectional side view of an exemplary 3D memory device having a hydrogen-rich semiconducting channel in accordance with some embodiments of the present disclosure. [Figure 1B] FIG. 2 illustrates a cross-sectional side view of another exemplary 3D memory device having a hydrogen-rich semiconducting channel, in accordance with some embodiments of the present disclosure. [Figure 2A] 1A-1B show cross-sectional side views of various exemplary hydrogen-rich insulating structures in the 3D memory device of FIG. 1A or FIG. 1B according to various embodiments of the present disclosure. [Figure 2B] 1A-1B show cross-sectional side views of various exemplary hydrogen-rich insulating structures in the 3D memory device of FIG. 1A or FIG. 1B according to various embodiments of the present disclosure. [Figure 2C]1A-1B show cross-sectional side views of various exemplary hydrogen-rich insulating structures in the 3D memory device of FIG. 1A or FIG. 1B according to various embodiments of the present disclosure. [Figure 2D] 1A-1B show cross-sectional side views of various exemplary hydrogen-rich insulating structures in the 3D memory device of FIG. 1A or FIG. 1B according to various embodiments of the present disclosure. [Figure 2E] 1A-1B show cross-sectional side views of various exemplary hydrogen-rich insulating structures in the 3D memory device of FIG. 1A or FIG. 1B according to various embodiments of the present disclosure. [Figure 2F] 1A-1B show cross-sectional side views of various exemplary hydrogen-rich insulating structures in the 3D memory device of FIG. 1A or FIG. 1B according to various embodiments of the present disclosure. [Figure 2G] 1A-1B show cross-sectional side views of various exemplary hydrogen-rich insulating structures in the 3D memory device of FIG. 1A or FIG. 1B according to various embodiments of the present disclosure. [Figure 2H] 1A-1B show cross-sectional side views of various exemplary hydrogen-rich insulating structures in the 3D memory device of FIG. 1A or FIG. 1B according to various embodiments of the present disclosure. [Figure 3A] 1 illustrates a fabrication process for forming an exemplary 3D memory device having a hydrogen-rich semiconducting channel according to some embodiments of the present disclosure. [Figure 3B] 1 illustrates a fabrication process for forming an exemplary 3D memory device having a hydrogen-rich semiconducting channel according to some embodiments of the present disclosure. [Figure 3C] 1 illustrates a fabrication process for forming an exemplary 3D memory device having a hydrogen-rich semiconducting channel according to some embodiments of the present disclosure. [Figure 3D] 1 illustrates a fabrication process for forming an exemplary 3D memory device having a hydrogen-rich semiconducting channel according to some embodiments of the present disclosure. [Figure 3E] 1 illustrates a fabrication process for forming an exemplary 3D memory device having a hydrogen-rich semiconducting channel according to some embodiments of the present disclosure. [Figure 3F]1 illustrates a fabrication process for forming an exemplary 3D memory device having a hydrogen-rich semiconducting channel according to some embodiments of the present disclosure. [Figure 3G] 1 illustrates a fabrication process for forming an exemplary 3D memory device having a hydrogen-rich semiconducting channel according to some embodiments of the present disclosure. [Figure 3H] 1 illustrates a fabrication process for forming an exemplary 3D memory device having a hydrogen-rich semiconducting channel according to some embodiments of the present disclosure. [Figure 3I] 1 illustrates a fabrication process for forming an exemplary 3D memory device having a hydrogen-rich semiconducting channel according to some embodiments of the present disclosure. [Figure 3J] 1 illustrates a fabrication process for forming an exemplary 3D memory device having a hydrogen-rich semiconducting channel according to some embodiments of the present disclosure. [Figure 3K] 1 illustrates a fabrication process for forming an exemplary 3D memory device having a hydrogen-rich semiconducting channel according to some embodiments of the present disclosure. [Figure 3L] 1 illustrates a fabrication process for forming an exemplary 3D memory device having a hydrogen-rich semiconducting channel according to some embodiments of the present disclosure. [Figure 3M] 1 illustrates a fabrication process for forming an exemplary 3D memory device having a hydrogen-rich semiconducting channel according to some embodiments of the present disclosure. [Figure 4] 1 illustrates a flowchart of a method for forming an exemplary 3D memory device having a hydrogen-rich semiconductor channel according to some embodiments of the present disclosure.

[0009] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will also be apparent to those skilled in the art that the present disclosure can be used in a variety of other applications.

[0011] References herein to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," and the like, should be noted as indicating that, although the described embodiment may include a particular feature, structure, or characteristic, not all embodiments necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of one of ordinary skill in the art to achieve such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0012] Generally, terminology may be understood at least in part from use in context. For example, the term "one or more" as used herein may be used in a singular sense to describe any feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may also be understood to convey singular or plural usage, depending at least in part on the context. Furthermore, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but instead may allow for the existence of additional factors not necessarily explicitly described, depending at least in part on the context.

[0013] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure are to be interpreted in their broadest manner, whereby "on" not only means "directly on" something, but can also include the meaning "on" something with intermediate features or layers between them, and "above" or "over" not only means "above" or "over" something, but can also include the meaning "above" or "over" something (i.e., directly on top of something) without intermediate features or layers between them.

[0014] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to facilitate describing the relative relationship of one element or feature to another element or feature as shown in the figures. This spatially relative terminology is intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be oriented in other directions (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0015] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or left unpatterned. Additionally, the substrate may include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0016] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend throughout an underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. Furthermore, a layer may be a uniform continuous structure, or a region of a non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be located in any pair of horizontal planes between a continuous structure, at the top and bottom surfaces of a continuous structure. A layer may extend along horizontal, vertical, and / or tapered surfaces. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0017] As used herein, the term "nominal" refers to a desired or target value of a characteristic or parameter of a component or process operation, as set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "about" refers to a value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of interest. Based on a particular technology node, the term "about" may refer to a value of a given quantity that varies within a range of, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0018] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings", such as NAND memory strings) on a laterally oriented substrate such that the memory strings extend vertically relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to the sides of the substrate.

[0019] When manufacturing some 3D memory devices, more thin films (e.g., silicon oxide, silicon nitride, polysilicon, etc.) need to be deposited on the silicon substrate as the level of memory cells increases. For example, in 3D NAND memory devices, more thin films need to fill the staircase region, the core array region, and the gate line slits, which may cause thin film deformation, especially when the thin film structure becomes more complex after thermal processes. The stress caused by thin film deformation may further cause deformation of the whole wafer (e.g., wafer curvature) and reduce the production yield.

[0020] In addition, 3D NAND memory devices typically use polysilicon as the material of the semiconductor channel. However, polysilicon may have defects between grain boundaries and at interfaces (e.g., between the semiconductor channel and the tunnel layer), which may affect the performance of the memory cell. For example, dangling bonds may be found at the interfaces, which may attract carriers and reduce the carrier mobility in the semiconductor channel. The dangling bonds may also affect the grain size of the polysilicon and increase the internal stress of the polysilicon semiconductor channel.

[0021] Various embodiments according to the present disclosure provide a 3D memory device having a hydrogen-rich semiconductor channel for improving cell performance and adjusting wafer stress. Hydrogen and its isotopes, such as protium, deuterium, or tritium, can form stable H-Si covalent bonds to reduce the number of dangling bonds in the polysilicon semiconductor channel, thereby improving carrier mobility and adjusting internal stress. In some embodiments, the 3D memory device includes a hydrogen-rich insulating structure, for example, by depositing a dielectric layer (e.g., silicon nitride) doped with hydrogen or at least one of its isotopes in the gate line slit. During a subsequent thermal process, hydrogen or its isotopes can diffuse from the hydrogen-rich insulating structure into the polysilicon semiconductor channel to form a hydrogen-rich semiconductor channel, thereby hardening defects in the polysilicon and adjusting wafer stress. As a result, memory cell performance can be improved and manufacturing yield can be improved.

[0022] FIG. 1A illustrates a cross-sectional side view of an exemplary 3D memory device 100 having a hydrogen-rich semiconductor channel, according to some embodiments of the present disclosure. In some embodiments, the 3D memory device 100 is a junction chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked above the first semiconductor structure 102. According to some embodiments, the first and second semiconductor structures 102 and 104 are coupled at a junction interface 106 therebetween. As shown in FIG. 1A, the first semiconductor structure 102 can include a substrate 101, which can include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0023] The first semiconductor structure 102 of the 3D memory device 100 may include peripheral circuitry 108 on the substrate 101. Note that x, y, and z axes are included in FIG. 1A to illustrate the spatial relationships of the components in the 3D memory device 100. The substrate 101 includes two sides extending laterally in the xy plane: a front surface on the front side of the wafer and a back surface on the back side opposite the front side of the wafer. The x and y directions are two orthogonal directions in the wafer plane, with the x direction being the word line direction and the y direction being the bit line direction. The z axis is perpendicular to both the x and y axes. As used herein, whether one component (e.g., layer or device) is "on," "above," or "below" another component (e.g., layer or device) of a semiconductor device (e.g., 3D memory device 100) is determined in the z-direction (i.e., perpendicular to the xy plane) relative to the substrate of the semiconductor device (e.g., substrate 101) when the substrate is positioned on the z-direction bottom-most surface of the semiconductor device. The same concepts for describing spatial relationships apply throughout this disclosure.

[0024] In some embodiments, the peripheral circuits 108 are configured to control and sense the 3D memory device 100. The peripheral circuits 108 can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to facilitate operation of the 3D memory device 100, including, but not limited to, page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits 108 can include transistors formed on the substrate 101, in which all or a portion of the transistors are formed directly within (e.g., below the top surface of) and / or on the substrate 101. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the transistors) can also be formed in the substrate 101. According to some embodiments, the transistors are of advanced logic processes (e.g., technology nodes such as 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, etc.) and are fast. It will be appreciated that in some embodiments, the peripheral circuitry 108 may further include any other circuitry compatible with advanced logic processes, including processors and logic circuits such as programmable logic devices (PLDs), or memory circuits such as static random access memories (SRAMs).

[0025] In some embodiments, the first semiconductor structure 102 of the 3D memory device 100 further includes an interconnect layer (not shown) above the peripheral circuitry 108 to transfer electrical signals to and from the peripheral circuitry 108. The interconnect layer may include a plurality of interconnects (also referred to herein as "contacts") including lateral interconnect lines and vertical interconnect access (VIA) contacts. As used herein, the term "interconnect" may broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects, and back-end-of-line (BEOL) interconnects. The interconnect layer may further include one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers") in which the interconnect lines and VIA contacts may be formed. That is, the interconnect layer may include interconnect lines and VIA contacts in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer may comprise a conductive material, including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layers in the interconnect layer may comprise a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectric, or any combination thereof.

[0026] As shown in FIG. 1A, the first semiconductor structure 102 of the 3D memory device 100 may further include a bonding layer 110 above the interconnect layer and the peripheral circuitry 108 at the bonding interface 106. The bonding layer 110 may include a plurality of bonding contacts 111 and a dielectric that electrically insulates the bonding contacts 111. The bonding contacts 111 may include a conductive material, including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. The remaining regions of the bonding layer 110 may be formed of a dielectric, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 111 and the surrounding dielectric within the bonding layer 110 may be used for hybrid bonding.

[0027] Similarly, as shown in FIG. 1A, the second semiconductor structure 104 of the 3D memory device 100 can also include a bonding layer 112 above the bonding interface 106 and the bonding layer 110 of the first semiconductor structure 102. The bonding layer 112 can include a plurality of bonding contacts 113 and a dielectric that electrically insulates the bonding contacts 113. The bonding contacts 113 can include a conductive material, including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. The remaining region of the bonding layer 112 can be formed of a dielectric, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 113 and the surrounding dielectric within the bonding layer 112 can be used for hybrid bonding. According to some embodiments, the bonding contacts 113 contact the bonding contacts 111 at the bonding interface 106.

[0028] As described in more detail below, the second semiconductor structure 104 can be bonded on top of the first semiconductor structure 102 in a face-to-face manner at the bonding interface 106. In some embodiments, the bonding interface 106 is disposed between the bonding layers 110 and 112 as a result of a hybrid bond (also known as a "metal / dielectric hybrid bond"). This is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as a solder or adhesive) where a metal-metal bond and a dielectric-dielectric bond can be achieved simultaneously. In some embodiments, the bonding interface 106 is where the bonding layers 112 and 110 come into contact and are bonded. In practice, the bonding interface 106 can be a layer having a certain thickness, including the top surface of the bonding layer 110 of the first semiconductor structure 102 and the bottom surface of the bonding layer 112 of the second semiconductor structure 104.

[0029] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes an interconnect layer (not shown) above the bonding layer 112 to transfer electrical signals. The interconnect layer can include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which the interconnect lines and VIA contacts can be formed. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials, including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0030] In some embodiments, the 3D memory device 100 is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As shown in FIG. 1A, the second semiconductor structure 104 of the 3D memory device 100 can include an array of channel structures 124 that function as an array of NAND memory strings. As shown in FIG. 1A, each channel structure 124 can extend vertically through multiple pairs, each including a stacked conductive layer 116 and a stacked dielectric layer 118. The interleaved stacked conductive layers 116 and stacked dielectric layers 118 are part of a memory stack 114. The number of pairs of stacked conductive layers 116 and stacked dielectric layers 118 in the memory stack 114 (e.g., 32, 64, 96, 128, 160, 192, 224, 256, or more) determines the number of memory cells in the 3D memory device 100. It will be appreciated that in some embodiments, the memory stack 114 may have a multi-deck structure (not shown) that includes multiple memory decks stacked on top of each other. The number of pairs of stacked conductive layers 116 and stacked dielectric layers 118 in each memory deck may be the same or different.

[0031] The memory stack 114 may include a plurality of interleaved stack conductive layers 116 and stack dielectric layers 118. The stack conductive layers 116 and stack dielectric layers 118 in the memory stack 114 may be vertically interleaved. In other words, except for the one at the top or bottom of the memory stack 114, each stack conductive layer 116 may be adjacent to two stack dielectric layers 118 on both sides, and each stack dielectric layer 118 may be adjacent to two stack conductive layers 116 on both sides. The stack conductive layers 116 may include conductive materials, including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each stack conductive layer 116 may include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer. The gate electrode of the stack conductive layer 116 may extend laterally as a word line and terminate at one or more staircase structures of the memory stack 114. The stack dielectric layer 118 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0032] As shown in FIG. 1A, the second semiconductor structure 104 of the 3D memory device 100 can also include a first semiconductor layer 120 above the memory stack 114 and a second semiconductor layer 122 above and in contact with the first semiconductor layer 120. In some embodiments, each of the first semiconductor layer 120 and the second semiconductor layer 122 is an N-type doped semiconductor layer, e.g., a silicon layer doped with an N-type dopant, such as phosphorus (P) or arsenic (As). In these cases, the first semiconductor layer 120 and the second semiconductor layer 122 can be collectively viewed as an N-type doped semiconductor layer 120 / 122 above the memory stack 114. In some embodiments, each of the first semiconductor layer 120 and the second semiconductor layer 122 includes an N-well. That is, each of the first semiconductor layer 120 and the second semiconductor layer 122 can be a region in a P-type substrate doped with an N-type dopant, such as P or As. It is understood that the doping concentrations of the first semiconductor layer 120 and the second semiconductor layer 122 may be the same or different. According to some embodiments, the first semiconductor layer 120 comprises polysilicon, e.g., N-type doped polysilicon. As will be described in more detail below, the first semiconductor layer 120 may be formed by thin film deposition and / or epitaxial growth above a P-type silicon substrate. In contrast, according to some embodiments, the second semiconductor layer 122 comprises single crystal silicon, e.g., N-type doped single crystal silicon. As will be described in more detail below, the second semiconductor layer 122 may be formed by implanting an N-type dopant into a P-type silicon substrate having single crystal silicon.

[0033] In some embodiments, each channel structure 124 includes a channel hole filled with a semiconductor layer (e.g., semiconductor channel 128) and a composite dielectric layer (e.g., memory film 126). In some embodiments, semiconductor channel 128 includes silicon, such as amorphous silicon, polysilicon, or single crystal silicon. For example, semiconductor channel 128 can include polysilicon, and in some embodiments, memory film 126 is a composite layer including a tunnel layer, a storage layer (also known as a "charge trapping layer"), and a blocking layer. The remaining space of channel structure 124 can be partially or completely filled with a cap layer including a dielectric material, such as silicon oxide, and / or voids. Channel structure 124 can have a cylindrical shape (e.g., pillar shape). According to some embodiments, the cap layer, semiconductor channel 128, tunnel layer, storage layer, and blocking layer of memory film 126 are arranged in this order radially from the center of the pillar toward the outer surface. The tunnel layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the memory film 126 may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0034] In some embodiments, the channel structure 124 further includes a channel plug 129 at a bottom (e.g., lower end) of the channel structure 124. As used herein, the "top" of a component (e.g., channel structure 124) is the end farther from the substrate 101 in the z-direction when the substrate 101 is located at the bottom-most surface of the 3D memory device 100, and the "bottom" of a component (e.g., channel structure 124) is the end closer to the substrate 101 in the z-direction. The channel plug 129 can include a semiconductor material (e.g., polysilicon). In some embodiments, the channel plug 129 functions as a drain of a NAND memory string.

[0035] As shown in FIG. 1A, each channel structure 124 can extend vertically through the interleaved stack conductive layers 116, stack dielectric layers 118, and first semiconductor layer 120, e.g., an N-type doped semi-polysilicon layer, of the memory stack 114. In some embodiments, the first semiconductor layer 120 surrounds a portion of the channel structure 124 and is in contact with a semiconductor channel 128 comprising polysilicon. That is, according to some embodiments, the memory film 126 is cut in a portion of the channel structure 124 abutting the first semiconductor layer 120, exposing the semiconductor channel 128 in contact with the surrounding first semiconductor layer 120. As a result, the first semiconductor layer 120 surrounding and in contact with the semiconductor channel 128 can function as a "sidewall semiconductor plug" of the channel structure 124.

[0036] In some embodiments, each channel structure 124 can further extend vertically into the second semiconductor layer 122, e.g., an N-type doped single crystal silicon layer. That is, according to some embodiments, each channel structure 124 extends vertically through the memory stack 114 into the N-type doped semiconductor layer (including the first semiconductor layer 120 and the second semiconductor layer 122). As shown in FIG. 1A, according to some embodiments, the top (e.g., upper end) of the channel structure 124 is in the second semiconductor layer 122. In some embodiments, each of the first semiconductor layer 120 and the second semiconductor layer 122 is an N-type doped semiconductor layer, e.g., an N-well, to enable GIDL-assisted body bias for erase operations. The GIDL around the source select gate of the NAND memory string can generate hole current in the NAND memory string to raise the body potential for the erase operation.

[0037] It is understood that the first semiconductor layer 120 and the second semiconductor layer 122 show one example of a semiconductor layer that can be used in the 3D memory device 100. In a more general case, the second semiconductor structure 104 of the 3D memory device 100 can include a semiconductor layer having one or more doped silicon layers, such as a doped polysilicon layer and / or a doped monocrystalline silicon layer. Furthermore, the number of doped silicon layers in the semiconductor layer and the doping type of each silicon layer in the semiconductor layer are not limited by the example above with respect to FIG. 1A and may vary in other examples. It is also understood that the relative position of the channel structure 124 with respect to the semiconductor layer is not limited by the example above with respect to FIG. 1A and may vary in other examples. In a more general case, each channel structure 124 may extend vertically into the semiconductor layer through the memory stack 114, regardless of the relative position of the end of the channel structure 124 with respect to each doped silicon layer in the semiconductor layer. It is further understood that the erase operation performed by the 3D memory device 100 is not limited to GIDL erase in the above example with respect to FIG. 1A, but may be a P-well bulk erase operation, or any other suitable erase operation based on different configurations of the semiconductor layer, e.g., the doping type of each doped silicon layer within the semiconductor layer.

[0038] Compared to known 3D memory devices having polysilicon semiconductor channels with defects (e.g., dangling bonds) between grain boundaries and at interfaces with the tunnel layer, the 3D memory device 100 can include a hydrogen-rich polysilicon semiconductor channel 128 in each channel structure 124 with fewer defects (e.g., dangling bonds). In some embodiments, the semiconductor channel 128 is doped with at least one of hydrogen or an isotope of hydrogen, such as protium, deuterium, tritium, hydrogen-4 (tetratium), hydrogen-5 (pentetium), and the like. The hydrogen or an isotope thereof can form stable H-Si covalent bonds with the dangling bonds between grain boundaries and at interfaces with the tunnel layer to reduce the number of dangling bonds, thereby improving carrier mobility and adjusting the stress of the semiconductor channel 128.

[0039] As shown in FIG. 1A, the second semiconductor structure 104 of the 3D memory device 100 can further include insulating structures 130 each extending vertically through the interleaved stack conductive layers 116 and stack dielectric layers 118 of the memory stack 114. According to some embodiments, unlike the channel structures 124 that extend further through the first semiconductor layer 120, the insulating structures 130 stop at the first semiconductor layer 120, i.e., do not extend vertically into the N-type doped semiconductor layer. That is, the top surface of the insulating structures 130 can be flush with the bottom surface of the first semiconductor layer 120. Each insulating structure 130 can also extend laterally to separate the channel structures 124 into multiple blocks. That is, the memory stack 114 can be divided into multiple memory blocks by the insulating structures 130, thereby separating the array of channel structures 124 into each memory block. It will be appreciated that the relative position of the insulating structure 130 with respect to the semiconductor layer is not limited by the example given above with respect to Figure 1A and may vary in other examples. For example, the insulating structure 130 may extend further into the semiconductor layer.

[0040] In some embodiments, according to some embodiments, the insulating structures 130 do not include any contacts therein (i.e., not functioning as source contacts), and therefore do not result in parasitic capacitance and leakage current with the conductive layer 116 (including the word lines). In some embodiments, each insulating structure 130 includes an opening (e.g., a slit) filled with one or more dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. As shown in FIG. 1A, the insulating structures 130 can include a dielectric layer 160 doped with at least one of hydrogen or an isotope of hydrogen, such as protium, deuterium, tritium, hydrogen-4 (tetratium), hydrogen-5 (pentetium), and the like. That is, the 3D memory device 100 can include the hydrogen-rich insulating structure 130 as a source for providing hydrogen or an isotope thereof to the semiconductor channel 128, as described in detail below with respect to the manufacturing process of the 3D memory device 100.

[0041] In some embodiments, the atomic percentage of hydrogen or at least one isotope of hydrogen in dielectric layer 160 is about 50% or less, e.g., 50% or less. In some embodiments, the atomic percentage of hydrogen or at least one isotope of hydrogen in dielectric layer 160 is about 0.1% to about 50%, e.g., 0.1% to 50% (e.g., 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, any range bounded by a lower end by any of these values, or any range defined by any two of these values). In one example, the atomic percentage of hydrogen or at least one isotope of hydrogen in the dielectric layer 160 can be about 1% to about 10%, such as 1% to 10% (e.g., 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, any range bounded at the lower end by any of these values, or any range defined by any two of these values). The dielectric layer 160 can include any dielectric material capable of absorbing hydrogen or its isotopes, such as tetraethyl orthosilicate (TEOS) or silicon nitride. In some embodiments, the dielectric layer 160 includes silicon nitride, which has a strong hydrogen absorption capability.

[0042] It is understood that the structure of the hydrogen-rich insulating structure 130 is not limited to the example shown in FIG. 1A. FIGS. 2A to 2H show cross-sectional side views of various exemplary hydrogen-rich insulating structures 130 in the 3D memory device 100 of FIG. 1A according to various embodiments of the present disclosure. As shown in FIG. 2A, in some embodiments, the insulating structure 130 includes a first silicon oxide layer 202, a dielectric layer 160, and a second silicon oxide layer 204. The first silicon oxide layer 202 can be laterally disposed between the dielectric layer 160 and the stack conductive layer 116 of the memory stack 114. In some embodiments, the first silicon oxide layer 202 is disposed along the sidewalls and bottom surface of the insulating structure 130 and contacts the stack conductive layer 116 of the memory stack 114. As described above, the dielectric layer 160, such as a silicon nitride layer, can be doped with at least one of hydrogen or an isotope of hydrogen. In some embodiments, the dielectric layer 160 is disposed on the first silicon oxide layer 202, for example along the sidewalls and bottom surface of the insulating structure 130. The second silicon oxide layer 204 can fill the remaining space of the insulating structure 130 with or without voids therein. In some embodiments, the dielectric layer 160 is disposed laterally between the first silicon oxide layer 202 and the second silicon oxide layer 204. In some embodiments, one end of the insulating structure 130 is coplanar with the respective ends of the dielectric layer 160. For example, the bottom end of the insulating structure 130 may be coplanar with the bottom end of the dielectric layer 160. As shown in FIG. 2A, the bottom ends of the first and second silicon oxide layers 202, 204 and the dielectric layer 160 are coplanar, i.e., in the same plane, at the bottom end of the insulating structure 130.

[0043] In some embodiments, one end of the insulating structure 130 is not flush with the respective end of the dielectric layer 160, but instead includes a silicon oxide cap 208 at that end. As shown in FIG. 2B, unlike the example shown in FIG. 2A, the insulating structure 130 can include a silicon oxide cap 208 at its bottom end. In some embodiments, the silicon oxide cap 208 is disposed below the bottom end of the dielectric layer 160 and is connected to the first and second silicon oxide layers 202 and 204. As a result, the silicon oxide cap 208 can prevent hydrogen or its isotopes from diffusing from the bottom end of the insulating structure 130, thereby reducing the amount of hydrogen or its isotopes that can diffuse laterally through the sidewalls of the insulating structure 130 into the channel structure 124.

[0044] In some embodiments, the insulating structure 130 does not include the second silicon oxide layer 204. As shown in FIGS. 2C and 2D, the dielectric layer 160, with or without voids therein, can fill the remaining space of the insulating structure 130, for example, replacing the second silicon oxide layer 204 shown in FIGS. 2A and 2B. Similar to FIGS. 2A and 2B, the insulating structure 130 may or may not include a silicon oxide cap 208 at its bottom end. Compared to the embodiment of FIGS. 2A and 2B, the dielectric layer 160 in FIGS. 2C and 2D can have a larger volume of dielectric material, such as silicon nitride, to absorb more hydrogen or its isotopes. Furthermore, the stress of the insulating structure 130 can also be adjusted by changing the material filling the remaining space of the insulating structure 130, for example, from silicon oxide to silicon nitride, which can further adjust the wafer stress as needed.

[0045] In some embodiments, the insulating structure 130 does not include the first and second silicon oxide layers 202 and 204. As shown in FIGS. 2E and 2F, the dielectric layer 160 can fill the space of the insulating structure 130 with or without voids therein, for example, replacing both the first silicon oxide layer 202 and the second silicon oxide layer 204 as shown in FIGS. 2A and 2B. That is, the dielectric layer 160 can contact the stack conductive layer 116 of the memory stack 114. Similar to FIGS. 2A and 2B, the insulating structure 130 may or may not include a silicon oxide cap 208 at its bottom end. Compared to the embodiment of FIGS. 2A and 2B, the dielectric layer 160 of FIGS. 2E and 2F can have a larger volume of dielectric material, such as silicon nitride, to absorb more hydrogen or its isotopes. Furthermore, the stress of the insulating structure 130 can also be adjusted by changing the material filling the space of the insulating structure 130, for example, from silicon oxide to silicon nitride, which can further adjust the wafer stress as needed.

[0046] In some embodiments, the insulating structure 130 does not include the second silicon oxide layer 204, but instead includes a polysilicon layer 210 that replaces the second silicon oxide layer 204. As shown in Figures 2G and 2H, the polysilicon layer 210 can fill the remaining space of the insulating structure 130, with or without voids therein, for example replacing the second silicon oxide layer 204 of Figures 2A and 2B. In some embodiments, the dielectric layer 160 is laterally disposed between the first silicon oxide layer 202 and the polysilicon layer 210. As in Figures 2A and 2B, the insulating structure 130 may or may not include a silicon oxide cap 208 at its bottom end. The stress of the insulating structure 130 can also be adjusted by changing the material that fills the remaining space of the insulating structure 130, for example from silicon oxide to polysilicon, which can further adjust the wafer stress as needed.

[0047] It is understood that the structure of the insulating structure 130 may be further varied in other examples, for example, by changing the material filling the remaining space of the insulating structure 130, the number of layers of the insulating structure 130, etc., to adjust the amount of hydrogen or its isotopes that may be absorbed by the dielectric layer 160 and / or to adjust the stress of the insulating structure 130 as needed. It is also understood that the insulating structure 130 may include additional layers, such as the high-k dielectric layer 206 shown in Figures 2A-2H. The high-k dielectric layer 206 may extend from the gate dielectric layer of the stack conductive layer 116.

[0048] Referring back to FIG. 1A, the 3D memory device 100 may include a backside source contact 132 above the memory stack 114 and in contact with the second semiconductor layer 122. The source contact 132 and the memory stack 114 (and the insulating structure 130 therethrough) may be located on either side of the semiconductor layer (e.g., a thinned substrate) and may therefore be considered a "backside" source contact. In some embodiments, the source contact 132 extends further into the second semiconductor layer 122 and is electrically connected to the first semiconductor layer 120 and the semiconductor channel 128 of the channel structure 124 through the second semiconductor layer 122. It is understood that the depth to which the source contact 132 extends into the second semiconductor layer 122 may vary in different examples. In some embodiments in which the second semiconductor layer 122 includes an N-well, the source contact 132 is also referred to herein as an "N-well pick-up." The source contact 132 may include any suitable type of contact. In some embodiments, the source contact 132 includes a VIA contact. In some embodiments, the source contact 132 includes a laterally extending wall-like contact. The source contact 132 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesion layer (e.g., titanium nitride (TiN)).

[0049] As shown in FIG. 1A, the 3D memory device 100 may further include a BEOL interconnect layer 133 above and in contact with source contacts 132 for signal output pads, for example, that transfer electrical signals between the 3D memory device 100 and an external circuit. In some embodiments, the interconnect layer 133 includes one or more ILD layers 134 on the second semiconductor layer 122, and a redistribution layer 136 on the ILD layer 134. According to some embodiments, the top ends of the source contacts 132 are flush with the top surface of the ILD layer 134 and the bottom surface of the redistribution layer 136, and the source contacts 132 extend vertically through the ILD layer 134 into the second semiconductor layer 122. The ILD layer 134 in the interconnect layer 133 may include a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The redistribution layer 136 in the interconnect layer 133 may include a conductive material, including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In some embodiments, the interconnect layer 133 further includes a passivation layer 138 as an outermost layer for passivation and protection of the 3D memory device 100. A portion of the redistribution layer 136 may be exposed from the passivation layer 138 as a contact pad 140. That is, the interconnect layer 133 of the 3D memory device 100 may also include contact pads 140 for wire bonding and / or bonding with an interposer.

[0050] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes contacts 142 and 144 that extend through the second semiconductor layer 122. The second semiconductor layer 122 may be a thinned substrate, for example an N-well of a P-type silicon substrate, so that according to some embodiments, the contacts 142 and 144 are through-silicon contacts. In some embodiments, the contact 142 extends through the second semiconductor layer 122 and the ILD layer 134 and contacts the redistribution layer 136, such that the first semiconductor layer 120 is electrically connected to the contact 142 through the second semiconductor layer 122, the source contact 132, and the interconnect layer 133 and the redistribution layer 136. In some embodiments, the contact 144 extends through the second semiconductor layer 122 and the ILD layer 134 to contact the contact pad 140. Each of the contacts 142 and 144 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesion layer (e.g., TiN). In some embodiments, at least the contact 144 further includes a spacer (e.g., a dielectric layer) to electrically isolate the contact 144 from the second semiconductor layer 122.

[0051] In some embodiments, the 3D memory device 100 further includes peripheral contacts 146 and 148, each extending vertically to the second semiconductor layer 122 (e.g., an N-well of a P-type silicon substrate) outside the memory stack 114. Each peripheral contact 146 or 148 can have a depth greater than the depth of the memory stack 114, such that it extends vertically from the bonding layer 112 to the second semiconductor layer 122 in a peripheral region outside the memory stack 114. In some embodiments, the peripheral contact 146 underlies and contacts the contact 142, such that the first semiconductor layer 120 is electrically connected to the peripheral circuitry 108 in the first semiconductor structure 102 via at least the second semiconductor layer 122, the source contact 132, the interconnect layer 133, the contact 142, and the peripheral contact 146. In some embodiments, the peripheral contacts 148 underlie and contact the contacts 144, such that the peripheral circuitry 108 in the first semiconductor structure 102 is electrically connected to the contact pads 140 for signal output pads via at least the contacts 144 and the peripheral contacts 148. The peripheral contacts 146 and 148 may each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesion layer (e.g., TiN).

[0052] As shown in FIG. 1A, the 3D memory device 100 also includes various local contacts (also known as “C1”) as part of the interconnect structure that directly contact structures in the memory stack 114. In some embodiments, the local contacts include channel local contacts 150 that underlie and contact the bottom ends of the respective channel structures 124. Each channel local contact 150 can be electrically connected to a bit line contact (not shown) for bit line fan-out. In some embodiments, the local contacts further include word line local contacts 152 that underlie and contact the respective conductive layers 116 (including word lines) in the staircase structure of the memory stack 114 for word line fan-out. The local contacts, such as the channel local contacts 150 and the word line local contacts 152, can be electrically connected to the peripheral circuitry 108 of the first semiconductor structure 102 through at least the bonding layers 112 and 110. Local contacts, such as channel local contact 150 and word line local contact 152, can each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesion layer (e.g., TiN).

[0053] FIG. 1B illustrates a cross-sectional side view of another exemplary 3D memory device 103 having a hydrogen-rich semiconductor channel according to some embodiments of the present disclosure. According to some embodiments, the 3D memory device 103 is similar to the 3D memory device 103, except that the backside source contact 132 in the 3D memory device 100 is replaced with a frontside source contact 162 in the 3D memory device 100. As shown in FIG. 1B, the source contact 162 can be in contact with a semiconductor layer (e.g., the second semiconductor layer 122), and the source contact 162 and the insulating structure 130 can be disposed on the same side of the semiconductor layer, e.g., the front side. It will be understood that for ease of explanation, details of other identical structures in both the 3D memory devices 103 and 100 will not be repeated.

[0054] 3A-3M illustrate a fabrication process for forming an exemplary 3D memory device having a hydrogen-rich semiconductor channel according to some embodiments of the present disclosure. FIG. 4 illustrates a flow chart of a method for forming an exemplary 3D memory device having a hydrogen-rich semiconductor channel according to some embodiments of the present disclosure. Examples of 3D memory devices are illustrated in FIGS. 3A-3M and 4, including 3D memory devices 100 and 103 illustrated in FIGS. 1A and 1B. FIGS. 3A-3M and 4 are described in conjunction with each other. It will be understood that the steps illustrated in method 400 are not exhaustive and that other steps may be performed before, after, or between any of the illustrated steps. Additionally, some of the steps may be performed simultaneously or in a different order than that illustrated in FIG. 4.

[0055] Referring to FIG. 4, the method 400 begins at step 402, where peripheral circuits are formed on a first substrate. The first substrate can be a silicon substrate. As shown in FIG. 3I, a plurality of transistors are formed on the silicon substrate 350 using a plurality of processes, including, but not limited to, photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions (not shown) are formed in the silicon substrate 350, for example, by ion implantation and / or thermal diffusion, which function as source and / or drain regions of the transistors. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 350 by wet and / or dry etching and thin film deposition. The transistors can form peripheral circuits 352 on the silicon substrate 350.

[0056] As shown in FIG. 3I, a bonding layer 348 is formed over the peripheral circuitry 352. The bonding layer 348 includes a bonding contact electrically connected to the peripheral circuitry 352. To form the bonding layer 348, an ILD layer is deposited using one or more thin film deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Bond contacts are formed through the ILD layer using wet and / or dry etching, e.g., RIE, followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0057] The method 400 continues at step 404, as shown in Figure 4, where a first semiconductor layer is sequentially formed on the second substrate, a sacrificial layer on the first semiconductor layer, and a dielectric stack on the sacrificial layer. The dielectric stack may include alternating stack sacrificial layers and stack dielectric layers. In some embodiments, polysilicon is deposited on the second semiconductor layer to form a sacrificial layer, and stack dielectric layers and stack sacrificial layers are alternately deposited on the sacrificial layer to form the dielectric stack, to subsequently form the sacrificial layer and the dielectric stack.

[0058] 3A, an N-type doped semiconductor layer 304 is formed on a silicon substrate 302. The N-type doped semiconductor layer 304 may comprise an N-well in a P-type silicon substrate 302 and may comprise single crystal silicon. The N-type doped semiconductor layer 304 may be formed by doping the P-type silicon substrate 302 with an N-type dopant, such as P or As, using ion implantation and / or thermal diffusion.

[0059] As shown in FIG. 3A, a sacrificial layer 306 is formed on the N-type doped semiconductor layer 304. The sacrificial layer 306 may be formed by depositing polysilicon or any other suitable sacrificial material (e.g., silicon nitride, carbon) that can be subsequently selectively removed using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, a pad oxide layer 305 is formed between the sacrificial layer 306 and the N-type doped semiconductor layer 304 by depositing a dielectric material, such as silicon oxide, on the silicon substrate 302 prior to the formation of the N-type doped semiconductor layer 304, or by thermal oxidation.

[0060] As shown in FIG. 3A, a dielectric stack 308 including multiple pairs of a first dielectric layer (herein referred to as “stack sacrificial layers” 312) and a second dielectric layer (herein referred to as “stack dielectric layers” 310, together referred to herein as “dielectric layer pairs”) is formed on the sacrificial layer 306. According to some embodiments, the dielectric stack 308 includes alternating stack sacrificial layers 312 and stack dielectric layers 310. The stack dielectric layers 310 and the stack sacrificial layers 312 can be alternately deposited on the sacrificial layer 306 above the silicon substrate 302 to form the dielectric stack 308. In some embodiments, each stack dielectric layer 310 includes a layer of silicon oxide and each stack sacrificial layer 312 includes a layer of silicon nitride. The dielectric stack 308 can be formed by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. As shown in FIG. 3A, a staircase structure can be formed on the edge of the dielectric stack 308. The staircase structure can be formed by performing multiple so-called "trim etch" cycles on the dielectric layer pairs of the dielectric stack 308 towards the silicon substrate 302. Due to the repeated trim etch cycles applied to the dielectric layer pairs of the dielectric stack 308, the dielectric stack 308 can have one or more sloping edges and a top dielectric layer pair that is shorter than the bottom, as shown in FIG.

[0061] The method 400 proceeds to step 406, as shown in Figure 4, where a channel structure is formed that extends vertically through the dielectric stack and the sacrificial layer into the first semiconductor layer. In some embodiments, to form the channel structure, a channel hole is formed that extends vertically through the dielectric stack and the sacrificial layer into the first semiconductor layer, a memory film and a semiconductor channel are sequentially formed on a sidewall of the channel hole, and a channel plug is formed above and in contact with the semiconductor channel. The semiconductor channel may include polysilicon.

[0062] As shown in FIG. 3A, the channel hole is an opening that extends vertically through the dielectric stack 308 and the sacrificial layer 306 into the N-type doped semiconductor layer 304. In some embodiments, multiple openings are formed, such that each opening becomes a location for growing an individual channel structure 314 in a later process. In some embodiments, the fabrication process for forming the channel hole of the channel structure 314 includes wet etching, such as deep ion reactive etching (DRIE), and / or dry etching. In some embodiments, the channel hole of the channel structure 314 extends further through the top of the N-type doped semiconductor layer 304. The etching process through the dielectric stack 308 and the sacrificial layer 306 can continue to etch a portion of the N-type doped semiconductor layer 304. In some embodiments, a separate etching process is used to etch a portion of the N-type doped semiconductor layer 304 after etching through the dielectric stack 308 and the sacrificial layer 306.

[0063] As shown in FIG. 3A, a memory film 316 including a blocking layer, a storage layer, and a tunnel layer, and a semiconductor channel 318 are formed in this order along the sidewall and bottom surface of the channel hole. In some embodiments, the memory film 316 is first deposited along the sidewall and bottom surface of the channel hole, and then the semiconductor channel 318 is deposited on the memory film 316. The blocking layer, the storage layer, and the tunnel layer can then be deposited in this order to form the memory film 316 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. The semiconductor channel 318 can then be formed by depositing a semiconductor material, such as polysilicon, on the tunnel layer of the memory film 316 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer ("SONO" structure) are sequentially deposited to form the memory film 316 and the semiconductor channel 318.

[0064] As shown in FIG. 3A, a cap layer is formed in the channel hole and above the semiconductor channel 318 to completely or partially fill the channel hole (e.g., with or without voids). The cap layer can be formed by depositing a dielectric material, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. A channel plug can then be formed at the top of the channel hole. In some embodiments, the memory film 316, the semiconductor channel 318, and a portion of the cap layer on the top surface of the dielectric stack 308 are removed and planarized by CMP, wet etching, and / or dry etching. A recess can then be formed at the top of the channel hole by wet and / or dry etching a portion of the semiconductor channel 318 and the cap layer at the top of the channel hole. A channel plug can then be formed by depositing a semiconductor material, such as polysilicon, in the recess by one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. This forms a channel structure 314 in the N-type doped semiconductor layer 304 through the dielectric stack 308 and the sacrificial layer 306 .

[0065] The method 400 continues at step 408, as shown in FIG. 4, where an opening is formed that extends vertically through the dielectric stack, for example, to expose a portion of the sacrificial layer. As shown in FIG. 3A, the slit 320 is an opening that extends vertically through the dielectric stack 308 and exposes a portion of the sacrificial layer 306. In some embodiments, the fabrication process for forming the slit 320 includes wet etching, such as DRIE, and / or dry etching. In some embodiments, the slit 320 extends further into the top of the sacrificial layer 306. The etching process through the dielectric stack 308 may not stop at the top surface of the sacrificial layer 306 and may continue to etch away a portion of the sacrificial layer 306.

[0066] The method 400 proceeds to step 410, as shown in FIG. 4, where the sacrificial layer is replaced with a second semiconductor layer through the opening. As shown in FIG. 3B, the sacrificial layer 306 (shown in FIG. 3A) is removed by wet etching and / or dry etching to form a cavity 322. In some embodiments, the sacrificial layer 306 is wet etched by applying a wet etchant through the slit 320, which may be stopped by the pad oxide layer 305 between the sacrificial layer 306 and the N-type doped semiconductor layer 304. That is, according to some embodiments, the removal of the sacrificial layer 306 does not affect the N-type doped semiconductor layer 304. In some embodiments, prior to removing the sacrificial layer 306, a spacer 324 is formed along the sidewall of the slit 320. The spacer 324 may be formed by depositing a dielectric material, such as silicon nitride, silicon oxide, and silicon nitride, into the slit 320 using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof.

[0067] As shown in FIG. 3C, a portion of the memory film 316 of the channel structure 314 exposed in the cavity 322 is removed to expose a portion of the semiconductor channel 318 of the channel structure 314 abutting the cavity 322. In some embodiments, the blocking layer (e.g., including silicon oxide), the storage layer (e.g., including silicon nitride), and the tunnel layer (e.g., including silicon oxide) are etched by applying an etchant, such as, for example, phosphoric acid for etching silicon nitride and hydrofluoric acid for etching silicon oxide, through the slit 320 and the cavity 322. The etching can be stopped by the semiconductor channel 318 of the channel structure 314. The spacer 324 including a dielectric material (shown in FIG. 3B) can also protect the dielectric stack 308 from etching the memory film 316 and can be removed by the etchant in the same step as removing the portion of the memory film 316. Similarly, the pad oxide layer 305 (shown in FIG. 3B) on the N-type doped semiconductor layer 304 can also be removed by a process similar to removing the portion of the memory film 316.

[0068] As shown in FIG. 3D, the N-type doped semiconductor layer 326 is formed above and in contact with the N-type doped semiconductor layer 304. In some embodiments, the N-type doped semiconductor layer 326 is formed by depositing polysilicon through the slit 320 into the cavity 322 (shown in FIG. 3C) using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. In some embodiments, in-situ doping of an N-type dopant, such as P or As, is performed when depositing the polysilicon to form an N-type doped polysilicon layer as the N-type doped semiconductor layer 326. The N-type doped semiconductor layer 326 can fill the cavity 322 to contact the exposed portion of the semiconductor channel 318 of the channel structure 314.

[0069] The method 400 proceeds to step 412, as shown in FIG. 4, where the dielectric stack is replaced with the memory stack, for example using a so-called "gate replacement" process, such that a channel structure extends vertically through the memory stack and the first semiconductor layer into the second semiconductor layer. In some embodiments, to replace the dielectric stack with the memory stack, the stack sacrificial layer is replaced with a stack conductive layer through an opening. In some embodiments, the memory stack includes alternating stack conductive layers and stack dielectric layers. According to some embodiments, a channel structure is thereby formed that extends vertically through the memory stack into the semiconductor layer on the second substrate.

[0070] As shown in FIG. 3E, the stack sacrificial layer 312 (shown in FIG. 3A) is replaced with the stack conductive layer 328, thereby forming a memory stack 330 including the interleaved stack conductive layer 328 and stack dielectric layer 310, replacing the dielectric stack 308 (shown in FIG. 3A). In some embodiments, a lateral recess (not shown) is first formed by removing the stack sacrificial layer 312 through the slit 320. In some embodiments, the stack sacrificial layer 312 is removed by applying an etchant through the slit 320 to form an interleaved lateral recess between the stack dielectric layer 310. The etchant may include any suitable etchant that etches the stack sacrificial layer 312 selective to the stack dielectric layer 310. As shown in FIG. 3E, the stack conductive layer 328 (including the gate electrode and the adhesion layer) is deposited in the lateral recess through the slit 320. In some embodiments, the gate dielectric layer 332 is deposited in the lateral recess before the stack conductive layer 328, thereby depositing the stack conductive layer 328 on the gate dielectric layer. A stack conductive layer 328, such as a metal layer, may be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a gate dielectric layer 332, such as a high-k dielectric layer, is also formed at the bottom of the slit 320 along the sidewalls. According to some embodiments, a channel structure 314 is thereby formed that extends vertically through the memory stack 330 and into the semiconductor layers (including the N-type doped semiconductor layers 304 and 306) on the silicon substrate 302.

[0071] The method 400 proceeds to step 414, as shown in FIG. 4, where an insulating structure is formed in the opening, the insulating structure extending vertically through the memory stack. The insulating structure may include a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen. In some embodiments, a first layer of silicon oxide, a dielectric layer, and a second layer of silicon oxide are sequentially formed in the opening to form the insulating structure. In some embodiments, a layer of silicon oxide, a dielectric layer, and a layer of polysilicon are sequentially formed in the opening to form the insulating structure. In some embodiments, a layer of silicon oxide and a dielectric layer are sequentially formed in the opening to form the insulating structure. In some embodiments, a layer of silicon nitride is deposited to form the dielectric layer, and the layer of silicon nitride is in situ doped with hydrogen or at least one isotope of hydrogen. In some embodiments, a layer of silicon nitride is deposited to form the dielectric layer, and the layer of silicon nitride is annealed in the presence of hydrogen or at least one isotope of hydrogen after deposition to form the dielectric layer. In some embodiments, a silicon oxide cap is formed on top of the insulating structure to form the insulating structure. In some embodiments, to form a silicon oxide cap, at least the top portion of the dielectric layer is etched back to form a recess, and a layer of silicon oxide is deposited to fill the recess.

[0072] As shown in FIG. 3F, an insulating structure 336 is formed, extending vertically through the memory stack 330 and stopping at the top surface of the N-type doped semiconductor layer 326. The insulating structure 336 can include a dielectric layer 334 doped with at least one of hydrogen or an isotope of hydrogen, such as protium, deuterium, tritium, hydrogen-4 (tetratium), hydrogen-5 (pentetium), etc. Referring to FIG. 2A and FIG. 2B, the insulating structure 130 (e.g., insulating structure 336 in FIG. 3F) can be formed by sequentially depositing the first silicon oxide layer 202, the dielectric layer 160 (e.g., dielectric layer 334 in FIG. 3F), and the second silicon oxide layer 204 in the slit 320 to completely or partially fill the slit 320 (with or without a void) using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. 2C and 2D, the first silicon oxide layer 202 and the dielectric layer 160 (e.g., the dielectric layer 334 in FIG. 3F) can be sequentially deposited in the slit 320 to completely or partially fill the slit 320 (with or without a void) to form the insulating structure 130 (e.g., the insulating structure 336 in FIG. 3F) using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. With reference to FIGS. 2E and 2F, the dielectric layer 160 (e.g., the dielectric layer 334 in FIG. 3F) can be sequentially deposited in the slit 320 to completely or partially fill the slit 320 (with or without a void) to form the insulating structure 130 (e.g., the insulating structure 336 in FIG. 3F) using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.2G and 2H, one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, can be used to sequentially deposit a first silicon oxide layer 202, a dielectric layer 160 (e.g., dielectric layer 334 of FIG. 3F), and a polysilicon layer 210 into the slit 320 to completely or partially fill the slit 320 (with or without voids) to form an insulating structure 130 (e.g., insulating structure 336 of FIG. 3F).

[0073] In some embodiments, a silicon nitride layer is deposited on the first silicon oxide layer 202 along the sidewalls and bottom surface of the slit 320 to form the dielectric layer 160 (e.g., the dielectric layer 334 in FIG. 3F) (e.g., FIGS. 2A-2D, 2G, and 2J). In one example, hydrogen or an isotope thereof may be in situ doped into the silicon nitride layer during deposition, such as by CVD. In another example, after depositing the silicon nitride layer, the silicon nitride layer may be annealed in the presence of hydrogen or an isotope thereof, for example, with hydrogen gas flowing through a furnace chamber. In some embodiments, the atomic percentage of the doped hydrogen or an isotope thereof in the dielectric layer 160 is controlled to be greater than about 50% after the formation of the dielectric layer 160.

[0074] 2B, 2D, 2F, and 2H, in some embodiments, a silicon oxide cap 208 is formed at one end of the insulating structure 130. The silicon oxide cap 208 can be formed by first etching back the top of at least the dielectric layer 160 (and in various examples, one or more of the first silicon oxide layer 202, the second silicon oxide layer 204, and the polysilicon layer 210) to form a recess, and depositing a layer of silicon oxide to fill the recess. In some embodiments, a CMP process is performed to planarize the top surface of the silicon oxide layer and form the silicon oxide cap 208. Referring back to FIG. 3F, an insulating structure 336 including a dielectric layer 334 doped with hydrogen or its isotopes is thereby formed in the slit 320 (shown in FIG. 3E).

[0075] The method 400 proceeds to step 416, as shown in FIG. 4, where at least a portion of hydrogen or at least one of the isotopes of hydrogen is diffused into the channel structure. In some embodiments, at least a portion of hydrogen or at least one of the isotopes of hydrogen is diffused from the dielectric layer into the semiconductor channel. During any thermal process after the formation of the insulating structure 336 with the hydrogen-rich dielectric layer 334, hydrogen or its isotopes can be diffused from the dielectric layer 334 through the sidewalls of the insulating structure 336 into the semiconductor channel of the channel structure 314 to dope the semiconductor channel, e.g., polysilicon, with hydrogen or its isotopes. The doped hydrogen or its isotopes can form H-Si covalent bonds with dangling bonds in the polysilicon semiconductor channel, thereby reducing dangling bonds in the polysilicon semiconductor channel, thereby improving carrier mobility and adjusting stress of the channel structure 314. Thus, the atomic percentage of hydrogen or its isotopes in the dielectric layer 334 can be reduced to 50% or less, e.g., 1% to 10%, after diffusion. It is understood that no additional thermal process can be added to the manufacturing process flow to diffuse hydrogen or its isotopes. Instead, existing processes in the manufacturing process flow after the formation of the insulating structure 336 may cause diffusion of hydrogen or its isotopes, such as the various processes described below for purposes of example only.

[0076] As shown in FIG. 3G, after the formation of the insulating structure 336, local contacts including channel local contact 344 and word line local contact 342, as well as peripheral contacts 338 and 340, are formed. A local dielectric layer can be formed on the memory stack 330 by depositing a dielectric material, such as silicon oxide or silicon nitride, on top of the memory stack 330 using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. The channel local contact 344, word line local contact 342, and peripheral contacts 338 and 340 can be formed by etching contact openings through the local dielectric layer (and any other ILD layers) using wet and / or dry etching, e.g., RIE, followed by filling the contact openings with a conductive material using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0077] 3H, in some embodiments, the front source contact 343 is formed in the same process for forming the wordline local contact 342. The front source contact 343 may contact the N-type doped semiconductor layer 326.

[0078] As shown in Figures 3G and 3H, a bonding layer 346 is formed over the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340 (as well as the source contact 343 in Figure 3H). The bonding layer 346 includes bonding contacts electrically connected to the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. To form the bonding layer 346, an ILD layer is deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, and bonding contacts are formed through the ILD layer using wet and / or dry etching, e.g., RIE, followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0079] As shown in FIG. 3I, the silicon substrate 302 and the components formed thereon (e.g., memory stack 330 and channel structure 314 formed therethrough) are flipped upside down. According to some embodiments, the downward-facing bonding layer 346 is bonded to the upward-facing bonding layer 348, i.e., in a face-to-face manner, thereby forming a bonding interface 354 between the silicon substrates 302 and 350. In some embodiments, a treatment process, such as a plasma treatment, a wet treatment, and / or a heat treatment, is applied to the bonding surfaces before bonding. After bonding, the bonding contacts in the bonding layer 346 and the bonding contacts in the bonding layer 348 are aligned and in contact with each other, such that the memory stack 330 and channel structure 314 formed therethrough can be electrically connected to and above the peripheral circuitry 352.

[0080] As shown in Figure 3J, the silicon substrate 302 (shown in Figure 3I) is thinned from the backside to expose the N-type doped semiconductor layer 304. The silicon substrate 302 can be thinned using CMP, grinding, dry etching, and / or wet etching. In some embodiments, a CMP process is performed to thin the silicon substrate 302 until the top surface of the N-type doped semiconductor layer 304 is reached.

[0081] As shown in FIG. 3K, one or more ILD layers 356 are formed on the N-type doped semiconductor layer 304. The ILD layer 356 can be formed by depositing a dielectric material on the top surface of the N-type doped semiconductor layer 304 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. As shown in FIG. 3K, a source contact opening 358 is formed through the ILD layer 356 into the N-type doped semiconductor layer 304. In some embodiments, a wet etch, such as RIE, and / or a dry etch is used to form the source contact opening 358. In some embodiments, the source contact opening 358 extends further into the top of the N-type doped semiconductor layer 304. The etching process through the ILD layer 356 can continue to etch a portion of the N-type doped semiconductor layer 304. In some embodiments, after etching through the ILD layer 356, a separate etching process is used to etch a portion of the N-type doped semiconductor layer 304. In some embodiments, the source contact openings 358 are patterned using lithography and aligned with the insulating structures 336 on either side of the N-type doped semiconductor layer 304 .

[0082] As shown in FIG. 3L, a source contact 364 is formed in a source contact opening 358 (shown in FIG. 3K) on the backside of the N-type doped semiconductor layer 304. According to some embodiments, the source contact 364 is above the memory stack 330 and contacts the N-type doped semiconductor layer 304. In some embodiments, one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, are used to deposit one or more conductive materials in the source contact opening 358 to fill the source contact opening 358 with an adhesion layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, can then be performed to remove excess conductive material such that the top surface of the source contact 364 is flush with the top surface of the ILD layer 356. In some embodiments, when the source contact opening 358 is aligned with the insulating structure 336, the backside source contact 364 is also aligned with the insulating structure 336.

[0083] As shown in FIG. 3M, a redistribution layer 370 is formed above and in contact with the source contact 364. In some embodiments, the redistribution layer 370 is formed by depositing a conductive material, such as Al, on top of the N-type doped semiconductor layer 304 and the source contact 364 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. As shown in FIG. 3M, a passivation layer 372 is formed on the redistribution layer 370. In some embodiments, the passivation layer 372 is formed by depositing a dielectric material, such as silicon nitride, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. According to some embodiments, this forms an interconnect layer 376 including the ILD layer 356, the redistribution layer 370, and the passivation layer 372.

[0084] As shown in FIG. 3K, contact openings 360 and 361 are formed that extend through the ILD layer 356 and the N-type doped semiconductor layer 304, respectively. The contact openings 360, 361 and the source contact opening 358 can be formed using the same etching process, reducing the number of etching processes. In some embodiments, the contact openings 360 and 361 are formed through the ILD layer 356 and the N-type doped semiconductor layer 304 using a wet etch, such as RIE, and / or a dry etch. In some embodiments, the contact openings 360 and 361 are patterned using lithography to be aligned with the peripheral contacts 338 and 340, respectively. The etching of the contact openings 360 and 361 can stop at the tops of the peripheral contacts 338 and 340 to expose the peripheral contacts 338 and 340. As shown in FIG. 3K, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, spacers 362 are formed along the sidewalls of contact openings 360 and 361 to electrically isolate N-type doped semiconductor layer 304.

[0085] As shown in FIG. 3L, contacts 366 and 368 are formed in contact openings 360 and 361 (shown in FIG. 3K) on the backside of N-type doped semiconductor layer 304, respectively. According to some embodiments, contacts 366 and 368 extend vertically through ILD layer 356 and N-type doped semiconductor layer 304. Contacts 366 and 368 and source contact 364 can be formed using the same deposition process to reduce the number of deposition processes. In some embodiments, one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, are used to deposit one or more conductive materials in contact openings 360 and 361 to fill contact openings 360 and 361 with an adhesion layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, can then be performed to remove excess conductive material such that the top surfaces of contacts 366 and 368 are flush with the top surface of ILD layer 356. In some embodiments, when contact openings 360 and 361 are aligned with peripheral contacts 338 and 340, respectively, contacts 366 and 368 also overlie and contact peripheral contacts 338 and 340, respectively.

[0086] 3M, a redistribution layer 370 is also formed over and in contact with the contact 366. As a result, the N-type doped semiconductor layer 326 can be electrically connected to the peripheral contact 338 via the N-type doped semiconductor layer 304, the source contact 364, the redistribution layer 370 of the interconnect layer 376, and the contact 366. In some embodiments, the N-type doped semiconductor layers 326 and 304 are electrically connected to the peripheral circuitry 352 via the source contact 364, the interconnect layer 376, the contact 366, the peripheral contact 338, and the bonding layers 346 and 348.

[0087] 3M, contact pads 374 are formed over and in contact with contacts 368. In some embodiments, portions of passivation layer 372 covering contacts 368 are removed by wet and dry etching to expose portions of the underlying redistribution layer 370 to form contact pads 374. As a result, contact pads 374 for signal output pads can be electrically connected to peripheral circuitry 352 via contacts 368, peripheral contacts 340, and bonding layers 346 and 348.

[0088] According to one aspect of the disclosure, a 3D memory device includes a memory stack including alternating stacked conductive layers and stacked dielectric layers, a semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and into the semiconductor layer, and an insulating structure extending vertically through the memory stack and including a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.

[0089] In some embodiments, the atomic percentage of hydrogen or at least one isotope of hydrogen in the dielectric layer is about 50% or less, hi some embodiments, the atomic percentage of hydrogen or at least one isotope of hydrogen in the dielectric layer is about 1% to about 10%.

[0090] In some embodiments, the dielectric layer comprises silicon nitride.

[0091] In some embodiments, the insulating structure further comprises a first silicon oxide layer laterally between the dielectric layer and the stack conductive layer of the memory stack.

[0092] In some embodiments, the insulating structure further comprises a second silicon oxide layer. According to some embodiments, the dielectric layer is laterally between the first silicon oxide layer and the second silicon oxide layer.

[0093] In some embodiments, the insulating structure further comprises a polysilicon layer. According to some embodiments, the dielectric layer is laterally between the first silicon oxide layer and the polysilicon layer.

[0094] In some embodiments, the insulating structure further comprises a silicon oxide cap at one end of the insulating structure.

[0095] In some embodiments, one end of the insulating structure is flush with each end of the dielectric layer.

[0096] In some embodiments, the semiconductor layer includes one or more doped silicon layers.

[0097] In some embodiments, each of the channel structures includes a memory membrane and a semiconductor channel doped with at least one of hydrogen or an isotope of hydrogen.

[0098] In some embodiments, the semiconductor channel comprises polysilicon.

[0099] In some embodiments, the insulating structures extend laterally to separate the channel structures into blocks.

[0100] In some embodiments, the 3D memory device further comprises a source contact in contact with the semiconductor layer. According to some embodiments, the source contact and the insulating structure are on opposite sides of the semiconductor layer.

[0101] In some embodiments, the 3D memory device further comprises a source contact in contact with the semiconductor layer. According to some embodiments, the source contact and the insulating structure are on the same side of the semiconductor layer.

[0102] According to another aspect of the disclosure, a 3D memory device includes a memory stack including alternating stacked conductive layers and stacked dielectric layers, a semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and into the semiconductor layer, and an insulating structure extending vertically through the memory stack and including a dielectric layer, each channel structure including a memory film and a semiconductor channel doped with at least one of hydrogen or an isotope of hydrogen.

[0103] In some embodiments, the dielectric layer is doped with at least one of hydrogen or an isotope of hydrogen.

[0104] In some embodiments, the atomic percentage of hydrogen or at least one isotope of hydrogen in the dielectric layer is about 50% or less, hi some embodiments, the atomic percentage of hydrogen or at least one isotope of hydrogen in the dielectric layer is about 1% to about 10%.

[0105] In some embodiments, the dielectric layer comprises silicon nitride.

[0106] In some embodiments, the insulating structure further comprises a first silicon oxide layer laterally between the dielectric layer and the stack conductive layer of the memory stack.

[0107] In some embodiments, the insulating structure further comprises a second silicon oxide layer. According to some embodiments, the dielectric layer is laterally between the first silicon oxide layer and the second silicon oxide layer.

[0108] In some embodiments, the insulating structure further comprises a polysilicon layer. According to some embodiments, the dielectric layer is laterally between the first silicon oxide layer and the polysilicon layer.

[0109] In some embodiments, the insulating structure further comprises a silicon oxide cap at one end of the insulating structure.

[0110] In some embodiments, one end of the insulating structure is flush with each end of the dielectric layer.

[0111] In some embodiments, the semiconductor layer includes one or more doped silicon layers.

[0112] In some embodiments, the semiconductor channel comprises polysilicon.

[0113] In some embodiments, the insulating structures extend laterally to separate the channel structures into blocks.

[0114] In some embodiments, the 3D memory device further comprises a source contact in contact with the semiconductor layer. According to some embodiments, the source contact and the insulating structure are on opposite sides of the semiconductor layer.

[0115] In some embodiments, the 3D memory device further comprises a source contact in contact with the semiconductor layer. According to some embodiments, the source contact and the insulating structure are on the same side of the semiconductor layer.

[0116] According to yet another aspect of the present disclosure, a method for forming a 3D memory device is disclosed. A channel structure is formed that extends vertically through a memory stack into a semiconductor layer on a substrate. The memory stack includes alternating stacked conductive layers and stacked dielectric layers. An insulating structure is formed in an opening that extends vertically through the memory stack and includes a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.

[0117] In some embodiments, at least a portion of the hydrogen or at least one of the isotopes of hydrogen is diffused into the channel structure.

[0118] In some embodiments, a first layer of silicon oxide, a dielectric layer, and a second layer of silicon oxide are sequentially formed in the opening to form an insulating structure.

[0119] In some embodiments, a layer of silicon oxide, a dielectric layer, and a layer of polysilicon are sequentially formed in the opening to form an insulating structure.

[0120] In some embodiments, the insulating structures do not extend vertically into the N-type doped semiconductor layer.

[0121] In some embodiments, a layer of silicon oxide and a dielectric layer are sequentially formed in the opening to form an insulating structure.

[0122] In some embodiments, a silicon oxide cap is formed on top of the insulating structure to form the insulating structure, in some embodiments, the silicon oxide cap is formed by etching back at least a top portion of the dielectric layer to form a recess and depositing a layer of silicon oxide to fill the recess.

[0123] In some embodiments, a layer of silicon nitride is deposited and the layer of silicon nitride is in situ doped with at least one of hydrogen or an isotope of hydrogen to form the dielectric layer.

[0124] In some embodiments, to form the dielectric layer, a layer of silicon nitride is deposited and, after deposition, the layer of silicon nitride is annealed in the presence of hydrogen or at least one isotope of hydrogen.

[0125] In some embodiments, to form a channel structure, a first semiconductor layer on a substrate, a sacrificial layer on the first semiconductor layer, and a dielectric stack on the sacrificial layer are sequentially formed, a channel structure extending vertically through the dielectric stack and the sacrificial layer into the first semiconductor layer is formed, an opening extending vertically through the dielectric stack is formed, the sacrificial layer is replaced with a second semiconductor layer through the opening, and the dielectric stack is replaced with a memory stack through the opening.

[0126] In some embodiments, to form the channel structure, a channel hole is formed that extends vertically through the dielectric stack and the sacrificial layer into the first semiconductor layer, and a memory film and a semiconductor channel are sequentially formed along sidewalls of the channel hole.

[0127] In some embodiments, due to diffusion, at least a portion of the hydrogen or at least one of the isotopes of hydrogen diffuses from the dielectric layer into the semiconductor channel.

[0128] In some embodiments, the semiconductor channel comprises polysilicon.

[0129] The foregoing description of specific embodiments reveals the general nature of the present disclosure, so that others can easily modify and / or adapt such specific embodiments to various applications by applying knowledge within the skill of those skilled in the art without departing from the general concept of the present disclosure and without undue experimentation. Such adaptations and modifications are therefore intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teachings and guidance presented herein. It should be understood that the expressions or terms in this specification are intended to be descriptive and not limiting, as the terms or terms in this specification would be interpreted by those skilled in the art in light of the teachings and guidance.

[0130] The embodiments of the present disclosure are described above with functional components illustrating implementation of specified functions and their relationships. The boundaries of these functional components are arbitrarily defined herein for convenience of description. Alternative boundaries may be defined so long as the specified functions and their relationships are appropriately performed.

[0131] The Summary and Abstract sections may describe one or more exemplary embodiments of the present disclosure, but not all, contemplated by the inventors, and thus are not intended to limit the scope of the disclosure and the appended claims in any way.

[0132] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. 1. A three-dimensional (3D) memory device, comprising: a memory stack including alternating stacked conductive layers and stacked dielectric layers; A semiconductor layer; a plurality of channel structures each extending vertically through the memory stack and into the semiconductor layer; an insulating structure extending vertically through the memory stack and including a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen; Including, Each of the channel structures includes a memory film including a tunnel layer and a semiconductor channel doped with at least one of hydrogen or an isotope of hydrogen; the hydrogen or at least one isotope of hydrogen forms H—Si covalent bonds with dangling bonds between grain boundaries in the semiconductor channel and at interfaces with the tunnel layer; the insulating structure further comprises a polysilicon layer; 1 is a cross-sectional side view of the three dimensional (3D) memory device; The dielectric layer has a U-shape, The polysilicon layer is disposed inside the U-shaped dielectric layer. Three-dimensional (3D) memory devices.

2. the atomic percentage of said hydrogen or at least one isotope of hydrogen in said dielectric layer is less than or equal to about 50%; 10. The 3D memory device of claim 1 .

3. the atomic percentage of the hydrogen or at least one isotope of hydrogen in the dielectric layer is between about 1% and about 10%; 3. The 3D memory device of claim 2.

4. the dielectric layer comprises silicon nitride; 10. The 3D memory device of claim 1 .

5. the insulating structure further comprises a first silicon oxide layer laterally between the dielectric layer and the stack conductive layer of the memory stack; 10. The 3D memory device of claim 1 .

6. The dielectric layer is laterally disposed between the first silicon oxide layer and the polysilicon layer.

6. The 3D memory device of claim 5.

7. the insulating structure further comprises a silicon oxide cap at one end of the insulating structure; 10. The 3D memory device of claim 1 .

8. one end of the insulating structure is flush with each end of the dielectric layer; 10. The 3D memory device of claim 1 .

9. the semiconductor layer comprises one or more doped silicon layers; 10. The 3D memory device of claim 1 .

10. the semiconductor channel comprises polysilicon; 10. The 3D memory device of claim 1 .

11. the insulating structure extends laterally to separate the plurality of channel structures into a plurality of blocks.

10. The 3D memory device of claim 1 .

12. a source contact in contact with the semiconductor layer, the source contact and the insulating structure being on opposite sides of the semiconductor layer.

10. The 3D memory device of claim 1 .

13. a source contact in contact with the semiconductor layer, the source contact and the insulating structure being on the same side of the semiconductor layer.

10. The 3D memory device of claim 1 .

14. 1. A three-dimensional (3D) memory device, comprising: a memory stack including alternating stacked conductive layers and stacked dielectric layers; A semiconductor layer; a plurality of channel structures each extending vertically through the memory stack and into the semiconductor layer, each of the channel structures including a memory film including a tunnel layer and a semiconductor channel doped with at least one of hydrogen or an isotope of hydrogen; an isolation structure extending vertically through the memory stack and including a dielectric layer; Including, the hydrogen or at least one isotope of hydrogen forms H—Si covalent bonds with dangling bonds between grain boundaries in the semiconductor channel and at interfaces with the tunnel layer; the insulating structure further comprises a polysilicon layer; 1 is a cross-sectional side view of the three dimensional (3D) memory device; The dielectric layer has a U-shape, The polysilicon layer is disposed inside the U-shaped dielectric layer. Three-dimensional (3D) memory devices.

15. the dielectric layer is doped with at least one of the hydrogen or isotopes of hydrogen; 15. The 3D memory device of claim 14.

16. the dielectric layer comprises silicon nitride; 15. The 3D memory device of claim 14.

17. 1. A method for forming a three dimensional (3D) memory device, comprising: forming a channel structure extending vertically through a memory stack into a semiconductor layer on a substrate, the memory stack including alternating stacked conductive layers and stacked dielectric layers; forming an isolation structure in the opening, the isolation structure extending vertically through the memory stack and including a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen; Including, The step of forming the channel structure includes: forming a memory film including a tunnel layer and a semiconductor channel; the hydrogen or at least one isotope of hydrogen forms H—Si covalent bonds with dangling bonds between grain boundaries in the semiconductor channel and at interfaces with the tunnel layer; the insulating structure further comprises a polysilicon layer; 1 is a cross-sectional side view of the three dimensional (3D) memory device; The dielectric layer has a U-shape, The polysilicon layer is disposed inside the U-shaped dielectric layer. A method for forming a three-dimensional (3D) memory device.

18. The step of forming the channel structure includes: sequentially forming a first semiconductor layer on the substrate, a sacrificial layer on the first semiconductor layer, and a dielectric stack on the sacrificial layer; forming the channel structure extending vertically through the dielectric stack and the sacrificial layer into the first semiconductor layer; forming the opening extending vertically through the dielectric stack; replacing the sacrificial layer with a second semiconductor layer through the opening; replacing the dielectric stack with the memory stack through the opening; Including, The step of forming the channel structure includes: forming a channel hole extending vertically through the dielectric stack and the sacrificial layer into the first semiconductor layer; the step of sequentially forming the memory film including the tunnel layer and the semiconductor channel along a sidewall of the channel hole; Including, 20. The method of claim 17.

19. Diffusing at least a portion of the hydrogen or at least one isotope of hydrogen into the channel structure.

20. The method of claim 17.

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