Method for manufacturing a semiconductor device

Abstract

To manufacture and provide a semiconductor device that comprises a thin-film transistor having a stable electrical characteristic and that has high reliability.SOLUTION: In a manufacturing method of a semiconductor device that has a thin-film transistor in which a semiconductor layer including a channel formation region is an oxide semiconductor layer, a degree of purity of the oxide semiconductor layer is increased, water components or the like being impurities are reduced, and heat treatment (dehydration or heat treatment for dehydrogenation) oxidizing the oxide semiconductor layer is performed. Impurities such as water components existing not only in the oxide semiconductor layer but also in the a gate insulation layer are reduced, and impurities such as water components existing in a boundary surface between a layer provided contacting with an upper / lower side and the oxide semiconductor layer are reduced.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. In general, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] In recent years, thin semiconductor layers (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used This forms a thin film transistor (TFT). This technology is attracting attention. Thin-film transistors are used in electronic devices such as ICs and electro-optical devices. It is widely used, and development is being accelerated especially as a switching element for image display devices. Indium oxide is a well-known material. It is used as a transparent electrode material required for liquid crystal displays and other devices.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin-film transistors that use metal oxides as channel formation regions and that exhibit excellent semiconductor properties are already known. (Patent Documents 1 to 5, Non-Patent Document 1).

[0005] Incidentally, metal oxides include not only single-component oxides but also multi-component oxides. For example, Homologous phase InGaO 3 (ZnO) m (m: natural number) is In, Ga, and Zn It is known as a multi-component oxide semiconductor having the above structure (Non-Patent Documents 2 to 4).

[0006] Then, the oxide semiconductor composed of the above-mentioned In-Ga-Zn-O system oxide was formed into a thin film. It has been confirmed that it can be used as a channel layer for transistors (Patent Document 6, Non-Patent Document 7, See references 5 and 6). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 1988-1986 [Patent Document 2] Japanese Patent Application Publication No. 8-264794 [Patent Document 3] Special Publication No. 11-505377 [Patent Document 4] JP 2000-150900 A [Patent Document 5] JP 2007-123861 A [Patent Document 6] JP 2004-103957 A [Non-patent literature]

[0008] [Non-Patent Document 1] MW Prins, KO Grosse-Holz, G.Muller, JFM Cillessen, JB Giesbers, RP Weening, and RM Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650-3652 [Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3 - Ga2ZnO4 - ZnO System at 1350℃", J. Solid State Chem., 1991, Vol. 93, p. 298 - 315 [Non - Patent Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, "Syntheses and Single - Crystal Data of Homologous Compounds, In2O3(ZnO)m(m = 3, 4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m = 7, 8, 9, and 16) in the In2O3 - ZnGa2O4 - ZnO System", J. Solid State Chem., 1995, Vol. 116, p. 170 - 178 [Non - Patent Document 4] M. Nakamura, N. Kimizuka, T. Mohri, M. Isobe, "Synthesis and Crystal Structure of Homologous Phases, InFeO3(ZnO)m (m: natural number) and Its Isomorphic Compounds", Solid State Physics, 1993, Vol. 28, No. 5, p. 317 - 327 [Non - Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin - film transistor fabricated in single - crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol. 300, p. 1269 - 1272 [Non - Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol.432 p.488-492 Summary of the Invention [Problem to be solved by the invention]

[0009] To manufacture a highly reliable semiconductor device having a thin film transistor with stable electrical characteristics. One of our objectives is to provide [Means for solving the problem]

[0010] A semiconductor device having a thin film transistor in which a semiconductor layer including a channel formation region is an oxide semiconductor layer In a method for manufacturing an organic semiconductor device, the purity of an oxide semiconductor layer is increased and moisture or the like, which is an impurity, is reduced. The heat treatment for dehydration or dehydrogenation is carried out in an oxygen atmosphere. Impurities such as moisture in the oxide semiconductor layer and in the gate insulating layer are reduced, and Impurities such as moisture that are present at the interface between the underlying layer and the oxide semiconductor layer are reduced. In addition, the oxide semiconductor layer can be oxidized by the heat treatment.

[0011] In order to reduce impurities such as moisture, the exposed oxide semiconductor layer is The oxide semiconductor layer is heat-treated in an oxygen atmosphere to reduce the moisture content of the oxide semiconductor layer and to The semiconductor layer is oxidized. The heat treatment temperature is 200° C. or higher and lower than the distortion point of the substrate, preferably 40° C. The temperature is 0°C to 700°C. After the heat treatment, the material is heated in an oxygen atmosphere or in a nitrogen or It is preferable to keep it under an inert gas atmosphere of rare gas (helium, argon, etc.) and slowly cool it. I wish.

[0012] The oxygen atmosphere is a gas atmosphere containing oxygen atoms, typically oxygen, ozone, or Nitrogen oxides (nitric oxide, nitrogen dioxide, dinitrogen monoxide, dinitrogen trioxide, dinitrogen tetroxide, pentoxide) In addition, nitrogen or rare gas (helium, etc.) in an oxygen atmosphere. Inert gases such as ammonium, argon, etc. may be included, but in that case, they should not contain oxygen atoms. There is less inert gas than gas.

[0013] In this specification, the oxide semiconductor layer is oxidized while being dehydrated or dehydrogenated in an oxygen atmosphere. The heat treatment is referred to as a heat treatment for dehydration or dehydrogenation. By reason 2 Dehydrogenation does not only mean that hydrogen is removed as hydrogen, but also as hydrogen. For convenience, this refers to the removal of molecules containing OH, etc. as dehydration or dehydrogenation. do.

[0014] By performing heat treatment in an oxygen atmosphere, impurities such as moisture contained in the oxide semiconductor layer are reduced. In addition, the oxide semiconductor layer is oxidized to improve the reliability of the thin film transistor. Furthermore, by forming an oxide insulating layer in contact with the oxide semiconductor layer, This makes it possible to improve the reliability of the thin film transistor.

[0015] Note that the oxide insulating layer formed in contact with the oxide semiconductor layer that has been subjected to heat treatment in an oxygen atmosphere is Molecular weight, hydrogen ions, and OH -An inorganic insulating layer is used to block impurities such as oxide insulation. Typical examples of edge layers include single or multilayer silicon oxide and silicon oxynitride layers.

[0016] Furthermore, an oxide insulating layer that becomes a protective layer in contact with the oxide semiconductor layer that has been heat-treated in an oxygen atmosphere is formed. After the formation of the oxide semiconductor layer, a second heating may be performed. After forming the oxide insulating layer, the second heating step improves the electrical characteristics of the thin film transistor. The variation can be reduced.

[0017] The above configuration solves at least one of the above problems.

[0018] In another embodiment of the present invention, a gate electrode layer is formed over a substrate having an insulating surface, a gate insulating layer is formed over the oxide semiconductor layer; and an oxide semiconductor layer is formed over the gate insulating layer. The layer was dehydrated or dehydrogenated in an oxygen atmosphere to obtain a dehydrated or dehydrogenated oxide semiconductor. A source electrode layer and a drain electrode layer are formed on the semiconductor layer, and a gate insulating layer, an oxide semiconductor layer, and a An oxide insulating layer is formed on the source electrode layer and the drain electrode layer, the oxide insulating layer being in contact with a part of the oxide semiconductor layer. The present invention relates to a method for manufacturing a semiconductor device.

[0019] In another embodiment of the present invention, a gate electrode layer is formed over a substrate having an insulating surface, A gate insulating layer is formed on the electrode layer, an oxide semiconductor layer is formed on the gate insulating layer, and an oxide semiconductor The conductor layer is heated in an oxygen atmosphere, and then the semiconductor layer is dehydrated or dehydrogenated. A source electrode layer and a drain electrode layer are formed, and a gate insulating layer, a heated oxide semiconductor layer, a source an oxide insulating layer in contact with a part of the oxide semiconductor layer on the source electrode layer and the drain electrode layer; The present invention relates to a method for manufacturing a semiconductor device, and a method for manufacturing the same. Heat in an atmosphere at a temperature of 200°C or higher, then slowly cool to room temperature or higher but below 100°C. is preferred.

[0020] The oxide semiconductor used in this specification is InMO 3 (ZnO) m (m>0) A thin film is formed and a thin film transistor is fabricated using the thin film as the semiconductor layer. , Ga, Fe, Ni, Mn and Co. For example, M can be Ga, Ga and Ni, Ga and Fe, etc. In the oxide semiconductor, M may contain any of the above metal elements other than a. In addition to the metallic elements contained in the steel, impurity elements include Fe, Ni and other transition metal elements, or In this specification, the term "InMO" refers to an oxide of the transition metal. 3 (Zn O) m Among oxide semiconductor layers having a structure represented by (m>0), those having a structure containing Ga as M The oxide semiconductor is called the In-Ga-Zn-O oxide semiconductor, and the thin film is called the In-Ga-Zn This is also called an nO-based non-single crystal layer.

[0021] In addition to the above, In-Sn-Zn- O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S n-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In In addition, the above-mentioned oxide semiconductors can be used. The oxide semiconductor layer may contain silicon oxide. SiOX (X>0)) is included, the formation of an oxide semiconductor layer during the manufacturing process When the oxide semiconductor is subsequently subjected to a heat treatment, crystallization can be suppressed. The conductor layer is preferably in an amorphous state, and may be partially crystallized.

[0022] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and In order to make the oxide semiconductor layer i-type (intrinsic), Hydrogenation or dehydrogenation is effective.

[0023] In addition, since thin-film transistors are easily damaged by static electricity, etc., It is preferable to provide a protection circuit for protecting the driver circuit on the same substrate as the line. is preferably configured using a nonlinear element using an oxide semiconductor.

[0024] In addition, the gate insulating layer and the oxide semiconductor layer are processed continuously (continuously) without being exposed to the air. It may be subjected to a continuous process (also called in-situ process, continuous formation, etc.). By performing the treatment continuously without causing any damage to the gate insulating layer and the oxide semiconductor layer, the interface between the gate insulating layer and the oxide semiconductor layer is free from moisture and Without being contaminated by atmospheric components such as hydrocarbons or impurities floating in the air Since it is possible to form each lamination interface, the variation in thin film transistor characteristics can be reduced. This can be done.

[0025] In this specification, the term "successive treatments" refers to the first treatment step performed by the PCVD method or the sputtering method. During the series of processes from the deposition of the substrate to the second treatment step using PCVD or sputtering, The environment in which the substrates are processed is always in a vacuum or This means that the atmosphere is controlled in an inert gas (nitrogen or rare gas). By performing subsequent processing, reattachment of moisture, etc. to the cleaned substrate can be avoided, and film formation can be prevented. Which processing can be performed?

[0026] To carry out a series of processes from the first processing step to the second processing step in the same chamber is considered to be within the scope of continuous processing in this specification.

[0027] In addition, a series of processes from the first process to the second process are carried out in different chambers. In this case, after the first processing step is completed, the substrate is transported between chambers without being exposed to the atmosphere. The application of a second treatment is also considered to be within the scope of the continuous treatment in this specification.

[0028] Between the first and second processing steps, a substrate transfer step, an alignment step, and a slow cooling step are performed. or a step of heating or cooling the substrate to a temperature required for the second step. However, such a process is considered to be within the scope of the continuous process in this specification.

[0029] However, the first step is to use liquids in the cleaning process, wet etching, and resist formation. If the first processing step is between the second processing step, it does not fall within the scope of continuous processing as used herein. Let's say that's not the case. Effect of the Invention

[0030] It is possible to manufacture a thin film transistor having stable electrical characteristics. A semiconductor device having a good and reliable thin film transistor can be manufactured. [Brief description of the drawings]

[0031] [Figure 1]1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Diagram 2] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 3] FIG. [Figure 4] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Diagram 5] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 16] FIG. 1 is a block diagram illustrating a display device. [Figure 17] FIG. 2 is a diagram illustrating a configuration of a signal line driver circuit. [Figure 18] FIG. 2 is a circuit diagram showing a configuration of a shift register. [Figure 19] FIG. 2 is a diagram illustrating the operation of a shift register. [Figure 20] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 21]1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 22] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 23] 1 illustrates a pixel equivalent circuit of a semiconductor device according to one embodiment of the present invention. [Figure 24] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 25] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 26] FIG. 1 is an external view showing an example of an electronic book. [Figure 27] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 28] FIG. 1 is an external view showing an example of a gaming machine. [Figure 29] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Diagram 30] 13A to 13C are diagrams illustrating calculation results of an interaction between oxygen molecules and a surface of an oxide semiconductor layer. [Diagram 31] 1A and 1B are diagrams illustrating a structure of an oxide semiconductor layer used in calculations. [Diagram 32] 11A and 11B are diagrams illustrating calculation results of oxygen density in oxide semiconductor layers. [Diagram 33] 1A and 1B are diagrams illustrating an interaction between oxygen and a surface of an oxide semiconductor layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0033] (Embodiment 1) A semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS.

[0034] FIG. 2A is a plan view of a thin film transistor 470 included in the semiconductor device, and FIG. FIG. 2(A) is a cross-sectional view taken along line C1-C2 of FIG. The transistor is a gate type thin film transistor, and a gate electrode is disposed on a substrate 400 having an insulating surface. A pole layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode layer or a drain electrode layer The thin film transistor 470 is covered with an oxide semiconductor An oxide insulating layer 407 is provided in contact with the layer 403 .

[0035] The oxide semiconductor layer 403 is formed by removing impurities such as moisture at least after the formation of the oxide semiconductor layer. The heat treatment to reduce oxygen (heat treatment for dehydration or dehydrogenation) is carried out in an oxygen atmosphere. The oxide semiconductor layer 403 that has been subjected to the heat treatment is used as a channel formation region of a thin film transistor. By using the organic EL element as a thin film transistor, the reliability of the thin film transistor can be improved.

[0036] Furthermore, by heat treatment in an oxygen atmosphere (heat treatment for dehydration or dehydrogenation), Minute(H 2 After the oxide semiconductor layer 403 is oxidized, impurities such as fluorine (O) are eliminated and the oxide semiconductor layer 403 is oxidized. It is preferable to carry out slow cooling under a nitrogen atmosphere or an inert gas atmosphere. After the heat treatment for dehydrogenation and the annealing, the oxide insulating layer is formed in contact with the oxide semiconductor layer. As a result, the reliability of the thin film transistor 470 is improved. leads to.

[0037] In addition to the oxide semiconductor layer 403, the oxide semiconductor layer 403 is also provided in the gate insulating layer 402 and in contact with the upper and lower surfaces. Specifically, the interface between the gate insulating layer 402 and the oxide semiconductor layer 403 Water present at the interface between the oxide insulating layer 407 and the oxide semiconductor layer 403 and at the interface between the oxide insulating layer 407 and the oxide semiconductor layer 403 It is preferable that impurities such as minerals are reduced.

[0038] In addition, the source and drain electrode layers 405a and 40 5b: Titanium, aluminum, manganese, magnesium, zirconium, beryllium The material is selected from one or more of the elements mentioned above. Combined alloy layers and the like can be laminated.

[0039] The oxide semiconductor layer 403 including the channel formation region is formed using an oxide material having semiconductor characteristics. Typically, an In-Ga-Zn-O based non-single crystal layer is used.

[0040] 1A to 1D are cross-sectional views showing a manufacturing process of the thin film transistor 470 shown in FIG.

[0041] In FIG. 1A, a gate electrode layer 401 is formed on a substrate 400 having an insulating surface. establish.

[0042] There is no particular limitation on the substrate 400, but it should have at least heat resistance sufficient to withstand the subsequent heat treatment. The substrate 400 is made of barium borosilicate glass or aluminoboron. A glass substrate such as silicate glass can be used.

[0043] In addition, when the temperature of the subsequent heat treatment is high, the substrate 400 having the light-transmitting property is The substrate 400 is preferably made of, for example, aluminosilicate. Glass materials such as vitreous glass, aluminoborosilicate glass, and barium borosilicate glass are used. It is used because it contains more barium oxide (BaO) than boric acid. Practical heat-resistant glass can be obtained. 2 O 3 Glass substrates containing more BaO It is preferable to use

[0044] The substrate 400 may be made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate. Alternatively, a substrate made of crystallized glass or the like may be used.

[0045] An insulating layer serving as a base layer may be provided between the substrate 400 and the gate electrode layer 401. The silicon nitride layer, the silicon oxide layer, the nitride layer, and the silicon oxide layer have a function of preventing the diffusion of impurity elements from the substrate 400. A laminate structure of one or more layers selected from a silicon oxide layer and a silicon oxynitride layer. It can be formed.

[0046] The material of the gate electrode layer 401 is molybdenum, titanium, chromium, tantalum, tungsten, Metallic materials such as aluminum, copper, neodymium, and scandium, or alloys containing these as the main components It can be formed of a gold material in a single layer or in a multilayer structure.

[0047] For example, the gate electrode layer 401 may have a two-layer laminate structure of molybdenum on an aluminum layer. A two-layer structure with a layer of molybdenum laminated on a copper layer, or a two-layer structure with a layer of molybdenum laminated on a copper layer, or The titanium nitride layer and the tantalum nitride layer are laminated on the copper layer. It is preferable to use a two-layer structure in which a tungsten layer is laminated with a tungsten layer. A tungsten layer or a tungsten nitride layer and an aluminum-silicon alloy layer or an aluminum It is preferable to use a laminate of a titanium-titanium alloy layer and a titanium nitride layer or a titanium layer. It is.

[0048] Next, a gate insulating layer 402 is formed over the gate electrode layer 401 .

[0049] The gate insulating layer 402 is formed by depositing silicon oxide by a plasma CVD method, a sputtering method, or the like. layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, or a tantalum oxide layer. The tantalum layer can be formed in a single layer or in a multi-layer structure. For example, the forming gas can be Si H 4 A silicon oxynitride layer may be formed by a plasma CVD method using oxygen and nitrogen.

[0050] Next, an oxide semiconductor layer is formed over the gate insulating layer 402.

[0051] Before the oxide semiconductor layer is formed by a sputtering method, argon gas is introduced. A reverse sputtering process is performed to generate plasma, and the gate insulating layer 402 is adhered to the surface of the gate insulating layer 402. It is preferable to remove the dust that is generated by applying a voltage to the target side. Without applying a voltage to the substrate side using an RF power supply in an argon atmosphere, plasma was generated near the substrate. This is a method for modifying the surface by forming a gas atmosphere. Note that the argon atmosphere can be replaced by helium or the like. It may be used.

[0052] The oxide semiconductor layer was formed by sputtering using an In-Ga-Zn-O oxide semiconductor target. The sputtering method uses a rare gas (typically argon), oxygen, or Alternatively, the treatment is carried out in an atmosphere of a mixture of a rare gas (typically argon) and oxygen.

[0053] The gate insulating layer 402 and the oxide semiconductor layer may be successively formed without exposure to air. By forming the film continuously without exposing it to the air, the interface is free from moisture and hydrocarbons. The interfaces of each layer are formed without being contaminated by atmospheric components or impurity elements floating in the air. Therefore, the variation in the characteristics of the thin film transistors can be reduced.

[0054] The oxide semiconductor layer is formed into an island-shaped oxide semiconductor layer (first oxide semiconductor layer) by a photolithography process. The resulting semiconductor layer is processed into a conductor layer 430 (see FIG. 1(A)).

[0055] Next, the oxide semiconductor layer is subjected to heat treatment in an oxygen atmosphere, and then subjected to a heat treatment in an oxygen atmosphere or an inert atmosphere. The oxide semiconductor layer 430 is preferably cooled slowly in a gas atmosphere. By the treatment, impurities such as hydrogen and moisture contained in the oxide semiconductor layer 430 are removed. In addition, an oxidized oxide semiconductor layer 431 can be formed (see FIG. 1B). Depending on the conditions of the heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized to form a microcrystalline layer or In some cases, the layer may be polycrystalline.

[0056] The oxygen atmosphere is a gas atmosphere containing oxygen atoms, and typically includes oxygen, ozone, or nitrogen oxides (nitric oxide, nitrogen dioxide, nitrous oxide, dinitrogen trioxide, dinitrogen tetroxide) In an oxygen atmosphere, nitrogen or Inert gases such as rare gases (helium, argon, etc.) may be included, but in that case, oxygen There is less amount of inert gas than gas with atoms.

[0057] In the heat treatment, it is preferable that the oxygen atmosphere does not contain moisture, hydrogen, etc. Alternatively, the purity of oxygen introduced into the heat treatment device is preferably 6N (99.9999%) or more. or 7N (99.99999%) or more (i.e. impurity concentration is 1 ppm or less, preferably It is preferable to keep the concentration at 0.1 ppm or less.

[0058] Heat treatment can be performed using an electric furnace or a GRTA (Gas-Reactor-Atomic-Tapered Atomic) method. Rapid Thermal Annealing (LRTA) using lamp light (La Use instantaneous heating methods such as the mp Rapid Thermal Anneal method. It is possible.

[0059] Here, as one mode of heat treatment of the oxide semiconductor layer 430, a heating method using an electric furnace 601 is used. The method will be explained with reference to FIG.

[0060] FIG. 3 is a schematic diagram of an electric furnace 601. A heater 603 is provided on the outside of a chamber 602. The chamber 602 is heated by a heater. A susceptor 605 for mounting a substrate 604 is provided in the chamber 602. The chamber 602 is provided with a gas supply means 606 and an exhaust means 607. A gas supply means 606 is provided to introduce gas into the chamber 602. In addition, the inside of the chamber 602 is evacuated by the exhaust means 607. The characteristic is preferably 0.1° C. / min or more and 20° C. / min or less. It is preferable that the temperature drop characteristic of 01 is 0.1° C. / min or more and 15° C. / min or less.

[0061] The gas supply means 606 includes a gas supply source 611, a pressure regulating valve 612, a purifier 613, and a mass flow meter. In this embodiment, the gas supply A purifier 613 is provided between the source 611 and the chamber 602. The gas introduced into the chamber 602 from the gas supply source 611 is depleted of moisture, hydrogen, and other impurities. Impurities can be removed by the purifier 613, and in the chamber 602, The amount of impurities such as moisture and hydrogen mixed in can be reduced.

[0062] In this embodiment, a gas having oxygen atoms is supplied from a gas supply source 611 to a chamber 602. The chamber is filled with oxygen and heated to 200° C. or higher but lower than the distortion point of the substrate, preferably 4 In a chamber 602 heated to 00° C. or higher and 700° C. or lower, The oxide semiconductor layer 430 is heated to dehydrate or dehydrate the oxide semiconductor layer 430. It is possible to carry out denitrification.

[0063] The oxide semiconductor layer 430 in this embodiment is dehydrated or dehydrogenated in an oxygen atmosphere. By performing the heat treatment for oxidation, the surface of the oxide semiconductor layer 430 can be oxidized, and moisture, hydrogen, and the like can be removed. Since oxygen bonds to the sites or defects where the impurities have been removed, the i-type crystal has fewer defects. Therefore, the dehydrated or dehydrogenated oxide semiconductor layer 430 is used as a channel of a thin film transistor. By using it in the region where the thin film transistor is formed, the reliability of the thin film transistor that will be formed later can be improved. Cut.

[0064] The dehydration or dehydrogenation of the oxide semiconductor layer is performed so that the oxide semiconductor layer after the dehydration or dehydrogenation is In contrast, TDS (Thermal Desorption Spectroscopy) Even when measurements were taken up to 450°C, there were two peaks for water, and at least one peak near 300°C. The heat treatment conditions are set so that no peaks are detected. The thin-film transistor using the oxide semiconductor layer was measured up to 450°C by TDS. However, the water peak that appears at around 300°C is not detected.

[0065] The heater is then turned off and the chamber 602 of the heating device is placed under oxygen or inert atmosphere. It is preferable to keep the mixture in a reactive gas atmosphere and gradually cool it (cool it slowly). After the treatment, the temperature is gradually cooled from the heat treatment temperature to above room temperature and below 100°C. This can improve the reliability of the thin film transistors that will be formed later.

[0066] In the cooling step, the heating temperature at which the oxide semiconductor layer 430 is dehydrated or dehydrogenated is From the temperature T to a temperature that is high enough to prevent water from entering again, specifically 100 degrees above the heating temperature T. It may be lowered by more than ℃.

[0067] After the substrate 604 in the chamber 602 of the heating device is cooled to less than 300° C., 604 may be transferred to an oxygen or inert gas atmosphere at room temperature or above but below 100°C. As a result, the cooling time of the substrate 604 can be shortened.

[0068] In addition, if the heating device is a multi-chamber device, the heating process and the cooling process are performed in different chambers. Typically, the substrate is heated in an oxygen atmosphere at a temperature of 200° C. or higher and lower than the distortion point of the substrate. In a first chamber heated to 400° C. or higher and 700° C. or lower, a The oxide semiconductor layer 430 is then heated under an oxygen atmosphere or an inert gas atmosphere. The transfer chamber is then heated to a temperature above room temperature and below 100°C in an oxygen or inert gas atmosphere. The substrate that has been subjected to the above heat treatment is transferred to a second chamber in which a cooling treatment is performed. This makes it possible to improve the throughput.

[0069] In addition, the heat treatment of the oxide semiconductor layer in an oxygen atmosphere can process the oxide semiconductor layer into an island-shaped oxide semiconductor layer. In this case, the treatment can be performed in an oxygen atmosphere or in an inert atmosphere. After the oxide semiconductor layer is heat-treated in a gas atmosphere, it is gradually cooled to a temperature of room temperature or higher and less than 100°C. Then, the substrate is removed from the heating device and a photolithography process is performed.

[0070] After the heat treatment in an oxygen atmosphere, the oxide semiconductor layer 431 is in an amorphous state. However, partial crystallization is permitted.

[0071] Next, a conductive layer is formed over the gate insulating layer 402 and the oxide semiconductor layer 431.

[0072] The conductive layer is made of an element selected from Al, Cr, Ta, Ti, Mo, and W, or The layer may be an alloy containing the above-mentioned elements or an alloy layer containing a combination of the above-mentioned elements.

[0073] In addition, when a heat treatment is performed after the formation of the conductive layer, the conductive layer is required to have heat resistance sufficient to withstand the heat treatment. Aluminum alone has problems such as poor heat resistance and susceptibility to corrosion. Therefore, it is formed by combining it with a heat-resistant conductive material. Heat-resistant conductive material combined with Al The materials are titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (M o), chromium (Cr), Nd (neodymium), Sc (scandium), or or an alloy layer containing the above elements as components, or an alloy layer of a combination of the above elements, It is formed of a nitride containing the selected elements.

[0074] The oxide semiconductor layer 431 and the conductive layer are etched by an etching process, and the oxide semiconductor layer 403, and source and drain electrode layers 405a and 405b are formed (FIG. 1( Note that the oxide semiconductor layer 431 is only partially etched, and a groove (a depression) is formed. The oxide semiconductor layer 403 has the following structure.

[0075] The oxide insulating layer 407 is formed in contact with the oxide semiconductor layer 403. The oxide insulating layer 407 is The thickness of the oxide insulating layer 40 is at least 1 nm. The method can be appropriately used to prevent impurities such as moisture and hydrogen from being mixed into the insulating film 7. In this case, the oxide insulating layer 407 is formed by a sputtering method. The oxide insulating layer 407 formed in contact with the oxide semiconductor layer is resistant to moisture, hydrogen ions, , O.H. - There is little moisture or OH. - Inorganic insulation that blocks the intrusion of Specifically, a single layer or a stack of a silicon oxide layer or a silicon oxynitride layer may be used. .

[0076] In this embodiment, a silicon oxide layer with a thickness of 300 nm is formed as the oxide insulating layer 407. The substrate temperature during the formation may be from room temperature to 300° C., and in this embodiment, it is set to 100° C. The silicon oxide layer is formed by sputtering using a rare gas (typically argon), an oxygen gas, and a The reaction can be carried out in an atmosphere of nitrogen or a mixture of rare gas (typically argon) and oxygen. In addition, a silicon oxide target or a silicon target may be used as the target. For example, a silicon target is used, and the sputtering method is performed under an oxygen and nitrogen atmosphere. Silicon oxide can be formed.

[0077] The dehydrated or dehydrogenated oxide semiconductor layer 403 is contacted with a sputtering method or a PC By forming an oxide insulating layer 407 by a VD method or the like, a highly reliable thin film transistor 4 70 can be produced (see FIG. 1(D)).

[0078] The heat treatment for the dehydration or dehydrogenation is carried out in an oxygen atmosphere. H contained in the semiconductor layer 2 It is preferable to reduce impurities such as O, H, and OH and then slowly cool the mixture. In addition, after the annealing, an oxide insulating layer may be formed in contact with the oxide semiconductor layer. As a result, the reliability of the thin film transistor 470 can be improved.

[0079] After the oxide insulating layer 407 is formed, a thin film is formed in an oxygen atmosphere or an inert atmosphere. The transistor 470 may be subjected to a heat treatment (preferably at 150° C. or higher and lower than 350° C.). For example, heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The oxide semiconductor layer 403 is heated in contact with the oxide insulating layer 407. This heat treatment (preferably The heating temperature is not particularly limited to 150° C. or higher and lower than 350° C. after the oxide insulating layer 407 is formed. In addition, other processes, such as a heat treatment during resin layer formation and a process for reducing the resistance of the transparent conductive layer, By combining this with heat treatment, it is possible to perform this without increasing the number of steps.

[0080] (Embodiment 2) A semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. The same parts or parts having similar functions and steps can be performed in the same manner as in the first embodiment. Therefore, repeated explanation will be omitted.

[0081] FIG. 5A is a plan view of a thin film transistor 460 included in a semiconductor device, and FIG. The thin film transistor 460 is a bottom gate. The transistor is a gate type thin film transistor, and a gate electrode is disposed on a substrate 450 having an insulating surface. A gate insulating layer 452, a source electrode layer or a drain electrode layer 455a, 455b, b and an oxide semiconductor layer 453. An oxide insulating layer 457 is provided in contact with the conductor layer 453. The oxide semiconductor layer 453 is An In-Ga-Zn-O based non-single crystal layer is used.

[0082] The thin film transistor 460 has a gate insulating layer in the entire region including the thin film transistor 460. A layer 452 is present between the gate insulating layer 452 and a substrate 450 that is a substrate having an insulating surface. A gate electrode layer 451 is provided. A source electrode layer or a drain electrode layer is provided on the gate insulating layer 452. Drain electrode layers 455a and 455b are provided. A gate insulating layer 452 and An oxide semiconductor layer 453 is provided over the source and drain electrode layers 455a and 455b. Although not shown, a source electrode layer or a drain electrode layer is formed on the gate insulating layer 452. In addition to the gate electrode layers 455a and 455b, a wiring layer is provided. It extends outward from the outer periphery.

[0083] The oxide semiconductor layer 453 is formed by removing an impurity from the oxide semiconductor layer 453 in an oxygen atmosphere at least after the oxide semiconductor layer is formed. Heat treatment to reduce moisture, hydrogen, etc. and oxidize (for dehydration or dehydrogenation) By performing the heat treatment, the reliability of the thin film transistor can be improved.

[0084] In addition, the water content (H 2 O) and other impurities After the desorption process, it is preferable to slowly cool the mixture in an oxygen atmosphere or an inert gas atmosphere. After heat treatment for dehydration or dehydrogenation and gradual cooling, the oxide semiconductor layer is bonded to the By forming an oxide insulating layer or the like, the reliability of the thin film transistor 460 can be improved. It is possible.

[0085] In addition, the source and drain electrode layers 455a and 45 As 5b, the source electrode layer or drain electrode layer 405a or 405b shown in Embodiment 1 It can be formed in the same manner as above.

[0086] 4A to 4D are cross-sectional views showing a manufacturing process of a thin film transistor 460. FIG.

[0087] A gate electrode layer 451 is provided over a substrate 450 having an insulating surface. An insulating layer may be provided between the substrate 450 and the gate electrode layer 451. These layers have the function of preventing the diffusion of impurity elements, and are silicon nitride layers, silicon oxide layers, and silicon oxynitride layers. or a silicon oxynitride layer. The gate electrode layer 451 has a shape similar to that of the gate electrode layer 401 described in Embodiment 1. It can be achieved.

[0088] A gate insulating layer 452 is formed over the gate electrode layer 451 .

[0089] The gate insulating layer 452 can be formed in a manner similar to that of the gate insulating layer 402 described in Embodiment 1. can.

[0090] A conductive layer is formed on the gate insulating layer 452, and an island-shaped source is formed by a photolithography process. The electrode or drain electrode layers 455a and 455b are formed (see FIG. 4A).

[0091] The source and drain electrode layers 455a and 455b are the same as those in the source and drain electrode layers shown in Embodiment 1. The electrode or drain electrode layers 405a and 450b can be formed in a similar manner.

[0092] Next, the gate insulating layer 452 and the source and drain electrode layers 455a and 455b are and forming an island-shaped oxide semiconductor layer 48 on the insulating layer 41 by a photolithography process. The resulting oxide semiconductor layer is processed into a first oxide semiconductor layer 3 (see FIG. 4B).

[0093] The oxide semiconductor layer 483 serves as a channel formation region. The same is formed as above.

[0094] Note that before the oxide semiconductor layer 483 is formed by a sputtering method, argon gas is introduced. The reverse sputtering is performed by introducing the silicon into the gate insulating layer 452 to generate plasma, and the silicon is deposited on the surface of the gate insulating layer 452. It is preferable to remove any debris that may be present.

[0095] The oxide semiconductor layer 483 is subjected to heat treatment for dehydration or dehydrogenation and then subjected to a thermal treatment in an oxygen atmosphere. It is preferable to carry out the slow cooling under an inert gas atmosphere. The heat treatment is preferably performed in an oxygen atmosphere at a temperature of 200° C. or higher and lower than the distortion point of the substrate. Heat treatment is performed at 400°C to 700°C. This process results in dehydration or dehydrogenation. The oxide semiconductor layer 453 (second oxide semiconductor layer) can be formed by etching the oxide semiconductor layer 453 (FIG. 4C). reference.).

[0096] In the heat treatment for dehydration or dehydrogenation, the oxygen atmosphere contains moisture, hydrogen, etc. It is preferable that the gas having oxygen atoms, nitrogen, etc., introduced into the heat treatment device is not mixed with the gas. or rare gases such as helium, neon, argon, etc., with a purity of 6N (99.9999%) or more Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0097] In addition, the heat treatment of the oxide semiconductor layer in an oxygen atmosphere can process the oxide semiconductor layer into an island-shaped oxide semiconductor layer. In this case, the oxide semiconductor layer is oxidized in an oxygen atmosphere. After the heat treatment of the semiconductor layer, it is preferable to gradually cool the layer to a temperature of room temperature or higher and lower than 100° C. The substrate is then removed from the heating apparatus and a photolithography process is carried out.

[0098] After the heat treatment in an oxygen atmosphere, the oxide semiconductor layer 453 is in an amorphous state. However, partial crystallization is permitted.

[0099] Next, an oxide semiconductor layer 453 is formed on the oxide semiconductor layer 453 by a sputtering method or a PCVD method. An insulating layer 457 is formed. In this embodiment, the oxide insulating layer 457 is formed with a thickness of 300 nm. The substrate temperature during the formation is set to room temperature or higher and 300° C. or lower. In this embodiment, the temperature is set to 100° C. Then, an oxide insulating layer 457, which is a silicon oxide layer, is formed by a sputtering method. During the manufacturing process, heat treatment for dehydration or dehydrogenation in an oxygen atmosphere, By slow cooling in a nitrogen atmosphere or an inert gas atmosphere and forming an oxide insulating layer, A highly reliable thin film transistor 460 can be manufactured (see FIG. 4D).

[0100] After a silicon oxide layer to be the oxide insulating layer 457 is formed, The thin film transistor 460 is subjected to a heat treatment (preferably at least 150° C. and less than 350° C.) in For example, a heat treatment may be performed at 250° C. for 1 hour in a nitrogen atmosphere. The insulating layer 453 is heated in a state where the insulating layer 453 is in contact with the oxide insulating layer 457. By using this method, it is possible to reduce the variation in the electrical characteristics of the thin film transistor 460. The treatment (preferably at 150° C. or higher and lower than 350° C.) may be performed after the oxide insulating layer 457 is formed. There is no particular limitation, and other processes, such as a heat treatment during the formation of a resin layer, or a process for reducing the resistance of a transparent conductive layer, By combining this with the heat treatment for bonding the substrate, the number of steps can be reduced.

[0101] In addition, this embodiment mode can be freely combined with the first embodiment mode.

[0102] (Embodiment 3) A manufacturing process of a semiconductor device including a thin film transistor will be described with reference to FIGS. .

[0103] In FIG. 6A, the light-transmitting substrate 100 is the substrate 100 shown in the first embodiment. It can be used appropriately.

[0104] Next, a conductive layer is formed on the entire surface of the substrate 100, and then a first photolithography process is performed. A resist mask is formed, and unnecessary parts are removed by etching to form wiring and electrodes (gate A gate wiring including an electrode layer 101, a capacitance wiring 108, and a first terminal 121) are formed. At this time, etching is performed so that at least the end of the gate electrode layer 101 is tapered. do.

[0105] The gate wiring including the gate electrode layer 101, the capacitance wiring 108, and the first terminal 121 of the terminal portion are The materials for the gate electrode layer 401 described in Embodiment 1 can be used as appropriate. When the base electrode layer 101 is made of a heat-resistant conductive material, titanium (Ti), tantalum (T a), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Nd (Neodymium), An element selected from scandium (Sc), or an alloy containing the above elements, or The layer is formed of an alloy layer that combines the above elements, or a nitride layer that contains the above elements.

[0106] Next, a gate insulating layer 102 is formed on the entire surface of the gate electrode layer 101. The gate insulating layer 02 can be formed in a manner similar to that of the gate insulating layer 402 described in Embodiment 1. The thickness of the gate insulating layer 102 is set to 50 to 250 nm.

[0107] For example, a silicon oxide layer is formed as the gate insulating layer 102 by sputtering. It is formed to a thickness of m.

[0108] Next, an oxide semiconductor layer (In-Ga-Zn-O-based non-single crystal layer) is formed on the gate insulating layer 102. After the gate insulating layer 102 is formed, an In-Ga-Zn-O-based The formation of a non-single crystal layer prevents dust and moisture from adhering to the interface between the gate insulating layer and the semiconductor layer. Here, an oxide semiconductor containing In, Ga, and Zn with a diameter of 8 inches is used. Target (In-Ga-Zn-O oxide semiconductor target (In 2 O 3 :Ga 2 O 3 ZnO=1:1:1) was used, and the distance between the substrate and the target was set to 170 mm, and the pressure 0.4 Pa, DC power supply 0.5 kW, oxygen, argon, or argon and oxygen It is formed in a mixed atmosphere. If a pulsed direct current (DC) power supply is used, dust can be reduced. The thickness distribution is also uniform, which is preferable. The thickness of the In-Ga-Zn-O system non-single crystal layer is 5 The oxide semiconductor layer is an In-Ga-Zn-O oxide semiconductor. Using a target, a 50 nm thick In-Ga-Zn-O system non-monocrystalline A crystal layer is formed.

[0109] The sputtering method uses a high-frequency power source as the sputtering power source. and DC sputtering, which uses a DC power source. There is also a pulsed DC sputtering method that applies a bias. RF sputtering is mainly used for insulating The DC sputtering method is mainly used to form a metal layer. can be done.

[0110] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The puttering device can form different layers in the same chamber, or multiple layers in the same chamber. It is also possible to form the electrode by discharging a plurality of types of materials simultaneously.

[0111] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. E using a plasma generating device using microwaves instead of glow discharge. There is a sputtering device that uses the CR sputtering method.

[0112] In addition, as a method of forming a film using a sputtering method, the target material and the sputtering are Reactive sputtering is a method of forming a thin layer of a compound by chemically reacting the gas components with the There is also a bias sputtering method in which a voltage is also applied to the substrate during formation.

[0113] Next, a second photolithography process is performed to form a resist mask, and the oxide semiconductor layer For example, wet etching is performed using a solution of phosphoric acid, acetic acid, and nitric acid. In this manner, unnecessary portions are removed to form the oxide semiconductor layer 133 (see FIG. 6A). The etching method used here is not limited to wet etching, and dry etching may also be used. good.

[0114] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. Chlorine (Cl 2 ), boron chloride (BCl 3 ), silicon chloride (SiCl 4 ), carbon tetrachloride (CC l 4 ) etc.) are preferred.

[0115] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF 4 ), sulfur fluoride (SF 6 ), nitrogen fluoride (NF 3 ), trifluoromethane (CHF 3 ), hydrogen bromide (HBr ), oxygen (O 2), and adding rare gases such as helium (He) and argon (Ar) to these gases. Additive gases, etc. can be used.

[0116] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0117] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0118] In addition, the etching solution after wet etching is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium, etc. contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0119] In order to etch the desired shape, the etching conditions (etching Adjust the etching conditions (liquid, etching time, temperature, etc.) as appropriate.

[0120] Next, heat treatment is performed on the oxide semiconductor layer 133 for dehydration or dehydrogenation. Conductive layer 133 is subjected to a heat treatment in an oxygen atmosphere, and then is cooled in an oxygen atmosphere or an inert atmosphere. It is preferable to slowly cool the mixture in a room temperature atmosphere.

[0121] The heat treatment is carried out at a temperature of 200° C. or higher and lower than the distortion point of the substrate, preferably 400° C. or higher and 700° C. or lower. For example, an oxide semiconductor layer that has been subjected to heat treatment at 450° C. for 1 hour in an oxygen atmosphere is The layer is shown as an organic semiconductor layer 134 (see FIG. 6(B)).

[0122] Next, the conductive layer 132 made of a metal material is formed on the oxide semiconductor layer 134 by sputtering or a vacuum deposition method. It is formed by vacuum deposition method (see FIG. 6(C)).

[0123] The conductive layer 132 can be formed from a material similar to that of the source or drain electrode layer 4 shown in Embodiment 1. Materials similar to those for 05a and 405b can be used as appropriate.

[0124] When a heat treatment is performed after the formation of the conductive layer 132, the conductive layer is required to have heat resistance sufficient to withstand the heat treatment. It is preferable to have it.

[0125] Next, a third photolithography process is performed to form a resist mask and to form a By removing unnecessary portions, the source electrode layer or the drain electrode layer 105a, 105b, and The second terminal 122 is formed (see FIG. 6(D)). For example, the conductive layer 132 is made of aluminum. When using a layer or an aluminum alloy layer, a solution of phosphoric acid, acetic acid, and nitric acid was used. Wet etching can be performed. In addition, ammonia hydrogen peroxide (31% by weight hydrogen peroxide) can be used. The conductive layer was then removed by wet etching using a mixture of 28% ammonia water and 5:2:2 water. The electrode layer 132 is etched to form the source electrode layer or the drain electrode layer 105a, 105b. In this etching step, the exposed region of the oxide semiconductor layer 134 may also be partially etched. The oxide semiconductor layer 103 is thus formed by etching the source electrode layer or the drain electrode layer. The oxide semiconductor layer 103 between 105a and 105b is a thin region. In the present embodiment, the source electrode layer or drain electrode layer 105a, 105b, the oxide semiconductor layer 10 3 is etched at once by dry etching, The ends of the oxide semiconductor layer 103 and the electrode layers 105a and 105b are aligned with each other, forming a continuous structure. It has become.

[0126] In addition, in the third photolithography process, the source electrode layer or the drain electrode layer The second terminal 122, which is made of the same material as 105a and 105b, is left in the terminal portion. The terminal 122 is a source wiring (a solenoid including the source electrode layer or the drain electrode layer 105a, 105b). The base wiring is electrically connected to the

[0127] Also, a resist having regions of multiple thicknesses (typically two types) formed by a multi-tone mask is used. By using a photomask, the number of resist masks can be reduced, simplifying the process and reducing costs. Cost reduction is possible.

[0128] Next, the resist mask is removed, and the gate insulating layer 102, the oxide semiconductor layer 103, and the source electrode An oxide insulating layer 107 is formed to cover the electrode layers 105a and 105b. The oxide insulating layer 107 is a silicon oxynitride layer formed by a PCVD method. The substrate temperature during the formation of the 07 film may be set to room temperature or higher and 300° C. or lower. In this embodiment, the substrate temperature is set to 100 The oxide film provided between the source and drain electrode layers 105a and 105b is The exposed region of the compound semiconductor layer 103 is in contact with a silicon oxynitride layer which is an oxide insulating layer 107. By this, a highly reliable thin film transistor can be manufactured (Figure 7(A)). reference.).

[0129] Next, heat treatment may be performed after the oxide insulating layer 107 is formed. The heating may be performed in a nitrogen atmosphere or in a nitrogen atmosphere at a temperature of 150° C. or higher and lower than 350° C. When the treatment is performed, the oxide semiconductor layer 103 is heated in a state of being in contact with the oxide insulating layer 107. This improves the electrical characteristics of the thin film transistor and reduces the variation in the electrical characteristics. This heat treatment (preferably at 150° C. or higher and lower than 350° C.) is performed to form the oxide insulating layer 1 There are no particular limitations on the process as long as it is after the formation of the resin layer 07, and other processes, such as heat treatment during resin layer formation and permeability This process also serves as a heat treatment to reduce the resistance of the transparent conductive layer, so there is no need to increase the number of steps. It is possible.

[0130] Through the above steps, the thin film transistor 170 can be fabricated.

[0131] Next, a fourth photolithography process is performed to form a resist mask, and the oxide insulating layer 1 07 and the gate insulating layer 102 are etched to form the source electrode layer or the drain electrode layer 105 A contact hole 125 is formed that reaches the second A contact hole 127 reaching the terminal 122, a contact hole 128 reaching the first terminal 121, A cross-sectional view at this stage is shown in FIG.

[0132] Next, after removing the resist mask, a transparent conductive layer is formed. Indium oxide (In 2 O 3) and indium tin oxide alloy (In 2 O 3 - SnO 2 The film is formed by sputtering or vacuum deposition using a material such as ITO. The etching process for such materials is carried out with a hydrochloric acid-based solution. Indium oxide is used to improve etching processability because etching tends to leave residue. Zinc alloy (In 2 O 3 In order to reduce the resistance of the transparent conductive layer, When heat treatment is performed for the purpose of improving the electrical characteristics of the thin film transistor and reducing the variation in the electrical characteristics, This can also serve as a heat treatment to reduce cracks.

[0133] Next, a fifth photolithography process is performed to form a resist mask and to form a Then, unnecessary portions are removed to form the pixel electrode layer 110.

[0134] In addition, in this fifth photolithography process, the gate insulating layer 102 in the capacitance section The oxide insulating layer 107 serves as a dielectric, and the capacitance wiring 108 and the pixel electrode layer 110 form a storage capacitance. A quantity is formed.

[0135] In the fifth photolithography process, the first terminal 121 and the second terminal 1 22 is covered with a resist mask to leave the transparent conductive layers 128 and 129 formed on the terminal portions. The conductive layers 128 and 129 serve as electrodes or wiring used for connection to an FPC. The transparent conductive layer 128 formed on the gate electrode 121 is a connection layer that functions as an input terminal of the gate wiring. The transparent conductive layer 129 formed on the second terminal 122 serves as a terminal electrode of the source line. This is a connection terminal electrode that functions as an input terminal.

[0136] Next, the resist mask is removed, and the cross-sectional view at this stage is shown in FIG. The plan view at this stage is shown in FIG.

[0137] 9(A1) and 9(A2) are a cross-sectional view and a plan view of the gate line terminal portion at this stage. 9(A1) is a cross-section taken along line E1-E2 in FIG. 9(A2). In FIG. 9(A1), a transparent conductive layer 1 is formed on an oxide insulating layer 154. 55 is a terminal electrode for connection that functions as an input terminal. In the terminal section, a first terminal 151 formed of the same material as the gate wiring and a second terminal 152 formed of the same material as the source wiring are provided. The gate insulating layer 152 is formed of the same material as the connection electrode layer 153, and the connection electrode layer 153 overlaps the gate insulating layer 152 via the gate insulating layer 152. The transparent conductive layer 128 and the first terminal 155 shown in FIG. The portion where the transparent conductive layer 155 and the first terminal 151 are in contact with each other is the portion where the transparent conductive layer 155 and the first terminal 151 are in contact with each other. It corresponds to the part in contact.

[0138] Also, FIG. 9(B1) and FIG. 9(B2) show a gate line terminal portion different from that shown in FIG. 7(C). 9(B1) shows a cross-sectional view and a plan view of the source wiring terminal portion. This corresponds to a cross-sectional view taken along the line F1-F2 in FIG. 9(B2). The transparent conductive layer 155 formed on the solid insulating layer 154 is a connection terminal that functions as an input terminal. In FIG. 9(B1), the terminal portion is made of the same material as the gate wiring. The electrode layer 156 is gated below the second terminal 150 which is electrically connected to the source line. The electrode layer 156 is electrically connected to the second terminal 150. The electrode layer 156 is set to a potential different from that of the second terminal 150, for example, floating or GND. , 0V, etc., a capacitance for noise countermeasures or a capacitance for static electricity countermeasures will be formed. The second terminal 150 can be formed by connecting a transparent conductive layer 152 to an oxide insulating layer 154. 155 and is electrically connected.

[0139] A plurality of gate lines, source lines, and capacitance lines are provided according to the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, The terminal 2 and the third terminal of the same potential as the capacitance wiring are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0140] In this way, five photolithography steps were performed using five photomasks to produce the bottom A pixel thin film having a thin film transistor 170 which is a gate-type staggered thin film transistor. The film transistor and storage capacitor can then be completed. By forming a pixel section by correspondingly arranging them in a matrix, an active matrix type It can be one of the substrates for manufacturing a display device. Such a substrate is called an active matrix substrate.

[0141] When manufacturing an active matrix type liquid crystal display device, an active matrix substrate A liquid crystal layer is provided between the active matrix substrate and a counter substrate having a counter electrode. The counter electrode is fixed to the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for

[0142] In addition, the capacitance wiring is not provided, and the pixel electrode is connected to the gate wiring of the adjacent pixels, the oxide insulating layer, and the gate A storage capacitor may be formed by stacking the layers with an insulating layer interposed therebetween.

[0143] In an active matrix type liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the pixel electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0144] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, resulting in image retention. In order to improve the moving image characteristics of the LCD device, There is a driving technique called black insertion, which displays black every other frame.

[0145] In addition, the video characteristics can be improved by increasing the normal vertical sync frequency by 1.5 or 2 times or more. There is also a driving technology called double speed driving.

[0146] In addition, in order to improve the video characteristics of liquid crystal display devices, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode) light source or multiple EL light sources, etc., and a surface light source is formed. There is also a driving technology that drives each light source to light intermittently within one frame period. In addition, three or more types of LEDs may be used, or white-emitting LEDs may be used. Since multiple LEDs can be controlled, the LE can be switched according to the timing of the optical modulation of the liquid crystal layer. The timing of the LEDs can also be synchronized. This is particularly useful when displaying images with a large proportion of black areas occupying the entire screen. This has the effect of reducing power consumption.

[0147] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the conventional method.

[0148] The n-type transistor disclosed in this specification uses an oxide semiconductor layer in a channel formation region. It has good dynamic properties and allows these drive technologies to be combined.

[0149] In addition, when a light-emitting display device is manufactured, one electrode (also called a cathode) of the organic light-emitting element is In order to set the low power supply potential, for example GND or 0V, the cathode is connected to the terminal. A fourth terminal is provided for setting the voltage level, for example, GND, 0V, etc. When manufacturing a device, a power supply line is provided in addition to a source line and a gate line. Therefore, the terminal section is provided with a fifth terminal that is electrically connected to the power supply line.

[0150] In addition, when manufacturing a light-emitting display device, a partition using an organic resin layer is provided between each of the organic light-emitting elements. In that case, the organic resin layer is heat-treated, so the electrical properties of the thin film transistor are This can also serve as a heat treatment to improve characteristics and reduce variations in electrical characteristics.

[0151] By forming the thin film transistor using an oxide semiconductor, the manufacturing cost can be reduced. In particular, the heat treatment for dehydration or dehydrogenation removes the moisture, which is an impurity, In order to reduce the amount of oxygen and increase the purity of the oxide semiconductor layer, the dew point in the formation chamber has been lowered. The electrical properties are excellent without using a special sputtering device or an ultra-high purity oxide semiconductor target. Thus, a semiconductor device having a thin film transistor with good electrical conductivity and high reliability can be manufactured.

[0152] The electrical characteristics of the thin film transistor are stabilized by heat treatment of the oxide semiconductor layer in an oxygen atmosphere. This stabilizes the resistance of the device and prevents an increase in the off-state current. This results in good electrical characteristics and high reliability. It is possible to provide a semiconductor device having a thin film transistor with excellent characteristics.

[0153] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0154] (Embodiment 4) In this embodiment, an example in which some steps are different from those in the first embodiment is shown. After the formation of the source electrode layer or drain electrode layer 405a, 405b, dehydration or dehydrogenation is performed. The form in which the heat treatment is performed is shown in FIG. 10. Note that the same parts as those in FIG. 1 are described using the same reference numerals. do.

[0155] As in the first embodiment, a gate electrode layer 401 and a gate insulator layer 402 are formed on a substrate 400 having an insulating surface. An insulating layer 402 and an oxide semiconductor layer 430 are formed (see FIG. 10A).

[0156] The source and drain electrode layers 405a and 405b are formed over the oxide semiconductor layer 430. Then, the oxide semiconductor layer 430 is partially etched to form an oxide semiconductor layer 441 (FIG. 1 See 0(B). ).

[0157] Next, the oxide semiconductor layer 441 and the source and drain electrode layers 405a and 405 It is preferable to subject b to a heat treatment and slow cooling in an oxygen atmosphere. Thus, the oxide semiconductor layer 441 is subjected to a dehydration treatment or a dehydrogenation treatment, and the oxide semiconductor layer 4 10C. The source or drain electrode layer 403 is formed (see FIG. 10C). The materials of 05a and 405b are materials that can withstand the heat treatment here, such as tungsten and molybdenum. It is preferable to use butene or the like.

[0158] After the heat treatment, a sputtering agent was applied to the oxide semiconductor layer 403 without exposure to air. An oxide insulating layer 407 is formed by deposition or PCVD. The oxide semiconductor layer 403 is then in contact with the oxide semiconductor layer 403 by a sputtering method or a PCVD method. By forming the insulating layer 407, a thin film transistor 470 can be manufactured (FIG. 1 See 0(D). ).

[0159] By performing the heat treatment for the dehydration treatment or the dehydrogenation treatment, H 2 It is preferable to gradually cool the mixture after reducing impurities such as O, H, and OH. The oxide insulating layer is formed in contact with the oxide semiconductor layer, and the like, to improve the reliability of the thin film transistor 470. It can improve the sex.

[0160] After the oxide insulating layer 407 is formed, heat treatment is performed in an oxygen atmosphere or a nitrogen atmosphere. (preferably 150° C. or higher and lower than 350° C.) may be used. For example, the reaction may be carried out in a nitrogen atmosphere for 25 Heat treatment is performed at 0° C. for 1 hour. By the heat treatment, the oxide semiconductor layer 403 becomes an oxide The thin film transistor 470 is heated while in contact with the insulating layer 407, and the electrical characteristics of the thin film transistor 470 are This can reduce gender variability.

[0161] In addition, this embodiment mode can be freely combined with the first embodiment mode.

[0162] (Embodiment 5) A semiconductor device and a manufacturing method thereof will be described with reference to FIGS. The parts or parts having similar functions and steps can be performed in the same manner as in embodiment 1. , and a repeated explanation will be omitted.

[0163] The thin film transistor 471 illustrated in FIG. In this example, a conductive layer 409 is provided so as to overlap with a channel region with an oxide insulating layer 407 interposed therebetween. .

[0164] 11 is a cross-sectional view of a thin film transistor 471 included in the semiconductor device. 471 is a bottom gate type thin film transistor, and 472 is a substrate having an insulating surface. 00, a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, and a the source or drain electrode layers 405a and 405b, the oxide insulating layer 407, and the conductive layer 409 The conductive layer 409 is formed on the oxide insulating layer 407 so as to overlap with the gate electrode layer 401. It is provided.

[0165] The conductive layer 409 is a gate electrode layer 401, a source electrode layer or a drain electrode layer 405a, It can be formed using the same material and method as 05b. When a pixel electrode layer is provided, The conductive layer 40 may be formed using the same material and method as the pixel electrode layer. 9 is a laminate of a titanium layer, an aluminum layer, and a titanium layer.

[0166] The conductive layer 409 may have a potential equal to or different from that of the gate electrode layer 401. The conductive layer 409 can also function as a gate electrode layer of the floating gate electrode 402. It may be in a state.

[0167] By providing the conductive layer 409 so as to overlap with the oxide semiconductor layer 403, a thin film transistor can be formed. In the bias-thermal stress test (hereinafter referred to as BT test) to check the reliability of the In this way, the threshold voltage of the thin film transistor 471 before and after the BT test can be controlled. In particular, after the substrate temperature is raised to 150°C, the voltage applied to the gate is set to -20V. This can reduce the variation in threshold voltage in the MOSFET-BT test.

[0168] This embodiment mode can be freely combined with the first embodiment mode.

[0169] (Embodiment 6) A semiconductor device and a manufacturing method thereof will be described with reference to FIG. The parts or parts having similar functions and steps can be performed in the same manner as in embodiment 1. , and a repeated explanation will be omitted.

[0170] The thin film transistor 472 illustrated in FIG. A conductive layer 419 is formed on the channel region via an oxide insulating layer 407 and an insulating layer 410. This is an example of setting

[0171] 12 is a cross-sectional view of a thin film transistor 472 included in the semiconductor device. 472 is a bottom gate type thin film transistor, and 473 is a substrate having an insulating surface. 00, a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source region and a source or drain region 404a, 404b, a source or drain electrode layer 405a. , 405b, an oxide insulating layer 407, an insulating layer 410, and a conductive layer 419. The insulating layer 410 is provided on the oxide insulating layer 407 so as to overlap the gate electrode layer 401. It is being done.

[0172] In this embodiment, an oxide semiconductor layer is formed over the gate insulating layer 402 as in Embodiment 1. The source and drain regions 404a and 404b are formed on the oxide semiconductor layer. Before or after the formation of the source and drain regions 404a and 404b, the source and drain regions 404a and 404b are etched in an oxygen atmosphere. After heat treatment in an atmosphere of oxygen, the material is cooled slowly in an atmosphere of oxygen or an inert gas. It is preferable to carry out the following.

[0173] In this embodiment, the source and drain regions 404a and 404b are made of Zn-O based polycrystalline silicon. The oxide semiconductor layer 403 is a Zn-based microcrystalline layer or a Zn-based microcrystalline layer, and is formed under conditions different from those for forming the oxide semiconductor layer 403. In this embodiment, the source region and the drain region are formed of The regions 404a and 404b are polycrystalline or microcrystalline. The oxide semiconductor layer 403 is also in a polycrystalline state or a microcrystalline state. The crystal can be made polycrystalline or microcrystalline.

[0174] In this embodiment, an insulating layer 410 serving as a planarization layer is stacked over the oxide insulating layer 407. The oxide insulating layer 407 and the insulating layer 410 are covered with the source or drain electrode layer 405b. An opening is formed in the insulating layer 410, the oxide insulating layer 407, and the insulating layer 410. A conductive layer is formed in the opening, and is etched into a desired shape to form the conductive layer 419 and the pixel electrode layer 4 In this manner, in the process of forming the pixel electrode layer 411, the same materials and methods are used. In this embodiment, the pixel electrode layer 411 and the conductive layer 419 can be formed using the same. The conductive layer 419 is an indium oxide tin oxide alloy containing silicon oxide (In-S nO-based oxides) are used.

[0175] The conductive layer 419 is formed on the gate electrode layer 401 and the source or drain electrode layer 405. They may be formed using the same materials and methods as those for 405a and 405b.

[0176] The conductive layer 419 may have the same potential as the gate electrode layer 401. The conductive layer 419 can also function as a second gate electrode layer. 419 may be in a floating state.

[0177] By providing the conductive layer 419 so as to overlap with the oxide semiconductor layer 403, a thin film transistor The threshold voltage of the transistor can be controlled.

[0178] This embodiment mode can be freely combined with the first embodiment mode.

[0179] (Embodiment 7) In this embodiment, an example of a channel stop type thin film transistor 1430 will be described with reference to FIG. 3(A), 13(B) and 13(C). Also, FIG. 13(C) shows a thin film transistor. FIG. 13(B) is an example of a top view of a resistor, and a cross-sectional view taken along the chain line Z1-Z2 in the figure is shown. In addition, the oxide semiconductor layer of the thin film transistor 1430 is formed of an oxide semiconductor material that does not contain gallium. An example using a solid semiconductor material is shown below.

[0180] In FIG. 13A, a gate electrode layer 1401 is provided over a substrate 1400. An oxide semiconductor layer is formed on a gate insulating layer 1402 that covers the gate electrode layer 1401 .

[0181] In this embodiment, a Sn-Zn-O system is used as the oxide semiconductor layer by sputtering. An oxide semiconductor is used. Since gallium is not used in the oxide semiconductor layer, Since no target is required, costs can be reduced.

[0182] Immediately after the formation of the oxide semiconductor layer or after the patterning of the oxide semiconductor layer, dehydration or decomposition To hydrogenate the material, heat treatment is performed under an oxygen atmosphere, and then the material is placed in an oxygen atmosphere or in an inert atmosphere. It is preferable to perform slow cooling in a gas atmosphere. The heat treatment is performed at a temperature of 200° C. or higher but lower than the distortion point of the substrate. The temperature is preferably from 400° C. to 700° C. The oxide semiconductor layer is heated in an oxygen atmosphere. By the heat treatment, an oxide semiconductor layer 1403 can be formed (see FIG. 13A). In this embodiment, the oxide semiconductor layer 1403 is in a microcrystalline state or a polycrystalline state.

[0183] Next, a channel protective layer 1418 is provided over and in contact with the oxide semiconductor layer 1403. By providing a protective layer 1418, the source and drain regions 1406a, Damage during the 1406b formation process (due to plasma or etching agent during etching) Therefore, the reliability of the thin film transistor 1430 can be improved. It is possible.

[0184] After the dehydration or dehydrogenation, the channel protection layer 141 is continuously formed without being exposed to the air. By continuously treating the film without exposing it to air, the interface Contaminated by atmospheric components and impurities suspended in the air, such as moisture and hydrocarbons. Since each lamination interface can be formed without any trouble, the variation in thin film transistor characteristics can be reduced. It can be reduced.

[0185] In addition, a semiconductor layer 1403 that has been dehydrated or dehydrogenated is contacted with a Alternatively, a channel protection layer 1418, which is an oxide insulating layer, is formed by a method such as PCVD. A thin film having a dehydrated or dehydrogenated oxide semiconductor layer 1403 in a channel formation region. A transistor can be fabricated.

[0186] The channel protection layer 1418 is made of an inorganic material containing oxygen (silicon oxide, silicon oxynitride, nitride, etc.). The material used for the fabrication of the SiO2 thin film is silicon oxide. The fabrication method is plasma CVD or thermal CVD. The channel protection layer 1418 may be formed by a vapor deposition method such as a sputtering method or the like. After the formation, the shape is processed by etching. A silicon oxide layer is formed and then etched using a photolithographic mask. Together, this forms a channel protection layer 1418.

[0187] Next, a source region and a drain region are formed on the channel protection layer 1418 and the oxide semiconductor layer 1403. In this embodiment, source or drain regions 1406a and 1406b are formed. The regions 1406a and 1406b are Zn-O based microcrystalline layers or Zn-O based polycrystalline layers. The oxide semiconductor layer 1403 is formed under different conditions from the oxide semiconductor layer 1403, and has a lower resistance. The source and drain regions 1406a and 1406b are made of nitride semiconductor layers. The Al-Zn-O non-single crystal layer contains ZnO, i.e., the Al-Zn-ON non-single crystal layer (AZ A layer (also called an ON layer) may be used.

[0188] Next, a source electrode layer 1405a is formed on the source region 1406a, and a drain electrode layer 1406b is formed on the drain region 1406b. A drain electrode layer 1405b is formed on each of the first and second electrodes 1405a and 1405b to fabricate a thin film transistor 1430 ( (see FIG. 13B). The source electrode layer 1405a and the drain electrode layer 1405b are The source electrode layer 405a and the drain electrode layer 405b can be formed similarly to those in the first embodiment. can.

[0189] The source and drain regions 1406a and 1406b are formed by the oxide semiconductor layer 1403 and the By providing the metal layer between the source electrode layer 1405a and the drain electrode layer 1405b, A source electrode layer 1405a, a drain electrode layer 1405b, and an oxide semiconductor layer 1403 This provides a good junction between the layers, and provides thermal stability compared to a Schottky junction. By reducing the resistance of the source region and the drain region 1406a, 1406b, a high drain Good mobility can be maintained even at high voltages.

[0190] In addition, the structure is not limited to the above-mentioned source and drain regions 1406a and 1406b. For example, a structure in which the source region and the drain region are not provided may be used.

[0191] After the channel protection layer 1418 is formed, a thin film transistor is formed in an oxygen or nitrogen atmosphere. The transistor 1430 is subjected to a heat treatment (preferably at 150° C. or higher and lower than 350° C.). For example, The heat treatment is then carried out at 250° C. for 1 hour in a nitrogen atmosphere. The dielectric layer 1403 is heated while in contact with the channel protection layer 1418, forming a thin film transistor. This heat treatment (preferably or 150° C. or higher and lower than 350° C.) is not particularly limited after the channel protection layer 1418 is formed. However, other processes, such as a heat treatment during resin layer formation and a process for reducing the resistance of the transparent conductive layer, may be used. By combining this with the heat treatment for the purpose, it is possible to carry out the process without increasing the number of steps.

[0192] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0193] (Embodiment 8) A semiconductor device and a manufacturing method thereof will be described with reference to FIGS. 14A and 14B. The same parts as those in the seventh embodiment or parts and steps having similar functions are the same as those in the seventh embodiment. The above process can be carried out in the same manner, and a repeated explanation will be omitted.

[0194] A thin film transistor 1431 shown in FIG. 14A includes a gate electrode layer 1401 and an oxide semiconductor A channel protection layer 1418 and an insulating layer 1407 are formed so as to overlap the channel region of the dielectric layer 1403. In this example, a conductive layer 1409 is provided through a gap.

[0195] FIG. 14A is a cross-sectional view of a thin film transistor 1431 included in a semiconductor device. The transistor 1431 is a bottom-gate type thin film transistor, and is mounted on a substrate with an insulating surface. A gate electrode layer 1401, a gate insulating layer 1402, an oxide semiconductor layer 1403, and a gate insulating layer 1404 are formed on a substrate 1400. 1403, source region or drain region 1406a, 1406b, source electrode layer or It includes drain electrode layers 1405 a and 1405 b , an insulating layer 1407 , and a conductive layer 1409 . The conductive layer 1409 is provided over the insulating layer 1407 so as to overlap with the gate electrode layer 1401. is.

[0196] In this embodiment, as in Embodiment 1, an oxide semiconductor layer A source region and a drain region 1406a and 1406b are formed on the oxide semiconductor layer. Before or after the formation of the source and drain regions 1406a, 1406b. After performing a heat treatment for dehydration or dehydrogenation in an oxygen atmosphere, It is preferable to slowly cool the mixture under an atmosphere of nitrogen or an inert gas.

[0197] In this embodiment, a source region and a drain region are formed over the oxide semiconductor layer 1403. The regions 1406a and 1406b are Zn-O based microcrystalline layers or Zn-O based polycrystalline layers. The oxide semiconductor layer 1403 is formed under different conditions from the oxide semiconductor layer 1403, and has a lower resistance. The oxide semiconductor layer 1403 is in an amorphous state.

[0198] The conductive layer 1409 is a gate electrode layer 1401, a source electrode layer or a drain electrode layer 1405, and a The pixel electrode layer can be formed using the same materials and methods as those of the pixel electrode layer 1405a and 1405b. In this case, the conductive layer may be formed using the same material and method as the pixel electrode layer. The conductive layer 1409 is a stack of a titanium layer, an aluminum layer, and a titanium layer.

[0199] The conductive layer 1409 may have the same potential as the gate electrode layer 1401 or may have a different potential. The conductive layer 1409 can also function as a second gate electrode layer. The device may be in a ring state.

[0200] By providing the conductive layer 1409 so as to overlap with the oxide semiconductor layer 1403, a thin film transistor Bias-thermal stress test (hereinafter referred to as BT test) is used to check the reliability of transistors. In this case, the threshold voltage of the thin film transistor 1431 before and after the BT test is controlled. can be done.

[0201] FIG. 14(B) shows an example that is partially different from FIG. 14(A). The parts and steps having the same functions as those in FIG. 14(A) can be carried out repeatedly. The explanation of this will be omitted.

[0202] A thin film transistor 1432 shown in FIG. 14B includes a gate electrode layer 1401 and an oxide semiconductor A channel protection layer 1418, an insulating layer 1407 and a dielectric layer 1403 are formed so as to overlap the channel region of the dielectric layer 1403. In this example, a conductive layer 1409 is provided with an insulating layer 1408 interposed therebetween.

[0203] In this embodiment, as in Embodiment 1, an oxide semiconductor layer After the oxide semiconductor layer is formed, the oxide semiconductor layer is dehydrated or dehydrogenated in an oxygen atmosphere. After the heat treatment for the purpose, the material is slowly cooled in an oxygen atmosphere or an inert gas atmosphere. It is preferred.

[0204] In FIG. 14B, an insulating layer 1408 functioning as a planarizing layer is stacked over the insulating layer 1407. do.

[0205] In addition, in FIG. 14B, a source region or a drain region is not provided, and the oxide semiconductor layer 14 03 and the source electrode layer or the drain electrode layer 1405a, 1405b are in direct contact with each other. It is.

[0206] In the structure of FIG. 14B, the conductive layer 1409 is By providing the BT test for checking the reliability of thin film transistors, The threshold voltage of the thin film transistor 1432 before and after the T test can be controlled.

[0207] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0208] (Embodiment 9) In this embodiment, an example in which the structure is partially different from that of the first embodiment is shown in FIG. The same parts or parts having similar functions and steps can be performed in the same manner as in the first embodiment. Therefore, repeated explanation will be omitted.

[0209] In this embodiment, after the first oxide semiconductor layer is patterned, After heat treatment for dehydration or dehydrogenation, the material is cooled in an oxygen atmosphere or an inert gas atmosphere. The first oxide semiconductor layer is preferably cooled slowly under the above atmosphere. Thus, impurities such as hydrogen and moisture contained in the oxide semiconductor layer 403 can be removed. Cut.

[0210] Next, a source region and a drain region of a thin film transistor are formed on the first oxide semiconductor layer. After the second oxide semiconductor layer to be used as the second oxide semiconductor layer is formed, a conductive layer is formed.

[0211] Next, the first oxide semiconductor layer, the second oxide semiconductor layer, and the conductive layer are subjected to an etching process. By etching more selectively, the oxide semiconductor layer 403 and the source region or the drain region 404a, 404b, and source or drain electrode layers 405a, 405b are formed. Note that the oxide semiconductor layer 403 is only partially etched and has a groove (a depression). This becomes an oxide semiconductor layer.

[0212] Next, a silicon oxide film is formed on the oxide semiconductor layer 403 by a sputtering method or a PCVD method. The base layer is formed as an oxide insulating layer 407. The oxide insulating layer 407 formed in contact with the - There are few, Moisture and OH - The inorganic insulating layer prevents the intrusion of oxygen from the outside. A silicon nitride layer or a silicon nitride oxide layer is used. It may also be laminated.

[0213] The dehydrated or dehydrogenated oxide semiconductor layer 403 is contacted with a sputtering method or a PC By forming the oxide insulating layer 407 by a VD method or the like, a dehydrated or dehydrogenated oxide A thin film transistor 473 having a nitride semiconductor layer 403 in a channel forming region is fabricated. This is possible (see Figure 15).

[0214] In the structure in FIG. 15, the source and drain regions 404a and 404b are An In-Ga-Zn-O based non-single crystal layer is used. Also, the source region and the drain region 404 The Al-Zn-O amorphous layer can be used for the source region and the The drain regions 404a and 404b are made of an Al-Zn-O-based amorphous layer containing nitrogen, i.e. An Al-Zn-ON amorphous layer may also be used.

[0215] A source region is formed between the oxide semiconductor layer 403 and the source electrode layer. A drain region is provided between the gate electrode layer and the drain region.

[0216] In addition, the source region or drain region 404a, 404b of the thin film transistor 473 The second oxide semiconductor layer used as the channel formation region is a first oxide semiconductor layer used as the It is preferable that the thickness of the insulating layer is thinner than that of the insulating layer 10 and has a higher electrical conductivity.

[0217] The first oxide semiconductor layer used as the channel forming region has an amorphous structure, and the source region The second oxide semiconductor layer used as the drain region has an amorphous structure with crystal grains (nanocrysts). The second oxide used as the source and drain regions may include a silicon nitride film. The crystal grains (nanocrystals) in the semiconductor layer have a diameter of 1 nm to 10 nm, typically 2 nm to It is about 4nm.

[0218] After the oxide insulating layer 407 is formed, a thin film transistor is formed in an oxygen atmosphere or a nitrogen atmosphere. The transistor 473 may be subjected to a heat treatment (preferably at 150° C. or higher and lower than 350° C.). For example, heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The semiconductor layer 403 is heated in contact with the oxide insulating layer 407. This can reduce the variation in the electrical characteristics of the resistor 473.

[0219] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0220] (Embodiment 10) In this embodiment, at least a part of the driver circuit and a thin film transistor to be disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0221] The thin film transistor disposed in the pixel portion is formed according to any one of the first to ninth embodiments. In addition, since the thin film transistors described in any of the embodiments 1 to 9 are n-type TFTs, Among the driving circuits, a part of the driving circuit that can be configured with n-type TFTs is It is formed on the same substrate as the transistor.

[0222] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 includes a signal line driver circuit 5303 and a signal line driver circuit 5304. is arranged extending from a signal line driver circuit 5304, and a plurality of scanning lines are arranged in a first scanning line driver circuit The first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. At the intersections of the signal lines and the display elements, pixels each having a display element are arranged in a matrix. In addition, the substrate 5300 of the display device is a flexible printed circuit (FPC). A timing control circuit 5305 (controller, control I / F) is connected to the timing control circuit 5305 via a connection part such as a It is connected to the

[0223] In FIG. 16A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of external components such as drive circuits, and therefore reduces costs. In addition, when a driving circuit is provided outside the substrate 5300, the wiring is extended to provide a connection portion. The number of connections can be reduced, improving reliability and increasing yield.

[0224] The timing control circuit 5305 is, for example, The first scanning line driving circuit start signal (GSP1), the first scanning line driving circuit clock The timing control circuit 5305 also supplies the second scan line For example, a second scanning line driver circuit start signal (GSP2 ) (also called a start pulse), and a clock signal (GCLK2) for the second scanning line driving circuit. A start signal (SSP) for the signal line driver circuit is supplied to the signal line driver circuit 5304. Clock signal for line driver circuit (SCLK), data for video signal (DATA) (simply video The clock signals are also called clock signals (CLK, CLK+CLK, CLK+CLK+CLK), and latch signals (LAT). It can be multiple clock signals with different periods, or a signal that is an inverted clock signal (CKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 may be supplied together. It is possible to omit one of the scanning line driver circuit 5302 and the scanning line driver circuit 5303 .

[0225] In FIG. 16B, a circuit with a low driving frequency (for example, the first scanning line driving circuit 5302, The second scanning line driver circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to its structure, the field effect mobility is smaller than that of a transistor using a single crystal semiconductor. The driving circuit formed on the substrate 5300 can be configured by the thin film transistor. Therefore, it is possible to increase the size of the display device, reduce the number of steps, reduce costs, or improve yields. It is possible to achieve this.

[0226] The thin film transistors described in any of the embodiments 1 to 9 are n-type TFTs. 17(A) and 17(B) show the configuration and operation of a signal line driver circuit made up of n-type TFTs. An example will be given below.

[0227] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 includes switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a A plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) are provided. An example in which the thin film transistors 5603_1 to 5603_k are n-type TFTs will be described. Reveal.

[0228] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are respectively connected to the wiring 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0229] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , or high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in sequence.

[0230] The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have a function of controlling whether or not potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k The thin film transistor 56 has a function of supplying the potential to the signal lines S1 to Sk. Each of 03_1 to 5603_k has a function as a switch.

[0231] In addition, the wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is analog data corresponding to the image information or image signal. Often a logged signal.

[0232] Next, the operation of the signal line driver circuit of FIG. 17(A) will be described with reference to the timing chart of FIG. 17(B). FIG. 17B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. These are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is a period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0233] In the drawings of the present embodiment, the signal waveforms of the components are not rounded for clarity. Therefore, the scale may not necessarily be limited to the actual scale. It should be noted that

[0234] During the period T1 to the period TN, the shift register 5601 outputs an H-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. Since 5603_1 to 5603_k are turned on, wiring 5604_1 to 5604_k and signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to a selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, Then, the video signal data (DATA) is sent to the pixels in the selected row in order of k columns. It will be written.

[0235] As described above, video signal data (DATA) is written to the pixels in multiple columns. This allows the number of video signal data (DATA) or wiring to be reduced. This reduces the number of connections to external circuits. Also, the video signal is transmitted in multiple columns. By writing to the pixel, the writing time can be increased, and the writing of the video signal This can prevent insufficient filling.

[0236] The shift register 5601 and the switching circuit 5602 may be the same as those in the first embodiment. It is possible to use a circuit configured with the thin film transistors shown in the first to ninth embodiments. In this case, the polarity of all the transistors in the shift register 5601 is set to n-type or p-type. The polarity of the polarity sensor may be either one of the polarities.

[0237] Regarding one form of a shift register used as a part of a scanning line driver circuit and / or a signal line driver circuit, This will be described with reference to FIG. 18 and FIG.

[0238] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter or a buffer. In the scanning line driver circuit, a clock signal is input to the shift register. The selection signal is generated by inputting the clock (CLK) and start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scan line. The gate electrodes of the transistors of the pixels for one line are connected to the scanning line. Since the transistors of the pixels in one line must be turned on simultaneously, The capacitor used is capable of carrying a large current.

[0239] The shift register includes a first pulse output circuit 10_1 to an N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 18(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is output from a third wiring 13, and a fourth clock signal CK4 is output from a fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), the pulse output A signal (called the previous signal OUT(n-1)) (n is a natural number between 2 and N) is input from the circuit. In addition, in the first pulse output circuit 10_1, the third pulse output circuit 1 0_3, and in the n-th pulse output circuit 10_n from the second stage onwards, The signal from the (n+2)th pulse output circuit 10_n+2 (hereafter referred to as the subsequent signal OUT(n+2)) In addition, the pulse output circuit of each stage outputs the pulses of the previous and / or subsequent stages. a first output signal (OUT(1)(SR) to OUT(N)(SR) for input to the input circuit; ), and a second output signal (OUT(1) to OUT(N)) electrically connected to another wiring, etc. As shown in FIG. 18(A), the last two stages of the shift register have Since the subsequent signal OUT(n+2) is not input, for example, a second start-up signal A first start pulse SP2 and a second start pulse SP3 may be input.

[0240] The clock signal (CK) goes between H and L levels (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are The fourth clock signal (CK4) is delayed by 1 / 4 cycle in sequence. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is GCK depending on the input drive circuit. It is sometimes called SCK, but here we will use the term CK for explanation.

[0241] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 18(B)). The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 18A, the wiring 11 is electrically connected to any one of the wirings 11 to 14. In the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11. , the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10_2 In the example shown in FIG. 1, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is The third input terminal 23 is electrically connected to the fourth wiring 14. It has been done.

[0242] In the first pulse output circuit 10_1, a first clock signal CK is input to a first input terminal 21. 1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, and the third input The third clock signal CK3 is input to the terminal 23, and the first start A pulse SP1 is input, a subsequent signal OUT(3) is input to the fifth input terminal 25, and a first The first output signal OUT(1)(SR) is output from the output terminal 26, and the second output signal OUT(2)(SR) is output from the output terminal 2 7 outputs the second output signal OUT(1).

[0243] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are each a three-terminal thin-film transistor. In addition to the TFT, the four-terminal thin film transistor described in the above embodiment is used. In this specification, a thin film transistor may be formed by sandwiching two thin film transistors between a semiconductor layer. In the case where the gate electrode has a semiconductor layer, the gate electrode below the semiconductor layer is called the lower gate electrode. The gate electrode above the layer is also called the upper gate electrode.

[0244] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, The threshold voltage may shift to the negative or positive side depending on the process. Therefore, in a thin film transistor in which an oxide semiconductor is used for a semiconductor layer including a channel formation region, A configuration capable of controlling the threshold voltage is preferable. The threshold voltage can be adjusted to the desired value by controlling the potential of the upper and / or lower gate electrodes. The value can be controlled.

[0245] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. This is explained in (C).

[0246] The pulse output circuit shown in FIG. 18C includes a first transistor 31 to a thirteenth transistor. The power supply line 51 to which the first high power supply potential VDD is supplied, A power supply line 52 to which a power supply potential VCC is supplied and a power supply line 53 to which a low power supply potential VSS is supplied A signal or a power supply potential is supplied to the first transistor 31 to the thirteenth transistor 43. Here, the magnitude relationship of the power supply potentials of the power supply lines in FIG. 18C is as follows: VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is a third power supply potential The potential is higher than VSS. Note that the first clock signal (CK1) to the fourth clock signal The signal (CK4) is a signal that alternates between H and L levels at regular intervals. When the power supply line 51 is at a low level, the potential VDD is set to VSS when the power supply line 51 is at a low level. By raising the potential of line 52 above VCC, the transistor The potential applied to the gate electrode of the transistor can be kept low, and the threshold voltage of the transistor can be shifted. In addition, the first transistor 31 to the thirteenth transistor Among the transistors 43, the first transistor 31, the sixth transistor 36 to the ninth transistor It is preferable to use a four-terminal thin film transistor for the transistor 39. The operation of the sixth transistor 31, the sixth transistor 36 to the ninth transistor 39 is The potential of the node to which one of the electrodes, which will be the gate or drain, is connected is controlled by the control signal of the gate electrode. A transistor that is required to be switched by a control signal input to the gate electrode. The fast response to the on-state current (the rise of the on-state current) reduces the risk of malfunction of the pulse output circuit. Therefore, a four-terminal thin-film transistor is used. This allows the threshold voltage to be controlled, resulting in a pulse output that can reduce malfunctions. It can be a circuit.

[0247] In FIG. 18C, the first transistor 31 has a first terminal electrically connected to a power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; (the lower gate electrode and the upper gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal a gate electrode electrically connected to the first terminal of the ninth transistor 39 and a gate electrode electrically connected to the first terminal of the fourth transistor The third transistor 33 is electrically connected to the gate electrode of the first terminal The first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53, The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is The first terminal is electrically connected to the power supply line 53, and the second terminal is connected to the gate of the second transistor 32. The electrode of the fourth transistor 34 is electrically connected to the gate electrode of the fourth transistor 34. The sixth transistor 36 has a first terminal electrically connected to the power supply line 52, and the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 33. The gate electrode of the transistor 34 is electrically connected to the gate electrode of the transistor 34. The seventh transistor (the gate electrode of the seventh transistor) is electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and a gate electrode (a lower gate electrode and an upper gate electrode) electrically connected to the second terminal of the is electrically connected to the third input terminal 23. The eighth transistor 38 is is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrodes (the lower gate electrode and the upper gate electrode) are connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the second transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to The gate electrodes (the lower gate electrode and the upper gate electrode) are electrically connected to the power supply line 52. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 2. 1, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. 41 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the second output terminal 27. The gate electrodes of the second transistor 32 and the fourth transistor The twelfth transistor 42 is electrically connected to the gate electrode of the first terminal of the transistor 34. The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27. The gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 5 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode The seventh transistor 37 has a gate electrode (lower gate electrode and upper gate electrode) are electrically connected.

[0248] In FIG. 18C, the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 4 The connection point of the gate electrode of transistor 0 and the second terminal of transistor 939 is referred to as node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is node B. Let us assume that.

[0249] FIG. 19(A) shows the pulse output circuit described in FIG. 18(C) as a first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and a signal input to or output from a second output terminal 27.

[0250] Specifically, a first clock signal CK1 is input to the first input terminal 21, and A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse is input to the fourth input terminal 24, and a clock signal CK3 is input to the fifth input terminal 25. The next stage signal OUT(3) is input to the first output terminal 25, and the first output signal OUT (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. will be done.

[0251] A thin film transistor is defined as a transistor having at least three elements including a gate, a drain, and a source. A semiconductor device with a channel region formed in the region overlapping the gate. By controlling the gate potential, the drain and source are connected via the channel region. The current flowing between the source and drain can be controlled by the thin film transistor. Which is the source and which is the drain depends on the transistor structure and operating conditions, etc. Therefore, the regions that function as the source and drain are In some cases, the term "source" or "drain" is not used. In such cases, for example, They may be written as terminal or second terminal.

[0252] In FIG. 18(C) and FIG. 19(A), node A is made floating, so that the boot A capacitor may be provided separately to perform a strap operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0253] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 19B corresponds to a vertical blanking period, and the period 62 corresponds to a gate selection period. do.

[0254] As shown in FIG. 19A, the ninth transistor has a gate to which the second power supply potential VCC is applied. By providing the transistor 39, the following can be achieved before and after the bootstrap operation: There are such advantages.

[0255] In the absence of the ninth transistor 39 having the gate electrode to which the second potential VCC is applied, the boot When the potential of the node A rises due to the strap operation, the second terminal of the first transistor 31 The potential of the source, which is the first power supply potential VDD, increases and becomes higher than the first power supply potential VDD. The source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. In the first transistor 31, the gate and source, and the gate and drain are In addition, a large bias voltage is applied, which causes a large stress and leads to deterioration of the transistor. Therefore, the ninth transistor, whose gate electrode is applied with the second power supply potential VCC, By providing the transistor 39, the potential of the node A is set by the bootstrap operation. However, the potential of the second terminal of the first transistor 31 does not increase. That is, by providing the ninth transistor 39, The negative bias voltage applied between the gate and source of the transistor 31 can be reduced. Therefore, by using the circuit configuration of this embodiment, the gate of the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the first-order This makes it possible to suppress the deterioration of the transistor 31.

[0256] The ninth transistor 39 is provided at a position corresponding to the second gate of the first transistor 31. A terminal is connected between the terminal and the gate of the third transistor 33 via a first terminal and a second terminal. In addition, in the present embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scan line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0257] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and Because it is possible to increase the field effect mobility and reduce the degree of degradation. In addition, a transistor including an oxide semiconductor can be Compared to transistors using amorphous silicon, a high potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line. Since the number of power lines to be routed can be reduced, the circuit can be made more compact.

[0258] The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 a clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38; The input electrodes (lower gate electrode and upper gate electrode) are supplied with a second input terminal 22. The clock signal is applied to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode). A clock signal is supplied to the gate electrode of the eighth transistor by the second input terminal 22. The gate electrodes of the gate electrodes of the first input terminal 23 are connected to the gate electrodes of the second input terminal 23. Therefore, the same effect can be obtained by switching the wiring so that the clock signal is supplied. In the shift register shown in FIG. The seventh transistor 37 is turned off, and the eighth transistor 38 is turned on. The seventh transistor 37 is turned off, and the eighth transistor 38 is turned on. When the power supply 38 is turned off, the second input terminal 22 and the third input terminal 23 are turned on. The voltage drop at node B is applied to the gate of the seventh transistor 37. 2 due to a drop in the potential of the gate electrode of the eighth transistor 38 and a drop in the potential of the gate electrode of the eighth transistor 39. On the other hand, if the shift register shown in FIG. 19(A) is changed to that shown in FIG. The seventh transistor 37 and the eighth transistor 38 are both in an on state. The transistor 37 is on, the eighth transistor 38 is off, and then the seventh transistor The second input is turned on by turning on the eighth transistor 37 and the eighth transistor 38. The potential drop at node B caused by the potential drop at terminal 22 and the third input terminal 23 is , the potential of the gate electrode of the eighth transistor 38 can be reduced to one. Therefore, the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) a clock signal provided by the third input terminal 23 to the eighth transistor 38 The gate electrodes (lower gate electrode and upper gate electrode) of By using the clock signal supplied, the fluctuation of the potential of node B can be reduced. This is preferable because it is possible to reduce noise.

[0259] In this manner, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during the period, the pulse output This makes it possible to suppress malfunction of the power circuit.

[0260] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0261] (Embodiment 11) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. It is possible to manufacture a semiconductor device (also called a display device) having a display function. A part or the whole of the driver circuit using transistors is formed on the same substrate as the pixel section. A system on panel can be formed.

[0262] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0263] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above is mounted. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is The element substrate is provided with a means for supplying a current to the display element in each of the plurality of pixels. Alternatively, only the pixel electrode (also called pixel electrode layer) of the display element may be formed. After forming the conductive layer to be the pixel electrode and before etching to form the pixel electrode, It can be a state, or it can take any form.

[0264] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0265] The appearance and cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device, will be described with reference to FIG. 20(A1) and (A2) show the third embodiment formed on a first substrate 4001. The highly reliable thin film transistors 4010 and 4011 each including an oxide semiconductor layer shown in A liquid crystal element 4013 is sealed between a second substrate 4006 and the liquid crystal element 4013 by a sealant 4005. FIG. 20(B) is a cross-sectional view taken along line MN in FIG. 20(A1) and (A2). Corresponding to the figure.

[0266] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor layer or a polycrystalline semiconductor layer is mounted.

[0267] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 20A shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0268] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 20B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 The protective insulating layer 4020 and the protective insulating layer 4021 are formed on the thin film transistors 4010 and 4011. 021 is provided.

[0269] The thin film transistors 4010 and 4011 are the signal transistors including the oxide semiconductor layer described in Embodiment 3. In addition, a highly reliable thin film transistor can be applied. In the present embodiment, the thin film transistor shown in FIG. The transistors 4010 and 4011 are n-type thin film transistors.

[0270] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed on the liquid crystal layer 4006. The overlapping portion corresponds to a liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0271] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Room can be used.

[0272] Also, 4035 is a columnar spacer 4035 obtained by selectively etching the insulating layer. and the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. A spherical spacer may be used. 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrodes via conductive particles disposed between the pair of substrates. The electrode layer 4031 can be electrically connected to a common potential line. It is incorporated into material 4005.

[0273] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 millisecond or less. Since it is optically isotropic, no alignment treatment is required, and the viewing angle dependency is small.

[0274] In addition to the transmissive LCD, the present invention can also be applied to reflective and semi-transmissive LCDs. can.

[0275] In addition, in liquid crystal display devices, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and a colored layer (color In this example, the polarizing plate is placed on the substrate in the order of the filter and the electrode layer used for the display element. The laminated structure of the polarizing plate and the colored layer is not limited to the embodiment, and may be provided on the polarizing side. The thickness may be appropriately set depending on the materials of the plate and the colored layer and the manufacturing process conditions. A light-shielding layer that functions as a shield may be provided.

[0276] In addition, a protective insulating layer 4020 is formed on the thin film transistors 4010 and 4011. The protective insulating layer 4020 is resistant to moisture, hydrogen ions, and OH - It does not contain impurities such as The inorganic insulating film blocks the intrusion of foreign matter from the outside. A protective insulating layer 402 is formed by using a silicon nitride oxide film, a silicon oxynitride film, an aluminum oxynitride film, or the like. The reference numeral 400 denotes a light-transmitting insulating film. Here, the protective insulating layer 4020 is formed by a PCVD method. A silicon nitride film is formed.

[0277] In addition, an insulating layer 4021 is formed as a planarizing insulating layer. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. are used. In addition, by laminating multiple insulating layers made of these materials, 4021 may be formed.

[0278] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0279] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, a S OG method, spin coating, dip, spray coating, droplet ejection method (inkjet method, screen Printing methods such as lean printing, offset printing, doctor knife, roll coater, curtain A tool (equipment) such as a coater or a knife coater can be used. By combining the baking process with the annealing of the semiconductor layer, it is possible to efficiently manufacture semiconductor devices. It becomes.

[0280] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material may be used.

[0281] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0282] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0283] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0284] The connection terminal electrode 4015 is formed from the same conductive layer as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layer and the drain electrode layer of the thin film transistor 4011. The gate electrode layer is formed from the same conductive layer.

[0285] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive layer 4019. The electrodes are electrically connected to each other.

[0286] In FIG. 20, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. The embodiment is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0287] FIG. 21 shows a semiconductor device using a TFT substrate 2600 fabricated by the fabrication method disclosed herein. 1 shows an example in which a liquid crystal display module is configured as a semiconductor device.

[0288] FIG. 21 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is necessary for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. A wiring board 2609 is connected to the wiring circuit section 2608 of the TFT board 2600, and the controller The LCD has external circuits such as a filter circuit and a power supply circuit. The layers may be laminated with a retardation plate interposed therebetween.

[0289] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0290] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0291] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0292] (Embodiment 12) An example of the semiconductor device is electronic paper.

[0293] Electronic paper is also called an electrophoretic display (electrophoretic display) and has the same properties as paper. The advantages are ease of reading, lower power consumption compared to other display devices, and the possibility of making them thin and lightweight. It has points.

[0294] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0295] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. Therefore, no polarizing plate, which is necessary for a liquid crystal display device, is required.

[0296] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0297] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. An active matrix substrate obtained by using the thin film transistor of 9 can be used. .

[0298] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0299] FIG. 22 shows an active matrix type electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in the embodiment mode 1. The thin film transistor can be fabricated in the same manner as the conventional thin film transistor, and is highly reliable, including an oxide semiconductor layer. The thin film transistors shown in the second to ninth embodiments are also the thin film transistor 5 of this embodiment. It can also be applied as 81.

[0300] The electronic paper in FIG. 22 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0301] The thin film transistor 581 formed on the substrate 580 is a bottom-gate thin film transistor. The thin film transistor 581 is covered with an insulating layer 583 that is in contact with the semiconductor layer. The first electrode layer 587 is connected to the insulating layer 583 and the insulating layer 584 by the source electrode layer or the drain electrode layer. The first electrode layer 587 and the substrate 585 are in contact with each other through an opening formed in the layer 585 and are electrically connected to each other. Between the second electrode layer 588 formed on the first electrode layer 596, there are black areas 590a and white areas 5 90b, and a spherical particle 589 is provided that includes a cavity 594 filled with liquid therearound. The spherical particles 589 are surrounded by a filler 595 such as a resin. The electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The electrode layer 588 is connected to a common potential line and a potential line provided on the same substrate 580 as the thin film transistor 581. A conductive layer is disposed between the substrate 580 and the substrate 596 using a common connection. The second electrode layer 588 and a common potential line can be electrically connected via the particles.

[0302] Also, instead of the twist ball, an electrophoretic element can be used. and a 10μm to 20μm diameter nanoparticle that contains positively charged white nanoparticles and negatively charged black nanoparticles. Microcapsules with a diameter of about 0 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, the microcapsules emit white light. White particles and black particles move in opposite directions, allowing the display to be white or black. A display element that applies this principle is an electrophoretic display element, commonly known as electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display, the image that was displayed can be retained. Therefore, the distance between the radio wave source and the semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The displayed image can be stored even if the semiconductor device (also called a semiconductor device equipped with a This makes it possible.

[0303] Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0304] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0305] (Embodiment 13) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that uses electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0306] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0307] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0308] FIG. 23 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0309] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. In this study, two n-type transistors using an oxide semiconductor layer for the channel formation region are used in one pixel. Here is an example.

[0310] The pixel 6400 includes a switching transistor 6401 and a light-emitting element driving transistor 6 The transistor 402 has a light emitting element 6404 and a capacitor element 6403. The gate of the gate electrode of the gate electrode 6401 is connected to the scanning line 6406, and the first electrode (the source electrode and the drain electrode) One of the electrodes) is connected to a signal line 6405, and the second electrode (the source electrode and the drain electrode) is connected to a signal line 6405. The other end of the transistor 6402 is connected to the gate of the light-emitting element driving transistor 6402. The transistor 6402 has a gate connected to a power supply line 6407 via a capacitor element 6403. The first electrode is connected to a power line 6407, and the second electrode is the first electrode (pixel The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0311] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0312] The capacitor 6403 is substituted for the gate capacitance of the light-emitting element driving transistor 6402. It is possible to omit it. Regarding the gate capacitance of the light-emitting element driving transistor 6402 A capacitance may be formed between the channel region and the gate electrode.

[0313] In the case of a voltage input voltage driving method, the gate of the light emitting element driving transistor 6402 In the test, the light emitting element driving transistor 6402 is either fully turned on or fully turned off. In other words, the light emitting element driving transistor 6402 is inputted with a video signal that is in the state of The light emitting element driving transistor 6402 is operated in the linear region. Therefore, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the light emitting element driving transistor 6402. The signal line 6405 is connected to the power supply line voltage + transistor for driving the light emitting element. Apply a voltage equal to or higher than the Vth of 6402.

[0314] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 23 can be used.

[0315] When analog gradation driving is performed, a light emitting element is connected to the gate of the light emitting element driving transistor 6402. Apply the forward voltage of 6404 + a voltage equal to or higher than the Vth of the light emitting element driving transistor 6402. The forward voltage of the light emitting element 6404 refers to a voltage for achieving a desired luminance. At least the forward threshold voltage is included. By inputting a video signal that operates in the region, a current is passed to the light emitting element 6404. In order to operate the light emitting element driving transistor 6402 in the saturation region, the power supply line 6 The potential of the gate of the transistor 407 is set higher than the gate potential of the light emitting element driving transistor 6402. By converting the video signal into an analog signal, a current corresponding to the video signal flows through the light emitting element 6404. Analog gray scale driving is possible.

[0316] Note that the pixel configuration shown in FIG. 23 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0317] Next, the configuration of the light-emitting element will be described with reference to FIG. The cross-sectional structure of a pixel will be described below by taking the case where FT is n-type as an example. (C) TFTs 7001 and 7011 which are TFTs for driving light emitting elements used in the semiconductor device The thin film transistor 7021 can be manufactured in the same manner as the thin film transistor arranged in the pixel shown in the embodiment mode 1. In addition, the thin film transistor according to the embodiment 2 to 5 has high reliability and includes an oxide semiconductor layer. The thin film transistors arranged in the pixels shown in the ninth embodiment are TFT7001, 7011, and 7 It can also be applied as 021.

[0318] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite the substrate. The top surface emission takes the light out from the surface on the substrate side, the bottom surface emission takes the light out from the surface on the substrate side, There are light-emitting elements with a double-sided emission structure that emits light from the opposite surface. The present invention can also be applied to light-emitting devices.

[0319] A light emitting element having a top emission structure will be described with reference to FIG.

[0320] In FIG. 24A, a TFT 7001 for driving a light-emitting element is an n-type TFT, and a light-emitting element 700 FIG. 24(A) shows a cross-sectional view of a pixel when light emitted from the cathode 2 exits to the anode 7005 side. ) is a cathode 7003 of a light-emitting element 7002 and a TFT 7001 which is a TFT for driving the light-emitting element. are electrically connected, and a light-emitting layer 7004 and an anode 7005 are laminated in this order on a cathode 7003. The cathode 7003 may be any conductive layer having a small work function and capable of reflecting light. Various materials can be used. For example, Ca, Al, MgAg, AlLi, etc. are preferable. The light-emitting layer 7004 may be composed of a single layer or may be composed of multiple layers stacked together. When it is made up of multiple layers, the cathode 7003 is provided with a layer The electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are laminated in this order. It is not necessary to provide all of these layers. The anode 7005 is made of a conductive material having a light transmitting property. For example, indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide A light-transmitting conductive layer such as indium tin oxide doped with silicon oxide is used. is also good.

[0321] In addition, a partition wall 7009 is provided on the cathode 7003. The partition wall 7009 is made of polyimide, acrylic, etc. , polyamide, epoxy or other organic resin film, inorganic insulating film or organic polysiloxane The partition wall 7009 is formed by using a photosensitive resin material in particular, and the side surface of the partition wall 7009 is continuous. It is preferable that the partition wall 7009 is formed to have an inclined surface having a certain curvature. When a photosensitive resin material is used, the step of forming a resist mask can be omitted. Cut.

[0322] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light-emitting element 7002. In the case of the pixel shown in FIG. 24(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as indicated by the mark.

[0323] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. The TFT 7011 is an n-type, and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013. FIG. 24B shows a cross-sectional view of a pixel in the case where a light-emitting element driving TFT 7011 and a A cathode 7013 of the light-emitting element 7012 is formed on the conductive layer 7017 having a light-transmitting property and is electrically connected to the light-transmitting layer 7017. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. In addition, when the anode 7015 has a light-transmitting property, a light reflecting or blocking layer is provided so as to cover the anode. A shielding layer 7016 for shielding the cathode 7013 may be formed. As in the case of the first embodiment, various conductive materials having a small work function can be used. However, the thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, an aluminum layer having a thickness of 20 nm can be used as the cathode 7013. The light-emitting layer 7014 may be composed of a single layer as in FIG. The anode 7015 is a light-transmitting layer. Although it is not necessary, the insulating film 11 may be formed using a conductive material having light transmitting properties as in FIG. 24(A). The shielding layer 7016 can be made of, for example, a metal that reflects light. The layer is not limited to a metal layer, and may be, for example, a resin to which a black pigment is added.

[0324] In addition, a partition wall 7019 is provided over the conductive layer 7017. The partition wall 7019 is made of a material such as polyimide, acrylic, or the like. The insulating film is made of organic resin such as polyamide or epoxy, inorganic insulating film, or organic polysiloxane. The partition wall 7019 is formed by using a photosensitive resin material in particular, and the side surface of the partition wall 7019 is continuous. It is preferable to form the partition wall 7019 so as to have an inclined surface having a certain curvature. When a photosensitive resin material is used as the resist mask, the step of forming a resist mask can be omitted. can.

[0325] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 24B, the light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0326] Next, a light emitting element having a dual emission structure will be described with reference to FIG. In the example, a light-transmitting conductive layer 702 is electrically connected to a light-emitting element driving TFT 7021. A cathode 7023 of a light-emitting element 7022 is formed on the light-emitting layer 7 24(A) and an anode 7025 are laminated in this order. Similarly, various conductive materials with small work functions can be used. The thickness of the film is set to a level that allows light to pass through. For example, an aluminum film having a thickness of 20 nm is It can be used as a cathode 7023. And the light-emitting layer 7024 can be formed in the same manner as in FIG. It can be made up of a single layer or multiple layers stacked together. The anode 7025 may be a light-transmitting conductive film similar to that shown in FIG. The material can be used to form the insulating film.

[0327] In addition, a partition wall 7029 is provided over the conductive layer 7027. The partition wall 7029 is made of polyimide, acrylic, or the like. The insulating film is made of organic resin such as polyamide or epoxy, inorganic insulating film, or organic polysiloxane. The partition wall 7029 is formed by using a photosensitive resin material in particular, and the side surface of the partition wall 7029 is continuous. It is preferable to form the partition wall 7029 so as to have an inclined surface having a certain curvature. When a photosensitive resin material is used as the resist mask, the step of forming a resist mask can be omitted. can.

[0328] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 70. In the case of the pixel shown in FIG. 24C, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0329] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0330] In addition, a thin film transistor (a TFT for driving a light-emitting element) that controls the driving of the light-emitting element and a light-emitting element In the above example, the light-emitting element driving TFT and the light-emitting element are electrically connected. A control TFT may be connected.

[0331] The semiconductor device is not limited to the configuration shown in FIG. 24, and may be any of the configurations disclosed in this specification. Various modifications based on the technical concept are possible.

[0332] Next, the appearance and structure of a light-emitting display panel (also called a light-emitting panel) which corresponds to one embodiment of a semiconductor device will be described. The cross section will be described with reference to FIG. 25. FIG. 25(A) shows a thin film formed on a first substrate. A panel in which the film transistor and the light emitting element are sealed between the second substrate and the film transistor and the light emitting element by a sealant. 25(B) is a plan view of the above-mentioned embodiment, and FIG. 25(B) is a cross-sectional view taken along line HI of FIG. 25(A).

[0333] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0334] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 25B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0335] The thin film transistors 4509 and 4510 are the signal transistors including the oxide semiconductor layer described in Embodiment 3. In addition, a highly reliable thin film transistor can be applied. In the present embodiment, the thin film transistor shown in FIG. The transistors 4509 and 4510 are n-type thin film transistors.

[0336] In addition, a protective insulating layer 4543 is formed over the thin film transistors 4509 and 4510. The protective insulating layer 4543 is a barrier against moisture, hydrogen ions, and OH - It does not contain impurities such as The inorganic insulating film blocks the intrusion of foreign matter from the outside. A protective insulating layer 454 is formed by using a silicon nitride oxide film, a silicon nitride oxide film, an aluminum oxide nitride film, or the like. 3 is an insulating film having light-transmitting properties. Here, the protective insulating layer 4543 is formed by the PCVD method. A silicon nitride film is formed.

[0337] In addition, an insulating layer 4544 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. are used. In addition, by stacking a plurality of insulating films made of these materials, an insulating layer can be formed. Alternatively, the insulating layer 4544 may be formed. Here, acrylic is used as the insulating layer 4544.

[0338] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured as a first electrode layer 4517, an electroluminescent layer The light emitting element 4512 and the second electrode layer 4513 are stacked together, but the structure is not limited to the one shown in the figure. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from the element 4511. It is possible.

[0339] The partition 4520 is formed using an organic resin layer, an inorganic insulating layer, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0340] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0341] In order to prevent hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer 451 An oxide insulating layer may be formed over the insulating film 3 and the partition 4520 .

[0342] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0343] The connection terminal electrode 4515 is a conductive layer that is the same as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed of a source electrode layer and The drain electrode layer is formed from the same conductive layer as the drain electrode layer.

[0344] The connection terminal electrode 4515 is connected to a terminal of the FPC 4518a via an anisotropic conductive layer 4519. The electrodes are electrically connected to each other.

[0345] The second substrate 4506 located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In this case, a glass plate, a plastic plate, a polyester film or A light-transmitting material such as an acrylic film is used.

[0346] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's good.

[0347] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) is placed on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be installed as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection layer. Anti-glare treatment can be applied to further diffuse reflected light and reduce glare.

[0348] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving element formed of a single crystal semiconductor layer or a polycrystalline semiconductor layer on a separately prepared substrate Also, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be implemented. Only the operating circuit or only a part of it may be formed separately and mounted, and is not limited to the configuration of FIG. stomach.

[0349] Through the above steps, a highly reliable light-emitting display panel (light-emitting panel) is manufactured as a semiconductor device. It is possible.

[0350] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0351] (Embodiment 14) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, train rides, etc. It can be used for in-car advertising, display on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 26.

[0352] FIG. 26 shows an example of an electronic book 2700. For example, the electronic book 2700 has a housing 2 The device is made up of two housings, housing 2701 and housing 2703. 03 is integrated with an axis portion 2711, and performs opening and closing operations around the axis portion 2711. This configuration makes it possible to operate like a paper book. .

[0353] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 26) and An image can be displayed on the display unit 2707 in FIG.

[0354] FIG. 26 shows an example in which the housing 2701 is provided with an operation unit. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a display board, a pointing device, etc. On the front side, there is a terminal for external connection (earphone terminal, USB terminal, or AC adapter and USB cable). A terminal that can be connected to various cables such as a USB cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. Good too.

[0355] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0356] (Embodiment 15) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), ), portable game machines, personal digital assistants, audio playback devices, pachinko machines and other large game machines, etc. Examples include:

[0357] FIG. 27A shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In addition, the stand 9605 supports the housing 9601. This shows a configuration in which the above is supported.

[0358] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0359] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0360] FIG. 27B shows an example of a digital photo frame 9700. The photo frame 9700 includes a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example images captured by a digital camera. By displaying the image data, it can function like a normal photo frame.

[0361] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have one as it improves the design. For example, the Digital Photo Frame 9700 Insert a memory that stores image data taken with a digital camera into the recording medium insertion section of the Image data can be captured and the captured image data can be displayed on the display unit 9703. do.

[0362] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0363] FIG. 28(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 28(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, odor, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and at least It is sufficient that the semiconductor device disclosed in the document is included, and other auxiliary equipment is appropriately provided. The portable game machine shown in FIG. 28(A) can be configured as a game machine having a game data recorded on a recording medium. The function of reading out the program or data and displaying it on the display unit, and wireless communication with other portable gaming machines It has a function to communicate and share information. The function to be performed is not limited to this, and may have various functions.

[0364] FIG. 28(B) shows an example of a slot machine 9900, which is a large-scale gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. The Machine 9900 also includes other operating means such as a start lever and stop switch, coin The slot machine 9900 is equipped with a slot slot, a speaker, etc. However, the present invention is not limited to the above, and may be configured to include at least the semiconductor device disclosed in this specification. Other auxiliary equipment may be provided as appropriate.

[0365] FIG. 29A is a perspective view showing an example of a portable computer.

[0366] The portable computer of FIG. 29(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display unit 9303 and a keyboard. The lower housing 9302 having the base 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to type on the keyboard, the hinge unit needs to be opened. The user can perform input operations by looking at the display portion 9303.

[0367] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the touch panel. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the USB communication standard is inserted. There are.

[0368] The upper housing 9301 further includes a display unit 93 that can be slid and stored inside the upper housing 9301. 07, it is possible to realize a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display unit.

[0369] The display unit 9303 or the foldable display unit 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses an image display device such as a light-emitting display panel using inorganic light-emitting elements.

[0370] The portable computer shown in FIG. 29(A) is configured with a receiver and the like, and is a television. It is possible to receive broadcasts and display images on the display unit. The display unit 9307 is slid while the hinge unit connecting the display unit 9302 to the display body 9302 is kept in the closed state. By adjusting the screen angle, the user can watch TV broadcasts. In this case, the hinge unit is opened to prevent the display unit 9303 from displaying anything. Since the system only activates the circuits that display the TV broadcast, power consumption is kept to a minimum. This is useful in portable computers where battery capacity is limited.

[0371] FIG. 29(B) shows a portable electronic device that can be worn on the user's arm like a wristwatch. FIG. 13 is a perspective view showing an example of a story.

[0372] This mobile phone is a main body having at least a communication device having a telephone function and a battery. A band part 9204 for attaching the body to the arm, and an adjustment part for adjusting the fastening state of the band part to the arm It is composed of a joint part 9205, a display part 9201, a speaker 9207, and a microphone 9208. There are.

[0373] The main body also has an operation switch 9203, which serves as a power input switch and a display switching switch. In addition to the camera start switch and the image capture start switch, there are also other switches, such as a button that starts an Internet program when pressed. Each function can be assigned using the operation switch 9203. Cut.

[0374] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the mobile phone. This is done by operating the operation switch 9203 or by voice input to the microphone 9208. FIG. 29B shows a display button 9202 displayed on a display unit 9201. Input can be made by touching the screen.

[0375] The main body also includes an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. The camera unit 9206 has a step. Note that the camera unit does not necessarily have to be provided.

[0376] The mobile phone shown in FIG. 29(B) is equipped with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in a memory or the like. As a configuration equipped with a storage device, television broadcasts can be recorded in the memory. The mobile phone shown in FIG. 2 may have a function for collecting location information such as GPS.

[0377] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in FIG. 29(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force actuable panel.

[0378] Although FIG. 29B illustrates an electronic device that is worn on the arm, the electronic device is not limited to this. It is sufficient that the device has a shape that can be carried around. EXAMPLES

[0379] Using the first-principles molecular dynamics (MD) method, we calculated the interaction between the oxide semiconductor layer and oxygen molecules. The calculation software used here is CASTEP, manufactured by Accelrys Corporation. The calculation conditions were NVT ensemble, time 0.5 picoseconds, and temperature 350°C. The calculation method is density functional theory using the plane wave basis pseudopotential method. The functional is GGA. PBE was used.

[0380] Here, the calculation model of the IGZO surface is a set of 12 In atoms, 12 Ga atoms, and 1 The amorphous structure was assumed to consist of 2 Zn atoms and 46 O atoms. The lattice is a rectangular parallelepiped of 1.02 nm × 1.02 nm × 2.06 nm. The boundaries are periodic boundary structures. In the following, a model in which oxygen molecules are added to the above surface model is used.

[0381] The figure shows the surface of an oxide semiconductor layer and the initial state of oxygen molecules arranged near the surface of the oxide semiconductor layer. The positions of the two are shown in Fig. 30(A) and 0.5 picoseconds later in Fig. 30(B). In this case, oxygen molecules are adsorbed on the metal on the surface of the oxide semiconductor layer. The covalent bond between the oxygen molecules was not lost.

[0382] However, oxygen atoms tend to be adjacent to metal atoms rather than bonded to each other. It is thermodynamically stable. In addition, the structural model created from the measured density of the oxide semiconductor layer is However, the space inside the oxide semiconductor layer is too narrow for oxygen molecules to diffuse while maintaining their covalent bonds. Therefore, when the thermodynamic equilibrium is reached, the oxygen atoms are in the oxide semiconductor layer. spread to the area.

[0383] Next, in the oxide semiconductor layer having a region with high oxygen density and a region with low oxygen density, The diffusion phenomenon of oxygen during heat treatment was calculated. The results are explained using Figures 31 and 32. Here, the software used for the calculation is Material Explorer 5.0 was used.

[0384] FIG. 31 shows a model of the oxide semiconductor layer used in the calculation. Here, the oxide semiconductor layer 70 1 had a structure in which a layer 703 with low oxygen density and a layer 705 with high oxygen density were stacked.

[0385] Here, the layer 703 with low oxygen density is made of 15 In atoms, 15 Ga atoms, and 15 The amorphous structure was composed of 10 Zn atoms and 54 O atoms.

[0386] The oxygen-rich layer 705 is made of 15 In atoms, 15 Ga atoms, and 15 The amorphous structure was composed of a Zn atom and 66 O atoms.

[0387] The density of the oxide semiconductor layer 701 is set to 5.9 g / cm 3 It was decided.

[0388] Next, the oxide semiconductor layer 701 was aged under the conditions of the NVT ensemble and a temperature of 250° C. A molecular dynamics (MD) calculation was performed. The time step size was set to 0.2 femtoseconds, and the total calculation time was The time was set to 200 picoseconds. The potential was set to the metal-oxygen bond and the oxygen-oxygen bond. A Born-Mayer-Huggins type potential was applied to the potential. In addition, the movements of atoms at the upper and lower ends of the oxide semiconductor layer 701 were fixed.

[0389] Next, the calculation results are shown in Figure 32. The area from 0 nm to 1.15 nm on the z-axis coordinate is the layer with low oxygen density. 703, and the region from 1.15 nm to 2.3 nm on the z-axis coordinate is the oxygen-rich layer 705. The oxygen density distribution before the MD calculation is shown by the solid line 707, and the oxygen density distribution after the MD calculation is shown by the dashed line Shown at 709.

[0390] In the solid line 707, the oxygen concentration is increased from the interface between the low oxygen density layer 703 and the high oxygen density layer 705. In the oxygen-rich layer 705, the oxygen density is high. The oxygen density is uniform in the low oxygen density layer 703 and the high oxygen density layer 705. It can be seen that...

[0391] From the above, the layer with low oxygen density 703 and the layer with high oxygen density 705 are stacked as shown in the figure. If there is a bias in the distribution of oxygen density, the oxygen will diffuse from areas with high oxygen density to areas with low oxygen density due to heat treatment. It can be seen that the oxygen density becomes homogenous.

[0392] The state of oxygen diffusion at this time is shown in FIG. Oxygen 713 moves to the surface of the oxide 1 (see FIG. 33(A)). The compound semiconductor layer 711 is shown in the form in which a metal (Me) and oxygen (O) are bonded. The oxygen 713 is adsorbed to the surface of the oxide semiconductor layer 711. The oxide semiconductor layer 715 is shown as being adsorbed by a semiconductor metal (Me). forms an ionic bond with the metal ion (Me) contained in the oxide semiconductor layer, and the state of the oxygen atom It can be seen that the diffusion of the ions into the oxide semiconductor layer occurs at 1000 nm (see FIG. 33C).

[0393] That is, as shown in Embodiment 1, the oxide insulating layer 407 is formed over the oxide semiconductor layer 403. As a result, the oxygen density is high at the interface between the oxide semiconductor layer 403 and the oxide insulating layer 407. Therefore, the oxygen diffuses to the oxide semiconductor layer 403 in a region with a low oxygen density. The layer 403 becomes highly resistive. From the above, it is possible to improve the reliability of the thin film transistor. can be done. [Explanation of symbols]

[0394] 10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminals 25 Input terminal 26 Output terminal 27 Output terminal 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 43 Transistor 51 Power line 52 Power line 53 Power line 61 period 62 period 100 Substrates 101 Gate electrode layer 102 Gate insulating layer 103 Oxide semiconductor layer 105a Drain electrode layer 105b Drain electrode layer 107 Oxide insulating layer 108 Capacitance wiring 110 Pixel electrode layer 121 Terminal 122 Terminal 125 Contact Hole 126 Contact Hole 127 Contact Hole 128 Transparent conductive layer 129 Transparent conductive layer 132 Conductive Layer 133 Oxide Semiconductor Layer 134 Oxide semiconductor layer 150 Terminals 151 Terminal 152 Gate Insulation Layer 153 Connection electrode layer 154 Oxide insulating layer 155 Transparent conductive layer 156 Electrode layer 170 Thin-film transistor 200 temperature 250 temperature 400 Substrates 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor layer 404a Source or drain region 405a Source electrode layer or drain electrode layer 405b Source electrode layer or drain electrode layer 407 Oxide insulating layer 409 Conductive Layer 410 Insulating layer 411 Pixel electrode layer 419 Conductive Layer 430 Oxide semiconductor layer 431 Oxide Semiconductor Layer 441 Oxide Semiconductor Layer 450 Substrate 451 Gate electrode layer 452 Gate insulation layer 453 Oxide Semiconductor Layer 455a Drain electrode layer 457 Oxide insulating layer 460 Thin Film Transistor 470 Thin Film Transistor 471 Thin-film transistor 472 Thin Film Transistor 473 Thin Film Transistor 483 Oxide Semiconductor Layer 580 Substrate 581 Thin Film Transistor 583 Insulating Layer 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 594 Cavity 595 Filling material 596 Board 601 Electric furnace 602 Chamber 603 Heater 604 Substrate 605 Susceptor 606 Gas Supply Means 607 Exhaust means 611 Gas supply source 612 Pressure Regulating Valve 613 Purifier 614 Mass Flow Controller 615 Stop valve 701 Oxide semiconductor layer 703 layers 705 layers 707 Solid Line 709 Dashed Line 711 Oxide semiconductor layer 713 Oxygen 715 Oxide Semiconductor Layer 1400 Board 1401 Gate electrode layer 1402 Gate insulation layer 1403 Oxide semiconductor layer 1405a Source electrode layer or drain electrode layer 1405b Source electrode layer or drain electrode layer 1406a Source or drain region 1406b Source or drain region 1407 Insulating layer 1408 Insulating layer 1409 Conductive layer 1418 Channel Protection Layer 1430 Thin-film transistor 1431 Thin-film transistor 1432 Thin-film transistor 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive layer 4020 Protective insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4035 Spacer 4501 Board 4502 Pixel section 4503a Signal line driver circuit 4504a Scanning line driver circuit 4505 Sealing material 4506 Board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4519 Anisotropic conductive layer 4520 Bulkhead 4543 Protective insulation layer 4544 Insulation layer 5300 Board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing Control Circuit 5601 Shift Register 5602 Switching Circuit 5603 Thin Film Transistor 5604 Wiring 5605 Wiring 590a black area 590b White area 6400 pixels 6401 Switching transistor 6402 Light emitting device driving transistor 6403 Capacitor 6404 Light emitting element 6405 Signal Line 6406 scan lines 6407 Power line 6408 Common electrode 7001 TFT 7002 Light emitting element 7003 Cathode 7004 Light-emitting layer 7005 Anode 7009 Bulkhead 7011 Light emitting element driving TFT 7012 Light emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding layer 7017 Conductive layer 7019 Bulkhead 7021 Light-emitting element driving TFT 7022 Light emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive layer 7029 Bulkhead 9201 Display section 9202 Display button 9203 Operation switch 9204 Band 9205 Adjustment section 9206 Camera Department 9207 Speaker 9208 Mike 9301 Upper housing 9302 Lower housing 9303 Display section 9304 Keyboard 9305 External connection port 9306 Pointing Device 9307 Display section 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control device 9700 Digital Photo Frame 9701 Case 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Input means (operation keys 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 Slot Machine 9901 Case 9903 Display section

Claims

1. forming a gate electrode; forming a gate insulating film having a laminated structure on the gate electrode; forming an oxide semiconductor layer containing In, Ga, and Zn on the gate insulating film; a first heating process is performed on the oxide semiconductor layer in an atmosphere containing nitrogen and oxygen; The first heating is performed at a temperature of 400° C. or more and 700° C. or less, forming a source electrode and a drain electrode on the oxide semiconductor layer after the first heating; forming an oxide insulating layer on the oxide semiconductor, the source electrode, and the drain electrode; After forming the oxide insulating layer, a second heating is performed in an inert gas atmosphere; The method for manufacturing a semiconductor device, wherein a water peak is not detected at around 300° C. in a TDS (Thermal Desorption Spectroscopy) measurement of the oxide semiconductor layer.

2. forming a gate electrode; forming a gate insulating film having a laminated structure on the gate electrode; forming an oxide semiconductor layer containing In, Ga, and Zn on the gate insulating film; a first heating process is performed on the oxide semiconductor layer in an atmosphere that does not contain moisture and contains nitrogen and oxygen; The first heating is performed at a temperature of 400° C. or more and 700° C. or less, forming a source electrode and a drain electrode on the oxide semiconductor layer after the first heating; forming an oxide insulating layer on the oxide semiconductor, the source electrode, and the drain electrode; After forming the oxide insulating layer, a second heating is performed in an inert gas atmosphere; The method for manufacturing a semiconductor device, wherein a water peak is not detected at around 300° C. in a TDS (Thermal Desorption Spectroscopy) measurement of the oxide semiconductor layer.

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