Semiconductor Device

Abstract

To provide a new semiconductor device.SOLUTION: A semiconductor device includes: a first control circuit having a first transistor using a silicon substrate for a channel; a second control circuit provided on the first control circuit and having a second transistor using metal oxide for a channel; a memory circuit provided on the second control circuit and having a third transistor using metal oxide for a channel; and a global bit line and an inverted global bit line having functions of transmitting signals between the first control circuit and the second control circuit. The first control circuit has a sense amplifier circuit having an input terminal and an inverted input terminal. During a first period in which data is read from the memory circuit to the first control circuit, the second control circuit controls whether or not to charge the global bit line in which the electric charge is discharged and the inverted global bit line according to the data read from the memory circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] This specification describes semiconductor devices and the like.

[0002] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may have semiconductor devices. [Background technology]

[0003] Metal oxides have been attracting attention as semiconductors that can be applied to transistors. In-Ga-Zn oxide, also known as "IGZO" or "Iguzo", is a representative multi-component metal oxide. In research on IGZO, a c-axis aligned crystalline (CAAC) structure and a nanocrystalline (nc) structure, which are neither single crystal nor amorphous, were discovered (e.g., Non-Patent Document 1).

[0004] It has been reported that a transistor having a metal oxide semiconductor in a channel formation region (hereinafter sometimes referred to as an "oxide semiconductor transistor" or an "OS transistor") has an extremely small off-state current (for example, Non-Patent Documents 1 and 2). Various semiconductor devices using OS transistors have been manufactured (for example, Non-Patent Documents 3 and 4).

[0005] The manufacturing process of OS transistors can be incorporated into a conventional CMOS process with Si transistors, and OS transistors can be stacked on Si transistors. For example, Patent Document 1 discloses a configuration in which multiple layers of memory cell arrays having OS transistors are stacked on a substrate on which Si transistors are provided.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Non-Patent Documents

[0007]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Non-Patent Document 4

Summary of the Invention

[0008] An object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that can reduce manufacturing costs in a semiconductor device that functions as a memory device using an extremely low off current. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that is excellent in low power consumption in a semiconductor device that functions as a memory device using an extremely low off current. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that can reduce the size of a semiconductor device that functions as a memory device using an extremely low off current. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that has excellent reliability of data read out in a semiconductor device that functions as a memory device using an extremely low off current. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that can perform writing back of data read out without inverting the logic of the data read out in a semiconductor device that functions as a memory device using an extremely low off current.

[0009] The description of multiple problems does not preclude the existence of each problem. One embodiment of the present invention does not need to solve all of the problems exemplified. In addition, problems other than those listed will become apparent from the description in this specification, and such problems may also be problems of one embodiment of the present invention. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device including a first control circuit having a first transistor using a silicon substrate for its channel, a second control circuit provided on the first control circuit and having a second transistor using a metal oxide for its channel, a memory circuit provided on the second control circuit and having a third transistor using a metal oxide for its channel, and a global bit line and an inverted global bit line having a function of transmitting a signal between the first control circuit and the second control circuit, wherein the first control circuit has a sense amplifier circuit having an input terminal and an inverted input terminal, and during a first period in which data is read from the memory circuit to the first control circuit, the second control circuit controls whether or not to charge the global bit line and the inverted global bit line from which electric charge has been discharged, depending on the data read from the memory circuit.

[0011] One embodiment of the present invention includes a first control circuit having a first transistor using a silicon substrate for its channel, a second control circuit provided on the first control circuit and having a second transistor using a metal oxide for its channel, a memory circuit provided on the second control circuit and having a third transistor using a metal oxide for its channel, a global bit line and an inverted global bit line having a function of transmitting signals between the first control circuit and the second control circuit, and a plurality of changeover switches provided between the global bit line and the second control circuit and between the inverted global bit line and the second control circuit, wherein the first control circuit has a sense amplifier having an input terminal and an inverted input terminal. In a first period in which data is read from the memory circuit to the first control circuit, the second control circuit has a function of controlling whether or not to discharge the charges precharged to the one bit line and the inverted global bit line in accordance with the data read from the memory circuit, and in the first period, the second control circuit switches so that the global bit line and the input terminal, and the inverted global bit line and the inverted input terminal, are each in a conductive state, and in a second period in which the data read from the memory circuit is refreshed, the second control circuit switches so that the global bit line and the inverted input terminal, and the inverted global bit line and the input terminal, are each in a conductive state.

[0012] One embodiment of the present invention includes a first control circuit having a first transistor using a silicon substrate for its channel, a second control circuit provided on the first control circuit and having a second transistor using a metal oxide for its channel, a memory circuit provided on the second control circuit and having a third transistor using a metal oxide for its channel, and a global bit line and an inverted global bit line having a function of transmitting a signal between the first control circuit and the second control circuit, the first control circuit having a sense amplifier having an amplifier circuit, an output terminal, an inverted output terminal, a first switch, a second switch, and a signal inversion circuit, the first switch being provided between the global bit line and the output terminal, the second switch being provided between the inverted global bit line and the inverted output terminal, and the signal inversion circuit inverting logical data corresponding to the potentials of the global bit line and the inverted global bit line. the second control circuit has a function of providing a potential to an output terminal and an inverted output terminal electrically connected to the amplifier circuit, and during a first period in which data is read from the memory circuit to the first control circuit, the second control circuit has a function of controlling whether or not to discharge the charges precharged to the global bit line and the inverted global bit line in accordance with the data read from the memory circuit, and during the first period, turns off the first switch and the second switch to provide a potential obtained by inverting logical data in accordance with the potentials of the global bit line and the inverted global bit line to the output terminal and the inverted output terminal electrically connected to the amplifier circuit, and during a second period in which the data read from the memory circuit is refreshed, turns on the first switch and the second switch to provide the potentials of the output terminal and the inverted output terminal amplified by the amplifier circuit to the global bit line and the inverted global bit line.

[0013] In one aspect of the present invention, the semiconductor device is preferably such that the global bit line and the inverted global bit line are provided in a direction perpendicular or approximately perpendicular to the surface of the silicon substrate.

[0014] In one embodiment of the present invention, the metal oxide preferably contains In, Ga, and Zn.

[0015] In one embodiment of the present invention, a semiconductor device is preferable in which the second control circuit has fourth to seventh transistors, a gate of the fourth transistor is electrically connected to a local bit line having a function of transmitting a signal between the second control circuit and the memory circuit, the fifth transistor has a function of controlling conduction between the gate of the fourth transistor and one of a source and a drain of the fourth transistor, the sixth transistor has a function of controlling conduction between the other of the source and the drain of the fourth transistor and a wiring to which a potential for causing a current to flow through the fourth transistor is applied, and the seventh transistor has a function of controlling conduction between the one of the source and the drain of the fourth transistor and a global bit line. Effect of the Invention

[0016] One embodiment of the present invention can provide a semiconductor device or the like having a novel structure. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure that can reduce manufacturing costs in a semiconductor device that functions as a memory device using an extremely low off current. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure that is excellent in low power consumption in a semiconductor device that functions as a memory device using an extremely low off current. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure that can reduce the size of a semiconductor device that functions as a memory device using an extremely low off current. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure that is excellent in reliability of data read out in a semiconductor device that functions as a memory device using an extremely low off current. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure that can perform writing back of data read out without inverting the logic of the data read out in a semiconductor device that functions as a memory device using an extremely low off current.

[0017] The description of multiple effects does not preclude the existence of other effects. In addition, one embodiment of the present invention does not necessarily have all of the exemplified effects. In addition, problems, effects, and novel features other than those described above regarding one embodiment of the present invention will become apparent from the description and drawings in this specification. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. [Diagram 2] 2A and 2B are a block diagram and a circuit diagram showing a configuration example of a semiconductor device. [Diagram 3] 3A and 3B are circuit diagrams showing configuration examples of a semiconductor device. [Figure 4] FIG. 4 is a circuit diagram showing a configuration example of a semiconductor device. [Diagram 5] FIG. 5 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 6] FIG. 6 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 7] FIG. 7 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 8] FIG. 8 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 9] FIG. 9 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 10] FIG. 10 is a timing chart showing an example of the configuration of a semiconductor device. [Figure 11] FIG. 11 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 12] FIG. 12 is a timing chart showing an example of the configuration of a semiconductor device. [Figure 13] FIG. 13 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 14] FIG. 14 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 15] FIG. 15 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 16]FIG. 16 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 17] FIG. 17 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 18] FIG. 18 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 19] FIG. 19 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 20] FIG. 20 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 21] FIG. 21 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 22] FIG. 22 is a circuit diagram showing a configuration example of a semiconductor device. [Diagram 23] FIG. 23 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 24] FIG. 24 is a circuit diagram showing a configuration example of a semiconductor device. [Diagram 25] FIG. 25 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 26] FIG. 26 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 27] FIG. 27 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 28] FIG. 28 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 29] FIG. 29 is a circuit diagram showing a configuration example of a semiconductor device. [Diagram 30] FIG. 30 is a circuit diagram showing a configuration example of a semiconductor device. [Diagram 31] FIG. 31 is a circuit diagram showing a configuration example of a semiconductor device. [Diagram 32] FIG. 32 is a circuit diagram showing a configuration example of a semiconductor device. [Diagram 33] FIG. 33 is a circuit diagram showing a configuration example of a semiconductor device. [Diagram 34] 34A and 34B are schematic diagrams showing configuration examples of a semiconductor device. [Diagram 35] FIG. 35 is a schematic diagram showing a configuration example of a semiconductor device. [Diagram 36] 36A and 36B are circuit diagrams showing configuration examples of a semiconductor device. [Figure 37] 37A and 37B are a block diagram and a circuit diagram showing a configuration example of a semiconductor device. [Figure 38] 38A and 38B are block diagrams showing configuration examples of a semiconductor device. [Figure 39] FIG. 39 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Diagram 40] 40A and 40B are schematic cross-sectional views showing configuration examples of a semiconductor device. [Diagram 41] 41A, 41B, and 41C are schematic cross-sectional views showing configuration examples of a semiconductor device. [Diagram 42] FIG. 42 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Diagram 43] FIG. 43 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Diagram 44] 44A, 44B, and 44C are a top view and a schematic cross-sectional view showing a configuration example of a semiconductor device. [Diagram 45] 45A, 45B, 45C, and 45D are top views for explaining configuration examples of a semiconductor device. [Figure 46] Fig. 46A is a diagram for explaining the classification of IGZO crystal structures, Fig. 46B is a diagram for explaining the XRD spectrum of a CAAC-IGZO film, and Fig. 46C is a diagram for explaining the ultrafine electron beam diffraction pattern of a CAAC-IGZO film. [Figure 47] FIG. 47 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 48] FIG. 48 is a conceptual diagram showing a configuration example of a semiconductor device. [Figure 49] 49A and 49B are schematic diagrams illustrating an example of an electronic component. [Figure 50] FIG. 50 is a diagram showing an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the embodiment and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0020] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0021] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0022] In this specification, for example, the power supply potential VDD may be abbreviated to potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0023] Furthermore, when the same reference symbol is used for multiple elements, particularly when it is necessary to distinguish between them, identification symbols such as “_1”, “_2”, "[n]”, "[m,n]”, etc. may be added to the reference symbol. For example, the second wiring GL is written as wiring GL[2].

[0024] (Embodiment 1) Structural examples of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

[0025] Note that the semiconductor device is a device that utilizes semiconductor characteristics, and is a circuit including a semiconductor element (transistor, diode, photodiode, etc.) or a device having the circuit. The semiconductor device described in this embodiment can function as a memory device that uses a transistor with extremely low off-state current.

[0026] <Configuration Example 1 of Semiconductor Device> FIG. 1 is a block diagram for explaining a schematic diagram of a cross-sectional structure of a semiconductor device 10. As shown in FIG.

[0027] The semiconductor device 10 has a plurality of element layers 20_1 to 20_M (M is a natural number) on a silicon substrate 50. Each of the element layers 20_1 to 20_M has a transistor layer 30 and a transistor layer 40. The transistor layer 40 is composed of a plurality of transistor layers 41_1 to 41_k (k is a natural number equal to or greater than 2).

[0028] In the schematic diagram shown in FIG. 1, the z-axis direction is defined in order to explain the arrangement of each component. The z-axis direction refers to a direction perpendicular or approximately perpendicular to the surface of the silicon substrate 50. Note that "approximately perpendicular" refers to a state in which the components are arranged at an angle of 85 degrees or more and 95 degrees or less. Note that for ease of understanding, the z-axis direction may be referred to as the vertical direction. Note that the surface of the silicon substrate 50 corresponds to a plane formed by the x-axis and y-axis defined in a direction perpendicular or approximately perpendicular to the z-axis direction. Note that for ease of understanding, the x-axis direction may be referred to as the depth direction and the y-axis direction as the horizontal direction.

[0029] The transistor layer 40, which is composed of a plurality of transistor layers 41_1 to 41_k, includes a memory circuit having a plurality of memory cells (not shown) in each transistor layer. Each memory cell has a transistor and a capacitor. The capacitor may be called a capacitive element. The element layer refers to a layer in which elements such as a capacitor and a transistor are provided, and is a layer having materials such as a conductor, a semiconductor, and an insulator.

[0030] Note that the memory cells of the transistor layers 41_1 to 41_k can be called dynamic oxide semiconductor random access memories (DOSRAMs) that use transistors having an oxide semiconductor in a channel formation region (hereinafter, referred to as OS transistors) as memory. Since the memory cells can be configured with one transistor and one capacitor, high memory density can be achieved. Furthermore, by using OS transistors, the data retention period can be increased.

[0031] In one embodiment of the present invention, a memory cell having an OS transistor is used, and by utilizing the extremely low leakage current (hereinafter, off-current) that flows between the source and drain when the transistor is off, a charge corresponding to a desired voltage can be held in a capacitor at the other of the source and drain. In other words, data once written in the memory cell can be held for a long time. This reduces the frequency of data refresh, leading to low power consumption.

[0032] In addition, in a memory cell using an OS transistor, data can be rewritten and read by charging or discharging an electric charge, so data can be written and read a virtually unlimited number of times. A memory cell using an OS transistor has excellent rewrite endurance because it does not involve structural changes at the atomic level, as in magnetic memory or resistive memory. Furthermore, unlike flash memory, a memory cell using an OS transistor does not exhibit instability due to an increase in electron trap centers even when repeatedly rewritten.

[0033] In addition, memory cells using OS transistors can be freely arranged on a silicon substrate that has transistors with silicon in the channel formation region (hereinafter, Si transistors), making integration easy. In addition, OS transistors can be manufactured using the same manufacturing equipment as Si transistors, making them low-cost to manufacture.

[0034] Furthermore, if an OS transistor includes a backgate electrode in addition to the gate electrode, source electrode, and drain electrode, it can be a four-terminal semiconductor element. It can be configured as an electric circuit network that can independently control the input and output of signals flowing between the source and drain depending on the voltage applied to the gate electrode or backgate electrode. Therefore, the circuit can be designed with the same concept as LSI. In addition, OS transistors have better electrical characteristics than Si transistors in high-temperature environments. Specifically, the ratio of on-current to off-current is large even at high temperatures of 125°C to 150°C, so good switching operation can be performed.

[0035] The silicon substrate 50 has a control circuit for writing or reading data to or from a memory cell selected in the transistor layer 30 via a global bit line (sometimes referred to as a global bit line GBL) and a local bit line (sometimes referred to as a local bit line LBL). The control circuit has a plurality of Si transistors using the silicon substrate 50 as a channel. The control circuit in the silicon substrate 50 has a sense amplifier circuit and the like constituted by Si transistors. The control circuit in the silicon substrate 50 may be referred to as a first control circuit.

[0036] The transistor layer 30 has a function of writing and reading data to and from a memory cell selected from one of the plurality of memory cells that the transistor layer 40 has.

[0037] The transistor layer 30 includes a control circuit having a read transistor for reading data and a transistor for controlling writing and reading data. The gate of the read transistor is connected to a local bit line connected to one of the memory cells. With this configuration, the read transistor can amplify a slight potential difference on the local bit line when reading data and output it to the global bit line. The control circuit provided in the transistor layer 30 functions as an amplifier circuit composed of OS transistors. The control circuit in the transistor layer 30 may be called a second control circuit.

[0038] Note that the second control circuit may have a function of holding a potential in a gate of a reading transistor according to a threshold voltage of the reading transistor. With this configuration, the reading transistor can reduce variations in data read from memory cells.

[0039] The local bit line LBL is a wiring directly connected to the memory cell. The global bit line GBL is a wiring electrically connected via a second control circuit by selecting one of the multiple local bit lines. The global bit line GBL or the local bit line LBL has a function of transmitting a signal. A data signal given to the global bit line GBL or the local bit line LBL corresponds to a signal written to the memory cell or a signal read from the memory cell. The data signal is explained as a binary signal having a high level or low level potential corresponding to data 1 or data 0. The data signal may be multi-valued, having three or more values. The global bit line GBL may function as an inverted global bit line GBLB as a wiring pair for reading data.

[0040] 1, the transistor layer 40 is stacked with the transistor layer 30 in the z-axis direction. The transistor layer 40 of each of the element layers 20_1 to 20_M is selected by a second control circuit. The second control circuit has a function of converting a data signal written in a memory cell into a change in the potential of the global bit line GBL and outputting it to the first control circuit by utilizing the difference in the amount of current flowing through the read transistor of the transistor layer 30. The second control circuit also has a function of providing the data signal output by the first control circuit to the local bit line.

[0041] In one embodiment of the present invention, an OS transistor having an extremely low off-state current is used as a transistor provided in each element layer. Therefore, the frequency of refreshing data held in a memory cell can be reduced, and a semiconductor device with low power consumption can be obtained. The OS transistor can be provided in a stacked manner and can be repeatedly manufactured in the vertical direction using the same manufacturing process, thereby reducing manufacturing costs. In addition, in one embodiment of the present invention, the transistors constituting the memory cell can be arranged in a vertical direction instead of a planar direction, thereby improving memory density and miniaturizing the device. Furthermore, since the OS transistor has smaller fluctuations in electrical characteristics than Si transistors even in a high-temperature environment, the semiconductor device can function as a highly reliable memory device.

[0042] 2A, there is shown a block diagram of device layer 20, which corresponds to any one of device layers 20_1 through 20_M of FIG.

[0043] As shown in FIG. 1, the element layer 20 according to one embodiment of the present invention is configured to include a plurality of transistor layers 40 having memory cells on a transistor layer 30 in the z-axis direction. This configuration allows the transistor layer 30 and the transistor layer 40 to be closer to each other. The parasitic capacitance can be reduced by shortening the local bit line. The manufacturing cost can be reduced by repeatedly manufacturing a plurality of transistor layers 40 in the vertical direction using the same manufacturing process.

[0044] FIG. 2B is a diagram showing, by circuit symbols, each component in the element layer 20 shown in FIG. 2A.

[0045] The transistor layer 30 includes a control circuit 35 having a transistor 31, a transistor 32, a transistor 33, and a transistor 34. Each of the transistor layers 41_1 and 41_2 includes a plurality of memory cells 42. The memory cells 42 include a transistor 43 and a capacitor 44. The transistor 43 functions as a switch that switches a conductive state (ON) or a non-conductive state (OFF) between the local bit line LBL and the capacitor 44 in response to control of a word line WL connected to the gate. The local bit line LBL is connected to the gate of the transistor 31. The word line WL switches the transistor 43 ON or OFF according to a word signal (sometimes referred to as a signal WL) provided to the word line WL. The capacitor 44 is connected to a wiring CSL that provides a fixed potential.

[0046] Each transistor in the control circuit 35 is connected as shown in FIG. 2B. Specifically, one of the source and drain of the transistor 33 is connected to the gate of the transistor 31. The other of the source and drain of the transistor 33 is connected to one of the source and drain of the transistor 34 and one of the source and drain of the transistor 31. One of the source and drain of the transistor 32 is connected to the other of the source and drain of the transistor 31. The other of the source and drain of the transistor 32 is connected to the wiring SL. The other of the source and drain of the transistor 34 is connected to the global bit line GBL. The transistors 32, 33, and 34 function as switches that switch the conductive state or non-conductive state between the source and the drain according to the control of the signals RE, WE, and MUX connected to the gates. The signals RE, WE, and MUX are signals for switching the transistors functioning as switches on or off, and as an example, the signals can function as on at H level and off at L level.

[0047] The transistor 43 is the above-described OS transistor. The capacitor 44 has an insulator sandwiched between conductors serving as electrodes. Note that, in addition to metal, a semiconductor layer having conductivity can be used as the conductor constituting the electrodes. The arrangement of the capacitor 44 will be described in detail later. In addition to the arrangement in which the capacitor 44 is arranged in an overlapping position above or below the transistor 43, a part of the semiconductor layer or electrode constituting the transistor 43 can be used as one of the electrodes of the capacitor 44.

[0048] The transistor 31 has a function of causing a current to flow between the source and drain of the transistor 31 in response to the potential of the local bit line LBL. When the potential of the gate of the transistor 31 exceeds the threshold voltage of the transistor 31, a current flows between the source and drain.

[0049] The control circuit 35 has a function of controlling whether or not a current flows between the source and drain of the transistor 31 between the wiring SL and the global bit line GBL, or a function of transmitting the potential of the global bit line GBL to the local bit line LBL, or a function of discharging the potential of the gate of the transistor 31 to the wiring SL through between the source and drain of the transistor 31.

[0050] The transistors 31 to 34 are formed of OS transistors, similar to the transistor 43. The transistor layers 30 and 40 constituting the element layer 20 using OS transistors can be stacked and arranged on the silicon substrate 50 having Si transistors, and therefore integration can be easily performed.

[0051] 3A shows an example of the circuit configuration of a control circuit 51 corresponding to a first control circuit composed of Si transistors on a silicon substrate 50. The control circuit 51 includes a switch circuit 52, a precharge circuit 53, a precharge circuit 54, a sense amplifier 55, a global bit line GBL, an inverted global bit line GBLB, a bit line BL, and an inverted bit line BLB connected to the control circuit 51. In this specification, some of the terminals or wirings connected to the global bit line GBL or the inverted global bit line GBLB in the control circuit 51 may be referred to as the input terminal and inverted input terminal of the control circuit 51. The bit line BL and inverted bit line BLB, which are wirings connected to the sense amplifier 55, may be referred to as the output terminal and inverted output terminal of the control circuit 51.

[0052] 3A, the switch circuit 52 has, for example, n-channel transistors 52_1 and 52_2. The transistors 52_1 and 52_2 switch the conductive state between the wiring pair of the global bit line GBL and the inverted global bit line GBLB and the wiring pair of the bit line BL and the inverted bit line BLB in response to a signal on the wiring CSEL. The switch circuit 52 may be configured to use an analog switch combined with a p-channel transistor.

[0053] The precharge circuit 53 is composed of n-channel transistors 53_1 to 53_3 as shown in FIG. 3A. The precharge circuit 53 is a circuit for precharging to a potential VPRE corresponding to a potential VDD / 2 between the bit line BL and the inverted bit line BLB in response to a signal on the wiring EQ. The precharge circuit 54 is composed of p-channel transistors 54_1 to 54_3 as shown in FIG. 3A. The precharge circuit 54 is a circuit for precharging to a potential VPRE corresponding to a potential VDD / 2 between the bit line BL and the inverted bit line BLB in response to a signal on the wiring EQB. Either one of the precharge circuits 53 and 54 may be configured. The precharge circuits 53 and 54 have a function of electrically connecting the bit line BL and the inverted bit line BLB and equalizing them.

[0054] 3A, the sense amplifier 55 is composed of p-channel transistors 55_1 and 55_2 and n-channel transistors 55_3 and 55_4 connected to a wiring SAP or a wiring SAN. The wiring SAP or the wiring SAN has a function of supplying VDD or VSS. The transistors 55_1 to 55_4 are transistors that configure an inverter loop.

[0055] Moreover, Fig. 3B shows a diagram for explaining a circuit block corresponding to the control circuit 51 described in Fig. 3A etc. As shown in Fig. 3B, the control circuit 51 may be represented as a block in the drawings etc.

[0056] Fig. 4 is a circuit diagram for explaining an example of the operation of the semiconductor device 10 of Fig. 1. Fig. 4 illustrates the circuit blocks explained in Fig. 3A and Fig. 3B.

[0057] 4, the transistor layers 41_1 to 41_k each have a memory cell 42. The memory cell 42 is connected to a pair of local bit lines LBL and LBL_pre. The memory cell 42 connected to the local bit line LBL is a memory cell to which data is written or read. The local bit line LBL_pre is a local bit line that is precharged for potential comparison, and the memory cell connected to the local bit line LBL_pre continues to hold data.

[0058] The local bit line LBL is connected to the global bit line GBL via the control circuit 35. The local bit line LBL_pre is electrically connected to the inverted global bit line GBLB via the control circuit 35_pre. The global bit line GBL and the inverted global bit line GBLB are electrically connected to the control circuit 51. Note that the illustration of signals RE, WE, and MUX that control the on or off of the transistors 32, 33, and 34 of the control circuit 35 and the control circuit 35_pre is omitted. The signals RE, WE, and MUX are signals that perform different controls in the control circuit 35 and the control circuit 35_pre. For example, the signals that control the on or off of the transistors 32, 33, and 34 of the control circuit 35 are signals RE1, WE1, and MUX1 (not shown), and the signals that control the on or off of the transistors 32, 33, and 34 of the control circuit 35_pre are signals RE2, WE2, and MUX2 (not shown).

[0059] 5 to 9 are schematic diagrams for explaining the operation of the circuit diagram shown in FIG. 5. In FIG. 5 to 9, in order to make the explanation easier to understand, some of the wirings that are electrically connected by turning on or off a transistor that functions as a switch may be illustrated with a thick line. In the explanation, the data held in the memory cell 42 that performs data reading and writing back is data "1", that is, a case where a potential of H level is held (illustrated as "H" in the drawings). In addition, the transistors of the control circuits 35 and 35_pre that are turned off are marked with a cross.

[0060] 5 is a schematic diagram for explaining a period during which the local bit line LBL and the local bit line LBL_pre are precharged. During the precharge period, the transistors 33 and 34 of both the control circuits 35 and 35_pre are turned on to apply a precharge voltage V LBL The precharge is performed by transmitting the precharge voltage V to the local bit line LBL and the local bit line LBL_pre. By precharging, each line is boosted to the power supply voltage VDD (for example, 1.5 V). LBLcorresponds to the potential VPRE described above.

[0061] In FIG. 6, the gate of transistor 31 is connected to the threshold voltage V TH The threshold voltage V TH 1 is a schematic diagram illustrating a period for performing a correction of the amount of charge applied to the global bit line GBL and the inverted global bit line GBLB. During this period, the control circuits 35 and 35_pre turn off both transistors 34 to prevent the precharge voltage V LBL is discharged to the line SL. During the discharge, the voltage of the line SL is set to, for example, half the precharge voltage. The current I dis The gate potential of transistor 31 is the threshold voltage 0.5 × V LBL +V TH During this period, the global bit line GBL and the inverted global bit line GBLB are set to a voltage V 0 Precharge to voltage V 0 is set to a voltage lower than the potential applied to other wirings, for example, 0V.

[0062] 7, the transistor 43 of the memory cell 42 from which data is to be read is turned on, and charge sharing is performed between the capacitor 44 and the local bit line LBL. The potential of the local bit line LBL is set to a voltage of 0.5×V LBL +V TH to voltage 0.5 x V LBL +V TH +ΔV. The voltage ΔV here is due to the movement of charges caused by the H-level potential held in the memory cell 42. The control circuits 35 and 35_pre turn off the transistor 33 and raise the potential of the line SL to a voltage V 0 For example, VDD. The control circuit 35 controls the gate voltage of the transistor 31 to be higher than 0.5×V LBL +V TH +ΔV, the current I H On the other hand, the control circuit 35_pre controls the gate voltage of the transistor 31 to be 0.5×V LBL +VTH Therefore, less current flows than in the control circuit 35. Therefore, the voltage of the global bit line GBL becomes higher than the voltage of the inverted global bit line GBLB.

[0063] 8, the transistors 32, 33 of both the control circuits 35, 35_pre are turned off, and the sense amplifier of the control circuit 51 is activated to fix the voltages of the global bit line GBL and the inverted global bit line GBLB at H level or L level. Note that the activation of the sense amplifier refers to the operation of fixing the H level or L level of each wiring according to the voltage difference between the global bit line GBL and the inverted global bit line GBLB.

[0064] In FIG. 9, the transistors 33, 34 of both the control circuits 35, 35_pre and the transistor 43 of the memory cell 42 are turned on, and the voltages of the global bit line GBL and the inverted global bit line GBLB determined in the previous period are written back to the memory cell 42.

[0065] With the above configuration, it is possible to write back a voltage according to the logic of data read by charge sharing to the memory cell 42 without inverting the logic. That is, in the memory cell 42 from which data "1", that is, H-level potential, has been read, data "1", that is, H-level potential, can be written back.

[0066] Fig. 10 shows a timing chart for explaining the operation including each period explained in Fig. 5 to Fig. 9. Note that the timing chart in Fig. 10 shows the wiring pair of the global bit line GBL and the inverted global bit line GBLB separately for the case where data is at H level (data=H) and the case where data is at L level (data=L).

[0067] In the timing chart shown in Fig. 10, the period from time T11 to time T13 corresponds to a data write period. The period from time T13 to time T16 corresponds to a threshold voltage acquisition period, i.e., a correction period. The period from time T16 to time T18 corresponds to a data read period. The period from time T18 to time T20 corresponds to a data write-back period. Note that in Fig. 10, the signals RE, WE, and MUX are different signals between the control circuit 35 and the control circuit 35_pre, but because the control circuit 35 and the control circuit 35_pre perform the same operation, they will be described as the signals RE, WE, and MUX.

[0068] At time T11, the signals MUX and WE are set to H level to transfer write data from the sense amplifier, thereby charging one of the pair of lines, the global bit line GBL or the inverted global bit line GBLB. The potential of the local bit line LBL rises. The potential of the word line WL is set to H level, and the potential applied to the local bit line LBL (H level in the case of FIG. 10) is written to the memory cell 42.

[0069] At time T12, the potential of the word line WL is set to the L level, and data is held in the memory cell .

[0070] At time T13, the lines SAP and SAN are both set to VDD, and the signals on the lines EQ and EQB are inverted to set the line pair of the global bit line GBL and the inverted global bit line GBLB to H level. The local bit line LBL_pre is precharged to a H level potential. Then, the signal MUX is set to L level. The signal WE may also be set to L level.

[0071] At time T14, the signals RE and WE are set to H level. The potential of the local bit line LBL and the potential of the local bit line LBL_pre drop due to discharge via the transistor 31. This discharge stops when the voltage between the gate and source of the transistor 31 becomes the threshold voltage of the transistor 31. Also, at time T14, both the lines SAP and SAN are set to VSS (0V), and the line pair of the global bit line GBL and the inverted global bit line GBLB is set to L level.

[0072] At time T15, both signals WE and RE are set to L level. A potential corresponding to the threshold voltage of the transistor 31 is held in the local bit line LBL and the local bit line LBL_pre. The signals of the wirings EQ and EQB are inverted again to stop precharging. In other words, the wiring pair of the global bit line GBL and the inverted global bit line GBLB is in an electrically floating state. Also, at time T15, the potential of the wiring SL is switched from L level to H level. This switching makes it possible to switch the direction of the current flowing through the transistor 31.

[0073] At time T16, the word line WL is set to H level to perform charge sharing. The potential of the local bit line LBL changes according to the data written to the memory cell 42. When H level data is written to the memory cell 42, the potential of the local bit line LBL increases, and when L level data is written to the memory cell 42, the potential of the local bit line LBL decreases. On the other hand, the potential of the local bit line LBL_pre does not change because charge sharing due to the operation of the word line WL is not performed.

[0074] At time T17, the signals RE and MUX are set to H level, so that a current flows through the transistor 31 of the control circuit 35 and the transistor 31 of the control circuit 35_pre according to the potentials of the local bit line LBL and the local bit line LBL_pre. Since the potentials of the local bit line LBL and the local bit line LBL_pre are different, a difference occurs in the current flowing through the transistor 31 of the control circuit 35 and the transistor 31 of the control circuit 35_pre. This current difference corresponds to the potential of the local bit line LBL that changes due to charge sharing, that is, the data read from the memory cell 42. Therefore, the data of the memory cell 42 can be converted into the amount of change in the potential of the wiring pair of the global bit line GBL and the inverted global bit line GBLB, as shown in FIG.

[0075] At time T18, the signal RE is set to the L level. Then, the power supply voltages (VDD, VSS) are applied to the lines SAP and SAN to operate the sense amplifier 55. The operation of the sense amplifier 55 determines the potential of the line pair of the global bit line GBL and the inverted global bit line GBLB.

[0076] At time T19, the signal WE is set to H level, so that a voltage according to the logic of the read data can be written back to the memory cell 42 again.

[0077] At time T20, the signals MUX, WL, and WE are set to level L. In the memory cell 42, the write-back of data corresponding to the logic of the read data is completed.

[0078] In the configuration shown in Fig. 4, the local bit line LBL is precharged via the global bit line GBL, but this is not limiting. For example, as shown in Fig. 11, it is preferable to provide a transistor 37 in the same layer as the control circuit, and to control the transistor 37 with a signal PE to perform a voltage Vp precharge. This configuration can reduce the power consumption for charging and discharging the global bit line GBL.

[0079] Fig. 12 is a timing chart for explaining the operation in the configuration shown in Fig. 11. As shown in the timing chart of Fig. 12, the signal PE is controlled to be at H level from time T13 to time T14. By adopting this configuration, unnecessary charging of the global bit line GBL and the inverted global bit line GBLB can be suppressed.

[0080] In one embodiment of the present invention, in a transistor layer including a memory cell and a control circuit, when data read from a memory cell is written back, the direction of a current flowing through the transistor 31 is inverted by switching the potentials of the wiring SL and the global bit line GBL. With this configuration, data can be written back to the memory cell without inverting the logic of the data.

[0081] <Configuration Example 2 of Semiconductor Device> 13 is another circuit diagram for explaining an operation example of the semiconductor device 10 of FIG. 1. In addition to the circuit blocks explained in FIG. 3A and FIG. 3B, FIG. 13 illustrates a configuration example in which changeover switches SW and SW_B are provided between the input terminal of the control circuit 51 and the global bit line GBL and the inverted global bit line GBLB for switching the connection between the two. As illustrated in FIG. 13, the input terminal of the control circuit 51 can switch the connection between the global bit line GBL and the inverted global bit line GBLB by the changeover switches SW and SW_B. Note that one of the pair of input terminals of the control circuit 51 may be called a first input terminal and the other a second input terminal.

[0082] 13, the transistor layers 41_1 to 41_k each have a memory cell 42. The memory cell 42 is connected to a pair of a local bit line LBL and a local bit line LBL_pre. The memory cell 42 connected to the local bit line LBL is a memory cell to which data is written or read. The local bit line LBL_pre is a precharged local bit line, and the memory cell connected to the local bit line LBL_pre continues to hold data.

[0083] The local bit line LBL is connected to the global bit line GBL via the control circuit 35. The local bit line LBL_pre is electrically connected to the inverted global bit line GBLB via the control circuit 35_pre. The global bit line GBL and the inverted global bit line GBLB are electrically connected to the control circuit 51 via the changeover switch SW or the changeover switch SW_B. Note that the signals RE, WE, and MUX that control the on or off of the transistors 32, 33, and 34 of the control circuit 35 and the control circuit 35_pre are omitted from the illustration. The signals RE, WE, and MUX are signals that perform different controls in the control circuit 35 and the control circuit 35_pre. For example, the signals that control the on or off of the transistors 32, 33, and 34 of the control circuit 35 are signals RE1, WE1, and MUX1, and the signals that control the on or off of the transistors 32, 33, and 34 of the control circuit 35_pre are signals RE2, WE2, and MUX2.

[0084] 14 to 17 are schematic diagrams for explaining the operation of the circuit diagram shown in FIG. 13. In order to make the explanation easier to understand, some of the wirings that are electrically connected by turning on or off a transistor that functions as a switch may be illustrated with a thick line in FIGS. 14 to 17. The explanation will be given assuming that the data held in the memory cell 42 that reads and writes back data is data "1", that is, a case where a potential of the H level is held (illustrated as "H" in the drawings). Also, the transistors of the control circuits 35 and 35_pre that are turned off are marked with a cross.

[0085] 14 to 17, the data writing to the memory is completed, and the voltages of the local bit lines LBL and LBL_pre caused by the threshold voltage correction operation are held as the initial state. LBL When the voltage is half that of the threshold voltage V TH The voltage considered is 0.5 x V LBL +V TH is held, and V 1 (for example, VDD) is held. The threshold voltage V TH The voltage can be held by setting the wiring SL to VSS and discharging the charge to the wiring SL through the transistor 31. The voltage held in the local bit line LBL and the local bit line LBL_pre is not limited to the threshold voltage and may be another voltage.

[0086] 14, the transistor 43 of the memory cell 42 from which data is to be read is turned on, and charge sharing is performed between the capacitor 44 and the local bit line LBL. The potential of the local bit line LBL is set to a voltage of 0.5×V LBL +V TH to voltage 0.5 x V LBL +V TH +ΔV. The voltage ΔV here is due to the movement of charges caused by the H-level potential held in the memory cell 42. In addition, the control circuits 35 and 35_pre turn off the transistor 33 and raise the potential of the line SL to a voltage V 0 For example, VSS (0V) is set to a value lower than the voltage of the transistor 31 of the control circuit 35. The gate voltage of the transistor 31 of the control circuit 35 is set to a value lower than the voltage of 0.5×V LBL +V TH +ΔV, the current I H On the other hand, the transistor 31 of the control circuit 35_pre has a gate voltage of 0.5×V LBL+V TH Therefore, compared to the control circuit 35, no current flows. Therefore, the voltage of the global bit line GBL is V 1 -ΔV, and the voltage of the inverted global bit line GBLB is a voltage V higher than the voltage of the global bit line GBL. 1 14, a first input terminal of the control circuit 51 is connected to one of the global bit line GBL or the inverted global bit line GBLB by the changeover switches SW and SW_B. A second input terminal of the control circuit 51 is connected to the other of the global bit line GBL or the inverted global bit line GBLB by the changeover switches SW and SW_B.

[0087] In Fig. 15, the transistors 32 and 33 are turned off. In addition, in the state of Fig. 15, the first input terminal and the second input terminal of the control circuit 51 are not connected to either the global bit line GBL or the inverted global bit line GBLB by the changeover switches SW and SW_B. The global bit line GBL or the inverted global bit line GBLB is in an electrically floating state. In this state, the first input terminal of the control circuit 51 is connected to the voltage V 1 -ΔV is maintained, and the voltage V 1 The voltage −ΔV here is due to a change in charge caused by a current flowing from the global bit line GBL through the transistor 31 to the line SL.

[0088] In FIG. 16, similarly to the state of FIG. 15, the first input terminal and the second input terminal of the control circuit 51 are not connected to either the global bit line GBL or the inverted global bit line GBLB by the changeover switches SW and SW_B. The global bit line GBL or the inverted global bit line GBLB is in an electrically floating state. In this state, the sense amplifier of the control circuit 51 is activated. The first input terminal is fixed to an L level, and the second input terminal is fixed to an H level. As shown in FIG. 16, the sense amplifier is activated with the global bit line GBL or the inverted global bit line GBLB in an electrically floating state, so that the power consumption for charging and discharging the load of the global bit line GBL or the inverted global bit line GBLB can be reduced, and the time until data is fixed can be shortened.

[0089] 17, a first input terminal of the control circuit 51 is connected to the other of the global bit line GBL or the inverted global bit line GBLB by the changeover switches SW and SW_B. A second input terminal of the control circuit 51 is connected to one of the global bit line GBL or the inverted global bit line GBLB by the changeover switches SW and SW_B. That is, the connection is made in a state different from the state in FIG. 14. Then, the global bit line GBL is determined to be at the H level, and the inverted global bit line GBLB is determined to be at the L level. Then, the transistors 33 and 34 and the transistor 43 of the memory cell 42 are turned on, and the determined voltages of the global bit line GBL and the inverted global bit line GBLB are written back to the memory cell 42.

[0090] With the above configuration, it is possible to write back a voltage according to the logic of data read by charge sharing to the memory cell 42 again without inverting the logic.

[0091] 18 to 21, configuration examples different from those described in FIGS. 14 to 17 will be described.

[0092] In Fig. 18, the transistor 43 of the memory cell 42 from which data is to be read is turned on, and charge sharing is performed between the capacitor 44 and the local bit line LBL. The explanation of Fig. 18 is the same as that of Fig. 14. In the state of Fig. 18, a first input terminal of the control circuit 51 is connected to one of the global bit line GBL or the inverted global bit line GBLB by the changeover switches SW and SW_B. A second input terminal of the control circuit 51 is connected to the other of the global bit line GBL or the inverted global bit line GBLB by the changeover switches SW and SW_B.

[0093] In Fig. 19, the transistors 32 and 33 are turned off. In addition, in the state of Fig. 19, the first input terminal and the second input terminal of the control circuit 51 are not connected to either the global bit line GBL or the inverted global bit line GBLB by the changeover switches SW and SW_B. The global bit line GBL or the inverted global bit line GBLB is in an electrically floating state. In this state, the first input terminal of the control circuit 51 is connected to the voltage V 1 is held, and the voltage V 1 -ΔV is maintained.

[0094] In Fig. 20, a first input terminal of the control circuit 51 is connected to the other of the global bit line GBL or the inverted global bit line GBLB by the changeover switches SW and SW_B. A second input terminal of the control circuit 51 is connected to one of the global bit line GBL or the inverted global bit line GBLB by the changeover switches SW and SW_B. In other words, the connection is made in a state different from the state in Fig. 18. In this state, the sense amplifier of the control circuit 51 is activated. The global bit line GBL is fixed to the H level, and the inverted global bit line GBLB is fixed to the L level.

[0095] In FIG. 21, the transistors 33 and 34 and the transistor 43 of the memory cell 42 are turned on, and the determined voltages of the global bit line GBL and the inverted global bit line GBLB are written back to the memory cell 42.

[0096] With the above configuration, it is possible to write back a voltage corresponding to the logic of data read by charge sharing to the memory cell 42 again without inverting the logic. In addition, in the configurations described in Fig. 18 to Fig. 21, when data is output from the sense amplifier to the outside of the memory, the data is output via the bit line BL and the inverted bit line BLB, but the logic of the global bit line GBL and the inverted global bit line GBLB and the logic of the bit line BL and the inverted bit line BLB can be output without being inverted.

[0097] 22 to 24, configuration examples different from those described in FIGS. 14 to 17 and FIGS. 18 to 21 will be described.

[0098] In Fig. 22, the transistor 43 of the memory cell 42 from which data is to be read is turned on, and charge sharing is performed between the capacitor 44 and the local bit line LBL. The explanation for Fig. 22 is the same as that for Fig. 14 or 18. In the state shown in Fig. 22, a first input terminal of the control circuit 51 is connected to one of the global bit line GBL or the inverted global bit line GBLB by the changeover switches SW and SW_B. A second input terminal of the control circuit 51 is connected to the other of the global bit line GBL or the inverted global bit line GBLB by the changeover switches SW and SW_B.

[0099] 23, the transistors 32 and 33 are turned off to activate the sense amplifier in the control circuit 51. The global bit line GBL is set to the L level, and the inverted global bit line GBLB is set to the H level.

[0100] 24, the changeover switches SW and SW_B are switched to the first input terminal side of the control circuit 51, and the global bit line GBL and the inverted global bit line GBLB are shorted. In other words, only the switch of the bit line to be written back is switched. The transistors 33 and 34 and the transistor 43 of the memory cell 42 are turned on, and the voltages of the determined global bit line GBL and the inverted global bit line GBLB become H, and the data H is written back to the memory cell 42.

[0101] With the above configuration, a voltage according to the logic of data read by charge sharing can be written back to the memory cell 42 again without inverting the logic. Furthermore, with this driving method, only the global bit line GBL to be written back is charged and discharged, so energy consumption is half that of switching both the switches SW and SW_B, resulting in low power consumption driving. Furthermore, in the above-described configuration example, electrons can be extracted from the global bit line GBL to the wiring SL, so the voltage Vgs between the gate and source of the transistor 31 can be kept constant at all times. This allows the read operation to be performed at a high speed.

[0102] <Configuration Example 3 of Semiconductor Device> FIG. 25 is a circuit diagram for explaining an example different from the above-mentioned configuration example 1 and configuration example 2. FIG. 25 shows a circuit configuration example of a control circuit 51A corresponding to a first control circuit composed of Si transistors on a silicon substrate 50. The control circuit 51A illustrates a switch circuit 52, a precharge circuit 53, a sense amplifier 55, a potential setting circuit 59, a global bit line GBL connected to the control circuit 51A, an inverted global bit line GBLB, a bit line BL, and an inverted bit line BLB. In this specification, a part of the terminal or wiring connected to the global bit line GBL or the inverted global bit line GBLB in the control circuit 51A may be called an input terminal and an inverted input terminal of the control circuit 51. Also, the bit line BL and the inverted bit line BLB, which are wiring connected to the sense amplifier 55, may be called an output terminal and an inverted output terminal of the control circuit 51A.

[0103] 25, the switch circuit 52 has, for example, n-channel transistors 52_1 and 52_2. The transistors 52_1 and 52_2 switch the conductive state between the wiring pair of the global bit line GBL and the inverted global bit line GBLB and the wiring pair of the bit line BL and the inverted bit line BLB in response to a signal on the wiring CSEL. The switch circuit 52 may be configured to use an analog switch combined with a p-channel transistor.

[0104] 25, the precharge circuit 53 is composed of n-channel transistors 53_1 to 53_3. The precharge circuit 53 is a circuit for balancing and precharging between the bit line BL and the inverted bit line BLB in response to a signal on the wiring EQ. The potential VPRE corresponds to the potential VDD / 2 between the bit line BL and the inverted bit line BLB.

[0105] 25, the sense amplifier 55 is composed of p-channel transistors 55_1 and 55_2 and n-channel transistors 55_3 and 55_4 connected to the wiring SAP or wiring SAN. The wiring SAP or wiring SAN has a function of providing VDD or VSS. The transistors 55_1 to 55_4 are transistors that configure an inverter loop. The sense amplifier 55 also functions as a circuit that performs precharging by providing a precharge voltage to the wiring SAP or wiring SAN.

[0106] 25, the potential setting circuit 59 has n-channel transistors 57_1 and 57_2 connected to a wiring that applies a potential VSS, and n-channel transistors 58_1 and 58_2 connected to the sense amplifier 55. The transistors 57_1 and 57_2 are controlled to be turned on or off in response to a signal EN1. The currents flowing through the transistors 58_1 and 58_2 are controlled in response to the potentials of the global bit line GBL and the inverted global bit line GBLB connected to the gates of the transistors 58_1 and 58_2. The data on the bit line BL and the inverted bit line BLB when the sense amplifier is operated are determined in response to the currents flowing through the transistors 58_1 and 58_2.

[0107] Fig. 26 is a circuit diagram for explaining an example of the operation of the semiconductor device 10 of Fig. 1. Fig. 26 illustrates a configuration in which the configuration of Fig. 2 and the control circuit 51A described in Fig. 25 are applied to a control circuit provided on a silicon substrate 50.

[0108] 26, the transistor layers 41_1 to 41_k each have a memory cell 42. The memory cell 42 is connected to a pair of a local bit line LBL and a local bit line LBL_pre. The memory cell 42 connected to the local bit line LBL is a memory cell to which data is written or read. The local bit line LBL_pre is a precharged local bit line, and the memory cell connected to the local bit line LBL_pre continues to hold data.

[0109] The local bit line LBL is connected to the global bit line GBL via a control circuit 35. The local bit line LBL_pre is electrically connected to the inverted global bit line GBLB via a control circuit 35_pre. The global bit line GBL and the inverted global bit line GBLB are electrically connected to a control circuit 51A provided on a silicon substrate 50. Note that signals RE, WE, and MUX that are given to the control circuits 35 and 35_pre to control the on / off of the transistors are different between the control circuit 35 and the control circuit 35_pre, although not shown.

[0110] 27 to 33 are schematic diagrams for explaining the operation of the circuit diagram shown in FIG. 26. In order to make the explanation easier to understand, some of the wirings that are electrically connected by turning on or off a transistor that functions as a switch may be illustrated with a thick line in FIG. 27 to 33. The explanation will be given assuming that the data held in the memory cell 42 that reads and writes back data is data "1", that is, a case where a potential of H level is held (illustrated as "H" in the drawings). Also, the transistors of the control circuits 35 and 35_pre that are turned off are marked with a cross.

[0111] 27 is a schematic diagram for explaining a period during which the local bit line LBL and the local bit line LBL_pre are precharged. During the precharge period, the transistors 33 and 34 are turned on to apply a precharge voltage V LBL to the local bit line LBL and the local bit line LBL_pre, thereby performing precharging.

[0112] 28 is a schematic diagram for explaining a period during which the local bit line LBL and the local bit line LBL_pre are equalized. During the period during which the equalization is performed, the transistors 53_1 to 53_3 are turned on to make the transistors between the global bit line GBL and the inverted global bit line GBLB conductive.

[0113] FIG. 29 shows a gate of the transistor 31, which is connected to the threshold voltage V TH The voltage reflecting the threshold voltage V TH 1 is a schematic diagram illustrating a period for performing a correction of the amount of charge applied to the global bit line GBL and the inverted global bit line GBLB. During this period, the control circuits 35 and 35_pre turn off both transistors 34 to prevent the precharge voltage V LBL For example, the potential of the line SL is set to a precharge voltage V LBLWhen the voltage is half that of the discharge current I dis The gate potential of transistor 31 is the threshold voltage 0.5 × V LBL +V TH During this period, the global bit line GBL and the inverted global bit line GBLB are set to a voltage V 1 Precharge to voltage V 1 is set to, for example, a potential VPRE. During this period, the global bit line GBL and the inverted global bit line GBLB are precharged, and then the transistors 52_1 and 52_2 are turned off to electrically separate the global bit line GBL and the inverted global bit line GBLB (input terminal side) from the bit line BL and the inverted bit line BLB (output terminal side). The global bit line GBL and the inverted global bit line GBLB are electrically floating.

[0114] 30, the transistor 43 of the memory cell 42 from which data is to be read is turned on, and charge sharing is performed between the capacitor 44 and the local bit line LBL. The potential of the local bit line LBL is set to a voltage of 0.5×V LBL +V TH to voltage 0.5 x V LBL +V TH The voltage ΔV is due to the movement of charges caused by the H-level potential held in the memory cell 42. The control circuits 35 and 35_pre turn off the transistor 33 and set the potential of the line SL to the precharge voltage V LBL The transistor 31 in the control circuit 35 has its gate voltage lowered to a voltage of 0.5×V LBL +V TH +ΔV, the current I H On the other hand, the transistor 31 of the control circuit 35_pre has a gate voltage of 0.5×V LBL +V TH Therefore, compared to the control circuit 35, no current flows through the global bit line GBL. 1 -ΔV, and the voltage of the inverted global bit line GBLB becomes V 1It becomes.

[0115] 31, the transistors 57_1 and 57_2 are turned on under the control of a signal EN1. A current I flows through the transistors 58_1 and 58_2 in accordance with the voltages of the global bit line GBL and the inverted global bit line GBLB. GBL , I GBLB This current I GBL , I GBLB A potential difference occurs between the bit line BL and the inverted bit line BLB according to the difference.

[0116] 32, the transistors 57_1 and 57_2 are turned off and a power supply voltage is applied to the wirings SAP and SAN, thereby activating the sense amplifier of the control circuit 51A. The bit line BL and the inverted bit line BLB are determined to be at the H level or L level. The logic is the inverted logic of the logic read from the memory cell 42.

[0117] In FIG. 33, the transistors 52_1, 52_2, the transistors 33, and the transistor 43 of the memory cell are turned on, and the voltages of the bit line BL and the inverted bit line BLB determined in the previous period are written back to the memory cell .

[0118] With the above configuration, it is possible to write back a voltage according to the logic of data read by charge sharing to the memory cell 42 again without inverting the logic.

[0119] In one embodiment of the present invention, a transistor layer having a memory cell and a control circuit is configured to be able to read a signal in which the threshold voltage of a transistor for reading data is corrected. With this configuration, the reliability of data read from the memory cell to the first control circuit can be improved. In addition, in the semiconductor device according to one embodiment of the present invention, a plurality of switches are provided between a pair of global bit lines, so that data can be written back to the memory cell according to the logic of data read from the memory cell.

[0120] <Modifications of the semiconductor device>

[0121] 34A is a perspective view of the semiconductor device 10 in which the element layers 20_1 to 20_M illustrated in FIG. 1 are arranged on a silicon substrate 50. In addition to the vertical direction (z-axis direction), FIG. 34A shows the depth direction (x-axis direction) and the horizontal direction (y-axis direction).

[0122] In FIG. 34A, the memory cells 42 included in the transistor layers 41_1 and 41_2 are illustrated by dotted lines.

[0123] 34A, the semiconductor device 10 according to one embodiment of the present invention includes stacked transistor layers 30 and 40 each having an OS transistor. Therefore, the same manufacturing process can be repeatedly used in the vertical direction to manufacture the semiconductor device 10, which can reduce manufacturing costs. Furthermore, the semiconductor device 10 according to one embodiment of the present invention includes the transistor layer 40 each having a memory cell 42 stacked in the vertical direction instead of in the planar direction to improve memory density and reduce the size of the device.

[0124] 34B omits the configurations of the element layers 20_1 to 20_M shown in Fig. 34A and shows the circuits provided on the silicon substrate 50. Fig. 34B shows a control logic circuit 61, a row driving circuit 62, a column driving circuit 63 and an output circuit 64, which are configured of Si transistors on the silicon substrate 50. The control logic circuit 61, the row driving circuit 62, the column driving circuit 63 and the output circuit 64 will be described in detail in the fourth embodiment.

[0125] FIG. 35 corresponds to a diagram illustrating the transistor layers 30, 41_1, and 41_2 of the semiconductor device 10 illustrated in FIG. 34A. FIG. 35 illustrates the transistors 43 and capacitors 44 of the memory cells in the transistor layers 41_1 and 41_2, the local bit lines LBL, and the word lines WL. In FIG. 35, the local bit lines LBL are illustrated with dashed lines to improve visibility. In FIG. 35, the global bit lines GBL are illustrated, which are provided penetrating each transistor layer in the z-axis direction. As described above, the global bit lines GBL are illustrated with thicker lines than the other lines to improve visibility.

[0126] As shown in FIG. 35, in the semiconductor device 10, the local bit line LBL connected to the transistor 43 of the memory cell, the control circuit 35 of the transistor layer 30, and the global bit line GBL connected to the silicon substrate 50 are provided in the z-axis direction, that is, perpendicular to the silicon substrate 50. This configuration allows the local bit line LBL connected to each memory cell to be shortened. Therefore, the parasitic capacitance of the local bit line LBL can be significantly reduced, so that the potential can be read even if the data signal held in the memory cell is multi-valued. In addition, in one embodiment of the present invention, the data held in the memory cell can be read as a current, so that the data can be easily read even if the data signal is multi-valued.

[0127] 36A and 36B are circuit diagrams for explaining a modified example of the control circuit 35 shown in FIG. 2B. In FIG. 2B, each transistor is shown as a top-gate or bottom-gate transistor without a backgate electrode, but the structure of the transistor is not limited thereto. For example, as shown in FIG. 36A, a control circuit 35B having a backgate electrode connected to a backgate electrode line BGL may be used. The configuration of FIG. 36A makes it easier to externally control the electrical characteristics of each transistor, such as the threshold voltage.

[0128] Alternatively, as shown in Fig. 36B, a control circuit 35C having a back gate electrode connected to the gate electrode may be used. By using the configuration of Fig. 36B, the amount of current flowing through each transistor can be increased.

[0129] Although the semiconductor device 10 in Fig. 1 has been described as having one type of memory cell, it may have two or more types of memory cells. Fig. 37A shows a block diagram of a semiconductor device 10A which is a modified example of the semiconductor device 10.

[0130] The semiconductor device 10A differs from the semiconductor device 10 in that a transistor layer 90 having memory cells with a different circuit configuration is provided between the element layer 20 and the transistor layer 30.

[0131] 37B is a circuit diagram showing a configuration example of a memory cell 91 included in the transistor layer 90. The memory cell 91 includes a transistor 92, a transistor 93, and a capacitor 94.

[0132] One of the source and the drain of transistor 92 is connected to the gate of transistor 93. The gate of transistor 93 is connected to one electrode of capacitor 94. The other of the source and the drain of transistor 92 and the one of the source and the drain of transistor 92 are connected to wiring BL2. The other of the source and the drain of transistor 93 is connected to wiring SL2. The other electrode of capacitor 94 is electrically connected to wiring CAL. Here, a node to which the one of the source and the drain of transistor 92, the gate of transistor 93, and one electrode of capacitor 94 are connected is referred to as node N.

[0133] The wiring CAL functions as a wiring for applying a predetermined potential to the other electrode of the capacitor 94. The potential of the wiring CAL when data is read from the memory cell 91 is made different from the potential of the wiring CAL when data is written to the memory cell 91 and while data is being held in the memory cell 91. This makes it possible to make the apparent threshold voltage of the transistor 93 when data is read from the memory cell 91 different from the apparent threshold voltage of the transistor 93 when data is written to the memory cell 91 and while data is being held in the memory cell 91.

[0134] 37B, when data is written to the memory cell 91 and while data is being held in the memory cell 91, no current flows between the wiring SL2 and the wiring BL2, regardless of the data written to the memory cell 91. On the other hand, when data is read from the memory cell 91, a current corresponding to the data held in the memory cell 91 flows between the wiring SL2 and the wiring BL2.

[0135] The transistors 92 and 93 are preferably OS transistors. As described above, OS transistors have an extremely low off-state current. Therefore, charge corresponding to data written to the memory cell 91 can be held in the node N for a long time. That is, data once written in the memory cell 91 can be held for a long time. As a result, the frequency of data refresh can be reduced, and the power consumption of the semiconductor device of one embodiment of the present invention can be reduced.

[0136] The memory cell 91 shown in FIG. 37B can be called a nonvolatile oxide semiconductor RAM (NOSRAM) that uses OS transistors as memory. NOSRAM has the characteristic of being able to perform nondestructive readout. On the other hand, the above-mentioned DOSRAM is a destructive readout when reading the stored data.

[0137] The semiconductor device 10A includes the memory cell 91, which allows data that is frequently read to be transferred from the DOSRAM to the NOSRAM. As described above, the NOSRAM allows non-destructive reading, and therefore the frequency of data refresh can be reduced. Thus, the power consumption of the semiconductor device of one embodiment of the present invention can be reduced. Note that, although the transistors 92 and 93 illustrated in FIG. 37B are transistors each having one gate, the present invention is not limited thereto. For example, either or both of the transistors 92 and 93 may be transistors having two gates (transistors each having a front gate and a back gate facing the front gate).

[0138] 38A and 38B are schematic diagrams for explaining a modification of the semiconductor device 10 shown in FIG.

[0139] Fig. 38A shows a semiconductor device 10B in which a transistor layer 40 is disposed below a transistor layer 30 in element layers 20_1 to 20_M in the semiconductor device 10 shown in Fig. 1. The semiconductor device 10B shown in Fig. 38A has a transistor layer 49 having transistor layers 49_1 to 49_k below the transistor layer 30. Even in this configuration, an operation for correcting the threshold voltage of the readout transistor is possible.

[0140] Fig. 38B shows a semiconductor device 10C in which a transistor layer 49 described in Fig. 38A is added to the transistor layer 40 in the element layers 20_1 to 20_M in the semiconductor device 10 shown in Fig. 1. This configuration also allows the operation of correcting the threshold voltage of the readout transistor.

[0141] (Embodiment 2) An example of a semiconductor device that functions as a memory device according to one embodiment of the present invention will be described below.

[0142] FIG. 39 is a diagram showing an example of a semiconductor device in which memory units 470 (memory units 470_1 to 470_m: m is a natural number of 2 or more) are stacked on an element layer 411 having a circuit provided on a semiconductor substrate 311. FIG. 39 shows an example in which an element layer 411 and a plurality of memory units 470 are stacked on the element layer 411, and the plurality of memory units 470 are provided with corresponding transistor layers 413 (transistor layers 413_1 to 413_m) and a plurality of memory device layers 415 (memory device layers 415_1 to 415_n: n is a natural number of 2 or more) on each transistor layer 413. Note that, in each memory unit 470, an example in which the memory device layer 415 is provided on the transistor layer 413 is shown, but this is not limited to this in the present embodiment. The transistor layer 413 may be provided on the plurality of memory device layers 415, or the memory device layers 415 may be provided above and below the transistor layer 413.

[0143] The element layer 411 includes the transistor 300 provided over the semiconductor substrate 311 and can function as a circuit (sometimes referred to as a peripheral circuit) of the semiconductor device. Examples of the circuits include a column driver, a row driver, a column decoder, a row decoder, a sense amplifier, a precharge circuit, an amplifier circuit, a word line driver circuit, an output circuit, a control logic circuit, and the like.

[0144] The transistor layer 413 includes a transistor 200T, and can function as a circuit that controls each memory unit 470. The memory device layer 415 includes a memory device 420. The memory device 420 shown in this embodiment includes a transistor 200M and a capacitor 292.

[0145] The value of m is not particularly limited, but is 2 to 100, preferably 2 to 50, and more preferably 2 to 10. The value of n is not particularly limited, but is 2 to 100, preferably 2 to 50, and more preferably 2 to 10. The product of m and n is 4 to 256, preferably 4 to 128, and more preferably 4 to 64.

[0146] FIG. 39 is a cross-sectional view in the channel length direction of a transistor 200T and a transistor 200M included in the memory unit.

[0147] As shown in FIG. 39, a transistor 300 is provided on a semiconductor substrate 311, and a transistor layer 413 and a memory device layer 415 of a memory unit 470 are provided on the transistor 300. In one memory unit 470, a transistor 200T of the transistor layer 413 and a memory device 420 of the memory device layer 415 are electrically connected by a plurality of conductors 424, and the transistor 300 and the transistor 200T of the transistor layer 413 in each memory unit 470 are electrically connected by a conductor 426. In addition, the conductor 426 is preferably electrically connected to the transistor 200T via a conductor 428 that is electrically connected to any one of the source, drain, and gate of the transistor 200T. The conductor 424 is preferably provided in each layer of the memory device layer 415. In addition, the conductor 426 is preferably provided in each layer of the transistor layer 413 and the memory device layer 415.

[0148] As will be described in detail later, an insulator that suppresses the transmission of impurities such as water or hydrogen and oxygen is preferably provided on the side surfaces of the conductor 424 and the side surfaces of the conductor 426. As such an insulator, for example, silicon nitride, aluminum oxide, or silicon nitride oxide can be used.

[0149] The memory device 420 includes a transistor 200M and a capacitor 292, and the transistor 200M may have a structure similar to that of the transistor 200T included in the transistor layer 413. The transistors 200T and 200M may be collectively referred to as the transistor 200.

[0150] Here, in the transistor 200, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for a semiconductor including a region where a channel is formed (hereinafter also referred to as a channel formation region).

[0151] As the oxide semiconductor, for example, a metal oxide such as In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. Indium oxide, In-Ga oxide, or In-Zn oxide may also be used as the oxide semiconductor. Note that by using an oxide semiconductor with a composition having a high ratio of indium, the on-current or field effect mobility of a transistor can be increased.

[0152] The transistor 200 using an oxide semiconductor for a channel formation region has an extremely small leakage current in a non-conducting state, and therefore a semiconductor device with low power consumption can be provided. In addition, an oxide semiconductor can be formed by a sputtering method or the like and therefore can be used for the transistor 200 that constitutes a highly integrated semiconductor device. Note that the method for forming the oxide semiconductor is not limited to the above-mentioned sputtering method and may be, for example, an atomic layer deposition (ALD) method.

[0153] On the other hand, the electrical characteristics of a transistor using an oxide semiconductor tend to fluctuate due to impurities and oxygen vacancies in the oxide semiconductor, and the transistor tends to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode).

[0154] Therefore, it is preferable to use an oxide semiconductor having a low impurity concentration and a low density of defect states. Note that in this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly pure intrinsic oxide semiconductor or a substantially highly pure intrinsic oxide semiconductor.

[0155] Therefore, it is preferable to reduce the impurity concentration in the oxide semiconductor as much as possible. Examples of impurities in the oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0156] In particular, hydrogen, an impurity contained in oxide semiconductors, creates oxygen vacancies (V O In addition, defects in which hydrogen enters an oxygen vacancy (hereafter referred to as V O H.) may generate carrier electrons. In addition, some of the hydrogen may react with oxygen, which bonds with metal atoms, generating carrier electrons.

[0157] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. In addition, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field, and therefore, when an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.

[0158] Therefore, the oxide semiconductor used for the transistor 200 is preferably a high-purity intrinsic oxide semiconductor in which impurities such as hydrogen and oxygen vacancies are reduced.

[0159] <Sealing structure> Therefore, in order to prevent intrusion of impurities from the outside, the transistor 200 may be sealed with a material that prevents diffusion of impurities (hereinafter also referred to as a barrier material against impurities).

[0160] In this specification, the term "barrier property" refers to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability), or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0161] For example, materials having a function of suppressing the diffusion of hydrogen and oxygen include aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride oxide, etc. In particular, silicon nitride or silicon nitride oxide has a high barrier property against hydrogen, and is therefore preferably used as a sealing material.

[0162] Furthermore, for example, materials having the function of capturing and fixing hydrogen include metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide.

[0163] Between the transistor 300 and the transistor 200, the insulator 211, the insulator 212, and the insulator 214 are preferably provided as layers having a barrier property. By using a material that suppresses the diffusion or permeation of impurities such as hydrogen for at least one of the insulators 211, 212, and 214, it is possible to suppress the diffusion of impurities such as hydrogen and water contained in the semiconductor substrate 311, the transistor 300, and the like to the transistor 200. Furthermore, by using a material that suppresses the permeation of oxygen for at least one of the insulators 211, 212, and 214, it is possible to suppress the diffusion of oxygen contained in the channel of the transistor 200 or the transistor layer 413 to the element layer 411. For example, it is preferable to use a material that suppresses the permeation of impurities such as hydrogen and water for the insulators 211 and 212, and to use a material that suppresses the permeation of oxygen for the insulator 214. It is further preferable to use a material having a property of absorbing and occluding hydrogen for the insulator 214. For example, a nitride such as silicon nitride or silicon nitride oxide can be used as the insulator 211 and the insulator 212. For example, a metal oxide such as aluminum oxide, hafnium oxide, gallium oxide, or indium gallium zinc oxide can be used as the insulator 214. In particular, it is preferable to use aluminum oxide as the insulator 214.

[0164] Furthermore, an insulator 287 is preferably provided on the side surfaces of the transistor layer 413 and the memory device layer 415, i.e., the side surfaces of the memory unit 470, and an insulator 282 is preferably provided on the upper surface of the memory unit 470. In this case, the insulator 282 is preferably in contact with the insulator 287, and the insulator 287 is preferably in contact with at least one of the insulators 211, 212, and 214. For the insulators 287 and 282, a material that can be used for the insulator 214 is preferably used.

[0165] Also, it is preferable that the insulators 283 and 284 are provided so as to cover the insulators 282 and 287, and it is preferable that the insulator 283 contacts at least one of the insulators 211, 212, and 214. FIG. 39 shows an example in which the insulator 287 contacts the side of the insulator 214, the side of the insulator 212, and the upper surface and side of the insulator 211, and the insulator 283 contacts the side of the insulator 287 and the upper surface of the insulator 211, but this embodiment is not limited to this. The insulator 287 may contact the side of the insulator 214 and the upper surface and side of the insulator 212, and the insulator 283 may contact the side of the insulator 287 and the upper surface of the insulator 212. It is preferable to use a material that can be used for the insulators 211 and 212 as the insulators 282 and 287.

[0166] In the above structure, it is preferable to use a material that suppresses oxygen permeation for the insulator 287 and the insulator 282. It is more preferable to use a material that has the property of trapping and fixing hydrogen for the insulator 287 and the insulator 282. By using a material that has the function of trapping and fixing hydrogen on the side close to the transistor 200, hydrogen in the transistor 200 or in the memory unit 470 is trapped and fixed by the insulator 214, the insulator 287, and the insulator 282, so that the hydrogen concentration in the transistor 200 can be reduced. It is preferable to use a material that suppresses the permeation of impurities such as hydrogen and water for the insulator 283 and the insulator 284.

[0167] With the above-mentioned structure, the memory unit 470 is surrounded by the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284. More specifically, the memory unit 470 is surrounded by the insulator 214, the insulator 287, and the insulator 282 (sometimes referred to as a first structure), and the memory unit 470 and the first structure are surrounded by the insulator 211, the insulator 212, the insulator 283, and the insulator 284 (sometimes referred to as a second structure). In addition, such a structure in which the memory unit 470 is surrounded by a plurality of structures of two or more layers may be called a nested structure. Here, the memory unit 470 being surrounded by a plurality of structures may be described as the memory unit 470 being sealed by a plurality of insulators.

[0168] Moreover, the second structure seals the transistor 200 via the first structure. Therefore, the second structure prevents hydrogen present outside the second structure from diffusing into the inside of the second structure (the transistor 200 side). In other words, the first structure can efficiently capture and fix hydrogen present in the internal structure of the second structure.

[0169] Specifically, in the above structure, a metal oxide such as aluminum oxide can be used for the first structure, and a nitride such as silicon nitride can be used for the second structure. More specifically, an aluminum oxide film is preferably disposed between the transistor 200 and a silicon nitride film.

[0170] Furthermore, the hydrogen concentration in the film of the material used for the structure can be reduced by appropriately setting the film formation conditions.

[0171] Generally, a film formed by CVD has higher coverage than a film formed by sputtering. However, the compound gas used in CVD often contains hydrogen, and the film formed by CVD has a higher hydrogen content than the film formed by sputtering.

[0172] Therefore, for example, a film with a reduced hydrogen concentration (specifically, a film formed by sputtering) may be used as a film adjacent to the transistor 200. On the other hand, when a film with high coverage but a relatively high hydrogen concentration (specifically, a film formed by CVD) is used as a film for suppressing the diffusion of impurities, a film that has the function of capturing and fixing hydrogen and has a reduced hydrogen concentration may be disposed between the transistor 200 and the film with a relatively high hydrogen concentration but high coverage.

[0173] That is, a film having a relatively low hydrogen concentration may be used for a film disposed close to the transistor 200. On the other hand, a film having a relatively high hydrogen concentration may be disposed far from the transistor 200.

[0174] Specifically, in the above structure, when the transistor 200 is sealed with silicon nitride formed by a CVD method, an aluminum oxide film formed by a sputtering method may be disposed between the transistor 200 and the silicon nitride film formed by a CVD method. More preferably, a silicon nitride film formed by a sputtering method may be disposed between the silicon nitride film formed by a CVD method and the aluminum oxide film formed by a sputtering method.

[0175] In addition, when a film is formed by a CVD method, the hydrogen concentration in the formed film may be reduced by forming the film using a compound gas that does not contain hydrogen atoms or has a small amount of hydrogen atoms.

[0176] In addition, the insulator 282 and the insulator 214 are preferably provided between each transistor layer 413 and the memory device layer 415 or between each memory device layer 415. In addition, the insulator 296 is preferably provided between the insulator 282 and the insulator 214. The insulator 296 can be made of a material similar to that of the insulator 283 and the insulator 284. Alternatively, silicon oxide or silicon oxynitride can be used. Alternatively, a known insulating material may be used. Here, the insulator 282, the insulator 296, and the insulator 214 may be elements constituting the transistor 200. It is preferable that the insulator 282, the insulator 296, and the insulator 214 also serve as components of the transistor 200, because this can reduce the number of steps required for manufacturing a semiconductor device.

[0177] Furthermore, it is preferable that the side surfaces of the insulators 282, 296, and 214 provided between each transistor layer 413 and the memory device layer 415 or between each memory device layer 415 are in contact with the insulator 287. With such a structure, the transistor layer 413 and the memory device layer 415 are surrounded and sealed by the insulators 282, 296, 214, 287, 283, and 284, respectively.

[0178] An insulator 274 may be provided around the insulator 284. A conductor 430 may be provided so as to be embedded in the insulators 274, 284, 283, and 211. The conductor 430 is electrically connected to the transistor 300, that is, a circuit included in the element layer 411.

[0179] Furthermore, in the memory device layer 415, since the capacitor 292 is formed in the same layer as the transistor 200M, the height of the memory device 420 can be made approximately the same as that of the transistor 200M, and the height of each memory device layer 415 can be prevented from becoming excessively large. This makes it possible to increase the number of memory device layers 415 relatively easily. For example, the number of stacked layers made up of the transistor layer 413 and the memory device layer 415 may be approximately 100 layers.

[0180] <Transistor 200> A transistor 200 that can be used for the transistor 200T included in the transistor layer 413 and the transistor 200M included in the memory device 420 will be described with reference to FIG. 40A.

[0181] As shown in FIG. 40A, transistor 200 has insulator 216, conductor 205 (conductor 205a and conductor 205b), insulator 222, insulator 224, oxide 230 (oxide 230a, oxide 230b, and oxide 230c), conductor 242 (conductor 242a and conductor 242b), oxide 243 (oxide 243a and oxide 243b), insulator 272, insulator 273, insulator 250, and conductor 260 (conductor 260a and conductor 260b).

[0182] Furthermore, the insulator 216 and the conductor 205 are provided over the insulator 214, and the insulator 280 and the insulator 282 are provided over the insulator 273. The insulator 214, the insulator 280, and the insulator 282 can be considered to constitute part of the transistor 200.

[0183] The semiconductor device of one embodiment of the present invention also includes a conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the transistor 200 and functions as a plug. Note that an insulator 241 (insulator 241a and insulator 241b) may be provided in contact with a side surface of the conductor 240 that functions as a plug. A conductor 246 (conductor 246a and conductor 246b) that is electrically connected to the conductor 240 and functions as a wiring is provided over the insulator 282 and the conductor 240.

[0184] The conductor 240a and the conductor 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240a and the conductor 240b may have a layered structure.

[0185] In addition, when the conductor 240 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. In addition, the conductive material having a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen may be used in a single layer or a laminate. By using the conductive material, it is possible to further reduce impurities such as water or hydrogen that diffuse from the insulator 280, etc., from being mixed into the oxide 230 through the conductor 240a and the conductor 240b. In addition, it is possible to prevent the oxygen added to the insulator 280 from being absorbed by the conductor 240a and the conductor 240b.

[0186] The insulator 241 provided in contact with the side surface of the conductor 240 may be made of, for example, silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 241 is provided in contact with the insulators 272, 273, 280, and 282, and therefore can prevent impurities such as water or hydrogen from the insulator 280 and the like from being mixed into the oxide 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0187] The conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0188] In the transistor 200, the conductor 260 functions as a first gate of the transistor, and the conductor 205 functions as a second gate of the transistor. In addition, the conductor 242a and the conductor 242b function as a source electrode and a drain electrode.

[0189] The oxide 230 functions as a semiconductor having a channel formation region.

[0190] Insulator 250 serves as a first gate insulator, and insulators 222 and 224 serve as second gate insulators.

[0191] Here, in the transistor 200 shown in FIG. 40A, the conductor 260 is formed in a self-aligned manner via the oxide 230c and the insulator 250 within openings provided in the insulator 280, the insulator 273, the insulator 272, the conductor 242, etc.

[0192] In other words, since the conductor 260 is formed to fill the openings provided in the insulator 280, etc., via the oxide 230c and the insulator 250, there is no need to align the conductor 260 in the region between the conductor 242a and the conductor 242b.

[0193] Here, it is preferable to provide the oxide 230c in an opening provided in the insulator 280 or the like. Therefore, the insulator 250 and the conductor 260 have a region overlapping with the stacked structure of the oxide 230b and the oxide 230a via the oxide 230c. This structure makes it possible to form the oxide 230c and the insulator 250 by successive film formation, so that the interface between the oxide 230 and the insulator 250 can be kept clean. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain high on-current and high frequency characteristics.

[0194] 40A, the bottom surface and side surfaces of the conductor 260 are in contact with the insulator 250. The bottom surface and side surfaces of the insulator 250 are in contact with the oxide 230c.

[0195] 40A, the transistor 200 has a structure in which the insulator 282 and the oxide 230c are in direct contact with each other. With this structure, diffusion of oxygen contained in the insulator 280 to the conductor 260 can be suppressed.

[0196] Therefore, the oxygen contained in insulator 280 can be efficiently supplied to oxide 230a and oxide 230b via oxide 230c, thereby reducing oxygen vacancies in oxide 230a and oxide 230b and improving the electrical characteristics and reliability of transistor 200.

[0197] A detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described below.

[0198] In the transistor 200, a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including the channel formation region.

[0199] For example, a metal oxide that functions as an oxide semiconductor has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large energy gap, the leakage current (off-state current) of the transistor 200 in a non-conducting state can be made extremely small. By using such a transistor, a semiconductor device with low power consumption can be provided.

[0200] Specifically, it is preferable to use a metal oxide such as In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) as the oxide 230. In particular, it is preferable to use aluminum, gallium, yttrium, or tin as the element M. Also, it is possible to use In-M oxide, In-Zn oxide, or M-Zn oxide as the oxide 230.

[0201] 40A, the oxide 230 preferably includes an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and an oxide 230c disposed on the oxide 230b and at least a portion of which is in contact with the upper surface of the oxide 230b. Here, the side surface of the oxide 230c is preferably in contact with the oxide 243a, the oxide 243b, the conductor 242a, the conductor 242b, the insulator 272, the insulator 273, and the insulator 280.

[0202] That is, the oxide 230 has an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. By having the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b. Also, by having the oxide 230c on the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed above the oxide 230c to the oxide 230b.

[0203] In the transistor 200, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c is shown in the channel formation region and its vicinity, but the present invention is not limited to this. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be provided. For example, the oxide 230c may be a two-layer structure, and a stacked structure of four layers may be provided.

[0204] In addition, the oxide 230 preferably has a laminated structure of a plurality of oxides with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of element M among the constituent elements is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230a, the atomic ratio of element M to In is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230b, the atomic ratio of In to element M is preferably larger than the atomic ratio of In to element M in the metal oxide used for the oxide 230a. In addition, the oxide 230c can use a metal oxide that can be used for the oxide 230a or the oxide 230b.

[0205] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or a composition close thereto, or an atomic ratio of 1:1:0.5 or a composition close thereto.

[0206] Also, the oxide 230b may be a metal oxide having a composition of In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, or a composition of 1:1:1 [atomic ratio] or a composition close thereto. Also, the oxide 230b may be a metal oxide having a composition of In:Ga:Zn=5:1:3 [atomic ratio] or a composition close thereto, or a composition of In:Ga:Zn=10:1:3 [atomic ratio] or a composition close thereto. Also, the oxide 230b may be an In-Zn oxide (for example, a composition of In:Zn=2:1 [atomic ratio] or a composition close thereto, a composition of In:Zn=5:1 [atomic ratio] or a composition close thereto, or a composition of In:Zn=10:1 [atomic ratio] or a composition close thereto). Also, the oxide 230b may be an In oxide.

[0207] The oxide 230c may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or a composition close thereto, an atomic ratio of Ga:Zn=2:1 or a composition close thereto, or an atomic ratio of Ga:Zn=2:5 or a composition close thereto. The oxide 230c may be a single layer or a multilayer structure formed by applying a material that can be used for the oxide 230b. For example, specific examples of the oxide 230c having a layered structure include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto and In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto, a layered structure of Ga:Zn=2:1 [atomic ratio] or a composition close thereto and In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, a layered structure of Ga:Zn=2:5 [atomic ratio] or a composition close thereto and In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, and a layered structure of gallium oxide and In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto.

[0208] Note that the configuration of the OS transistor included in the memory cell 42 shown in the first embodiment may be different from the configuration of the OS transistor included in the transistor layer 30. For example, the oxide 230c included in the OS transistor provided in the memory cell 42 may be a metal oxide having a composition of In:Ga:Zn=4:2:3 [atomic ratio] or a composition thereabout, and the oxide 230c included in the OS transistor provided in the transistor layer 30 may be a metal oxide having a composition of In:Ga:Zn=5:1:3 [atomic ratio] or a composition thereabout, In:Ga:Zn=10:1:3 [atomic ratio] or a composition thereabout, In:Zn=10:1 [atomic ratio] or a composition thereabout, In:Zn=5:1 [atomic ratio] or a composition thereabout, or In:Zn=2:1 [atomic ratio] or a composition thereabout.

[0209] In addition, by increasing the ratio of indium in the oxide 230b and the oxide 230c, the on-current or the field effect mobility of the transistor can be increased, which is preferable. In addition, the above-mentioned vicinity composition includes a range of ±30% of the desired atomic ratio.

[0210] The oxide 230b may have crystallinity. For example, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) described later. Crystalline oxides such as CAAC-OS have few impurities and defects (oxygen vacancies, etc.), and have a dense structure with high crystallinity. This can suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. Even if a heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0211] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably embedded in the insulator 216.

[0212] When the conductor 205 functions as a gate electrode, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be increased and the off-current can be reduced. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to not applying a negative potential.

[0213] As shown in FIG. 40A, the conductor 205 is preferably larger than the size of a region of the oxide 230 that does not overlap with the conductor 242a and the conductor 242b. Although not shown here, the conductor 205 preferably extends to a region outside the oxide 230a and the oxide 230b in the channel width direction of the oxide 230. In other words, outside the side surface of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other through an insulator. By providing the conductor 205 to a large size, local charging (referred to as charge-up) may be alleviated in a process using plasma in a manufacturing process after the formation of the conductor 205. However, one embodiment of the present invention is not limited thereto. The conductor 205 may overlap with at least the oxide 230 located between the conductor 242a and the conductor 242b.

[0214] Furthermore, it is preferable that, with respect to the bottom surface of insulator 224, the height of the bottom surface of conductor 260 in the area where oxide 230a and oxide 230b do not overlap with conductor 260 is positioned at a lower position than the height of the bottom surface of oxide 230b.

[0215] Although not shown, in the channel width direction, the conductor 260 functioning as a gate has a structure that covers the side and top surfaces of the oxide 230b in the channel formation region via the oxide 230c and the insulator 250, which makes it easier for the electric field generated from the conductor 260 to act on the entire channel formation region generated in the oxide 230b. This makes it possible to increase the on-current of the transistor 200 and improve the frequency characteristics. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the conductor 260 and the conductor 205 is called a surrounded channel (S-channel) structure.

[0216] The conductor 205a is preferably a conductor that suppresses the permeation of impurities such as water or hydrogen, and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. The conductor 205b is preferably a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 205 is illustrated as having two layers, it may have a multi-layer structure of three or more layers.

[0217] Here, it is preferable to successively form different types of films, that is, an oxide semiconductor, an insulator or conductor located under the oxide semiconductor, and an insulator or conductor located over the oxide semiconductor, without exposure to the air, because this makes it possible to form a substantially high-purity intrinsic oxide semiconductor film in which the concentration of impurities (particularly, hydrogen and water) is reduced.

[0218] At least one of the insulator 222, the insulator 272, and the insulator 273 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side or from above. Therefore, at least one of the insulator 222, the insulator 272, and the insulator 273 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side or from above. 2 O, NO, NO 2 It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (the impurities are unlikely to permeate through the insulating material), or that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is unlikely to permeate through the insulating material).

[0219] For example, it is preferable to use silicon nitride or silicon nitride oxide as insulator 273, and to use aluminum oxide or hafnium oxide as insulator 222 and insulator 272.

[0220] This can suppress impurities such as water or hydrogen from diffusing to the transistor 200 side through the insulator 222. Alternatively, it can suppress oxygen contained in the insulator 224 or the like from diffusing to the substrate side through the insulator 222.

[0221] Furthermore, it is possible to suppress diffusion of impurities such as water or hydrogen from the insulator 280 disposed between the insulators 272 and 273 to the transistor 200. In this manner, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 272 and 273, which have a function of suppressing diffusion of impurities such as water or hydrogen, and oxygen.

[0222] Here, the insulator 224 in contact with the oxide 230 preferably releases oxygen by heating. In this specification, oxygen released by heating is sometimes referred to as excess oxygen. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

[0223] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as the insulator 224. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 More than 1.0×10 19 molecules / cm 3 More preferably, 2.0×10 19 molecules / cm 3 or more than 3.0×10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.

[0224] The insulator 222 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224 and the oxide 230 with the insulator 222 and the insulator 283, impurities such as water or hydrogen can be prevented from entering the transistor 200 from the outside.

[0225] Furthermore, it is preferable that the insulator 222 has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). For example, it is preferable that the insulator 222 has lower oxygen permeability than the insulator 224. This is because the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, which can reduce the diffusion of oxygen contained in the oxide 230 below the insulator 222. Furthermore, it is possible to suppress the conductor 205 from reacting with the insulator 224 or the oxygen contained in the oxide 230.

[0226] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 and the intrusion of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230.

[0227] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0228] The insulator 222 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba,Sr)TiO 3 An insulator containing a so-called high-k material such as (BST) may be used in a single layer or a stacked layer. For example, when the insulator 222 is a stacked layer, a three-layer stack in which zirconium oxide, aluminum oxide, and zirconium oxide are formed in this order may be used, or a four-layer stack in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are formed in this order may be used. In addition, a compound containing hafnium and zirconium may be used as the insulator 222. As semiconductor devices become finer and more highly integrated, problems such as leakage currents in transistors and capacitors may occur due to the thinning of the gate insulator and the dielectric used in the capacitor. By using a high-k material for the insulator that functions as the gate insulator and the dielectric used in the capacitor, it is possible to reduce the gate potential during transistor operation and ensure the capacitance of the capacitor while maintaining the physical film thickness.

[0229] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, and may be made of different materials.

[0230] Furthermore, the oxide 243 (oxide 243a and oxide 243b) may be disposed between the oxide 230b and the conductor 242 (conductor 242a and conductor 242b) functioning as a source electrode or a drain electrode. Since the conductor 242 and the oxide 230b are not in contact with each other, it is possible to prevent the conductor 242 from absorbing oxygen from the oxide 230b. In other words, by preventing the oxidation of the conductor 242, it is possible to prevent a decrease in the conductivity of the conductor 242. Therefore, it is preferable that the oxide 243 has a function of suppressing the oxidation of the conductor 242.

[0231] By disposing the oxide 243 having a function of suppressing oxygen permeation between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b can be reduced, which is preferable. With such a structure, the electrical characteristics and reliability of the transistor 200 can be improved.

[0232] The oxide 243 may be a metal oxide having an element M consisting of one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. In particular, the element M may be aluminum, gallium, yttrium, or tin. The oxide 243 preferably has a higher concentration of element M than the oxide 230b. Gallium oxide may be used as the oxide 243. A metal oxide such as an In-M-Zn oxide may be used as the oxide 243. Specifically, in the metal oxide used for the oxide 243, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. The thickness of the oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less. Moreover, it is preferable that the oxide 243 has crystallinity. When the oxide 243 has crystallinity, it is possible to suitably suppress the release of oxygen from the oxide 230. For example, when the oxide 243 has a crystal structure such as a hexagonal crystal structure, it may be possible to suppress the release of oxygen from the oxide 230.

[0233] Incidentally, the oxide 243 does not necessarily have to be provided. In that case, when the conductor 242 (conductor 242a and conductor 242b) comes into contact with the oxide 230, oxygen in the oxide 230 may diffuse into the conductor 242, and the conductor 242 may be oxidized. When the conductor 242 is oxidized, the conductivity of the conductor 242 is more likely to decrease. The diffusion of oxygen in the oxide 230 into the conductor 242 can be rephrased as the conductor 242 absorbing the oxygen in the oxide 230.

[0234] Furthermore, oxygen in the oxide 230 may diffuse into the conductor 242 (conductor 242a and conductor 242b), forming a foreign layer between the conductor 242a and the oxide 230b and between the conductor 242b and the oxide 230b. Since the foreign layer contains more oxygen than the conductor 242, the foreign layer is presumed to have insulating properties. In this case, the three-layer structure of the conductor 242, the foreign layer, and the oxide 230b can be regarded as a three-layer structure made of a metal-insulator-semiconductor, and may be called a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly based on the MIS structure.

[0235] In addition, the above-mentioned different layer is not limited to being formed between the conductor 242 and the oxide 230b. For example, the different layer may be formed between the conductor 242 and the oxide 230c, between the conductor 242 and the oxide 230b, and between the conductor 242 and the oxide 230c.

[0236] A conductor 242 (conductor 242a and conductor 242b) functioning as a source electrode and a drain electrode is provided over the oxide 243. The thickness of the conductor 242 is, for example, 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0237] As the conductor 242, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed.

[0238] The insulator 272 is preferably provided in contact with the top surface of the conductor 242 and functions as a barrier layer. This structure can suppress the absorption of excess oxygen contained in the insulator 280 by the conductor 242. Furthermore, suppressing oxidation of the conductor 242 can suppress an increase in contact resistance between the transistor 200 and the wiring. Thus, the transistor 200 can have favorable electrical characteristics and reliability.

[0239] Therefore, the insulator 272 preferably has a function of suppressing the diffusion of oxygen. For example, the insulator 272 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280. As the insulator 272, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. As the insulator 272, for example, an insulator containing aluminum nitride may be used.

[0240] The insulator 272 contacts a part of the upper surface of the conductor 242b and the side surface of the conductor 242b. Although not shown, the insulator 272 contacts a part of the upper surface of the conductor 242a and the side surface of the conductor 242a. Insulator 273 is disposed on the insulator 272. In this manner, for example, oxygen added to the insulator 280 can be prevented from being absorbed by the conductor 242.

[0241] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230c. The insulator 250 can be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0242] Like the insulator 224, the insulator 250 is preferably formed using an insulator that releases oxygen when heated. By providing an insulator that releases oxygen when heated as the insulator 250 in contact with the top surface of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b. Also, like the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 be reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0243] A metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Also, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0244] Moreover, the metal oxide may function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material having a high relative dielectric constant. By forming the gate insulator into a laminated structure of the insulator 250 and the metal oxide, it is possible to obtain a laminated structure that is stable against heat and has a high relative dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Also, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0245] Specifically, it is possible to use a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0246] Alternatively, the metal oxide may function as a part of the gate. In this case, a conductive material containing oxygen may be provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0247] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate. The conductive material containing the metal element and nitrogen described above may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Or, hydrogen mixed in from an external insulator may be captured.

[0248] Although conductor 260 is shown as having a two-layer structure in FIG. 40A, it may have a single-layer structure or a laminated structure of three or more layers.

[0249] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N 2 O, NO, NO 2 It is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as copper atoms, etc., or oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0250] Furthermore, since the conductor 260a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0251] Moreover, it is preferable that the conductor 260b is made of a conductive material mainly composed of tungsten, copper, or aluminum. Since the conductor 260 also functions as wiring, it is preferable that a conductor having high conductivity is used. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material.

[0252] <<Metal oxides>> It is preferable to use a metal oxide that functions as an oxide semiconductor as the oxide 230. Hereinafter, metal oxides that can be used as the oxide 230 according to the present invention will be described.

[0253] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.

[0254] Here, the case is considered where the metal oxide is an In-M-Zn oxide having indium, an element M, and zinc (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.). In particular, it is preferable to use aluminum, gallium, yttrium, or tin as the element M.

[0255] In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0256] <Transistor 300> The transistor 300 will be described with reference to Fig. 40B. The transistor 300 is provided on a semiconductor substrate 311, and has a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of a part of the semiconductor substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel type or an n-channel type.

[0257] Here, in the transistor 300 shown in FIG. 40B, the semiconductor region 313 (part of the semiconductor substrate 311) in which the channel is formed has a convex shape. Although not shown, the side and upper surface of the semiconductor region 313 are covered with a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN type transistor because it uses the convex portion of the semiconductor substrate 311. An insulator that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate 311 has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0258] Note that the transistor 300 illustrated in FIG. 40B is just an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration and driving method.

[0259] <Memory Device 420> Next, the memory device 420 shown in Fig. 39 will be described with reference to Fig. 41A. Note that, for the transistor 200M included in the memory device 420, a description that overlaps with that of the transistor 200 will be omitted.

[0260] In the memory device 420, the conductor 242a of the transistor 200M functions as one of the electrodes of the capacitance 292, and the insulator 272 and the insulator 273 function as dielectrics. The conductor 290 is provided to overlap the conductor 242a with the insulator 272 and the insulator 273 sandwiched therebetween, and functions as the other electrode of the capacitance 292. The conductor 290 may be used as the other electrode of the capacitance 292 of the adjacent memory device 420. Alternatively, the conductor 290 may be electrically connected to the conductor 290 of the adjacent memory device 420.

[0261] Conductor 290 is disposed not only on the top surface of conductor 242a but also on the side surface of conductor 242a, with insulators 272 and 273 sandwiched therebetween. In this case, capacitance 292 can be obtained that is larger than the capacitance obtained by the area where conductor 242a and conductor 290 overlap, which is preferable.

[0262] The conductor 424 is electrically connected to the conductor 242b, and is also electrically connected via the conductor 205 to the conductor 424 located in the lower layer.

[0263] As the dielectric of the capacitor 292, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, etc. can be used. Moreover, these materials can be stacked. When the dielectric of the capacitor 292 has a stacked structure, a stack of aluminum oxide and silicon nitride, or a stack of hafnium oxide and silicon oxide can be used. Here, the top and bottom of the stack is not limited. For example, silicon nitride may be stacked on aluminum oxide, or aluminum oxide may be stacked on silicon nitride.

[0264] Alternatively, zirconium oxide, which has a higher dielectric constant than the above materials, may be used as the dielectric of the capacitor 292. Zirconium oxide may be used as a single layer or as part of a laminated layer for the dielectric of the capacitor 292. For example, a laminated layer of zirconium oxide and aluminum oxide may be used. Alternatively, the dielectric of the capacitor 292 may be a three-layered laminate, with zirconium oxide used for the first and third layers and aluminum oxide used for the second layer between the first and third layers.

[0265] By using zirconium oxide having a high dielectric constant as the dielectric of the capacitor 292, it is possible to reduce the area that the capacitor 292 occupies in the memory device 420. Therefore, it is possible to reduce the area required for the memory device 420 and improve the bit cost, which is preferable.

[0266] Furthermore, the conductor 290 can be made of a material that can be used for the conductor 205, the conductor 242, the conductor 260, the conductor 424, etc.

[0267] In this embodiment, an example is shown in which the transistor 200M and the capacitor 292 are arranged symmetrically with the conductor 424 sandwiched therebetween. By arranging a pair of the transistor 200M and the capacitor 292 in this manner, the number of conductors 424 electrically connected to the transistor 200M can be reduced. Therefore, the area required for the memory device 420 can be reduced, and the bit cost can be improved, which is preferable.

[0268] When the insulator 241 is provided on the side surface of the conductor 424, the conductor 424 is connected to at least a portion of the upper surface of the conductor 242b.

[0269] The conductor 424 and the conductor 205 can be used to electrically connect the transistor 200T and the memory device 420 in the memory unit 470.

[0270] <Modification 1 of memory device 420> Next, a memory device 420A will be described with reference to Figure 41B as a modification of the memory device 420. The memory device 420A has a capacitor 292A electrically connected to the transistor 200M, in addition to the transistor 200M described with reference to Figure 41A. The capacitor 292A is provided below the transistor 200M.

[0271] In memory device 420A, conductor 242a is disposed in an opening in oxide 243a, oxide 230b, oxide 230a, insulator 224, and insulator 222, and electrically connects to conductor 205 at the bottom of the opening. Conductor 205 electrically connects to capacitor 292A.

[0272] The capacitor 292A has a conductor 294 that functions as one of the electrodes, an insulator 295 that functions as a dielectric, and a conductor 297 that functions as the other of the electrodes. The conductor 297 overlaps with the conductor 294 with the insulator 295 sandwiched therebetween. The conductor 297 is also electrically connected to the conductor 205.

[0273] The conductor 294 is provided on the bottom and side of an opening formed in an insulator 298 provided on the insulator 296, and the insulator 295 is provided so as to cover the insulator 298 and the conductor 294. The conductor 297 is provided so as to be embedded in a recessed portion of the insulator 295.

[0274] Furthermore, a conductor 299 is provided so as to be embedded in the insulator 296, and the conductor 299 is electrically connected to the conductor 294. The conductor 299 may be electrically connected to the conductor 294 of the adjacent memory device 420A.

[0275] Conductor 297 is disposed on the side surface of conductor 294 as well as on the top surface of conductor 294 with insulator 295 sandwiched therebetween. In this case, capacitance 292A is preferable because a capacitance larger than the capacitance obtained by the overlapping area of ​​conductor 294 and conductor 297 can be obtained.

[0276] Silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, and the like can be used as the insulator 295 functioning as the dielectric of the capacitor 292A. Moreover, these materials can be stacked. When the insulator 295 has a stacked structure, a stack of aluminum oxide and silicon nitride, or a stack of hafnium oxide and silicon oxide can be used. Here, the top and bottom of the stack is not limited. For example, silicon nitride may be stacked on aluminum oxide, or aluminum oxide may be stacked on silicon nitride.

[0277] Alternatively, zirconium oxide, which has a higher dielectric constant than the above materials, may be used as the insulator 295. Zirconium oxide may be used as a single layer or as part of a stack. For example, a stack of zirconium oxide and aluminum oxide may be used. Alternatively, the insulator 295 may be a three-layer stack, with zirconium oxide used for the first and third layers and aluminum oxide used for the second layer between the first and third layers.

[0278] By using zirconium oxide having a high dielectric constant as the insulator 295, it is possible to reduce the area that the capacitor 292A occupies in the memory device 420A. Therefore, it is possible to reduce the area required for the memory device 420A, and it is preferable because the bit cost can be improved.

[0279] Furthermore, materials that can be used for the conductor 205, the conductor 242, the conductor 260, the conductor 424, etc. can be used for the conductor 297, the conductor 294, and the conductor 299.

[0280] Furthermore, the materials that can be used for insulator 214, insulator 216, insulator 224, insulator 280, etc. can be used as insulator 298.

[0281] <Modification 2 of memory device 420> Next, a memory device 420B will be described with reference to Figure 41C as a modification of the memory device 420. The memory device 420B has a capacitor 292B electrically connected to the transistor 200M, in addition to the transistor 200M described with reference to Figure 41A. The capacitor 292B is provided above the transistor 200M.

[0282] The capacitor 292B has a conductor 276 that functions as one of the electrodes, an insulator 277 that functions as a dielectric, and a conductor 278 that functions as the other of the electrodes. The conductor 278 overlaps with the conductor 276 with the insulator 277 sandwiched therebetween.

[0283] The insulator 275 is provided on the insulator 282, and the conductor 276 is provided on the bottom and side of the opening formed in the insulator 275, the insulator 282, the insulator 280, the insulator 273, and the insulator 272. The insulator 277 is provided so as to cover the insulator 282 and the conductor 276. The conductor 278 is provided so as to overlap the conductor 276 in the recess of the insulator 277, and at least a part of the conductor 278 is provided on the insulator 275 via the insulator 277. The conductor 278 may be used as the other electrode of the capacitance 292B of the adjacent memory device 420B. Alternatively, the conductor 278 may be electrically connected to the conductor 278 of the adjacent memory device 420B.

[0284] Conductor 278 is disposed on the side surface of conductor 276 as well as on the top surface of conductor 276 with insulator 277 sandwiched therebetween. In this case, capacitance 292B is preferable because a capacitance larger than the capacitance obtained by the overlapping area of ​​conductor 276 and conductor 278 can be obtained.

[0285] In addition, an insulator 279 may be provided so as to fill the recess of the conductor 278 .

[0286] Silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, and the like can be used as the insulator 277 functioning as the dielectric of the capacitor 292B. Moreover, these materials can be stacked. When the insulator 277 has a stacked structure, a stack of aluminum oxide and silicon nitride, or a stack of hafnium oxide and silicon oxide can be used. Here, the top and bottom of the stack is not limited. For example, silicon nitride may be stacked on aluminum oxide, or aluminum oxide may be stacked on silicon nitride.

[0287] Alternatively, zirconium oxide, which has a higher dielectric constant than the above materials, may be used as the insulator 277. Zirconium oxide may be used as a single layer or as part of a stack. For example, a stack of zirconium oxide and aluminum oxide may be used. Alternatively, the insulator 277 may be a three-layer stack, with zirconium oxide used for the first and third layers and aluminum oxide used for the second layer between the first and third layers.

[0288] The area that the capacitor 292B occupies in the memory device 420B can be reduced by using zirconium oxide having a high dielectric constant as the insulator 277. Therefore, the area required for the memory device 420B can be reduced, and the bit cost can be improved, which is preferable.

[0289] Furthermore, materials that can be used for the conductor 205, the conductor 242, the conductor 260, the conductor 424, etc. can be used for the conductor 276 and the conductor 278.

[0290] Furthermore, materials that can be used for insulators 214, 216, 224, and 280 can be used for insulators 275 and 279.

[0291] <Connection between memory device 420 and transistor 200T> In FIG. 39, in a region 422 surrounded by a dashed line, the memory device 420 is electrically connected to the gate of the transistor 200T via a conductor 424 and a conductor 205, but the present embodiment is not limited to this.

[0292] FIG. 42 shows an example in which memory device 420 is electrically connected to conductor 424, conductor 205, conductor 246b, and conductor 240b via conductor 242b, which functions as one of the source and drain of transistor 200T.

[0293] In this way, the method of connecting the memory device 420 and the transistor 200T can be determined depending on the circuit function of the transistor layer 413.

[0294] FIG. 43 shows an example in which a memory unit 470 includes a transistor layer 413 including a transistor 200T and four memory device layers 415 (memory device layers 415_1 to 415_4).

[0295] Each of the memory device layers 415_1 to 415_4 includes a plurality of memory devices 420.

[0296] The memory device 420 is electrically connected to a memory device 420 in a different memory device layer 415 and a transistor 200T in a transistor layer 413 via a conductor 424 and a conductor 205.

[0297] The memory unit 470 is sealed by the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284. The insulator 274 is provided around the insulator 284. Further, the conductor 430 is provided on the insulator 274, the insulator 284, the insulator 283, and the insulator 211 and is electrically connected to the element layer 411.

[0298] Further, an insulator 280 is provided inside the sealing structure. The insulator 280 has a function of releasing oxygen when heated. Alternatively, the insulator 280 has an excess oxygen region.

[0299] Note that the insulators 211, 283, and 284 are preferably made of a material having a high blocking property against hydrogen, and the insulators 214, 282, and 287 are preferably made of a material having a function of capturing or fixing hydrogen.

[0300] For example, the material having a high blocking property against hydrogen includes silicon nitride, silicon oxynitride, etc. Furthermore, the material having a function of capturing or fixing hydrogen includes aluminum oxide, hafnium oxide, and oxide containing aluminum and hafnium (hafnium aluminate), etc.

[0301] In this specification, the term "barrier property" refers to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability), or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0302] Note that the crystal structure of the materials used for the insulators 211, 212, 214, 287, 282, 283, and 284 is not particularly limited, and may be an amorphous or crystalline structure. For example, an amorphous aluminum oxide film is preferably used as a material having a function of capturing or fixing hydrogen. Amorphous aluminum oxide may be capable of capturing and fixing a larger amount of hydrogen than aluminum oxide with high crystallinity.

[0303] Here, the following model can be considered for the diffusion of excess oxygen in the insulator 280 and hydrogen in the oxide semiconductor in contact with the insulator 280.

[0304] Hydrogen present in the oxide semiconductor diffuses to other structures through the insulator 280 in contact with the oxide semiconductor. In the diffusion of hydrogen, excess oxygen in the insulator 280 reacts with hydrogen in the oxide semiconductor to form an OH bond, and the hydrogen diffuses through the insulator 280. When the hydrogen atom having the OH bond reaches a material (typically the insulator 282) having a function of capturing or fixing hydrogen, the hydrogen atom reacts with an oxygen atom bonded to an atom (e.g., a metal atom, etc.) in the insulator 282, and is captured or fixed in the insulator 282. On the other hand, it is presumed that the oxygen atom of the excess oxygen having the OH bond remains in the insulator 280 as excess oxygen. In other words, there is a high probability that the excess oxygen in the insulator 280 plays a bridging role in the diffusion of hydrogen.

[0305] In order to satisfy the above model, the manufacturing process of the semiconductor device is one of the important factors.

[0306] As an example, the insulator 280 containing excess oxygen is formed in an oxide semiconductor, and then the insulator 282 is formed. After that, heat treatment is preferably performed. Specifically, the heat treatment is performed in an atmosphere containing oxygen, an atmosphere containing nitrogen, or an atmosphere containing a mixture of oxygen and nitrogen at a temperature of 350° C. or higher, preferably 400° C. or higher. The heat treatment time is 1 hour or longer, preferably 4 hours or longer, and more preferably 8 hours or longer.

[0307] By the above heat treatment, hydrogen in the oxide semiconductor can diffuse outward through the insulator 280, the insulator 282, and the insulator 287. That is, the absolute amount of hydrogen present in the oxide semiconductor and in the vicinity of the oxide semiconductor can be reduced.

[0308] After the heat treatment, the insulators 283 and 284 are formed. The insulators 283 and 284 are made of materials having a high blocking property against hydrogen, and therefore can prevent hydrogen that has diffused to the outside or hydrogen present on the outside from entering the inside, specifically, the oxide semiconductor or the insulator 280 side.

[0309] Note that the above heat treatment is performed after the insulator 282 is formed, but is not limited thereto. For example, the heat treatment may be performed after the transistor layer 413 is formed or after the memory device layers 415_1 to 415_3 are formed. When hydrogen is diffused outward by the heat treatment, hydrogen is diffused upward or laterally of the transistor layer 413. Similarly, when the heat treatment is performed after the memory device layers 415_1 to 415_3 are formed, hydrogen is diffused upward or laterally.

[0310] By using the above manufacturing process, the insulator 211 and the insulator 283 are bonded to each other, thereby forming the above-described sealing structure.

[0311] As described above, by using the above structure and manufacturing process, a semiconductor device including an oxide semiconductor in which the hydrogen concentration is reduced can be provided. Therefore, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided.

[0312] 44A to 44C are diagrams showing different examples of the arrangement of the conductor 424. FIG. 44A shows a layout diagram of the memory device 420 seen from above, FIG. 44B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 44A, and FIG. 44C is a cross-sectional view of the portion indicated by the dashed line B1-B2 in FIG. 44A. Note that in FIG. 44A, the conductor 205 is omitted from illustration in order to facilitate understanding of the figure. When the conductor 205 is provided, the conductor 205 has an area overlapping with the conductor 260 and the conductor 424.

[0313] As shown in Fig. 44A, the opening in which the conductor 424 is provided, i.e., the conductor 424, is provided not only in the region overlapping with the oxide 230a and the oxide 230b, but also outside the oxide 230a and the oxide 230b. Fig. 44A shows an example in which the conductor 424 is provided so as to protrude on the B2 side of the oxide 230a and the oxide 230b, but the present embodiment is not limited to this. The conductor 424 may be provided so as to protrude on the B1 side of the oxide 230a and the oxide 230b, or may be provided so as to protrude on both the B1 side and the B2 side.

[0314] 44B and 44C show an example in which a memory device layer 415_p is stacked on a memory device layer 415_p-1 (p is a natural number between 2 and n). The memory device 420 in the memory device layer 415_p-1 is electrically connected to the memory device 420 in the memory device layer 415_p via the conductor 424 and the conductor 205.

[0315] 44B shows that in the memory device layer 415_p-1, the conductor 424 is connected to the conductor 242 of the memory device layer 415_p-1 and the conductor 205 of the memory device layer 415_p. Here, the conductor 424 is also connected to the conductor 205 of the memory device layer 415_p-1 on the outside of the B2 side of the conductor 242, the oxide 243, the oxide 230b, and the oxide 230a.

[0316] In Fig. 44C, it can be seen that the conductor 424 is formed along the side surfaces on the B2 side of the conductor 242, the oxide 243, the oxide 230b, and the oxide 230a, and is electrically connected to the conductor 205 through the openings formed in the insulators 280, the insulators 273, the insulators 272, the insulators 224, and the insulators 222. Here, the manner in which the conductor 424 is provided along the side surfaces on the B2 side of the conductor 242, the oxide 243, the oxide 230b, and the oxide 230a is shown by dotted lines in Fig. 44B. In addition, an insulator 241 may be formed between the conductor 424 and the side surfaces on the B2 side of the conductor 242, the oxide 243, the oxide 230b, the oxide 230a, the insulators 224, and the insulators 222.

[0317] By providing the conductor 424 in an area that does not overlap with the conductor 242, etc., the memory device 420 can be electrically connected to the memory device 420 provided in a different memory device layer 415. The memory device 420 can also be electrically connected to the transistor 200T provided in the transistor layer 413.

[0318] In addition, when the conductor 424 is used as a bit line, the distance between the bit lines of the memory devices 420 adjacent in the B1-B2 direction can be increased by providing the conductor 424 in an area that does not overlap with the conductor 242, etc. As shown in FIG. 44, the distance between the conductors 424 on the conductor 242 is d1, but the distance between the conductors 424 located below the oxide 230a, i.e., in the insulator 224 and in the opening formed in the insulator 222, is d2, and d2 is greater than d1. By making some of the distance d2, the parasitic capacitance of the conductor 424 can be reduced compared to when the distance between the conductors 424 adjacent in the B1-B2 direction is d1. Reducing the parasitic capacitance of the conductor 424 is preferable because it can reduce the capacitance required for the capacitance 292.

[0319] In the memory device 420, a conductor 424 is provided to function as a common bit line for two memory cells. The cell size of each memory cell can be reduced by appropriately adjusting the dielectric constant of the dielectric material used for the capacitance and the parasitic capacitance between the bit lines. Here, an estimate of the cell size, bit density, and bit cost of a memory cell when the channel length is set to 30 nm (also called a 30 nm node) will be described. Note that in FIGS. 45A to 45D described below, the conductor 205 is omitted from the illustration in order to facilitate understanding of the figures. When the conductor 205 is provided, the conductor 205 has a region overlapping with the conductor 260 and the conductor 424.

[0320] 45A shows an example in which hafnium oxide having a thickness of 10 nm and silicon oxide having a thickness of 1 nm are laminated thereon as a dielectric of the capacitance, slits are provided between the conductor 242, the oxide 243, the oxide 230a, and the oxide 230b of each memory cell of the memory device 420, and the conductor 424 functioning as a bit line is provided so as to overlap the conductor 242 and the slit. The memory cell 432 obtained in this way is called cell A.

[0321] The cell size in cell A is 45.25F 2 It is.

[0322] 45B shows an example in which a first zirconium oxide is laminated on top of an aluminum oxide as a capacitor dielectric, a slit is provided between the conductor 242, the oxide 243, the oxide 230a, and the oxide 230b of each memory cell of the memory device 420, and a conductor 424 functioning as a bit line is provided so as to overlap the conductor 242 and the slit. The memory cell 433 obtained in this way is called cell B.

[0323] Cell B has a higher dielectric constant than cell A, so the area of ​​the capacitance can be reduced. Therefore, the cell size of cell B can be reduced compared to cell A. The cell size of cell B is 25.53F. 2 It is.

[0324] Cell A and cell B correspond to memory cells included in memory device 420, memory device 420A, or memory device 420B shown in FIGS. 39, 41A to 41C, and 42.

[0325] 45C shows an example in which a first zirconium oxide is laminated on top of aluminum oxide as a capacitor dielectric, the conductor 242, oxide 243, oxide 230a, and oxide 230b of the memory device 420 are shared by each memory cell, and a conductor 424 functioning as a bit line is provided so as to overlap a part of the conductor 242 and an outer part of the conductor 242. The memory cell 434 obtained in this manner is called cell C.

[0326] The spacing of the conductors 424 in cell C is wider below the oxide 230a than above the conductor 242. This allows the parasitic capacitance of the conductors 424 to be reduced, and the area of ​​the capacitance to be reduced. In addition, no slits are provided in the conductors 242, the oxide 243, the oxide 230a, and the oxide 230b. As a result, the cell size of cell C can be reduced compared to cells A and B. The cell size of cell C is 17.20F 2 It is.

[0327] 45D shows an example in which the conductor 205 and the insulator 216 are not provided in the cell C. Such a memory cell 435 is referred to as a cell D.

[0328] By not providing the conductor 205 and the insulator 216 in the cell D, the memory device 420 can be made thinner. Therefore, the memory device layer 415 having the memory device 420 can be made thinner, and the height of the memory unit 470 in which a plurality of memory device layers 415 are stacked can be reduced. When the conductor 424 and the conductor 205 are regarded as bit lines, the bit lines can be shortened in the memory unit 470. Since the bit lines can be shortened, the parasitic load of the bit lines is reduced, the parasitic capacitance of the conductor 424 can be further reduced, and the area of ​​the capacitance can be reduced. In addition, slits are not provided in the conductor 242, the oxide 243, the oxide 230a, and the oxide 230b. As a result, the cell size of the cell D can be reduced compared to the cells A, B, and C. The cell size of the cell D is 15.12F 2 It is.

[0329] Cells C and D correspond to memory cells included in memory device 420 shown in Figures 44A to 44C.

[0330] Here, for cells A to D and cell E obtained by multi-value encoding of cell D, the bit density and bit cost C b We also compared the estimates with the bit density and bit cost of currently available DRAMs.

[0331] The bit cost C in the semiconductor device according to one embodiment of the present invention b was estimated using Equation 1.

[0332]

number

[0333] where n is the number of stacked memory device layers, P c is the number of times of patterning of the element layer 411 as a common part, P s is the number of patternings per layer of the memory device layer 415 and the transistor layer 413, D dis the bit density of the DRAM, D 3d is the bit density of one layer of the memory device layer 415, P d indicates the number of patterning times for the DRAM. d Including the increase due to scaling.

[0334] Table 1 shows the expected bit density of commercially available DRAMs and the estimated bit density of the semiconductor device of one embodiment of the present invention. Note that the commercially available DRAMs have two process nodes, 18 nm and 1X nm. The process node of the semiconductor device of one embodiment of the present invention was set to 30 nm, and the estimation was performed with the number of stacked memory device layers in Cells A to E set to 5, 10, and 20.

[0335] [Table 1]

[0336] Table 2 shows the results of estimating the relative bit cost of the semiconductor device of one embodiment of the present invention based on the bit cost of a commercially available DRAM. Note that a DRAM with a process node of 1X nm was used for the comparison of bit costs. The process node of the semiconductor device of one embodiment of the present invention was set to 30 nm, and the number of stacked memory device layers in Cells A to D was set to 5, 10, and 20.

[0337] [Table 2]

[0338] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes.

[0339] (Embodiment 3) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) which can be used for the OS transistor described in the above embodiment will be described.

[0340] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0341] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 46A. Fig. 46A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0342] As shown in FIG. 46A, oxide semiconductors are broadly classified into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and poly crystal). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystal" includes single crystal and poly crystal.

[0343] The structure in the bold frame shown in Fig. 46A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" and "Crystal".

[0344] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. FIG. 46B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline". The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 46B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in FIG. 46B is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 46B is 500 nm.

[0345] As shown in Figure 46B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 46B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0346] The crystal structure of the film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 46C. FIG. 46C is a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 46C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0347] As shown in FIG. 46C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0348] <<Structure of oxide semiconductor>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 46A. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0349] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0350] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0351] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0352] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0353] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0354] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0355] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a pentagonal or heptagonal lattice arrangement. In addition, no clear grain boundary can be confirmed in the CAAC-OS even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction and the bond distance between atoms changes due to the substitution of metal atoms.

[0356] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0357] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0358] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0359] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0360] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0361] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0362] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0363] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0364] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0365] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0366] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0367] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0368] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0369] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0370] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0371] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than or equal to 1×10 15 cm -3 Less than 1×10, more preferably 13 cm -3 Less than or equal to 1×10 11 cm -3 Less than 1×10, more preferably 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0372] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0373] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0374] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0375] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0376] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as 2×10 18 atoms / cm 3 Less than or equal to 2×10 17atoms / cm 3 The following applies.

[0377] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of an alkali metal or an alkaline earth metal in an oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0378] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 To the following:

[0379] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0380] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0381] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0382] (Embodiment 4) In this embodiment, a control logic circuit 61, a row driving circuit 62, a column driving circuit 63 and an output circuit 64 provided on a silicon substrate 50 in the semiconductor device 10 described in the first embodiment will be described.

[0383] 47 is a block diagram showing a configuration example of a semiconductor device functioning as a memory device. The semiconductor device 10E has a peripheral circuit 80 and a memory cell array 70. The peripheral circuit 80 has a control logic circuit 61, a row driving circuit 62, a column driving circuit 63, and an output circuit 64.

[0384] The memory cell array 70 has a plurality of memory cells 42. The row driving circuit 62 has a row decoder 71 and a word line driver circuit 72. The column driving circuit 63 has a column decoder 81, a precharge circuit 82, an amplifier circuit 83, and a write circuit 84. The precharge circuit 82 has a function of precharging the global bit line GBL or the local bit line LBL. The amplifier circuit 83 has a function of amplifying a data signal read from the global bit line GBL or the local bit line LBL. The amplified data signal is outputted to the outside of the semiconductor device 10E via the output circuit 64 as a digital data signal RDATA.

[0385] A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 80, and a high power supply voltage (VIL) for the memory cell array 70 are supplied to the semiconductor device 10E from the outside as power supply voltages.

[0386] Further, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input from the outside to the semiconductor device 10E. The address signal ADDR is input to a row decoder 71 and a column decoder 81, and the WDATA is input to a write circuit 84.

[0387] The control logic circuit 61 processes external input signals (CE, WE, RE) to generate control signals for the row decoder 71 and column decoder 81. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 61 are not limited to these, and other control signals may be input as necessary. For example, a control signal for determining a defective bit may be input, and a data signal read from an address of a specific memory cell may be identified as a defective bit.

[0388] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as necessary.

[0389] Generally, various storage devices (memories) are used in semiconductor devices such as computers depending on the application. Figure 48 shows various storage devices by hierarchy. The higher the storage device, the faster the access speed is required, while the lower the storage device, the larger the storage capacity and the higher the recording density are required. Figure 48 shows, from the top layer, memories embedded as registers in arithmetic processing devices such as CPUs, SRAMs (Static Random Access Memory), DRAMs (Dynamic Random Access Memory), and 3D NAND memories.

[0390] The memory embedded as a register in a processor such as a CPU is used for temporary storage of calculation results, and is accessed frequently by the processor. Therefore, a faster operating speed is required rather than a larger memory capacity. The register also has the function of storing setting information for the processor.

[0391] SRAM is used, for example, in caches. A cache has the function of storing a copy of some of the information stored in the main memory. By storing a copy of frequently used data in the cache, the speed of accessing the data can be increased.

[0392] DRAM is used, for example, as a main memory. The main memory has a function of storing programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 It is.

[0393] 3D NAND memory is used, for example, in storage. Storage has the function of holding data that needs to be stored for a long time and various programs used in processing units. Therefore, storage requires a larger memory capacity and a higher recording density than the operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm 2 It is.

[0394] A semiconductor device functioning as a memory device according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. The semiconductor device according to one embodiment of the present invention can be suitably used as a semiconductor device located in a boundary region 901 including both a layer in which a cache is located and a layer in which a main memory is located. The semiconductor device according to one embodiment of the present invention can be suitably used as a semiconductor device located in a boundary region 902 including both a layer in which a main memory is located and a layer in which a storage is located.

[0395] (Embodiment 5) This embodiment mode will show an example of an electronic component or electronic device in which the semiconductor device or the like described in the above embodiment mode is incorporated.

[0396] <Electronic components> First, an example of an electronic component incorporating the semiconductor device 10 etc. will be described with reference to FIGS. 49A and 49B.

[0397] FIG. 49A shows a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in FIG. 49A has a semiconductor device 10 in which an element layer 20 is laminated on a silicon substrate 50 in a mold 711. FIG. 49A does not show a part of the inside of the electronic component 700 in order to show the inside of the electronic component 700. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 10 by wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0398] 49B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 10 provided on interposer 731.

[0399] The electronic component 730 shows an example in which the semiconductor device 10 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0400] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 732. A silicon interposer, a resin interposer, or the like can be used for the interposer 731.

[0401] The interposer 731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate." In addition, a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode. In addition, in a silicon interposer, a TSV (Through Silicon Via) may be used as the through electrode.

[0402] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult to form with a resin interposer.

[0403] In HBM, many wirings need to be connected to realize a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts HBM.

[0404] In addition, in SiPs and MCMs that use silicon interposers, reliability is less likely to decrease due to differences in the expansion coefficient between the integrated circuit and the interposer. In addition, because the surface of the silicon interposer is highly flat, connection defects are less likely to occur between the integrated circuit mounted on the silicon interposer and the silicon interposer. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged side by side on the interposer.

[0405] A heat sink (heat dissipation plate) may be provided so as to overlap the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 10 and the height of the semiconductor device 735.

[0406] In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided on the bottom of the package substrate 732. Fig. 49B shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. The electrodes 733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.

[0407] The electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as Staggered Pin Grid Array (SPGA), Land Grid Array (LGA), Quad Flat Package (QFP), Quad Flat J-leaded package (QFJ), and Quad Flat Non-leaded package (QFN).

[0408] <Electronic equipment> Next, an example of an electronic device equipped with the above electronic components will be described with reference to FIG.

[0409] The robot 7100 includes an illuminance sensor, a microphone, a camera, a speaker, a display, various sensors (infrared sensor, ultrasonic sensor, acceleration sensor, piezoelectric sensor, light sensor, gyro sensor, etc.), and a moving mechanism. The electronic component 730 includes a processor and the like, and has a function of controlling these peripheral devices. For example, the electronic component 700 has a function of storing data acquired by the sensors.

[0410] The microphone has a function of detecting acoustic signals such as the user's voice and environmental sounds. The speaker has a function of emitting audio signals such as voice and warning sounds. The robot 7100 can analyze the audio signal input via the microphone and emit a necessary audio signal from the speaker. The robot 7100 can communicate with the user using the microphone and the speaker.

[0411] The camera has a function of capturing an image of the surroundings of the robot 7100. The robot 7100 also has a function of moving using a moving mechanism. The robot 7100 can capture an image of the surroundings using the camera and detect the presence or absence of an obstacle when moving by analyzing the image.

[0412] The flying object 7120 has a propeller, a camera, a battery, etc., and has a function of flying autonomously. The electronic components 730 have a function of controlling these peripheral devices.

[0413] For example, image data captured by a camera is stored in the electronic component 700. The electronic component 730 can analyze the image data and detect the presence or absence of obstacles when moving. In addition, the electronic component 730 can estimate the remaining battery charge from changes in the battery's charge capacity.

[0414] The cleaning robot 7140 has a display arranged on the top surface, multiple cameras arranged on the sides, a brush, operation buttons, various sensors, etc. Although not shown, the cleaning robot 7140 is equipped with tires, a suction port, etc. The cleaning robot 7140 can move by itself, detect dirt, and suck up the dirt from the suction port arranged on the bottom surface.

[0415] For example, the electronic component 730 can analyze images captured by the camera and determine the presence or absence of obstacles such as walls, furniture, steps, etc. Furthermore, if the electronic component 730 detects an object that may become entangled in the brush, such as a wire, through image analysis, it can stop the rotation of the brush.

[0416] The automobile 7160 has an engine, tires, brakes, a steering device, a camera, etc. For example, the electronic component 730 performs control to optimize the running state of the automobile 7160 based on data such as navigation information, speed, engine state, gear selection state, and frequency of brake use. For example, image data captured by a camera is stored in the electronic component 700.

[0417] The electronic component 700 and / or the electronic component 730 can be incorporated into a TV device 7200 (television receiver), a smartphone 7210, a PC (personal computer) 7220, 7230, a game console 7240, a game console 7260, etc.

[0418] For example, the electronic component 730 built into the TV device 7200 can function as an image engine. For example, the electronic component 730 performs image processing such as noise removal and resolution up-conversion.

[0419] The smartphone 7210 is an example of a portable information terminal. The smartphone 7210 includes a microphone, a camera, a speaker, various sensors, and a display unit. These peripheral devices are controlled by the electronic component 730.

[0420] PC7220 and PC7230 are examples of a notebook PC and a stationary PC, respectively. A keyboard 7232 and a monitor device 7233 can be connected to PC7230 wirelessly or via a wire. Game machine 7240 is an example of a portable game machine. Game machine 7260 is an example of a stationary game machine. A controller 7262 is connected to game machine 7260 wirelessly or via a wire. Electronic component 700 and / or electronic component 730 can also be incorporated into controller 7262.

[0421] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0422] (Additional Notes Regarding the Description of the Present Specification, etc.) The above embodiment and each configuration in the embodiment will be described below with additional notes.

[0423] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments or examples to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0424] In addition, the content (or a part of the content) described in one embodiment can be applied to, combined with, or replaced by another content (or a part of the content) described in that embodiment, and / or the content (or a part of the content) described in one or more other embodiments.

[0425] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0426] In addition, a figure (or a part of it) described in one embodiment can be combined with another part of that figure, with another figure (or a part of it) described in that embodiment, and / or with a figure (or a part of it) described in one or more other embodiments to form even more figures.

[0427] In addition, in the present specification and the like, in the block diagrams, the components are classified by function and shown as mutually independent blocks. However, in actual circuits and the like, it is difficult to separate the components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and may be rephrased appropriately according to the situation.

[0428] In addition, in the drawings, the size, layer thickness, or region are shown at an arbitrary size for convenience of explanation. Therefore, they are not necessarily limited to the scale. Note that the drawings are shown diagrammatically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0429] In addition, the positional relationship of components shown in the drawings is relative. Therefore, when describing components with reference to the drawings, terms such as "above" and "below" that indicate the positional relationship may be used for convenience. The positional relationship of components is not limited to the contents described in this specification, and can be rephrased appropriately depending on the situation.

[0430] In this specification and the like, when describing the connection relationship of a transistor, the term "one of the source or drain" (or first electrode or first terminal) is used, and the other of the source and drain is used as the "other of the source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. The source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, etc. depending on the situation.

[0431] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally.

[0432] In addition, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage is a potential difference from a reference potential, and if the reference potential is a ground voltage (earth voltage), for example, voltage can be interchanged with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may be changed depending on the reference potential.

[0433] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0434] In this specification, A and B are connected means that A and B are electrically connected. Here, A and B are electrically connected means a connection in which an electrical signal between A and B can be transmitted when an object (an element such as a switch, a transistor element, or a diode, or a circuit including the element and wiring) exists between A and B. Note that when A and B are electrically connected, this includes a case in which A and B are directly connected. Here, A and B are directly connected means a connection in which an electrical signal between A and B can be transmitted through wiring (or electrodes) between A and B without passing through the object. In other words, a direct connection means a connection that can be regarded as the same circuit diagram when expressed as an equivalent circuit.

[0435] In this specification, a switch refers to a device that has a function of controlling whether a current flows or not by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0436] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between the source and drain in a region where a channel is formed.

[0437] In this specification, the channel width refers to, for example, the length of the region where a semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap, or the length of the portion where a source and a drain face each other in a region in which a channel is formed.

[0438] In this specification and the like, the terms "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". [Explanation of symbols]

[0439] BL2: wiring, EN1: signal, RE1: signal, RE2: signal, SL2: wiring, T11: time, T12: time, T13: time, T14: time, T15: time, T16: time, T17: time, T18: time, T19: time, T20: time, 10: semiconductor device, 10A: semiconductor device, 10B: semiconductor device, 10C: semiconductor device, 10E: semiconductor device, 20: element layer, 20_M: element layer, 20_1: element layer, 30: transistor layer, 31: transistor, 32: transistor, 33: transistor, 34: transistor, 35: control circuit, 35_pre: control circuit , 35B: control circuit, 35C: control circuit, 36: control circuit, 36_pre: control circuit, 37: transistor, 40: transistor layer, 40_k: transistor layer, 40_1: transistor layer, 41_k: transistor layer, 41_1: transistor layer, 41_2: transistor layer, 42: memory cell, 43: transistor, 44: capacitor, 49: transistor layer, 49_k: transistor layer, 49_1: transistor layer, 50: silicon substrate, 51: control circuit, 51A: control circuit, 52: switch circuit, 52_1: transistor, 52_2: transistor , 53: Precharge circuit, 53_1: Transistor, 53_3: Transistor, 54: Precharge circuit, 54_1: Transistor, 54_3: Transistor, 55: Sense amplifier, 55_1: Transistor, 55_2: Transistor, 55_3: Transistor, 55_4: Transistor, 57_1: Transistor, 57_2: Transistor, 58_1: Transistor, 58_2: Transistor, 59: Potential setting circuit, 61: Control logic circuit, 62: Row drive circuit, 63: Column drive circuit, 64: Output circuit, 70: Memory cell array, 71: Row deco , 72: word line driver circuit, 80: peripheral circuit, 81: column decoder, 82: precharge circuit, 83: amplifier circuit, 84: write circuit, 90: transistor layer, 91: memory cell, 92: transistor, 93: transistor, 94: capacitor, 100: memory device, 200: transistor, 200M: transistor, 200T: transistor, 205: conductor, 205a: conductor, 205b: conductor, 211: insulator, 212: insulator, 214: insulator, 216: insulator, 222: insulator, 224: insulator, 230: oxide, 230a: oxide,230b: oxide, 230c: oxide, 240: conductor, 240a: conductor, 240b: conductor, 241: insulator, 241a: insulator, 241b: insulator, 242: conductor, 242a: conductor, 242b: conductor, 243: oxide, 243a: oxide, 243b: oxide, 246: conductor, 246a: conductor, 246b: conductor, 250: insulator, 260: conductor, 260a: conductor, 260b: conductor, 272: insulator, 273: insulator, 274: insulator, 275: insulator, 276: conductor, 277: insulator, 278: conductor, 279: insulator, 280 : insulator, 282: insulator, 283: insulator, 284: insulator, 287: insulator, 290: conductor, 292: capacitance, 292A: capacitance, 292B: capacitance, 294: conductor, 295: insulator, 296: insulator, 297: conductor, 298: insulator, 299: conductor, 300: transistor, 311: semiconductor substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 411: element layer, 413: transistor layer, 413_m: transistor layer, 413_1: transistor layer, 415: memory device layer, 415 _n: memory device layer, 415_p: memory device layer, 415_p-1: memory device layer, 415_1: memory device layer, 415_3: memory device layer, 415_4: memory device layer, 420: memory device, 420A: memory device, 420B: memory device, 422: region, 424: conductor, 426: conductor, 428: conductor, 430: conductor, 432: memory cell, 433: memory cell, 434: memory cell, 435: memory cell, 470: memory unit, 470_m: memory unit, 470_1: memory unit, 700 : Electronic component, 702: Printed circuit board, 704: Mounting board, 711: Mold, 712: Land, 713: Electrode pad, 714: Wire, 730: Electronic component, 731: Interposer, 732: Package board, 733: Electrode, 735: Semiconductor device, 820: Peripheral circuit, 901: Boundary area, 902: Boundary area, 7100: Robot, 7120: Aircraft, 7140: Cleaning robot, 7160: Automobile, 7200: TV device, 7210: Smartphone, 7220: PC, 7230: PC, 7232: Keyboard, 7233: Monitor device, 7240: Game machine,7260: Game console, 7262: Controller,

Claims

[Claim 1] a first control circuit having a sense amplifier circuit; a second control circuit having an area disposed over the first control circuit; a memory circuit having an area disposed on the second control circuit; a global bit line and an inverted global bit line having a function of transmitting a first signal between the first control circuit and the second control circuit; a local bit line having a function of transmitting a second signal between the second control circuit and the memory circuit; having the first control circuit includes a first transistor having a channel in a silicon substrate; the second control circuit includes second to sixth transistors each having a metal oxide in a channel; the memory circuit includes a seventh transistor having a metal oxide in a channel; a gate of the second transistor electrically connected to the local bit line; the third transistor has a function of controlling a conduction state between a gate of the second transistor and one of a source and a drain of the second transistor; the fourth transistor has a function of controlling electrical continuity between the other of the source and the drain of the second transistor and a wiring; the fifth transistor has a function of controlling a conductive state between one of a source or a drain of the second transistor and the global bit line; a precharge voltage is applied to one of the source and drain of the sixth transistor; the other of the source and the drain of the sixth transistor is electrically connected to the local bit line; during a first period in which data is read from the memory circuit to the first control circuit, the second control circuit controls whether or not to charge the global bit line and the inverted global bit line from which electric charges have been discharged, in accordance with the data read from the memory circuit; Semiconductor device.

Images